From newsfish@newsfish Tue Dec 29 16:42:52 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Convert ADC output format to DAC input Date: Wed, 17 Apr 2013 13:13:36 -0400 Organization: A noiseless patient Spider Lines: 138 Message-ID: References: <8a08004e-14e8-4734-97e9-15d6f3a101ed@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Apr 2013 17:11:46 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="9fce6e44d3643a774a64f1ed77ec3a22"; logging-data="19210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19HCuWIRCzfQy3vovQFLULd" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <8a08004e-14e8-4734-97e9-15d6f3a101ed@googlegroups.com> Cancel-Lock: sha1:f2MqCKPCpPEYAvhgRhryiNVWi9I= Xref: mx05.eternal-september.org comp.lang.vhdl:6480 On 4/16/2013 6:36 PM, snake368@gmail.com wrote: > I want to do the following operation using VHDL. The INPUT and OUTPUT are 14-bit signals and I have to divide INPUT by a constant, in this case 132, which is in decimal form. > Here's my code: > > > PROCESS (clk) > VARIABLE d, q: INTEGER; > BEGIN > IF (clk'EVENT AND clk = '1') THEN > CASE state IS > WHEN min_132000 => > d := CONV_INTEGER (a); > q := 0; > IF (d>= 132000) THEN > d := d - 132000; > q := q + 1000; > END IF; > IF (d>= 13200) THEN > state<= min_13200; > ELSIF (d>= 1320) THEN > state<= min_1320; > ELSIF (d>= 132) THEN > state<= min_132; > ELSE > state<= to_dac; > END IF; > WHEN min_13200 => > IF (d>= 13200) THEN > d := d - 13200; > q := q + 100; > END IF; > IF (d< 13200) THEN > IF (d>= 1320) THEN > state<= min_1320; > ELSIF (d>= 132) THEN > state<= min_132; > ELSE > state<= to_dac; > END IF; > END IF; > WHEN min_1320 => > IF (d>= 1320) THEN > d := d - 1320; > q := q + 10; > END IF; > IF (d< 1320) THEN > IF (d>= 132) THEN > state<= min_132; > ELSE > state<= to_dac; > END IF; > END IF; > WHEN min_132 => > IF (d>= 132) THEN > d := d - 132; > q := q + 1; > END IF; > IF (d< 132) THEN > state<= end; > b<= CONV_STD_LOGIC_VECTOR ((q), 14); > END IF; > WHEN end => > state<= end; > END CASE; > > As you see it's a FSM and takes several rising edges to complete. Is there anyway to do it easier? Or maybe in a single rising edge? You have the right idea, sort of. I see two problems. One is that you are thinking in decimal while your data is really binary. The other is that you don't fully understand how VHDL works in processes. Let's deal with the second problem first. Looking at the case for WHEN min_132000 => you will see that every time you enter this section the variables d and q are initialized and yet you only subtract 132000 once before leaving. So nothing outside of the process is changed and it will repeat these same operations on every clock edge without updating either a or b. Rather than coding this using decimal notation why not think in terms of binary? Remember your long division? Try doing that on paper using binary numbers. Say a = 133,000. Then the long division will be... 1000000011... ________________________|||||||||| 0010 0000 0011 1010 0000)0010 0000 0111 1000 1000||||||||| - 0010 0000 0011 1010 0000||||||||| ------------------------||||||||| 0000 0000 0111 1101 0000|||||||| 0000 0000 0000 0000 0000|||||||| ------------------------|||||||| 0000 0000 1111 1010 0000||||||| 0000 0000 0000 0000 0000||||||| ------------------------||||||| 0000 0001 1111 0100 0000|||||| 0000 0000 0000 0000 0000|||||| ------------------------|||||| 0000 0011 1110 1000 0000||||| 0000 0000 0000 0000 0000||||| ------------------------||||| 0000 0111 1101 0000 0000|||| 0000 0000 0000 0000 0000|||| ------------------------|||| 0000 1111 1010 0000 0000||| 0000 0000 0000 0000 0000||| ------------------------||| 0001 1111 0100 0000 0000|| 0000 0000 0000 0000 0000|| ------------------------|| 0011 1110 1000 0000 0000| 0010 0000 0011 1010 0000| ------------------------| 0011 1100 1000 1100 0000 0010 0000 0011 1010 0000 ------------------------ This is not hard to code in a loop, but it will be one clock cycle per bit of precision in the result if you use a clocked process. I don't think there is an easy way to do division in one step. You can implement long division in successive conditional subtractions without breaking it up into clock cycles, but it will still be slow. How fast is your clock? A subtraction of say, 24 bits will take around 8 ns in many FPGAs, give or take a couple of ns. If you want a 20 bit accurate result it would require perhaps 160 ns to run through that many subtractions. This may be a bit more in order to include the delay for the comparison that has to be done. So a division might be done in one 5 MHz clock if that helps... There are faster methods that start with an approximate result and use iteration to get closer to a result that is "good enough". Look up Newton-Raphson iteration. If you are dividing by a constant, it can be easier to multiply by the reciprocal of that constant. Then you can use multiplier hardware that many FPGAs have. -- Rick From newsfish@newsfish Tue Dec 29 16:42:52 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Convert ADC output format to DAC input Date: Wed, 17 Apr 2013 10:42:11 -0700 Organization: Highland Technology, Inc. Lines: 42 Message-ID: <20130417104211.2d8d54ba@rg.highlandtechnology.com> References: <8a08004e-14e8-4734-97e9-15d6f3a101ed@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="50e98e5aeb95dd52ea314f22976498bc"; logging-data="20529"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/OCvoIFGggZGglq3aaTrZi" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:NiwoR0QekL0iko2S347c0zdjvhE= Xref: mx05.eternal-september.org comp.lang.vhdl:6481 On Wed, 17 Apr 2013 00:01:03 -0700 (PDT) goouse99@gmail.com wrote: > Am Mittwoch, 17. April 2013 00:36:48 UTC+2 schrieb snak...@gmail.com: > > I want to do the following operation using VHDL. The INPUT and OUTPUT are 14-bit signals and I have to divide INPUT by a constant, in this case 132, which is in decimal form. > > > > [snip] > > Also you might think about using some dedicated multiplier (e.g. DSP48 Macro in Xilinx devices). You can either use some IP-Generator or use a multiplier with the inverse divisor. > So instead of A/B you calculate A*(B^-1). > > Have a nice synthesis > Eilert Let me clarify that a bit, since the OP seems pretty new at this. You can't actually multiply by 1/132 since you don't have any way of representing fractional numbers. What you can do is multiply by (2^N / 132 / 2^(N)). Let's assume you're doing this on the 18 bit * 18 bit = 36 bit multipliers that are fairly common on FPGA architectures. What you'd want to do is multiply your number by (2^24 / 132) ~= 127,000. This product is nearly what you want, except you're high by a factor of 2^24. Fortunately, this is easily fixed in hardware; you simply discard the 24 least significant bits, leaving you the 12 uppermost, and move on. This entire operation can in fact be performed in one clock cycle on a dedicated multiplier, which the tools are smart enough to infer, and in fact if you convert your signals to integers you can even write it all on one line. variable my_input, my_output : integer range 0 to 2**14-1; ... -- Divide by 132. my_output := my_input * 127_000 / (2**24); Do be sure to leave that comment in, otherwise you'll never understand what that line is meant to accomplish 3 months from now. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.180.24.132 with SMTP id u4mr6245264wif.6.1366220715979; Wed, 17 Apr 2013 10:45:15 -0700 (PDT) X-Received: by 10.49.132.196 with SMTP id ow4mr800446qeb.28.1366220707621; Wed, 17 Apr 2013 10:45:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!nntp.giganews.com!19no96249370wie.1!news-out.google.com!hg5ni4684wib.1!nntp.google.com!19no96249363wie.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Apr 2013 10:45:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <177cd3bd-aeed-4a08-994d-80eb94988a92@googlegroups.com> <64611fed-23e9-4909-8f44-ab3e44534645@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Dual Edged Counter From: Cory Shol Cc: gabor@alacron.com Injection-Date: Wed, 17 Apr 2013 17:45:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 228 Xref: mx05.eternal-september.org comp.lang.vhdl:6482 On Wednesday, April 17, 2013 10:54:46 AM UTC-5, Gabor Sz wrote: > Cory Shol wrote: > > > On Wednesday, April 17, 2013 10:21:19 AM UTC-5, Gabor Sz wrote: > > >> Cory Shol wrote: > > >> > > >>> Hi All, > > >>> I am researching ways onto create a dual edged Counter. > > >>> Problem details: > > >>> Original Clock = 25 MHz Put the Original clock through a PLL and multiply it by 5 making a new: Clk_125MHz = 125 MHz clock. > > >>> Using the 125 MHz clock, I want to use a 9 bit register [Called Duty_cycle] to state the Duty cycle of a PWM. > > >>> For example if the Duty_cycle = "011111111" it will have a 50% duty cycle. Duty_cycle = "1111111110" it will have a ~0.2% duty cycle etc... > > >>> The period of the PWM is 4096 ns (125 Mhz/ 2^9) = 125000000/512 = 244KHz =1/244KHz= 4096 ns. > > >>> Code looks something like: > > >>> process(clk_125Mhz, reset) > > >>> > > >>> begin > > >>> if (reset = '1') then > > >>> dc_count_i <= X"00" &'0'; -- you can use others statement as well. > > >>> elsif(rising_edge(clk_125Mhz)) then > > >>> if(dc_count_i < duty_cycle) then > > >>> duty_out <='0'; > > >>> else > > >>> duty_out <= '1'; > > >>> end if; > > >>> dc_count_i <= dc_count_i + 1; > > >>> end if; > > >>> end process; > > >>> Alright this is all fine and works decent. > > >>> Now the extension I want to make my PWM have a period of 2048 ns. There are three ways I can think of to do this: > > >>> 1) PLL the clock to 250 MHz ( Do not want to run at Max frequency in the device) > > >>> 2) Change the 9 bit Duty Cycle register to 8 bits (Lower the resolution) > > >>> 3) Every time there is a rising or falling edge count up the counter > > >>> This is coming back to topic title: to create a dual Edged Counter that can generate a duty cycle of a PWM. > > >>> I tried something like: > > >>> ------------------------------------------------------ > > >>> process(clk_125Mhz, reset) > > >>> > > >>> begin > > >>> if (reset = '1') then > > >>> rise_counter <= X"00" &'0'; > > >>> elsif(rising_edge(clk_125Mhz)) then > > >>> rise_counter <= rise_counter + 2; > > >>> end if; > > >>> end process; > > >>> process(clk_125Mhz, reset) > > >>> > > >>> begin > > >>> if (reset = '1') then > > >>> fall_counter <= X"00" &'1'; > > >>> elsif(falling_edge(clk_125Mhz)) then > > >>> fall_counter <= fall_counter + 2; > > >>> end if; > > >>> end process; > > >>> process(xor_counter, final_counter) > > >>> begin > > >>> final_counter <= final_counter + 1; > > >>> end process; > > >>> xor_counter <= rise_counter XOR fall_counter; > > >>> dc_count <= final_counter; > > >>> > > >>> duty_out <= '0' when (final_counter < duty_cycle) else '1'; > > >>> But this creates a Combinatorial loop. > > >>> I tried: > > >>> --------------------------------------------------- > > >>> process(clk_125Mhz, reset) > > >>> > > >>> begin > > >>> if (reset = '1') then > > >>> rise_counter <= X"00" &'0'; > > >>> elsif(rising_edge(clk_125Mhz)) then > > >>> rise_counter <= rise_counter + 2; > > >>> end if; > > >>> end process; > > >>> final_counter <= rise_counter when clk_125Mhz ='1' else (rise_counter or "000000001"); > > >>> duty_out <= '0' when (final_counter < duty_cycle) else '1'; > > >>> But this produced a glitch in simulation. > > >>> Does anyone else have any other ideas, on how to implement a dual edged counter? I feel like this should be an easy solution, I just keep thinking too complex. > > >> > > >> > > >> Is the output of the PWM going to a pin that is supported by a DDR > > >> > > >> output flop? If so, then you could simply reduce the counter > > >> > > >> by one bit, but compare it with the upper bits of the duty cycle > > >> > > >> input. If the LSB of the duty cycle is zero, then the output DDR > > >> > > >> flop D inputs go from 11 to 00, but the it is 1, then the D inputs > > >> > > >> go from 11 to 10 to 00 as you pass the duty cycle threshold. > > >> > > >> No internal dual edges, no glitches. > > >> > > >> > > >> > > >> -- > > >> > > >> Gabor > > > > > > The research is for an Microsemi Actel Igloo AGL1000. I don't think it has a DDR output flop. > > > > Realize that without an output DDR flop, there will be some influence > > of routing delays between even and odd values of duty cycle, but the > > same approach of using a shorter counter to make the PWM with half the > > resolution could work. Follow that with a single flop on the falling > > clock edge. Then you have two PWM signals offset by half a clock cycle. > > At the output, you would either select the first, or the OR of the two > > signals based on the LSB of duty cycle. Again no glitches, but the > > monotonicity could suffer slightly. > > > > -- > > Gabor THE DDR flip flop got me thinking. So I went back and looked at Spartan 3A user guide to see the DDR flip flop. I then looked for a similar flip flop in the Actel AGL1000 and it indeed does have a DDR register input or output type. Even after working 2 years in Logic design I still feel like I know nothing. From newsfish@newsfish Tue Dec 29 16:42:52 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Dual Edged Counter Date: Wed, 17 Apr 2013 15:18:39 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <177cd3bd-aeed-4a08-994d-80eb94988a92@googlegroups.com> <64611fed-23e9-4909-8f44-ab3e44534645@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Apr 2013 19:16:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="9fce6e44d3643a774a64f1ed77ec3a22"; logging-data="13353"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QagDDoVkOvQ5/GDhdD3Us" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:Pi3TsqD2noJLicbCEbhDgrn0KOY= Xref: mx05.eternal-september.org comp.lang.vhdl:6483 On 4/17/2013 1:45 PM, Cory Shol wrote: > > Even after working 2 years in Logic design I still feel like I know nothing. I know the feeling. There is just so much to learn. Are you looking for an *average* PWM on the pin or does it need to be exact on every cycle? If the average value is what is important you can use a fractional divider which should be easier and can get you even more precision. A fractional divider just counts the number of PWM cycles and periodically adds or subtracts one from the duty_cycle value. This can be done in a manner that is not actually periodic so that the side tones it introduces are spread out and at a low level if that is important. You might also consider using a DCO. I tried to do that for a few minutes and couldn't think of how that would work. But I'm pretty sure there is a way. I'm just drawing a blank at the moment. A DCO will give you a much more precise average value with one clock cycle of jitter on the edge, similar to the fractional divider, but easier to tune. -- Rick From newsfish@newsfish Tue Dec 29 16:42:52 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Dual Edged Counter Date: Wed, 17 Apr 2013 15:26:46 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <177cd3bd-aeed-4a08-994d-80eb94988a92@googlegroups.com> <64611fed-23e9-4909-8f44-ab3e44534645@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Apr 2013 19:24:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="9fce6e44d3643a774a64f1ed77ec3a22"; logging-data="18462"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/OkL1efzFpfJOhuwCUUA82" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:/l73lBPvdYax77FxEbXX4mEJONI= Xref: mx05.eternal-september.org comp.lang.vhdl:6484 On 4/17/2013 3:18 PM, rickman wrote: > > You might also consider using a DCO. I tried to do that for a few > minutes and couldn't think of how that would work. But I'm pretty sure > there is a way. I'm just drawing a blank at the moment. A DCO will give > you a much more precise average value with one clock cycle of jitter on > the edge, similar to the fractional divider, but easier to tune. Ok, brain cramp over... Use a DCO to generate a ramp signal in as many bits as you want. The step size will set the rate at which it rolls over and so the PWM frequency. Since the DCO can be lots of bits, the duty_cycle can be more bits than with a simple counter. So the point in the cycle where the counter is above the duty_cycle will jitter around a clock edge, but the average can be very precise, as long as your step_size is not an integer ratio to the modulus. You need the steps to walk around the number space. -- Rick From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.58.77 with SMTP id f13mr6153917qah.7.1366237924632; Wed, 17 Apr 2013 15:32:04 -0700 (PDT) X-Received: by 10.49.119.99 with SMTP id kt3mr892247qeb.22.1366237924612; Wed, 17 Apr 2013 15:32:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ca1no1039338qab.0!news-out.google.com!ef9ni1990qab.0!nntp.google.com!ca1no1039337qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Apr 2013 15:32:04 -0700 (PDT) In-Reply-To: <48e01072-ba56-4a9c-813c-345d70c8e236@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.169.117.21; posting-account=kaTTJgkAAABgkpwrvCAIZXRDUPc93Gv5 NNTP-Posting-Host: 82.169.117.21 References: <43ede514-fdf5-4cc9-b855-89df4b6b023f@googlegroups.com> <0cbd3562-68af-4e7a-bfa9-e117df31906c@googlegroups.com> <48e01072-ba56-4a9c-813c-345d70c8e236@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: configurable number of interfaces From: ananth kamath Injection-Date: Wed, 17 Apr 2013 22:32:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6485 Thanks a lot for the timely help. I found even XST supporting it :) On Friday, April 12, 2013 4:16:30 AM UTC+2, KJ wrote: > On Wednesday, April 10, 2013 9:14:38 AM UTC-4, ananth kamath wrote: >=20 > > If I synthesize this code, the port having NULL vectors will not be pre= sent=20 >=20 > > in my entity .. is my understanding correct ? And is the result true fo= r=20 >=20 > > all synthesizers ? Regards, Anantha >=20 >=20 >=20 > It is allowed to have a null vector on the entity. You just have to conn= ect it to a null vector or leave it as 'open'. Either way, the vector is s= till listed in the port section of the entity and it can still be connected= so your source code does not need to be modified for the special case. >=20 >=20 >=20 > Since it is a null vector it will not synthesize to anything. The genera= l use for null vectors is when the vector size is controlled by a generic (= like you had in your post) and a perfectly legitimate setting for that gene= ric happens to result in not actually needing the vector. >=20 >=20 >=20 > As to 'all synthesizers', I dunno but if the one you're using doesn't sup= port it then open a case with them and tell them that their competitiors do= , you're considering switching to their tools which seem to be better suppo= rted. Quartus and Synplify support it. >=20 >=20 >=20 > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.180.10.230 with SMTP id l6mr6822230wib.3.1366269642811; Thu, 18 Apr 2013 00:20:42 -0700 (PDT) X-Received: by 10.182.142.202 with SMTP id ry10mr284208obb.14.1366269642537; Thu, 18 Apr 2013 00:20:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!nntp.giganews.com!19no100983529wie.1!news-out.google.com!hg5ni16271wib.1!nntp.google.com!gp5no45116qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Apr 2013 00:20:42 -0700 (PDT) In-Reply-To: <3195934d-e721-40ab-a069-54426fc8d5d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <8a08004e-14e8-4734-97e9-15d6f3a101ed@googlegroups.com> <856d2e86-43ff-475a-adb8-e37f54ac6580@googlegroups.com> <3195934d-e721-40ab-a069-54426fc8d5d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Convert ADC output format to DAC input From: goouse99@gmail.com Injection-Date: Thu, 18 Apr 2013 07:20:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 73 Xref: mx05.eternal-september.org comp.lang.vhdl:6486 Am Mittwoch, 17. April 2013 15:59:50 UTC+2 schrieb Andy: > I would avoid using std_logic_arith. It is non-standard, non-compliant, d= iffers between tools and vendors, and is generally a bad idea. >=20 >=20 >=20 > If your tools support vhdl-2008, there is a new package ieee.numeric_std_= unsigned, which difines unsigned arithmetic and conversions to/from integer= , but is officially balloted, approved and supported by IEEE. Use to_intege= r() and to_slv() functions from this package. >=20 >=20 >=20 > I disagree whole-heartedly with advice to avoid using integers in synthes= izable RTL. They are accepted by every synthesis tool I know of, and have s= everal advantages, not the least of which is a huge increase in simulation = performance. All HW is implemented in binary, no matter how you describe it= (in decimal, octal, hex, etc). If you want to describe binary using intege= rs, simply base your literals: 2#1011# =3D 16#b# =3D 11. >=20 >=20 >=20 > Andy Hi Andi, integers are convenient to use when you know what you are doing. But for a beginner (The OP doesn't even know the concept of pipelining) it = has many pitfalls. The obvious and easy avoidable one is the waste of bits if you are not rest= ricting the range. Otherwise you may end up with everything done with 32 bi= t datawidth.=20 So someone who wants to create an 8 bit counter can declare it like: signal count : integer range 0 to 2^8-1;=20 This looks nice indeed. So lets do some code-reuse and scale that thing up to get a larger counter: signal count : integer range 0 to 2^64-1; You know it's crap, I know it's crap. What's your guess, does the OP know the reason why this is crap? =20 ____________ The tools won't care about the representation of constants in your code, th= at's right. But maybe the human reader cares. 132 seems to be some average number in decimal. But in Binary (I reduce it to 8 bits here) it will look like this: 10000100 Now it becomes obvious that this number has just two '1'es. For some algorithms this can be quite useful. e.g. A multiplication is reduced to two shifts and an addition. Synthesis tools might recognize this or not, you only know afterwards. Still I admitted, that the OPs choice might be the better one for his appro= ach. My reply to the OP was targeted to someone at the beginner level. Professionals are aware of all the bad things that may happen and avoid the= m blindfolded. So they have a higher degree of freedom in their coding habi= ts. Have a nice synthesis Eilert =20 =20 From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.58.77 with SMTP id f13mr8185698qah.7.1366297402878; Thu, 18 Apr 2013 08:03:22 -0700 (PDT) X-Received: by 10.182.133.100 with SMTP id pb4mr335394obb.29.1366297402792; Thu, 18 Apr 2013 08:03:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no814049qab.0!news-out.google.com!ef9ni885qab.0!nntp.google.com!gp5no814043qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Apr 2013 08:03:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <8a08004e-14e8-4734-97e9-15d6f3a101ed@googlegroups.com> <856d2e86-43ff-475a-adb8-e37f54ac6580@googlegroups.com> <3195934d-e721-40ab-a069-54426fc8d5d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5bb35f8f-f6a6-4ede-be0a-f232c2dd2b67@googlegroups.com> Subject: Re: Convert ADC output format to DAC input From: Andy Injection-Date: Thu, 18 Apr 2013 15:03:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6487 Eilert, Nice explanation... That would have been much more useful advice for the OP, a beginner, than an admonishment to use "signed/unsigned types instead of integer" with no justification. Andy From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr18971841qab.5.1366606887663; Sun, 21 Apr 2013 22:01:27 -0700 (PDT) X-Received: by 10.49.86.98 with SMTP id o2mr96990qez.4.1366606887649; Sun, 21 Apr 2013 22:01:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gp5no1202492qab.0!news-out.google.com!ef9ni2qab.0!nntp.google.com!gp5no4551725qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Apr 2013 22:01:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.22.169.177; posting-account=aO191goAAADb0KPalPotBlV6UIjcijcS NNTP-Posting-Host: 99.22.169.177 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> Subject: Compiling error... not sure how to address the errors From: Zak Asaad Injection-Date: Mon, 22 Apr 2013 05:01:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 297 Xref: mx05.eternal-september.org comp.lang.vhdl:6488 Hi, Im new here and fairly new to vhdl. Im designing a simple register bank= . My main issue is handling the integers in a case statement. I think I am = missing something, but I don't know what. Im using ModelSim to code. Here i= s my code. You can paste it in a program and try to compile to see the erro= r I am getting, but I am going to post the errors, in case you dont have th= e program. Thanks: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity RegBank16x8 IS=20 port( clk : IN std_logic; writeEnable : IN std_logic; w_bk_aluop_reg : IN std_logic_vector = (7 downto 0); rdx_decoder_reg , rdy_decoder_reg : IN std_logic_vector = (3 downto 0); rx_reg_alu, ry_reg_mux : OUT std_logic_vector= (7 downto 0); wr_sp_e_reg_scratchpad : IN std_logic =20 ); end RegBank16x8; architecture RegisterBank of RegBank16x8 is=20 --type register_array is array(0 to 15) of std_logic_vector(7 downto 0); --signal reg : register_array; =20 signal reg0 : std_logic_vector(7 downto 0) :=3D "01111000"; signal reg1 : std_logic_vector(7 downto 0) :=3D "00010100"; signal reg2 : std_logic_vector(7 downto 0) :=3D "00010000"; signal reg3 : std_logic_vector(7 downto 0) :=3D "00000011"; signal reg4 : std_logic_vector(7 downto 0) :=3D "00000000"; signal reg5 : std_logic_vector(7 downto 0) :=3D "01111110"; signal reg6 : std_logic_vector(7 downto 0) :=3D "10000001"; signal reg7 : std_logic_vector(7 downto 0) :=3D "00111000"; signal reg8 : std_logic_vector(7 downto 0) :=3D "10000000"; signal reg9 : std_logic_vector(7 downto 0) :=3D "11111111"; signal reg10 : std_logic_vector(7 downto 0) :=3D "00111000"; signal reg11 : std_logic_vector(7 downto 0) :=3D "00000000"; signal reg12 : std_logic_vector(7 downto 0) :=3D "01010010"; signal reg13 : std_logic_vector(7 downto 0) :=3D "00100100"; signal reg14 : std_logic_vector(7 downto 0) :=3D "00000001"; signal reg15 : std_logic_vector(7 downto 0) :=3D "01111111"; =20 =20 =20 begin =20 variable temp_rxCount : range Integer 0 to 16; variable temp_ryCount : range Integer 1 to 17; =20 variable rxCount : range Integer 0 to 16; variable ryCount : range Integer 1 to 17; =20 ---- reg0 <=3D "00000000"; -- reg1 <=3D "00011010"; -- reg2 <=3D "00100101"; -- reg3 <=3D "00100010"; -- reg4 <=3D "01011010"; -- reg5 <=3D "00000000"; -- reg6 <=3D "00000010"; -- reg7 <=3D "00010011"; -- reg8 <=3D "10000001"; -- reg9 <=3D "00001000"; -- reg10 <=3D "00000111"; -- reg11 <=3D "01010101"; -- reg12 <=3D "01100110"; -- reg13 <=3D "00000110"; -- reg14 <=3D "01111111"; -- reg15 <=3D "01111110"; =20 =20 first: process (clk, writeEnable, rdx_decoder_reg, rdy_decoder_reg, w_b= k_aluop_reg) =20 begin =20 =20 =20 if clk'event and clk=3D'1' then =20 if (wr_sp_e_reg_scratchpad =3D '1') then --if register is enabled = to write to scratchpad, execute the following =20 =20 =20 case rxCount is when 0 =3D> rx_reg_alu <=3D reg0; when 2 =3D> rx_reg_alu <=3D reg2; when 4 =3D> rx_reg_alu <=3D reg4; when 6 =3D> rx_reg_alu <=3D reg6; when 8 =3D> rx_reg_alu <=3D reg8; when 10 =3D> rx_reg_alu <=3D reg10; when 12 =3D> rx_reg_alu <=3D reg12; when 14 =3D> rx_reg_alu <=3D reg14; = =20 when others =3D> null;=20 end case; =20 temp_rxCount :=3D rxCount + 2; rxCount :=3D temp_rxCount; =20 =20 case ryCount is when 1 =3D> ry_reg_mux <=3D reg1; when 3 =3D> ry_reg_mux <=3D reg3; when 5 =3D> ry_reg_mux <=3D reg5; when 7 =3D> ry_reg_mux <=3D reg7; when 9 =3D> ry_reg_mux <=3D reg9; when 11 =3D> ry_reg_mux <=3D reg11; when 13 =3D> ry_reg_mux <=3D reg13; when 15 =3D> ry_reg_mux <=3D reg15; = =20 when others =3D> null;=20 end case; =20 temp_ryCount :=3D ryCount + 2; ryCount :=3D temp_ryCount; =20 if (rxCount =3D 16) then rxCount :=3D 0; end if; if (ryCount =3D 17) then ryCount :=3D 1; end if; =20 else --if register is NOT enabled to write to scratchpad then will= continue with usual processes =20 if (writeEnable=3D'1') then=20 =20 case rdx_decoder_reg is when "0000" =3D> reg0 <=3D w_bk_aluop_reg; when "0001" =3D> reg1 <=3D w_bk_aluop_reg; when "0010" =3D> reg2 <=3D w_bk_aluop_reg; when "0011" =3D> reg3 <=3D w_bk_aluop_reg; when "0100" =3D> reg4 <=3D w_bk_aluop_reg; when "0101" =3D> reg5 <=3D w_bk_aluop_reg; when "0110" =3D> reg6 <=3D w_bk_aluop_reg; when "0111" =3D> reg7 <=3D w_bk_aluop_reg; when "1000" =3D> reg8 <=3D w_bk_aluop_reg; when "1001" =3D> reg9 <=3D w_bk_aluop_reg; when "1010" =3D> reg10<=3D w_bk_aluop_reg; when "1011" =3D> reg11<=3D w_bk_aluop_reg; when "1100" =3D> reg12<=3D w_bk_aluop_reg; when "1101" =3D> reg13<=3D w_bk_aluop_reg; when "1110" =3D> reg14<=3D w_bk_aluop_reg; when "1111" =3D> reg15<=3D w_bk_aluop_reg; = =20 when others =3D> null;=20 end case; =20 else case rdx_decoder_reg is when "0000" =3D> rx_reg_alu <=3D reg0; when "0001" =3D> rx_reg_alu <=3D reg1; when "0010" =3D> rx_reg_alu <=3D reg2; when "0011" =3D> rx_reg_alu <=3D reg3; when "0100" =3D> rx_reg_alu <=3D reg4; when "0101" =3D> rx_reg_alu <=3D reg5; when "0110" =3D> rx_reg_alu <=3D reg6; when "0111" =3D> rx_reg_alu <=3D reg7; when "1000" =3D> rx_reg_alu <=3D reg8; when "1001" =3D> rx_reg_alu <=3D reg9; when "1010" =3D> rx_reg_alu <=3D reg10; when "1011" =3D> rx_reg_alu <=3D reg11; when "1100" =3D> rx_reg_alu <=3D reg12; when "1101" =3D> rx_reg_alu <=3D reg13; when "1110" =3D> rx_reg_alu <=3D reg14; when "1111" =3D> rx_reg_alu <=3D reg15; = =20 when others =3D> null;=20 end case; =20 case rdy_decoder_reg is when "0000" =3D> ry_reg_mux <=3D reg0; when "0001" =3D> ry_reg_mux <=3D reg1; when "0010" =3D> ry_reg_mux <=3D reg2; when "0011" =3D> ry_reg_mux <=3D reg3; when "0100" =3D> ry_reg_mux <=3D reg4; when "0101" =3D> ry_reg_mux <=3D reg5; when "0110" =3D> ry_reg_mux <=3D reg6; when "0111" =3D> ry_reg_mux <=3D reg7; when "1000" =3D> ry_reg_mux <=3D reg8; when "1001" =3D> ry_reg_mux <=3D reg9; when "1010" =3D> ry_reg_mux <=3D reg10; when "1011" =3D> ry_reg_mux <=3D reg11; when "1100" =3D> ry_reg_mux <=3D reg12; when "1101" =3D> ry_reg_mux <=3D reg13; when "1110" =3D> ry_reg_mux <=3D reg14; when "1111" =3D> ry_reg_mux <=3D reg15; = =20 when others =3D> null;=20 end case; =20 end if; =20 end if; end if; end process first; end RegisterBank; And here are the errors the code is throwing: ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(44): near "variable": syntax error ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(79): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(80): Enumeration literal '0' is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(81): Enumeration literal '2' is type std.STANDARD.CHARACTER; expe= cting type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(82): Integer literal 4 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(83): Integer literal 6 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(84): Integer literal 8 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(85): Integer literal 10 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(86): Integer literal 12 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(87): Integer literal 14 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(91): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(91): (vcom-1136) Unknown identifier "temp_rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(91): Bad right hand side (infix expression) in variable assignmen= t. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(92): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(92): (vcom-1136) Unknown identifier "temp_rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(95): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(96): Integer literal 1 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(97): Integer literal 3 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(98): Integer literal 5 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(99): Integer literal 7 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(100): Integer literal 9 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(101): Integer literal 11 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(102): Integer literal 13 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(103): Integer literal 15 is not of type (error). ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(107): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(107): (vcom-1136) Unknown identifier "temp_ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(107): Bad right hand side (infix expression) in variable assignme= nt. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(108): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(108): (vcom-1136) Unknown identifier "temp_ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(110): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(110): Type error resolving infix expression "=3D" as type std.STA= NDARD.BOOLEAN. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(111): Target type (error) in variable assignment is different fro= m expression type Integer. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(113): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(113): Type error resolving infix expression "=3D" as type std.STA= NDARD.BOOLEAN. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(114): Target type (error) in variable assignment is different fro= m expression type Integer. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount". ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(186): VHDL Compiler exiting I know it looks like a lot of errors but Im sure its a small issue that wil= l get rid of most of the errors. Thanks for looking From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr18698050qab.0.1366607022255; Sun, 21 Apr 2013 22:03:42 -0700 (PDT) X-Received: by 10.49.27.233 with SMTP id w9mr2215663qeg.23.1366607022172; Sun, 21 Apr 2013 22:03:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.87.MISMATCH!gp5no1202781qab.0!news-out.google.com!ef9ni2qab.0!nntp.google.com!gp5no4551991qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Apr 2013 22:03:41 -0700 (PDT) In-Reply-To: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.22.169.177; posting-account=aO191goAAADb0KPalPotBlV6UIjcijcS NNTP-Posting-Host: 99.22.169.177 References: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4105f230-121a-4491-aa97-59323e234e07@googlegroups.com> Subject: Re: Compiling error... not sure how to address the errors From: Zak Asaad Injection-Date: Mon, 22 Apr 2013 05:03:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx05.eternal-september.org comp.lang.vhdl:6489 Oh and the errors are all coming from the first two case statements utilizing the rxCount and ryCount variables inside the cases. The rest of the code after those is ok because the first two case statements are being added to working/compiling code. From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr19076666qab.5.1366610502746; Sun, 21 Apr 2013 23:01:42 -0700 (PDT) X-Received: by 10.49.37.39 with SMTP id v7mr2222840qej.27.1366610502717; Sun, 21 Apr 2013 23:01:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no4559637qab.0!news-out.google.com!ef9ni2qab.0!nntp.google.com!gp5no4559636qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Apr 2013 23:01:42 -0700 (PDT) In-Reply-To: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Compiling error... not sure how to address the errors From: goouse99@gmail.com Injection-Date: Mon, 22 Apr 2013 06:01:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6490 Am Montag, 22. April 2013 07:01:27 UTC+2 schrieb Zak Asaad: > Hi, Im new here and fairly new to vhdl. Im designing a simple register ba= nk. My main issue is handling the integers in a case statement. I think I a= m missing something, but I don't know what. Im using ModelSim to code. Here= is my code. You can paste it in a program and try to compile to see the er= ror I am getting, but I am going to post the errors, in case you dont have = the program. Thanks: >=20 >=20 >=20 > library ieee; >=20 > use ieee.std_logic_1164.all; >=20 > use ieee.std_logic_arith.all; >=20 >=20 >=20 > entity RegBank16x8 IS=20 >=20 > port( clk : IN std_logic; >=20 > writeEnable : IN std_logic; >=20 > w_bk_aluop_reg : IN std_logic_vecto= r (7 downto 0); >=20 > rdx_decoder_reg , rdy_decoder_reg : IN std_logic_vecto= r (3 downto 0); >=20 > rx_reg_alu, ry_reg_mux : OUT std_logic_vect= or (7 downto 0); >=20 > wr_sp_e_reg_scratchpad : IN std_logic >=20 > =20 >=20 > ); >=20 >=20 >=20 > end RegBank16x8; >=20 >=20 >=20 > architecture RegisterBank of RegBank16x8 is=20 >=20 >=20 >=20 > --type register_array is array(0 to 15) of std_logic_vector(7 downto 0)= ; >=20 > --signal reg : register_array; >=20 > =20 >=20 > signal reg0 : std_logic_vector(7 downto 0) :=3D "01111000"; >=20 > signal reg1 : std_logic_vector(7 downto 0) :=3D "00010100"; >=20 > signal reg2 : std_logic_vector(7 downto 0) :=3D "00010000"; >=20 > signal reg3 : std_logic_vector(7 downto 0) :=3D "00000011"; >=20 > signal reg4 : std_logic_vector(7 downto 0) :=3D "00000000"; >=20 > signal reg5 : std_logic_vector(7 downto 0) :=3D "01111110"; >=20 > signal reg6 : std_logic_vector(7 downto 0) :=3D "10000001"; >=20 > signal reg7 : std_logic_vector(7 downto 0) :=3D "00111000"; >=20 > signal reg8 : std_logic_vector(7 downto 0) :=3D "10000000"; >=20 > signal reg9 : std_logic_vector(7 downto 0) :=3D "11111111"; >=20 > signal reg10 : std_logic_vector(7 downto 0) :=3D "00111000"; >=20 > signal reg11 : std_logic_vector(7 downto 0) :=3D "00000000"; >=20 > signal reg12 : std_logic_vector(7 downto 0) :=3D "01010010"; >=20 > signal reg13 : std_logic_vector(7 downto 0) :=3D "00100100"; >=20 > signal reg14 : std_logic_vector(7 downto 0) :=3D "00000001"; >=20 > signal reg15 : std_logic_vector(7 downto 0) :=3D "01111111"; >=20 > =20 >=20 > =20 >=20 >=20 >=20 > =20 >=20 > begin >=20 > =20 >=20 > variable temp_rxCount : range Integer 0 to 16; >=20 > variable temp_ryCount : range Integer 1 to 17; >=20 > =20 >=20 > variable rxCount : range Integer 0 to 16; >=20 > variable ryCount : range Integer 1 to 17; >=20 > =20 >=20 > ---- reg0 <=3D "00000000"; >=20 > -- reg1 <=3D "00011010"; >=20 > -- reg2 <=3D "00100101"; >=20 > -- reg3 <=3D "00100010"; >=20 > -- reg4 <=3D "01011010"; >=20 > -- reg5 <=3D "00000000"; >=20 > -- reg6 <=3D "00000010"; >=20 > -- reg7 <=3D "00010011"; >=20 > -- reg8 <=3D "10000001"; >=20 > -- reg9 <=3D "00001000"; >=20 > -- reg10 <=3D "00000111"; >=20 > -- reg11 <=3D "01010101"; >=20 > -- reg12 <=3D "01100110"; >=20 > -- reg13 <=3D "00000110"; >=20 > -- reg14 <=3D "01111111"; >=20 > -- reg15 <=3D "01111110"; >=20 > =20 >=20 > =20 >=20 > first: process (clk, writeEnable, rdx_decoder_reg, rdy_decoder_reg, w= _bk_aluop_reg) =20 >=20 > begin >=20 > =20 >=20 > =20 >=20 > =20 >=20 > if clk'event and clk=3D'1' then >=20 > =20 >=20 > if (wr_sp_e_reg_scratchpad =3D '1') then --if register is enable= d to write to scratchpad, execute the following >=20 > =20 >=20 > =20 >=20 > =20 >=20 > case rxCount is >=20 > when 0 =3D> rx_reg_alu <=3D reg0; >=20 > when 2 =3D> rx_reg_alu <=3D reg2; >=20 > when 4 =3D> rx_reg_alu <=3D reg4; >=20 > when 6 =3D> rx_reg_alu <=3D reg6; >=20 > when 8 =3D> rx_reg_alu <=3D reg8; >=20 > when 10 =3D> rx_reg_alu <=3D reg10; >=20 > when 12 =3D> rx_reg_alu <=3D reg12; >=20 > when 14 =3D> rx_reg_alu <=3D reg14; = =20 >=20 > when others =3D> null;=20 >=20 > end case; >=20 > =20 >=20 > temp_rxCount :=3D rxCount + 2; >=20 > rxCount :=3D temp_rxCount; >=20 > =20 >=20 > =20 >=20 > case ryCount is >=20 > when 1 =3D> ry_reg_mux <=3D reg1; >=20 > when 3 =3D> ry_reg_mux <=3D reg3; >=20 > when 5 =3D> ry_reg_mux <=3D reg5; >=20 > when 7 =3D> ry_reg_mux <=3D reg7; >=20 > when 9 =3D> ry_reg_mux <=3D reg9; >=20 > when 11 =3D> ry_reg_mux <=3D reg11; >=20 > when 13 =3D> ry_reg_mux <=3D reg13; >=20 > when 15 =3D> ry_reg_mux <=3D reg15; = =20 >=20 > when others =3D> null;=20 >=20 > end case; >=20 > =20 >=20 > temp_ryCount :=3D ryCount + 2; >=20 > ryCount :=3D temp_ryCount; >=20 > =20 >=20 > if (rxCount =3D 16) then >=20 > rxCount :=3D 0; >=20 > end if; >=20 > if (ryCount =3D 17) then >=20 > ryCount :=3D 1; >=20 > end if; >=20 > =20 >=20 > else --if register is NOT enabled to write to scratchpad then wi= ll continue with usual processes >=20 > =20 >=20 > if (writeEnable=3D'1') then=20 >=20 > =20 >=20 > case rdx_decoder_reg is >=20 > when "0000" =3D> reg0 <=3D w_bk_aluop_reg; >=20 > when "0001" =3D> reg1 <=3D w_bk_aluop_reg; >=20 > when "0010" =3D> reg2 <=3D w_bk_aluop_reg; >=20 > when "0011" =3D> reg3 <=3D w_bk_aluop_reg; >=20 > when "0100" =3D> reg4 <=3D w_bk_aluop_reg; >=20 > when "0101" =3D> reg5 <=3D w_bk_aluop_reg; >=20 > when "0110" =3D> reg6 <=3D w_bk_aluop_reg; >=20 > when "0111" =3D> reg7 <=3D w_bk_aluop_reg; >=20 > when "1000" =3D> reg8 <=3D w_bk_aluop_reg; >=20 > when "1001" =3D> reg9 <=3D w_bk_aluop_reg; >=20 > when "1010" =3D> reg10<=3D w_bk_aluop_reg; >=20 > when "1011" =3D> reg11<=3D w_bk_aluop_reg; >=20 > when "1100" =3D> reg12<=3D w_bk_aluop_reg; >=20 > when "1101" =3D> reg13<=3D w_bk_aluop_reg; >=20 > when "1110" =3D> reg14<=3D w_bk_aluop_reg; >=20 > when "1111" =3D> reg15<=3D w_bk_aluop_reg; = =20 >=20 > when others =3D> null;=20 >=20 > end case; >=20 > =20 >=20 > else >=20 > case rdx_decoder_reg is >=20 > when "0000" =3D> rx_reg_alu <=3D reg0; >=20 > when "0001" =3D> rx_reg_alu <=3D reg1; >=20 > when "0010" =3D> rx_reg_alu <=3D reg2; >=20 > when "0011" =3D> rx_reg_alu <=3D reg3; >=20 > when "0100" =3D> rx_reg_alu <=3D reg4; >=20 > when "0101" =3D> rx_reg_alu <=3D reg5; >=20 > when "0110" =3D> rx_reg_alu <=3D reg6; >=20 > when "0111" =3D> rx_reg_alu <=3D reg7; >=20 > when "1000" =3D> rx_reg_alu <=3D reg8; >=20 > when "1001" =3D> rx_reg_alu <=3D reg9; >=20 > when "1010" =3D> rx_reg_alu <=3D reg10; >=20 > when "1011" =3D> rx_reg_alu <=3D reg11; >=20 > when "1100" =3D> rx_reg_alu <=3D reg12; >=20 > when "1101" =3D> rx_reg_alu <=3D reg13; >=20 > when "1110" =3D> rx_reg_alu <=3D reg14; >=20 > when "1111" =3D> rx_reg_alu <=3D reg15; = =20 >=20 > when others =3D> null;=20 >=20 > end case; >=20 > =20 >=20 > case rdy_decoder_reg is >=20 > when "0000" =3D> ry_reg_mux <=3D reg0; >=20 > when "0001" =3D> ry_reg_mux <=3D reg1; >=20 > when "0010" =3D> ry_reg_mux <=3D reg2; >=20 > when "0011" =3D> ry_reg_mux <=3D reg3; >=20 > when "0100" =3D> ry_reg_mux <=3D reg4; >=20 > when "0101" =3D> ry_reg_mux <=3D reg5; >=20 > when "0110" =3D> ry_reg_mux <=3D reg6; >=20 > when "0111" =3D> ry_reg_mux <=3D reg7; >=20 > when "1000" =3D> ry_reg_mux <=3D reg8; >=20 > when "1001" =3D> ry_reg_mux <=3D reg9; >=20 > when "1010" =3D> ry_reg_mux <=3D reg10; >=20 > when "1011" =3D> ry_reg_mux <=3D reg11; >=20 > when "1100" =3D> ry_reg_mux <=3D reg12; >=20 > when "1101" =3D> ry_reg_mux <=3D reg13; >=20 > when "1110" =3D> ry_reg_mux <=3D reg14; >=20 > when "1111" =3D> ry_reg_mux <=3D reg15; = =20 >=20 > when others =3D> null;=20 >=20 > end case; >=20 > =20 >=20 > end if; =20 >=20 > end if; >=20 > end if; >=20 > end process first; >=20 > end RegisterBank; >=20 >=20 >=20 >=20 >=20 > And here are the errors the code is throwing: >=20 >=20 >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(44): near "variable": syntax error >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(79): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(80): Enumeration literal '0' is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(81): Enumeration literal '2' is type std.STANDARD.CHARACTER; ex= pecting type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(82): Integer literal 4 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(83): Integer literal 6 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(84): Integer literal 8 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(85): Integer literal 10 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(86): Integer literal 12 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(87): Integer literal 14 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(91): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(91): (vcom-1136) Unknown identifier "temp_rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(91): Bad right hand side (infix expression) in variable assignm= ent. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(92): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(92): (vcom-1136) Unknown identifier "temp_rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(95): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(96): Integer literal 1 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(97): Integer literal 3 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(98): Integer literal 5 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(99): Integer literal 7 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(100): Integer literal 9 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(101): Integer literal 11 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(102): Integer literal 13 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(103): Integer literal 15 is not of type (error). >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(107): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(107): (vcom-1136) Unknown identifier "temp_ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(107): Bad right hand side (infix expression) in variable assign= ment. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(108): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(108): (vcom-1136) Unknown identifier "temp_ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(110): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(110): Type error resolving infix expression "=3D" as type std.S= TANDARD.BOOLEAN. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(111): Target type (error) in variable assignment is different f= rom expression type Integer. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(113): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(113): Type error resolving infix expression "=3D" as type std.S= TANDARD.BOOLEAN. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(114): Target type (error) in variable assignment is different f= rom expression type Integer. >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount". >=20 > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterB= ank16x8.vhd(186): VHDL Compiler exiting >=20 >=20 >=20 > I know it looks like a lot of errors but Im sure its a small issue that w= ill get rid of most of the errors. Thanks for looking Hi, you have missed the very first error on line 44. ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBan= k16x8.vhd(44): near "variable": syntax error=20 Variables have to be declared inside a process. Have a nice simulation Eilert From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.178.205 with SMTP id bn13mr19343854qab.3.1366618501337; Mon, 22 Apr 2013 01:15:01 -0700 (PDT) X-Received: by 10.49.35.111 with SMTP id g15mr2298037qej.15.1366618501322; Mon, 22 Apr 2013 01:15:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no4595417qab.0!news-out.google.com!ef9ni2qab.0!nntp.google.com!gp5no4595415qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 01:15:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.203.64.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.203.64.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: CFP - High-level synthesis - Methodologies and Practice From: Nikolaos Kavvadias Injection-Date: Mon, 22 Apr 2013 08:15:01 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6491 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Hindawi VLSI Design Special issue on High-level synthesis: Methodologies and Practice =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Call for Papers --------------- Current VLSI technology allows the design of sophisticated digital systems = with ever-growing demands in performance and power/energy consumption. Rapi= dly changing user demands, unprecedented applications, evolved existing, or= newly introduced standards, continuously shape the computational landscape= . It has long been observed that human designers' productivity does not escal= ate sufficiently to match the corresponding increase in chip complexity. Th= is technology-productivity gap is probably the most important problem in th= e industrial development of innovative products. A dramatic increase in des= igner productivity is only possible through the adoption and practicing of = methodologies that raise the specification abstraction level, ingeniously h= iding low-level, time-consuming, error-prone details. New EDA (Electronic D= esign Automation) methodologies aim to generate high-performance digital de= signs from high-level descriptions, a process called High-Level Synthesis (= HLS). The input to this process is usually an algorithmic-level description= , generating synthesizable register-transfer level designs that can be impl= emented on FPGAs or ASICs We invite authors from both the academic and industrial communities to cont= ribute original research articles as well as review articles that present n= ew high-level synthesis methodologies and techniques or showcase interestin= g aspects of their practice. Potential topics include, but are not limited = to: - Very high-level specifications and associated models of computation - Challenges in high-level synthesis for heterogeneous manycore custom comp= utation on FPGA-based platforms - Imperative-, functional-, and concurrency-oriented domain-specific langua= ges for hardware compilation - Transparent optimization through code refactoring and source-to-source tr= ansformations - Intermediate representations for multistage transformation and optimizati= on - Link-time and interprocedural optimizations for improving whole program h= ardware compilation - Automatic compiler retargeting for efficient hardware generation - New approaches for compiling dynamic languages to hardware - Architecture description languages (ADLs) for automated hardware architec= ture and toolchain generation - Early assessment, design-space exploration, and analysis tools in the HLS= environment - Applying HLS for application-specific programmable processor generation Before submission authors should carefully read over the journal=92s Author= Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guid= elines/. Prospective authors should submit an electronic copy of their comp= lete manuscript through the journal Manuscript Tracking System at http://mt= s.hindawi.com/submit/journals/vlsi/hsmp/ according to the following timetab= le: Important Dates --------------- Manuscript Due: Friday, 2 August 2013 First Round of Reviews: Friday, 25 October 2013 Publication Date: Friday, 20 December 2013 Lead Guest Editor ----------------- Konstantinos Masselos, Department of Computer Science and Technology, Unive= rsity of Peloponnese, Tripolis 22100, Greece Guest Editors ------------- Steven Derrien, University of Rennes 1, INRIA Research Institute, Rennes, F= rance Nikolaos Kavvadias, Ajax Compilers, Athens, Greece Hiren D. Patel, University of Waterloo, Waterloo, ON, Canada N2L 3G1 Direct link ----------- http://www.hindawi.com/journals/vlsi/si/320389/cfp/ From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.66.226.233 with SMTP id rv9mr2493355pac.42.1366620975268; Mon, 22 Apr 2013 01:56:15 -0700 (PDT) X-Received: by 10.49.53.6 with SMTP id x6mr44602qeo.11.1366620974703; Mon, 22 Apr 2013 01:56:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!fb4no2578520pbd.1!news-out.google.com!bp1ni188pbd.1!nntp.google.com!ok2no2479468pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 01:56:14 -0700 (PDT) In-Reply-To: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f15429c-d3a5-4b47-8873-7a84af22837c@googlegroups.com> Subject: Re: Compiling error... not sure how to address the errors From: Thomas Stanka Injection-Date: Mon, 22 Apr 2013 08:56:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6492 Am Montag, 22. April 2013 07:01:27 UTC+2 schrieb Zak Asaad: > use ieee.std_logic_arith.all; No error, but source of a lot problems. Using this library is in best case outdated since 10 years, as it is despite beeing named ieee no standard and might vary from tool to tool. Please use numeric_std instead. > variable temp_rxCount : range Integer 0 to 16; [..] > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC > Project/RegisterBank16x8.vhd(44): near "variable": syntax error This definition is wrong and causes most likely also most following errors. 1. put in in process 2. Integer range 0 to 16 (you sure not to use 0 to 15 instead?) BTW is there a reason, why you avoid array for the regfile? e.g: type regfile_t is array 0 to 15 of std_ulogic_vector(7 downto 0) use ieee.numeric_std.all; signal my_regfile : regfile_t; -- initial signal assignments are dangerous! if reset = activelevel then my_regfile <= (0 => x"38", 1 => x"14",...) elsif rising_edge(Clk) then rx_reg_alu <= my_regfile(rx_count); ry_reg_alu <= my_regfile(ry_count); ... if write_enable='1' then my_regfile(to_integer(unsigned(rdx_decoder_reg))) <= w_bk_aluop_reg; end if; .. best regards Thomas From newsfish@newsfish Tue Dec 29 16:42:52 2015 X-Received: by 10.224.185.17 with SMTP id cm17mr6005934qab.6.1366637764275; Mon, 22 Apr 2013 06:36:04 -0700 (PDT) X-Received: by 10.49.27.5 with SMTP id p5mr2321148qeg.32.1366637764108; Mon, 22 Apr 2013 06:36:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no1357501qab.0!news-out.google.com!ef9ni2qab.0!nntp.google.com!gp5no4709172qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 06:36:03 -0700 (PDT) In-Reply-To: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54c46d6f-eb1f-4ef5-b7f3-d6a85d8600c8@googlegroups.com> Subject: Re: Compiling error... not sure how to address the errors From: Andy Injection-Date: Mon, 22 Apr 2013 13:36:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6493 In addition to previously noted problems, some additional suggestions: Clocked processes' sensitivity lists should not contain signals other than = the clock, and possibly an asynchronous reset, if applicable. Use the rising_edge(clk) function instead of clk'event and clk =3D '1' to d= etect the clock edge; the function is standard, more robust, and more reada= ble. Integer counters don't rollover in simulation. Synthesis optimization will = usually implement a rollover counter, but then the behavior of your circuit= and your simulation will not agree. If a rollover is desired for integer c= ounters, use "(count + 1) mod 16", where mod's RH argument is a power of tw= o. Resetting via initialization is hazardous, and non-portable. Implement a HW= reset (either asynchronous or synchronous). If your tools support the vhdl-2008 language version, you can use the ieee.= numeric_std_unsigned package, which defines arithmetic operations on std_lo= gic_vectors using an unsigned interpretation of the contents. It is similar= to std_logic_arith in concept, but is an officially supported IEEE standar= d package (like numeric_std). It also defines to_integer() and to_slv() con= version functions. I strongly agree with the use of arrays for the registers in an application= such as this.=20 Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.88.200 with SMTP id b8mr21685718qam.8.1366687281014; Mon, 22 Apr 2013 20:21:21 -0700 (PDT) X-Received: by 10.49.86.98 with SMTP id o2mr513898qez.4.1366687280985; Mon, 22 Apr 2013 20:21:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no5009736qab.0!news-out.google.com!ef9ni833qab.0!nntp.google.com!gp5no1655297qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 20:21:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.179.160.156; posting-account=XTnbHgoAAABC9bENYRS1C3x2yCQQx9Fp NNTP-Posting-Host: 70.179.160.156 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b2eddc8-7b71-4e61-abae-cc795d9ea94a@googlegroups.com> Subject: Compiler Question From: VerilogNewb Injection-Date: Tue, 23 Apr 2013 03:21:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6494 Hello, I'm new to this group and new to Verilog and am having a compiler error for what i hope is a simple syntax mistake. I'm a first year college student with a little background in Java, that might show in how I wrote my verilog code... I'd rather not put my entire code onto this page since sharing projects between students would constitute cheating and if someone sniped it I'd never know until it was too late... So I'll post a general area of where I'm getting an error, and if you can see what I'm doing wrong, that'd be nice but if you would like to see the rest just let me know. ERRORS IM RECEIVING: Error (10170): Verilog HDL syntax error at controller.v(25) near text "always"; expecting "end" Error (10170): Verilog HDL syntax error at controller.v(43) near text "always"; expecting "end" Error (10170): Verilog HDL syntax error at controller.v(165) near text "always"; expecting "end" Error (10170): Verilog HDL syntax error at controller.v(188) near text "always"; expecting "end" Error (10112): Ignored design unit "controller" at controller.v(1) due to previous errors Info: Found 0 design units, including 0 entities, in source file controller.v Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings Error: Peak virtual memory: 199 megabytes Error: Processing ended: Mon Apr 22 22:02:24 2013 Error: Elapsed time: 00:00:00 Error: Total CPU time (on all processors): 00:00:00 Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings ----------------------------------------------------------------- A sample of my code with most of the case statement info removed: always @ (posedge clk) begin always @ (posedge enter) begin case (inputState) endcase // end case 1 end // end inner always 1 always @ (inputState) begin case (inputState) endcase // end case 2 end // end inner always 2 end // end outer always ----------------------------------------------------------------- the first error happens at the second always @: "always @ (posedge clk) begin" but i know its connected to the end at my line 41 which is the end at: "end // end inner always 1" the second error happens at the third always @: "always @ (inputState) begin" but i know its connected to the end at my line 58 which is the end at: "end // end inner always 2" The other two syntax errors happen later in the code but in similiar circumstance (2 always @ statements within another always @ statement) Is there an issue of trying to have an always @ statement within another always @ statement? Any help you could give would be appreciated. From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.58.77 with SMTP id f13mr21908350qah.7.1366696744501; Mon, 22 Apr 2013 22:59:04 -0700 (PDT) X-Received: by 10.49.27.233 with SMTP id w9mr2646437qeg.23.1366696744473; Mon, 22 Apr 2013 22:59:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gp5no5054886qab.0!news-out.google.com!ef9ni9516qab.0!nntp.google.com!gp5no5054884qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 22:59:04 -0700 (PDT) In-Reply-To: <0f15429c-d3a5-4b47-8873-7a84af22837c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=152.15.112.168; posting-account=aO191goAAADb0KPalPotBlV6UIjcijcS NNTP-Posting-Host: 152.15.112.168 References: <3ae1d34c-c958-4915-b960-2420f83f0e0f@googlegroups.com> <0f15429c-d3a5-4b47-8873-7a84af22837c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6bc7c6e7-0729-4757-a866-66e9e234597c@googlegroups.com> Subject: Re: Compiling error... not sure how to address the errors From: Zak Asaad Injection-Date: Tue, 23 Apr 2013 05:59:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 79 Xref: mx05.eternal-september.org comp.lang.vhdl:6495 On Monday, April 22, 2013 4:56:14 AM UTC-4, Thomas Stanka wrote: > Am Montag, 22. April 2013 07:01:27 UTC+2 schrieb Zak Asaad: >=20 >=20 >=20 > > use ieee.std_logic_arith.all; >=20 >=20 >=20 > No error, but source of a lot problems. Using this library is in best cas= e outdated since 10 years, as it is despite beeing named ieee no standard a= nd might vary from tool to tool. Please use numeric_std instead. >=20 >=20 >=20 > > variable temp_rxCount : range Integer 0 to 16; >=20 > [..]=20 >=20 > > ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC=20 >=20 > > Project/RegisterBank16x8.vhd(44): near "variable": syntax error >=20 >=20 >=20 > This definition is wrong and causes most likely also most following error= s. >=20 > 1. put in in process >=20 > 2. Integer range 0 to 16 (you sure not to use 0 to 15 instead?) >=20 >=20 >=20 >=20 >=20 > BTW is there a reason, why you avoid array for the regfile? >=20 > e.g: >=20 > =20 >=20 > type regfile_t is array 0 to 15 of std_ulogic_vector(7 downto 0) >=20 > use ieee.numeric_std.all; >=20 > signal my_regfile : regfile_t; -- initial signal assignments are dangerou= s! >=20 >=20 >=20 > if reset =3D activelevel then >=20 > my_regfile <=3D (0 =3D> x"38", 1 =3D> x"14",...) >=20 > elsif rising_edge(Clk) then >=20 > rx_reg_alu <=3D my_regfile(rx_count);=20 >=20 > ry_reg_alu <=3D my_regfile(ry_count); >=20 > ... >=20 > if write_enable=3D'1' then >=20 > my_regfile(to_integer(unsigned(rdx_decoder_reg))) <=3D w_bk_aluop_reg= ; >=20 > end if; >=20 > .. >=20 >=20 >=20 > best regards Thomas this actually help get rid of most of the errors. Thanks man. And also, I f= ound a mistake in my signal declarations for my variable assignments. The "= range" comes after the "integer". That was completely foolish on my part. I= got the whole thing working now. Thanks From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.18.133 with SMTP id w5mr8444887qaa.1.1366698883933; Mon, 22 Apr 2013 23:34:43 -0700 (PDT) X-Received: by 10.49.61.234 with SMTP id t10mr2655069qer.16.1366698883919; Mon, 22 Apr 2013 23:34:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!gp5no5067882qab.0!news-out.google.com!ef9ni9516qab.0!nntp.google.com!gp5no5067874qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Apr 2013 23:34:43 -0700 (PDT) In-Reply-To: <2b2eddc8-7b71-4e61-abae-cc795d9ea94a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <2b2eddc8-7b71-4e61-abae-cc795d9ea94a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e7370e3-0916-4ca7-87a3-ce89279dab58@googlegroups.com> Subject: Re: Compiler Question From: goouse99@gmail.com Injection-Date: Tue, 23 Apr 2013 06:34:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6496 Am Dienstag, 23. April 2013 05:21:20 UTC+2 schrieb VerilogNewb: > Hello, > > > > I'm new to this group and new to Verilog and am having a compiler error for what i hope is a simple syntax mistake. I'm a first year college student with a little background in Java, that might show in how I wrote my verilog code... > > > > I'd rather not put my entire code onto this page since sharing projects between students would constitute cheating and if someone sniped it I'd never know until it was too late... > > > > So I'll post a general area of where I'm getting an error, and if you can see what I'm doing wrong, that'd be nice but if you would like to see the rest just let me know. > > > > ERRORS IM RECEIVING: > > > > Error (10170): Verilog HDL syntax error at controller.v(25) near text "always"; expecting "end" > > Error (10170): Verilog HDL syntax error at controller.v(43) near text "always"; expecting "end" > > Error (10170): Verilog HDL syntax error at controller.v(165) near text "always"; expecting "end" > > Error (10170): Verilog HDL syntax error at controller.v(188) near text "always"; expecting "end" > > Error (10112): Ignored design unit "controller" at controller.v(1) due to previous errors > > Info: Found 0 design units, including 0 entities, in source file controller.v > > Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings > > Error: Peak virtual memory: 199 megabytes > > Error: Processing ended: Mon Apr 22 22:02:24 2013 > > Error: Elapsed time: 00:00:00 > > Error: Total CPU time (on all processors): 00:00:00 > > Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings > > > > ----------------------------------------------------------------- > > > > A sample of my code with most of the case statement info removed: > > > > always @ (posedge clk) begin > > > > always @ (posedge enter) begin > > > > case (inputState) > > endcase // end case 1 > > > > end // end inner always 1 > > > > always @ (inputState) begin > > > > case (inputState) > > endcase // end case 2 > > > > end // end inner always 2 > > end // end outer always > > > > ----------------------------------------------------------------- > > > > the first error happens at the second always @: > > "always @ (posedge clk) begin" > > > > but i know its connected to the end at my line 41 which is the end at: > > "end // end inner always 1" > > > > the second error happens at the third always @: > > "always @ (inputState) begin" > > > > but i know its connected to the end at my line 58 which is the end at: > > "end // end inner always 2" > > > > The other two syntax errors happen later in the code but in similiar circumstance (2 always @ statements within another always @ statement) > > > > Is there an issue of trying to have an always @ statement within another always @ statement? > > > > Any help you could give would be appreciated. Hi, this is comp.lang.VHDL so you are quite wrong here. You should choose to post on comp.lang.verilog instead. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Compiler Question Date: Tue, 23 Apr 2013 07:29:39 +0000 (UTC) Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <2b2eddc8-7b71-4e61-abae-cc795d9ea94a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 23 Apr 2013 07:29:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="5760"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fG1WunGUJ/ywIMz6Lj0DMdOyyNOwUU1g=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:yMFYLVqp8QA8Zk9v3DTGCzWy76A= Xref: mx05.eternal-september.org comp.lang.vhdl:6497 On Mon, 22 Apr 2013 20:21:20 -0700, VerilogNewb wrote: > Hello, > > I'm new to this group and new to Verilog and am having a compiler error > for what i hope is a simple syntax mistake. (a) this is comp.lang.vhdl : the Verilog experts are somewhere else. > Is there an issue of trying to have an always @ statement within another > always @ statement? based on the tiny amount of Verilog I've seen, I'm going to say, yes there is : find another approach. This is in the same class as a register with two clocks which must occur exactly simultaneously for anything to happen - use one of them as a clock enable instead. - Brian From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.185.17 with SMTP id cm17mr12817521qab.6.1366878160647; Thu, 25 Apr 2013 01:22:40 -0700 (PDT) X-Received: by 10.49.72.225 with SMTP id g1mr3512274qev.36.1366878160592; Thu, 25 Apr 2013 01:22:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news1.as3257.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.88.MISMATCH!gp5no6704670qab.0!news-out.google.com!ef9ni16888qab.0!nntp.google.com!gp5no6704666qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Apr 2013 01:22:40 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.144.71.14; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F NNTP-Posting-Host: 195.144.71.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e41843f-f3a5-4f8f-8446-8e4d0573fbb8@googlegroups.com> Subject: Design entry poll: which is your favorite editor? From: Philippe Injection-Date: Thu, 25 Apr 2013 08:22:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6498 Hi everybody! There's a new poll on which design entry tool is popular for VHDL / Verilog design entry. Results will be posted in a few weeks. Your participation is greatly appreciated. http://www.vhdleditor.com/design-entry-poll-2013 best regards Philippe From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr27681613qab.0.1366918871356; Thu, 25 Apr 2013 12:41:11 -0700 (PDT) X-Received: by 10.182.42.164 with SMTP id p4mr156386obl.22.1366918871324; Thu, 25 Apr 2013 12:41:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.nobody.at!texta.sil.at!newsfeed.utanet.at!feeder1.cambriumusenet.nl!82.197.223.108.MISMATCH!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.88.MISMATCH!gp5no6950481qab.0!news-out.google.com!ef9ni16888qab.0!nntp.google.com!gp5no6950480qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Apr 2013 12:41:10 -0700 (PDT) In-Reply-To: <35841FEC.167EB0E7@mtu.edu> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=223.235.238.189; posting-account=LJ_fLgoAAADspSPnmu6hrVMRoSdHVO0T NNTP-Posting-Host: 223.235.238.189 References: <35841FEC.167EB0E7@mtu.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <571bd880-5607-4bcd-aae3-58178ac54f52@googlegroups.com> Subject: Re: Application for a job of design engineer From: allen.pegasys@gmail.com Injection-Date: Thu, 25 Apr 2013 19:41:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6499 Looking for design engineers in Michigan - mail to allen.pegasys@gmail.com On Sunday, June 14, 1998 3:00:00 AM UTC-4, Umesh D. Painaik wrote: > Dear Sir/Mam, > > I am applying for a full time job position of design engineer in your > company. > > I am currently pursuing a Master's degree in Electrical engineering > at Michigan Technological University and will be graduating in > July '98. I have been working with the VLSI group in MTU on various > modelling and design aspects of VLSI interconnections. I am also a teaching > assistant in Michigan tech. > > My coursework at Michigan Tech and Vivekanand Institute of technology (my > undergraduate school) has prepared me well to contribute to your > organisation. My analytical and logical skills have been > sharpened by several design projects which are a part of the > course curriculum. > > A strong personal work ethic, an outgoing personality, and a desire > to excel combined with my work experience assures that I will be a > suitable candidate. A call to my references will assure that I have > the technical and interpersonal skills to make working enjoyable as > well as productive. > > I have enclosed my resume with this letter and I would greatly > appreciate an oppurtunity to further discuss my qualifications with > you at your convenience. I can be reached by phone at "906-487-6154" > and also by e-mail at "udpainai@mtu.edu" > > Thank you for your consideration. I look forward to hearing from you. > > Sincerely, > Umesh Painaik > > > > OBJECTIVE : > Application for a design engineer position. > > > NAME : Umesh D. Painaik > > HOME ADDRESS : 225 Hubbel St. ,apt 1 > Houghton ,MI 49931-1533 > phone- 906-487-6154 > > WORK ADDRESS : Michigan Technological University > 1400 ,Townsend drive > Houghton ,MI 49931-1533 > > E-Mail : udpainai@mtu.edu > > > EMPLOYMENT HISTORY :1) Worked in Patni Computer Services as a Junior > Design Engineer from 2/96 to 8/96 > 2) Teaching Assistant at Michigan Tech. University > From 10/96 to till date. > Recitation in pspice network analysis, Magic and > VLSI design. > > > EDUCATIONAL BACKGROUND : 1)B.E. ELECTRONICS ,VESIT ,BOMBAY,1996. GPA 3.6 > 2)Currently in Second year M.S.E.E. with VLSI > option in Michigan Tech univ.,GPA 3.7. > > > ADDITIONAL SKILLS : 1) Knowledge of VHDL,MAGIC,VIEWSIM,Schematics, > Verilog(Learning),Powerview,Xilinx > (Learning),Cadence Valid, Altera MAX+PLUS2, > Smartspice,Spice,Athena,Atlas,TCAD > 2) Knowledge of C,HTML,Java(Learning),UNIX,DOS > 3) Taken courses in > -- Advanced electronic design > -- VLSI (GaAs)interconnections > -- Advanced semiconductor physics > -- Advanced microprocessors and memory elements > -- Computer architecture > -- Digital signal processing > -- Digital communication > -- VLSI fabrication > 3) Thesis topic- `Multisectional Interconnections' > > > RESEARCH BACKGROUND : 1) Project leader in Developing a `DRAM > Controller' using Powerview and viewsim in > undergrad. > 2) Surveys on `SiC applications' and `Ion > implantation using Lasers'. > 3) Research on `Frequency variance in High speed > semiconductor interconnections' in summer > 97-98. > 4) Developement and simulation of `DRAM > Controller' and 'Hamming decoder'using VHDL. > 5) Currently working on CADENCE VALID and TCAD. > 6) Currently working on a proposal topic > `High Speed Multisection interconnections and > their feasibility' > > > HONORS : 1) Dean's list in two successive years in > undergraduate studies. > 2) Best programmer's award in undergraduate studies. > > > OTHER INTERESTS : 1) Treasurer of Indian students association in > Michigan Tech > 2) Student body President in Undergrad University. > 3) Graduate Student Council member in Michigan Tech. > 4) Member of the Soccer team. > 5) Member of Worldwide Indian network. > > VISA STATUS : F1-Visa > > > AVAILABILITY : July 1998 (Willing to relocate) > > > REFERENCES : Available upon request From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: Application for a job of design engineer Date: Fri, 26 Apr 2013 14:06:22 -0700 Organization: Aioe.org NNTP Server Lines: 16 Message-ID: <517AEC4E.9060608@yahoo.com> References: <35841FEC.167EB0E7@mtu.edu> <571bd880-5607-4bcd-aae3-58178ac54f52@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx05.eternal-september.org comp.lang.vhdl:6500 I think Allen Pegasys shows a serious lack of professional ethics and respect by broadcasting somebody's personal information to the world. Once it gets on usenet, there's no getting it back. JJS On 4/25/2013 12:41 PM, allen.pegasys@gmail.com wrote: > Looking for design engineers in Michigan - mail to allen.pegasys@gmail.com > > > On Sunday, June 14, 1998 3:00:00 AM UTC-4, Umesh D. Painaik wrote: >> Dear Sir/Mam, ( personal cover letter and resume deleted ) From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: sll Date: Mon, 29 Apr 2013 14:04:20 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 29 Apr 2013 11:01:04 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="29043"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hWyxhpbY6+kKuQ2wtN0h0X/yMtxJYg3w=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> Cancel-Lock: sha1:zU6Q+e+xAOOtLlPUvsXkKj0iMBE= Xref: mx05.eternal-september.org comp.lang.vhdl:6501 Operators in VHDL are type-dependent. Sll is defined for arrays of bits and booleans. I am not sure about integer. The standard packages extend sll support to the other types. From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: write(output, string) Date: Mon, 29 Apr 2013 14:31:53 +0300 Organization: A noiseless patient Spider Lines: 14 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 29 Apr 2013 11:28:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="5354"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RYFP+z/GUV0b8ICJ7LLsX8ewijyESSmA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 Cancel-Lock: sha1:93qqB/ioqMlcWc59NoZSwnahQoI= Xref: mx05.eternal-september.org comp.lang.vhdl:6502 In the MiniMips I have the following code process begin write (output, "Enter the filename : "); http://opencores.org/websvn,filedetails?repname=minimips&path=%2Fminimips%2Ftrunk%2FminiMIPS%2Fbench%2Fbench_minimips.vhd It seems that output is the famous file variable, defined in the std.textio. Yet, I see no write() function that had the first argument of type 'file'. I wonder why others do not have the problems with simulating this test bench (e.g. here http://stackoverflow.com/questions/7003098/vcd-dump-of-only-a-sub-part-of-the-design-via-modelsim seem to be able consume it)? From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Mon, 29 Apr 2013 21:29:25 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: sll References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 12 Message-ID: <517eca12$0$2236$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Apr 2013 21:29:22 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1367263762 news-1.free.fr 2236 88.185.146.198:1408 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6503 Le 29/04/2013 13:04, valtih1978 a écrit : > Operators in VHDL are type-dependent. Sll is defined for arrays of bits > and booleans. I am not sure about integer. The standard packages extend > sll support to the other types. Hello It doesn't make any sense to define sll for integers in VHDL. Nor for booleans, for that matter. In which package is this so ? In numeric_std it is defined for signed and unsigned (I think), not std_logic_vector Niclas From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp3-1.free.fr!not-for-mail Date: Mon, 29 Apr 2013 22:11:51 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: sll References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> <517eca12$0$2236$426a74cc@news.free.fr> In-Reply-To: <517eca12$0$2236$426a74cc@news.free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 18 Message-ID: <517ed404$0$18736$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Apr 2013 22:11:48 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1367266308 news-1.free.fr 18736 88.185.146.198:1892 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6504 Le 29/04/2013 21:29, Nicolas Matringe a écrit : > Le 29/04/2013 13:04, valtih1978 a écrit : >> Operators in VHDL are type-dependent. Sll is defined for arrays of bits >> and booleans. I am not sure about integer. The standard packages extend >> sll support to the other types. > > Hello > It doesn't make any sense to define sll for integers in VHDL. Nor for > booleans, for that matter. In which package is this so ? > In numeric_std it is defined for signed and unsigned (I think), not > std_logic_vector Ok my bad, it is defined for "arrays of booleans" If you want to shift an array of integer you can define your own, thanks to operator overloading. Nicolas From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!newsfeed.datemas.de!feeder.erje.net!eu.feeder.erje.net!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 29 Apr 2013 18:22:05 -0500 Date: Tue, 30 Apr 2013 00:22:05 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130402 Thunderbird/17.0.5 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: write(output, string) References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-vVD3qx8xp2IkuwVh6Rk86q3dTvAwM/ea1vBmkqkdrQ0A9Z7ao/A7lO8NE6O3G9RvsAibxrKNGt7vgkx!OlEIrJvvViaDYjYoz0XbiYxBI8wvnbEP6p8kFSPYcwtE4Wmfjob0alK2tJv0/++DrsEpDfQBghBh!kTj0FhSnRotnbFz960f3PwqY1Js= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2127 Xref: mx05.eternal-september.org comp.lang.vhdl:6505 On 29/04/13 12:31, valtih1978 wrote: > In the MiniMips I have the following code > > process > begin > write (output, "Enter the filename : "); > > http://opencores.org/websvn,filedetails?repname=minimips&path=%2Fminimips%2Ftrunk%2FminiMIPS%2Fbench%2Fbench_minimips.vhd > > It seems that output is the famous file variable, defined in the > std.textio. Yet, I see no write() function that had the first argument > of type 'file'. I wonder why others do not have the problems with > simulating this test bench (e.g. here > http://stackoverflow.com/questions/7003098/vcd-dump-of-only-a-sub-part-of-the-design-via-modelsim > seem to be able consume it)? > Every file type has an implicit read and implicit write procedure declared - see 1076-2002 3.4.1 File Operations (sorry I don't have the reference for 1076-2008 handy). In other words, this is the implicit write procedure for files of type text *not* the write procedure overloaded in std.textio, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.68.115.204 with SMTP id jq12mr750194pbb.8.1367416301653; Wed, 01 May 2013 06:51:41 -0700 (PDT) X-Received: by 10.49.121.200 with SMTP id lm8mr135457qeb.5.1367416301130; Wed, 01 May 2013 06:51:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!w15no2881388pbs.1!news-out.google.com!bp1ni1073pbd.1!nntp.google.com!jr1no1510372pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 May 2013 06:51:41 -0700 (PDT) In-Reply-To: <517eca12$0$2236$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> <517eca12$0$2236$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: sll From: Andy Injection-Date: Wed, 01 May 2013 13:51:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6506 Numeric_std_unsigned (vhdl-2008) applies the numeric_std-defined operators and functions for unsigned to std_logic_vector. It includes to_integer(slv), and to_slv(natural, size) Borrowing a page from SW, shift operations (with zero fill or sign extension) on integers can be implemented by multiplication or division by powers of two. Modulo by power of two may be required with multiplication to control the overall magnitude. SLL = (int * 2**n) mod 2**m; -- n = shift bits, m=int bits SRL = nat / 2**n; SRA = int / 2**n; Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.88.200 with SMTP id b8mr6811150qam.8.1367439983474; Wed, 01 May 2013 13:26:23 -0700 (PDT) X-Received: by 10.50.1.2 with SMTP id 2mr2986740igi.6.1367439983429; Wed, 01 May 2013 13:26:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s14no1726159qam.0!news-out.google.com!ef9ni40844qab.0!nntp.google.com!s14no1755665qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 May 2013 13:26:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Announcing release of OSVVM 2013.04 From: Jim Lewis Injection-Date: Wed, 01 May 2013 20:26:23 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6507 OSVVM release 2013.04 is now available at either http://www.synthworks.com/= downloads or http://www.osvvm.org/downloads. Open Source VHDL Verification Methodology (OSVVM) is VHDL=92s leading edge = verification methodology. OSVVM makes adding functional coverage, randomiz= ation, and Intelligent Coverage (coverage driven randomization) to your VHD= L testbench simple, concise, and powerful. =20 With OSVVM, you don't need a specialized verification language such as Syst= emVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is a= step ahead. =20 You can get more information about OSVVM at http://www.synthworks.com/blog/= osvvm or at http://www.osvvm.org Get training in our VHDL Testbenches and Verification - OS-VVM Boot Camp. = See http://www.synthworks.com/vhdl_testbench_verification.htm From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Wed, 01 May 2013 22:53:48 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: sll References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> <517eca12$0$2236$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 7 Message-ID: <518180d7$0$2105$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 01 May 2013 22:53:43 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1367441623 news-3.free.fr 2105 88.185.146.198:1190 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6508 Le 01/05/2013 15:51, Andy a écrit : > Numeric_std_unsigned (vhdl-2008) This is heretic ! ;o) Nicolas From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.10.6 with SMTP id n6mr12399361qan.4.1367517758943; Thu, 02 May 2013 11:02:38 -0700 (PDT) X-Received: by 10.49.42.1 with SMTP id j1mr675718qel.41.1367517758892; Thu, 02 May 2013 11:02:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m7no430729qam.0!news-out.google.com!y6ni0qax.0!nntp.google.com!m7no430723qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 May 2013 11:02:38 -0700 (PDT) In-Reply-To: <518180d7$0$2105$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <36af8dc7-0d9d-4889-b59e-ed80e0348451@googlegroups.com> <517eca12$0$2236$426a74cc@news.free.fr> <518180d7$0$2105$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: sll From: Andy Injection-Date: Thu, 02 May 2013 18:02:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6509 I have been using unsigned as my "standard" vector data type for a long tim= e anyway, since it can do anything SLV can, except be compabitle with top l= evel ports on gate level netlists. Numeric_std_unsigned just flips the tabl= e the other way. You still need two different types for signed and unsigned= arithmetic, so it's not a big deal there either. But there are some uses (e.g. one-hot, thermometer, or hamming/ECC encoding= ), for which the new package would permit an ill-advised numeric interpreta= tion, and reserving SLV for those, and using unsigned/signed for others mig= ht makes sense. On the other hand, detecting all zeros by comparing to an i= nteger literal 0 is very user friendly even in those cases. YMMV. Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: clocked process and sensitivity list Date: Fri, 03 May 2013 11:51:54 +0200 Lines: 54 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 2hbLNNbH5wrJ/DwheEpbiw45IyxLVgpuLXcZz4tb9YtqyAw1dC Cancel-Lock: sha1:wpEhwWlLVoLPMYLkUyZi48TgVGg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6510 Hi everyone (geez has been a long time since my last post...), I'm looking at a piece of code that I would feel embarrassed to post here and when I synthesize it I get a warning about 'Feedback mux created for signal...'. Any insight on the type of warning? I am also puzzled about the style used in the code which goes along these lines: process (clr, rst, foo, bar, foobar) begin if rst = '1' then -- a bunch of assignments elsif foo = '1' then -- another bunch of assignments elsif bar = '1' then -- another bloody bunch of assignments elsif (bar = '0') and (foo = '1') and (foobar = '1') then -- another insane bunch of assignments elsif rising_edge(clk) then case mysterious_signal is when '1' => foobar <= '0'; mysterious_signal <= '0'; -- gibberish when '0' => -- some more gibberish end case; end if; end process; -- thanks GOD!!! Except for the readability issues, there's something deeper I'd like to understand; when there's an asynchronous set and reset I would definitely need to have both signals in the sensitivity list otherwise the pre-synthesis simulation would never trigger the process assignments. But why synthesis does not need them? Moreover the 'foobar' signal in the above snippet is truly not needed in the sensitivity list since an event should be scheduled for it to change at next delta cycle. Am I wrong? There's a possibility that my questions are badly formulated!! But I'm trying to figure out what the heck stroke the designer's mind when he wrote this... Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.59.205 with SMTP id m13mr16427986qah.7.1367574733359; Fri, 03 May 2013 02:52:13 -0700 (PDT) X-Received: by 10.50.33.175 with SMTP id s15mr3949701igi.8.1367574733112; Fri, 03 May 2013 02:52:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l3no623459qak.0!news-out.google.com!y6ni7qax.0!nntp.google.com!l3no623458qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 May 2013 02:52:12 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=120.96.54.15; posting-account=y5khOwoAAABtRPniMEcO_PSkC8XegbZf NNTP-Posting-Host: 120.96.54.15 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: help for usb3300 From: =?UTF-8?B?5p6X5a2f6bS7?= Injection-Date: Fri, 03 May 2013 09:52:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6511 Hey every one does someone had use VHDL code to control USB3300 IC to design Host and Device CHRIP who can help thx every one forgive me have poor English From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Design entry poll: which is your favorite editor? Date: Fri, 03 May 2013 12:43:32 +0200 Lines: 13 Message-ID: References: <3e41843f-f3a5-4f8f-8446-8e4d0573fbb8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net WZGTbg3fzOXLtSvTMlBFHAeUSlXmxw4HIzJ4PLDdj9OoLu3Oex Cancel-Lock: sha1:u3VcY3WyOEdCCSidrUvNaYxgHdc= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: <3e41843f-f3a5-4f8f-8446-8e4d0573fbb8@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6512 On 25/04/2013 10:22, Philippe wrote: > Hi everybody! > > There's a new poll on which design entry tool is popular for VHDL / > Verilog design entry. Results will be posted in a few weeks. Your > participation is greatly appreciated. > > http://www.vhdleditor.com/design-entry-poll-2013 I just hit twice my preferred editor... does it mean it gets counted 'twice'? How can you guarantee there are not repeated hit? From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.59.205 with SMTP id m13mr17793224qah.7.1367593843006; Fri, 03 May 2013 08:10:43 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.95.68 with SMTP id di4mr168682obb.2.1367593842951; Fri, 03 May 2013 08:10:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!l3no705951qak.0!news-out.google.com!y6ni0qax.0!nntp.google.com!m7no719466qam.0!postnews.google.com!r4g2000vbf.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 May 2013 08:10:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: r4g2000vbf.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.9.0.11735) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.28) Gecko/20120306 Firefox/3.6.28,gzip(gfe) Message-ID: <8ee339e6-60f7-48a1-8b32-e3c94554bdf6@r4g2000vbf.googlegroups.com> Subject: Re: clocked process and sensitivity list From: Thomas Stanka Injection-Date: Fri, 03 May 2013 15:10:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6513 On 3 Mai, 11:51, alb wrote: > here and when I synthesize it I get a warning about 'Feedback mux > created for signal...'. Any insight on the type of warning? [..] > process (clr, rst, foo, bar, foobar) > begin > =A0 if rst =3D '1' then > =A0 =A0 -- a bunch of assignments > =A0 elsif foo =3D '1' then > =A0 =A0 -- another bunch of assignments > =A0 elsif bar =3D '1' then > =A0 =A0 -- another bloody bunch of assignments > =A0 elsif (bar =3D '0') and (foo =3D '1') and (foobar =3D '1') then > =A0 =A0 -- another insane bunch of assignments > > =A0 elsif rising_edge(clk) then [..] First I assume the clr in sensitivity list should be clk. In fact the designer wrote a bunch of logic in the asynchronous (re)set path of the FF. I see no wrong on a formal point(depending on conntent of the "bunch of assignments" there could still be trouble), but I guess that usual synthesis tools accept only if resetcondition =3D true then reset/set elsif rising_edge(Clk) then modify end if Depending on content of the commented lines, you could have logic that is hard to implement in a technology that contains no FF with both set and reset. This would lead to creation of latch with a lot surrounding stuff to emulate FF with async set and reset. The warning is for me first hint that some latch or even worse is instantiated. I think you need to analyse for all signals in (re)set whats happing. A good example of what is sometimes desired on first glance, but not synthesiseable by any tool: if reset =3D '1' than FF <=3D Inputsignal; elsif .... best regards Thomas From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr17829059qab.5.1367594008500; Fri, 03 May 2013 08:13:28 -0700 (PDT) X-Received: by 10.182.66.198 with SMTP id h6mr172762obt.6.1367594008423; Fri, 03 May 2013 08:13:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l3no706560qak.0!news-out.google.com!y6ni0qax.0!nntp.google.com!m7no720150qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 May 2013 08:13:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Fri, 03 May 2013 15:13:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6514 First things first. A "feedback mux generated" message almost always indica= tes an issue with asynchronous resets.=20 In your code, if any of those reset conditions trigger, the elsif rising_ed= ge(clk) section does not execute (nor do the other reset sections execute).= Therefore the synthesis tool has to add a feedback mux for those registers= not reset by all reset conditions. The feedback mux is controlled by the r= eset conditions (oops, they're asynchronous!) so that the register does not= update on rising clock edges while any of the reset conditions is true. If you really want to have non-reset and reset registers in the same proces= s, then you should use an "if rising_edge(clk)" section first, with a matc= hing end if, and then a separate if statement (NOT elsif!) afterwards for E= ACH reset input condition.=20 Note that using multiple, partial asynchronous resets can cause strange pro= blems, if circuitry that is not reset is using outputs from other asynchron= ously reset circuitry, since those outputs can be reset at any time relativ= e to the clock. For this reason, asynchronous resets should generally only = be used for general initialization, and not for functional logic purposes. = Consider other ways to accomplish what the multiple asynchronous resets are= trying to do. As for the sensitivity list issues, generating an event is not the same as = triggering a process. A process has to be sensitive to the signal in order = for an event on that signal to cause the process to re-execute. Synthesis tools started out ignoring sensitivity lists, and have continued = to do so to this day, much to my chagrin. At least they warn you when they = find a sensitivity list problem that would cause a mismatch between the cod= e's simulated behavior and that of the resulting hardware. Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.160.65 with SMTP id m1mr20682464qax.2.1367632965614; Fri, 03 May 2013 19:02:45 -0700 (PDT) X-Received: by 10.49.30.168 with SMTP id t8mr1201121qeh.8.1367632965556; Fri, 03 May 2013 19:02:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m7no888038qam.0!news-out.google.com!y6ni0qax.0!nntp.google.com!m7no888037qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 May 2013 19:02:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.48.162.122; posting-account=O3Op7QoAAABrdZrjePqXZ3TGvEFy2Rcc NNTP-Posting-Host: 72.48.162.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL Model for a MIPS Processor From: jdavis7667@gmail.com Injection-Date: Sat, 04 May 2013 02:02:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6515 If anyone is able to do the following for me, it would be appreciated. Please comment the code, since I am trying to learn how to do code in VHDL for the future. 1.Develop a VHDL model for the MIPS processor. The model should simulate a 4-stage (Fetch, Decode, Execute, and Write-back) pipeline design. 2.The instruction memory should be modeled as a ROM, which can be part of the Fetch unit. 3.The data memory should be modeled as a read/write Random Access Memory, which can be included within the Write-back stage. 4.The register file should be modeled as a 3-port, 32 word, Random Access Memory, which can be included within the Decode unit. 5.It should be assumed that all RAW data hazards will be handled using data forwarding between the Execute state and the Decode stage. 6.Branch hazards should be resolved statically, i.e. assume that branch delay slots are filled either with a valid instruction or with nops. 7.Implement the following R format instructions: jr, add, sub, and, or, slt, lw, sw, sb 8.Implement the following I format instructions: beq, bne lbu, addi, subi 9.Implement the following J format instructions: jal, j and nop. From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Ralf Hildebrandt Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Mon, 06 May 2013 09:43:28 +0200 Lines: 58 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 3Wmeiuf0JSxNREkXXZofawCUub8NTof5dgcUISMSzWNKMXvw== Cancel-Lock: sha1:urlakSCZTETTAlRVxni9JRpBOW4= User-Agent: Mozilla/5.0 (Windows NT 5.2; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: Xref: mx05.eternal-september.org comp.lang.vhdl:6516 Hi alb! > process (clr, rst, foo, bar, foobar) ... > elsif (bar = '0') and (foo = '1') and (foobar = '1') then > -- another insane bunch of assignments > > elsif rising_edge(clk) then > case mysterious_signal is > when '1' => > foobar <= '0'; ... > end process; -- thanks GOD!!! > Moreover the 'foobar' signal in the above snippet is truly not needed in > the sensitivity list since an event should be scheduled for it to change > at next delta cycle. Am I wrong? foobar is needed in the sensitivity list: it is a Flipflop written in the rising_edge(clk) part and furthermore it is used as async. reset/set for the "another insane bunch of assignments"-branch. Therefore it may be that foobar is a signal, that triggers it's own reset. But I guess the designer of this code was aware of this and did pay attention to it. But let's come back to the "feedback mux"-problem: foobar is used as input for the reset/set conditions. Therefore if the "another insane bunch of assignments"-branch gets active, then the "rising_edge(clk)"-part should not be reached. For this purpose synthesis tools may infer a data multiplexer. Let's have a look at some synthesizable code: process(reset_n,set_n,clk) begin if (reset_n='0') then dout(1) <= '0'; dout(0) <= '0'; elsif (set_n='0') then dout(1) <= '1'; --dout(0) <= '1'; elsif rising_edge(clk) then dout(1) <= din(1); dout(0) <= din(0); end if; end process; As can be seen, dout(0) does not have a set-Input, but if set_n gets active, then dout(0) must not change. Therefore synthesis builds the following logic for the "rising_edge(clk)"-part : "if set_n='0' then dout(0)<=dout(0); else dout(0)<=din(0);" Please note that all this depends on your synthesis tool and the target library. Ralf From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Ralf Hildebrandt Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Mon, 06 May 2013 09:48:16 +0200 Lines: 24 Message-ID: References: <8ee339e6-60f7-48a1-8b32-e3c94554bdf6@r4g2000vbf.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net KyJnDhFxWVpGeYswqaUFgAi2cdoT18oB3+iiy8pyrl+mu1uA== Cancel-Lock: sha1:yUxR/4vIYUkIGZJg3ekqmdtsiZ0= User-Agent: Mozilla/5.0 (Windows NT 5.2; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: <8ee339e6-60f7-48a1-8b32-e3c94554bdf6@r4g2000vbf.googlegroups.com> Xref: mx05.eternal-september.org comp.lang.vhdl:6517 Hi Thomas! > A good example of what is sometimes desired on first glance, but not > synthesiseable by any tool: > > if reset = '1' than > FF <= Inputsignal; > elsif .... This synthesizes "well" to a Flipflop with reset and set input and some logic in front of that. set_input gets active, if reset='1' and Inputsignal='1' reset_input gets active, if reset='1' and Inputsignal='0' This works fine as long as Inputsignal does not change around the time when reset gets inactive. This is not code that is accepted as good code, may cause trouble with synthesis and ATPG tools and so on, but it is synthesizable and works. Ralf From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr35382693qab.5.1367847814934; Mon, 06 May 2013 06:43:34 -0700 (PDT) X-Received: by 10.49.106.231 with SMTP id gx7mr1565646qeb.6.1367847814774; Mon, 06 May 2013 06:43:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l3no2724608qak.0!news-out.google.com!y6ni7qax.0!nntp.google.com!l3no2724606qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 May 2013 06:43:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <71f58695-ed6e-44d4-8274-f9326bbdb430@googlegroups.com> Subject: Re: VHDL Model for a MIPS Processor From: Andy Injection-Date: Mon, 06 May 2013 13:43:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6518 Who is your professor, so I can forward it directly to him/her to save you the trouble? Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Tue, 07 May 2013 10:34:57 +0200 Lines: 69 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ujRfioShJ+x9+cBO0OMuXQgTf6WYPcQLcTkEJgKOmAakeHPeXQ Cancel-Lock: sha1:XkC9D8f3ZtB62f56VCA2tJkLMgs= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6519 Hi Andy, On 03/05/2013 17:13, Andy wrote: > First things first. A "feedback mux generated" message almost always > indicates an issue with asynchronous resets. I believe that 'almost' in your statement is referred to the variability of the various synthesis tools' implementation. > > In your code, if any of those reset conditions trigger, the elsif > rising_edge(clk) section does not execute (nor do the other reset > sections execute). Therefore the synthesis tool has to add a feedback > mux for those registers not reset by all reset conditions. The > feedback mux is controlled by the reset conditions (oops, they're > asynchronous!) so that the register does not update on rising clock > edges while any of the reset conditions is true. meaning that if a signal is not set for *all* sets and resets, the synthesis needs to 'remember' the state of the not-assigned signal to maintain its state. Sorry if I needed to reformulate it, but I guess is part of my 'learning process'! > > If you really want to have non-reset and reset registers in the same > process, then you should use an "if rising_edge(clk)" section first, > with a matching end if, and then a separate if statement (NOT elsif!) > afterwards for EACH reset input condition. > got your point. > Note that using multiple, partial asynchronous resets can cause > strange problems, if circuitry that is not reset is using outputs > from other asynchronously reset circuitry, since those outputs can be > reset at any time relative to the clock. For this reason, > asynchronous resets should generally only be used for general > initialization, and not for functional logic purposes. Consider other > ways to accomplish what the multiple asynchronous resets are trying > to do. This is the direction towards which I'm willing to go. The code (as I sarcastically described) has been put together with patches after patches up to a point where 'it works', but I've been asked to review the code and pin point any suspicious part which might cause problems. The fun part of it is the total absence of specs and a very primitive verification plan in place... but that's another issue. > > As for the sensitivity list issues, generating an event is not the > same as triggering a process. A process has to be sensitive to the > signal in order for an event on that signal to cause the process to > re-execute. Meaning that every signal the process depends on (i.e. resets/sets and clock) should be in the sensitivity list. Correct? > > Synthesis tools started out ignoring sensitivity lists, and have > continued to do so to this day, much to my chagrin. At least they > warn you when they find a sensitivity list problem that would cause a > mismatch between the code's simulated behavior and that of the > resulting hardware. > That is unfortunate and allows proliferating bad habits as well. I often see designers rushing to the synthesis phase (or even the FPGA programming) without paying too much of attention to pre-synth simulations. From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Tue, 07 May 2013 10:55:41 +0200 Lines: 78 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net E6ffa6pgFsMOWMHI4YlzowZGdPuIiCqTB1OsUT3HwSASs0MCkj Cancel-Lock: sha1:6B3rgpq1NyJeugj+Y0exO/iBfT8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6520 Hi Ralf, On 06/05/2013 09:43, Ralf Hildebrandt wrote: > .... >> elsif (bar = '0') and (foo = '1') and (foobar = '1') then >> -- another insane bunch of assignments >> >> elsif rising_edge(clk) then >> case mysterious_signal is >> when '1' => >> foobar <= '0'; > .... >> end process; -- thanks GOD!!! > >> Moreover the 'foobar' signal in the above snippet is truly not needed in >> the sensitivity list since an event should be scheduled for it to change >> at next delta cycle. Am I wrong? > > foobar is needed in the sensitivity list: it is a Flipflop written in > the rising_edge(clk) part and furthermore it is used as async. reset/set > for the "another insane bunch of assignments"-branch. Uhm, I guess you are right. Indeed I guess I was also right that 'foobar' is scheduled for a change in the next delta cycle, but if the process is not sensitive to it (with the sensitivity list) than it will not trigger. Is this a correct statement? > > Therefore it may be that foobar is a signal, that triggers it's own > reset. But I guess the designer of this code was aware of this and did > pay attention to it. Well, I've raised this question also. Indeed I did not even receive a strong opinion on why the resets/sets should really be asynchronous... > > But let's come back to the "feedback mux"-problem: foobar is used as > input for the reset/set conditions. Therefore if the "another insane > bunch of assignments"-branch gets active, then the > "rising_edge(clk)"-part should not be reached. For this purpose > synthesis tools may infer a data multiplexer. Let's have a look at some > synthesizable code: > > process(reset_n,set_n,clk) > begin > if (reset_n='0') then > dout(1) <= '0'; > dout(0) <= '0'; > elsif (set_n='0') then > dout(1) <= '1'; > --dout(0) <= '1'; > elsif rising_edge(clk) then > dout(1) <= din(1); > dout(0) <= din(0); > end if; > end process; > > As can be seen, dout(0) does not have a set-Input, but if set_n gets > active, then dout(0) must not change. Therefore synthesis builds the > following logic for the "rising_edge(clk)"-part : > "if set_n='0' then dout(0)<=dout(0); else dout(0)<=din(0);" that is crystal clear. In the even of a reset_n/set_n and clk happening at the same time both will have an event schedule for the same delta-cycle and to prevent the clk branch to trigger there should be some logic 'around' it, hence the feedback mux. > > > Please note that all this depends on your synthesis tool and the target > library. [OT] This is indeed very unfortunate. When we will have a common agreement by synthesis tool vendors on 'how a synthesis tool should behave'. Is there any standard they need to obey? I apologize but I got a bit 'infected' by the *nix world where platforms aim to comply to POSIX standards and code can be - to a large extent - portable. From newsfish@newsfish Tue Dec 29 16:42:53 2015 X-Received: by 10.224.165.130 with SMTP id i2mr3805191qay.2.1367933268616; Tue, 07 May 2013 06:27:48 -0700 (PDT) X-Received: by 10.182.85.162 with SMTP id i2mr18103obz.31.1367933268541; Tue, 07 May 2013 06:27:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l3no3140074qak.0!news-out.google.com!y6ni16024qax.0!nntp.google.com!m7no3181028qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 May 2013 06:27:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Tue, 07 May 2013 13:27:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6521 Alb, My use of "almost always" instead of "always" is just being cautious. I hav= e never had a case where it was not caused by a missing assignment in a pro= cess with a preceding asynchronous reset clause. But I have not written eve= ry possible combination of code yet, nor have I used every synthesis tool. Anytime a description has to remember a previously (in simulation time) sto= red value, there is some type of storage or storage modification involved i= n the implementation. This fundamental behavioral aspect of synthesis is at= the root of how/why latches, registers and clock enables are inferred, and= holds true whether you use signals or variables for your data. But that's = another subject... I feel your pain. The absence of specifications for what the code is actual= ly required to do (NOT how it has to or does do it) creates problems whenev= er the code must be changed. An effective testbench is not possible without= a good specification. Otherwise, the testbench can only test what you thin= k the code is supposed to do, which must be extracted from what the code ac= tually does. All causal signals must be in the sensitivity list. Non-causal signals shou= ld not be in the sensitivity list. In a combinatorial process, every signal= read is causal. In a clocked process, only the clock and if present, async= hronous reset(s) are causal. Andy From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Tue, 07 May 2013 14:27:40 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 8 May 2013 00:50:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="049fbe98628e386c080afd3816a6421e"; logging-data="29895"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+zSnqdRiJ2XfLhkK1t+3Z9" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:mqr/CvTgyetPuijw/vJqQlN4VyQ= Xref: mx05.eternal-september.org comp.lang.vhdl:6522 On 5/7/2013 9:27 AM, Andy wrote: > Alb, > > My use of "almost always" instead of "always" is just being cautious. I have never had a case where it was not caused by a missing assignment in a process with a preceding asynchronous reset clause. But I have not written every possible combination of code yet, nor have I used every synthesis tool. > > Anytime a description has to remember a previously (in simulation time) stored value, there is some type of storage or storage modification involved in the implementation. This fundamental behavioral aspect of synthesis is at the root of how/why latches, registers and clock enables are inferred, and holds true whether you use signals or variables for your data. But that's another subject... > > I feel your pain. The absence of specifications for what the code is actually required to do (NOT how it has to or does do it) creates problems whenever the code must be changed. An effective testbench is not possible without a good specification. Otherwise, the testbench can only test what you think the code is supposed to do, which must be extracted from what the code actually does. > > All causal signals must be in the sensitivity list. Non-causal signals should not be in the sensitivity list. In a combinatorial process, every signal read is causal. In a clocked process, only the clock and if present, asynchronous reset(s) are causal. I'm not following the issue here. I can't see why any extra logic would need to be asserted. The clocked process infers a register for each bit assigned in the edge triggered section. Are the async assigned bits *not* assigned in the edge triggered section? What am I missing? -- Rick From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Ralf Hildebrandt Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Wed, 08 May 2013 07:30:18 +0200 Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 5RVr1H/9JfsFYmNrKY0soQDjS0MUeu6a8UqCGG5+B3AntDcA== Cancel-Lock: sha1:NpTFGhecE9h22oe37MOqKH/Ihis= User-Agent: Mozilla/5.0 (Windows NT 5.2; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: Xref: mx05.eternal-september.org comp.lang.vhdl:6523 Hi alb! > Uhm, I guess you are right. Indeed I guess I was also right that > 'foobar' is scheduled for a change in the next delta cycle, but if the > process is not sensitive to it (with the sensitivity list) than it will > not trigger. Is this a correct statement? This is correct for simulation. Most synthesis tools don't care for the sensitivity list and "generate their depending on the code". >> Please note that all this depends on your synthesis tool and the target >> library. > > [OT] This is indeed very unfortunate. When we will have a common > agreement by synthesis tool vendors on 'how a synthesis tool should > behave'. It depends on the target library, because it has to include flipflops with async. set and reset. An for these flipflops in the synthesis model there must be a specification what to do is set and reset are activated together. (This will in most cases not happen, but the synthesis tool has to be aware of it.) And then it depends on the synthesis tool, how it solves the given problem. It is not some kind of "incompatibility" but more a problem of choosing one solution. Ralf From newsfish@newsfish Tue Dec 29 16:42:53 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: verification strategy with no specs Date: Wed, 08 May 2013 11:13:40 +0200 Lines: 29 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net KMz6DIp5fEpswlSyv9Ha7QhbJZMe+RzS500OYOfB+DkP/Mg/Ck Cancel-Lock: sha1:CF5sRCMuvNz9Q7KNHaMeP+oaA3g= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6524 Dear all, I've been appointed to review and verify a vhdl project of about 25k lines of code, *without* a specification document! There are various scattered notes/docs which describes somehow some details (*not all*), but there's no description of what the individual parts should do, even though there are only 4 types of FPGA in the system. It seems unbelievable to me that they got there without any spec but this is something I cannot change. My main question here is to understand if there exist strategies to face such type of situations and which one is more effective. I've started looking at the craziness at some implementation level (all code is practically uncommented!), but I'm at the level of firing a question to the designers for each line of code just to understand the reason behind! I know it sounds like a 'rescue' plan, but if anyone can point me to some - preferably documented - direction I would greatly appreciate. Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: verification strategy with no specs Date: Wed, 08 May 2013 09:50:47 -0700 Organization: Aioe.org NNTP Server Lines: 33 Message-ID: References: NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx05.eternal-september.org comp.lang.vhdl:6525 On 5/8/2013 2:13 AM, alb wrote: > Dear all, > > I've been appointed to review and verify a vhdl project of about 25k > lines of code, *without* a specification document! > > There are various scattered notes/docs which describes somehow some > details (*not all*), but there's no description of what the individual > parts should do, even though there are only 4 types of FPGA in the system. > > It seems unbelievable to me that they got there without any spec but > this is something I cannot change. My main question here is to > understand if there exist strategies to face such type of situations and > which one is more effective. > > I've started looking at the craziness at some implementation level (all > code is practically uncommented!), but I'm at the level of firing a > question to the designers for each line of code just to understand the > reason behind! > > I know it sounds like a 'rescue' plan, but if anyone can point me to > some - preferably documented - direction I would greatly appreciate. Here's what you do: Get an audience, scratch your head and rub your beard while looking pensive. Then declare with authority "It appears the product meets all stated specifications". Seriously, you'll need to write the specs before you can test it. It sounds like that's what you're doing anyway. I sympathize with you. It must be a huge undertaking if you actually expect to successfully complete it. JJS From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: verification strategy with no specs Date: Wed, 08 May 2013 22:42:27 +0200 Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net NOvjg0WrzNsSqqs1VIBhTQUNe3aYQDui1eug2y6bXdAp04Oyfl Cancel-Lock: sha1:t3GsoWntVaqx7TZnO0939CX+Q4k= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6526 Hi John, On 08/05/2013 18:50, John Speth wrote: [] >> I've started looking at the craziness at some implementation level (all >> code is practically uncommented!), but I'm at the level of firing a >> question to the designers for each line of code just to understand the >> reason behind! [] > Here's what you do: Get an audience, scratch your head and rub your > beard while looking pensive. Then declare with authority "It appears > the product meets all stated specifications". I wish I had the kind of beard to allow me such a statement! > > Seriously, you'll need to write the specs before you can test it. It > sounds like that's what you're doing anyway. I sympathize with you. It > must be a huge undertaking if you actually expect to successfully > complete it. So your suggestion is to sit down with the current designer(s) and try to get an higher level description of the various components in order to define interfaces, functionality and performances. Maybe I should size the effort and come with a proposal to the group in order to make it effective. I'm not sure how long will it take to write the specs from scratch and it certainly adds time to the already tight schedule (of course!). A very diffused sentiment in my environment comes from the false belief that every piece of hardware or software is buggy and in the end you can still live with it, so why bother with all these specs and verifications? They seem to see a 'verification plan' as another bureaucratic wall to tear down or to dodge quickly filling a couple of formal tests required by the funding agencies. Sometimes, I must say, I feel like tilting at windmills... From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr10325734qab.0.1368123417615; Thu, 09 May 2013 11:16:57 -0700 (PDT) X-Received: by 10.50.164.200 with SMTP id ys8mr3681450igb.1.1368123417395; Thu, 09 May 2013 11:16:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m7no4139101qam.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4139091qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 11:16:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL Standards Invitation and Status From: Jim Lewis Injection-Date: Thu, 09 May 2013 18:16:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6527 Hi, The VHDL Standards group is currently working on VHDL 1076-201X. Currently we are working on developing language change proposals. Check them out at: http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements Did we miss something? Could the proposals be better? Join us and help out. We have many tasks that can involve a wide range of skills. For starters we need users reviewing proposals and saying, yes if you add that I will use it. For more experienced VHDL users, we have proposals that need owners or helpers working on them. Proposals describe the problem, and identify a solution to it. After the proposals are done, we need highly knowledgeable VHDL community members to help convert the proposals into LRM text. Some may participate in all tasks, some may only participate in one or two. Lets face it while standards take time, they take less time with more participation. Best Regards, Jim Lewis IEEE P1076 VHDL Working Group Chair VHDL Training Expert, http://www.SynthWorks.com OSVVM, Chief Architect and Co-founder From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL Standards Invitation and Status Date: Thu, 09 May 2013 14:45:39 -0400 Organization: Alacron, Inc. Lines: 43 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 May 2013 18:42:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32442"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+7VTCwL2RCElTBFdkH3A3BQ9+2pK2utqc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:WrwxH5Sdtdueb6JZ4PNscXT1jfA= Xref: mx05.eternal-september.org comp.lang.vhdl:6528 Jim Lewis wrote: > Hi, > The VHDL Standards group is currently working on VHDL 1076-201X. > Currently we are working on developing language change proposals. > Check them out at: > http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements > > Did we miss something? Could the proposals be better? > > Join us and help out. We have many tasks that can involve > a wide range of skills. For starters we need users > reviewing proposals and saying, yes if you add that I > will use it. For more experienced VHDL users, we have > proposals that need owners or helpers working on them. > Proposals describe the problem, and identify a solution > to it. After the proposals are done, we need highly > knowledgeable VHDL community members to help convert > the proposals into LRM text. Some may participate in all > tasks, some may only participate in one or two. > > Lets face it while standards take time, they take less > time with more participation. > > Best Regards, > Jim Lewis > IEEE P1076 VHDL Working Group Chair > VHDL Training Expert, http://www.SynthWorks.com > OSVVM, Chief Architect and Co-founder I didn't look very deep into the existing requests, but I wonder if anyone considered bit reversal, for example allowing SLV's defined as (N downto 0) to be referenced in reverse order (0 to N). PRO: Reduces use of loops for intentional bit reversal CON: Could happen unintentionally when you thought you had a signal defined with "downto", when it was actually defined with "to" causing undesired bit reversal. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.10.6 with SMTP id n6mr10359729qan.4.1368125739803; Thu, 09 May 2013 11:55:39 -0700 (PDT) X-Received: by 10.49.1.197 with SMTP id 5mr1222540qeo.24.1368125739733; Thu, 09 May 2013 11:55:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l3no4102507qak.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4157957qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 11:55:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Thu, 09 May 2013 18:55:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6529 Rick, In the typical pattern for clocked logic with asynchronous reset: if reset then -- asynchronous reset/preset assignments to registers eslif rising_edge(clk) then -- synchronous assignments to registers end if; The elsif keeps the synchronous section from executing while reset is activ= e.=20 Thus, even if a register is not reset, the register does not keep updating = on clock edges while reset is active. In order to correctly implement that = behavior in the circuit, a feedback mux (clock enable) is used to retain th= e previously stored value in the register on every clock edge while reset i= s active. That feedback mux is extra logic, whether it is in the form of a = built-in clock enable or not. Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.10.6 with SMTP id n6mr10387245qan.4.1368126825379; Thu, 09 May 2013 12:13:45 -0700 (PDT) X-Received: by 10.50.109.228 with SMTP id hv4mr2142748igb.2.1368126825105; Thu, 09 May 2013 12:13:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m7no4166969qam.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4166968qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 12:13:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: verification strategy with no specs From: Andy Injection-Date: Thu, 09 May 2013 19:13:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6530 I agree, without a specification, you cannot verify function.=20 However, there are established design standards, regardless of function, th= at are prescribed to avoid certain, most often unintended, consequences and= hazards.=20 The design can be reviewed per those standards with little or no knowledge = of what the circuit is supposed to do.=20 Also, revising the circuit in response to the review findings will likely r= equire some knowledge of what it was supposed to do. I gather that more is known about what the system of FPGAs is supposed to d= o, than is known about what the individual FPGAs are supposed to do. If thi= s is the case, you may have to devise some tests to exercise the intended s= ystem behavior, while instrumenting the interfaces between FPGAs to gather = information on what is happening. Together with reviewing the code, one cou= ld presumably come up with a "spec" for what all of the interfaces of each = FPGA are supposed to do. And from that, a functional spec can be written fo= r each FPGA. Such a specification will be much tighter than necessary, since you only ha= ve visibility to what they actually did, not what they really needed to do.= Slight variations to what they did might still work, but it is impossible = to know if you don't know what 'works' means.=20 Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Generics, packages, and VHDL-2008 Date: Thu, 9 May 2013 12:16:09 -0700 Organization: Highland Technology, Inc. Lines: 16 Message-ID: <20130509121609.76f13be5@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4d736eb7372dfbec09ce671174b8b29e"; logging-data="7929"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/1TIDbDiEF4RyTNSm0Sz77" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:fMzUcs+ka3KNhYjjHYvVz416FfE= Xref: mx05.eternal-september.org comp.lang.vhdl:6531 Hey y'all -- If I have an entity with a generic, call it DATA_WIDTH. And I want that entity to use a package that has a DATA_WIDTH generic, in this specific case the package provides for a queue, implemented on shared variables, that the package would use. Is there any way to call out the instantiated package using the DATA_WIDTH that was passed into the entity? Thanks, Rob -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.42.141 with SMTP id s13mr10452799qae.3.1368128724442; Thu, 09 May 2013 12:45:24 -0700 (PDT) X-Received: by 10.49.35.111 with SMTP id g15mr1257677qej.15.1368128724375; Thu, 09 May 2013 12:45:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m7no4179706qam.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4179705qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 12:45:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL Standards Invitation and Status From: Andy Injection-Date: Thu, 09 May 2013 19:45:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6532 Rather than allow the reverse range to be used as an index range, I would p= refer a standard function(s), such as right_to_left() to return a bit-rever= sed vector (with reversed range to match.) Such a fix would have far less impact on tool vendors (and therefore adopti= on/support) than directly allowing reversed range access of vectors. I would also prefer such a function NOT be defined for types for which nume= ric interpretations (arithmetic, conversion between integer/real) are defin= ed in the same standard package. This would allow right_to_left(SLV), even = though numeric interpretation of SLV is applied by numeric_std_unsigned.=20 If a user wants to write their own overloaded function for unsigned, etc. s= o be it, but it should not be in the numeric_standard package. Especially s= o for fixed point types, which depend on index values for numeric interpret= ation. Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.42.141 with SMTP id s13mr10503969qae.3.1368130661726; Thu, 09 May 2013 13:17:41 -0700 (PDT) X-Received: by 10.182.84.227 with SMTP id c3mr153741obz.35.1368130661474; Thu, 09 May 2013 13:17:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!1.eu.reader.erje.net!1.us.reader.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!l3no4132692qak.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4188213qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 13:17:41 -0700 (PDT) In-Reply-To: <20130509121609.76f13be5@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <20130509121609.76f13be5@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <043bf5cd-fcf7-497f-8ac1-2e5370025398@googlegroups.com> Subject: Re: Generics, packages, and VHDL-2008 From: Andy Injection-Date: Thu, 09 May 2013 20:17:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6533 Rob, You can put a Package Instantiation Declaration in the declarative region of the entity, architecture, block, or several other declarative regions (not process). If the generic you wish to use is visible where the PID is, then that generic can be used in the PID's generic map aspect. You can include a use statement after the PID to access declarations within it. Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Generics, packages, and VHDL-2008 Date: Thu, 9 May 2013 13:35:04 -0700 Organization: Highland Technology, Inc. Lines: 35 Message-ID: <20130509133504.3c08bca5@rg.highlandtechnology.com> References: <20130509121609.76f13be5@rg.highlandtechnology.com> <043bf5cd-fcf7-497f-8ac1-2e5370025398@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4d736eb7372dfbec09ce671174b8b29e"; logging-data="445"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+VgMgfncK1rzQARYz3utVh" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:2YjFKrN5KAyXIQX/irQe3nPQ7lo= Xref: mx05.eternal-september.org comp.lang.vhdl:6534 On Thu, 9 May 2013 13:17:41 -0700 (PDT) Andy wrote: > Rob, > > You can put a Package Instantiation Declaration in the declarative region of the entity, architecture, block, or several other declarative regions (not process). > > If the generic you wish to use is visible where the PID is, then that generic can be used in the PID's generic map aspect. > > You can include a use statement after the PID to access declarations within it. > > Andy Thanks, Andy. I added the following line into the architecture declaration: package ldq is new data_queue generic map ( DATA_WIDTH => DATA_WIDTH ); But during compilation I got the message: Local instantiation of packages is not supported yet. Please contact Aldec Support to receive the latest status. Any clever workarounds, or am I subject to Aldec's implementational whims / my willingness to copy and paste code that should be nicely compartmentalized. Also, wasn't VHDL-2008 five years ago? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Generics, packages, and VHDL-2008 Date: Thu, 9 May 2013 13:59:59 -0700 Organization: Highland Technology, Inc. Lines: 51 Message-ID: <20130509135959.23419b40@rg.highlandtechnology.com> References: <20130509121609.76f13be5@rg.highlandtechnology.com> <043bf5cd-fcf7-497f-8ac1-2e5370025398@googlegroups.com> <20130509133504.3c08bca5@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4d736eb7372dfbec09ce671174b8b29e"; logging-data="445"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18KK+Pt89SBg2sD8RF0iHXr" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:XR//fnyEAO3O1R60+LQV8ip98cU= Xref: mx05.eternal-september.org comp.lang.vhdl:6535 On Thu, 9 May 2013 13:35:04 -0700 Rob Gaddi wrote: > On Thu, 9 May 2013 13:17:41 -0700 (PDT) > Andy wrote: > > > Rob, > > > > You can put a Package Instantiation Declaration in the declarative region of the entity, architecture, block, or several other declarative regions (not process). > > > > If the generic you wish to use is visible where the PID is, then that generic can be used in the PID's generic map aspect. > > > > You can include a use statement after the PID to access declarations within it. > > > > Andy > > Thanks, Andy. > > I added the following line into the architecture declaration: > > package ldq is new data_queue > generic map ( > DATA_WIDTH => DATA_WIDTH > ); > > But during compilation I got the message: > Local instantiation of packages is not supported yet. Please contact > Aldec Support to receive the latest status. > > Any clever workarounds, or am I subject to Aldec's implementational > whims / my willingness to copy and paste code that should be nicely > compartmentalized. > > Also, wasn't VHDL-2008 five years ago? > Found a workaround, at least for the special case of this issue. I was under the impression for some reason that you couldn't take a pointer to an incomplete type, and so I needed to make subtype t_element is std_logic_vector(DATA_WIDTH-1 downto 0); if I wanted to do dynamic structures with it. Turns out I'm just wrong, and I can use subtype t_element is std_logic_vector; and eliminate the need for DATA_WIDTH as a generic entirely. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.10.6 with SMTP id n6mr10800266qan.4.1368141155348; Thu, 09 May 2013 16:12:35 -0700 (PDT) X-Received: by 10.49.12.43 with SMTP id v11mr1311241qeb.38.1368141155243; Thu, 09 May 2013 16:12:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!1.us.reader.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!m7no4226597qam.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4226591qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 16:12:35 -0700 (PDT) In-Reply-To: <20130509133504.3c08bca5@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: <20130509121609.76f13be5@rg.highlandtechnology.com> <043bf5cd-fcf7-497f-8ac1-2e5370025398@googlegroups.com> <20130509133504.3c08bca5@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6dde988b-0f27-4133-a462-6639aa34562d@googlegroups.com> Subject: Re: Generics, packages, and VHDL-2008 From: Andy Injection-Date: Thu, 09 May 2013 23:12:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6536 I think the large number of changes in 2008, combined with poor user-knowledge of the new features, and therefore little input from customers clamoring for them, all contributed to the delay in implementing these changes. Regardless of whether you find/use a work-around, let them know you need this feature. It helps them prioritize their efforts. Also, if you know of a competitor that supports the feature you need already, let Aldec know that too. That often helps. Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Fri, 10 May 2013 00:48:31 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 10 May 2013 04:44:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="2f1d56cc32a64948e21bd8c19c258ccf"; logging-data="3911"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PkQA/bsKlWawAxX7NHxRv" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:WiGDiL5PLfMYUuxF+vG0o7WGiec= Xref: mx05.eternal-september.org comp.lang.vhdl:6537 On 5/9/2013 2:55 PM, Andy wrote: > Rick, > > In the typical pattern for clocked logic with asynchronous reset: > > if reset then > -- asynchronous reset/preset assignments to registers > eslif rising_edge(clk) then > -- synchronous assignments to registers > end if; > > The elsif keeps the synchronous section from executing while reset is active. > > Thus, even if a register is not reset, the register does not keep updating on clock edges while reset is active. In order to correctly implement that behavior in the circuit, a feedback mux (clock enable) is used to retain the previously stored value in the register on every clock edge while reset is active. That feedback mux is extra logic, whether it is in the form of a built-in clock enable or not. That's what I'm not clear on. I don't see why *anything* is needed to keep the register in reset as long as the reset is asserted. That's what the reset does, it holds the FF in reset. I've never seen a feedback mux added to a FF to implement a reset. Or are you referring to the internal logic of the FF? I looked and I couldn't find a transistor based model of a D FF with set and reset inputs. -- Rick From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.36.66 with SMTP id s2mr11434637qad.6.1368166690141; Thu, 09 May 2013 23:18:10 -0700 (PDT) X-Received: by 10.50.111.230 with SMTP id il6mr103735igb.14.1368166690048; Thu, 09 May 2013 23:18:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!Gin.tags.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!m7no4312226qam.0!news-out.google.com!y6ni20871qax.0!nntp.google.com!m7no4312221qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 May 2013 23:18:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.207.193.173; posting-account=cX_31woAAADM71oOddxndBkrviIYVa0i NNTP-Posting-Host: 117.207.193.173 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ed9795d-a695-4532-88c2-b5fb42f54f24@googlegroups.com> Subject: Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs From: cfp.hctlopen@gmail.com Injection-Date: Fri, 10 May 2013 06:18:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 11 Xref: mx05.eternal-september.org comp.lang.vhdl:6538 Dear Fellow Students and Researchers, I am sharing one useful announcement for those who are interested in writing and publishing research papers in the field of Reconfigurable Computing - FPGA, Embedded, VLSI, ASIC based designs. Please have a look to the following call for paper on Reconfigurable Computing. http://us6.forward-to-friend.com/forward/show?u=77fb907e5c2fb6cc2d4ffd642&id=214e464b5f http://www.hctl.org/STL/callforpaper.html Thank you! Best Regards, Raj Gaurav Mishra From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 10 May 2013 11:45:56 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130308 Thunderbird/17.0.4 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 Message-ID: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 6a4125f9.news.skynet.be X-Trace: 1368179156 news.skynet.be 3122 91.179.162.235:41712 X-Complaints-To: usenet-abuse@skynet.be Xref: mx05.eternal-september.org comp.lang.vhdl:6539 On 05/10/2013 06:48 AM, rickman wrote: > That's what I'm not clear on. I don't see why *anything* is needed > to keep the register in reset as long as the reset is asserted. > That's what the reset does, it holds the FF in reset. I've never > seen a feedback mux added to a FF to implement a reset. Or are you > referring to the internal logic of the FF? The feedback mux is needed if you *forget* to reset the register in the 'if reset' clause. In that case, HDL semantics dictate that the register should keep its previous value during reset, hence the feedback mux. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Fri, 10 May 2013 09:33:05 -0400 Organization: Alacron, Inc. Lines: 26 Message-ID: References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 10 May 2013 13:30:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="17951"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RdXBJNVejdfqv2Gu2Y3UhZapyNarHCXU=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Cancel-Lock: sha1:b9Y+7H3pmb/mrE9hee4M2crJfAg= Xref: mx05.eternal-september.org comp.lang.vhdl:6540 Jan Decaluwe wrote: > On 05/10/2013 06:48 AM, rickman wrote: > >> That's what I'm not clear on. I don't see why *anything* is needed >> to keep the register in reset as long as the reset is asserted. >> That's what the reset does, it holds the FF in reset. I've never >> seen a feedback mux added to a FF to implement a reset. Or are you >> referring to the internal logic of the FF? > > The feedback mux is needed if you *forget* to reset the register > in the 'if reset' clause. In that case, HDL semantics dictate > that the register should keep its previous value during reset, > hence the feedback mux. > > Jan > I've found that Symplify is very good at warning you about forgetting the reset terms in this case. You get a warning about feedback mux, followed by "Did you forget..." I wish XST did that instead of all the useless warnings it gives... -- Gabor From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: clocked process and sensitivity list Date: Fri, 10 May 2013 11:04:16 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 10 May 2013 15:00:38 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="bbb779971806bc669cc687df78f34f97"; logging-data="12674"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/abkfU+YW0TwqyBUIzO7N8" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Cancel-Lock: sha1:NfV/PzPgXHJDbgUYEugSV1K4aAU= Xref: mx05.eternal-september.org comp.lang.vhdl:6541 On 5/10/2013 5:45 AM, Jan Decaluwe wrote: > On 05/10/2013 06:48 AM, rickman wrote: > >> That's what I'm not clear on. I don't see why *anything* is needed >> to keep the register in reset as long as the reset is asserted. >> That's what the reset does, it holds the FF in reset. I've never >> seen a feedback mux added to a FF to implement a reset. Or are you >> referring to the internal logic of the FF? > > The feedback mux is needed if you *forget* to reset the register > in the 'if reset' clause. In that case, HDL semantics dictate > that the register should keep its previous value during reset, > hence the feedback mux. I'm not sure that is really needed. If the reset clause is missing an assignment doesn't it become a clock enable? When the reset is asserted the clock does not work and the output is held. Still no need for a feedback mux... -- Rick From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.59.205 with SMTP id m13mr18811399qah.7.1368449608757; Mon, 13 May 2013 05:53:28 -0700 (PDT) X-Received: by 10.49.95.40 with SMTP id dh8mr1958185qeb.19.1368449608624; Mon, 13 May 2013 05:53:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!m7no5316964qam.0!news-out.google.com!y6ni29564qax.0!nntp.google.com!m7no5316962qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 May 2013 05:53:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.35 References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Mon, 13 May 2013 12:53:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6542 Rick, We are in complete agreement, but saying the same thing in different ways. The feedback mux IS A CLOCK ENABLE. If the target architecture supports built-in clock enables on registers, then one will be used to implement the feedback mux. It may be that at the time during processing when the need for a feedback mux is determined, it may not be known whether the target architecture supports built-in clock enables, thus the message indicates a feedback mux. Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.36.66 with SMTP id s2mr20232035qad.6.1368500864690; Mon, 13 May 2013 20:07:44 -0700 (PDT) X-Received: by 10.50.56.51 with SMTP id x19mr84393igp.0.1368500864596; Mon, 13 May 2013 20:07:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!l3no5620468qak.0!news-out.google.com!y6ni29564qax.0!nntp.google.com!m7no5698244qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 May 2013 20:07:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=113.22.164.201; posting-account=fwdJ2goAAABs6ka1a5bR9hS80zSot9Cc NNTP-Posting-Host: 113.22.164.201 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0801ce0c-6761-4568-ab67-0fc90dc78ceb@googlegroups.com> Subject: Re: i need solutions of chapter 5 wireless communication by Andrea Goldsmith From: mrdungdoan@gmail.com Injection-Date: Tue, 14 May 2013 03:07:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6543 On Tuesday, April 20, 2010 12:16:26 PM UTC-7, tahir wrote: > i need solutions of chapter 5 wireless communication by Andrea > Goldsmith.. plz if any one can help me in this regard... reply here or > to my mail address Yes. So do I. Can you share them to me? Thank you so much. My email : Mrdungdoan@gmail.com From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.36.66 with SMTP id s2mr21797904qad.6.1368563427420; Tue, 14 May 2013 13:30:27 -0700 (PDT) X-Received: by 10.49.106.231 with SMTP id gx7mr2597345qeb.6.1368563427390; Tue, 14 May 2013 13:30:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l3no6298879qak.0!news-out.google.com!y6ni43361qax.0!nntp.google.com!m7no6380163qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 May 2013 13:30:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=63.239.65.11; posting-account=Dt5gPQoAAACE2KOpBdUJHEyRkfN3g9rg NNTP-Posting-Host: 63.239.65.11 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> Subject: Counting number of asserted register bits in VHDL From: bucketonuts@gmail.com Injection-Date: Tue, 14 May 2013 20:30:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3771 Xref: mx05.eternal-september.org comp.lang.vhdl:6544 Hello, I have a status register of width, R_SIZE. This is a generic so the register width may be different depending on the application. The R_SIZE is limited to values, 4, 8 and 16. Each bit in the register is set by different module as an indication of that module's done status. These status bits are asserted for only one clock and may be asserted again as each module may run its application multiple times on different data. I need to count the number of bits set in the status register on each clock and accumulate a total to match a predetermined "max" value. I thought I'd use the VHDL 'generate' statement to compile RTL based on R_SIZE as follows. =================== start RTL ===================== architecture behave of b is component modx port( mod_cmplt : out std_logic ); end component modx; signal mod_cmplt : std_logic_vector(15 downto 0); signal cmplt_cnt : integer range 0 to 512; signal next_cmplt_cnt : integer range 0 to 512; begin mod_cmplt(15 downto R_SIZE) <= (others => '0'); g1: for i in 0 to R_SIZE-1 generate u_modx : modx port map( mod_cmplt => mod_cmplt(i) ); end generate; process (mod_cmplt, cmplt_cnt) begin next_cmplt_cnt <= cmplt_cnt; gen4: if R_SIZE = 4 generate next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + mod_cmplt(3) + cmplt_cnt; end generate; gen8: if R_SIZE = 8 generate next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) + mod_cmplt(6) + mod_cmplt(7) + cmplt_cnt; end generate; gen16:if R_SIZE = 16 generate next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) + mod_cmplt(6) + mod_cmplt(7) + mod_cmplt(8) + mod_cmplt(9) + mod_cmplt(10) + mod_cmplt(11) + mod_cmplt(12) + mod_cmplt(13) + mod_cmplt(14) + mod_cmplt(15) + cmplt_cnt; end generate end process; process (reset, clk) begin if (reset = '1') then cmplt_cnt <= 0; elsif (clk'event and clk='1') cmplt_cnt <= next_cmplt_cnt; end if; end process end behave; ================================ end RTL ================= The first error I get is a syntax error: Error-[IEEEVHDLSYNTAXERR] Syntax error gen4: if R_SIZE = 4 generate ^ Syntax error detected during VHDL parsing. I don't know what to do about this. Is there a better way to code what I want the system to do? Thank you. From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Counting number of asserted register bits in VHDL Date: Tue, 14 May 2013 16:52:31 -0400 Organization: Alacron, Inc. Lines: 94 Message-ID: References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 May 2013 20:48:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="20955"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18R0TxNvrXzJrNuAp2n2von4XS7tl+0qGM=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> Cancel-Lock: sha1:fKXA4oWh+6lKxXUg5z9MvkCNG+Q= Xref: mx05.eternal-september.org comp.lang.vhdl:6545 bucketonuts@gmail.com wrote: > Hello, > > I have a status register of width, R_SIZE. This is a generic so the register width may be different depending on the application. The R_SIZE is limited to values, 4, 8 and 16. > > Each bit in the register is set by different module as an indication of that module's done status. These status bits are asserted for only one clock and may be asserted again as each module may run its application multiple times on different data. > > I need to count the number of bits set in the status register on each clock and accumulate a total to match a predetermined "max" value. > > I thought I'd use the VHDL 'generate' statement to compile RTL based on R_SIZE as follows. > > =================== start RTL ===================== > architecture behave of b is > > component modx port( > mod_cmplt : out std_logic > ); > end component modx; > > signal mod_cmplt : std_logic_vector(15 downto 0); > signal cmplt_cnt : integer range 0 to 512; > signal next_cmplt_cnt : integer range 0 to 512; > > begin > mod_cmplt(15 downto R_SIZE) <= (others => '0'); > > g1: for i in 0 to R_SIZE-1 generate > u_modx : modx port map( > mod_cmplt => mod_cmplt(i) > ); > end generate; > > process (mod_cmplt, cmplt_cnt) > begin > next_cmplt_cnt <= cmplt_cnt; > > gen4: if R_SIZE = 4 generate > next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + > mod_cmplt(3) + cmplt_cnt; > end generate; > > gen8: if R_SIZE = 8 generate > next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + > mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) + > mod_cmplt(6) + mod_cmplt(7) + cmplt_cnt; > end generate; > > gen16:if R_SIZE = 16 generate > next_cmplt_cnt <= mod_cmplt(0) + mod_cmplt(1) + mod_cmplt(2) + > mod_cmplt(3) + mod_cmplt(4) + mod_cmplt(5) + > mod_cmplt(6) + mod_cmplt(7) + mod_cmplt(8) + > mod_cmplt(9) + mod_cmplt(10) + mod_cmplt(11) + > mod_cmplt(12) + mod_cmplt(13) + mod_cmplt(14) + > mod_cmplt(15) + cmplt_cnt; > end generate > > end process; > > process (reset, clk) > begin > if (reset = '1') then > cmplt_cnt <= 0; > elsif (clk'event and clk='1') > cmplt_cnt <= next_cmplt_cnt; > end if; > end process > > end behave; > ================================ end RTL ================= > > The first error I get is a syntax error: > > Error-[IEEEVHDLSYNTAXERR] Syntax error > > gen4: if R_SIZE = 4 generate > ^ > Syntax error detected during VHDL parsing. > > I don't know what to do about this. Is there a better way to code what I want the system to do? > > Thank you. > I'm not up enough on VHDL to tell you if it's even valid to have generate statements within a process, but the point is that you don't need them here. Since mod_cmplt is always the same size regardless of the value of R_SIZE, you can just use if ... elsif ... else without the generates. Or even use a case statement. Basically there's nothing in your equations that requires generate statements. And note that because R_SIZE is known at compile time it won't create extra logic. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.10.6 with SMTP id n6mr22077522qan.4.1368572701063; Tue, 14 May 2013 16:05:01 -0700 (PDT) X-Received: by 10.182.96.131 with SMTP id ds3mr38976obb.40.1368572700848; Tue, 14 May 2013 16:05:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!news.franciliens.net!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m7no6513132qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no6513125qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 May 2013 16:05:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: kevin.neilson@xilinx.com Injection-Date: Tue, 14 May 2013 23:05:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1519 Xref: mx05.eternal-september.org comp.lang.vhdl:6546 Yeah, it seems like something much simpler like this would work fine: process (reset, clk) variable sum : integer := 0; begin if (reset = '1') then cmplt_cnt <= 0; elsif (clk'event and clk='1') for k in 0 to R_SIZE - 1 loop sum := sum + mod_cmplt(k); end loop; cmplt_cnt <= cmplt_cnt + sum; end if; end process; From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.59.205 with SMTP id m13mr23211749qah.7.1368617977923; Wed, 15 May 2013 04:39:37 -0700 (PDT) X-Received: by 10.49.12.43 with SMTP id v11mr1376qeb.38.1368617976902; Wed, 15 May 2013 04:39:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!m7no7403150qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7403144qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 04:39:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=63.239.65.11; posting-account=Dt5gPQoAAACE2KOpBdUJHEyRkfN3g9rg NNTP-Posting-Host: 63.239.65.11 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e20c721-d2e8-4330-b851-24e3b9e0e7e6@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: bucketonuts@gmail.com Injection-Date: Wed, 15 May 2013 11:39:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 31 Xref: mx05.eternal-september.org comp.lang.vhdl:6547 On Tuesday, May 14, 2013 4:52:31 PM UTC-4, Gabor Sz wrote: >=20 >=20 >=20 > I'm not up enough on VHDL to tell you if it's even valid >=20 > to have generate statements within a process, but the point is >=20 > that you don't need them here. Since mod_cmplt is always the >=20 > same size regardless of the value of R_SIZE, you can just use >=20 > if ... elsif ... else without the generates. Or even use a case >=20 > statement. Basically there's nothing in your equations that >=20 > requires generate statements. And note that because R_SIZE is >=20 > known at compile time it won't create extra logic. >=20 >=20 >=20 > --=20 >=20 > Gabor Thank you. I thought about this but didn't know what would happen to the ad= der if only 8 modx modules were instantiated. Even though the if-else branc= h for 16 modx's wouldn't be reached, the adder would still have inputs for = modx[8]to modx[15] which would not be driven. Also, you are correct, generate statements may not be located in a process. Thanks again. From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.10.6 with SMTP id n6mr23235683qan.4.1368618542565; Wed, 15 May 2013 04:49:02 -0700 (PDT) X-Received: by 10.49.107.226 with SMTP id hf2mr2713809qeb.25.1368618542552; Wed, 15 May 2013 04:49:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!l3no7319772qak.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7410614qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 04:49:02 -0700 (PDT) In-Reply-To: <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=63.239.65.11; posting-account=Dt5gPQoAAACE2KOpBdUJHEyRkfN3g9rg NNTP-Posting-Host: 63.239.65.11 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Counting number of asserted register bits in VHDL From: bucketonuts@gmail.com Injection-Date: Wed, 15 May 2013 11:49:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6548 On Tuesday, May 14, 2013 7:05:00 PM UTC-4, kevin....@xilinx.com wrote: > Yeah, it seems like something much simpler like this would work fine: > > > > process (reset, clk) > > variable sum : integer := 0; > > begin > > if (reset = '1') then > > cmplt_cnt <= 0; > > elsif (clk'event and clk='1') > > for k in 0 to R_SIZE - 1 loop > > sum := sum + mod_cmplt(k); > > end loop; > > cmplt_cnt <= cmplt_cnt + sum; > > end if; > > end process; Thank you - this looks interesting. So sum gets evaluated at clk'event in time for cmplt_cnt to be updated with the new value of sum? From newsfish@newsfish Tue Dec 29 16:42:54 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Counting number of asserted register bits in VHDL Date: Wed, 15 May 2013 10:21:34 -0400 Organization: Alacron, Inc. Lines: 47 Message-ID: References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8e20c721-d2e8-4330-b851-24e3b9e0e7e6@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 May 2013 14:18:01 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="12726"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cRtNwHC5umbgOL7a3mWALTWq23zZ7TOw=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <8e20c721-d2e8-4330-b851-24e3b9e0e7e6@googlegroups.com> Cancel-Lock: sha1:TVY/fyxigQok9r3FKAjFWx/7Kq4= Xref: mx05.eternal-september.org comp.lang.vhdl:6549 bucketonuts@gmail.com wrote: > On Tuesday, May 14, 2013 4:52:31 PM UTC-4, Gabor Sz wrote: >> >> >> I'm not up enough on VHDL to tell you if it's even valid >> >> to have generate statements within a process, but the point is >> >> that you don't need them here. Since mod_cmplt is always the >> >> same size regardless of the value of R_SIZE, you can just use >> >> if ... elsif ... else without the generates. Or even use a case >> >> statement. Basically there's nothing in your equations that >> >> requires generate statements. And note that because R_SIZE is >> >> known at compile time it won't create extra logic. >> >> >> >> -- >> >> Gabor > > Thank you. I thought about this but didn't know what would happen to the adder > if only 8 modx modules were instantiated. Even though the if-else branch for > 16 modx's wouldn't be reached, the adder would still have inputs for modx[8] > to modx[15] which would not be driven. > Also, you are correct, generate statements may not be located in a process. > Thanks again. Actually the adder would not have extra undriven inputs _because_ those branches are not reached, and the synthesizer only implements code that is reached. For the cases where you don't have the maximum R_SIZE, there would be some unused (and undriven) signals, but these would generally get trimmed at or after physical synthesis. If you used the other example with a loop, you could size the mod_cmplt vector using R_SIZE and then there would be no unused signals. If you like to avoid warnings during synthesis and build, then that is a cleaner approach. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr23514597qab.5.1368629402482; Wed, 15 May 2013 07:50:02 -0700 (PDT) X-Received: by 10.49.71.135 with SMTP id v7mr2784118qeu.22.1368629402454; Wed, 15 May 2013 07:50:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!m7no7606812qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7606806qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 07:50:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> Subject: Asynchronous With Select and When Else Statements From: Cory Shol Injection-Date: Wed, 15 May 2013 14:50:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 64 Xref: mx05.eternal-september.org comp.lang.vhdl:6550 Hi everyone, I am coding up a project to route and control Gigabit ethernet. Basically the FPGA receives MDIO communication from Processor 1 or Processor 2( Both masters, only one can be master at a time). The logic decides based on a priority and a keep alive signal which master controls the MDIO bus. Now I have the handling for who is master of the system and keep alive signal etc... My question lies with the Asynchronous With Select and When Else Statements: my code looks something like below: (Keep in mind MDIO communication is BIDIRECTIONAL, I have a pull up on the mdio_proc1 pin) The question is about the Nested When else in the the With select statement: with arb_select_proc1_iso & smi_control select mdio_proc1 <= ('Z' when (direction = '0' or mdio_device_data = '1') else '0') when "001", arb_proc1_out_iso when "100", arb_proc1_out_iso when "101", arb_proc1_out_iso when "110", arb_proc1_out_iso when "111", 'Z' when others; with arb_select_proc2_iso & smi_control select mdio_proc2 <= ('Z' when (direction = '0' or mdio_device_data = '1') else '0') when "010", arb_proc2_out_iso when "100", arb_proc2_out_iso when "101", arb_proc2_out_iso when "110", arb_proc2_out_iso when "111", 'Z' when others; This comes up with the error in Xilinx: ERROR:HDLParsers:164 - "C:/workspace/head/Smm_xilinx_tb/smm/smm.vhd" Line 325. parse error, unexpected WHEN, expecting COMMA or CLOSEPAR ERROR:HDLParsers:164 - "C:/workspace/head/Smm_xilinx_tb/smm/smm.vhd" Line 333. parse error, unexpected WHEN, expecting COMMA or CLOSEPAR So I try this: mdio_bus <= 'Z' when (direction = '0' or mdio_device_data = '1') else '0'; with arb_select_proc1_iso & smi_control select mdio_proc1 <= mdio_bus when "001", arb_proc1_out_iso when "100", arb_proc1_out_iso when "101", arb_proc1_out_iso when "110", arb_proc1_out_iso when "111", 'Z' when others; with arb_select_proc2_iso & smi_control select mdio_mezz <= mdio_bus when "010", arb_proc2_out_iso when "100", arb_proc2_out_iso when "101", arb_proc2_out_iso when "110", arb_proc2_out_iso when "111", 'Z' when others; and I get the warning: WARNING:Xst:2042 - Unit smm: 2 internal tristates are replaced by logic (pull-up yes): mdio_bus, mdio_proc_data. Are there any other ways to do what I want to do?? From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.165.130 with SMTP id i2mr23635548qay.2.1368632836513; Wed, 15 May 2013 08:47:16 -0700 (PDT) X-Received: by 10.49.81.162 with SMTP id b2mr119129qey.10.1368632836397; Wed, 15 May 2013 08:47:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m7no7672946qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7672943qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 08:47:16 -0700 (PDT) In-Reply-To: <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: Andy Injection-Date: Wed, 15 May 2013 15:47:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3006 Xref: mx05.eternal-september.org comp.lang.vhdl:6551 A nice little problem to illustrate VHDL RTL... I don't know if it makes a real difference, but constraining the range of s= um is seldom a bad idea: variable sum : natural range 0 to mod_cmplt'length; Don't forget to initialize sum to 0 before the loop, on every clock cycle. = Variable declaration initializations in processes only happen once, at time= 0. Also, syntactic tricks are required to add a std_logic bit to an integer an= d get an integer result: sum :=3D sum + to_integer(unsigned(0 =3D> mod_cmplt(k))); Or simply: if mod_complt(k) =3D '1' then sum :=3D sum + 1; end if; Since cmplt_cnt is an integer, you need to make sure it never overflows. Pr= esumably it would be set to zero once it reaches some limit where something= happens. If you want cmplt_cnt to roll over, either use mod (modulo operat= or) or make cmplt_cnt an unsigned instead of integer type (sum can still be= integer, and it cannot overflow). More syntactic sugar: when iterating in a loop over the range of a vector, = use vector'range as the loop index range: for k in mod_cmplt'range loop Finally, if you want to pipeline the sum and cmplt_cnt updates, just update= cnt_cmplt before sum is initialized: pipelined: process (rst, clk) is variable sum : natural range 0 to mod_cmplt'length; begin if rst =3D '1' then cmplt_cnt <=3D 0; sum :=3D 0; -- used as register, so reset it elsif rising_edge(clk) then cmplt_cnt <=3D cmplt_cnt + sum; -- sum is register here sum :=3D 0; -- sum is combinatorial hereafter for k in mod_complt'range loop sum :=3D sum + to_integer(unsigned(0 =3D> mod_cmplt(k))); end loop; end if; end process pipelined; Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.130.195 with SMTP id u3mr23705110qas.1.1368634265147; Wed, 15 May 2013 09:11:05 -0700 (PDT) X-Received: by 10.49.41.1 with SMTP id b1mr134076qel.18.1368634265119; Wed, 15 May 2013 09:11:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!m7no7696327qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7696323qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 09:11:05 -0700 (PDT) In-Reply-To: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9a679ddd-4fc2-4d75-891c-50312af35d25@googlegroups.com> Subject: Re: Asynchronous With Select and When Else Statements From: Andy Injection-Date: Wed, 15 May 2013 16:11:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 13 Xref: mx05.eternal-september.org comp.lang.vhdl:6552 You need to break up the assignments into a separate with-select assignment= for the data, followed by a when-else assignment for the tri-state buffer. You might try to see if XST has a "tri-state push" option, but I doubt it w= ill work for your code anyway. BTW, the statements you are using are not called "asynchronous" (a function= of the logic expressed), but are called "concurrent" (a function of when t= he statement is executed). Concurrent assignment statements can infer synch= ronous registers, as in the following: q <=3D d when rising_edge(clk); Andy From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.42.141 with SMTP id s13mr23871710qae.3.1368640694911; Wed, 15 May 2013 10:58:14 -0700 (PDT) X-Received: by 10.49.130.170 with SMTP id of10mr193748qeb.37.1368640694894; Wed, 15 May 2013 10:58:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!m7no7810053qam.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7810051qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 10:58:14 -0700 (PDT) In-Reply-To: <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=63.239.65.11; posting-account=Dt5gPQoAAACE2KOpBdUJHEyRkfN3g9rg NNTP-Posting-Host: 63.239.65.11 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <721bfac3-2336-4540-9823-d0434ce7b9d3@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: bucketonuts@gmail.com Injection-Date: Wed, 15 May 2013 17:58:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 97 Xref: mx05.eternal-september.org comp.lang.vhdl:6553 On Wednesday, May 15, 2013 11:47:16 AM UTC-4, Andy wrote: > A nice little problem to illustrate VHDL RTL... >=20 >=20 >=20 > I don't know if it makes a real difference, but constraining the range of= sum is seldom a bad idea: >=20 >=20 >=20 > variable sum : natural range 0 to mod_cmplt'length; >=20 >=20 >=20 > Don't forget to initialize sum to 0 before the loop, on every clock cycle= . Variable declaration initializations in processes only happen once, at ti= me 0. >=20 >=20 >=20 > Also, syntactic tricks are required to add a std_logic bit to an integer = and get an integer result: >=20 >=20 >=20 > sum :=3D sum + to_integer(unsigned(0 =3D> mod_cmplt(k))); >=20 >=20 >=20 > Or simply: >=20 >=20 >=20 > if mod_complt(k) =3D '1' then >=20 > sum :=3D sum + 1; >=20 > end if; >=20 >=20 >=20 > Since cmplt_cnt is an integer, you need to make sure it never overflows. = Presumably it would be set to zero once it reaches some limit where somethi= ng happens. If you want cmplt_cnt to roll over, either use mod (modulo oper= ator) or make cmplt_cnt an unsigned instead of integer type (sum can still = be integer, and it cannot overflow). >=20 >=20 >=20 > More syntactic sugar: when iterating in a loop over the range of a vector= , use vector'range as the loop index range: >=20 >=20 >=20 > for k in mod_cmplt'range loop >=20 >=20 >=20 > Finally, if you want to pipeline the sum and cmplt_cnt updates, just upda= te cnt_cmplt before sum is initialized: >=20 >=20 >=20 > pipelined: process (rst, clk) is >=20 > variable sum : natural range 0 to mod_cmplt'length; >=20 > begin >=20 > if rst =3D '1' then >=20 > cmplt_cnt <=3D 0; >=20 > sum :=3D 0; -- used as register, so reset it >=20 > elsif rising_edge(clk) then >=20 > cmplt_cnt <=3D cmplt_cnt + sum; -- sum is register here >=20 > sum :=3D 0; -- sum is combinatorial hereafter >=20 > for k in mod_complt'range loop >=20 > sum :=3D sum + to_integer(unsigned(0 =3D> mod_cmplt(k))); >=20 > end loop; >=20 > end if; >=20 > end process pipelined; >=20 >=20 >=20 > Andy Thanks, Andy. I'm new to VHDL. It took me most of the morning to figure out= how to add a std_logic bit to an integer (to_integer). You make some very = good points in the rest of your post as well. From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr23991006qab.0.1368645784962; Wed, 15 May 2013 12:23:04 -0700 (PDT) X-Received: by 10.49.6.201 with SMTP id d9mr2965197qea.12.1368645784922; Wed, 15 May 2013 12:23:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!l3no7809510qak.0!news-out.google.com!y6ni43806qax.0!nntp.google.com!m7no7903572qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 May 2013 12:23:04 -0700 (PDT) In-Reply-To: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> Subject: Re: Asynchronous With Select and When Else Statements From: Cory Shol Injection-Date: Wed, 15 May 2013 19:23:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 128 Xref: mx05.eternal-september.org comp.lang.vhdl:6554 On Wednesday, May 15, 2013 9:50:02 AM UTC-5, Cory Shol wrote: > Hi everyone, > > > > I am coding up a project to route and control Gigabit ethernet. > > > > Basically the FPGA receives MDIO communication from Processor 1 or Processor 2( Both masters, only one can be master at a time). > > > > The logic decides based on a priority and a keep alive signal which master controls the MDIO bus. > > > > Now I have the handling for who is master of the system and keep alive signal etc... > > > > My question lies with the Asynchronous With Select and When Else Statements: > > > > my code looks something like below: (Keep in mind MDIO communication is BIDIRECTIONAL, I have a pull up on the mdio_proc1 pin) > > > > The question is about the Nested When else in the the With select statement: > > > > with arb_select_proc1_iso & smi_control select > > mdio_proc1 <= ('Z' when (direction = '0' or mdio_device_data = '1') else '0') when "001", > > arb_proc1_out_iso when "100", > > arb_proc1_out_iso when "101", > > arb_proc1_out_iso when "110", > > arb_proc1_out_iso when "111", > > 'Z' when others; > > > > with arb_select_proc2_iso & smi_control select > > mdio_proc2 <= ('Z' when (direction = '0' or mdio_device_data = '1') else '0') when "010", > > arb_proc2_out_iso when "100", > > arb_proc2_out_iso when "101", > > arb_proc2_out_iso when "110", > > arb_proc2_out_iso when "111", > > 'Z' when others; > > > > This comes up with the error in Xilinx: > > ERROR:HDLParsers:164 - "C:/workspace/head/Smm_xilinx_tb/smm/smm.vhd" Line 325. parse error, unexpected WHEN, expecting COMMA or CLOSEPAR > > ERROR:HDLParsers:164 - "C:/workspace/head/Smm_xilinx_tb/smm/smm.vhd" Line 333. parse error, unexpected WHEN, expecting COMMA or CLOSEPAR > > > > So I try this: > > > > mdio_bus <= 'Z' when (direction = '0' or mdio_device_data = '1') else '0'; > > > > with arb_select_proc1_iso & smi_control select > > mdio_proc1 <= mdio_bus when "001", > > arb_proc1_out_iso when "100", > > arb_proc1_out_iso when "101", > > arb_proc1_out_iso when "110", > > arb_proc1_out_iso when "111", > > 'Z' when others; > > > > with arb_select_proc2_iso & smi_control select > > mdio_mezz <= mdio_bus when "010", > > arb_proc2_out_iso when "100", > > arb_proc2_out_iso when "101", > > arb_proc2_out_iso when "110", > > arb_proc2_out_iso when "111", > > 'Z' when others; > > > > and I get the warning: > > > > WARNING:Xst:2042 - Unit smm: 2 internal tristates are replaced by logic (pull-up yes): mdio_bus, mdio_proc_data. > > > > > > Are there any other ways to do what I want to do?? Yeah when I meant Asynchronous I meant not using a clock. I would never write Q <= d when rising_edge(clk); I would rather put it in a process and use an if statement etc... Could you give me an example of what you mean by Break up the assignments into a seperate with-select assignment for the data, followed by a when-else assignment for the tri-state buffer. From newsfish@newsfish Tue Dec 29 16:42:54 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr25864832qab.5.1368711651054; Thu, 16 May 2013 06:40:51 -0700 (PDT) X-Received: by 10.49.117.229 with SMTP id kh5mr439437qeb.29.1368711651031; Thu, 16 May 2013 06:40:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gj8no310456qab.0!news-out.google.com!y6ni49017qax.0!nntp.google.com!gj8no310454qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 May 2013 06:40:50 -0700 (PDT) In-Reply-To: <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7f0c5a16-a2a5-490d-907a-a5813739e4bf@googlegroups.com> Subject: Re: Asynchronous With Select and When Else Statements From: Andy Injection-Date: Thu, 16 May 2013 13:40:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2759 Xref: mx05.eternal-september.org comp.lang.vhdl:6555 "I would never write Q <=3D d when rising_edge(clk); I would rather put it= in a process and use an if statement etc... " I don't use the concurrent clocked assignment alot, but for the occasional = single register or two, a process is just more code to do the same thing wi= th no benefit. The concurrent assignment is slightly less efficient in simu= lation, but for a single register here and there, the impact is nil. If you want an asynchronous reset on the register: q <=3D '0' when rst =3D '1' else d when rising_edge(clk); After looking at your OP again, the synthesis tool is complaining about an = internal tri-state on mdio_bus (and some other signal you don't describe). = It assumes pull-up logic, meaning that if no driver is enabled, the result = is '1', and it replicates that behavior with logic gates, since FPGA's no l= onger provide internal tri-state drivers (they are only available on IO pin= s). Is mdio_bus supposed to be an inout port on the FPGA device? If so, and you= synthesize this at the module level (without IO insertion), it may impleme= nt differently than if synthesized as part of a whole design. As to an example (but after reading your OP, I don't think it would solve t= he problem), I will leave that as "an exercise for the student" with the fo= llowing hint: Code the multiplexer in a with-select statement, assigning an= intermediate signal (no tristate). Code the tri-state buffer in a when-els= e statement using the intermediate signal. Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr25896745qab.8.1368713648424; Thu, 16 May 2013 07:14:08 -0700 (PDT) X-Received: by 10.49.12.7 with SMTP id u7mr144252qeb.31.1368713648400; Thu, 16 May 2013 07:14:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gj8no344684qab.0!news-out.google.com!y6ni49017qax.0!nntp.google.com!gj8no344676qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 May 2013 07:14:08 -0700 (PDT) In-Reply-To: <7f0c5a16-a2a5-490d-907a-a5813739e4bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> <7f0c5a16-a2a5-490d-907a-a5813739e4bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7fd81e35-d3cf-4f26-a958-2777df65a9e8@googlegroups.com> Subject: Re: Asynchronous With Select and When Else Statements From: Cory Shol Injection-Date: Thu, 16 May 2013 14:14:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4639 Xref: mx05.eternal-september.org comp.lang.vhdl:6556 On Thursday, May 16, 2013 8:40:50 AM UTC-5, Andy wrote: > "I would never write Q <=3D d when rising_edge(clk); I would rather put = it in a process and use an if statement etc... " >=20 >=20 >=20 > I don't use the concurrent clocked assignment alot, but for the occasiona= l single register or two, a process is just more code to do the same thing = with no benefit. The concurrent assignment is slightly less efficient in si= mulation, but for a single register here and there, the impact is nil. >=20 >=20 >=20 > If you want an asynchronous reset on the register: >=20 >=20 >=20 > q <=3D '0' when rst =3D '1' >=20 > else d when rising_edge(clk); >=20 >=20 >=20 > After looking at your OP again, the synthesis tool is complaining about a= n internal tri-state on mdio_bus (and some other signal you don't describe)= . It assumes pull-up logic, meaning that if no driver is enabled, the resul= t is '1', and it replicates that behavior with logic gates, since FPGA's no= longer provide internal tri-state drivers (they are only available on IO p= ins). >=20 >=20 >=20 > Is mdio_bus supposed to be an inout port on the FPGA device? If so, and y= ou synthesize this at the module level (without IO insertion), it may imple= ment differently than if synthesized as part of a whole design. >=20 >=20 >=20 > As to an example (but after reading your OP, I don't think it would solve= the problem), I will leave that as "an exercise for the student" with the = following hint: Code the multiplexer in a with-select statement, assigning = an intermediate signal (no tristate). Code the tri-state buffer in a when-e= lse statement using the intermediate signal. >=20 >=20 >=20 > Andy I understand what you were talking about, but I didn't understand how that = was going to change anything in my problem. mdio_proc1 and mdio_proc2 are the I/O bidirectional pins in the top module= . =20 I want mdio_proc1 and mdio_proc2 to behave like mdio_bus when it is selecte= d. For example: The pre existing code only had the capabilities of one master in the system= , therefore mdio_proc1 looked like below. This statement says: if direction is towards the Slave devices from the processor than release t= he bidirectional I/O. Else if Direction from the slave to the processor th= an either the output will be pulled up or driven to '0'. =20 mdio_proc1 <=3D 'Z' when (direction =3D '0' or mdio_device_data =3D '1') el= se '0';=20 Now attached to my FPGA is another master. The slave devices can only be controlled by proc1 or proc2. Therefore I wa= nt to add a mux to select who controls the bus, but I still want the bus to= act the same. =20 For simplicity: with control select mdio_proc1 <=3D Normal operation as before when '0', 'Z' when others; Now my problem is how can I force it to normal operation within the with se= lect or another method.=20 The only thing I can think of now is adding Direction and Device data into = my mux select and making it like: with direction & mdio_device_data & control select mdio_proc1 <=3D '0' when "100", 'Z' when others; mdio_proc2 would look like: with direction & mdio_device_data & control select mdio_proc2 <=3D '0' when "101", 'Z' when others; From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.130.195 with SMTP id u3mr26028686qas.1.1368716563883; Thu, 16 May 2013 08:02:43 -0700 (PDT) X-Received: by 10.49.86.98 with SMTP id o2mr509776qez.4.1368716563822; Thu, 16 May 2013 08:02:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news1.as3257.net!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l3no8841308qak.0!news-out.google.com!y6ni49017qax.0!nntp.google.com!gj8no393987qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 May 2013 08:02:43 -0700 (PDT) In-Reply-To: <7fd81e35-d3cf-4f26-a958-2777df65a9e8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> <7f0c5a16-a2a5-490d-907a-a5813739e4bf@googlegroups.com> <7fd81e35-d3cf-4f26-a958-2777df65a9e8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Asynchronous With Select and When Else Statements From: Andy Injection-Date: Thu, 16 May 2013 15:02:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1666 Xref: mx05.eternal-september.org comp.lang.vhdl:6557 If you are willing to live with the warning, it looks like synthesis built HW that behaves like you want, but without any internal tristate, using equivalent logic (assuming pullup). Simulate the gate level (post-synthesis) netlist to verify. If you don't want the warning, you will have to describe the behavior you want without using internal tri-state signals. Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.74.7 with SMTP id s7mr334637qaj.4.1368733373019; Thu, 16 May 2013 12:42:53 -0700 (PDT) X-Received: by 10.182.84.202 with SMTP id b10mr133292obz.14.1368733372864; Thu, 16 May 2013 12:42:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!gj8no657833qab.0!news-out.google.com!y6ni49017qax.0!nntp.google.com!gj8no657827qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 May 2013 12:42:52 -0700 (PDT) In-Reply-To: <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Counting number of asserted register bits in VHDL From: kevin.neilson@xilinx.com Injection-Date: Thu, 16 May 2013 19:42:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6558 Andy, Thanks--I wasn't sure if the variable had to be initialized to zero. I don= 't use variables often. =20 I elided the type conversion in my code snippet (even though that's where I= spend half my VHDL development time). I tried your std_logic->integer con= version above and Synplify didn't seem to be liking it, and I ended up havi= ng to do a ridiculous conversion like this: sum :=3D sum + to_integer(unsigned(std_logic_vector'(0=3D>mod_cmplt(k)))); This is why Verilog is awesome. You want to add a real number and the msb = of an integer and a slice of a character string? No problem; no conversion= s required. -Kevin From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp2-2.free.fr!not-for-mail Date: Thu, 16 May 2013 22:51:24 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Counting number of asserted register bits in VHDL References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 9 Message-ID: <519546c9$0$13982$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 16 May 2013 22:51:21 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1368737481 news-3.free.fr 13982 88.185.146.198:1426 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6559 Le 16/05/2013 21:42, kevin.neilson@xilinx.com a écrit : > This is why Verilog is awesome. You want to add a real number and the msb of an integer and > a slice of a character string? No problem; no conversions required. That's weak typing's advantage. But it lets you so easily shoot yourself in the foot... Nicolas From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Generics, packages, and VHDL-2008 Date: Thu, 16 May 2013 14:52:27 -0700 Organization: Highland Technology, Inc. Lines: 16 Message-ID: <20130516145227.2e6c5d8a@rg.highlandtechnology.com> References: <20130509121609.76f13be5@rg.highlandtechnology.com> <043bf5cd-fcf7-497f-8ac1-2e5370025398@googlegroups.com> <20130509133504.3c08bca5@rg.highlandtechnology.com> <6dde988b-0f27-4133-a462-6639aa34562d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4d736eb7372dfbec09ce671174b8b29e"; logging-data="12567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18UUoGhorrcsoc2XfM27ib5" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:qKxO4vt7jHtohcEtwTLE4bvnQlM= Xref: mx05.eternal-september.org comp.lang.vhdl:6560 On Thu, 9 May 2013 16:12:35 -0700 (PDT) Andy wrote: > I think the large number of changes in 2008, combined with poor user-knowledge of the new features, and therefore little input from customers clamoring for them, all contributed to the delay in implementing these changes. > > Regardless of whether you find/use a work-around, let them know you need this feature. It helps them prioritize their efforts. > > Also, if you know of a competitor that supports the feature you need already, let Aldec know that too. That often helps. > > Andy Just to follow up on this, Aldec says that version 9.3 should come out in August and fix this issue. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.42.141 with SMTP id s13mr26843718qae.3.1368746057756; Thu, 16 May 2013 16:14:17 -0700 (PDT) X-Received: by 10.49.95.40 with SMTP id dh8mr746390qeb.19.1368746057637; Thu, 16 May 2013 16:14:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!gj8no765296qab.0!news-out.google.com!y6ni49017qax.0!nntp.google.com!gj8no765292qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 16 May 2013 16:14:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66ca157b-edad-440f-aec2-b630956cc124@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: Andy Injection-Date: Thu, 16 May 2013 23:14:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6561 Kevin, Did you try to_integer(unsigned'(0 => mod_cmplt(k)))? I usually use the if statement anyway. Much more readable. Verilog: "Hold my beer and watch this!" Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Asynchronous With Select and When Else Statements Date: Thu, 16 May 2013 23:33:48 -0400 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <8970ac03-3eee-4a1c-9ee0-bb426c321ee2@googlegroups.com> <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 17 May 2013 03:30:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="2f1d56cc32a64948e21bd8c19c258ccf"; logging-data="25021"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mpxuO7v73Gmv7gw4e24MJ" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <18674bb5-297e-45df-a7c8-d66bfcafb085@googlegroups.com> Cancel-Lock: sha1:5mbNPe5naey7O4OqZ3rhcPqDlnw= Xref: mx05.eternal-september.org comp.lang.vhdl:6562 On 5/15/2013 3:23 PM, Cory Shol wrote: > > Could you give me an example of what you mean by Break up the assignments into a seperate with-select assignment for the data, followed by a when-else assignment for the tri-state buffer. He means something like this... A <= 'z' when (foo = 1) else B; B <= stuff when (other stuff); BTW, separate has "a rat". I was taught that in elementary school and I never forgot it. -- Rick From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.174.145 with SMTP id t17mr1329646qaz.4.1368806390252; Fri, 17 May 2013 08:59:50 -0700 (PDT) X-Received: by 10.50.111.131 with SMTP id ii3mr2926391igb.15.1368806390071; Fri, 17 May 2013 08:59:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!l3no9502788qak.0!news-out.google.com!y6ni50164qax.0!nntp.google.com!gj8no1064902qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 May 2013 08:59:49 -0700 (PDT) In-Reply-To: <66ca157b-edad-440f-aec2-b630956cc124@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> <66ca157b-edad-440f-aec2-b630956cc124@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18ea62fe-05eb-4bda-9106-5240a246d9bb@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: kevin.neilson@xilinx.com Injection-Date: Fri, 17 May 2013 15:59:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6563 Andy: Yes, that does work, with the unsigned cast (using ') instead of the unsigned function. I don't really know the difference, but the cast does work. -Kevin From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.36.66 with SMTP id s2mr28449284qad.6.1368809345226; Fri, 17 May 2013 09:49:05 -0700 (PDT) X-Received: by 10.49.30.105 with SMTP id r9mr740885qeh.27.1368809345159; Fri, 17 May 2013 09:49:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!l3no9513125qak.0!news-out.google.com!y6ni50164qax.0!nntp.google.com!gj8no1075468qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 May 2013 09:49:05 -0700 (PDT) In-Reply-To: <18ea62fe-05eb-4bda-9106-5240a246d9bb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <3055736e-feb8-4abb-b70b-3e408682dad7@googlegroups.com> <8c2ff01a-0e9a-4b5e-b65c-517a0be5a372@googlegroups.com> <07a146fa-01b4-4434-8bf4-a850350e8d75@googlegroups.com> <66ca157b-edad-440f-aec2-b630956cc124@googlegroups.com> <18ea62fe-05eb-4bda-9106-5240a246d9bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e9de1c5-9dd9-4602-b0af-83cd623c7d21@googlegroups.com> Subject: Re: Counting number of asserted register bits in VHDL From: Andy Injection-Date: Fri, 17 May 2013 16:49:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6564 Kevin, leaving out the ' was an unfortunate typo in my original suggestion. Unsigned() is a built-in type conversion function from any closely related = type to unsigned (a cast). In order for it to work, the argument must be st= atically determinable to be of a single type that is acceptable for the con= verion function.=20 The problem is (0 =3D> [std_logic expression]) could be any of: slv, sulv, = signed or unsigned, and perhaps others if additional packages are used. Mo= re importantly, all of those potential types are closely related to unsigne= d and allowable arguments for unsigned(). Thus the compiler cannot make a u= nique determination of which ONE of those types to use, so it throws an err= or (even though we know it really would not make a difference in the end). Unsigned'() is a type designator. The type designator tells the compiler th= at the following anonymous expression IS of the type indicated. It is used = when the following anonymous expression could be numerous types that would = all "work", but VHDL needs to know which ONE of those that "will work" it s= hould use. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr30202487qab.0.1368877491078; Sat, 18 May 2013 04:44:51 -0700 (PDT) X-Received: by 10.49.96.8 with SMTP id do8mr192066qeb.30.1368877491048; Sat, 18 May 2013 04:44:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gj8no1339414qab.0!news-out.google.com!y6ni50164qax.0!nntp.google.com!gj8no1339411qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 18 May 2013 04:44:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.21.33.69; posting-account=P4tq1QoAAAA5jIVtSJQ7dEPdfnyZ9yGA NNTP-Posting-Host: 78.21.33.69 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> Subject: Signal xx cannot be synthesized, bad synchronous description error From: robbevt@gmail.com Injection-Date: Sat, 18 May 2013 11:44:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 43 Xref: mx05.eternal-september.org comp.lang.vhdl:6565 Hi I need to make a kind of controller for a school project but i keep getting= stuck on the same error. which is:=20 "ERROR:Xst:827 - "D:/School/VHDL/ServoController/ControllerBeta.vhd" line 1= 32: Signal nextstate cannot be synthesized, bad synchronous description. Th= e description style you are using to describe a synchronous element (regist= er, memory, etc.) is not supported in the current software release." I had the exact same error before, but then with a different signal above t= his line, and when i fixed that (i did not alter the code below line 132) t= his one popped up. Here is the code beginning from line 132: NEXT_STATE_DECODE: process (state, doneData, donePuls, SET, CLK) begin nextstate <=3D state; =09 case (state) is when idle =3D> if rising_edge(SET) then nextstate <=3D leesAdres; end if; when leesAdres =3D> if (ADDRDATA =3D Address) then nextstate <=3D leesData= ;=20 else nextstate <=3D idle; end if; when leesData =3D> if doneData =3D '1' then nextstate <=3D geefPuls; end i= f; when geefPuls =3D> if donePuls =3D '1' then nextstate <=3D idle; end if; when others =3D> nextstate <=3D idle; end case; end process; end Behavioral; I don't quite understand where i could have gone wrong in such a small and = relatively simple block of code, i'm using the language templates and they = do it in the same way. The previous error got solved by changing a case sta= tement to an if statement, but that shouldn't be necessary right? Any help would be very appreciated. If you need me to post the rest of the code just ask, i didn't include it n= ow to reduce the clutter of my post. From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.165.130 with SMTP id i2mr30497046qay.2.1368887900693; Sat, 18 May 2013 07:38:20 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.71.75 with SMTP id s11mr53347qeu.20.1368887900660; Sat, 18 May 2013 07:38:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gj8no1425109qab.0!news-out.google.com!y6ni50274qax.0!nntp.google.com!l3no9859140qak.0!postnews.google.com!gq1g2000vbb.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 18 May 2013 07:38:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: gq1g2000vbb.googlegroups.com; posting-host=188.98.124.219; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 188.98.124.219 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:20.0) Gecko/20100101 Firefox/20.0,gzip(gfe) Message-ID: Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Thomas Stanka Injection-Date: Sat, 18 May 2013 14:38:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2682 Xref: mx05.eternal-september.org comp.lang.vhdl:6566 On 18 Mai, 13:44, robb...@gmail.com wrote: > NEXT_STATE_DECODE: process (state, doneData, donePuls, SET, CLK) This is a combinatorial process, it describes the logic behavior of pure combinatoric (the style for a statemachine is widely used in old/ bad books, use search function to learn about that issue as fsm style has nothing to do with your problem and it is not wrong) > =A0 =A0 =A0 =A0 when idle =3D> if rising_edge(SET) then nextstate <=3D le= esAdres; end if combinatorial process don't allow rising edge. Rising edge is only allowed in sequential process in the following style: process (clk, asyncreset) if asyncreset =3D condition then -- resetstatements elsif rising_edge(Clk) then -- sequential statements with the asynchronous reset beeing optional I guess you like to stay in a state, till a signal rises from 0 to 1, this needs to be done by clocking that signal into a shiftregister and detect rising edge by xor the last two register of the shiftreg if rising_egde(Clk) then my_sr <=3D my_sr(my_sr'high-1 downto 0) & inputsignal; -- if inputsignal is syncronous to clk, use only 2 ff, or if you need it fast only 1 ff and xor with inputsignal, else use additional ff (typically 2) edge <=3D my_sr(my_sr'high) xor my_sr(my_sr'high -1); -- this means edge is stored in a ff, edge could be also generate outside clocked process to represent xor without ff end if From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.42.141 with SMTP id s13mr32524004qae.3.1368965988742; Sun, 19 May 2013 05:19:48 -0700 (PDT) X-Received: by 10.49.61.137 with SMTP id p9mr3965283qer.40.1368965988683; Sun, 19 May 2013 05:19:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!l3no10403827qak.0!news-out.google.com!y6ni50351qax.0!nntp.google.com!l3no10403824qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 May 2013 05:19:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.22.211.117; posting-account=P4tq1QoAAAA5jIVtSJQ7dEPdfnyZ9yGA NNTP-Posting-Host: 78.22.211.117 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: robbevt@gmail.com Injection-Date: Sun, 19 May 2013 12:19:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6567 Hi Thomas Thank you for your response. I understand what you mean, i didn't realize this wasn't allowed but it is quite logical once you think about it. Could i perhaps change the rising_edge(SET) statement by: if SET'event and SET='1' then ... or is this also wrong? Or should i let SET go through a D-flipflop so i can check if SET='1' and Q='0' with Q being the output of the flipflop. The reason i ask this i because i don't fully understand where to put this register, in a new process? Thanks again for your feedback. From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.36.66 with SMTP id s2mr32639821qad.6.1368971217303; Sun, 19 May 2013 06:46:57 -0700 (PDT) X-Received: by 10.49.1.197 with SMTP id 5mr1317327qeo.24.1368971217243; Sun, 19 May 2013 06:46:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!t11no360890qal.0!news-out.google.com!y6ni50289qax.0!nntp.google.com!t11no360884qal.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 May 2013 06:46:57 -0700 (PDT) In-Reply-To: <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.22.211.117; posting-account=P4tq1QoAAAA5jIVtSJQ7dEPdfnyZ9yGA NNTP-Posting-Host: 78.22.211.117 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: robbevt@gmail.com Injection-Date: Sun, 19 May 2013 13:46:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6568 After going over this a few times in my head, i think i now understand what to do. I make a new process with the sole purpose of storing the 2 latest values of SET (with the appropriate CLK), then i can change the rising_edge statement with an if (register(0) = '0' and register(1) = '1') then ... Could you confirm if i have this correctly? Thanks in advance From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.174.145 with SMTP id t17mr8059446qaz.4.1369064211637; Mon, 20 May 2013 08:36:51 -0700 (PDT) X-Received: by 10.49.96.8 with SMTP id do8mr576434qeb.30.1369064211538; Mon, 20 May 2013 08:36:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!t11no546889qal.0!news-out.google.com!y6ni50289qax.0!nntp.google.com!t11no546888qal.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 May 2013 08:36:51 -0700 (PDT) In-Reply-To: <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66bec2d1-a80e-487e-b8af-67c83e1640a9@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Andy Injection-Date: Mon, 20 May 2013 15:36:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6569 I might use (assuming register is defined with a downto range) the following: if register = "10" then ... I would also use a more meaningful name like "edge" instead of "register". Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.215.194 with SMTP id hf2mr35164351qab.0.1369064556152; Mon, 20 May 2013 08:42:36 -0700 (PDT) X-Received: by 10.49.96.8 with SMTP id do8mr579363qeb.30.1369064556048; Mon, 20 May 2013 08:42:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!news.glorb.com!t11no547626qal.0!news-out.google.com!y6ni50289qax.0!nntp.google.com!t11no547619qal.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 20 May 2013 08:42:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Andy Injection-Date: Mon, 20 May 2013 15:42:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6570 Warning: XOR on the shift register contents will detect both falling AND rising edges! Note: While this problem (or any other) can be solved by correctly applying the two-process model (separate processes for combiinatorial logic and registers), the solution is much easier and more understandable in a single process model. Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Signal xx cannot be synthesized, bad synchronous description error Date: Mon, 20 May 2013 13:13:21 -0400 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 20 May 2013 17:09:32 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="803eaee5f1c66902ef50fa2b579214f2"; logging-data="24172"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+SX1dacyXueFlTVvoTEDdH" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> Cancel-Lock: sha1:IpV7nW4gbkQa3TfEPz51soUSy/E= Xref: mx05.eternal-september.org comp.lang.vhdl:6571 On 5/19/2013 8:19 AM, robbevt@gmail.com wrote: > Hi Thomas > > Thank you for your response. > I understand what you mean, i didn't realize this wasn't allowed but it is quite logical once you think about it. > > Could i perhaps change the rising_edge(SET) statement by: if SET'event and SET='1' then ... or is this also wrong? > > Or should i let SET go through a D-flipflop so i can check if SET='1' and Q='0' with Q being the output of the flipflop. > > The reason i ask this i because i don't fully understand where to put this register, in a new process? I'm not sure what your background is, but this is the sort of misunderstanding that happens when people with a software background start out writing HDL programs. HDL stands for "hardware description language" so it isn't programming as such, but rather describing the functionality of hardware. The functionality you are describing does not correspond to any hardware I am familiar with. Try drawing a block diagram of what you intend the logic to be. Draw blocks for registers and just use ovals for the combinatorial logic with some equations describing the logic function. Then you can easily code this by writing code with the boiler plate that Thomas gave you for the registers and the combinatorial equations can be in a combinatorial process or using concurrent statements. Once you learn where this takes you, you can omit the block diagrams just start coding in the future. -- Rick From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Signal xx cannot be synthesized, bad synchronous description error Date: Mon, 20 May 2013 13:15:48 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 20 May 2013 17:11:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="803eaee5f1c66902ef50fa2b579214f2"; logging-data="24172"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX187d9/s4aye3UbQDCNtT2Ly" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:2OYvkL4Zmu4+6C3M5raFlziTR1g= Xref: mx05.eternal-september.org comp.lang.vhdl:6572 On 5/20/2013 11:42 AM, Andy wrote: > Warning: > > XOR on the shift register contents will detect both falling AND rising edges! > > Note: While this problem (or any other) can be solved by correctly applying the two-process model (separate processes for combiinatorial logic and registers), the solution is much easier and more understandable in a single process model. The caveat is that the single process model has *no* combinatorial outputs. So any output that decodes the state will have a clock cycle delay which may or may not matter in any given design. -- Rick From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Signal xx cannot be synthesized, bad synchronous description error Date: Mon, 20 May 2013 22:08:44 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 May 2013 02:04:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="9a4464ebbde45b378727542e57d5685e"; logging-data="26370"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jNB+GSwg/O8JPQzULq9fZ" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:taN021mGbJYWhDRgJcVUIBH5hyQ= Xref: mx05.eternal-september.org comp.lang.vhdl:6573 On 5/20/2013 1:15 PM, rickman wrote: > On 5/20/2013 11:42 AM, Andy wrote: >> Warning: >> >> XOR on the shift register contents will detect both falling AND rising >> edges! >> >> Note: While this problem (or any other) can be solved by correctly >> applying the two-process model (separate processes for combiinatorial >> logic and registers), the solution is much easier and more >> understandable in a single process model. > > The caveat is that the single process model has *no* combinatorial > outputs. So any output that decodes the state will have a clock cycle > delay which may or may not matter in any given design. > It's pretty easy to work around this issue. First, outputs that decode *only* the state can easily be external to the process, but as continuous assignments, avoiding the potential latch pitfalls of a two-process state machine where the next state is in the combinatorial process. Second, you can have outputs that change *with* the state rather than one cycle later if you assign them in the transition rather than the state, i.e. at the same time you assign the next state. Once you get used to thinking a cycle ahead, it gets quite easy to do, and I always prefer code where I can see as much as possible in one screen of statements. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.165.130 with SMTP id i2mr1128149qay.2.1369129153318; Tue, 21 May 2013 02:39:13 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.87.232 with SMTP id bb8mr67185qeb.28.1369129153295; Tue, 21 May 2013 02:39:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no128875qab.0!news-out.google.com!y6ni50669qax.0!nntp.google.com!ch1no128872qab.0!postnews.google.com!y5g2000vbg.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 May 2013 02:39:13 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: y5g2000vbg.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.9.0.11735) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.28) Gecko/20120306 Firefox/3.6.28,gzip(gfe) Message-ID: <2cfc7eb8-3c78-417e-9e39-f5c983ef898a@y5g2000vbg.googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Thomas Stanka Injection-Date: Tue, 21 May 2013 09:39:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6574 On 19 Mai, 15:46, robb...@gmail.com wrote: > After going over this a few times in my head, i think i now understand what to do. > > I make a new process with the sole purpose of storing the 2 latest values of SET (with the appropriate CLK), then i can change the rising_edge statement with an if (register(0) = '0' and register(1) = '1') then ... > > Could you confirm if i have this correctly? I can confirm this. You could check out the code sniplet in my first post. It is quick&dirty, as using 2 FF with 1 XOR detects falling and rising edges, so you need to check the content of the last shift register as well in order to see which edge you have. regards Thomas From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Signal xx cannot be synthesized, bad synchronous description error Date: Tue, 21 May 2013 10:03:18 -0400 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> <2cfc7eb8-3c78-417e-9e39-f5c983ef898a@y5g2000vbg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 May 2013 13:59:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="803eaee5f1c66902ef50fa2b579214f2"; logging-data="24330"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/csLOTVZ9R/cAh24TAfgMi" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <2cfc7eb8-3c78-417e-9e39-f5c983ef898a@y5g2000vbg.googlegroups.com> Cancel-Lock: sha1:BCLtH4uD5qEq++YsafM8qWSWfNI= Xref: mx05.eternal-september.org comp.lang.vhdl:6575 On 5/21/2013 5:39 AM, Thomas Stanka wrote: > On 19 Mai, 15:46, robb...@gmail.com wrote: >> After going over this a few times in my head, i think i now understand what to do. >> >> I make a new process with the sole purpose of storing the 2 latest values of SET (with the appropriate CLK), then i can change the rising_edge statement with an if (register(0) = '0' and register(1) = '1') then ... >> >> Could you confirm if i have this correctly? > > I can confirm this. You could check out the code sniplet in my first > post. It is quick&dirty, as using 2 FF with 1 XOR detects falling and > rising edges, so you need to check the content of the last shift > register as well in order to see which edge you have. To detect just one edge, you use an AND gate with one input inverted. Invert the first FF and you have a falling edge detection. Invert the second FF and you get a rising edge detection. -- Rick From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.36.66 with SMTP id s2mr3887859qad.6.1369229778251; Wed, 22 May 2013 06:36:18 -0700 (PDT) X-Received: by 10.49.30.105 with SMTP id r9mr644635qeh.27.1369229778186; Wed, 22 May 2013 06:36:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!l3no10915257qak.0!news-out.google.com!y6ni50756qax.0!nntp.google.com!ch1no311465qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 06:36:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8bdbe6bb-cbbf-4fcc-adcf-842b5933ceae@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Andy Injection-Date: Wed, 22 May 2013 13:36:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 48 Xref: mx05.eternal-september.org comp.lang.vhdl:6576 Ah, but you CAN have combinatorial outputs driven from a synchronous proces= s! But they cannot be a combinatorial function of an input to the process, = they must be a combinatorial function of register(s) inferred by the proce= ss Structurally speaking, if you use a variable for the register, then any exp= ressions in assignments from those variables occurring after the last (rst/= clock) end-if will infer combinatorial logic after the register. process (rst, clk) is variable state is ... begin if rst then state :=3D init; elsif rising_edge(clk) then case state is when init =3D> state :=3D start; ... end case; end if; -- combinatorial outputs from registered variables ouput <=3D '0'; -- default to avoid latches case state is -- state is a register here when init | start =3D> output <=3D '1';=20 when others =3D> null; end case; end process; This behavior/synthesis is documented in IEEE 1076.6-2002, the VHDL RTL Syn= thesis Standard. Note that it is the behavior that drives the synthesis res= ult, not the structure of the process. The structure shown is one way to de= scribe the behavior that results in combinatorial outputs from registers. B= ecause state is accessed on a falling edge of the clock, when it was last a= ssigned on a previous rising edge, the last reference to state is to a prev= iously (in simulated time) stored value, the registered value of state is u= sed. Because the output is updated (assigned) on both edges of the clock, i= t must be combinatorial. Note that if the output case statement was moved to before the final end-if= , then output is registered, and the combinatorial logic for it is fed by t= he combinatorial value of state, which includes the update logic for state.= But the cycle-accurate behavior of the state machine and of output is not = changed whether the outputs are assigned within the clocked if-statement or= afterward, assuming you included a reset assignment for output. Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.36.66 with SMTP id s2mr3907134qad.6.1369230489972; Wed, 22 May 2013 06:48:09 -0700 (PDT) X-Received: by 10.49.121.9 with SMTP id lg9mr637739qeb.39.1369230489949; Wed, 22 May 2013 06:48:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no312743qab.0!news-out.google.com!y6ni50926qax.0!nntp.google.com!l3no10916599qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 06:48:09 -0700 (PDT) In-Reply-To: <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=93.93.41.2; posting-account=BTwBmgoAAACIIiI-cTWrGpF0cxuMtdsY NNTP-Posting-Host: 93.93.41.2 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> <860f38af-b593-4427-bbda-e3761d844fdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a9e65cf-536d-4438-a82f-653fb097ff17@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: celine.boutet.perso@gmail.com Injection-Date: Wed, 22 May 2013 13:48:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2237 Xref: mx05.eternal-september.org comp.lang.vhdl:6577 Le dimanche 19 mai 2013 15:46:57 UTC+2, rob...@gmail.com a =E9crit=A0: > After going over this a few times in my head, i think i now understand wh= at to do. >=20 >=20 >=20 > I make a new process with the sole purpose of storing the 2 latest values= of SET (with the appropriate CLK), then i can change the rising_edge state= ment with an if (register(0) =3D '0' and register(1) =3D '1') then ...=20 >=20 >=20 >=20 > Could you confirm if i have this correctly? >=20 > Thanks in advance Yes, that's it. Just a question : do you really want to make an asynchronous FSM ? I you re= ally want an asynchronous FSM you should delete CLK from the sensitivity li= st as it can lead to mismatch between simulation and synthesis. But as an old school gal I recommend to make your FSM synchronous. It will = prevent you from many errors if you are new to VHDL. From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr4087095qab.8.1369235660994; Wed, 22 May 2013 08:14:20 -0700 (PDT) X-Received: by 10.182.105.103 with SMTP id gl7mr292091obb.16.1369235660923; Wed, 22 May 2013 08:14:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!ch1no324025qab.0!news-out.google.com!y6ni50756qax.0!nntp.google.com!ch1no324022qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 08:14:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <746790fa-955c-46da-b8fa-563cfdcdecf0@googlegroups.com> Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: Andy Injection-Date: Wed, 22 May 2013 15:14:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6578 Rick, I agree that designers need to be aware of what kinds of hardware are reali= zable and reliable in FPGAs/ASICs. And I agree that the designer needs to focus on the functionality (I call i= t behavior) of the HW. However, I completely disagree that a block diagram should desicribe separa= te registers and equations for combinatorial logic. The diagram should be hierarchical based on related behavior, and ultimatel= y broken down into blocks of related behaviors that can be described in a s= equential manner (a flow chart). Then I suggest coding clock-cycle-accurate= , behavioral RTL models of the blocks (flow charts) from the diagram.=20 Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.36.66 with SMTP id s2mr4098341qad.6.1369235912781; Wed, 22 May 2013 08:18:32 -0700 (PDT) X-Received: by 10.182.89.130 with SMTP id bo2mr295667obb.38.1369235912553; Wed, 22 May 2013 08:18:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no324566qab.0!news-out.google.com!y6ni50756qax.0!nntp.google.com!ch1no324565qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 08:18:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0c658471-d117-4420-aca8-b8d385d41d34@googlegroups.com> Subject: Re: VHDL Standards Invitation and Status From: Jim Lewis Injection-Date: Wed, 22 May 2013 15:18:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 36 Xref: mx05.eternal-september.org comp.lang.vhdl:6579 Hi Gabor, > I didn't look very deep into the existing requests, but I wonder if > > anyone considered bit reversal, for example allowing SLV's defined > > as (N downto 0) to be referenced in reverse order (0 to N). > > > > PRO: > > Reduces use of loops for intentional bit reversal > > > > CON: > > Could happen unintentionally when you thought you had a > > signal defined with "downto", when it was actually defined > > with "to" causing undesired bit reversal. We don't have any requests for this. Do you have a specific use case? This is what is required to initiate a proposal. Perhaps you want to post this as a separate thread to gauge the interest level. I agree with Andy, it would be bad to do this with index ranges, however, a reverse function would work just as well. If it were something for broad usage, I would prefer an implicitly defined function - like "&" which is implicitly defined for all single dimensional arrays. Jim From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.217.195 with SMTP id hn3mr4136609qab.5.1369237175573; Wed, 22 May 2013 08:39:35 -0700 (PDT) X-Received: by 10.49.95.137 with SMTP id dk9mr777263qeb.34.1369237175559; Wed, 22 May 2013 08:39:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l3no10930102qak.0!news-out.google.com!y6ni50756qax.0!nntp.google.com!ch1no327341qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 08:39:35 -0700 (PDT) In-Reply-To: <518cc1d4$0$3122$ba620e4c@news.skynet.be> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=93.93.41.2; posting-account=N5yKXQoAAACmjypJy0tR9bRYrpl47s7a NNTP-Posting-Host: 93.93.41.2 References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: celine Injection-Date: Wed, 22 May 2013 15:39:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5142 Xref: mx05.eternal-september.org comp.lang.vhdl:6580 Le vendredi 10 mai 2013 11:45:56 UTC+2, Jan Decaluwe a =E9crit=A0: > On 05/10/2013 06:48 AM, rickman wrote: >=20 >=20 >=20 > > That's what I'm not clear on. I don't see why *anything* is needed >=20 > > to keep the register in reset as long as the reset is asserted. >=20 > > That's what the reset does, it holds the FF in reset. I've never >=20 > > seen a feedback mux added to a FF to implement a reset. Or are you >=20 > > referring to the internal logic of the FF? >=20 >=20 >=20 > The feedback mux is needed if you *forget* to reset the register >=20 > in the 'if reset' clause. In that case, HDL semantics dictate >=20 > that the register should keep its previous value during reset, >=20 > hence the feedback mux. >=20 >=20 >=20 > Jan >=20 >=20 >=20 > --=20 >=20 > Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com >=20 > Python as a HDL: http://www.myhdl.org >=20 > VHDL development, the modern way: http://www.sigasi.com >=20 > World-class digital design: http://www.easics.com Hi all, Your discussion rises a lot of questions in my head on whether I usually do= right or not. For simple FSMs I usually use a one process description, and when I have so= me signals that I am sure that are assigned in a state before use I don't r= eset them. I do this because I work with Xilinx technology and I understood= that not resetting these signals gives more freedom to the tool: from Spartan 6 CLB User Guide : "To maximize design flexibility and utiliza= tion, use the GSR and avoid local initialization signals." For instance it gives this kind of process: --! @brief Receiver Finite State Machine --! @details The module detects the frame header according to the frame f= orming protocol, receives the data and check the CRC p_rx_fsm : process (clk, rst) constant DFL_NULL : unsigned(rx_ctr_dfl'length-1 downto 0) :=3D (others= =3D> '0'); variable frx_sr : std_logic_vector((maximum(maximum(ADR_L, CRC_L), ma= ximum(CMD_L, DFL_L))*FW_L)-1 downto 0); --!=20 begin if (rst =3D RST_ALVL) then frx_fsm <=3D FRX_IDLE; -- no reset required for frx_dat_cnt elsif (rising_edge(clk)) then case frx_fsm is when FRX_IDLE =3D> if (f_rx_wr =3D '1' and f_rx_d =3D rx_ctr_sof) then frx_fsm <=3D FRX_DFL; end if; when FRX_DFL =3D> if (f_rx_wr =3D '1') then frx_fsm <=3D FRX_DAT; frx_dat_cnt <=3D unsigned(frx_sr(DFL_L*FW_L-1 downto 0))-1; end if; when FRX_DAT =3D> if (f_rx_wr =3D '1') then if (frx_dat_cnt =3D DFL_NULL) then frx_fsm <=3D FRX_EOF; else frx_fsm <=3D FRX_DAT; frx_dat_cnt <=3D frx_dat_cnt - 1; end if; end if; when FRX_EOF =3D> if (f_rx_wr =3D '1') then frx_fsm <=3D FRX_IDLE; end if; when others =3D> frx_fsm <=3D FRX_IDLE; end case; end if; end process p_rx_fsm; I synthesized it on a Spartan 6 and looked in FPGA Editor what the frx_dat_= cnt FF looked like and I saw that no SR pin was used. I then wrote the above process in two different processes, one for the FSM = state in a (clk, rst) process and another for the frx_dat_cnt signal with c= lk only process. Both methods gave me exactly the same diagram in FPGA Editor. So here is my question: is it just an XST interpretation of the VHDL or is = it valid in all cases ?=20 In other words can the code above lead to the same "feedback mux" warning i= n another synthesizer ? From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.66.197.229 with SMTP id ix5mr722790pac.23.1369248806147; Wed, 22 May 2013 11:53:26 -0700 (PDT) X-Received: by 10.49.71.135 with SMTP id v7mr953867qeu.22.1369248805908; Wed, 22 May 2013 11:53:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.nobody.at!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!c5no20554392pbj.1!news-out.google.com!d5ni8333pbl.0!nntp.google.com!ch1no341026qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 11:53:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Wed, 22 May 2013 18:53:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6581 OK, you implied that both code versions generated the same circuit with res= pect to set/reset, but you did not say whether they had exactly the same cl= ock enable (feedback mux) logic for the counter. Did they? The reason I ask is that many years ago, Synopsys FPGA Compiler II (may it = rest in peace) did not give warnings about feedback muxes, because it did n= ot insert them!=20 Synplify, as far as I know (I've been using it for at least 15 years) has a= lways implemented the feedback mux (and issued warnings) in order to create= hardware that behaved like the RTL, even while reset was asserted and the = clock was still running. I have no idea whether XST inserts feedback muxes or not, or if it does, wh= ether it issues warnings for them. Any tool that does not insert feedback m= uxes (usually implemented using the clock enable input on the flip-flop) in= this situation is broken. As to whether all registers should be reset, there are many design techniqu= es that will work. There are fewer of them that are easily verifiable and a= re not mistake-prone.=20 If you reset all registers, it is fairly easy to find out if you missed one= (look for register primitives that do not have reset inputs). Verifying th= at all non-reset registers are initialized otherwise is more difficult to v= erify, and more prone to mistakes.=20 When I worked with PALs, we designed state machines that handled asynchrono= us inputs without separately synchronizing them by controlling the state ma= pping and ensuring that only one register bit changed in response to that a= synchronous input. It worked really well, and saved registers in PALs with = very few registers available. I would not recommend using the same techniqu= e in FPGAs because it is much harder to verify, much more mistake-prone, an= d using an extra register or two to explicily synchronize an input before t= he state machine reads it is no big deal in an FPGA, they have lots of regi= sters. Also, IIRC, Xilinx FPGAs cannot merge multiple registers into the same CLB = (or slice?) that have different reset or clock signals. This means that you= are better off resetting all registers to allow maximum freedom in mapping= them to CLBs and slices during P&R.=20 Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.66.161.72 with SMTP id xq8mr717334pab.33.1369249693170; Wed, 22 May 2013 12:08:13 -0700 (PDT) X-Received: by 10.49.30.105 with SMTP id r9mr968154qeh.27.1369249692894; Wed, 22 May 2013 12:08:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c5no20588179pbj.1!news-out.google.com!d5ni8333pbl.0!nntp.google.com!ch1no342080qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 May 2013 12:08:12 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.8.47.233; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 194.8.47.233 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: abstract type signal From: Ilya Kalistru Injection-Date: Wed, 22 May 2013 19:08:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6582 Hi everyone! I have a module, that makes some actions with signal S of the type myType. This actions with signal S is independent of its type. For using this modules for signals of various types I create a copies of module with another name and "Find and replace" myType to MyOtherType. I think that it is conceptually wrong way. Is there a way to define a signal of abstract data type and substitute the correct type in place abstract when I need use it? May I use "generic" for this purpose? -- Best Regards, Ilya Kalistru Engineer looking for a complicated job. From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: abstract type signal Date: Wed, 22 May 2013 12:25:00 -0700 Organization: Highland Technology, Inc. Lines: 22 Message-ID: <20130522122500.35f14199@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4d736eb7372dfbec09ce671174b8b29e"; logging-data="31707"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2yLb0HkpQVJX8TCfRhe5r" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:uIHuBkvXI9FHDCJ4k6FXspCx3Uo= Xref: mx05.eternal-september.org comp.lang.vhdl:6583 On Wed, 22 May 2013 12:08:12 -0700 (PDT) Ilya Kalistru wrote: > Hi everyone! > > I have a module, that makes some actions with signal S of the type myType. This actions with signal S is independent of its type. > > For using this modules for signals of various types I create a copies of module with another name and "Find and replace" myType to MyOtherType. > I think that it is conceptually wrong way. > > Is there a way to define a signal of abstract data type and substitute the correct type in place abstract when I need use it? May I use "generic" for this purpose? > > -- > Best Regards, > Ilya Kalistru > Engineer looking for a complicated job. That's a feature in VHDL-2008, and in my experience one that's not very widely supported yet. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Signal xx cannot be synthesized, bad synchronous description error Date: Wed, 22 May 2013 17:01:39 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> <93bcee8f-aa1f-4ed0-8620-cb67ea56e364@googlegroups.com> <746790fa-955c-46da-b8fa-563cfdcdecf0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 22 May 2013 20:57:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="131d71abdca206f852e85f753b3a8167"; logging-data="27742"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1809F1swJ2Ou2IxaNH7Dgi0" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <746790fa-955c-46da-b8fa-563cfdcdecf0@googlegroups.com> Cancel-Lock: sha1:Ztwzg3qVDa73nvJ98UHaYnfr2MY= Xref: mx05.eternal-september.org comp.lang.vhdl:6584 On 5/22/2013 11:14 AM, Andy wrote: > Rick, > > I agree that designers need to be aware of what kinds of hardware are realizable and reliable in FPGAs/ASICs. > > And I agree that the designer needs to focus on the functionality (I call it behavior) of the HW. > > However, I completely disagree that a block diagram should desicribe separate registers and equations for combinatorial logic. > > The diagram should be hierarchical based on related behavior, and ultimately broken down into blocks of related behaviors that can be described in a sequential manner (a flow chart). Then I suggest coding clock-cycle-accurate, behavioral RTL models of the blocks (flow charts) from the diagram. I have not seen flow charts used to describe hardware other than sequential functions like state machines. When designing logic, I am typically more concerned with the data paths and often use the block diagrams I described for that. I don't often have much need for flow charts for state machines since I typically code in a way that makes a flow chart redundant. But for newbies, I encourage the use of block diagrams to facilitate the mapping from flow charts to logic. -- Rick From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.42.141 with SMTP id s13mr5850189qae.3.1369297479706; Thu, 23 May 2013 01:24:39 -0700 (PDT) X-Received: by 10.49.4.39 with SMTP id h7mr64374qeh.2.1369297479693; Thu, 23 May 2013 01:24:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no768547qab.0!news-out.google.com!y6ni50967qax.0!nntp.google.com!ch1no768542qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 May 2013 01:24:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=93.93.41.2; posting-account=N5yKXQoAAACmjypJy0tR9bRYrpl47s7a NNTP-Posting-Host: 93.93.41.2 References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: clocked process and sensitivity list From: celine Injection-Date: Thu, 23 May 2013 08:24:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3630 Xref: mx05.eternal-september.org comp.lang.vhdl:6585 Le mercredi 22 mai 2013 20:53:25 UTC+2, Andy a =E9crit=A0: > OK, you implied that both code versions generated the same circuit with r= espect to set/reset, but you did not say whether they had exactly the same = clock enable (feedback mux) logic for the counter. Did they? In the case of only one process, the CE pin is directly driven by f_rx_wr a= lone, but in the equation of the D pin I see my asynchronous reset. In the case of two separated processes, one with clk an rst, the other with= clk only, the D pin has a complicated equation where I don't see my asynch= ronous reset, and the CE pin has also a complicated equation where the asyn= chronous reset doesn't appear. And if I add the initialization on reset of frx_dat_cnt in the one process = above, the SR pin is now driven by my asynchronous reset, the CE pin simply= by f_rx_wr, and the D pin has an equation not so much complicated. I'll go with this one. In fact I used to systematically initialize all my registers on an external= reset for ten years until I had to design an FPGA with multiple digital fi= lters in a virtex 6 at a quite high speed (240MHz) and I found that the res= et line exploded the timing constraints. So I changed my reset strategy to initialize only the signals that needed i= t. Seems that I have gone a little too far this way... You're right about the fact that Xilinx FPGAs cannot merge multiple registe= rs into the same CLB if they have different control signals (clock, reset b= ut I think also clock enable), but I can not find what is the best for the = placer:=20 avoiding local initialization or having all signals with the same controls.= =20 I understood that the need to avoid local initialization was statistical: i= f you have a big design the Xilinx placer will fit it more easily if a good= part of your registers are not initialized because some of the FF resource= s don't have SR pin at all. I hope I'm not mistaken. In the case of my little FSM though I think I should initialize all the reg= isters in my process. From newsfish@newsfish Tue Dec 29 16:42:55 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Colin Paul Gloster Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship Sought Date: Thu, 23 May 2013 11:13:01 +0200 Organization: A noiseless patient Spider Lines: 930 Message-ID: Mime-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="8323328-48355185-1368887451=:23960" Injection-Info: mx05.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="15813"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Nz/GfHU7QWKc0OPu5+rfkcrxsTHcltmPjqWCGL6cS+g==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <20080328124249.A8873@docenti.ing.unipi.it> Content-ID: Return-Receipt-To: Cancel-Lock: sha1:UUZBo2fx053VH5mVKwVcfci5FYY= X-X-Sender: gloster@anapnea.net Xref: mx05.eternal-september.org comp.arch.fpga:19068 comp.lang.vhdl:6586 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-48355185-1368887451=:23960 Content-Type: TEXT/PLAIN; CHARSET=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Content-ID: On March 28th, 2008, I posted to these Usenet newsgroups: |--------------------------------------------------------------------------= ---------------------| |"Ladies (if any actually read comp.lang.vhdl = | |or comp.arch.fpga) and gentlemen, = | | = | |You may have been wondering why I have not = | |been posting much to Usenet and SystemC.org = | |since September 2007. = | | = | |In January 2006 I became a Ph.D. student in = | |the largest University of Pisa but I quit = | |in September 2007 (details follow). I have = | |unsuccessfully tried to apply for a number = | |of Ph.D. scholarships and jobs to replace my = | |sabotaged attempt at a Ph.D. in Pisa, and I = | |do not have much money remaining so now I = | |announce my woe here in the hope that one = | |of you might help me. = | | = | |I had the misfortune to unintentionally but = | |quite clearly empirically disprove a published = | |theory of my main tutor's. I was discouraged to = | |submit a paper for publication which would highlight = | |points similar to those below, and I was too afraid to = | |continue with writing the paper in my spare time = | |before I quit lest that could still be used as a = | |sufficient excuse to expell me. I was also warned = | |that if I would not quit, then my empty refereed = | |publication record would be used as a reason to = | |fail me in the second annual review. I quit in = | |September 2007. = | | = | |In addition to the problems below, = | |Prof. Luca Fanucci forbade me from pointing out = | |in my presentations that high-level SystemC(R) = | |modeling did not prove to be competitive with = | |Verilog. = | | = | |Please feel free to discuss these points on = | |Usenet for yourselves, but if you have = | |anything to say to me (hopefully an offer, = | |but even advice would be welcome) please = | |reply to me directly by writing to = | |Colin Paul Gloster, = | | Via Tosco Romagnola 2461, = | | Titignano, = | | 56023 Cascina (PI), = | | Italy = | |or by emailing to C...@ACM.org = | |but please bear in mind that my Internet = | |access is currently chiefly restricted to = | |approximately three gratis hours in a local = | |library. = | | = | |Yours faithfully, = | |Colin Paul Gloster = | | = | | = | |Table of Contents = | |Introduction to C++ Issues in Pisa = | |An example of where similar, unrelated objects should be refactored into a= single | |hierarchy on Sourceforge = | |Lack of effective inheritance on Sourceforge = | |Unnecessary case branches on Sourceforge = | |A number of bad practices on Sourceforge = | |Miscellaneous C++ Issues in Pisa = | |VHDL Issues in Pisa = | |Bibliography = | | = | |Introduction to C++ Issues in Pisa = | |A non disclosure agreement between myself; my former tutor, Prof. Luca Fan= ucci, | |and his partner, STMicroelectronics, prevents me from mentioning a number = of items | |for a number of years. Fortunately, I am legally at liberty to highlight m= any | |problems which I detected in published source code which was written by = | |STMicroelectronics and is available for gratis on the Internet. My project= in Pisa | |involved using this source code. I had offered to help with that source co= de, but | |despite the large list of flaws which I uncovered, my offer was ignored. I= t is | |trivial to check my list (below) in which I give exact file names and line= | |numbers. I was not permitted to write a paper concerning these issues. Wha= t I | |accidentally uncovered irrefutably contradicted published papers by my tut= or of | |the time (the [Fanucci] entry in the bibliography) and published papers by= his | |partner, STMicroelectronics (the [OCCN2] entry in the bibliography). This = tragic | |incident is another case highlighting that the IEEE allows untrue papers. = It is | |not a sin to not be the best programmer in the World, but they incorrectly= claimed | |in papers that they are highly competent at writing source code in C++. = | | = | | = | | = | |An example of where similar, unrelated objects should be refactored into a= single | |hierarchy on Sourceforge = | |The reader may wish to download the file occn_lib_2.0.1.beta.tar.gz from = | | https://sourceforge.net/project/showfiles.php?group_idt058 = | |and to consult the files occn_lib_2.0.1.beta/include/utils/CQueueObject.n = and | |occn_lib_2.0.1.beta/include/utils/CQueuePtrObjectEv.n therein for what is = | |discussed here. = | | = | |A constructor for a derived class (which e.g. CQueuePtrObjectEv could beco= me in a | |new version) must call a constructor for the base class (which e.g. CQueue= Object | |could become in a new version). Three of the four lines from a constructor= of | |CQueueObject are lexically copied in a constructor of CQueuePtrObjectEv, a= nd the | |counterpart to the remaining line from CQueueObject differs by simply havi= ng an | |array of type T* instead of of type T (but as templates are used everywher= e, a | |pointer to a type is actually a type so perhaps CQueuePtrObjectEv should b= e | |replaced by a future class which we could call "CQueueObjectEv" or even be= tter | |"CQueueEv"). Somewhat similarly, the bodies of the destructors are lexical= ly | |identical; the remove() methods contain identical semantics but differing = | |quantities of braces, but even worse they return an element without expell= ing it | |from the agenda; the method add() of CQueuePtrObjectEv performs identical,= | |lexically copied steps as in the method add() of CQueueObject and after th= ose | |steps has some additional steps which would be more maintainably added as = in "When | |a base-class member function is overridden in a derived class, it is commo= n to | |have the derived-class version call the base-class version and do some add= itional | |work" as written in a C++ book (the entry [Deitel and Deitel] in the = | |bibliography); the get_length() methods are lexically identical and each o= f them | |contains two off by one errors; the methods is_not_empty() are lexically = | |identical; and the methods is_not_full() are lexically identical. = | | = | |diff include/utils/CQueueObject.n include/utils/CQueuePtrObjectEv.n = | |32,33c32,33 = | |< // File: CQueueObject.n = | |< // Created: Fri Jun 14 09:36:43 2002 = | |--- = | |> // File: CQueuePtrObjEv.n = | |> // Created: Tue Jul 2 14:56:24 2002 = | |44c44 = | |< CQueueObject::CQueueObject(N_uint _size) = | |--- = | |> CQueuePtrObjectEv::CQueuePtrObjectEv(N_uint _size, sc_event& _ev) = | |48c48 = | |< data (new (T) [size]) , = | |--- = | |> data (new (T*) [size]) , = | |50,51c50,56 = | |< tail(0) = | |< {} = | |--- = | |> tail(0), = | |> wait(false), = | |> trig_ev(_ev), = | |> delay(0) = | |> { = | |> = | |> } = | |56c61 = | |< CQueueObject::~CQueueObject() = | |--- = | |> CQueuePtrObjectEv::~CQueuePtrObjectEv() = | |66c71 = | |< void CQueueObject::add(T item) = | |--- = | |> void CQueuePtrObjectEv::add(T* ptr) = | |71d75 = | |< { = | |73c77 = | |< } = | |--- = | |> = | |75c79,85 = | |< data[tail]=3Ditem; = | |--- = | |> = | |> data[tail]=3Dptr; = | |> if (wait) = | |> { = | |> trig_ev.notify(delay,SC_SEC); = | |> wait=C3=BAlse; = | |> } = | |81c91 = | |< T CQueueObject::remove() = | |--- = | |> T* CQueuePtrObjectEv::remove() = | |88d97 = | |< { = | |90d98 = | |< } = | |97c105,106 = | |< T CQueueObject::check() = | |--- = | |> inline = | |> N_uint CQueuePtrObjectEv::get_length() const = | |101,106c110 = | |< N_uint tmp_head=3Dhead+1; = | |< if (tmp_head=3D=3Dsize) = | |< { = | |< tmp_head=3D0; = | |< } = | |< return data[tmp_head]; = | |--- = | |> return (tail >=3D head) ? tail -head : tail - head + size; = | |113c117 = | |< N_uint CQueueObject::get_length() const = | |--- = | |> N_uint CQueuePtrObjectEv::is_not_empty() const = | |117c121 = | |< return (tail >=3D head) ? tail -head : tail - head + size; = | |--- = | |> return (tail!=3Dhead); = | |124c128 = | |< N_uint CQueueObject::is_not_empty() const = | |--- = | |> N_uint CQueuePtrObjectEv::is_not_full() const = | |128c132,134 = | |< return (tail!=3Dhead); = | |--- = | |> const N_uint tmp=3D tail+1; = | |> return (tmp=3D=3Dsize) ? (0!=3Dhead) : (tmp!=3Dhead); = | |> = | |135c141 = | |< N_uint CQueueObject::is_not_full() const = | |--- = | |> void CQueuePtrObjectEv::trigger() = | |139,141c145,156 = | |< const N_uint tmp=3D tail+1; = | |< return (tmp=3D=3Dsize) ? (0!=3Dhead) : (tmp!=3Dhead); = | |< = | |--- = | |> wait=3Dtrue; = | |> } = | |> = | |> // }}} = | |> = | |> template = | |> inline = | |> void CQueuePtrObjectEv::set_delay(double _ref) = | |> // {{{ = | |> = | |> { = | |> delay=3D_ref; = | | = | | = | | = | |Lack of effective inheritance on Sourceforge = | |In occn_lib_2.0.1.beta/include/channels/BusBaseChannel.n from STMicroelect= ronics, | |both MasterIf and SlaveIf are subclasses of = | |Msgbox and their respective set_index() methods are almost id= entical | |but were clearly implemented using lexical copying. This is in contrast to= the | |claim in [OCCN1]: "The On-Chip Communication Network (OCCN) proposes an ef= ficient, | |open-source research and development framework for the specification, mode= ling and | |simulation of on-chip communication architectures. OCCN increases the prod= uctivity | |of developing new models for on-chip communication architectures through t= he | |definition of a universal Application Programming Interface (API) and an o= bject- | |oriented C++ library built on top of SystemC. [..] = | | = | |This environment provides several important on-chip network modeling featu= res. | |* Object-oriented design concepts, fully exploiting advantages of this sof= tware | |development paradigm. = | | = | |[..]" The following claim in [OCCN2] is similarly nonsensical: "OCCN focus= es on | |NoC modeling by providing a flexible, state-of-the-art, C++-based framewor= k | |consisting of an open-source, GNU GPL library, built on top of SystemC. OC= CN | |design methodology offers unique features, such as = | |* object-oriented design concepts," and is reminiscent of a comparison in = Embedded | |Systems Conference, 1990 to teenage sex and object oriented programming si= milar to | |"The state of the art of Software Architecture is like teenage sex: it's o= n every- | |body's mind all the time, everyone talks about it all the time (but they d= on't | |really know what they are talking about), everyone thinks everyone else is= doing | |it, the few that are doing it: 1) are doing it poorly, 2) think it will be= better | |next time, and 3) are not practising it safely" reproduced in e.g. [Crocke= r]. | |Conceited delusions of grandeur such as those expressed in [OCCN1,OCCN2] m= ight be | |attributed to electronic engineers having a basis for arrogance more than = a decade | |behind realtime embedded programmers' and justifiably not knowing enough a= bout | |software development, but one of the coauthors of [OCCN1] and [OCCN2] owns= a | |company which allegedly[ISD1]: "Integrated Systems Development S.A. (ISD) = is a | |company established in 1998, active in the domain of Integrated Sy= stems | |(IS) of Guaranteed Quality and Performance. It is an R&D organization = [..]" | |and allegedly[ISD2}:"The ISD software group is dedicated to efficient and = retance_id < 1000000)| | 168 sprintf(tmp_str, "f%u_favg_", instance_id); = | | 169 else if (instance_id >=3D 1000000) { = | | 170 fprintf(stderr, "way too many filenames \n"); = | | 171 OCCN_error_exit("error in stats"); = | | 172 } = | | 173 strcat(string_gen_tbl[BaseStat::F_FREQ_STAT_AVG], t= mp_str); | | 174 = | | 175 ptr =3D string_gen_tbl[BaseStat::F_FREQ_STAT_AVG]; = | | 176 break; = | | 177 = | | 178 case BaseStat::FREQ_STAT_CURR: = | | 179 string_gen_tbl[BaseStat::F_FREQ_STAT_CURR] =3D new = | |char[max_string_size]; = | | 180 if (string_gen_tbl =3D=3D NULL) = | | 181 { = | | 182 fprintf(stderr, "Statistics Error: new string_ge= n_tbl (in | | BaseStat::activate_stats) failed: retry with smaller max_string_size\n")= ; | | 183 OCCN_error_exit("error in stats"); = | | 184 } = | | 185 strcpy(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR], = | |"./stat/"); = | | 186 //strcpy(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR]= +7, | |"fn_fcur_"); = | | 187 if (instance_id < 10) = | | 188 sprintf(tmp_str, "f00000%u_fcur_", instance_id); = | | 189 else if (instance_id < 100) = | | 190 sprintf(tmp_str, "f0000%u_fcur_", instance_id); = | | 191 else if (instance_id < 1000) = | | 192 sprintf(tmp_str, "f000%u_fcur_", instance_id); = | | 193 else if (instance_id < 10000) = | | 194 sprintf(tmp_str, "f00%u_fcur_", instance_id); = | | 195 else if (instance_id < 100000) = | | 196 sprintf(tmp_str, "f0%u_fcur_", instance_id); = | | 197 else if (instance_id < 1000000) = | | 198 sprintf(tmp_str, "f%u_fcur_", instance_id); = | | 199 else if (instance_id >=3D 1000000) { = | | 200 fprintf(stderr, "way too many filenames \n"); = | | 201 OCCN_error_exit("error in stats"); = | | 202 } = | | 203 strcat(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR], = tmp_str); | | 204 = | | 205 ptr =3D string_gen_tbl[BaseStat::F_FREQ_STAT_CURR];= | | 206 break; = | | = | | = | | = | |A number of bad practices on Sourceforge = | |From occn_lib_2.0.1.beta/include/interfaces/Pdu.n: = | | 137 template = | | 138 int Pdu::operator=3D=3D(const Pdu& right) c= onst | | 139 // {{{ = | | 140 = | | 141 { = | | 142 e_last_addr = | |RPdu* SlavePort::receive(sc_time& time_out, bool& received) = | |// {{{ = | | = | |{ = | | if ( (*this)->wait_read_authorization(time_out)=3D=3D1 ) = | | { = | | received =3D true; = | | } = | | else = | | { = | | = | | received =3D false; = | | (*this)->cancel_receiving(); = | | } = | | return (RPdu*)((*this)->get_read_pdu_ptr()); = | | // maybe not valid but need to send back something ! = | |} = | | = | |// }}} = | | = | | = | |VHDL Issues in Pisa = | |I had applied to Pisa in September 2005 when I was living in Ireland, havi= ng just | |returned from my Swedish internship in the Netherlands. I was in contact b= y | |telephone and email with Prof. Luca Fanucci who was in Italy. At home, in = a | |different country from university, I had a subscription to the ACM Digital= | |Library, but instead Prof. Fanucci's publications tend to be on IEEEXplore= for | |which I did not have a subscription. He did email me a publication and I w= as able | |to download an abstract of his from an old MAPLD conference. We establishe= d that | |VHDL would be something I would want to be seriously involved in if I was = to | |secure a scholarship in Pisa. After I secured the scholarship and moved to= Italy, | |he mentioned C++ to me for the first time and he revealed his agenda again= st VHDL. | |However, in time it became clear that he was very good at neither VHDL nor= C++. | |For example in his book of lecture notes entitled "Digital Sistems Design = Using | |VHDL" (he blamed the misspelling of Systems on the publisher) published by= | |Servizio Editoriale Universitario di Pisa, = | |Via Curtatone e Montanara 6, = | |56126 Pisa, = | |Italy, = | |telephone/fax +39 050 540120 = | |dated May 2002, he went against best practice which was standardised in th= e 1990's | |by using a clock edge synchronization coding style which is well-known by = experts | |to result in mismatches between simulation and synthesis. He did this on S= lides | |3.19; 4.12; 4.24 and 4.27. You can check with = | | http://groups.google.com = | |that I already knew how to do this in a less error-prone manner before I m= oved to | |Italy. He has mistakes on Slides 2.14; 4.5; 4.16 and 4.20 (and also misspe= llings | |on other slides). = | | = | |I do not know everything concerning VHDL. I have entirely through my own f= ault | |unintentionally overlooked things. I admit that. I am not perfect. One pro= minent | |example is that though I had looked at the relevant part of the VHDL stand= ards | |concerning implicit initializations, I had not noticed this feature of VHD= L so | |when I discovered that one of our VHDL tools performs implicit initializat= ions I | |was very displeased with it and I deplored this feature to Prof. Luca Fanu= cci. He | |ignored me, as usual, so I eventually proposed as part of the VHDL standar= dization | |process to have implicit initializations illegal. Someone unaffiliated wit= h the largest | |University of Pisa explained the legality and rationale to me on the newsg= roup | |news:comp.lang.vhdl and I retracted my proposal. I felt like a fool and it= became | |clear that no one in the University of Pisa except for myself was interest= ed | |enough in VHDL (our most important language (we never even had a C++ compi= ler and | |almost everyone else in the group in Pisa used only VHDL for the project))= to | |monitor the standardization process and that no one in the University of P= isa was | |an expert of VHDL and that no one in the University of Pisa cared enough a= bout me | |to support me. This inaction of Prof. Luca Fanucci's was extremely inappro= piate. | |Please see my proposal and its retraction on = | | https://bugzilla.mentor.com/show_bug.cgi?id=3D120 = | | = | |Luca Fanucci is fit to be a professor of none of VHDL; C++; C; and SystemC= (R) | |intellectual properties. = | | = | |Also, when I was applying to Pisa, Luca Fanucci showed me a public webpage= of | |STMicroelectronics's concerning the project which he initially assigned me= to. | |After I arrived in Italy and saw the true algorithm, I learnt that the web= page was | |misleading. = | | = | |Bibliography = | |[Crocker] Will Tracz, Quote of the Day attributed to Ron Crocker, Internat= ional | |Conference on Software Engineering 1995 "Window On the World", Volume 1, N= umber 1 | | = | |[Deitel and Deitel] Deitel and Deitel; "C++: How to Program", third editio= n, | |Prentice Hall, 2001, Section 9.6 Overriding Base-Class Members in a Derive= d Class | |and 9.9 Using Constructors and Destructors in Derived Classes = | | = | |[Fanucci] Armaroli; Coppola; Diaz Nava; Fanucci, "High Level Modeling and = | |Simulation of a VDSL Modem in SystemC 2.0 - IPsim", "Proceedings of The 3r= d IEEE | |International Workshop on System-on-Chip for Real-Time Applications", 2003= | | = | |[Grammatikakis] WWW.CS.TEICrete.Gr/english/showdetails.asp?id=3D12 = | | = | |[ISD1] WWW.ISD.Gr/index.htm#top11 = | | = | |[ISD2] WWW.ISD.Gr/index.htm#top23 = | | = | |[OCCN1] Grammatikakis, HTTP://OCCN.Sourceforge.net/coverpg.html, February = 2005 | | = | |[OCCN2] Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giusep= pe | |Maruccia and Francesco Papariello, "OCCN: A Network-On-Chip Modeling and = | |Simulation Framework", Design for Automation and Test in Europe 2004 confe= rence | | = | |[structured programming] Leonard H. Weiner, "The Roots of Structured Progr= amming", | |"ACM SIGCSE Bulletin", February 1978" = | |--------------------------------------------------------------------------= ---------------------| Hello again, During 2006 I accidentally discovered that "Prof." Luca Fanucci of the so-called "University" of Pisa is a coauthor of the fraudulent publication Armaroli et al. (2003). I worked for him during 2006 and he ordered me to prop this fraud up by lying during a presentation about two similar fraudulent publications - Coppola, Locatelli, et al. (2004) and Coppola, Maruccia, et al. (2004) - by other members of the consortium which we were in. He gave me a single-word order: "Lie." I refused and I became a whistleblower. He ruined my life. Dr. Sergio Saponara supported Prof. Luca Fanucci in trying to coerce me to obey Prof. Luca Fanucci. There was a cover-up by the University of Pisa. "Prof." Roberto Saletti was one of the perpetrators of this cover-up. There is now an article by me about this in a scientific journal: Paul Colin de Gloucester (2013): "Referees Often Miss Obvious Errors in Computer and Electronic Publications", "Accountability in Research: Policies and Quality Assurance", 20:3, 143-166, WWW.TandFonline.com/doi/abs/10.1080/08989621.2013.788379 After I have been forced to leave Pisa, I have informed Mr. Werner Steinhoegl of the funding agency the European Commission of the European Union about fraud by Fanucci et al. which Werner Steinhoegl had funded. Werner Steinhoegl did not seem to do anything with this information. Regards, Colin Paul Gloster References ---------- Armaroli, A., M. Coppola, M.D. Nava, and L. Fanucci. 2003. High level modeling and simulation of a VDSL modem in SystemC 2.0-IPsim. In Proceedings, the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003, pp. 175-180. Coppola, M., Curaba, S., Grammatikakis, M. D., Locatelli, R., Maruccia, G., and Papariello, F. (2004). OCCN: A NoC modeling framework for design exploration. Special issue on networks on chip. Journal of Systems Architecture, 50(2-3): 129-163. Coppola, M., Curaba, S., Grammatikakis, M. D., Maruccia, G., and Papariello, F. (2004). OCCN: A network-on-chip modeling and simulation framework. DATE '04: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 174-179. --8323328-48355185-1368887451=:23960-- From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.66.163.97 with SMTP id yh1mr1580536pab.5.1369314113457; Thu, 23 May 2013 06:01:53 -0700 (PDT) X-Received: by 10.49.49.67 with SMTP id s3mr106093qen.29.1369314113001; Thu, 23 May 2013 06:01:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!c5no22848206pbj.1!news-out.google.com!d5ni9411pbl.0!nntp.google.com!c5no22848197pbj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 May 2013 06:01:52 -0700 (PDT) In-Reply-To: <20130522122500.35f14199@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <20130522122500.35f14199@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <78283996-a495-45f0-96e6-8e7b50c8b2ea@googlegroups.com> Subject: Re: abstract type signal From: Andy Injection-Date: Thu, 23 May 2013 13:01:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6587 I agree with Rob, but notify your tool vendor(s) if they do not yet support it(generic types). This will help them prioritize implementation of 2008 features, and let the know that more customers want to use 2008 features. Andy From newsfish@newsfish Tue Dec 29 16:42:55 2015 X-Received: by 10.224.42.141 with SMTP id s13mr6525521qae.3.1369321464412; Thu, 23 May 2013 08:04:24 -0700 (PDT) X-Received: by 10.49.97.130 with SMTP id ea2mr1297105qeb.13.1369321464377; Thu, 23 May 2013 08:04:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t14no446840qam.0!news-out.google.com!y6ni51092qax.0!nntp.google.com!ch1no809829qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 May 2013 08:04:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <518cc1d4$0$3122$ba620e4c@news.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <290cfa44-81a5-40e4-b85f-be9e6d2913d3@googlegroups.com> Subject: Re: clocked process and sensitivity list From: Andy Injection-Date: Thu, 23 May 2013 15:04:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 51 Xref: mx05.eternal-september.org comp.lang.vhdl:6588 It sounds like you are seeing the logic of the feedback mux in the single p= rocess version where you don't reset all registers. There is an easy way to infer different registers with different types of r= eset (or no reset) from a single process, without feedback muxes. The key is to code it such that the reset (whatever kind) has priority over= clocked logic, but is not exlusive of the clocked logic. Here is an exampl= e pattern for defining registers with asynchronous, synchronous, or no rese= t, all in one process, with no feedback muxes" process (arst, clk) is begin if rising_edge(clk) then -- synchronous assignments and control statements here if srst =3D '1' then -- synchronous reset assignments here end if; -- srst end if; -- clk if arst =3D '1' then -- asynchronous reset assignments here end if; -- arst -- don't assign non-reset registers in either reset region end process; The reset assignments override the effects of the synchronous asssignments,= but they do not keep the latter from executing. Thus registers that are no= t reset are not overridden by reset either, and behave as if there were no = reset at all (and therefore need no feedback mux). I should note that having asynchronously reset registers feeding other regi= sters that are not held in reset can cause problems with unsynchronized inp= uts to the non-reset registers. This can be very hard to detect and diagnos= e without gate level simulation and lots of variation in the onset of the a= synchronous reset relative to the clock.=20 All asynchronous reset control signals should be synchronized to each clock= domain for their deasserting edge only. This makes sure that all asynchron= ously reset registers come out of reset on the same clock edge. You also ne= ed to ensure that the STA tool is checking timing on that path. Finally, WRT timing on a heavily used asynchronous (or synchronous) reset s= ignal, you can pipeline the reset (you are synchronizing the deasserting ed= ge aren't you?!), and P&R on some tools can replicate the last pipeline sta= ge(s), creating a "reset tree" to ease timing. If the replication is perfor= med in synthesis, I don't know whether the P&R tool will be able to swap lo= ads between the replicated registers to match a given placement, and you ca= rtainly don't want the synthesis register allocations to drive placement. O= f course, physical synthesis tools will handle this latter issue automatica= lly. Andy From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.174.145 with SMTP id t17mr6676584qaz.4.1369326494588; Thu, 23 May 2013 09:28:14 -0700 (PDT) X-Received: by 10.50.41.104 with SMTP id e8mr2874293igl.5.1369326494518; Thu, 23 May 2013 09:28:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ch1no820879qab.0!news-out.google.com!y6ni51092qax.0!nntp.google.com!ch1no820872qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 May 2013 09:28:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4bb4be78-8d7f-42ff-93fd-29ccc69c3a78@googlegroups.com> Subject: Re: abstract type signal From: kevin.neilson@xilinx.com Injection-Date: Thu, 23 May 2013 16:28:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6589 I had the same experience recently in which I had to make four almost-ident= ical modules so I tried passing in the type as a generic, which looks like = this: entity delay is generic (type DATATYPE); port (... In my notes I see that this was supported by my synthesizer (Synplify Pro) = but not by Modelsim 10.1d, which despite being sold for ridiculous prices, = does not support basic features from a standard from 2008, which if I calcu= late correctly, was FIVE YEARS AGO. Even if this feature is supported, it's not really that great. It would be= preferable to have an unconstrained type, so you could do something like t= his: signal internal_sig : data_in'type(data_in'range); Your other option is to use Verilog. From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.36.66 with SMTP id s2mr8454910qad.6.1369395570944; Fri, 24 May 2013 04:39:30 -0700 (PDT) X-Received: by 10.49.30.105 with SMTP id r9mr1644169qeh.27.1369395570836; Fri, 24 May 2013 04:39:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t14no570447qam.0!news-out.google.com!y6ni51184qax.0!nntp.google.com!ch1no939002qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 May 2013 04:39:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.67.16.222; posting-account=6Oa1xgoAAACoU2eNTUxMK0MofSqxVXRO NNTP-Posting-Host: 109.67.16.222 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> Subject: implementation of traffic light... From: danddad61@gmail.com Injection-Date: Fri, 24 May 2013 11:39:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6590 hi all, i'm new in the area of vhdl. and i need to do a traffic light that turn the red light for 10 second. the yellow light to 4 second and the green light for 2 seconds. it's maybe sound simple program in vhdl. but who can help me and say how to program it. and what is the machine statement for this. thank's all... From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.42.141 with SMTP id s13mr8551847qae.3.1369398863023; Fri, 24 May 2013 05:34:23 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.71.135 with SMTP id v7mr1644324qeu.22.1369398862969; Fri, 24 May 2013 05:34:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!ch1no944597qab.0!news-out.google.com!y6ni51184qax.0!nntp.google.com!ch1no944595qab.0!postnews.google.com!dk8g2000vbb.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 May 2013 05:34:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: dk8g2000vbb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.9.0.11735) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.28) Gecko/20120306 Firefox/3.6.28,gzip(gfe) Message-ID: <724a7958-821a-49ac-818c-5481d91e4bfd@dk8g2000vbb.googlegroups.com> Subject: Re: implementation of traffic light... From: Thomas Stanka Injection-Date: Fri, 24 May 2013 12:34:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6591 On 24 Mai, 13:39, dandda...@gmail.com wrote: > and i need to do a traffic light that turn the red light for 10 second. > the yellow light to 4 second and the green light for 2 seconds. Tell your teacher that no one needs such a ridicoluos bad traffic light. He missed a yellow phase between green and red, together with only 2 sec green this will lead to horrible traffic jams. > it's maybe sound simple program in vhdl. > but who can help me and say how to program it. architecture programm of trafficjam is type traffic_light_t is (red, green, yellow); begin program: process variable traffic_light is traffic_light_type; begin traffic_light := red; wait for 10 sec; traffic_light=yellow; wait for 4 sec; traffic_light = green; wait for 2 sec; end process; > and what is the machine statement for this. > thank's all... You sure you will manage to do the following steps to your master of copy&paste yourself? best regards Thomas From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr2546644qab.1.1369406071294; Fri, 24 May 2013 07:34:31 -0700 (PDT) X-Received: by 10.49.86.98 with SMTP id o2mr1701188qez.4.1369406071203; Fri, 24 May 2013 07:34:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news1.as3257.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!209.85.216.87.MISMATCH!t14no589569qam.0!news-out.google.com!y6ni51288qax.0!nntp.google.com!ch1no958516qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 May 2013 07:34:31 -0700 (PDT) In-Reply-To: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.67.16.222; posting-account=6Oa1xgoAAACoU2eNTUxMK0MofSqxVXRO NNTP-Posting-Host: 109.67.16.222 References: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: implementation of traffic light... From: danddad61@gmail.com Injection-Date: Fri, 24 May 2013 14:34:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6592 Hi Thomas, first of all thank's for the fast reply. i don't know also why he want such a traffic light. about your program... i don't need to initialize an entity at all? something like: entity lights is port (CLK: in STD_LOGIC; GO_GREEN: in STD_LOGIC; GO_RED: in STD_LOGIC; GO_YELLOW: in STD_LOGIC; LIGHT_GREEN: out STD_LOGIC; LIGHT_RED: out STD_LOGIC; LIGHT_YELLOW: out STD_LOGIC); end; and what the circle that the traffic light need to do? when the green light finish he need to go back to be red and so on... how he do that in your code? and how i do it in real? and what about a clk, i don't need to use one for geting a real seconds? thank's dan From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.datemas.de!rt.uk.eu.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: implementation of traffic light... Date: Fri, 24 May 2013 11:01:45 -0700 Organization: Aioe.org NNTP Server Lines: 31 Message-ID: References: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx05.eternal-september.org comp.lang.vhdl:6593 On 5/24/2013 7:34 AM, danddad61@gmail.com wrote: > Hi Thomas, > first of all thank's for the fast reply. > i don't know also why he want such a traffic light. > about your program... > i don't need to initialize an entity at all? > something like: > entity lights is > port (CLK: in STD_LOGIC; > GO_GREEN: in STD_LOGIC; > GO_RED: in STD_LOGIC; > GO_YELLOW: in STD_LOGIC; > LIGHT_GREEN: out STD_LOGIC; > LIGHT_RED: out STD_LOGIC; > LIGHT_YELLOW: out STD_LOGIC); > end; > and what the circle that the traffic light need to do? > when the green light finish he need to go back to be red and so on... > how he do that in your code? and how i do it in real? > and what about a clk, i don't need to use one for geting a real seconds? This is the part where you get to do the work now. Mr Stanka threw you a very generous bone. He probably already has his EE degree. It's time for you to earn yours. I recommend you experiment and iterate using a test bench simulator. That's where you'll find your answers. JJS From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Cascading the attributes Date: Sat, 25 May 2013 22:55:44 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 25 May 2013 19:51:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10595"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fJMFVa4LBTGyMixIo+prLl7vqWiYTKpk=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 Cancel-Lock: sha1:OZc6fph60VKxOYRX8Ilms2KcPqE= Xref: mx05.eternal-september.org comp.lang.vhdl:6594 What is supposed to happen when one invokes boolean'base'base'image(true)'base'base'val(1) or E'SIMPLE_NAME'length or S'transaction'transaction? From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.165.143 with SMTP id i15mr97791qay.0.1369590291478; Sun, 26 May 2013 10:44:51 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.49.67 with SMTP id s3mr990753qen.29.1369590291457; Sun, 26 May 2013 10:44:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no1242045qab.0!news-out.google.com!y6ni51517qax.0!nntp.google.com!ch1no1242034qab.0!postnews.google.com!gb2g2000vbb.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 26 May 2013 10:44:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: gb2g2000vbb.googlegroups.com; posting-host=94.217.229.21; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 94.217.229.21 References: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:21.0) Gecko/20100101 Firefox/21.0,gzip(gfe) Message-ID: <3fd46395-7189-43f4-951a-48eb43a9db57@gb2g2000vbb.googlegroups.com> Subject: Re: implementation of traffic light... From: Thomas Stanka Injection-Date: Sun, 26 May 2013 17:44:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2749 Xref: mx05.eternal-september.org comp.lang.vhdl:6595 On 24 Mai, 16:34, dandda...@gmail.com wrote: > Hi Thomas, > first of all thank's for the fast reply. > i don't know also why he want such a traffic light. > about your program... > i don't need to initialize an entity at all? You always need an entity. Don't expect me to write basics down for you. The code from me is not even syntactically correct. You asked for a program, and I gave you one. It will do what is needed include looping infinite, but you cannot expect this to be simple converted into real hardware. To get real hardware you would need first to learn the difference between a program (software) and a circuit (hardware). If you don't know these differences, and understand why there is a reason to have both possibilities in VHDL you will have a hard time till you have your first own circuit running. If you think about a circuit, you need to think about hardware representations for time, lightbulbs, and so one. But why would this circuit traffic light have some inputs called "go_green"? This is a question to be answered by the guy who invents the system. If you like me to invent your system, you should be able to pay me. Else it will be your task. > and what about a clk, i don't need to use one for geting a real seconds? Yes you will need a source that allows you to tell, when a second has passed. This can be a (precise) clock for your design, or an cyclic pulse that is not used as clock in your design, but represents a clock on system level. bye Thomas From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: implementation of traffic light... Date: Sun, 26 May 2013 20:57:24 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <919fd640-4a09-4645-90ee-788f498d6d58@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 May 2013 00:53:17 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="bc719c76050d4ea985adc17ec073e5e8"; logging-data="3946"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+l+ze9tLI/i/VRSgO3S0Kk" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:TAkL1CHHo+A71esRn0wtWLfkWEo= Xref: mx05.eternal-september.org comp.lang.vhdl:6596 On 5/24/2013 10:34 AM, danddad61@gmail.com wrote: > Hi Thomas, > first of all thank's for the fast reply. > i don't know also why he want such a traffic light. > about your program... > i don't need to initialize an entity at all? > something like: > entity lights is > port (CLK: in STD_LOGIC; > GO_GREEN: in STD_LOGIC; > GO_RED: in STD_LOGIC; > GO_YELLOW: in STD_LOGIC; > LIGHT_GREEN: out STD_LOGIC; > LIGHT_RED: out STD_LOGIC; > LIGHT_YELLOW: out STD_LOGIC); > end; > and what the circle that the traffic light need to do? > when the green light finish he need to go back to be red and so on... > how he do that in your code? and how i do it in real? > and what about a clk, i don't need to use one for geting a real seconds? > > thank's > dan I don't know what grade you will get, but I think your professor should get an F for how poorly he has prepared you for this assignment. If you don't understand VHDL well enough to know what is happening in the program Thomas gave you and what the problems are with using it, there is no chance you will complete this assignment. What book are you using? Where are you in the book. What has been covered in class so far? Here is a hint... "wait for xxx sec;" is not synthesizable in hardware. So you need to think of another way of controlling the timing. If you weren't using an HDL, but were designing this using schematics, how would you control the timing? -- Rick From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes Date: Tue, 28 May 2013 16:12:51 +0300 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 May 2013 13:08:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="12237"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX184C9PTHuWOOADUUXGdN5fWPsOw7qdB54Y=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:rybgxNgL1ouPSNXietQxzFOXYIE= Xref: mx05.eternal-september.org comp.lang.vhdl:6597 and, the most intriguing, val := a'range'high It seems that there is internal range type in VHDL. Although it is not exposed explicitly and, therefore you cannot instantiate objects of this type, I see no rule that forbids testing its attributes this way. Similarly to OOP, where you write object.method(arg), where methods are just functions, tied to the object, I consider the attribute as a function (operators are the other kind of fancy functions). It takes an object and produces a result. I see no objection against cascading function calls. From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr11748602qab.1.1369760462931; Tue, 28 May 2013 10:01:02 -0700 (PDT) X-Received: by 10.49.86.98 with SMTP id o2mr2501578qez.4.1369760462907; Tue, 28 May 2013 10:01:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!p1no1233480qaj.0!news-out.google.com!y6ni51517qax.0!nntp.google.com!ch1no2618688qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 May 2013 10:01:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Subject: Calculating Pulse per minute in a FPGA From: Cory Shol Injection-Date: Tue, 28 May 2013 17:01:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6598 Hi all, Another problem from the two year FPGA newbie. I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. I need to calculate how many pulses per minute of an input to display out of a Seven segment display. I have completed all the user interface stuff and it works fine etc... The problem is with the calculation. I am running at 25 Mhz clock. 40 ns period. Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. The hard part is converting 1500000 counts into a PPM. I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM 60/ (1500000 *(0.00000004))= 1000 ppm Doing division in VHDL seems to be tough. I have one algorithm idea of doing basically the basic of all basics. which is: 60/clkPeriod = 1.5 billion initially do this: newCount <= newCount - count; quotient <= quotient + 1; Then after initial do this: if(newCount >= Count) then newCount <= newcount -count; quotient <= quotient + 1; else finalanswer <= quotient; end if; Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? Thanks Cory From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Calculating Pulse per minute in a FPGA Date: Tue, 28 May 2013 10:19:31 -0700 Organization: Highland Technology, Inc. Lines: 63 Message-ID: <20130528101931.3adad9bd@rg.highlandtechnology.com> References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="7a89dde196082de0e965aec8c036e07b"; logging-data="27565"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+YSd5MYPowdVBWnqnaYhT+" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:67rq1OQtWPEDPqOl4quuX6Yi9N0= Xref: mx05.eternal-september.org comp.lang.vhdl:6599 On Tue, 28 May 2013 10:01:02 -0700 (PDT) Cory Shol wrote: > Hi all, > > Another problem from the two year FPGA newbie. > > > I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. > > I need to calculate how many pulses per minute of an input to display out of a Seven segment display. > > I have completed all the user interface stuff and it works fine etc... > > The problem is with the calculation. > > I am running at 25 Mhz clock. 40 ns period. > > Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. > > Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. > > The hard part is converting 1500000 counts into a PPM. > > I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM > > 60/ (1500000 *(0.00000004))= 1000 ppm > > Doing division in VHDL seems to be tough. > > I have one algorithm idea of doing basically the basic of all basics. > > which is: 60/clkPeriod = 1.5 billion > initially do this: > > newCount <= newCount - count; > quotient <= quotient + 1; > > Then after initial do this: > > if(newCount >= Count) then > newCount <= newcount -count; > quotient <= quotient + 1; > else > finalanswer <= quotient; > end if; > > > Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? > > Thanks > > Cory > > Stupid question: if you're trying to count how many pulses per minute you get, why don't you just block off 1 minute chunks of time, and see how many pulses you get in each chunk? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.59.205 with SMTP id m13mr18093429qah.7.1369766099148; Tue, 28 May 2013 11:34:59 -0700 (PDT) X-Received: by 10.49.95.3 with SMTP id dg3mr407006qeb.41.1369766099080; Tue, 28 May 2013 11:34:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no2629536qab.0!news-out.google.com!y6ni52054qax.0!nntp.google.com!ch1no2629531qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 May 2013 11:34:58 -0700 (PDT) In-Reply-To: <20130528101931.3adad9bd@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> <20130528101931.3adad9bd@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Calculating Pulse per minute in a FPGA From: Cory Shol Injection-Date: Tue, 28 May 2013 18:34:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 127 Xref: mx05.eternal-september.org comp.lang.vhdl:6600 On Tuesday, May 28, 2013 12:19:31 PM UTC-5, Rob Gaddi wrote: > On Tue, 28 May 2013 10:01:02 -0700 (PDT) > > Cory Shol wrote: > > > > > Hi all, > > > > > > Another problem from the two year FPGA newbie. > > > > > > > > > I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. > > > > > > I need to calculate how many pulses per minute of an input to display out of a Seven segment display. > > > > > > I have completed all the user interface stuff and it works fine etc... > > > > > > The problem is with the calculation. > > > > > > I am running at 25 Mhz clock. 40 ns period. > > > > > > Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. > > > > > > Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. > > > > > > The hard part is converting 1500000 counts into a PPM. > > > > > > I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM > > > > > > 60/ (1500000 *(0.00000004))= 1000 ppm > > > > > > Doing division in VHDL seems to be tough. > > > > > > I have one algorithm idea of doing basically the basic of all basics. > > > > > > which is: 60/clkPeriod = 1.5 billion > > > initially do this: > > > > > > newCount <= newCount - count; > > > quotient <= quotient + 1; > > > > > > Then after initial do this: > > > > > > if(newCount >= Count) then > > > newCount <= newcount -count; > > > quotient <= quotient + 1; > > > else > > > finalanswer <= quotient; > > > end if; > > > > > > > > > Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? > > > > > > Thanks > > > > > > Cory > > > > > > > > > > Stupid question: if you're trying to count how many pulses per minute > > you get, why don't you just block off 1 minute chunks of time, and see > > how many pulses you get in each chunk? > > > > -- > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Email address domain is currently out of order. See above to fix. Because The input of the pulse can change at any time. So if it changed within the minute period you wouldn't have the correct PPM. From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr18077975qab.8.1369766188011; Tue, 28 May 2013 11:36:28 -0700 (PDT) X-Received: by 10.49.87.70 with SMTP id v6mr2068755qez.25.1369766187987; Tue, 28 May 2013 11:36:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no2629677qab.0!news-out.google.com!y6ni52054qax.0!nntp.google.com!ch1no2629672qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 May 2013 11:36:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> <20130528101931.3adad9bd@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72a7d3a2-9621-4061-bf0c-3437a7027e40@googlegroups.com> Subject: Re: Calculating Pulse per minute in a FPGA From: Cory Shol Injection-Date: Tue, 28 May 2013 18:36:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6601 On Tuesday, May 28, 2013 1:34:58 PM UTC-5, Cory Shol wrote: > On Tuesday, May 28, 2013 12:19:31 PM UTC-5, Rob Gaddi wrote: > > > On Tue, 28 May 2013 10:01:02 -0700 (PDT) > > > > > > Cory Shol wrote: > > > > > > > > > > > > > Hi all, > > > > > > > > > > > > > > Another problem from the two year FPGA newbie. > > > > > > > > > > > > > > > > > > > > > I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. > > > > > > > > > > > > > > I need to calculate how many pulses per minute of an input to display out of a Seven segment display. > > > > > > > > > > > > > > I have completed all the user interface stuff and it works fine etc... > > > > > > > > > > > > > > The problem is with the calculation. > > > > > > > > > > > > > > I am running at 25 Mhz clock. 40 ns period. > > > > > > > > > > > > > > Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. > > > > > > > > > > > > > > Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. > > > > > > > > > > > > > > The hard part is converting 1500000 counts into a PPM. > > > > > > > > > > > > > > I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM > > > > > > > > > > > > > > 60/ (1500000 *(0.00000004))= 1000 ppm > > > > > > > > > > > > > > Doing division in VHDL seems to be tough. > > > > > > > > > > > > > > I have one algorithm idea of doing basically the basic of all basics. > > > > > > > > > > > > > > which is: 60/clkPeriod = 1.5 billion > > > > > > > initially do this: > > > > > > > > > > > > > > newCount <= newCount - count; > > > > > > > quotient <= quotient + 1; > > > > > > > > > > > > > > Then after initial do this: > > > > > > > > > > > > > > if(newCount >= Count) then > > > > > > > newCount <= newcount -count; > > > > > > > quotient <= quotient + 1; > > > > > > > else > > > > > > > finalanswer <= quotient; > > > > > > > end if; > > > > > > > > > > > > > > > > > > > > > Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? > > > > > > > > > > > > > > Thanks > > > > > > > > > > > > > > Cory > > > > > > > > > > > > > > > > > > > > > > > > > > Stupid question: if you're trying to count how many pulses per minute > > > > > > you get, why don't you just block off 1 minute chunks of time, and see > > > > > > how many pulses you get in each chunk? > > > > > > > > > > > > -- > > > > > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > > > > > Email address domain is currently out of order. See above to fix. > > > > Because The input of the pulse can change at any time. So if it changed within the minute period you wouldn't have the correct PPM. Also it is a requirement to update after every pulse. From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Calculating Pulse per minute in a FPGA Date: Tue, 28 May 2013 19:26:32 -0400 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 May 2013 23:22:29 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="452c4424461ba29acf74e3b7933296f9"; logging-data="4525"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+9ScJWCUe8V0+onXtgLHIc" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Cancel-Lock: sha1:emdrsvbNHCCU37DldQbNl71NR98= Xref: mx05.eternal-september.org comp.lang.vhdl:6602 On 5/28/2013 1:01 PM, Cory Shol wrote: > Hi all, > > Another problem from the two year FPGA newbie. > > > I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. > > I need to calculate how many pulses per minute of an input to display out of a Seven segment display. > > I have completed all the user interface stuff and it works fine etc... > > The problem is with the calculation. > > I am running at 25 Mhz clock. 40 ns period. > > Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. > > Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. > > The hard part is converting 1500000 counts into a PPM. > > I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM > > 60/ (1500000 *(0.00000004))= 1000 ppm > > Doing division in VHDL seems to be tough. > > I have one algorithm idea of doing basically the basic of all basics. > > which is: 60/clkPeriod = 1.5 billion > initially do this: > > newCount<= newCount - count; > quotient<= quotient + 1; > > Then after initial do this: > > if(newCount>= Count) then > newCount<= newcount -count; > quotient<= quotient + 1; > else > finalanswer<= quotient; > end if; > > > Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? Can you say, "look up table"? -- Rick From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Calculating Pulse per minute in a FPGA Date: Tue, 28 May 2013 21:08:19 -0400 Organization: A noiseless patient Spider Lines: 64 Message-ID: References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 29 May 2013 01:04:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d8b60282d4728eb6ad9448dfc385e522"; logging-data="31681"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18pEbCSuqEJFW871RocbTau" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> Cancel-Lock: sha1:AgY2x++at8htD/ovSyM6Le6TT24= Xref: mx05.eternal-september.org comp.lang.vhdl:6603 On 5/28/2013 1:01 PM, Cory Shol wrote: > Hi all, > > Another problem from the two year FPGA newbie. > > > I am working on a new work project that does all this magnificent things and now I am a little stumped on a rather easy to understand problem. > > I need to calculate how many pulses per minute of an input to display out of a Seven segment display. > > I have completed all the user interface stuff and it works fine etc... > > The problem is with the calculation. > > I am running at 25 Mhz clock. 40 ns period. > > Basically I wait for a rising edge of the first pulse and reset my counter. Every rising edge of my 25 Mhz clock I increment the counter until the next rising edge of the pulse. > > Basically the Pulse can be as slow as 15 ppm to 1000 ppm. So if you have a 1000 ppm pulse inputting you would see 1500000 25 Mhz clock counts. > > The hard part is converting 1500000 counts into a PPM. > > I know the math is easy : 60 /[(count)*(Period of Clk)] = PPM > > 60/ (1500000 *(0.00000004))= 1000 ppm > > Doing division in VHDL seems to be tough. > > I have one algorithm idea of doing basically the basic of all basics. > > which is: 60/clkPeriod = 1.5 billion > initially do this: > > newCount <= newCount - count; > quotient <= quotient + 1; > > Then after initial do this: > > if(newCount >= Count) then > newCount <= newcount -count; > quotient <= quotient + 1; > else > finalanswer <= quotient; > end if; > > > Are there any other easy algorithms that are relatively easy to implement? Or a standard way the VHDL community does divisions? > > Thanks > > Cory > > Even updating 1000 times per minute you have a long time to make the calculation. If 1000 ppm is the highest rate, you could even do a simple successive subtraction loop in 1000 cycles or about 40 microseconds with a 25 MHz clock. On the other hand unless you're really short of resources, why not just use a division IP core? I know Xilinx has it in Coregen, and would assume other vendors offer one, too. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: chrisabele Newsgroups: comp.lang.vhdl Subject: Re: Calculating Pulse per minute in a FPGA Date: Tue, 28 May 2013 21:52:30 -0400 Lines: 28 Message-ID: References: <509f8add-bbf3-459a-9976-fa7dcdaf1c8a@googlegroups.com> <20130528101931.3adad9bd@rg.highlandtechnology.com> <72a7d3a2-9621-4061-bf0c-3437a7027e40@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net RlUYdyHigQyFSBt616ITLQG3FQKXhr4DM6RsIelK/1s4HmDsTS Cancel-Lock: sha1:0C1W1/qnKwm1w6XpSB21qsIJ55Y= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <72a7d3a2-9621-4061-bf0c-3437a7027e40@googlegroups.com> Xref: mx05.eternal-september.org comp.lang.vhdl:6604 On 5/28/2013 2:36 PM, Cory Shol wrote: > On Tuesday, May 28, 2013 1:34:58 PM UTC-5, Cory Shol wrote: >> On Tuesday, May 28, 2013 12:19:31 PM UTC-5, Rob Gaddi wrote: >> Stupid question: if you're trying to count how many pulses per minute >> you get, why don't you just block off 1 minute chunks of time, and see >> how many pulses you get in each chunk? >> >>> On Tue, 28 May 2013 10:01:02 -0700 (PDT) >>> Cory Shol wrote: >> >> Because The input of the pulse can change at any time. So if it changed within the minute period you wouldn't have the correct PPM. > > Also it is a requirement to update after every pulse. > If you're display is seven segment then I have to assume it's for people to read. A display that changes at 1KHz (your specified maximum rate) would be very difficult for most people to make sense of. One solution would be to average the PPM values that you collect over some period that's closer to human perception scale and display that. Rob's suggestion of simply accumulating pulses for one minute is a very simple direct way to achieve that. Or you could accumulate pulses for one second and display that value multiplied by 60. You'd have to how to handle the 15 to 60 PPM range, but still the problem would be much easier. As usual starting out with a good specification of what's really needed makes developing a solution more efficient. From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes Date: Wed, 29 May 2013 13:27:32 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 29 May 2013 10:23:14 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13581"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19WaGFmBMhmvVXz13EZ470ngakKK1Nr4Yg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:mzlUHZe/YmSFSkg73ewVM0IwvYU= Xref: mx05.eternal-september.org comp.lang.vhdl:6605 arr : string (5 downto 3); Should arr'range'rightof(5) evaluate to 6 or 4? From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr10969122qab.8.1370159878131; Sun, 02 Jun 2013 00:57:58 -0700 (PDT) X-Received: by 10.49.59.162 with SMTP id a2mr1334956qer.5.1370159878025; Sun, 02 Jun 2013 00:57:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!p1no370541qaj.0!news-out.google.com!y6ni340qax.0!nntp.google.com!ch1no380531qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Jun 2013 00:57:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.176.17.201; posting-account=wzIkQQoAAABfLcu-9n_Sg3nmEfa_4NQk NNTP-Posting-Host: 79.176.17.201 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: A few question about vhdl(clk,signal,etc..) From: natiben27@gmail.com Injection-Date: Sun, 02 Jun 2013 07:57:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 Xref: mx05.eternal-september.org comp.lang.vhdl:6606 hi, i want to know two things about vhdl signal... why to use signal count: STD_LOGIC_VECTOR(3 downto 0); when i use a clock and do counting+1 in the state machine? and for what to configure it 3 downto 0... in addtion for what i use signal at all? thank's nati From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 02 Jun 2013 17:09:39 -0500 Date: Sun, 02 Jun 2013 23:09:39 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-6I6cFg18wpoYtjq/Ja+UX9I5r+44eU+QfdgMOAE/oCCRKHg0HfvHqEKDCUzajVjbpS1ZXr6bltA3Wwr!qNt3X7PjqHTSaC0BVX26Rj45juSHtz71DbClKe1uVTlqNlh+xhSinCoVbHcVJFCDmXrn+0vPZxQ5!op5DvDXXt1jCJI5qDewR6HR5yQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1586 Xref: mx05.eternal-september.org comp.lang.vhdl:6607 On 25/05/13 20:55, valtih1978 wrote: > What is supposed to happen when one invokes > boolean'base'base'image(true)'base'base'val(1) or E'SIMPLE_NAME'length > or S'transaction'transaction? > I imagine things like that should "just work". Of course the prefix to a signal attribute must be a signal, so S'transaction'event works fine as s'transaction returns an implicit signal - but s'event'event doesn't work as s'event returns a boolean value, Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 02 Jun 2013 17:24:04 -0500 Date: Sun, 02 Jun 2013 23:24:03 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 29 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Lq254E+4AobJOzGIysX+dhoZAvn2Ia6sJaKP89jUwv9UIK4m7zdPsXcol49AiwuS9pNIUWQIM4f1C0i!YlHfoqflvishQHwzXLDMeEqx49TkjZdmrtZSRpqN3RhPlfGh8+EughJzoW7LXR4mtLS/epj15IYH!y9qkgGrvdWuQDjcxzu6v0cbrKw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2010 Xref: mx05.eternal-september.org comp.lang.vhdl:6608 On 28/05/13 14:12, valtih1978 wrote: > and, the most intriguing, > > val := a'range'high > > It seems that there is internal range type in VHDL. Although it is not > exposed explicitly and, therefore you cannot instantiate objects of this > type, I see no rule that forbids testing its attributes this way. > > Similarly to OOP, where you write object.method(arg), where methods are > just functions, tied to the object, I consider the attribute as a > function (operators are the other kind of fancy functions). It takes an > object and produces a result. I see no objection against cascading > function calls. > Ranges are defined in 1076-2002 3.1 "Scalar Types". In 14.1 it says that the result type of A'RANGE[(N)] is "The type of the Nth index range of A." so it makes sense that you can use 'HIGH on the result regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 02 Jun 2013 17:26:44 -0500 Date: Sun, 02 Jun 2013 23:26:44 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-cbudmapTy9KdiT4ludmo+uiHbxqUMUQM1Go2pa8kQfK/JlD4AvQ/TFdzt6PqtQiNtGWTc6/i+JuEW4+!KE5/6NrjwpkT5sDIQDnRgw2DG4jpNKMpDsv41/GrwjEYpH7Lv350guYYMWvqCOL6kQRUcAEexIyd!HAuqWyU4ntNFONyKPZak+hEV8g== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1508 Xref: mx05.eternal-september.org comp.lang.vhdl:6609 On 29/05/13 11:27, valtih1978 wrote: > arr : string (5 downto 3); > > Should arr'range'rightof(5) evaluate to 6 or 4? > The standard says arr'range returns a type, i.e. type T is 5 downto 3 For rightof, it says the return value is "The value that is to the right of the parameter in the range of T." so I would expect the value 4. regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: A few question about vhdl(clk,signal,etc..) Date: Sun, 02 Jun 2013 21:29:23 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 3 Jun 2013 01:25:03 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1d8daf3a055262a13f8a7420ca4afbb2"; logging-data="30698"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+4qj2DjVsqZB/V1qZYiVHn" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:6pAmTOKrKH/+hOSUjK274sMEJ4Q= Xref: mx05.eternal-september.org comp.lang.vhdl:6610 On 6/2/2013 3:57 AM, natiben27@gmail.com wrote: > hi, > i want to know two things about vhdl signal... > why to use signal count: STD_LOGIC_VECTOR(3 downto 0); > when i use a clock and do counting+1 in the state machine? > and for what to configure it 3 downto 0... > in addtion for what i use signal at all? > thank's > nati > It sounds like you could use some quality time with a VHDL textbook. Basically you must use a signal if you need to use the value of count outside the process with your state machine. If you don't need to use its value outside this process, you could use a variable instead of a signal, but then you need to understand the difference in the way variables are updated. There's no real reason to use standard_logic_vector for a counter unless you're also placing this on a port of the entity, where you generally avoid other problems by sticking with standard logic / vectors. Otherwise you'd normally use a ranged natural or integer. -- Gabor From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.3.131 with SMTP id 3mr13311643qan.5.1370241220556; Sun, 02 Jun 2013 23:33:40 -0700 (PDT) X-Received: by 10.50.39.84 with SMTP id n20mr1337398igk.13.1370241220481; Sun, 02 Jun 2013 23:33:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ch1no502718qab.0!news-out.google.com!y6ni524qax.0!nntp.google.com!ch1no502715qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Jun 2013 23:33:40 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.173.224.154; posting-account=tnn0sQoAAAB0K8_DGOzZfd64IrrqFI3T NNTP-Posting-Host: 122.173.224.154 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <322f5eaf-d252-4dac-a32c-de9b1293b49f@googlegroups.com> Subject: get accustomed with vhdl 2008 From: Ishaan Wadhwa Injection-Date: Mon, 03 Jun 2013 06:33:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6611 hey i have been learning vhdl from many books.... but as most of hese books cater vhdl 93 and below i am unaware of advancements and also changes in coding methodologies... Can someone please provide me some guide where i can quicly learn vhdl 2008 and also its better if that guide could compare vhdl 2008 with the older versions !!! From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf03.am4!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: get accustomed with vhdl 2008 References: <322f5eaf-d252-4dac-a32c-de9b1293b49f@googlegroups.com> In-Reply-To: <322f5eaf-d252-4dac-a32c-de9b1293b49f@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130602-1, 02/06/2013), Outbound message X-Antivirus-Status: Clean Lines: 14 Message-ID: <9LXqt.36725$Wt5.28231@fx24.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1370245189 86.29.12.221 (Mon, 03 Jun 2013 07:39:49 UTC) NNTP-Posting-Date: Mon, 03 Jun 2013 07:39:49 UTC Organization: virginmedia.com Date: Mon, 03 Jun 2013 08:39:45 +0100 X-Received-Bytes: 1577 Xref: mx05.eternal-september.org comp.lang.vhdl:6612 On 03/06/2013 07:33, Ishaan Wadhwa wrote: > hey i have been learning vhdl from many books.... but as most of hese books cater vhdl 93 and below i am unaware of advancements and also changes in coding methodologies... > > Can someone please provide me some guide where i can quicly learn vhdl 2008 and also its better if that guide could compare vhdl 2008 with the older versions !!! > There are some excellent VHDL2008 video tutorial by Jim Lewis on Mentor's Verification Academy website, I believe registration is free. verificationacademy.com Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.42.141 with SMTP id s13mr14107866qae.3.1370269627160; Mon, 03 Jun 2013 07:27:07 -0700 (PDT) X-Received: by 10.49.97.130 with SMTP id ea2mr1588812qeb.13.1370269627085; Mon, 03 Jun 2013 07:27:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ch1no548839qab.0!news-out.google.com!y6ni654qax.0!nntp.google.com!ch1no548835qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Jun 2013 07:27:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f0c9309-8430-4a13-8a1d-dda6a41e457a@googlegroups.com> Subject: Re: Cascading the attributes From: Andy Injection-Date: Mon, 03 Jun 2013 14:27:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6613 Actually, the string type's index is positive (which is an integer subtype), so arr'range is integer range 5 downto 3; Therefore arr'range'rightof(5) evaluates to an integer value of 4. Andy From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes Date: Mon, 03 Jun 2013 18:16:06 +0300 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 3 Jun 2013 15:11:40 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="3725"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vXDm7Dns/gaqAjKjOIU2nWqniTJMxzf4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:iQeC9epJCWSM0UQohd1FUv0mrIk= Xref: mx05.eternal-september.org comp.lang.vhdl:6614 Thanks for your answers. You is the first one who almost explicitly says that cascading is not prohibited in the LRM and "should just work". I asked this question just because our de-facto standard implementaion, called Modelsim, does not think so. Particularly, he produces compilation error | Prefix (attribute name "range") for attribute "rightof" | is not a type mark for arr'range'rightof(5) whose syntax you have approved. Might be somebody can comment on Modelsim behaviour. From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: get accustomed with vhdl 2008 Date: Mon, 03 Jun 2013 18:19:39 +0300 Organization: A noiseless patient Spider Lines: 5 Message-ID: References: <322f5eaf-d252-4dac-a32c-de9b1293b49f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 3 Jun 2013 15:15:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4965"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/KK8TeosunnqXUDTW8PwVQYoudMJ/Dzyw=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <322f5eaf-d252-4dac-a32c-de9b1293b49f@googlegroups.com> Cancel-Lock: sha1:I+8DaXOZLvqQtviorRv7CbQufuE= Xref: mx05.eternal-september.org comp.lang.vhdl:6615 Google provided me with a link to doulos. They are prefect quality. http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/ Just give me a note if you need anything to google for more. From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 03 Jun 2013 11:26:38 -0500 Date: Mon, 03 Jun 2013 17:26:38 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes References: <5f0c9309-8430-4a13-8a1d-dda6a41e457a@googlegroups.com> In-Reply-To: <5f0c9309-8430-4a13-8a1d-dda6a41e457a@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-kwA09WcnpOl+NlvAg2XeH56gTCdtSPU2lTBdQDsKexU4gaKxGoqrsE+16H33fpnR/vbT5X2BS7si4Kp!GhK74g2fzagYkDZ48BdzMNyn+eD08YBL32ckVRM/Dbv4DCA8d+KGFRWNrIyAllhEgojxr/H/qbfa!0z3pPmEclvVEwxqwHGHGA3j5IA== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1635 Xref: mx05.eternal-september.org comp.lang.vhdl:6616 On 03/06/13 15:27, Andy wrote: > Actually, the string type's index is positive (which is an integer subtype), so > > arr'range is integer range 5 downto 3; > > Therefore arr'range'rightof(5) evaluates to an integer value of 4. > > Andy > Hi Andy, Yes, sorry I forgot the word "integer". Luckily we both agree the answer should be 4! Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!xmission!news.snarked.org!news.he.net!usenetcore.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 03 Jun 2013 11:32:13 -0500 Date: Mon, 03 Jun 2013 17:32:13 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cascading the attributes References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <0K6dnZSfr6WQWDHMnZ2dnUVZ8hCdnZ2d@brightview.co.uk> Lines: 23 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-QdNaZcDtrg3gXU61zCGRWCuBo7WY0SY063nOr+IbezQc9WbBz0gRFysK3yrKtqx50okPvp9fF+/Hh0k!iGBReHUecB/PxnllDaWrj3QzRWOeUCrimsrY3a3TQsuDYM7Y0odQbWWweHVyAfmNmN8oasw3eP6O!cSFP7NRTAdzAwJS3UrCrgZQGjw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1885 Xref: mx05.eternal-september.org comp.lang.vhdl:6617 On 03/06/13 16:16, valtih1978 wrote: > Thanks for your answers. You is the first one who almost explicitly says > that cascading is not prohibited in the LRM and "should just work". I > asked this question just because our de-facto standard implementaion, > called Modelsim, does not think so. Particularly, he produces > compilation error > > | Prefix (attribute name "range") for attribute "rightof" > | is not a type mark > > for arr'range'rightof(5) whose syntax you have approved. > > Might be somebody can comment on Modelsim behaviour. > Oh dear, perhaps I'm wrong - there are clever people writing Modelsim :-) I guess you could ask Modelsim support. Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr14558087qab.8.1370284150892; Mon, 03 Jun 2013 11:29:10 -0700 (PDT) X-Received: by 10.49.116.132 with SMTP id jw4mr1752583qeb.33.1370284150768; Mon, 03 Jun 2013 11:29:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ch1no579867qab.0!news-out.google.com!y6ni654qax.0!nntp.google.com!ch1no579863qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Jun 2013 11:29:10 -0700 (PDT) In-Reply-To: <0K6dnZSfr6WQWDHMnZ2dnUVZ8hCdnZ2d@brightview.co.uk> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <0K6dnZSfr6WQWDHMnZ2dnUVZ8hCdnZ2d@brightview.co.uk> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f53c1c9-e89b-4409-8eec-bacc6c48338a@googlegroups.com> Subject: Re: Cascading the attributes From: Andy Injection-Date: Mon, 03 Jun 2013 18:29:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6618 Alan, Per LRM (2008) 16.2 Predefined attributes, A'range is of kind "range", whereas T'base is of kind "type". Also, the result of A'range is defined as a range of the index type of A, which is not a type itself. So arr'range is just "5 downto 3", not "integer range 5 downto 3". Accordingly, you would not be able to use A'range as follows: variable arr_ndx : arr'range; But you could use: variable arr_ndx : integer range arr'range; To get what was apparently desired from arr'range'rightof(5), you'd probably need to write a function. Andy From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.224.53.198 with SMTP id n6mr15753970qag.2.1370325238921; Mon, 03 Jun 2013 22:53:58 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.95.3 with SMTP id dg3mt8099685qeb.41.1370325238904; Mon, 03 Jun 2013 22:53:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p1no1147334qaj.0!news-out.google.com!y6ni74qax.0!nntp.google.com!ch1no572244qab.0!postnews.google.com!q9g2000vbj.googlegroups.com!not-for-mail Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog,comp.arch.embedded Date: Mon, 3 Jun 2013 22:53:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: q9g2000vbj.googlegroups.com; posting-host=94.67.121.151; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.121.151 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/27.0.1453.94 Safari/537.36,gzip(gfe) Message-ID: <5c8dc98a-f65d-4ed2-b8bc-cc0340256408@q9g2000vbj.googlegroups.com> Subject: [ANN] XMODZ-Fast modulo reduction VHDL IPs From: Nikolaos Kavvadias Injection-Date: Tue, 04 Jun 2013 05:53:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2831 Xref: mx05.eternal-september.org comp.arch.fpga:19092 comp.lang.vhdl:6619 comp.lang.verilog:3503 comp.arch.embedded:31679 The XMODZ IP collection provides fast hardware implementations for the modulo computation on integers. The collection comprises of two distinct IP modules, modk for modulo by a fixed integer constant and modv for modulo by an integer variable. Modulo reduction is widely used in cryptographically-secure systems, for fast pseudo-random number generation and is suitable for RNS (Residue Number System) applications. XMODZ can be used as a ROYALTY-FREE component for use in your projects. Interesting features and characteristics of XMODZ include: - highly-parameterized synchronous architecture - register-pipelined operation with single-cycle throughput - scalable architecture supporting any data bitwidth - 198-230 MHz achieved clock rates for both cores on Xilinx Virtex-6. The XMODZ IPs comprise of the following deliverables: - Documentation in ASCII text, PDF, HTML formats - Vendor-independent VHDL code for both modk and modv - Self-checking testbenches - Configurable multi-precision integer reference C models for test data generation using the public domain "free GMP" library (GMP API- compatible) - Various helper scripts for simulation (GHDL, Modelsim) and synthesis. SPECIAL OFFER! -------------- Any user that will register and download MPRFGEN within 2013 is eligible to ALL of the following: - free updates for the entire lifetime of the product - free email support. Pricing information and sample downloads: http://www.nkavvadias.com/eshop Best regards, Nikolaos Kavvadias Research Scientist Lamia, Fthiotis, Greece http://www.nkavvadias.com http://www.perfeda.gr From newsfish@newsfish Tue Dec 29 16:42:56 2015 X-Received: by 10.66.227.71 with SMTP id ry7mr4477486pac.30.1370365487267; Tue, 04 Jun 2013 10:04:47 -0700 (PDT) X-Received: by 10.49.2.170 with SMTP id 10mr2063042qev.38.1370365486805; Tue, 04 Jun 2013 10:04:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!oz11no3083826pbb.0!news-out.google.com!d5ni18pbl.0!nntp.google.com!oz11no3083824pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Jun 2013 10:04:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.134.166.151; posting-account=ukH30goAAADF7uBVr6qQrGZ-BEXs5KX_ NNTP-Posting-Host: 64.134.166.151 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> Subject: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? From: adam.kimura@googlemail.com Injection-Date: Tue, 04 Jun 2013 17:04:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6620 Hello I am fairly new to VHDL and have hit a wall in my code. Basically, I am wanting to convert a 50% duty cycle frequency signal into a= period with microsecond units. In VHDL, I perform a 1/frequency operation= in order to get the period and then convert it to seconds. I declared the= period as a real type. The problem I have is when I end up with a frequen= cy that creates an infinite decimal for the period calculation (Example: 1/= 3 =3D 0.333333..... )My simulator cannot handle the infinite decimal. Is there a way to limit the precision of a REAL type number in VHDL? Shoul= d I use a floating point? I appreciate the help! From newsfish@newsfish Tue Dec 29 16:42:56 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 04 Jun 2013 14:18:30 -0500 Date: Tue, 04 Jun 2013 20:18:30 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? References: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> In-Reply-To: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-vg2fSykiBdJ+ZvwMFFi7WGOKbVF4F3/jUr6WmHKRLY9AyYuZYy3RZ7N5wzAwL1ZHJbno0hhZ2yMTwAp!A+JWK8Ww2OpSHfev09TyBKfRbbVlDLY7rp1L9l288LG4KgxKRmx/5TToBVqJNRZnUhkarYpbKgQX!Wt4tNjNGAq0qGp+0d3TeiM0sP5Q= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2089 Xref: mx05.eternal-september.org comp.lang.vhdl:6621 On 04/06/13 18:04, adam.kimura@googlemail.com wrote: > Hello > > I am fairly new to VHDL and have hit a wall in my code. > > Basically, I am wanting to convert a 50% duty cycle frequency signal into a period with microsecond units. In VHDL, I perform a 1/frequency operation in order to get the period and then convert it to seconds. I declared the period as a real type. The problem I have is when I end up with a frequency that creates an infinite decimal for the period calculation (Example: 1/3 = 0.333333..... )My simulator cannot handle the infinite decimal. > > Is there a way to limit the precision of a REAL type number in VHDL? Should I use a floating point? I appreciate the help! > That sounds strange. Can you post the code and the error message? To answer you last question, REAL *is* floating point. regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.174.145 with SMTP id t17mr17605939qaz.4.1370390382227; Tue, 04 Jun 2013 16:59:42 -0700 (PDT) X-Received: by 10.49.59.162 with SMTP id a2mr2211017qer.5.1370390382160; Tue, 04 Jun 2013 16:59:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!p1no1453748qaj.0!news-out.google.com!10ni239qax.0!nntp.google.com!ch1no883201qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Jun 2013 16:59:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.93.244.249; posting-account=ukH30goAAADF7uBVr6qQrGZ-BEXs5KX_ NNTP-Posting-Host: 108.93.244.249 References: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> Subject: Re: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? From: adam.kimura@googlemail.com Injection-Date: Tue, 04 Jun 2013 23:59:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 65 Xref: mx05.eternal-september.org comp.lang.vhdl:6622 Hello Alan, I think I got it working. I honestly don't know what happened. I was tryi= ng to re-create the error that I was getting, but it seemed to work fine no= w. Is there a limit on the number of decimal places a REAL type can have? = From what I understood from the error message, the decimal places were inf= inite; which caused the simulation error. I understood this to mean that V= HDL cannot represent such a number beyond a certain number of decimal place= s. In languages like C++, a number like 1/3 cannot be accurately represent= ed since it is 0.3333333.... (re-occurring 3.) I have the situation where = I am dividing 1 by decimal numbers... hence the long decimals.=20 Thanks again for your help. ak On Tuesday, June 4, 2013 3:18:30 PM UTC-4, Alan Fitch wrote: > On 04/06/13 18:04, adam.kimura@googlemail.com wrote: >=20 > > Hello >=20 > >=20 >=20 > > I am fairly new to VHDL and have hit a wall in my code. >=20 > >=20 >=20 > > Basically, I am wanting to convert a 50% duty cycle frequency signal in= to a period with microsecond units. In VHDL, I perform a 1/frequency opera= tion in order to get the period and then convert it to seconds. I declared= the period as a real type. The problem I have is when I end up with a fre= quency that creates an infinite decimal for the period calculation (Example= : 1/3 =3D 0.333333..... )My simulator cannot handle the infinite decimal. >=20 > >=20 >=20 > > Is there a way to limit the precision of a REAL type number in VHDL? S= hould I use a floating point? I appreciate the help! >=20 > >=20 >=20 >=20 >=20 > That sounds strange. >=20 >=20 >=20 > Can you post the code and the error message? >=20 >=20 >=20 > To answer you last question, REAL *is* floating point. >=20 >=20 >=20 > regards >=20 > Alan >=20 >=20 >=20 > --=20 >=20 > Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? Date: Tue, 04 Jun 2013 21:03:30 -0400 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Jun 2013 00:59:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="803eaee5f1c66902ef50fa2b579214f2"; logging-data="31428"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+pCsHq6yjPz8C3VX3TmA+R" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> Cancel-Lock: sha1:0MkYriAEuduyccELuu6L9Ax+dVs= Xref: mx05.eternal-september.org comp.lang.vhdl:6623 Yes, the REAL data type in VHDL has limited precision just like most data types in programming languages. I'm not sure what error you might have seen. I can't think of anything in VHDL that would have a problem with your use of a REAL data type unless you were trying to synthesize it. To turn 1/3 into a real number you must first convert the 1 and the 3 into reals and then divide them as real. No, it won't give you exactly 1/3, but it will not give you an error. I think the error must have been related to how you were trying to convert them. Rick On 6/4/2013 7:59 PM, adam.kimura@googlemail.com wrote: > Hello Alan, > > I think I got it working. I honestly don't know what happened. I was trying to re-create the error that I was getting, but it seemed to work fine now. Is there a limit on the number of decimal places a REAL type can have? From what I understood from the error message, the decimal places were infinite; which caused the simulation error. I understood this to mean that VHDL cannot represent such a number beyond a certain number of decimal places. In languages like C++, a number like 1/3 cannot be accurately represented since it is 0.3333333.... (re-occurring 3.) I have the situation where I am dividing 1 by decimal numbers... hence the long decimals. > > Thanks again for your help. > > ak > > > On Tuesday, June 4, 2013 3:18:30 PM UTC-4, Alan Fitch wrote: >> On 04/06/13 18:04, adam.kimura@googlemail.com wrote: >> >>> Hello >> >>> >> >>> I am fairly new to VHDL and have hit a wall in my code. >> >>> >> >>> Basically, I am wanting to convert a 50% duty cycle frequency signal into a period with microsecond units. In VHDL, I perform a 1/frequency operation in order to get the period and then convert it to seconds. I declared the period as a real type. The problem I have is when I end up with a frequency that creates an infinite decimal for the period calculation (Example: 1/3 = 0.333333..... )My simulator cannot handle the infinite decimal. >> >>> >> >>> Is there a way to limit the precision of a REAL type number in VHDL? Should I use a floating point? I appreciate the help! >> >>> >> >> >> >> That sounds strange. >> >> >> >> Can you post the code and the error message? >> >> >> >> To answer you last question, REAL *is* floating point. >> >> >> >> regards >> >> Alan >> >> >> >> -- >> >> Alan Fitch > -- Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.53.198 with SMTP id n6mr17929538qag.2.1370404050481; Tue, 04 Jun 2013 20:47:30 -0700 (PDT) X-Received: by 10.49.2.228 with SMTP id 4mr2261017qex.3.1370404050462; Tue, 04 Jun 2013 20:47:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no911545qab.0!news-out.google.com!y6ni243qax.0!nntp.google.com!ch1no911542qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Jun 2013 20:47:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=174.105.250.126; posting-account=ukH30goAAADF7uBVr6qQrGZ-BEXs5KX_ NNTP-Posting-Host: 174.105.250.126 References: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <114cb2a1-35d8-4e6b-8aa0-2ed66ab99b82@googlegroups.com> Subject: Re: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? From: adam.kimura@googlemail.com Injection-Date: Wed, 05 Jun 2013 03:47:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 171 Xref: mx05.eternal-september.org comp.lang.vhdl:6624 Thank you Rick... very helpful information. Thanks for taking the time to = respond. I sincerely appreciate it! Best, Adam. On Tuesday, June 4, 2013 9:03:30 PM UTC-4, rickman wrote: > Yes, the REAL data type in VHDL has limited precision just like most=20 >=20 > data types in programming languages. I'm not sure what error you might= =20 >=20 > have seen. I can't think of anything in VHDL that would have a problem= =20 >=20 > with your use of a REAL data type unless you were trying to synthesize=20 >=20 > it. To turn 1/3 into a real number you must first convert the 1 and the= =20 >=20 > 3 into reals and then divide them as real. No, it won't give you=20 >=20 > exactly 1/3, but it will not give you an error. >=20 >=20 >=20 > I think the error must have been related to how you were trying to=20 >=20 > convert them. >=20 >=20 >=20 > Rick >=20 >=20 >=20 >=20 >=20 >=20 >=20 > On 6/4/2013 7:59 PM, adam.kimura@googlemail.com wrote: >=20 > > Hello Alan, >=20 > > >=20 > > I think I got it working. I honestly don't know what happened. I was = trying to re-create the error that I was getting, but it seemed to work fin= e now. Is there a limit on the number of decimal places a REAL type can ha= ve? From what I understood from the error message, the decimal places were= infinite; which caused the simulation error. I understood this to mean th= at VHDL cannot represent such a number beyond a certain number of decimal p= laces. In languages like C++, a number like 1/3 cannot be accurately repre= sented since it is 0.3333333.... (re-occurring 3.) I have the situation wh= ere I am dividing 1 by decimal numbers... hence the long decimals. >=20 > > >=20 > > Thanks again for your help. >=20 > > >=20 > > ak >=20 > > >=20 > > >=20 > > On Tuesday, June 4, 2013 3:18:30 PM UTC-4, Alan Fitch wrote: >=20 > >> On 04/06/13 18:04, adam.kimura@googlemail.com wrote: >=20 > >> >=20 > >>> Hello >=20 > >> >=20 > >>> >=20 > >> >=20 > >>> I am fairly new to VHDL and have hit a wall in my code. >=20 > >> >=20 > >>> >=20 > >> >=20 > >>> Basically, I am wanting to convert a 50% duty cycle frequency signal = into a period with microsecond units. In VHDL, I perform a 1/frequency ope= ration in order to get the period and then convert it to seconds. I declar= ed the period as a real type. The problem I have is when I end up with a f= requency that creates an infinite decimal for the period calculation (Examp= le: 1/3 =3D 0.333333..... )My simulator cannot handle the infinite decimal. >=20 > >> >=20 > >>> >=20 > >> >=20 > >>> Is there a way to limit the precision of a REAL type number in VHDL? = Should I use a floating point? I appreciate the help! >=20 > >> >=20 > >>> >=20 > >> >=20 > >> >=20 > >> >=20 > >> That sounds strange. >=20 > >> >=20 > >> >=20 > >> >=20 > >> Can you post the code and the error message? >=20 > >> >=20 > >> >=20 > >> >=20 > >> To answer you last question, REAL *is* floating point. >=20 > >> >=20 > >> >=20 > >> >=20 > >> regards >=20 > >> >=20 > >> Alan >=20 > >> >=20 > >> >=20 > >> >=20 > >> -- >=20 > >> >=20 > >> Alan Fitch >=20 > > >=20 >=20 >=20 >=20 >=20 > --=20 >=20 >=20 >=20 > Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 05 Jun 2013 17:52:25 -0500 Date: Wed, 05 Jun 2013 23:52:25 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: HELP! VHDL real TYPE produces infinite decimal. How to approximate or reduce precision? References: <121aea8b-67e7-4bbf-bbe4-ff938cc9a00a@googlegroups.com> <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> In-Reply-To: <21fff6be-9133-4527-9123-db4b62fe8967@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <04OdnXrQaMG0XDLMnZ2dnUVZ7vydnZ2d@brightview.co.uk> Lines: 69 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-6SQL3w0nU/NdyJ385+QuQm3i/DTu4ZJ3SY7kv03nOBSYrh6ZoGEBLdlvxkiygXNDnataPvNpI5dETHR!PKqtxTFwaV+Pihh5XmIUKvD6j0/xg5tQjHJzMxfVXsr2fmotVwRQRW4e7ECorhpV+kpvAFpmFHYG!FbGx9jfhDbdIVzEjf7EbXYxmIu0= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3641 Xref: mx05.eternal-september.org comp.lang.vhdl:6625 On 05/06/13 00:59, adam.kimura@googlemail.com wrote: > Hello Alan, > > I think I got it working. I honestly don't know what happened. I was trying to re-create the error that I was getting, but it seemed to work fine now. Is there a limit on the number of decimal places a REAL type can have? From what I understood from the error message, the decimal places were infinite; which caused the simulation error. I understood this to mean that VHDL cannot represent such a number beyond a certain number of decimal places. In languages like C++, a number like 1/3 cannot be accurately represented since it is 0.3333333.... (re-occurring 3.) I have the situation where I am dividing 1 by decimal numbers... hence the long decimals. > > Thanks again for your help. When I'm teaching VHDL courses, I sometimes joke that we need CCTV on every keyboard so when people say "oh, it works now!", I could just play back the tape to find out exactly what they typed :-) >From VHDL 2002 onwards (I think - or was it VHDL 93?) REAL was defined to be IEEE P754 - in earlier versions of VHDL it was just guaranteed to have at least a certain range and precision (which I can't recall) regards Alan > > ak > > > On Tuesday, June 4, 2013 3:18:30 PM UTC-4, Alan Fitch wrote: >> On 04/06/13 18:04, adam.kimura@googlemail.com wrote: >> >>> Hello >> >>> >> >>> I am fairly new to VHDL and have hit a wall in my code. >> >>> >> >>> Basically, I am wanting to convert a 50% duty cycle frequency signal into a period with microsecond units. In VHDL, I perform a 1/frequency operation in order to get the period and then convert it to seconds. I declared the period as a real type. The problem I have is when I end up with a frequency that creates an infinite decimal for the period calculation (Example: 1/3 = 0.333333..... )My simulator cannot handle the infinite decimal. >> >>> >> >>> Is there a way to limit the precision of a REAL type number in VHDL? Should I use a floating point? I appreciate the help! >> >>> >> >> >> >> That sounds strange. >> >> >> >> Can you post the code and the error message? >> >> >> >> To answer you last question, REAL *is* floating point. >> >> >> >> regards >> >> Alan >> >> >> >> -- >> >> Alan Fitch > -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.165.143 with SMTP id i15mr20174426qay.0.1370482337073; Wed, 05 Jun 2013 18:32:17 -0700 (PDT) X-Received: by 10.49.85.234 with SMTP id k10mr782144qez.17.1370482337050; Wed, 05 Jun 2013 18:32:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no1717489qab.0!news-out.google.com!y6ni465qax.0!nntp.google.com!ch1no1717488qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Jun 2013 18:32:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> Subject: 2 counters, counting states of Bit stream From: brandon.spiteri@gmail.com Injection-Date: Thu, 06 Jun 2013 01:32:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3938 Xref: mx05.eternal-september.org comp.lang.vhdl:6626 I need to implement 2 counters that counts 1's and 0's of an incoming bit stream. However I have a problem that not even the clock is generated on ModelSim and all the signals are labeled as 'no data'. Is there a problem in my code or is it related to some configuration or settings? This is my code; --bit_counter.vhd LIBRARY ieee; -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; entity bit_counter is port(Start : in std_logic := '0' ; --was in Reset : in std_logic := '1'; Clock : in std_logic := '0'; Bit_stream : in std_logic := '0'; Q_H, Q_L : out std_logic_vector (3 downto 0) ); end entity bit_counter; architecture RTL of bit_counter is --type state_type is (IDLE, Bit_is_high, Bit_is_low); --signal initBitH, initBitL, BitH, BitL : std_logic; signal cnt_L, cnt_H : integer range 0 to 15; begin count: process(Start, Reset, Clock, Bit_stream, cnt_L, cnt_H) begin Q_H <= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); Q_L <= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); if(Reset = '0') then cnt_H <= 0; cnt_L <= 0; elsif (Start = '1') then if(rising_edge(Clock)) then if (Bit_stream = '1') then cnt_H <= cnt_H + 1; cnt_L <= cnt_L; elsif (Bit_stream = '0') then Cnt_H <= Cnt_H; Cnt_L <= Cnt_L + 1; end if; end if; end if; end process; end architecture RTL; --bit_counter_test.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity bit_counter_test is end Entity bit_counter_test; Architecture behavioral of bit_counter_test is Signal Bit_stream, Clock : std_logic := '0'; Signal Reset_count, Start_count : std_logic := '1'; Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); begin UUT : entity work.bit_counter port map ( Bit_stream => Bit_stream, Start => Start_count, Reset => Reset_count, Clock => Clock); CLK_process :process begin for C in 30 downto 0 loop Clock <= NOT Clock after 5ns; end loop; end process; Signals : process Begin for I in 30 downto 0 loop wait for 10 ns; Start_count <= '1'; Reset_count <= '1'; Bit_stream <= '0'; end loop ; wait for 10 ns; for J in 30 downto 0 loop wait for 10 ns; Start_count <= '1'; Reset_count <= '1'; Bit_stream <= '1'; end loop ; wait; end process; end Architecture behavioral; In the past I already managed to simulate combinational logic with model sim so clock wasn't involved. It seams that the problem is I am not using the clock correctly.. From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.165.143 with SMTP id i15mr20506329qay.0.1370496375340; Wed, 05 Jun 2013 22:26:15 -0700 (PDT) X-Received: by 10.49.107.234 with SMTP id hf10mr2718919qeb.21.1370496375304; Wed, 05 Jun 2013 22:26:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p1no2708134qaj.0!news-out.google.com!y6ni784qax.0!nntp.google.com!ch1no2145300qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Jun 2013 22:26:15 -0700 (PDT) In-Reply-To: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: goouse99@gmail.com Injection-Date: Thu, 06 Jun 2013 05:26:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 6953 Xref: mx05.eternal-september.org comp.lang.vhdl:6627 Am Donnerstag, 6. Juni 2013 03:32:16 UTC+2 schrieb Brandon Spiteri: > I need to implement 2 counters that counts 1's and 0's of an incoming bit stream. > > However I have a problem that not even the clock is generated on ModelSim and all the signals > > are labeled as 'no data'. Is there a problem in my code or is it related to some configuration or settings? > > > > This is my code; > > > > --bit_counter.vhd > > > > LIBRARY ieee; > > -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions > > use ieee.std_logic_1164.all; > > > > -- SIGNED and UNSIGNED types, and relevant functions > > use ieee.numeric_std.all; > > > > > > entity bit_counter is > > > > port(Start : in std_logic := '0' ; --was in > > Reset : in std_logic := '1'; > > Clock : in std_logic := '0'; > > Bit_stream : in std_logic := '0'; > > > > Q_H, Q_L : out std_logic_vector (3 downto 0) > > ); > > > > > > end entity bit_counter; > > > > architecture RTL of bit_counter is > > > > --type state_type is (IDLE, Bit_is_high, Bit_is_low); > > > > --signal initBitH, initBitL, BitH, BitL : std_logic; > > signal cnt_L, cnt_H : integer range 0 to 15; > > > > > > begin > > > > count: process(Start, Reset, Clock, Bit_stream, cnt_L, cnt_H) > > > > begin > > > > Q_H <= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); > > Q_L <= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); > > > > if(Reset = '0') then > > cnt_H <= 0; > > cnt_L <= 0; > > > > elsif (Start = '1') then > > if(rising_edge(Clock)) then > > > > if (Bit_stream = '1') then > > cnt_H <= cnt_H + 1; > > cnt_L <= cnt_L; > > elsif (Bit_stream = '0') then > > Cnt_H <= Cnt_H; > > Cnt_L <= Cnt_L + 1; > > end if; > > end if; > > end if; > > > > > > > > end process; > > > > end architecture RTL; > > > > --bit_counter_test.vhd > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > use ieee.std_logic_unsigned.all; > > > > entity bit_counter_test is > > end Entity bit_counter_test; > > > > Architecture behavioral of bit_counter_test is > > > > Signal Bit_stream, Clock : std_logic := '0'; > > Signal Reset_count, Start_count : std_logic := '1'; > > Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); > > > > begin > > > > UUT : entity work.bit_counter > > port map ( > > > > Bit_stream => Bit_stream, > > Start => Start_count, > > Reset => Reset_count, > > Clock => Clock); > > > > > > CLK_process :process > > begin > > for C in 30 downto 0 loop > > Clock <= NOT Clock after 5ns; > > end loop; > > end process; > > > > Signals : process > > > > Begin > > > > for I in 30 downto 0 loop > > wait for 10 ns; > > Start_count <= '1'; > > Reset_count <= '1'; > > Bit_stream <= '0'; > > > > > > end loop ; > > > > wait for 10 ns; > > > > for J in 30 downto 0 loop > > wait for 10 ns; > > Start_count <= '1'; > > Reset_count <= '1'; > > Bit_stream <= '1'; > > > > end loop ; > > > > wait; > > end process; > > > > > > > > end Architecture behavioral; > > > > In the past I already managed to simulate combinational logic with model sim so clock wasn't involved. It seams that the problem is I am not using the clock correctly.. Hi Brandon. so many loops... you may end up in a knot. :-) Think about what you are doing in your clock process: You have a signal assignment that gets overwritten a number of times in the loop. The after statement will just add one event to the event list, but this is not accumulating. It will just be overwritten. Instead you may use this: Clock <= NOT Clock; wait for 5ns; Hint: The loops in your stimuli process can be simplified. after you set some variable you can just use wait for 30*10ns; -- 30 can be replaced by any other number. To avoid problems that may arise when you have signal changes on the rising clock edge, you can either use an initial delay that puts the signal chanses clearly out of phase : e.g. wait for 3 ns; -- put this in the beginning of your stimuli list. There are other methods like implementing a clock counter and using a synchronous process with a case to select the time for signal assignments: sig1 <= '0'; --default assignment case clockcount is when 5 => sig1<= '1'; when 7 to 9 => sig1<= '1'; -- and so on Another thing: aside from the asynchronous reset you shouldn't have statements outside the synchronous parts. The assignments for Q_L and Q_H can be placed outside the process, thus becoming concurrent assignments. elsif (Start = '1') then if(rising_edge(Clock)) then should be rewritten as: elsif(rising_edge(Clock)) then if (Start = '1') then Ranged integers work well, but there may come a time where you want to handle more than 32 bits. While you are using numeric_std anyway you could also declare the counting signals like this: signal cnt_L, cnt_H : unsigned(3 downto 0); This way your type conversions become shorter and you never get into the hazzle of "integer overflow errors". The unsigned type would simply roll over to 0. Still adding integers to unsigned type signals works, so no further code changes are needed. Have a nice simulation Eilert From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr21557270qab.1.1370534503993; Thu, 06 Jun 2013 09:01:43 -0700 (PDT) X-Received: by 10.49.87.70 with SMTP id v6mr2817778qez.25.1370534503939; Thu, 06 Jun 2013 09:01:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no2638435qab.0!news-out.google.com!10ni1106qax.0!nntp.google.com!ch1no2638431qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Jun 2013 09:01:43 -0700 (PDT) In-Reply-To: <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Thu, 06 Jun 2013 16:01:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6628 Thanks a lot for your help. I managed to simulate the test bench and I got what I wanted. Now I need to implement this on an FPGA. I have the board driver and I modified it accordingly like I did for other small projects. My friend told me that to implement it on an FPGA, the vhdl code needs some minor tweaking but I do not know what he was referring to. In the board driver I used debouncing for the 2 tact switches; Bit_stream and clock. Can you guide me what tweaking is needed? thanks This is my code; --bit_counter.vhd LIBRARY ieee; -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; entity bit_counter is port(Start : in std_logic := '0' ; --was in Reset : in std_logic := '1'; Clock : in std_logic := '0'; Bit_stream : in std_logic := '0'; Q_H, Q_L : out std_logic_vector (3 downto 0) := (others => '0') ); end entity bit_counter; architecture RTL of bit_counter is signal cnt_L, cnt_H : integer range 0 to 15; begin Q_H <= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); Q_L <= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); count: process(Start, Reset, Clock, Bit_stream, cnt_L, cnt_H) begin if(Reset = '0' ) then cnt_H <= 0; cnt_L <= 0; elsif (rising_edge(Clock)) then if(Start = '1') then if (Bit_stream = '1') then cnt_H <= cnt_H + 1 ; cnt_L <= cnt_L ; elsif (Bit_stream = '0') then Cnt_L <= Cnt_L + 1 ; Cnt_H <= Cnt_H ; end if; end if; end if; end process; end architecture RTL; --bit_counter_test.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity bit_counter_test is end Entity bit_counter_test; Architecture behavioral of bit_counter_test is Signal Bit_stream, ext_Clock : std_logic := '0'; Signal Reset_count, Start_count : std_logic := '1'; Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); Signal Endsim : std_logic := '0'; begin UUT : entity work.bit_counter port map ( Bit_stream => Bit_stream, Start => Start_count, Reset => Reset_count, Clock => ext_Clock, Q_L => Q_L, Q_H => Q_H); CLK_process :process begin if(EndSim = '0') then ext_Clock <= NOT ext_Clock; wait for 2ns; end if; end process; Signals : process Begin wait for 0.5 ns; Start_count <= '1'; Reset_count <= '1'; for I in 15 downto 0 loop Bit_stream <= '1'; wait for 4 ns; Bit_stream <= '0'; wait for 4 ns; end loop ; EndSim <= '1'; wait; end process; end Architecture behavioral; --boarddriver.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.QuantumBaseSupport.all; entity BoardDriver is Port ( BUTTON : in STD_LOGIC_VECTOR(3 downto 0); DIP : in STD_LOGIC_VECTOR(7 downto 0); RESET : in STD_LOGIC; --Active Low CLK0 : in STD_LOGIC; --20MHz input CLK2 : in STD_LOGIC; -- Output ports COM : out STD_LOGIC_VECTOR(3 downto 0); FND_EN : out STD_LOGIC; LED : out STD_LOGIC_VECTOR(7 downto 0); SEGMENTS : out STD_LOGIC_VECTOR(7 downto 0); EXPANSION : out STD_LOGIC_VECTOR(26 downto 0) ); end BoardDriver; architecture RTL of BoardDriver is alias Button1 is BUTTON(0); alias Button2 is BUTTON(1); alias Button3 is BUTTON(2); alias Button4 is BUTTON(3); alias DIP1 is DIP(0); alias DIP2 is DIP(1); alias DIP3 is DIP(2); alias DIP4 is DIP(3); alias DIP5 is DIP(4); alias DIP6 is DIP(5); alias DIP7 is DIP(6); alias DIP8 is DIP(7); alias LED1 is LED(0); alias LED2 is LED(1); alias LED3 is LED(2); alias LED4 is LED(3); alias LED5 is LED(4); alias LED6 is LED(5); alias LED7 is LED(6); alias LED8 is LED(7); signal ButtonDB_stream : std_logic; signal ButtonDB_clk : std_logic; begin EXPANSION <= (others => 'Z'); DeBounce_stream : entity work.SwDebounce port map( Clock => CLK0, Reset => Reset, Input => Button1, Debounced_out => ButtonDB_stream ); DeBounce_clk : entity work.SwDebounce port map( Clock => CLK0, Reset => Reset, Input => Button1, Debounced_out => ButtonDB_clk ); Count_Bits: entity work.bit_counter Port map( Reset => Reset, Clock => ButtonDB_clk, Bit_stream => ButtonDB_stream, Start => DIP1, Q_L => LED (3 downto 0), Q_H => LED (7 downto 4) ); end architecture RTL; From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.53.198 with SMTP id n6mr21747652qag.2.1370541916153; Thu, 06 Jun 2013 11:05:16 -0700 (PDT) X-Received: by 10.49.27.200 with SMTP id v8mr608221qeg.22.1370541916118; Thu, 06 Jun 2013 11:05:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no2711873qab.0!news-out.google.com!10ni1106qax.0!nntp.google.com!ch1no2711872qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Jun 2013 11:05:15 -0700 (PDT) In-Reply-To: <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Andy Injection-Date: Thu, 06 Jun 2013 18:05:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6629 A few more tips... General: You don't need () around conditions in if-statements. bit_counter: Remove all but clock and reset from sensitivity list. Remove assignments to self for clk_L and Clk_H. You can combine if-statements for rising_edge() and start: if rising_edge(clock) and start = '1' then Testbench: Insert an "else wait;" statement before "end if;" in your clock driver process. This keeps it from running in an endless, zero-delay loop when endsim becomes '1'. But I usually drive the clock from a concurrent assignment: ext_clock <= not ext_clock after 2 ns when endsim = '0'; Pace the testbench by using "wait for falling_edge(clk);" instead of 'wait for 4 ns;" This keeps it syncrhonized to the clock no matter what. Andy From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2 counters, counting states of Bit stream Date: Thu, 06 Jun 2013 17:25:00 -0400 Organization: A noiseless patient Spider Lines: 250 Message-ID: References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 6 Jun 2013 21:20:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="af17bf98bc6f01ff515486b6a43321b0"; logging-data="22180"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18656ITL3lPhNT60z8kUhqE" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> Cancel-Lock: sha1:mJgITMIkyqOUc/4r4fTKPJq/zhY= Xref: mx05.eternal-september.org comp.lang.vhdl:6630 On 6/6/2013 12:01 PM, Brandon Spiteri wrote: > Thanks a lot for your help. I managed to simulate the test bench and I got what I wanted. > > Now I need to implement this on an FPGA. I have the board driver and I modified it accordingly like > I did for other small projects. > > My friend told me that to implement it on an FPGA, the vhdl code needs some minor tweaking but I do not know what he was referring to. In the board driver I used debouncing for the 2 tact switches; Bit_stream and clock. > > Can you guide me what tweaking is needed? thanks Tweaking for synthesis after simulation is not a good idea. If changes are made to the code to be synthesized, it would need to be simulated again to make sure nothing functional has changed. The only thing I see that should be changed is your sensitivity list that contains not only the clock and the async reset, but other inputs to the process. These should not be included in the sensitivity list because of how the sensitivity list works. Any change to any of the signals in the list cause the process to run. There are cases where this will cause the simulation results to be different from the way the synthesized hardware to work. I think I see one mistake in your code. You use Button1 as input to both debounce circuits. I assume one should be Button1 and the other Button2? I wouldn't change the use of parens in IF statements. They clearly delineate the expression being evaluated just like using a period at the end of a sentence. I also wouldn't worry about using assignments of signals to themselves when you want the value of a FF to remain unchanged. This is redundant since if nothing is specified it is assumed that the signal will hold a value, but specifying it can make some code more clear. In other words, it is a judgement call by the author and I would never criticize this. Rick > This is my code; > > --bit_counter.vhd > > LIBRARY ieee; > -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions > use ieee.std_logic_1164.all; > > -- SIGNED and UNSIGNED types, and relevant functions > use ieee.numeric_std.all; > > > entity bit_counter is > > port(Start : in std_logic := '0' ; --was in > Reset : in std_logic := '1'; > Clock : in std_logic := '0'; > Bit_stream : in std_logic := '0'; > > Q_H, Q_L : out std_logic_vector (3 downto 0) := (others => '0') > ); > > > end entity bit_counter; > > architecture RTL of bit_counter is > > > signal cnt_L, cnt_H : integer range 0 to 15; > > begin > Q_H<= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); > Q_L<= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); > > count: process(Start, Reset, Clock, Bit_stream, cnt_L, cnt_H) > > begin > > if(Reset = '0' ) then > cnt_H<= 0; > cnt_L<= 0; > > elsif (rising_edge(Clock)) then > if(Start = '1') then > > if (Bit_stream = '1') then > cnt_H<= cnt_H + 1 ; > cnt_L<= cnt_L ; > > > elsif (Bit_stream = '0') then > Cnt_L<= Cnt_L + 1 ; > Cnt_H<= Cnt_H ; > > end if; > end if; > end if; > > > end process; > > end architecture RTL; > > --bit_counter_test.vhd > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > use ieee.std_logic_unsigned.all; > > > entity bit_counter_test is > end Entity bit_counter_test; > > Architecture behavioral of bit_counter_test is > > Signal Bit_stream, ext_Clock : std_logic := '0'; > Signal Reset_count, Start_count : std_logic := '1'; > Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); > Signal Endsim : std_logic := '0'; > begin > > UUT : entity work.bit_counter > port map ( > > Bit_stream => Bit_stream, > Start => Start_count, > Reset => Reset_count, > Clock => ext_Clock, > Q_L => Q_L, > Q_H => Q_H); > > > CLK_process :process > begin > if(EndSim = '0') then > ext_Clock<= NOT ext_Clock; > wait for 2ns; > end if; > end process; > > Signals : process > > Begin > > wait for 0.5 ns; > Start_count<= '1'; > Reset_count<= '1'; > > for I in 15 downto 0 loop > Bit_stream<= '1'; > wait for 4 ns; > Bit_stream<= '0'; > wait for 4 ns; > > end loop ; > > EndSim<= '1'; > wait; > end process; > > end Architecture behavioral; > > --boarddriver.vhd > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > use work.QuantumBaseSupport.all; > > entity BoardDriver is > Port ( > BUTTON : in STD_LOGIC_VECTOR(3 downto 0); > DIP : in STD_LOGIC_VECTOR(7 downto 0); > RESET : in STD_LOGIC; --Active Low > CLK0 : in STD_LOGIC; --20MHz input > CLK2 : in STD_LOGIC; > > -- Output ports > COM : out STD_LOGIC_VECTOR(3 downto 0); > FND_EN : out STD_LOGIC; > LED : out STD_LOGIC_VECTOR(7 downto 0); > SEGMENTS : out STD_LOGIC_VECTOR(7 downto 0); > EXPANSION : out STD_LOGIC_VECTOR(26 downto 0) > ); > end BoardDriver; > > architecture RTL of BoardDriver is > > alias Button1 is BUTTON(0); > alias Button2 is BUTTON(1); > alias Button3 is BUTTON(2); > alias Button4 is BUTTON(3); > > alias DIP1 is DIP(0); > alias DIP2 is DIP(1); > alias DIP3 is DIP(2); > alias DIP4 is DIP(3); > alias DIP5 is DIP(4); > alias DIP6 is DIP(5); > alias DIP7 is DIP(6); > alias DIP8 is DIP(7); > > alias LED1 is LED(0); > alias LED2 is LED(1); > alias LED3 is LED(2); > alias LED4 is LED(3); > alias LED5 is LED(4); > alias LED6 is LED(5); > alias LED7 is LED(6); > alias LED8 is LED(7); > > signal ButtonDB_stream : std_logic; > signal ButtonDB_clk : std_logic; > > begin > > EXPANSION<= (others => 'Z'); > > DeBounce_stream : entity work.SwDebounce > port map( Clock => CLK0, > Reset => Reset, > Input => Button1, > Debounced_out => ButtonDB_stream > ); > DeBounce_clk : entity work.SwDebounce > port map( Clock => CLK0, > Reset => Reset, > Input => Button1, > Debounced_out => ButtonDB_clk > ); > Count_Bits: entity work.bit_counter > Port map( > Reset => Reset, > Clock => ButtonDB_clk, > Bit_stream => ButtonDB_stream, > Start => DIP1, > Q_L => LED (3 downto 0), > Q_H => LED (7 downto 4) > > ); > > end architecture RTL; > > -- Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.66.117.172 with SMTP id kf12mr301234pab.31.1370587674919; Thu, 06 Jun 2013 23:47:54 -0700 (PDT) X-Received: by 10.49.17.42 with SMTP id l10mr361073qed.10.1370587674483; Thu, 06 Jun 2013 23:47:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!oz11no8830461pbb.0!news-out.google.com!d5ni3643pbl.0!nntp.google.com!oz11no8830458pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Jun 2013 23:47:54 -0700 (PDT) In-Reply-To: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73ee1d80-b53d-4a20-9602-b78828e108dc@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: goouse99@gmail.com Injection-Date: Fri, 07 Jun 2013 06:47:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6631 Am Donnerstag, 6. Juni 2013 03:32:16 UTC+2 schrieb Brandon Spiteri: > I need to implement 2 counters that counts 1's and 0's of an incoming bit stream. > > However I have a problem that not even the clock is generated on ModelSim and all the signals > > are labeled as 'no data'. Is there a problem in my code or is it related to some configuration or settings? > > > > This is my code; > > > > --bit_counter.vhd > > > > LIBRARY ieee; > > -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions > > use ieee.std_logic_1164.all; > > > > -- SIGNED and UNSIGNED types, and relevant functions > > use ieee.numeric_std.all; > > > > > > entity bit_counter is > > > > port(Start : in std_logic := '0' ; --was in > > Reset : in std_logic := '1'; > > Clock : in std_logic := '0'; > > Bit_stream : in std_logic := '0'; > > > > Q_H, Q_L : out std_logic_vector (3 downto 0) > > ); > > > > > > end entity bit_counter; > > > > architecture RTL of bit_counter is > > > > --type state_type is (IDLE, Bit_is_high, Bit_is_low); > > > > --signal initBitH, initBitL, BitH, BitL : std_logic; > > signal cnt_L, cnt_H : integer range 0 to 15; > > > > > > begin > > > > count: process(Start, Reset, Clock, Bit_stream, cnt_L, cnt_H) > > > > begin > > > > Q_H <= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); > > Q_L <= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); > > > > if(Reset = '0') then > > cnt_H <= 0; > > cnt_L <= 0; > > > > elsif (Start = '1') then > > if(rising_edge(Clock)) then > > > > if (Bit_stream = '1') then > > cnt_H <= cnt_H + 1; > > cnt_L <= cnt_L; > > elsif (Bit_stream = '0') then > > Cnt_H <= Cnt_H; > > Cnt_L <= Cnt_L + 1; > > end if; > > end if; > > end if; > > > > > > > > end process; > > > > end architecture RTL; > > > > --bit_counter_test.vhd > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > use ieee.std_logic_unsigned.all; > > > > entity bit_counter_test is > > end Entity bit_counter_test; > > > > Architecture behavioral of bit_counter_test is > > > > Signal Bit_stream, Clock : std_logic := '0'; > > Signal Reset_count, Start_count : std_logic := '1'; > > Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); > > > > begin > > > > UUT : entity work.bit_counter > > port map ( > > > > Bit_stream => Bit_stream, > > Start => Start_count, > > Reset => Reset_count, > > Clock => Clock); > > > > > > CLK_process :process > > begin > > for C in 30 downto 0 loop > > Clock <= NOT Clock after 5ns; > > end loop; > > end process; > > > > Signals : process > > > > Begin > > > > for I in 30 downto 0 loop > > wait for 10 ns; > > Start_count <= '1'; > > Reset_count <= '1'; > > Bit_stream <= '0'; > > > > > > end loop ; > > > > wait for 10 ns; > > > > for J in 30 downto 0 loop > > wait for 10 ns; > > Start_count <= '1'; > > Reset_count <= '1'; > > Bit_stream <= '1'; > > > > end loop ; > > > > wait; > > end process; > > > > > > > > end Architecture behavioral; > > > > In the past I already managed to simulate combinational logic with model sim so clock wasn't involved. It seams that the problem is I am not using the clock correctly.. Hi Brandon, one little question concerning your debouncer : It is clocked with 20 MHz. Does it have an internal counter to further reduce the sampling rate of the switch/button signals? Otherwise you would take samples every 50ns and since debouncers normally have just a few stages the debouncing period then will be just a few hundred ns. Switches/buttons tend to have bouncing times in the micro to milliseconds range. So please check this before you are wondering about strange hardware behavior. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.36.66 with SMTP id s2mr834269qad.6.1370588957798; Fri, 07 Jun 2013 00:09:17 -0700 (PDT) X-Received: by 10.49.99.74 with SMTP id eo10mr3067954qeb.37.1370588957696; Fri, 07 Jun 2013 00:09:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!ch1no2967383qab.0!news-out.google.com!y6ni1135qax.0!nntp.google.com!ch1no2967378qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 7 Jun 2013 00:09:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Fri, 07 Jun 2013 07:09:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6632 I modified the sensitivity list as you specified and I had 8 warnings, one for each signal which I removed. But there was no errors. Is there a particular reason why we leave only Reset and Clock? Can I eliminate the warnings? thanks for pointing out the button1 issue.. Regarding the self assigning to cnt_H and cnt_L, I was advised to do this to avoid extra memory elements. I do not know if this is true. From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr851067qab.1.1370589137444; Fri, 07 Jun 2013 00:12:17 -0700 (PDT) X-Received: by 10.49.6.201 with SMTP id d9mr3051346qea.12.1370589137428; Fri, 07 Jun 2013 00:12:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no2967957qab.0!news-out.google.com!y6ni1135qax.0!nntp.google.com!ch1no2967956qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 7 Jun 2013 00:12:17 -0700 (PDT) In-Reply-To: <73ee1d80-b53d-4a20-9602-b78828e108dc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <73ee1d80-b53d-4a20-9602-b78828e108dc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51baf434-67a9-42cc-a3cf-ee0f2fd6900d@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Fri, 07 Jun 2013 07:12:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2150 Xref: mx05.eternal-september.org comp.lang.vhdl:6633 Hi Eilert, thanks for pointing that out. I should have shown this file as well: I think this is sufficient.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.QuantumBaseSupport.all; entity ClockDiv_Gen is Generic( Source : integer := BoardClock; --20MHz Destination : integer := 200); --100Hz Port ( Reset : in STD_LOGIC; Clock : in STD_LOGIC; refresh_Clock : out STD_LOGIC); end ClockDiv_Gen; architecture RTL of ClockDiv_Gen is begin process(Reset,Clock) variable Counter : integer range 0 to (Source/(Destination * 2)) := 0; variable Cout : std_logic := '0'; begin if (Reset = '0') then refresh_Clock <= '0'; elsif rising_edge(Clock) then Counter := Counter + 1; if (Counter = (Source/(Destination * 2))) then Cout := not Cout; Counter := 0; end if; end if; refresh_Clock <= Cout; end process; end RTL; From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.165.143 with SMTP id i15mr858068qay.0.1370589383362; Fri, 07 Jun 2013 00:16:23 -0700 (PDT) X-Received: by 10.49.106.169 with SMTP id gv9mr3030379qeb.7.1370589383298; Fri, 07 Jun 2013 00:16:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!p1no3525472qaj.0!news-out.google.com!y6ni1135qax.0!nntp.google.com!ch1no2968759qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 7 Jun 2013 00:16:23 -0700 (PDT) In-Reply-To: <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Fri, 07 Jun 2013 07:16:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 17 Xref: mx05.eternal-september.org comp.lang.vhdl:6634 Hi Andy, thanks for the tips :) I managed to implement them all. Except= the wait for falling_edge(clk); part. Quartus is giving me the error when I try to compile: Error (10511): VHDL Qualified Expression error at bit_counter_test.vhd(49):= falling_edge type specified in Qualified Expression must match time type t= hat is implied for expression by context I think this is because ext_clock is declared as std_logic and this express= ion is expecting type time. I tried to modify the type to time in the gener= al and testbech however, it seems that then I have to change all the logic = of the code.. Is this the case?=20 thanks Brandon From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.59.205 with SMTP id m13mr1392449qah.7.1370610725661; Fri, 07 Jun 2013 06:12:05 -0700 (PDT) X-Received: by 10.49.1.197 with SMTP id 5mr3075623qeo.24.1370610725643; Fri, 07 Jun 2013 06:12:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p1no3576948qaj.0!news-out.google.com!y6ni1135qax.0!nntp.google.com!ch1no3022380qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 7 Jun 2013 06:12:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.158.71.187; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 195.158.71.187 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Synchronous programmable counter From: Brandon Spiteri Injection-Date: Fri, 07 Jun 2013 13:12:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5766 Xref: mx05.eternal-september.org comp.lang.vhdl:6635 I implemented an 8-bit Synchronous programmable counter with; -asynchronous active low reset -Synchronous enable -Count up or down (with rising edge) -Terminal counter up (for overflow) -Terminal Counter down (underflow) -Asynch load -8-bit parallel load: --counter.vhd LIBRARY ieee; -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; =20 ENTITY counter IS PORT ( dir, cnt_en, clk : in std_logic :=3D '0'; Reset, load : in std_logic; p : in INTEGER RANGE 0 TO 255; qd : inout INTEGER RANGE 0 TO 255; TCU, TCD : out std_logic; cnt_in : inout std_logic_vector (7 downto 0) :=3D (others =3D> '= 0'); cnt_out : out std_logic_vector (7 downto 0) :=3D (others =3D> '0'= )); END counter; ARCHITECTURE RTL OF counter IS signal cnt : INTEGER RANGE 0 TO 255; signal NotCPU : std_logic :=3D '0'; BEGIN =20 =20 cnt_out <=3D std_logic_vector(to_unsigned(cnt, cnt_out'length)); =09 PROCESS (clk, Reset, p, qd, dir, cnt_en, cnt, load) =20 =20 =20 BEGIN IF (Reset =3D '0') THEN cnt <=3D 0; =09 ELSIF (load =3D '1' and Reset =3D '1') THEN --load is activated cnt <=3D p; =09 =09 ELSE IF (rising_edge(clk)) THEN IF (dir =3D '1' and cnt_en =3D '1') THEN cnt <=3D cnt + 1; TCD <=3D '1'; TCU <=3D '1'; =09 ELSIF (dir =3D '0' and cnt_en =3D '1') THEN cnt <=3D cnt - 1; TCD <=3D '1'; TCU <=3D '1'; =09 END IF; =09 END IF; END IF; qd <=3D cnt;=09 if cnt =3D 0 then if (dir =3D '1') then TCD <=3D '1'; TCU <=3D '1'; elsif (dir =3D '0') then TCD <=3D '0'; TCU <=3D '1'; end if; elsif (cnt =3D 255) then if (dir =3D '1') then TCD <=3D '1'; TCU <=3D '0'; elsif (dir =3D '0') then TCD <=3D '1'; TCU <=3D '1'; end if; end if;=09 END PROCESS; END RTL; ___________________________________________________________________________= __________________________ When I simulated with the following test bench I got results that match the= Truth table in the 74HC193 data sheet. What do you think? The only problem= is that although I am declaring an integer with a range, when the integer = (cnt) is exceeding the maximum upper limit 255, the simulation stops instea= d of resetting the this integer (cnt) automatically. Do I have to take care= of resetting it my self in the vhdl code? --counter_test.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity counter_test is end Entity counter_test; Architecture behavioral of counter_test is Signal dir, cnt_en, clk, TCU, TCD : std_logic :=3D '0'; Signal Reset, load : std_logic :=3D '1'; signal p, qd : integer range 0 to 255 ; Signal Endsim : std_logic :=3D '0'; Signal cnt_in, cnt_out : std_logic_vector (7 downto 0) :=3D (others =3D> '= 0'); begin UUT : entity work.counter port map ( clk =3D> clk, Reset =3D> Reset, load =3D> load, p =3D> p, dir =3D> dir, qd =3D> qd, TCU =3D> TCU, TCD =3D> TCD, cnt_en =3D> cnt_en, cnt_in =3D> cnt_in, cnt_out =3D> cnt_out); =09 CLK_process :process begin=09 if(EndSim =3D '0') then=09 clk <=3D NOT clk;=20 wait for 2ns; else wait; end if; end process; =09 Signals : process =09 Begin =09 wait for 0.5 ns; =09 Reset <=3D '1'; dir <=3D '1'; cnt_en <=3D '1'; load <=3D '0'; =09 wait for 1020ns; =09 cnt_en <=3D '0'; =09 wait for 50ns; cnt_en <=3D '1'; dir <=3D '0'; =09 wait for 1020ns; cnt_en <=3D '0'; =09 wait for 50ns; load <=3D '1'; p <=3D 100; =09 wait for 4ns; load <=3D '0'; cnt_en <=3D '1'; =09 wait for 200ns; Reset <=3D '0'; =09 wait for 100ns; EndSim <=3D '1'; wait; end process; =09 end Architecture behavioral; =09 =09 =20 From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed2-b.proxad.net!nnrp2-1.free.fr!not-for-mail Date: Fri, 07 Jun 2013 22:27:58 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Synchronous programmable counter References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 19 Message-ID: <51b2424b$0$2556$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 07 Jun 2013 22:27:55 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1370636875 news-1.free.fr 2556 88.185.146.198:1351 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6636 Le 07/06/2013 15:12, Brandon Spiteri a écrit : [...] > When I simulated with the following test bench I got results that match the Truth > table in the 74HC193 data sheet. What do you think? The only problem is that > although I am declaring an integer with a range, when the integer (cnt) is exceeding > the maximum upper limit 255, the simulation stops instead of resetting the this integer > (cnt) automatically. Do I have to take care of resetting it my self in the vhdl code? Hello Integers do not rollover in VHDL, you have to test for upper and lower bounds and explicitly set the integer to the expected value. numeric_std.signed and unsigned do rollover implicitly, on the other hand. Nicolas From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2 counters, counting states of Bit stream Date: Fri, 07 Jun 2013 19:31:27 -0400 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 7 Jun 2013 23:26:55 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="8098a795e5d663d2b79b663610afe961"; logging-data="27701"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/xknfHJS38l+1GPDjv2ba0" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:8q6BnoUPm4glfRmQdOk8e6IohXM= Xref: mx05.eternal-september.org comp.lang.vhdl:6637 On 6/7/2013 3:09 AM, Brandon Spiteri wrote: > I modified the sensitivity list as you specified and I had 8 warnings, one for each signal which I removed. But there was no errors. Is there a particular reason why we leave only Reset and Clock? I can't say since I don't know what the errors are. They aren't because the signals belong in the sensitivity list. > Can I eliminate the warnings? thanks for pointing out the button1 issue.. What are the errors? > Regarding the self assigning to cnt_H and cnt_L, I was advised to do this to avoid extra memory elements. I do not know if this is true. That is only true for combinatorial logic processes. This process is sequential, no? When you write, "elsif (rising_edge(Clock)) then", you are describing a register. All of the signals assigned inside of this IF will be remembered in FFs regardless. If you have a combinatorial process without an edge or level sensitivity, you want all of the inputs (signals on the right side of the assignments) in the sensitivity list (or you can just use "all" in VHDL 2008 or later) and you need to make sure signals that are assigned values are assigned values for all conditions to avoid generating registers. Inadvertent latches are not uncommon. Does that make sense? -- Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2 counters, counting states of Bit stream Date: Fri, 07 Jun 2013 19:35:31 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 7 Jun 2013 23:31:01 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="8098a795e5d663d2b79b663610afe961"; logging-data="28910"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/z/u8H6HMlsg4Jg/7wvr1G" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:4eXlO8sTKpPje0mFHeFxY93qJqg= Xref: mx05.eternal-september.org comp.lang.vhdl:6638 On 6/7/2013 3:16 AM, Brandon Spiteri wrote: > Hi Andy, > thanks for the tips :) I managed to implement them all. Except the wait for falling_edge(clk); part. > > Quartus is giving me the error when I try to compile: > > Error (10511): VHDL Qualified Expression error at bit_counter_test.vhd(49): falling_edge type specified in Qualified Expression must match time type that is implied for expression by context > > I think this is because ext_clock is declared as std_logic and this expression is expecting type time. I tried to modify the type to time in the general and testbech however, it seems that then I have to change all the logic of the code.. Is this the case? How about showing the code? I expect this is something in a test bench since I can't imagine time and a falling_edge spec would be mixed in synthesized code. -- Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.174.145 with SMTP id t17mr2981968qaz.4.1370675853381; Sat, 08 Jun 2013 00:17:33 -0700 (PDT) X-Received: by 10.49.87.70 with SMTP id v6mr106568qez.25.1370675853365; Sat, 08 Jun 2013 00:17:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ch1no3139603qab.0!news-out.google.com!y6ni1323qax.0!nntp.google.com!ch1no3139596qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 8 Jun 2013 00:17:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.232.217.72; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 85.232.217.72 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5fbf943f-8257-4fce-9f69-34b96d1be1c9@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Sat, 08 Jun 2013 07:17:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2763 Xref: mx05.eternal-september.org comp.lang.vhdl:6639 On Saturday, 8 June 2013 01:35:31 UTC+2, rickman wrote: > On 6/7/2013 3:16 AM, Brandon Spiteri wrote: >=20 > > Hi Andy, >=20 > > thanks for the tips :) I managed to implement them all. E= xcept the wait for falling_edge(clk); part. >=20 > > >=20 > > Quartus is giving me the error when I try to compile: >=20 > > >=20 > > Error (10511): VHDL Qualified Expression error at bit_counter_test.vhd(= 49): falling_edge type specified in Qualified Expression must match time ty= pe that is implied for expression by context >=20 > > >=20 > > I think this is because ext_clock is declared as std_logic and this exp= ression is expecting type time. I tried to modify the type to time in the g= eneral and testbech however, it seems that then I have to change all the lo= gic of the code.. Is this the case? >=20 >=20 >=20 > How about showing the code? I expect this is something in a test bench= =20 >=20 > since I can't imagine time and a falling_edge spec would be mixed in=20 >=20 > synthesized code. >=20 >=20 >=20 > --=20 >=20 >=20 >=20 > Rick The test bench is the same one in my first post. The warnings are: Warning (10492): VHDL Process Statement warning at bit_counter.vhd(43): sig= nal "Start" is read inside the Process Statement but isn't in the Process S= tatement's sensitivity list From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.42.141 with SMTP id s13mr4251478qae.3.1370719277664; Sat, 08 Jun 2013 12:21:17 -0700 (PDT) X-Received: by 10.49.30.105 with SMTP id r9mr183239qeh.27.1370719277643; Sat, 08 Jun 2013 12:21:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!p1no3748908qaj.0!news-out.google.com!y6ni1323qax.0!nntp.google.com!ch1no3201734qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 8 Jun 2013 12:21:17 -0700 (PDT) In-Reply-To: <51baf434-67a9-42cc-a3cf-ee0f2fd6900d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.8.47.233; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 194.8.47.233 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <73ee1d80-b53d-4a20-9602-b78828e108dc@googlegroups.com> <51baf434-67a9-42cc-a3cf-ee0f2fd6900d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 2 counters, counting states of Bit stream From: Ilya Kalistru Injection-Date: Sat, 08 Jun 2013 19:21:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6640 =D0=BF=D1=8F=D1=82=D0=BD=D0=B8=D1=86=D0=B0, 7 =D0=B8=D1=8E=D0=BD=D1=8F 2013= =C2=A0=D0=B3., 11:12:17 UTC+4 =D0=BF=D0=BE=D0=BB=D1=8C=D0=B7=D0=BE=D0=B2=D0= =B0=D1=82=D0=B5=D0=BB=D1=8C Brandon Spiteri =D0=BD=D0=B0=D0=BF=D0=B8=D1=81= =D0=B0=D0=BB: > Hi Eilert, >=20 > thanks for pointing that out. I should have shown this file as= well: >=20 > I think this is sufficient.. >=20 >=20 >=20 > library IEEE; >=20 > use IEEE.STD_LOGIC_1164.ALL; >=20 > use IEEE.NUMERIC_STD.ALL; >=20 > use work.QuantumBaseSupport.all; >=20 >=20 >=20 > entity ClockDiv_Gen is >=20 > Generic( Source : integer :=3D BoardClock; --20MHz >=20 > Destination : integer :=3D 200); --100Hz >=20 > Port ( Reset : in STD_LOGIC; >=20 > Clock : in STD_LOGIC; >=20 > refresh_Clock : out STD_LOGIC); >=20 > end ClockDiv_Gen; >=20 >=20 >=20 > architecture RTL of ClockDiv_Gen is >=20 >=20 >=20 > begin >=20 > process(Reset,Clock) >=20 > variable Counter : integer range 0 to (Source/(Destination * 2)) :=3D = 0; >=20 > variable Cout : std_logic :=3D '0'; >=20 > begin >=20 > if (Reset =3D '0') then >=20 > refresh_Clock <=3D '0'; >=20 > elsif rising_edge(Clock) then >=20 > Counter :=3D Counter + 1; >=20 > if (Counter =3D (Source/(Destination * 2))) then >=20 > Cout :=3D not Cout; >=20 > Counter :=3D 0; >=20 > end if; >=20 > end if; >=20 > refresh_Clock <=3D Cout; >=20 > end process; >=20 >=20 >=20 > end RTL; Are you use refresh_Clock for clocking your scheme? I don't think that is a= good idea. Xilinx prohibit this technic. I think you should use dedicated = primitives to clock generating that use dedicated clock nets. If I can't use clock primitives or I don't want it, I use a simple entity t= hat generate strobe signal that '0' several clock periods and then '1' one = period and so on. Then I use it if (rising_edge(Clock)) and (strobe =3D '1') then do_what_you_want; end if; This strobe signal reduce speed of do_what_you_want code without changing o= f frecuency of Clock. From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2 counters, counting states of Bit stream Date: Sat, 08 Jun 2013 19:19:10 -0400 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> <5fbf943f-8257-4fce-9f69-34b96d1be1c9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 8 Jun 2013 23:14:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="dd7f903106951093490a5e74c4d6b87f"; logging-data="32199"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19gKWfLgLvovC52N0NgevWa" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <5fbf943f-8257-4fce-9f69-34b96d1be1c9@googlegroups.com> Cancel-Lock: sha1:X9j0Dmrvq6UrBN9iINeu8zY72Lg= Xref: mx05.eternal-september.org comp.lang.vhdl:6641 On 6/8/2013 3:17 AM, Brandon Spiteri wrote: > On Saturday, 8 June 2013 01:35:31 UTC+2, rickman wrote: >> On 6/7/2013 3:16 AM, Brandon Spiteri wrote: >> >>> Hi Andy, >> >>> thanks for the tips :) I managed to implement them all. Except the wait for falling_edge(clk); part. >> >>> >> >>> Quartus is giving me the error when I try to compile: >> >>> >> >>> Error (10511): VHDL Qualified Expression error at bit_counter_test.vhd(49): falling_edge type specified in Qualified Expression must match time type that is implied for expression by context >> >>> >> >>> I think this is because ext_clock is declared as std_logic and this expression is expecting type time. I tried to modify the type to time in the general and testbech however, it seems that then I have to change all the logic of the code.. Is this the case? >> >> >> >> How about showing the code? I expect this is something in a test bench >> >> since I can't imagine time and a falling_edge spec would be mixed in >> >> synthesized code. >> >> >> >> -- >> >> >> >> Rick > > The test bench is the same one in my first post. The warnings are: > > Warning (10492): VHDL Process Statement warning at bit_counter.vhd(43): signal "Start" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Sorry, there is no way I can relate "line 43" to the contents of your previous post. You need to post the text in a format that preserves the lines and replace tabs with spaces so the text isn't all skewed across the screen. I'm happy to help, but I don't want to have to dig the info out of your posts. Or repost the code pointing to the offending line. Looking at the original code I do see a couple of lines at the beginning of the count: process (good that you name your processes) that I think should not be there. Q_H <= std_logic_vector(to_unsigned(Cnt_H, Q_H'length)); Q_L <= std_logic_vector(to_unsigned(Cnt_L, Q_L'length)); These are in the clocked process, but not inside the reset or the clocked clauses and so are combinatorial statements. They will not function in simulation the way they will work in the hardware. Move them outside of the process maybe? I'm not sure what your intent is with these. Looking at the code I think they need to be concurrent statements outside of the clocked process. That may be confusing the tools. Oh, I see the problem... another problem. You have swapped the enable and the clock edge test. The enable (Start = '1') needs to be inside the clock test clause. elsif (rising_edge(Clock)) then if (Start = '1') then ... -- Rick From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr5527697qab.1.1370766156574; Sun, 09 Jun 2013 01:22:36 -0700 (PDT) X-Received: by 10.50.98.1 with SMTP id ee1mr363346igb.5.1370766156382; Sun, 09 Jun 2013 01:22:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no3264810qab.0!news-out.google.com!y6ni1323qax.0!nntp.google.com!ch1no3264809qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Jun 2013 01:22:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=36.86.169.18; posting-account=6q3jswoAAAAGQbceqUFBHdp7th17Slur NNTP-Posting-Host: 36.86.169.18 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: ram problem From: dwi jayanto Wibowo Injection-Date: Sun, 09 Jun 2013 08:22:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6642 hi .. the fpga and vhdl master ... I want to ask about the ram ... I have a little problem in the call data th= at are saved on ram ... when I try to testbench or i simulate in single blo= ck outgoing data is correct, but when the block I combine and i synthesis i= n quartus then i run in modelsim Altera with data such as skipped out .. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D -- 2D ram subtype p_simb is std_logic_vector(7 downto 0); type t_simb is array(1 to 257) of p_simb; -- deklarasi sinyal ram signal ram_kor : t_simb; BEGIN process (rst,clk) begin if rst=3D '0' then << problem1 sig_pros <=3D '0'; Dec_codword_out <=3D "00000000"; cnt4wraddr <=3D 1; cnt4rdaddr <=3D 1; ram_kor <=3D (others=3D>"UUUUUUUU"); << problem2 elsif (rising_edge(clk)) then last_state <=3D enb_dec; last_state2 <=3D sig_pros; if enb_dec =3D '1' then cnt4wraddr <=3D cnt4wraddr + 1; ram_kor(cnt4wraddr) <=3D Dec_Din; else cnt4wraddr <=3D 1; end if; if (str_koreksi =3D '1' or str_koreksi2 =3D '1') then sig_pros <=3D '1'; elsif sig_pros =3D '1' then cnt4rdaddr<=3Dcnt4rdaddr+1; if (cnt4rdaddr >=3D 255 ) then Dec_codword_out <=3D "00000000"; if (cnt4rdaddr > 255 ) then cnt4rdaddr <=3D 1; sig_pros <=3D '0'; ram_kor <=3D (others=3D>"UUUUUUUU"); << problem2 end if; end if; if (cnt4rdaddr <=3D 255 ) then if cnt4rdaddr =3D lokasi_err1 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err1; elsif cnt4rdaddr =3D lokasi_err2 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err2; elsif cnt4rdaddr =3D lokasi_err3 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err3; elsif cnt4rdaddr =3D lokasi_err4 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err4; elsif cnt4rdaddr =3D lokasi_err5 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err5; elsif cnt4rdaddr =3D lokasi_err6 then Dec_codword_out <=3D ram_kor(cnt4rdaddr) xor nilai_err6; else Dec_codword_out <=3D ram_kor(cnt4rdaddr); end if; end if; end if; end if; end process; koreksi_done <=3D '1' when (last_state2 =3D '1' and sig_pros =3D '0') else = '0'; data_valid_out <=3D "00000000" when (cnt4rdaddr > 244 ) else Dec_codword_ou= t; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D the problem occurs when I add a reset, when reset I remove the program work= s well, but source which used to be much .... I asked how to use the ram so that I could get the data properly ..... does anyone have a solution? thanks 4 answer....=20 From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.174.145 with SMTP id t17mr5499431qaz.4.1370767097768; Sun, 09 Jun 2013 01:38:17 -0700 (PDT) X-Received: by 10.49.24.243 with SMTP id x19mr218810qef.34.1370767097730; Sun, 09 Jun 2013 01:38:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no3265857qab.0!news-out.google.com!y6ni1323qax.0!nntp.google.com!ch1no3265846qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Jun 2013 01:38:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.88.237; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.88.237 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> <5fbf943f-8257-4fce-9f69-34b96d1be1c9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 2 counters, counting states of Bit stream From: Brandon Spiteri Injection-Date: Sun, 09 Jun 2013 08:38:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6643 " The enable (Start = '1') needs to be inside the clock test clause. " That solved the problem :) .. thanks a lot. Below is my modified code; LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.unsigned; use IEEE.std_logic_unsigned.all; entity bit_counter is port(Start : in std_logic := '0' ; --was in Reset : in std_logic := '1'; Clock : in std_logic := '0'; Bit_stream : in std_logic := '0'; Q_H, Q_L : out std_logic_vector (3 downto 0) := (others => '0') ); end entity bit_counter; architecture RTL of bit_counter is signal cnt_L, cnt_H : STD_LOGIC_VECTOR (3 downto 0) := "0000"; begin Q_H <= Cnt_H; Q_L <= Cnt_L; count: process(Reset, Clock) begin if(Reset = '0' ) then cnt_H <= "0000"; cnt_L <= "0000"; elsif (rising_edge(Clock)) then if (start = '1' and Bit_stream = '1') then cnt_H <= cnt_H + 1 ; cnt_L <= cnt_L ; elsif (start = '1' and Bit_stream = '0') then Cnt_L <= Cnt_L + 1 ; Cnt_H <= Cnt_H ; end if; end if; end process; end architecture RTL; _________________________________________________________________________________________________ Regarding the test bench code below, do you think there is a better way to test my above code? Do you think this is sufficient? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity bit_counter_test is end Entity bit_counter_test; Architecture behavioral of bit_counter_test is Signal Bit_stream, ext_Clock : std_logic := '0'; Signal Reset_count, Start_count : std_logic := '1'; Signal Q_H, Q_L : std_logic_vector (3 downto 0) := (others => '0'); Signal Endsim : std_logic := '0'; begin UUT : entity work.bit_counter port map ( Bit_stream => Bit_stream, Start => Start_count, Reset => Reset_count, Clock => ext_Clock, Q_L => Q_L, Q_H => Q_H); CLK_process :process begin if(EndSim = '0') then ext_Clock <= NOT ext_Clock; wait for 2ns; else wait; end if; end process; Signals : process Begin wait for 0.5 ns; Start_count <= '1'; Reset_count <= '1'; for I in 18 downto 0 loop Bit_stream <= '1'; wait for 4 ns; Bit_stream <= '0'; wait for 4 ns; end loop ; Reset_count <= '0'; Start_count <= '1'; wait for 4 ns; Reset_count <= '1'; for J in 8 downto 0 loop Bit_stream <= '1'; wait for 4 ns; Bit_stream <= '0'; wait for 4 ns; end loop; Start_count <= '0'; wait for 20 ns; Start_count <= '1'; for K in 8 downto 0 loop Bit_stream <= '1'; wait for 4 ns; Bit_stream <= '0'; wait for 4 ns; end loop; EndSim <= '1'; wait; end process; end Architecture behavioral; From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.86.200 with SMTP id t8mr4777496qal.0.1370785948956; Sun, 09 Jun 2013 06:52:28 -0700 (PDT) X-Received: by 10.49.6.201 with SMTP id d9mr263845qea.12.1370785948888; Sun, 09 Jun 2013 06:52:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!ch1no3287263qab.0!news-out.google.com!y6ni1323qax.0!nntp.google.com!ch1no3287258qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Jun 2013 06:52:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.217.251.102; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 94.217.251.102 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <44053726-fb7a-488d-9f61-09025e4efd9a@googlegroups.com> Subject: Re: A few question about vhdl(clk,signal,etc..) From: Thomas Stanka Injection-Date: Sun, 09 Jun 2013 13:52:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6644 Am Sonntag, 2. Juni 2013 09:57:57 UTC+2 schrieb nati...@gmail.com: > why to use signal count: STD_LOGIC_VECTOR(3 downto 0); >=20 > when i use a clock and do counting+1 in the state machine? >=20 > and for what to configure it 3 downto 0... a vector(3 downto 0) means you have 4 bit width. This is easy to adopt on y= our hardware needs. YOu could for instance use integer instead and have the= problem, that you could end up with a 32 bit width counter while needing o= nly 4 bit. If you detect later that you need not 4 bit width but 400 bit wi= dth, it is easy to change in vector, but impossible in integer. Plus the is= sue that integer is quite special in VHDL concerning covered range (see lrm= , or google for details). bye Thomas=20 From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: vmkr segmentation fault Date: Mon, 10 Jun 2013 10:15:54 +0200 Lines: 47 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /fIdIsdD1KL8neF4ELZAWQ21TkeSytLT887DB9X6Zy0Y+/9nCY Cancel-Lock: sha1:WRwnRzsunYMD6il716iij1eyEDE= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6645 Hi everyone, I'm trying to use vmkr to generate Makefiles to handle dependencies. I downloaded version 2.8 from here: > http://tams-www.informatik.uni-hamburg.de/vhdl/index.php?content=07-tools built it with gcc (instead of cc), got a bunch of warnings like these: > warning: incompatible implicit declaration of built-in function 'strlen' but managed to compile. At the moment of execution I run the program as suggested in the user manual (vmkr.doc.ps): vmkr -ts *.vhd > Makefile and got this as the output: > vmkr -ts *.vhd > Makefile > BNR vmkr version 2.8 (Nov 08/93 11:10) > Copyright (C) 1993 Bell-Northern Research. > Please email bugs/suggestions to hemi@bnr.ca > > The possible top level architectures are : > > The possible top level configurations are : > Segmentation fault As if it was not even capable to find the top level architecture. By the way, I have one unit only per file so there shouldn't be a problem on that end. Any insight would be helpful. Thanks a lot, Al p.s.: it seems like this software dates back in the 1993, which may explain the list of warnings. If anyone knows a more recent one that could be helpful. -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:42:57 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: ram problem Date: Mon, 10 Jun 2013 09:42:48 -0700 Organization: Highland Technology, Inc. Lines: 112 Message-ID: <20130610094248.792b9770@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="7a89dde196082de0e965aec8c036e07b"; logging-data="9087"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19MgoYuSwCc24ZaIUgsQhdR" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Xm/u/QLxUBR67AJd9C5HlF3fPZ8= Xref: mx05.eternal-september.org comp.lang.vhdl:6646 On Sun, 9 Jun 2013 01:22:36 -0700 (PDT) dwi jayanto Wibowo wrote: > hi .. > the fpga and vhdl master ... > > I want to ask about the ram ... I have a little problem in the call data that are saved on ram ... when I try to testbench or i simulate in single block outgoing data is correct, but when the block I combine and i synthesis in quartus then i run in modelsim Altera with data such as skipped out .. > > > ================================================== ============================ > -- 2D ram > subtype p_simb is std_logic_vector(7 downto 0); > type t_simb is array(1 to 257) of p_simb; > > -- deklarasi sinyal ram > signal ram_kor : t_simb; > > > BEGIN > > process (rst,clk) > begin > if rst= '0' then << problem1 > sig_pros <= '0'; > Dec_codword_out <= "00000000"; > cnt4wraddr <= 1; > cnt4rdaddr <= 1; > ram_kor <= (others=>"UUUUUUUU"); << problem2 > > elsif (rising_edge(clk)) then > last_state <= enb_dec; > last_state2 <= sig_pros; > if enb_dec = '1' then > cnt4wraddr <= cnt4wraddr + 1; > ram_kor(cnt4wraddr) <= Dec_Din; > else > cnt4wraddr <= 1; > end if; > > if (str_koreksi = '1' or str_koreksi2 = '1') then > sig_pros <= '1'; > > elsif sig_pros = '1' then > cnt4rdaddr<=cnt4rdaddr+1; > > if (cnt4rdaddr >= 255 ) then > Dec_codword_out <= "00000000"; > > if (cnt4rdaddr > 255 ) then > cnt4rdaddr <= 1; > sig_pros <= '0'; > ram_kor <= (others=>"UUUUUUUU"); << problem2 > end if; > end if; > > if (cnt4rdaddr <= 255 ) then > if cnt4rdaddr = lokasi_err1 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err1; > > elsif cnt4rdaddr = lokasi_err2 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err2; > > elsif cnt4rdaddr = lokasi_err3 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err3; > > elsif cnt4rdaddr = lokasi_err4 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err4; > > elsif cnt4rdaddr = lokasi_err5 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err5; > > elsif cnt4rdaddr = lokasi_err6 then > Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err6; > > else > Dec_codword_out <= ram_kor(cnt4rdaddr); > > end if; > end if; > > end if; > end if; > end process; > > koreksi_done <= '1' when (last_state2 = '1' and sig_pros = '0') else '0'; > data_valid_out <= "00000000" when (cnt4rdaddr > 244 ) else Dec_codword_out; > > ================================================== ============================= > > the problem occurs when I add a reset, when reset I remove the program works well, but source which used to be much .... > I asked how to use the ram so that I could get the data properly ..... > > does anyone have a solution? > > > thanks 4 answer.... Offhand, it's probably the fact that you can't have a block RAM have a reset signal for the contents; they don't do that. You can have an initializer on them, i.e. signal ram_kor : t_simb := (others => (others => 'U')); But no true signal reset. As a side note, PLEASE indent your code if you want people to read it. If copying and pasting it into your news client strips that out, then try again a a different way, because it's nearly illegible as is. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr8830928qab.8.1370883081307; Mon, 10 Jun 2013 09:51:21 -0700 (PDT) X-Received: by 10.50.36.41 with SMTP id n9mr1019868igj.11.1370883081265; Mon, 10 Jun 2013 09:51:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no3430201qab.0!news-out.google.com!y6ni1655qax.0!nntp.google.com!ch1no3430195qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 09:51:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: ram problem From: Andy Injection-Date: Mon, 10 Jun 2013 16:51:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 20 Xref: mx05.eternal-september.org comp.lang.vhdl:6647 First, RAMs contents cannot be reset. Second, if you want to reset some things, and not others, in one clocked process, then you should execute the rising_edge() stuff first, then (not else) execute the reset assignments if reset is active. Otherwise, synthesis will add a feedback mux (clock disable) for things that are not reset, because the conventional "eslif rising_edge()..." prevents the any synchronous updates from occuring if reset is active. The following example template does this: process (rst, clk) is begin if rising_edge(clk) then -- synchronous assignments go here end if; if rst = '1' then -- asynchronous reset assignments go here end if; end process; Also, remove all but the clock and reset signals from your process sensitivity list for clocked processes. Andy From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.59.205 with SMTP id m13mr8835339qah.7.1370883613693; Mon, 10 Jun 2013 10:00:13 -0700 (PDT) X-Received: by 10.49.87.232 with SMTP id bb8mr507317qeb.28.1370883613589; Mon, 10 Jun 2013 10:00:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p1no3969202qaj.0!news-out.google.com!y6ni1655qax.0!nntp.google.com!ch1no3431117qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 10:00:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> <9213a17f-d9b3-4bfe-baaa-70996d7c8343@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <193d1c52-772b-44dd-b403-11f1d69ab899@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Andy Injection-Date: Mon, 10 Jun 2013 17:00:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1460 Xref: mx05.eternal-september.org comp.lang.vhdl:6648 Brandon, wait until falling_edge(clk); -- not wait "for" Use "until" for conditions, "for" for time. Andy From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.59.205 with SMTP id m13mr8901815qah.7.1370885782660; Mon, 10 Jun 2013 10:36:22 -0700 (PDT) X-Received: by 10.49.116.132 with SMTP id jw4mr524709qeb.33.1370885782593; Mon, 10 Jun 2013 10:36:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no3435358qab.0!news-out.google.com!y6ni1655qax.0!nntp.google.com!ch1no3435353qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 10:36:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <66e9f714-909d-4549-a2bf-867a76fdc412@googlegroups.com> <72a49b55-2356-45c3-90d4-7ccb013bd8c7@googlegroups.com> <12e84249-fa63-4966-ae94-958fed3c02a1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <726668e9-d80f-4fb9-9eaa-aa3bbf5b8d6e@googlegroups.com> Subject: Re: 2 counters, counting states of Bit stream From: Andy Injection-Date: Mon, 10 Jun 2013 17:36:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 32 Xref: mx05.eternal-september.org comp.lang.vhdl:6649 Rick, This illustrates why I advise not using self assignments. People start usin= g them because they heard it did something useful (and they even saw it on = the interweb), and nobody really knows what purpose they serve. A self assi= gnment will NEVER prevent inferrence of a latch, but it may actually create= one! These crutches keep new users from learning what actually causes a latch: A= storage device is inferred when the RTL description requires remembering a= value stored at a previous time (or delta-cycle). If that previous time wa= s a previous clock edge, a register is inferred; if not, a latch is inferre= d. =20 When we read code, we assume that it is needed. That assumption is false in= this case. A self assignment is NEVER needed, but its presence implies it = is needed. Otherwise, why would the author have typed it? If you want to le= ave it in for misguided self-documentation, at least comment it as unnecess= ary. BTW, I use "if" and "then" (also if/generate, while/loop, or when/else) to = clearly delineate a conditional expression. There may be parenthesis within= in the expression that do not delineate the entire expression, so parenthe= ses alone do not provide that service. However, I sometimes use them to "he= lp" the editor format multi-line conditional expressions more clearly. But the latter is a matter of style, and less of substance (no additional o= peration by the simulator or the synthesis tool is implied). Many users ass= ume that since other languages require it, it must be required in VHDL too,= which is incorrect. Use them if you wish, but not because they are require= d, that's all. Andy From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr8922172qab.8.1370886195598; Mon, 10 Jun 2013 10:43:15 -0700 (PDT) X-Received: by 10.49.107.234 with SMTP id hf10mr526940qeb.21.1370886195520; Mon, 10 Jun 2013 10:43:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!p1no3973943qaj.0!news-out.google.com!y6ni1655qax.0!nntp.google.com!ch1no3436121qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 10:43:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e52357a-0e75-4816-bcee-90013f17a75e@googlegroups.com> Subject: Re: A few question about vhdl(clk,signal,etc..) From: Andy Injection-Date: Mon, 10 Jun 2013 17:43:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6650 Gabor, I would say "top level" entity. Lower level entities (whose ports are not t= hose of the FPGA) are fine for other data types. The top level is special, because the gate level model produced after synth= esis and/or place & route will always use std_logic and std_logic_vector fo= r the ports, regardless of what types the RTL used. If you want to use both= RTL and post-S/P&R models in the same testbench (without constructing a wr= apper for the latter), then only use std_logic and std_logic_vector data ty= pes for the ports on the top level entity. Andy From newsfish@newsfish Tue Dec 29 16:42:57 2015 X-Received: by 10.180.76.115 with SMTP id j19mr4288448wiw.2.1370891295629; Mon, 10 Jun 2013 12:08:15 -0700 (PDT) X-Received: by 10.50.98.1 with SMTP id ee1mr1128785igb.5.1370891295458; Mon, 10 Jun 2013 12:08:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.212.216.MISMATCH!mf3no2564936wib.1!news-out.google.com!hv6ni12796wib.1!nntp.google.com!ch1no3444981qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 12:08:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=216.16.247.154; posting-account=BjPtEgoAAAD6yHYy_PU4Ud8vXp32q1m7 NNTP-Posting-Host: 216.16.247.154 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2bade78c-f58b-412e-8ccf-8db38289c167@googlegroups.com> Subject: DSP48 in synchronous process or not, what's the difference? From: Ethan Zheng Injection-Date: Mon, 10 Jun 2013 19:08:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6651 I am so curious about the behavior difference between the following codes. Please comment, CODE1: signal reg_in : signed(17 downto 0); signal reg_product : signal(35 downto 0); Product_out_pipe_process : PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEM reg_in <= port_in; -- multiplication pipeline in reg_product <= reg_in * reg_in; -- pipeline out port_out <= reg_product; END IF; END PROCESS Product_out_pipe_process; CODE2: signal reg_in : signed(17 downto 0); signal reg_product : signal(35 downto 0); signal reg_product_1 : signal(35 downto 0); Pipe_in_process : PROGRESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEM reg_in <= port_in; END IF END PROCESS Pipe_in_process; reg_product <= reg_in * reg_in; -- multiplication not clk sensitive Pipe_out_process : PROGRESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEM reg_product_1 <= reg_product END IF END PROGRESS Pipe_out_process From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.180.11.239 with SMTP id t15mr4486057wib.3.1370897953986; Mon, 10 Jun 2013 13:59:13 -0700 (PDT) X-Received: by 10.49.94.174 with SMTP id dd14mr591820qeb.14.1370897953307; Mon, 10 Jun 2013 13:59:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.212.215.MISMATCH!lg1no15441557wic.0!news-out.google.com!hv6ni12796wib.1!nntp.google.com!ch1no3452532qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Jun 2013 13:59:13 -0700 (PDT) In-Reply-To: <2bade78c-f58b-412e-8ccf-8db38289c167@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.35 References: <2bade78c-f58b-412e-8ccf-8db38289c167@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4057349c-bc47-44dd-bcdc-aaecc5267d40@googlegroups.com> Subject: Re: DSP48 in synchronous process or not, what's the difference? From: Andy Injection-Date: Mon, 10 Jun 2013 20:59:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6652 In code2, reg_product is not a register, so it does not consume a clock cycle, but it does consume one in code1. Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.59.205 with SMTP id m13mr12621919qah.7.1371018592568; Tue, 11 Jun 2013 23:29:52 -0700 (PDT) X-Received: by 10.49.35.195 with SMTP id k3mr80216qej.2.1371018592552; Tue, 11 Jun 2013 23:29:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!ch1no4156471qab.0!news-out.google.com!y6ni1854qax.0!nntp.google.com!ch1no4156464qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Jun 2013 23:29:52 -0700 (PDT) In-Reply-To: <2bade78c-f58b-412e-8ccf-8db38289c167@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.216 References: <2bade78c-f58b-412e-8ccf-8db38289c167@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <294ee0e7-47f6-4e59-9b5d-ff8a7de58c15@googlegroups.com> Subject: Re: DSP48 in synchronous process or not, what's the difference? From: goouse99@gmail.com Injection-Date: Wed, 12 Jun 2013 06:29:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 88 Xref: mx05.eternal-september.org comp.lang.vhdl:6653 Am Montag, 10. Juni 2013 21:08:15 UTC+2 schrieb Ethan Zheng: > I am so curious about the behavior difference between the following codes. > > Please comment, > > > > CODE1: > > signal reg_in : signed(17 downto 0); > > signal reg_product : signal(35 downto 0); > > > > Product_out_pipe_process : PROCESS (clk) > > BEGIN > > IF clk'EVENT AND clk = '1' THEM > > reg_in <= port_in; -- multiplication pipeline in > > reg_product <= reg_in * reg_in; -- pipeline out > > port_out <= reg_product; > > END IF; > > END PROCESS Product_out_pipe_process; > > > > CODE2: > > signal reg_in : signed(17 downto 0); > > signal reg_product : signal(35 downto 0); > > signal reg_product_1 : signal(35 downto 0); > > > > Pipe_in_process : PROGRESS (clk) > > BEGIN > > IF clk'EVENT AND clk = '1' THEM > > reg_in <= port_in; > > END IF > > END PROCESS Pipe_in_process; > > > > reg_product <= reg_in * reg_in; -- multiplication not clk sensitive > > > > Pipe_out_process : PROGRESS (clk) > > BEGIN > > IF clk'EVENT AND clk = '1' THEM > > reg_product_1 <= reg_product > > END IF > > END PROGRESS Pipe_out_process Hi, Code1 has a latency of 3 while code 2 has a latency of 2. (I assume reg_product1 to be identical with port_out). Code 2 could be rewritten like this without functional changes: Pipe_out_process : PROGRESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEM reg_product_1 <= reg_in*reg_in; -- now inside sync process, END IF END PROGRESS Pipe_out_process Both architectures might synthesize to DSP48, since the multiplication is enclosed with registers. Additional pipeline stages are possible, but only required if your algorithm needs it. Otherwise you are just wasting clock cycles. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.18.203 with SMTP id x11mr1235155qaa.2.1371118006533; Thu, 13 Jun 2013 03:06:46 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.49.13.71 with SMTP id f7mt17664qec.31.1371118005512; Thu, 13 Jun 2013 03:06:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bw2no1490523qab.0!news-out.google.com!y6ni1854qax.0!nntp.google.com!ch1no5645122qab.0!postnews.google.com!ce7g2000vbb.googlegroups.com!not-for-mail Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog,comp.arch.embedded Date: Thu, 13 Jun 2013 03:06:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: ce7g2000vbb.googlegroups.com; posting-host=94.67.100.138; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.100.138 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/27.0.1453.110 Safari/537.36,gzip(gfe) Message-ID: <3345c5c6-7070-4136-a798-0ae040658d81@ce7g2000vbb.googlegroups.com> Subject: [ANN] LOOPGEN-Fast hardware looping VHDL IPs From: Nikolaos Kavvadias Injection-Date: Thu, 13 Jun 2013 10:06:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3029 Xref: mx05.eternal-september.org comp.arch.fpga:19112 comp.lang.vhdl:6654 comp.lang.verilog:3509 comp.arch.embedded:31694 The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants), namely: - HWLU, a mixed-level structural/RTL architecture, - IXGENB, a behavioral-level and - IXGENR, a high-performance, pure RTL description of a more generalized form of the architecture. Hardware looping architectures have potential uses for data-intensive processing in embedded systems. The implemented architectures are able to execute perfect loop nests without any cycle overhead for updating the iteration vector. Actually, successive last iterations of nested loops are collapsed in a single cycle. LOOPGEN can be used as a ROYALTY-FREE component for use in your projects. Interesting features and characteristics of LOOPGEN include: - three different architectural variants - support for any number of loops and datapath bitwidth - single-cycle iteration vector update - 201-243 MHz achieved clock rates on Xilinx Virtex-6. The LOOPGEN IPs comprise of the following deliverables: - Documentation in ASCII text, PDF, HTML formats - Vendor-independent VHDL code for all architectural variants - Configurable testbench - HDL code generators for the HWLU and IXGENR architectures - Various helper scripts for simulation (GHDL, Modelsim) and synthesis. SPECIAL OFFER! -------------- All users that will register and download LOOPGEN within 2013 are eligible to the following: - FREE updates for the entire lifetime of the product - FREE email support. Pricing information and sample downloads: http://www.nkavvadias.com/eshop Best regards, Nikolaos Kavvadias Hardware and EDA tools developer, Research Scientist Lamia, Fthiotis, Greece http://www.nkavvadias.com http://www.perfeda.gr From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.18.203 with SMTP id x11mr2290844qaa.2.1371259271669; Fri, 14 Jun 2013 18:21:11 -0700 (PDT) X-Received: by 10.50.176.137 with SMTP id ci9mr7735igc.16.1371259271632; Fri, 14 Jun 2013 18:21:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!news.glorb.com!bw2no1738060qab.0!news-out.google.com!y6ni2876qax.0!nntp.google.com!j2no234629qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Jun 2013 18:21:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> Subject: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Sat, 15 Jun 2013 01:21:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6655 Hi all, I'm compiling the following VHDL to make a simple ROM, and I'm getting these errors: # Error: COMP96_0305: SUBONE_MODULE_VHDL.vhd : (93, 23): Cannot find function "TO_INTEGER" for these actuals. # Error: COMP96_0138: SUBONE_MODULE_VHDL.vhd : (93, 23): The index types in the reference to the array object are incompatible with its range type. I'm using Active-HDL 9.2. This was based off an example I got online, but I had to switch to the NUMERIC_STD IEEE library because I want to synthesize this. Thanks! library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity SUBONE_MODULE_VHDL is port( addr : in STD_LOGIC_VECTOR(4 downto 0); clk : in STD_LOGIC; dout : out STD_LOGIC_VECTOR(4 downto 0) ); end SUBONE_MODULE_VHDL; --}} End of automatically maintained section architecture SUBONE_MODULE_VHDL of SUBONE_MODULE_VHDL is -- enter your statements here -- type ROM_Array is array (0 to 31) of std_logic_vector(4 downto 0); constant Content: ROM_Array := ( 0 => "10011", -- Suppose ROM has 1 => "00000", -- prestored value 2 => "00001", -- like this table 3 => "00010", -- 4 => "00011", -- 5 => "00100", -- 6 => "00101", -- 7 => "00110", -- 8 => "00111", -- 9 => "01000", -- 10 => "01001", -- 11 => "01010", -- 12 => "01011", -- 13 => "01100", -- 14 => "01101", -- 15 => "01110", -- 16 => "01111", -- 17 => "01110", -- 18 => "01110", -- 19 => "01110", -- 20 => "01110", -- 21 => "00000", -- 22 => "00001", -- 23 => "00010", -- 24 => "00011", -- 25 => "00100", -- 26 => "00101", -- 27 => "00110", -- 28 => "00111", -- 29 => "01000", -- 30 => "01001", -- 31 => "01010", -- OTHERS => "00000" ); begin process(clk, addr) variable addr : integer := 0; begin if( clk'event and clk = '1' ) then dout <= Content(TO_INTEGER(addr)); end if; end process; end SUBONE_MODULE_VHDL; From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.86.200 with SMTP id t8mr2407438qal.0.1371264448992; Fri, 14 Jun 2013 19:47:28 -0700 (PDT) X-Received: by 10.49.105.229 with SMTP id gp5mr152250qeb.35.1371264448916; Fri, 14 Jun 2013 19:47:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!j2no239887qak.0!news-out.google.com!y6ni2876qax.0!nntp.google.com!j2no239880qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Jun 2013 19:47:28 -0700 (PDT) In-Reply-To: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.242.197 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: KJ Injection-Date: Sat, 15 Jun 2013 02:47:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6656 You have... dout <=3D Content(TO_INTEGER(addr)); should be... dout <=3D Content(TO_INTEGER(unsigned(addr))); The reason is that addr is defined to be a std_logic_vector. Std_logic_vec= tor has no numeric interpretation it is just an arbitrary collection of bit= s. By casting it as 'unsigned' you are saying to interpret it as an unsign= ed numeric quantity which can then be converted to an integer value. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.66.121.168 with SMTP id ll8mr725398pab.38.1371272453390; Fri, 14 Jun 2013 22:00:53 -0700 (PDT) X-Received: by 10.49.12.141 with SMTP id y13mr156078qeb.41.1371272452965; Fri, 14 Jun 2013 22:00:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.albasani.net!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!x10no550636pbg.1!news-out.google.com!e10ni6983pbm.0!nntp.google.com!x10no550634pbg.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Jun 2013 22:00:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.111.11.101; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 68.111.11.101 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e8e53a2-b0c5-4b7e-99f7-d9d1a1276589@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Sat, 15 Jun 2013 05:00:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6657 Thank you so much! I'll try it ASAP and report back! On Friday, June 14, 2013 7:47:28 PM UTC-7, KJ wrote: > You have... >=20 >=20 >=20 > dout <=3D Content(TO_INTEGER(addr)); >=20 >=20 >=20 > should be... >=20 >=20 >=20 > dout <=3D Content(TO_INTEGER(unsigned(addr))); >=20 >=20 >=20 > The reason is that addr is defined to be a std_logic_vector. Std_logic_v= ector has no numeric interpretation it is just an arbitrary collection of b= its. By casting it as 'unsigned' you are saying to interpret it as an unsi= gned numeric quantity which can then be converted to an integer value. >=20 >=20 >=20 > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.57.65 with SMTP id b1mr4670518qah.2.1371473865906; Mon, 17 Jun 2013 05:57:45 -0700 (PDT) X-Received: by 10.49.40.167 with SMTP id y7mr117289qek.36.1371473865827; Mon, 17 Jun 2013 05:57:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bw2no1977135qab.0!news-out.google.com!y6ni2993qax.0!nntp.google.com!j2no485422qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 05:57:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Andy Injection-Date: Mon, 17 Jun 2013 12:57:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1307 Xref: mx05.eternal-september.org comp.lang.vhdl:6658 Travis, You also need to remove the unused variable declaration for addr in the process. It is hiding the addr port. Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.236.20.83 with SMTP id o59mr8949074yho.28.1371475935805; Mon, 17 Jun 2013 06:32:15 -0700 (PDT) X-Received: by 10.49.35.68 with SMTP id f4mr359744qej.0.1371475935708; Mon, 17 Jun 2013 06:32:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no488271qak.0!news-out.google.com!y6ni3347qax.0!nntp.google.com!bw2no1979646qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 06:32:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.132.239.130; posting-account=w8wfdgoAAACP6NAlrRg-j4-svQ-oD2K9 NNTP-Posting-Host: 95.132.239.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> Subject: How can I avoid variable in this loop (outside the process)? From: =?UTF-8?Q?troll_green=D0=AA?= Injection-Date: Mon, 17 Jun 2013 13:32:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1415 Lines: 11 Xref: mx05.eternal-september.org comp.lang.vhdl:6659 Good day to all! How can I avoid variable in this loop (outside the process)? variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) := (others => '0'); for i in 0 to ADRESS_WIDTH-2 loop var1 := var1 + '1'; with r_addr select fifo_data_out <= array_reg(i) when var1, end loop; array_reg(ADRESS_WIDTH-1) when others; Thanks! From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.57.65 with SMTP id b1mr5326851qah.2.1371484247477; Mon, 17 Jun 2013 08:50:47 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr360731qeg.5.1371484247462; Mon, 17 Jun 2013 08:50:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no501663qak.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no501654qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 08:50:47 -0700 (PDT) In-Reply-To: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.132.239.130; posting-account=w8wfdgoAAACP6NAlrRg-j4-svQ-oD2K9 NNTP-Posting-Host: 95.132.239.130 References: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> Subject: Re: How can I avoid variable in this loop (outside the process)? From: =?UTF-8?Q?troll_green=D0=AA?= Injection-Date: Mon, 17 Jun 2013 15:50:47 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2514 Xref: mx05.eternal-september.org comp.lang.vhdl:6660 =D0=BF=D0=BE=D0=BD=D0=B5=D0=B4=D0=B5=D0=BB=D1=8C=D0=BD=D0=B8=D0=BA, 17 =D0= =B8=D1=8E=D0=BD=D1=8F 2013=C2=A0=D0=B3., 16:32:15 UTC+3 =D0=BF=D0=BE=D0=BB= =D1=8C=D0=B7=D0=BE=D0=B2=D0=B0=D1=82=D0=B5=D0=BB=D1=8C troll green=D0=AA = =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BB: > Good day to all! >=20 > How can I avoid variable in this loop (outside the process)? >=20 >=20 >=20 > variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) :=3D (others = =3D> '0'); >=20 > for i in 0 to ADRESS_WIDTH-2 loop >=20 > var1 :=3D var1 + '1'; >=20 > with r_addr select >=20 > fifo_data_out <=3D array_reg(i) when var1, >=20 > end loop; >=20 > array_reg(ADRESS_WIDTH-1) when others; >=20 >=20 >=20 > Thanks! This version (in process) isn't correct too - syntax errors process (r_addr, r_addr1, fifo_data_out, array_reg, r_data1) variable var1 : std_logic_vector (ADRESS_WIDTH-1 downto 0) :=3D (others =3D= > '0'); begin case r_addr is when "0000000000" =3D> fifo_data_out <=3D array_reg(0); for i in 1 to ADRESS_WIDTH-2 loop when var1 =3D> fifo_data_out <=3D array_reg(i); var1 :=3D var1 + '1'; end loop; when others =3D> fifo_data_out <=3D array_reg(ADRESS_WIDTH-1); end case; From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.129.196 with SMTP id p4mr8932869qas.6.1371484439939; Mon, 17 Jun 2013 08:53:59 -0700 (PDT) X-Received: by 10.50.9.40 with SMTP id w8mr464561iga.4.1371484439906; Mon, 17 Jun 2013 08:53:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bw2no1991316qab.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no501970qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 08:53:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <663d90c8-293b-48a8-842d-4664e97ad347@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Mon, 17 Jun 2013 15:53:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1966 Xref: mx05.eternal-september.org comp.lang.vhdl:6661 Hi Andy, I just tried Kevin's solution, noticed the error, got bummed, noticed your = solution, and now all is fixed. Thank you both! Andy & Kevin, if I could ask, it appears I was interpreting what "variable = addr : integer;" was doing. I thought it was providing context for use of "= addr" within the process block, but this is apparently incorrect. Do you ha= ve a good reference or pointer for these types of things?=20 Thanks again! On Monday, June 17, 2013 5:57:45 AM UTC-7, Andy wrote: > Travis, >=20 >=20 >=20 > You also need to remove the unused variable declaration for addr in the p= rocess. It is hiding the addr port. >=20 >=20 >=20 > Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.42.141 with SMTP id s13mr8948087qae.3.1371484588746; Mon, 17 Jun 2013 08:56:28 -0700 (PDT) X-Received: by 10.50.20.136 with SMTP id n8mr463692ige.5.1371484588665; Mon, 17 Jun 2013 08:56:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no1991592qab.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no502215qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 08:56:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: kevin.neilson@xilinx.com Injection-Date: Mon, 17 Jun 2013 15:56:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx05.eternal-september.org comp.lang.vhdl:6662 Another option is to make the input 'unsigned', which is a better type in this context. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.174.145 with SMTP id t17mr9199724qaz.4.1371488963225; Mon, 17 Jun 2013 10:09:23 -0700 (PDT) X-Received: by 10.182.61.6 with SMTP id l6mr3772obr.7.1371488963055; Mon, 17 Jun 2013 10:09:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.freenet.ag!news2.euro.net!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bw2no1998512qab.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no509528qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 10:09:22 -0700 (PDT) In-Reply-To: <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <36f12666-7c5f-4058-beb0-1e055c474e20@googlegroups.com> Subject: Re: How can I avoid variable in this loop (outside the process)? From: Andy Injection-Date: Mon, 17 Jun 2013 17:09:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1478 Xref: mx05.eternal-september.org comp.lang.vhdl:6663 It looks like you have an array of registers that your are trying to index with an address, but there are fewer registers than address values. Try this: for i in reg_array'range loop if i = unsigned(addr) then fifo_data_out <= reg_array(i); end if; end loop; Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.236.20.83 with SMTP id o59mr9542411yho.28.1371489538668; Mon, 17 Jun 2013 10:18:58 -0700 (PDT) X-Received: by 10.49.87.70 with SMTP id v6mr376102qez.25.1371489538525; Mon, 17 Jun 2013 10:18:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no510572qak.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no510567qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 10:18:58 -0700 (PDT) In-Reply-To: <663d90c8-293b-48a8-842d-4664e97ad347@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <663d90c8-293b-48a8-842d-4664e97ad347@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <91f4b18f-5e69-4552-a1d0-8d5c7f72049a@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Andy Injection-Date: Mon, 17 Jun 2013 17:18:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1924 Xref: mx05.eternal-september.org comp.lang.vhdl:6664 Variables are storage objects that are usually local to processes or subpro= grams where they are declared. They are assigned using ":=3D" instead of "= <=3D". Their value updates immediately upon execution of the assignment sta= tement, instead of waiting until the process suspends, like signal values d= o.=20 Most VHDL texts cover variables, but most will tell you not to use them for= RTL (or at least not for registers in RTL), which is unfortunate, since va= riables are quite powerful for both combinatorial and register logic, once = you know how to use them. Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.129.196 with SMTP id p4mr9284496qas.6.1371490083914; Mon, 17 Jun 2013 10:28:03 -0700 (PDT) X-Received: by 10.50.164.200 with SMTP id ys8mr480069igb.14.1371490083827; Mon, 17 Jun 2013 10:28:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!bw2no2000177qab.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no511450qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 10:28:03 -0700 (PDT) In-Reply-To: <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Andy Injection-Date: Mon, 17 Jun 2013 17:28:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6665 What Kevin said (make addr unsigned). Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned. Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Chasing Bugs in the Fog Date: Mon, 17 Jun 2013 20:00:01 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 17 Jun 2013 23:55:08 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="07e0113e7292c0c4d172540aaeca7bec"; logging-data="8007"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/342PMz4cqciBJF//TXF2e" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 Cancel-Lock: sha1:UB5tZr3Ux7dmOmC4ACb9g4Psq0s= Xref: mx05.eternal-september.org comp.lang.vhdl:6666 comp.arch.fpga:19140 I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it around I've concluded it must be in the FPGA code. I didn't think it was in the VHDL because it had been simulated well and the nature of the bug is an occasional dropped character on the receive side. Who can't design a UART? Well, it could be in the handshake with the state machine, but still... So I finally got around to adding some debug signals which I would monitor on an analyzer and guess what, the bug is gone! I *hate* when that happens. I can change the code so the debug signals only appear when a control register is set to enable them, but still, I don't like this. I want to know what is causing this DURN THING! Anyone see this happen to them before? Oh yeah, someone in another thread (that I can't find, likely because I don't recall the group I posted it in) suggested I add synchronizing FFs to the serial data in. Sure enough I had forgotten to do that. Maybe that was the fix... of course! It wasn't metastability, I bet it was feeding multiple bits of the state machine! Durn, I never make that sort of error. Thanks to whoever it was that suggested the obvious that I had forgotten. -- Rick From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Chasing Bugs in the Fog Date: Mon, 17 Jun 2013 17:14:58 -0700 Organization: Highland Technology, Inc. Lines: 44 Message-ID: <20130617171458.6578c59c@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="7a89dde196082de0e965aec8c036e07b"; logging-data="15685"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+a8iwLVUuyUOqnHEhxCHCA" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:zqP8MnxjX+OJvkXzWZ0ykoTfsUg= Xref: mx05.eternal-september.org comp.lang.vhdl:6667 comp.arch.fpga:19141 On Mon, 17 Jun 2013 20:00:01 -0400 rickman wrote: > So I finally got around to adding some debug signals which I would > monitor on an analyzer and guess what, the bug is gone! I *hate* when > that happens. I can change the code so the debug signals only appear > when a control register is set to enable them, but still, I don't like > this. I want to know what is causing this DURN THING! > > Anyone see this happen to them before? > > Oh yeah, someone in another thread (that I can't find, likely because I > don't recall the group I posted it in) suggested I add synchronizing FFs > to the serial data in. Sure enough I had forgotten to do that. Maybe > that was the fix... of course! It wasn't metastability, I bet it was > feeding multiple bits of the state machine! Durn, I never make that > sort of error. Thanks to whoever it was that suggested the obvious that > I had forgotten. > > -- > > Rick Not metastability, a race condition. Asynchronous external input headed to multiple clocked elements, each of which it reaches via a different path with a different delay. When you added debugging signals you changed the netlist, which changed the place and route, making unpredictable changes to those delays. In this case, it happened to push it into a place where _as far as you tested_, it seems happy. But it's still unsafe, because as you change other parts of the design, the P&R of that section will still change anyhow, and you start getting my favorite situation, the problem that comes and goes based on entirely unrelated factors. The fix you fixed fixes it. When you resynchronized it on the same clock as you're running around the rest of the logic, you forced that path to become timing constrained. As such, the P&R takes it upon itself to make sure that the timing of that route is irrelevant with respect to the clock period, and your problem goes away for good. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr10854474qab.8.1371518356419; Mon, 17 Jun 2013 18:19:16 -0700 (PDT) X-Received: by 10.50.9.40 with SMTP id w8mr535152iga.4.1371518356339; Mon, 17 Jun 2013 18:19:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2043709qab.0!news-out.google.com!y6ni3349qax.0!nntp.google.com!j2no559950qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Jun 2013 18:19:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.65.207.102; posting-account=BizAawoAAAAeM9txHVd8Xw39M3VO8TJW NNTP-Posting-Host: 150.65.207.102 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> Subject: Ask about finding maximum and second's maximum number in array is given. From: phanhuyich Injection-Date: Tue, 18 Jun 2013 01:19:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: mx05.eternal-september.org comp.lang.vhdl:6668 I am starting to study VHDL. Now, I have to do an exercise with the following content: I have to define an array of 10 elements ( 8 bit range) ([3,4,2,8,9,0,1,5,7,6] for example). And 10 elements were imported to within 10 clock cycles. The question is find the maximum number and second maximum number in this array after 10 clock cycle. Anyone help to show me the method to solve it using VHDL ? Thank you. From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.freenet.ag!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <51c08b85$0$26904$e4fe514c@dreader37.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: How can I avoid variable in this loop (outside the process)? Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 18:32:05 +0200 References: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> <36f12666-7c5f-4058-beb0-1e055c474e20@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 21 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1371573125 dreader37.news.xs4all.nl 26904 puiterl/195.242.97.150:42486 Xref: mx05.eternal-september.org comp.lang.vhdl:6669 Andy wrote: > It looks like you have an array of registers that your are trying to index > with an address, but there are fewer registers than address values. > > Try this: > > for i in reg_array'range loop > if i = unsigned(addr) then > fifo_data_out <= reg_array(i); > end if; > end loop; Except for the needless burning of simulation CPU cycles in the loop, I think the above is equivalent with: a := to_integer(unsigned(addr)); if a >= reg_array'low and a <= reg_array'high then fifo_data_out <= reg_array(a); end if; From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <51c08d82$0$26904$e4fe514c@dreader37.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: vmkr segmentation fault Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 18:40:34 +0200 References: Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 15 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1371573634 dreader37.news.xs4all.nl 26904 puiterl/195.242.97.150:42603 Xref: mx05.eternal-september.org comp.lang.vhdl:6670 alb wrote: > Hi everyone, > > I'm trying to use vmkr to generate Makefiles to handle dependencies. > p.s.: it seems like this software dates back in the 1993, which may > explain the list of warnings. If anyone knows a more recent one that > could be helpful. I would suggest using vmk: http://vmk.sourceforge.net/ I have been using it for years. -- Paul. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.174.145 with SMTP id t17mr13443734qaz.4.1371573946127; Tue, 18 Jun 2013 09:45:46 -0700 (PDT) X-Received: by 10.50.114.138 with SMTP id jg10mr691896igb.16.1371573946088; Tue, 18 Jun 2013 09:45:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!bw2no2126088qab.0!news-out.google.com!y6ni3493qax.0!nntp.google.com!j2no649428qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 09:45:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Tue, 18 Jun 2013 16:45:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6671 Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update. On Monday, June 17, 2013 10:28:03 AM UTC-7, Andy wrote: > What Kevin said (make addr unsigned). > > > > Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned. > > > > Andy From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.215.68 with SMTP id hd4mr13538198qab.5.1371574748801; Tue, 18 Jun 2013 09:59:08 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr479992qeg.5.1371574748555; Tue, 18 Jun 2013 09:59:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!bw2no2127619qab.0!news-out.google.com!y6ni3493qax.0!nntp.google.com!j2no651055qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 09:59:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.11; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.11 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <536bce40-8b93-4f9f-98db-b1a72b4478ba@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: kevin.neilson@xilinx.com Injection-Date: Tue, 18 Jun 2013 16:59:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6672 And who knows how much 2008 Vivado really supports. Probably not much. Use Synplify, if possible. The VHDL 2008 additions are indispensable. One thing I could not do without is the fixed-point package. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.42.141 with SMTP id s13mr13752914qae.3.1371579067495; Tue, 18 Jun 2013 11:11:07 -0700 (PDT) X-Received: by 10.50.67.74 with SMTP id l10mr716193igt.0.1371579067444; Tue, 18 Jun 2013 11:11:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no659078qak.0!news-out.google.com!y6ni3493qax.0!nntp.google.com!j2no659072qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 11:11:06 -0700 (PDT) In-Reply-To: <536bce40-8b93-4f9f-98db-b1a72b4478ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> <536bce40-8b93-4f9f-98db-b1a72b4478ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0c69bc34-8562-405b-81d1-375ac1cd69de@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Tue, 18 Jun 2013 18:11:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1896 Lines: 4 Xref: mx05.eternal-september.org comp.lang.vhdl:6673 I will examine the Synopsys tools; I'm converting a design that is largely schematic based in Active-HDL (that has components that date back to Active-CAD) to VHDL, and there are numerous headaches. On Tuesday, June 18, 2013 9:59:08 AM UTC-7, kevin....@xilinx.com wrote: > And who knows how much 2008 Vivado really supports. Probably not much. Use Synplify, if possible. The VHDL 2008 additions are indispensable. One thing I could not do without is the fixed-point package. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.59.205 with SMTP id m13mr13795316qah.7.1371579639817; Tue, 18 Jun 2013 11:20:39 -0700 (PDT) X-Received: by 10.50.132.65 with SMTP id os1mr718429igb.13.1371579638530; Tue, 18 Jun 2013 11:20:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2136235qab.0!news-out.google.com!y6ni3493qax.0!nntp.google.com!j2no660260qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 11:20:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: signal ram: ram_t := (others => (others '0')); From: Travis Injection-Date: Tue, 18 Jun 2013 18:20:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 45 Xref: mx05.eternal-september.org comp.lang.vhdl:6674 I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site: http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html The code I'm looking at is as follows: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_example is port (Clk : in std_logic; address : in integer; we : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM --with each element being 8 bit wide. type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => '0')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(we='1') then ram(address) <= data_i; end if; data_o <= ram(address); end if; END PROCESS; end Behavioral; But I had a question about this part: signal ram : ram_t := (others => (others => '0')); I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description? Thanks all, -Travis From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: signal ram: ram_t := (others => (others '0')); Date: Tue, 18 Jun 2013 11:35:17 -0700 Organization: Highland Technology, Inc. Lines: 57 Message-ID: <20130618113517.49c3c1da@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="7a89dde196082de0e965aec8c036e07b"; logging-data="22580"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/SAx7ogbL7+NfzibStTAc3" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:g/kGk6yrQvsXNfnLJkOnb1oipac= Xref: mx05.eternal-september.org comp.lang.vhdl:6675 On Tue, 18 Jun 2013 11:20:38 -0700 (PDT) Travis wrote: > I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site: > http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html > > The code I'm looking at is as follows: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > > entity ram_example is > port (Clk : in std_logic; > address : in integer; > we : in std_logic; > data_i : in std_logic_vector(7 downto 0); > data_o : out std_logic_vector(7 downto 0) > ); > end ram_example; > > architecture Behavioral of ram_example is > > --Declaration of type and signal of a 256 element RAM > --with each element being 8 bit wide. > type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); > signal ram : ram_t := (others => (others => '0')); > > begin > > --process for read and write operation. > PROCESS(Clk) > BEGIN > if(rising_edge(Clk)) then > if(we='1') then > ram(address) <= data_i; > end if; > data_o <= ram(address); > end if; > END PROCESS; > > end Behavioral; > > But I had a question about this part: > signal ram : ram_t := (others => (others => '0')); > > I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description? > > Thanks all, > -Travis It's just declaring that the initial contents of the RAM should be all zeros. You can actually assign the initial values to be whatever you'd like. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: signal ram: ram_t := (others => (others '0')); Date: Tue, 18 Jun 2013 14:54:30 -0400 Organization: Alacron, Inc. Lines: 70 Message-ID: References: <20130618113517.49c3c1da@rg.highlandtechnology.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Jun 2013 18:50:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="8936"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+9uIm6EpvANe46CObb/sc120ni2MCVXnI=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <20130618113517.49c3c1da@rg.highlandtechnology.com> Cancel-Lock: sha1:I0IG6yuSnWHGNql8FcrUh+K+SOY= Xref: mx05.eternal-september.org comp.lang.vhdl:6676 Rob Gaddi wrote: > On Tue, 18 Jun 2013 11:20:38 -0700 (PDT) > Travis wrote: > >> I'm examining the VHDL for block and distributed ram on Xilinx, and a short google search led me to this site: >> http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html >> >> The code I'm looking at is as follows: >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> >> entity ram_example is >> port (Clk : in std_logic; >> address : in integer; >> we : in std_logic; >> data_i : in std_logic_vector(7 downto 0); >> data_o : out std_logic_vector(7 downto 0) >> ); >> end ram_example; >> >> architecture Behavioral of ram_example is >> >> --Declaration of type and signal of a 256 element RAM >> --with each element being 8 bit wide. >> type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); >> signal ram : ram_t := (others => (others => '0')); >> >> begin >> >> --process for read and write operation. >> PROCESS(Clk) >> BEGIN >> if(rising_edge(Clk)) then >> if(we='1') then >> ram(address) <= data_i; >> end if; >> data_o <= ram(address); >> end if; >> END PROCESS; >> >> end Behavioral; >> >> But I had a question about this part: >> signal ram : ram_t := (others => (others => '0')); >> >> I assume this is necessary because it helps the synthesizer make some optimizations and better infer LUTs or block ram, but I don't quite 'understand' it. I can parrot it in the meantime, but maybe someone out there has a good description? >> >> Thanks all, >> -Travis > > It's just declaring that the initial contents of the RAM should be all > zeros. You can actually assign the initial values to be whatever you'd > like. > For _most_ Xilinx FPGA famlies, the bitstream initializes all memories by default. If you don't specify a value to initialize the RAMs, then it will be all zeroes in the bitstream. This also helps to reduce bitstream size when using compression. Explicitly choosing all zeroes, when you really don't care about the initial value has the effect of making simulation match the hardware. If instead you wanted to make sure you don't read uninitialized memory and rely on its value, I've seen something like: signal ram : ram_t := (others => (others => 'U')); -- Gabor From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.215.68 with SMTP id hd4mr13918qab.5.1371582281506; Tue, 18 Jun 2013 12:04:41 -0700 (PDT) X-Received: by 10.50.127.231 with SMTP id nj7mr731615igb.17.1371582281425; Tue, 18 Jun 2013 12:04:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!j2no665442qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no665431qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 12:04:40 -0700 (PDT) In-Reply-To: <0c69bc34-8562-405b-81d1-375ac1cd69de@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.11; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.11 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> <536bce40-8b93-4f9f-98db-b1a72b4478ba@googlegroups.com> <0c69bc34-8562-405b-81d1-375ac1cd69de@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7f37ca72-ebe6-4ddc-8473-96803e3474f5@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: kevin.neilson@xilinx.com Injection-Date: Tue, 18 Jun 2013 19:04:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6677 I've had to do the same thing, but years ago. I assumed nobody was using schematics anymore. I do see a lot of HDL that looks like schematic netlists. From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Chasing Bugs in the Fog Date: Tue, 18 Jun 2013 17:45:18 -0400 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <20130617171458.6578c59c@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Jun 2013 21:40:22 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="020435d04e00c077c9a9c520be93b93f"; logging-data="2805"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jXyfwipc25C6PfGZBcTdY" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <20130617171458.6578c59c@rg.highlandtechnology.com> Cancel-Lock: sha1:tbAObaBVyDfXVUoRvqiaR3/11HY= Xref: mx05.eternal-september.org comp.lang.vhdl:6678 comp.arch.fpga:19148 On 6/17/2013 8:14 PM, Rob Gaddi wrote: > On Mon, 17 Jun 2013 20:00:01 -0400 > rickman wrote: > >> So I finally got around to adding some debug signals which I would >> monitor on an analyzer and guess what, the bug is gone! I *hate* when >> that happens. I can change the code so the debug signals only appear >> when a control register is set to enable them, but still, I don't like >> this. I want to know what is causing this DURN THING! >> >> Anyone see this happen to them before? >> >> Oh yeah, someone in another thread (that I can't find, likely because I >> don't recall the group I posted it in) suggested I add synchronizing FFs >> to the serial data in. Sure enough I had forgotten to do that. Maybe >> that was the fix... of course! It wasn't metastability, I bet it was >> feeding multiple bits of the state machine! Durn, I never make that >> sort of error. Thanks to whoever it was that suggested the obvious that >> I had forgotten. >> >> -- >> >> Rick > > Not metastability, a race condition. Asynchronous external input > headed to multiple clocked elements, each of which it reaches via a > different path with a different delay. > > When you added debugging signals you changed the netlist, which changed > the place and route, making unpredictable changes to those delays. No, when changing the debug output I added the synchronization FFs which fixed the problem. My point was that when the other poster suggested that I need to sync to the clock I mistook that for metastability forgetting that the input went to multiple sections of logic. So actually I made the same mistake twice... lol > In > this case, it happened to push it into a place where _as far as you > tested_, it seems happy. But it's still unsafe, because as you change > other parts of the design, the P&R of that section will still change > anyhow, and you start getting my favorite situation, the problem that > comes and goes based on entirely unrelated factors. > > The fix you fixed fixes it. When you resynchronized it on the same > clock as you're running around the rest of the logic, you forced that > path to become timing constrained. As such, the P&R takes it upon > itself to make sure that the timing of that route is irrelevant with > respect to the clock period, and your problem goes away for good. Just to make sure of what was what (it has been two years since I last worked with this design) I pulled the FFs out and added back just one. Sure enough the bug reappears with no FFs, but goes away with just one. The added debug info available allowed me to see exactly the error and sure enough, when a start bit comes in there is a chance that the two counters are not properly set and the error shows up in the center of the bit where the current contents of the shift register are moved into the holding register as a new char. I guess what most likely happened is that when I wrote the UART code I assumed the sync FFs would be external and when I wrote the wrapper code I assumed the FFs were inside the UART. In other words, I didn't have a proper spec and never gave this problem proper consideration. I will revisit this design and look at the other inputs. No reason to assume I didn't make the same mistake elsewhere. -- Rick From newsfish@newsfish Tue Dec 29 16:42:58 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp3-1.free.fr!not-for-mail Date: Wed, 19 Jun 2013 00:13:41 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Chasing Bugs in the Fog References: <20130617171458.6578c59c@rg.highlandtechnology.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <51c0db95$0$18755$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 19 Jun 2013 00:13:41 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1371593621 news-1.free.fr 18755 88.185.146.198:4165 X-Complaints-To: abuse@proxad.net Xref: mx05.eternal-september.org comp.lang.vhdl:6679 comp.arch.fpga:19150 Le 18/06/2013 23:45, rickman a écrit : > I guess what most likely happened is that when I wrote the UART code I > assumed the sync FFs would be external and when I wrote the wrapper code > I assumed the FFs were inside the UART. In other words, I didn't have a > proper spec and never gave this problem proper consideration. Several years ago a young engineer reused my long proven UART code and modified it, carelessly removing the synchronizing FF. He came to see me and complained that my UART didn't work, it hung after some unpredictable time. I thought for a few minutes, guessed he probably had removed the FF and fixed his problem right away. Nicolas From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.86.200 with SMTP id t8mr781683qal.0.1371595747195; Tue, 18 Jun 2013 15:49:07 -0700 (PDT) X-Received: by 10.50.8.5 with SMTP id n5mr777650iga.7.1371595746976; Tue, 18 Jun 2013 15:49:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no689276qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no689271qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 15:49:06 -0700 (PDT) In-Reply-To: <7f37ca72-ebe6-4ddc-8473-96803e3474f5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> <536bce40-8b93-4f9f-98db-b1a72b4478ba@googlegroups.com> <0c69bc34-8562-405b-81d1-375ac1cd69de@googlegroups.com> <7f37ca72-ebe6-4ddc-8473-96803e3474f5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Travis Injection-Date: Tue, 18 Jun 2013 22:49:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2158 Lines: 7 Xref: mx05.eternal-september.org comp.lang.vhdl:6680 Schematics are great from a top down perspective, "The block does this", etc, but the design I'm converting has AND, OR, inverters, Virtex specific buffers, etc sprinkled throughout it. We're using Active-HDL, and we have uncovered SO many problems with the tool it is ridiculous. Apparently so few people do it this way they're dropping support for updated Xilinx schematic input in Active-HDL 9.3. On Tuesday, June 18, 2013 12:04:40 PM UTC-7, kevin....@xilinx.com wrote: > I've had to do the same thing, but years ago. I assumed nobody was using schematics anymore. I do see a lot of HDL that looks like schematic netlists. From newsfish@newsfish Tue Dec 29 16:42:58 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr1024552qab.8.1371601290873; Tue, 18 Jun 2013 17:21:30 -0700 (PDT) X-Received: by 10.50.20.162 with SMTP id o2mr12159ige.9.1371601290794; Tue, 18 Jun 2013 17:21:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no698236qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no698230qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 17:21:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.169.112.122; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 206.169.112.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> Subject: Distributed Ram with Initial Values (Virtex) From: Travis Injection-Date: Wed, 19 Jun 2013 00:21:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1426 Lines: 8 Xref: mx05.eternal-september.org comp.lang.vhdl:6681 Hi all,=20 I'm trying to implement a distributed RAM with initial values in VHDL. I'm = targeting a Virtex-5 (that part doesn't matter on comp.lang.vhdl...) - is t= here an example somewhere? I know that some of the Virtex components do hav= e an initial value that can be passed in using generics - should I tie this= to a global reset or something in order to get the behavior I want? Thanks! From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Distributed Ram with Initial Values (Virtex) Date: Tue, 18 Jun 2013 22:29:21 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 19 Jun 2013 02:25:07 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="77278c5c28cacf475adc81b3fe18ce7e"; logging-data="13319"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+fP7g6ydtRgcIS9KSwQoKD" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> Cancel-Lock: sha1:bHMVPYt3gxuNF8E0kAYzZ5yLpII= Xref: mx05.eternal-september.org comp.lang.vhdl:6682 On 6/18/2013 8:21 PM, Travis wrote: > Hi all, > > I'm trying to implement a distributed RAM with initial values in VHDL. I'm targeting a Virtex-5 (that part doesn't matter on comp.lang.vhdl...) - is there an example somewhere? I know that some of the Virtex components do have an initial value that can be passed in using generics - should I tie this to a global reset or something in order to get the behavior I want? > > Thanks! > I assume by "with initial values" you mean some values other than all zeroes as in your last thread. Have you looked in the XST user guide for inferring ROM? I know it's possible to load the initial values from a file, as well as to list them explicitly in the declaration (gets messy for larger memories). -- Gabor From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.59.205 with SMTP id m13mr2087670qah.7.1371622272571; Tue, 18 Jun 2013 23:11:12 -0700 (PDT) X-Received: by 10.49.24.208 with SMTP id w16mr20789qef.37.1371622272547; Tue, 18 Jun 2013 23:11:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2251693qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no780636qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Jun 2013 23:11:12 -0700 (PDT) In-Reply-To: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Distributed Ram with Initial Values (Virtex) From: goouse99@gmail.com Injection-Date: Wed, 19 Jun 2013 06:11:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: mx05.eternal-september.org comp.lang.vhdl:6683 Am Mittwoch, 19. Juni 2013 02:21:30 UTC+2 schrieb Travis: > Hi all,=20 >=20 >=20 >=20 > I'm trying to implement a distributed RAM with initial values in VHDL. I'= m targeting a Virtex-5 (that part doesn't matter on comp.lang.vhdl...) - is= there an example somewhere? I know that some of the Virtex components do h= ave an initial value that can be passed in using generics - should I tie th= is to a global reset or something in order to get the behavior I want? >=20 >=20 >=20 > Thanks! Hi, whatever way you choose to get the initial data into your RAM/ROM (INIT or = file, actually XST also supports the use of file_io functions but this is n= ot standard VHDL compliant) this has nothing to do with the reset. The data comes from the configuration bitstream and is only loaded once dur= ing configuration. Any kind of reset (if possible at all for a RAM) will no= t reload that initial data. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.57.65 with SMTP id b1mr3305950qah.2.1371644677709; Wed, 19 Jun 2013 05:24:37 -0700 (PDT) X-Received: by 10.49.17.42 with SMTP id l10mr46679qed.10.1371644677647; Wed, 19 Jun 2013 05:24:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!j2no812472qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no812467qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 05:24:37 -0700 (PDT) In-Reply-To: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.21.33.69; posting-account=P4tq1QoAAAA5jIVtSJQ7dEPdfnyZ9yGA NNTP-Posting-Host: 78.21.33.69 References: <6f569218-c417-451d-811e-a9778d2c2675@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Signal xx cannot be synthesized, bad synchronous description error From: robbevt@gmail.com Injection-Date: Wed, 19 Jun 2013 12:24:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6684 Hello Thank you all for your input, i will certainly be able to make it work with all this new information. Thanks! From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr3833253qab.8.1371654613129; Wed, 19 Jun 2013 08:10:13 -0700 (PDT) X-Received: by 10.49.116.132 with SMTP id jw4mr72588qeb.33.1371654613057; Wed, 19 Jun 2013 08:10:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no829622qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no829618qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 08:10:12 -0700 (PDT) In-Reply-To: <51c08b85$0$26904$e4fe514c@dreader37.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> <36f12666-7c5f-4058-beb0-1e055c474e20@googlegroups.com> <51c08b85$0$26904$e4fe514c@dreader37.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73d118f3-a8a2-43de-8f6c-5f77d6345021@googlegroups.com> Subject: Re: How can I avoid variable in this loop (outside the process)? From: Andy Injection-Date: Wed, 19 Jun 2013 15:10:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1659 Xref: mx05.eternal-september.org comp.lang.vhdl:6685 Paul, In the (not recent) past, I've had problems with your approach creating significantly more (and slower) clock enable logic for fifo_data_out. For reasonable size reg_arrays, the simlation overhead of the loop is insignificant. Perhaps the synthesizer (Synplify in my case) has gotten better, since I have not tried your approach lately? Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.57.65 with SMTP id b1mr3896104qah.2.1371655024244; Wed, 19 Jun 2013 08:17:04 -0700 (PDT) X-Received: by 10.50.18.40 with SMTP id t8mr948667igd.3.1371655024139; Wed, 19 Jun 2013 08:17:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!bw2no2298426qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no830337qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 08:17:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <20130618113517.49c3c1da@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: signal ram: ram_t := (others => (others '0')); From: Andy Injection-Date: Wed, 19 Jun 2013 15:17:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6686 While the explicit 'U' initialization may be more readable (which is generally an admirable goal), it is not necessary. Per the LRM and the type definition, ram is initialized to (others => (others => 'U')) unless explicitly initialized otherwise. Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr3897751qab.8.1371655717757; Wed, 19 Jun 2013 08:28:37 -0700 (PDT) X-Received: by 10.182.129.47 with SMTP id nt15mr5825obb.13.1371655717682; Wed, 19 Jun 2013 08:28:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!bw2no2299741qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no831750qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 08:28:37 -0700 (PDT) In-Reply-To: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Distributed Ram with Initial Values (Virtex) From: Andy Injection-Date: Wed, 19 Jun 2013 15:28:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6687 Travis, Distributed RAM can be inferred from arrays just like block ram, except you can do combinatorial (non-registered) reads with distributed RAMs. Just initialize the array in its declaration, and those values will be stored in the ram(s) during configuration. You cannot reset ram contents on any FPGA that I know of. You can re-configure the FPGA though... Flash based FPGAs from MicroSemi do not support initial values on RAMs. There is no "configuration" phase in which to perform the initialization. Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.86.200 with SMTP id t8mr4325888qal.0.1371662796379; Wed, 19 Jun 2013 10:26:36 -0700 (PDT) X-Received: by 10.50.29.2 with SMTP id f2mr983215igh.12.1371662796338; Wed, 19 Jun 2013 10:26:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no844210qak.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no844199qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 10:26:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.111.11.101; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 68.111.11.101 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> Subject: Re: Distributed Ram with Initial Values (Virtex) From: Travis Injection-Date: Wed, 19 Jun 2013 17:26:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2406 Xref: mx05.eternal-september.org comp.lang.vhdl:6688 Hi Gabor,=20 Yes, this would be a RAM with initial values, but I was going to try to fit= it into distributed ram. Its 512x32 bits, so I was going to make it distri= buted. I will check the XST user guide, but I really wanted to make sure my= VHDL was synthesizable :) Thanks! On Tuesday, June 18, 2013 7:29:21 PM UTC-7, Gabor wrote: > On 6/18/2013 8:21 PM, Travis wrote: >=20 > > Hi all, >=20 > > >=20 > > I'm trying to implement a distributed RAM with initial values in VHDL. = I'm targeting a Virtex-5 (that part doesn't matter on comp.lang.vhdl...) - = is there an example somewhere? I know that some of the Virtex components do= have an initial value that can be passed in using generics - should I tie = this to a global reset or something in order to get the behavior I want? >=20 > > >=20 > > Thanks! >=20 > > >=20 > I assume by "with initial values" you mean some values other than >=20 > all zeroes as in your last thread. Have you looked in the XST >=20 > user guide for inferring ROM? I know it's possible to load the >=20 > initial values from a file, as well as to list them explicitly >=20 > in the declaration (gets messy for larger memories). >=20 >=20 >=20 > --=20 >=20 > Gabor From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.129.196 with SMTP id p4mr4319242qas.6.1371663023739; Wed, 19 Jun 2013 10:30:23 -0700 (PDT) X-Received: by 10.50.73.69 with SMTP id j5mr65164igv.14.1371663023698; Wed, 19 Jun 2013 10:30:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2311705qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no844611qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 10:30:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.111.11.101; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 68.111.11.101 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3528a1d9-855b-4839-8135-50e9ee45112c@googlegroups.com> Subject: Re: Distributed Ram with Initial Values (Virtex) From: Travis Injection-Date: Wed, 19 Jun 2013 17:30:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 30 Xref: mx05.eternal-september.org comp.lang.vhdl:6689 Hi Andy, Thank you, I will initialize the array in its declaration (that's what I did now, but I wanted to make sure it made sense for synthesis). I'm primarily targeting Xilinx devices; hopefully I'll get a chance to work with some other FPGAs at some point. -Travis On Wednesday, June 19, 2013 8:28:37 AM UTC-7, Andy wrote: > Travis, > > > > Distributed RAM can be inferred from arrays just like block ram, except you can do combinatorial (non-registered) reads with distributed RAMs. > > > > Just initialize the array in its declaration, and those values will be stored in the ram(s) during configuration. > > > > You cannot reset ram contents on any FPGA that I know of. You can re-configure the FPGA though... > > > > Flash based FPGAs from MicroSemi do not support initial values on RAMs. There is no "configuration" phase in which to perform the initialization. > > > > Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Distributed Ram with Initial Values (Virtex) Date: Wed, 19 Jun 2013 19:43:54 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 19 Jun 2013 23:38:57 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c17778a8cc17a4c37494527ac2854514"; logging-data="13016"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+QwkkZFfHhzvuApN6WeIpO" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> Cancel-Lock: sha1:gb+2gRnt9DDQBUSqcBhWZLnV0D8= Xref: mx05.eternal-september.org comp.lang.vhdl:6690 On 6/19/2013 1:26 PM, Travis wrote: > Hi Gabor, > > Yes, this would be a RAM with initial values, but I was going to try to fit it into distributed ram. Its 512x32 bits, so I was going to make it distributed. I will check the XST user guide, but I really wanted to make sure my VHDL was synthesizable :) I can't say I can see why you want to use distributed RAM rather than block RAM. I think 512 x 32 bits would use a lot of LUTs but would only use 2 block RAMs depending on the device family. Are you saving the block RAMs for something else? -- Rick From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.129.196 with SMTP id p4mr5398230qas.6.1371685764801; Wed, 19 Jun 2013 16:49:24 -0700 (PDT) X-Received: by 10.50.108.47 with SMTP id hh15mr269325igb.12.1371685764715; Wed, 19 Jun 2013 16:49:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2351905qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no886593qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Jun 2013 16:49:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.12; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.12 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Distributed Ram with Initial Values (Virtex) From: kevin.neilson@xilinx.com Injection-Date: Wed, 19 Jun 2013 23:49:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx05.eternal-september.org comp.lang.vhdl:6691 I'd agree. It would only be 1 16-kbit BRAM and it would be much faster. Putting this in distributed RAM would eat up a ton of CLBs and make a routing/placement mess. From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.59.205 with SMTP id m13mr6750284qah.7.1371714221725; Thu, 20 Jun 2013 00:43:41 -0700 (PDT) X-Received: by 10.49.15.40 with SMTP id u8mr58373qec.12.1371714221670; Thu, 20 Jun 2013 00:43:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!bw2no2391878qab.0!news-out.google.com!y6ni3510qax.0!nntp.google.com!j2no928542qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Jun 2013 00:43:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.111.11.101; posting-account=UHiw4woAAAAbJGES9P87sN_zClx0D-hZ NNTP-Posting-Host: 68.111.11.101 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Distributed Ram with Initial Values (Virtex) From: Travis Injection-Date: Thu, 20 Jun 2013 07:43:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6692 On Wednesday, June 19, 2013 4:49:24 PM UTC-7, kevin....@xilinx.com wrote: > I'd agree. It would only be 1 16-kbit BRAM and it would be much faster. Putting this in distributed RAM would eat up a ton of CLBs and make a routing/placement mess. Ah; I will put it into block ram if it would be more sensible, which it looks like it is! Thank you both! From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.freenet.ag!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <51c2d3b8$0$6354$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: How can I avoid variable in this loop (outside the process)? Newsgroups: comp.lang.vhdl Date: Thu, 20 Jun 2013 12:04:40 +0200 References: <2087d7de-7bb8-4c3e-9630-39285043aaca@googlegroups.com> <9cb78747-257c-4cd4-8f29-a649da97ff33@googlegroups.com> <36f12666-7c5f-4058-beb0-1e055c474e20@googlegroups.com> <51c08b85$0$26904$e4fe514c@dreader37.news.xs4all.nl> <73d118f3-a8a2-43de-8f6c-5f77d6345021@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 20 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1371722680 dreader35.news.xs4all.nl 6354 puiterl/195.242.97.150:54358 Xref: mx05.eternal-september.org comp.lang.vhdl:6693 Andy wrote: > Paul, > > In the (not recent) past, I've had problems with your approach creating > significantly more (and slower) clock enable logic for fifo_data_out. For > reasonable size reg_arrays, the simlation overhead of the loop is > insignificant. > > Perhaps the synthesizer (Synplify in my case) has gotten better, since I > have not tried your approach lately? Andy, To be honest, I did not think of any synthesis issues. I use VHDL for verification, so generally I am not bothered by limitations set by synthesizers. -- Paul. From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Distributed Ram with Initial Values (Virtex) Date: Thu, 20 Jun 2013 18:43:12 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Jun 2013 22:38:10 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="fe040945d7a723a2edac16ff8861b786"; logging-data="22282"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181FdkHceaiG3AUpLfvBOyE" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:kQ19NuNxOxTOPDTdO0xE7Y3tCLs= Xref: mx05.eternal-september.org comp.lang.vhdl:6694 On 6/20/2013 3:43 AM, Travis wrote: > On Wednesday, June 19, 2013 4:49:24 PM UTC-7, kevin....@xilinx.com wrote: >> I'd agree. It would only be 1 16-kbit BRAM and it would be much faster. Putting this in distributed RAM would eat up a ton of CLBs and make a routing/placement mess. > > Ah; I will put it into block ram if it would be more sensible, which it looks like it is! Thank you both! I think for the most part, as long as your coding allows it to be implemented in block RAM, the tool will automatically put it in block RAM. I'm not sure where they draw the line between using block RAM and using distributed RAM, but I'm sure it is a RAM that is smaller than 1 block which yours is not. -- Rick From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Cannot find function "TO_INTEGER" for these actuals Date: Wed, 19 Jun 2013 21:45:21 -0400 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Jun 2013 23:35:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="fe040945d7a723a2edac16ff8861b786"; logging-data="8278"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fce4SIjkU/7qjtETzHjzc" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:aucV/IJsnL1FIqa5ePn7ubI6Xik= Xref: mx05.eternal-september.org comp.lang.vhdl:6695 On 6/18/2013 12:45 PM, Travis wrote: > Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update. That is pretty amazing! I can't believe Xilinx is ignoring VHDL 2008. I am coding in VHDL 2008 and expect my tools to support that. I don't have any trouble with the Lattice tools including the Active-HDL simulator. I was working with the iceCube tool for the iCE40 parts, but haven't done anything with VHDL 2008 in the main line devices. I may try it with the current design I'm working on. I need to get a new laptop and will install the newer tools on it and give VHDL 2008 a run under Diamond. -- Rick From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr10510915qab.1.1371775067920; Thu, 20 Jun 2013 17:37:47 -0700 (PDT) X-Received: by 10.182.237.84 with SMTP id va20mr30087obc.5.1371775067884; Thu, 20 Jun 2013 17:37:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!bw2no2486638qab.0!news-out.google.com!y6ni3811qax.0!nntp.google.com!j2no1030764qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Jun 2013 17:37:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.12; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.12 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4db224da-1201-4599-97d4-22bdd64e440e@googlegroups.com> Subject: Re: Distributed Ram with Initial Values (Virtex) From: kevin.neilson@xilinx.com Injection-Date: Fri, 21 Jun 2013 00:37:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6696 If you want to target BRAM, you have to have at least one cycle of latency,= since the BRAM address is registered. (Distributed RAM can be fully combi= natorial.) The tools will then target BRAM if it's over a certain (small) = depth. You can add synthesis directives, but you probably don't need them. From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.42.141 with SMTP id s13mr13427657qae.3.1371825839563; Fri, 21 Jun 2013 07:43:59 -0700 (PDT) X-Received: by 10.50.117.106 with SMTP id kd10mr224290igb.14.1371825839529; Fri, 21 Jun 2013 07:43:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!j2no1101303qak.0!news-out.google.com!y6ni3811qax.0!nntp.google.com!j2no1101300qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Jun 2013 07:43:59 -0700 (PDT) In-Reply-To: <3cb54821@news.mhogaming.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.241.140.58; posting-account=YVSu9woAAABGuI1DA0wNMKvBvtdKpbOe NNTP-Posting-Host: 115.241.140.58 References: <3cb54821@news.mhogaming.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <012898a8-98f1-4648-a4a2-6e20b7b5975c@googlegroups.com> Subject: Re: Digital PLL From: rupesh.raghatate@gmail.com Injection-Date: Fri, 21 Jun 2013 14:43:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6697 On Thursday, 11 April 2002 13:53:01 UTC+5:30, Roberto Capobianco wrote: > Hi all, could you suggest me some methods to realize a digital PLL in VHD= L different from that used in USB (www.usb.org/developers/data/siewp.pdf). = In particular is possible to avoid ripple clock ?--Roberto Capobianco Conso= rzio RFX - CNR di PadovaC.so Stati Uniti, 435127 - Camin (PD) email: capobi= anco@igi.pd.cnr.itweb: www.igi.pd.cnr.it tel.: +39-049-8295048fax: +39-049-= 8700718 dear sir , i am trying to design dpll using vhdl could you please suggest me some boo= k or refrence papers on any thing=20 thanks=20 regards=20 Rupesh Raghatate asst prof AVBIT,pawnar ,INDIA From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.42.141 with SMTP id s13mr13716787qae.3.1371831025876; Fri, 21 Jun 2013 09:10:25 -0700 (PDT) X-Received: by 10.49.35.109 with SMTP id g13mr301628qej.1.1371831025818; Fri, 21 Jun 2013 09:10:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!bw2no2560208qab.0!news-out.google.com!y6ni3811qax.0!nntp.google.com!j2no1109843qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Jun 2013 09:10:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.76.39; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.76.39 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Subject: How can I design Galois field 2^m multiplier. From: lokesh kumar Injection-Date: Fri, 21 Jun 2013 16:10:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx05.eternal-september.org comp.lang.vhdl:6698 Hi, I am new to VHDL design. I want to design Galois field 2^m multiplier. First I want to start with Galois field 4 bit multiplier then 8 bit and then m bit multiplier. So please help me out with it.Any suggestion will be helpful. From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.lang.vhdl Subject: Re: How can I design Galois field 2^m multiplier. Date: Fri, 21 Jun 2013 16:16:54 -0700 Organization: Aioe.org NNTP Server Lines: 15 Message-ID: References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> NNTP-Posting-Host: D5DinR2G1m7OmzSvko9AvA.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx05.eternal-september.org comp.lang.vhdl:6699 On 6/21/2013 9:10 AM, lokesh kumar wrote: > Hi, > > I am new to VHDL design. I want to design Galois field 2^m > multiplier. First I want to start with Galois field 4 bit multiplier > then 8 bit and then m bit multiplier. So please help me out with > it.Any suggestion will be helpful. > I don't know how FPGAs do it... but in software most Galois field multipliers exponentiate the two terms and then add them. Exponentiation is a simple lookup table. Rob. From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed3.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Cannot find function "TO_INTEGER" for these actuals Date: Mon, 24 Jun 2013 13:31:06 +0300 Lines: 10 Message-ID: References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> NNTP-Posting-Host: 2001:708:310:3430:b0cc:4560:f5ca:7478 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1372069866 22426 2001:708:310:3430:b0cc:4560:f5ca:7478 (24 Jun 2013 10:31:06 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Mon, 24 Jun 2013 10:31:06 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:bAqJwkIUbwU+p1d2UvDSksmGT1w= Xref: mx05.eternal-september.org comp.lang.vhdl:6700 rickman writes: > On 6/18/2013 12:45 PM, Travis wrote: >> Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update. > > That is pretty amazing! I can't believe Xilinx is ignoring VHDL > 2008. I am coding in VHDL 2008 and expect my tools to support that. I'd also expect Xilinx to support at least the fixed point stuff in ISE. Didn't everyone add that almost overnight? From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.59.205 with SMTP id m13mr26591072qah.7.1372092552761; Mon, 24 Jun 2013 09:49:12 -0700 (PDT) X-Received: by 10.182.50.162 with SMTP id d2mr50045obo.3.1372092552586; Mon, 24 Jun 2013 09:49:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.216.88.MISMATCH!j2no1589316qak.0!news-out.google.com!fv2ni0qab.0!nntp.google.com!j2no1589315qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Jun 2013 09:49:12 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.12; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.12 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ef4853d-9ee6-4299-93cb-9abe9719fb70@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: kevin.neilson@xilinx.com Injection-Date: Mon, 24 Jun 2013 16:49:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6701 Do you mean the size of the field is 2^m, i.e. you want to build a multipli= er over GF{2^m}? And are you talking about a constant multiplier (i.e., mu= ltiplying r*k, where k is a constant)? Probably; this is the type used in = something like a Reed-Solomon encoder. If this is what you are doing there= is a simple matrix operation you can use which synthesizes to a bunch of X= ORs. I forget the exact matrix but I found it in Petersen's book, which is= nice concise manual. From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.215.68 with SMTP id hd4mr26596857qab.5.1372093177005; Mon, 24 Jun 2013 09:59:37 -0700 (PDT) X-Received: by 10.50.126.33 with SMTP id mv1mr569883igb.1.1372093176957; Mon, 24 Jun 2013 09:59:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.216.87.MISMATCH!j2no424900qak.0!news-out.google.com!fv2ni0qab.0!nntp.google.com!j2no1595182qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Jun 2013 09:59:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.12; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.12 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: kevin.neilson@xilinx.com Injection-Date: Mon, 24 Jun 2013 16:59:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6702 Theoretically, the fixed point library shouldn't require any special synthe= sizer support but I wouldn't be surprised if ISE didn't like it for some re= ason. I definitely wouldn't try it with unconstrained i/o. And, as with i= nteger math functions, I wouldn't expect it to map to DSP48s very well. From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 24 Jun 2013 16:48:48 -0500 From: Jon Elson Subject: Re: Chasing Bugs in the Fog Newsgroups: comp.lang.vhdl,comp.arch.fpga Followup-To: comp.lang.vhdl Reply-To: jmelson@wustl.edu Date: Mon, 24 Jun 2013 16:56:44 -0500 References: Organization: Washington University User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8Bit Message-ID: <4bGdnXLO96RdI1XMnZ2dnUVZ_iydnZ2d@giganews.com> Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-XeP/O+EYJUGTmtOxN7hy1xDJuW0jmZW/C9MooqPyWjfbfCM6YB7JNepzMhfHzQcOBYnkSYwQ1SvDS39!/VGdSWmZnlB08rAUCgHVmSShg8wdamc4Qig88HK7mAxmuaew1fLZASipvyej7B1SFqX+q2+rjlDd!7w== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1952 Xref: mx05.eternal-september.org comp.lang.vhdl:6703 comp.arch.fpga:19268 rickman wrote: > I didn't think it was in the VHDL because it had been simulated well and > the nature of the bug is an occasional dropped character on the receive > side.  Who can't design a UART?  Well, it could be in the handshake with > the state machine, but still... > Any time you recompile an FPGA and the problem disappears or changes, it is a STRONG indication it is a timing problem. Regenerating the place & route changes timings subtly between sections, and may eliminate a marginal setup or hold time problem. You should make sure all signals that cross clock boundaries are properly synchronized, and that you are giving the right clock specification to your clocks in the ucf file. If there are tricky timings on parts connected to the FPGA, then you need to define the timings in the ucf file. Jon From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.57.65 with SMTP id b1mr27735580qah.2.1372112818550; Mon, 24 Jun 2013 15:26:58 -0700 (PDT) X-Received: by 10.49.17.166 with SMTP id p6mr576815qed.18.1372112818513; Mon, 24 Jun 2013 15:26:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no500944qak.0!news-out.google.com!fv2ni168qab.0!nntp.google.com!j2no1677400qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Jun 2013 15:26:58 -0700 (PDT) In-Reply-To: <4db224da-1201-4599-97d4-22bdd64e440e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <69ba8dba-8d81-4c8a-a01b-2503ce0af79f@googlegroups.com> <29c4e09a-38ee-4aa7-90d1-af1644206969@googlegroups.com> <4db224da-1201-4599-97d4-22bdd64e440e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46f1e8ae-c88c-48ac-883d-bf56fdcd80b2@googlegroups.com> Subject: Re: Distributed Ram with Initial Values (Virtex) From: Andy Injection-Date: Mon, 24 Jun 2013 22:26:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2491 Xref: mx05.eternal-september.org comp.lang.vhdl:6704 On Thursday, June 20, 2013 7:37:47 PM UTC-5, kevin....@xilinx.com wrote: > If you want to target BRAM, you have to have at least one cycle of latenc= y, since the BRAM address is registered. (Distributed RAM can be fully comb= inatorial.) The tools will then target BRAM if it's over a certain (small) = depth. You can add synthesis directives, but you probably don't need them. Depending on the target device, block RAM read data may be registered inste= ad of (or in addition to) the address being registered. Most synthesis tool= s don't care, as long as there is one cycle of latency between address and = read data. I have not tried this on a device that had both distributed and block rams,= but if you describe RAM accesses with 1 cycle latency on reads, then it sh= ould use block rams first, then it should switch to distributed rams plus r= egisters. You can also use an attribute on the array to direct the ram style. See you= r synthesis tool documentation for details. Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.205.138 with SMTP id fq10mr28866309qab.1.1372144353016; Tue, 25 Jun 2013 00:12:33 -0700 (PDT) X-Received: by 10.49.97.34 with SMTP id dx2mr627258qeb.42.1372144352974; Tue, 25 Jun 2013 00:12:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!news-out.readnews.com!transit3.readnews.com!209.85.216.88.MISMATCH!j2no1766661qak.0!news-out.google.com!fv2ni168qab.0!nntp.google.com!j2no1766657qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Jun 2013 00:12:32 -0700 (PDT) In-Reply-To: <0ef4853d-9ee6-4299-93cb-9abe9719fb70@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=63.78.85.4; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 63.78.85.4 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> <0ef4853d-9ee6-4299-93cb-9abe9719fb70@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How can I design Galois field 2^m multiplier. From: kevin.neilson@xilinx.com Injection-Date: Tue, 25 Jun 2013 07:12:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6705 I meant Peter Sweeney's book, not Petersen's. Here's that matrix. I don't= know if it will format properly in this font. This multiplies an input nu= mber b (beta) in the polynomial basis by alpha to the ith power, where i is= constant. Beta is a J-bit row vector, where the field is GF{2**J}, and th= e matrix is JxJ bits. The multiplications are over GF{2}. I hope this mak= es sense. There's an example in Sweeney. You'll need to make a table of t= he powers of alpha first so you can populate the matrix. b*(a**i) =3D [ a**(i+J-1) ]=20 [ ... ] b*[ a**(i+1) ] [ a**i ] From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Ask about finding maximum and second's maximum number in array is given. Date: Tue, 25 Jun 2013 12:44:25 +0300 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 25 Jun 2013 09:39:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="31639"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19sSEa5nIOp9bVes3GE3Vv5Zg2hjvg/mJ8=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> Cancel-Lock: sha1:57XJsfusPN+wIqT+w+Br4B+uLAs= Xref: mx05.eternal-september.org comp.lang.vhdl:6706 Here is the computation of the max process variable max: integer := Integer.Minimum; begin for I in 1 to 10 loop wait until clk = '1'; if (input > max) max := input; end if; end loop; report "max = " & integer'image(max); end process; I am sure, you can extend it to the pre-max variable by something like if (input > max) premax := max; max := input; end if; From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.174.145 with SMTP id t17mr29771466qaz.4.1372164655768; Tue, 25 Jun 2013 05:50:55 -0700 (PDT) X-Received: by 10.49.35.195 with SMTP id k3mr620427qej.2.1372164655698; Tue, 25 Jun 2013 05:50:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no623619qak.0!news-out.google.com!fv2ni168qab.0!nntp.google.com!j2no1813870qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Jun 2013 05:50:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <617bede2-65c9-49fb-be73-3c81e9abfd7e@googlegroups.com> Subject: Re: Cannot find function "TO_INTEGER" for these actuals From: Andy Injection-Date: Tue, 25 Jun 2013 12:50:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2305 Xref: mx05.eternal-september.org comp.lang.vhdl:6707 Unconstrained IO fixed point should work fine, since the bound object is st= atic and therefore it's index range is static too. Just be real careful wit= h bit string literals! (e.g. don't use bit string literals for fixed/floati= ng point). Fixed point arithmetic is implemented using numeric_std operators, so it sh= ould do fine for anything=20 IIRC, some synthesis tools had problems with fixed point because they did n= ot support negative indices on arrays (slv/signed/unsigned have natural ind= ex ranges). There are '93 compatible versions of the fixed point package av= ailable, they just don't support package generics for saturate/rollover or = round/truncate and number of guard bits for division. You have to change th= e constants in the '93 package. Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.224.174.145 with SMTP id t17mr29910179qaz.4.1372167539068; Tue, 25 Jun 2013 06:38:59 -0700 (PDT) X-Received: by 10.182.80.6 with SMTP id n6mr52096obx.16.1372167538911; Tue, 25 Jun 2013 06:38:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no628655qak.0!news-out.google.com!fv2ni168qab.0!nntp.google.com!j2no1819827qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Jun 2013 06:38:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Ask about finding maximum and second's maximum number in array is given. From: Andy Injection-Date: Tue, 25 Jun 2013 13:38:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1680 Lines: 8 Xref: mx05.eternal-september.org comp.lang.vhdl:6708 Your premax solution only works if the highest value occurs in the input stream after the 2nd highest value, and the 2nd highest value does not have the same value as the highest value. You need a separate comparison of input and premax. That means premax needs initialization too. Process variables are only initialized at time zero; when the implied process loop (not the loop statement) repeats, the variable is not re-initialized. In all fairness though, the OP did not state he needed a synthesizable solution. Andy From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 25 Jun 2013 13:46:11 -0500 Date: Tue, 25 Jun 2013 19:46:11 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130514 Thunderbird/17.0.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Cannot find function "TO_INTEGER" for these actuals References: <7c0e9bc8-b770-4a98-8011-dc0b9fe45df9@googlegroups.com> <892290c6-aba7-4583-b4ae-d66f78c014e4@googlegroups.com> <617bede2-65c9-49fb-be73-3c81e9abfd7e@googlegroups.com> In-Reply-To: <617bede2-65c9-49fb-be73-3c81e9abfd7e@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 24 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-EqzFaSCNjR7P7nR8JqqeEUlUDlGxC5nK9acweBa/cBEEvTVzuigSboEjA9/Wwmj6EiaWKqf2VTFfAlt!pIdXQH8bqiUDpyVF777zu5zv88Mp2beUrOAlmOFyBNLQ8PmwG+Bcg6CdSQ62gPhM4Ip61aZ+t2VK!boiUwwdyJQh5FcsntQg6qm1K X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2773 Xref: mx05.eternal-september.org comp.lang.vhdl:6709 On 25/06/13 13:50, Andy wrote: > Unconstrained IO fixed point should work fine, since the bound object is static and therefore it's index range is static too. Just be real careful with bit string literals! (e.g. don't use bit string literals for fixed/floating point). > > Fixed point arithmetic is implemented using numeric_std operators, so it should do fine for anything > > IIRC, some synthesis tools had problems with fixed point because they did not support negative indices on arrays (slv/signed/unsigned have natural index ranges). There are '93 compatible versions of the fixed point package available, they just don't support package generics for saturate/rollover or round/truncate and number of guard bits for division. You have to change the constants in the '93 package. > > Andy > >From memory, there was an ieee_proposed library in Xilinx XST. Also there are Xilinx (and other tool) versions of the packages at www.eda.org/fphdl which should work fine. I haven't tested the VHDL 2008 support in Vivado yet - amusingly Xilinx now have three VHDL parsers. Two in ISE depending on which device you select; and a new one in Vivado, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.180.24.138 with SMTP id u10mr140134wif.4.1372362109235; Thu, 27 Jun 2013 12:41:49 -0700 (PDT) X-Received: by 10.50.4.38 with SMTP id h6mr16136igh.8.1372362109018; Thu, 27 Jun 2013 12:41:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.212.215.MISMATCH!cw2no4930394wib.0!news-out.google.com!b5ni26418wiz.1!nntp.google.com!j2no2809158qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Jun 2013 12:41:48 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.223.230.201; posting-account=HNfK-goAAADwkIDLX_feA2D4NIcjWSNt NNTP-Posting-Host: 134.223.230.201 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> Subject: Multiple Clocks on single bus From: TheHogs88 Injection-Date: Thu, 27 Jun 2013 19:41:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6710 Tried looking for this on here and couldn't find anything. What are the current thoughts on putting all of the clocks in a bus on the top level? This is not a good idea to do right? Can someone explain to me why though? From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiple Clocks on single bus Date: Thu, 27 Jun 2013 15:59:25 -0400 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 27 Jun 2013 19:54:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="25769"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+27NP12usQLSwFAIAzi/zw" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> Cancel-Lock: sha1:gyy/Od+RJ5x4Xoo5grXVwpwk2Ow= Xref: mx05.eternal-september.org comp.lang.vhdl:6711 On 6/27/2013 3:41 PM, TheHogs88 wrote: > Tried looking for this on here and couldn't find anything. What are the current thoughts on putting all of the clocks in a bus on the top level? This is not a good idea to do right? Can someone explain to me why though? I assume by "bus" you mean a vector of signals such as std_logic_vector? I don't know that it is a *bad* idea, but I don't see any value in it. If you run a clock (or any other signal) into a module and don't use it, you will get a warning that you will need to know to ignore. I try to avoid warnings that are ignored because they mask other warnings that you should not ignore. Other than the warnings you might get, I don't see any real advantage or disadvantage to running a clock bus, but the bus itself has no meaning to the tools or in the FPGA. They are purely for our convenience in reading the code. It is still just a bunch of signals whether in a vector or not. -- Rick From newsfish@newsfish Tue Dec 29 16:42:59 2015 X-Received: by 10.180.187.229 with SMTP id fv5mr174234wic.6.1372363433848; Thu, 27 Jun 2013 13:03:53 -0700 (PDT) X-Received: by 10.50.4.38 with SMTP id h6mr19218igh.8.1372363433677; Thu, 27 Jun 2013 13:03:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.212.215.MISMATCH!cw2no4968171wib.0!news-out.google.com!b5ni26418wiz.1!nntp.google.com!j2no2809536qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Jun 2013 13:03:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.223.230.200; posting-account=HNfK-goAAADwkIDLX_feA2D4NIcjWSNt NNTP-Posting-Host: 134.223.230.200 References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiple Clocks on single bus From: TheHogs88 Injection-Date: Thu, 27 Jun 2013 20:03:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6712 On Thursday, June 27, 2013 3:59:25 PM UTC-4, rickman wrote: > On 6/27/2013 3:41 PM, TheHogs88 wrote: > > > Tried looking for this on here and couldn't find anything. What are the current thoughts on putting all of the clocks in a bus on the top level? This is not a good idea to do right? Can someone explain to me why though? > > > > I assume by "bus" you mean a vector of signals such as std_logic_vector? > > > > I don't know that it is a *bad* idea, but I don't see any value in it. > > If you run a clock (or any other signal) into a module and don't use it, > > you will get a warning that you will need to know to ignore. I try to > > avoid warnings that are ignored because they mask other warnings that > > you should not ignore. > > > > Other than the warnings you might get, I don't see any real advantage or > > disadvantage to running a clock bus, but the bus itself has no meaning > > to the tools or in the FPGA. They are purely for our convenience in > > reading the code. It is still just a bunch of signals whether in a > > vector or not. > > > > -- > > > > Rick I meant more in a record rather than a std_logic_vector. For example a record with a 125Hz signal, 260Hz signal, and 30Hz signal all used throughout the design. From newsfish@newsfish Tue Dec 29 16:42:59 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiple Clocks on single bus Date: Thu, 27 Jun 2013 16:27:32 -0400 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 27 Jun 2013 20:22:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="3432"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18j4Epwmoz+CmhWtG2JMmQt" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:yLaeCYTCTmfPTULiIADIiyFYK+U= Xref: mx05.eternal-september.org comp.lang.vhdl:6713 On 6/27/2013 4:03 PM, TheHogs88 wrote: > On Thursday, June 27, 2013 3:59:25 PM UTC-4, rickman wrote: >> On 6/27/2013 3:41 PM, TheHogs88 wrote: >> >>> Tried looking for this on here and couldn't find anything. What are the current thoughts on putting all of the clocks in a bus on the top level? This is not a good idea to do right? Can someone explain to me why though? >> >> >> >> I assume by "bus" you mean a vector of signals such as std_logic_vector? >> >> >> >> I don't know that it is a *bad* idea, but I don't see any value in it. >> >> If you run a clock (or any other signal) into a module and don't use it, >> >> you will get a warning that you will need to know to ignore. I try to >> >> avoid warnings that are ignored because they mask other warnings that >> >> you should not ignore. >> >> >> >> Other than the warnings you might get, I don't see any real advantage or >> >> disadvantage to running a clock bus, but the bus itself has no meaning >> >> to the tools or in the FPGA. They are purely for our convenience in >> >> reading the code. It is still just a bunch of signals whether in a >> >> vector or not. >> >> >> >> -- >> >> >> >> Rick > > I meant more in a record rather than a std_logic_vector. For example a record with a 125Hz signal, 260Hz signal, and 30Hz signal all used throughout the design. Ok, everything I said above still applies I'm pretty sure. Why do you want to use a record? Do all the clocks get used in all modules the record goes to? Any input to a module that doesn't get used gets a warning. Do you read all the warnings every time you compile? I do. -- Rick From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.180.37.229 with SMTP id b5mr677357wik.4.1372381251689; Thu, 27 Jun 2013 18:00:51 -0700 (PDT) X-Received: by 10.49.12.141 with SMTP id y13mr293068qeb.41.1372381251440; Thu, 27 Jun 2013 18:00:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!weretis.net!feeder4.news.weretis.net!newsreader4.netcologne.de!news.netcologne.de!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.212.216.MISMATCH!mf3no7634504wib.1!news-out.google.com!md6ni27897wic.0!nntp.google.com!j2no2817760qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Jun 2013 18:00:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.242.197 References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ee749a2-22a8-4c3b-b282-7da9b71f5db0@googlegroups.com> Subject: Re: Multiple Clocks on single bus From: KJ Injection-Date: Fri, 28 Jun 2013 01:00:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6714 > I meant more in a record rather than a std_logic_vector. For example a re= cord > with a 125Hz signal, 260Hz signal, and 30Hz signal all used throughout th= e > design. The bigger question in my mind is why all throughout the design you're usin= g multiple clocks in the first place. On the surface, it sounds like a des= ign destined for a long debug cycle. But if the multiple clocks really are needed then a record to hold all thre= e still would seem to have the following drawbacks: - All modules would now be dependent on an external package to define the r= ecord simply as a mechanism to bring in three signals. Having such a globa= l package is useful for things that are really design independent (ieee.std= _logic_1164 as an example); I doublt that a record for defining three signa= ls would merit that importance. While you might reuse this idea on some ot= her design, it is probably much less likely that you would reuse the actual= package that contains this record ever again. - For those modules that actually only use one of those clocks it is a bit = clumsy to bring in a three element record just to use one element. It woul= d likely be cleaner to have the entity bring it in as std_ulogic and then p= ort map that signal to the intended record element. On the plus side, there could be a little bit less typing and visual clutte= r, but only when looking at the entity and the top level where the entities= are tied together. But the clutter level remains the same when you're loo= king at the architecture which is where one spends most of the time looking= since that is where the logic is described. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.180.187.229 with SMTP id fv5mr1022218wic.6.1372402897738; Fri, 28 Jun 2013 00:01:37 -0700 (PDT) X-Received: by 10.50.2.34 with SMTP id 2mr123662igr.8.1372402897414; Fri, 28 Jun 2013 00:01:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!news.qsc.de!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.212.216.MISMATCH!mf3no8126418wib.1!news-out.google.com!md6ni27897wic.0!nntp.google.com!j2no2821979qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 00:01:36 -0700 (PDT) In-Reply-To: <27634eee-60c8-4b46-9a30-e19b15833440@y7g2000prc.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.33.81.70; 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Date: Fri, 28 Jun 2013 10:06:20 +0300 Lines: 17 Message-ID: References: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> NNTP-Posting-Host: 2001:708:310:3430:f995:86b4:79ac:9933 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1372403180 2004 2001:708:310:3430:f995:86b4:79ac:9933 (28 Jun 2013 07:06:20 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Fri, 28 Jun 2013 07:06:20 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:P+fSEQXDfZBoDPmAGKn66uQLMuY= Xref: mx05.eternal-september.org comp.lang.vhdl:6716 Andy writes: > Your premax solution only works if the highest value occurs in the input stream after the 2nd highest value, and the 2nd highest value does not have the same value as the highest value. > > You need a separate comparison of input and premax. That means premax needs initialization too. > > Process variables are only initialized at time zero; when the implied process loop (not the loop statement) repeats, the variable is not re-initialized. > > In all fairness though, the OP did not state he needed a synthesizable solution. Didn't he mention a clock cycle limit of 10 though? So it slightly hints towards synthesizable. Or at least synchronous. Another solution is of course sorting the array and taking the two largest values. I'd do that if this were a real problem and there were some doubt that maybe it's not the two largest but perhaps the fourth or seventh largest value I need... Or the median for that matter. From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.29.76 with SMTP id p12mr13001058qac.5.1372425640327; Fri, 28 Jun 2013 06:20:40 -0700 (PDT) X-Received: by 10.50.45.35 with SMTP id j3mr205584igm.3.1372425640130; Fri, 28 Jun 2013 06:20:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no1610292qak.0!news-out.google.com!f7ni62qai.0!nntp.google.com!j2no2830793qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 06:20:39 -0700 (PDT) In-Reply-To: <5ee749a2-22a8-4c3b-b282-7da9b71f5db0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> <5ee749a2-22a8-4c3b-b282-7da9b71f5db0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27cd0cfd-e6fc-4948-afca-0297d7612b0b@googlegroups.com> Subject: Re: Multiple Clocks on single bus From: Andy Injection-Date: Fri, 28 Jun 2013 13:20:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2336 Xref: mx05.eternal-september.org comp.lang.vhdl:6717 Are these clocks related (synchronous) to each other? If so, I could see so= me merit to bundling them together in a single signal/port if they often ge= t used in the same places. If they are not related, then extreme care must be used when transferring d= ata between them. You want those transfers to be rare and easily identified= , neither of which is well served by bundling them together on one signal/p= ort. In defense of custom aggregate data types, I often define a package of inte= rface types for a project that defines composites (arrays & records), enume= rated types, subranges of integer, constants, etc. for use in the design.= =20 For example, I find it extremely useful to define a record with an element = for the data (maybe an array/record itself), and another element for a "val= id" or "mode" indicator for that data. By bundling data and indicator in th= e same object, you always have all the information needed to interact with = that data, whether you are producing it or consuming it.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: [long] look up table for procedure call Date: Fri, 28 Jun 2013 15:33:54 +0200 Lines: 81 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net OeKYQiwn1aDZjraL5+sHZQSWcKmj0sYxhIOHUlfCd4DMlU55gT Cancel-Lock: sha1:C4sVb4Fz0jqxEdcWrX2zp87A2uQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6718 Hi all, this thread is intended for testbench only, no RTL needed. I've just finished to read JB's 'Writing Testbenches' 2nd edition and I must say that I found it quite enlightening. The model he proposes to write testbenches is essentially to wrap away the physical interface of the DUT and provide a level of abstraction to the testcases so that interface implementation changes do not affect the rewrite of the testcases. The book covers well the fact that a package is not a 'structural element' in VHDL, therefore you cannot abstract away the interface by means of a package (you always need to pass all the signals in your procedure call) and a bus functional model entity is proposed in place (for details see pag. 325 - VHDL TEST HARNESS). His proposal, as I think I have understood, is to use an entity with a 'server' process which is implementing the bus functional model while serving 'abstract' requests from the client process which does not know the details of the physical interface. Abstract signals to handle handshake between client and server are also needed, but the great advantage of the proposed method is that test cases are now at a much higher level and have no details referred to the DUT (a test case for a read/modify/write operation can be completely independent on the DUT and the test case may be reused for very many projects where read/write operations are meaningful). I started out writing like hell the various elements of my bus functional model, the test harness and some of the test cases, but now my problem is the following: my 'server' has to perform abstract actions (read_data, write_data, setup_interface, generate_input_pattern, ...) which are essentially mapped to an 'address'. To be more specific, my test case would call a procedure like this: procedure exec( type: in bool; -- read/write addr: in natural; -- what to do data: inout natural; -- data provided or returned signal: to_server: out to_srv_control; --handshake signal: from_server: in frm_srv_control;); --handshake while the test case will look like: -- RD/WR are type defined as true/false exec(RD, reg0, data, to_srv, frm_srv); exec(WR, reg1, data, to_srv, frm_srv); exec(WR, reg2, data, to_srv, frm_srv); ... by changing the address (reg[0,1,2]) we may want to either send a pulse to the interface or have a write cycle, the server needs to have some sort of switch statement based on the 'address' content and call the appropriate procedure where the appropriate operation is performed. Given the fact that I'm extremely lazy, in C I would solve this problem with a simple table (possibly stored in a struct) with two elements, an address and a function pointer initialized to a specific function. A 'for loop' will then check the function to call every time there's a new request from the client (only problem is that with this approach the function parameters should be standardized for all functions, but this is a different problem). Now, after all this chatter, comes the real question: is there a way to write a 'table' (maybe an array of registers), in which one element is the address and the other is a procedure call, in such a way that every time I need to add a new address and a new procedure call I simply extend the table without touching the 'for loop' part of the code? I'm not sure the problem is clear and if the additional context is helping understanding my question, but that was my intent. Thank you all for any hint. Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.172.136 with SMTP id l8mr3912430qaz.2.1372429296137; Fri, 28 Jun 2013 07:21:36 -0700 (PDT) X-Received: by 10.49.129.104 with SMTP id nv8mr371434qeb.27.1372429296073; Fri, 28 Jun 2013 07:21:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!j2no2835071qak.0!news-out.google.com!f7ni62qai.0!nntp.google.com!j2no2835067qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 07:21:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <54d3a148-bbf3-41bb-a956-5ec6ecec973d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0615ecb6-8737-4c0b-b242-33083412e61f@googlegroups.com> Subject: Re: Ask about finding maximum and second's maximum number in array is given. From: Andy Injection-Date: Fri, 28 Jun 2013 14:21:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: mx05.eternal-september.org comp.lang.vhdl:6719 The OP said; "And 10 elements were imported to within 10 clock cycles". That is not the same as "only 10 clocks will be provided". What does the model do on the 11th and following clock cycles? Andy From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr2231798qag.7.1372430730071; Fri, 28 Jun 2013 07:45:30 -0700 (PDT) X-Received: by 10.50.126.33 with SMTP id mv1mr228234igb.1.1372430729997; Fri, 28 Jun 2013 07:45:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!j2no2836721qak.0!news-out.google.com!f7ni62qai.0!nntp.google.com!j2no2836717qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 07:45:29 -0700 (PDT) In-Reply-To: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.223.230.200; posting-account=HNfK-goAAADwkIDLX_feA2D4NIcjWSNt NNTP-Posting-Host: 134.223.230.200 References: <0eddfe4d-f483-49be-92af-204dd410321e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiple Clocks on single bus From: TheHogs88 Injection-Date: Fri, 28 Jun 2013 14:45:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 6 Xref: mx05.eternal-september.org comp.lang.vhdl:6720 Well in the actual design there are about 10-15 clock pins coming into the = top level. These pins then get fed into a clock manager entity which branch= es them out into separate DCMs/PLLs. From the clock manager onward, some cl= ocks are grouped together based on interface (QDR clks, RIO clks).=20 The input to the top level is just a pads record with records underneath it= for each interface (clks, DDR, QDR, RIO, etc.). From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.29.76 with SMTP id p12mr13453864qac.5.1372431739244; Fri, 28 Jun 2013 08:02:19 -0700 (PDT) X-Received: by 10.182.50.162 with SMTP id d2mr43698obo.3.1372431739165; Fri, 28 Jun 2013 08:02:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!j2no2837734qak.0!news-out.google.com!f7ni62qai.0!nntp.google.com!j2no2837729qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 08:02:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <557d87ae-fa33-4c14-8a15-73c9767c8a71@googlegroups.com> Subject: Re: [long] look up table for procedure call From: Jim Lewis Injection-Date: Fri, 28 Jun 2013 15:02:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 28 Xref: mx05.eternal-september.org comp.lang.vhdl:6721 I use a case statement. If you use procedures like you suggest and keep the choice and procedure call on one line, it looks similar to a table. process begin=20 wait ;=20 case to_srv.addr is when ADDR1 =3D> DO_ADDR1_ACTION(...) ;=20 when ADDR2 =3D> DO_ADDR2_ACTION(...); For most BFMs (TLM/server) that I do I don't bother with calling procedures= , I just write the code following the case target. I suppose it depends on= the complexity of the code. =20 A couple of things I do different: Rather than using a generalized "exec", I put the operation name into the p= rocedure. So I do CpuWrite rather than CpuExec(WR, ... With writing, thi= s means that data can be a constant rather than a variable and you can pass= a value directly to the call. CpuWrite(reg0, X"A5", ...) ;=20 =20 I use a single record and resolution functions. The resolution functions m= ake it more complicated, but I prefer only one record in the call. =20 Jim SynthWorks' VHDL Testbench and Verification class covers this, OSVVM, and m= ore. See http://www.synthworks.com/vhdl_testbench_verification.htm From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: VHDL to CMOS Date: Fri, 28 Jun 2013 18:21:51 +0200 Organization: A noiseless patient Spider Lines: 14 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Jun 2013 16:16:31 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="22148"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+KH6L0WklmsvCEKpvWDV9q" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 Cancel-Lock: sha1:okIT+Ty6ZYBS0zR+V55YO6ZQe2U= Xref: mx05.eternal-september.org comp.lang.vhdl:6722 In the last months we have been designing an RF CMOS chip. The next step will be to integrate some functionality that now is run in an FPGA into the same chip. I guess there has to be a more or less straightforward way to translate a VHDL description into a layout, but don't know which software package we should be looking at. How straightforward is this? How good is the final result? Which tools are required? Is some manual place&route of the final logic cells (which are black boxes in our technology) still required? Thanks for any input! Pere From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.200.202 with SMTP id ex10mr15709874qab.8.1372455063810; Fri, 28 Jun 2013 14:31:03 -0700 (PDT) X-Received: by 10.49.120.67 with SMTP id la3mr400094qeb.35.1372455063771; Fri, 28 Jun 2013 14:31:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j2no2864942qak.0!news-out.google.com!f7ni126qai.0!nntp.google.com!j2no1641580qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Jun 2013 14:31:03 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.205.59.51; posting-account=k9XFkgoAAACeNZgO_S-XzZIM6OWHe7Uo NNTP-Posting-Host: 81.205.59.51 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> Subject: VHDL, Big RGB-generator - needs shortening, algorithms From: rik.wilmer@kpnplanet.nl Injection-Date: Fri, 28 Jun 2013 21:31:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2604 Xref: mx05.eternal-september.org comp.lang.vhdl:6723 So. I got this big lump of code. It generates up to 75 numbers (2 digits) on a screen. Now I have 8 rows of "stupid" code (no algorithms), and I'm sure there must be some easier way. (Notes: getalvec is an array (15 downto 0) of 8x8 ram for characters image is what I project on the screen (to be filtered with some rgb-values) index is the current number being drawn. It is used to read from a (75 downto 0) vector if that number should be highlighted or not ) Any thoughts would be much appreciated. It's purpose: to put on a FPGA attached to any RGB-monitor and game around. Here's a bit of the code: if(2x>=14 AND 2x<30) then if(2y >=140 AND 2y<156) then image := getalvec(0) (63-((x-7) + 8*(x-70) )); index := 1; elsif(2y >=166 AND 2y <182) then image := getalvec(0) (63-((x-7) + 8*(y-83) )); index := 2; elsif(2y >=192 AND 2y<208) then image := getalvec(0) (63-((x-7) + 8*(y-96) )); index := 3; elsif(2y >=218 AND 2y<234) then image := getalvec(0) (63-((x-7) + 8*(y-109) )); index := 4; elsif(2y >=244 AND 2y<260) then image := getalvec(0) (63-((x-7) + 8*(y-122) )); index := 5; elsif(2y >=270 AND 2y<286) then image := getalvec(0) (63-((x-7) + 8*(y-135) )); index := 6; elsif(2y >=296 AND 2y<312) then image := getalvec(0) (63-((x-7) + 8*(y-148) )); index := 7; elsif(2y >=322 AND 2y<338) then image := getalvec(0) (63-((x-7) + 8*(y-161) )); index := 8; else image := '0'; index := 0; end if; elsif(next) %etc.. From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: Fri, 28 Jun 2013 21:06:17 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 29 Jun 2013 01:01:28 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5bb03508bd7460ed6d1e79a1033b9bbc"; logging-data="27643"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19E1nbOtP30N0VVzfekgdEa" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:UtVsAWWxRz5Isy1M8BYz5wPY/qI= Xref: mx05.eternal-september.org comp.lang.vhdl:6724 On 6/28/2013 12:21 PM, o pere o wrote: > In the last months we have been designing an RF CMOS chip. The next step > will be to integrate some functionality that now is run in an FPGA into > the same chip. > > I guess there has to be a more or less straightforward way to translate > a VHDL description into a layout, but don't know which software package > we should be looking at. How straightforward is this? How good is the > final result? Which tools are required? Is some manual place&route of > the final logic cells (which are black boxes in our technology) still > required? > > Thanks for any input! > > Pere Chip design is not my forte, but my understanding is that digital logic and RF put different requirements on the process and are not often combined on a single chip. There is typically a compelling need when this is done, like sales of millions of chips. Are you designing a chip with a vendor in mind? They typically can point you to tools and provide you with libraries. -- Rick From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.129.196 with SMTP id p4mr23935319qas.6.1372638585478; Sun, 30 Jun 2013 17:29:45 -0700 (PDT) X-Received: by 10.50.22.9 with SMTP id z9mr677697ige.6.1372638585441; Sun, 30 Jun 2013 17:29:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.ripco.com!news.glorb.com!j2no1882672qak.0!news-out.google.com!f7ni121qai.0!nntp.google.com!j2no3114619qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 30 Jun 2013 17:29:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.240.61; posting-account=MCuIyAoAAABhyXJvMbOBS9PDz4_d4m08 NNTP-Posting-Host: 50.46.240.61 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> Subject: Re: VHDL to CMOS From: react66@gmail.com Injection-Date: Mon, 01 Jul 2013 00:29:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6725 On Friday, June 28, 2013 9:21:51 AM UTC-7, o pere o wrote: > In the last months we have been designing an RF CMOS chip. The next step= =20 >=20 > will be to integrate some functionality that now is run in an FPGA into= =20 >=20 > the same chip. >=20 >=20 >=20 > I guess there has to be a more or less straightforward way to translate= =20 >=20 > a VHDL description into a layout, but don't know which software package= =20 >=20 > we should be looking at. How straightforward is this? How good is the=20 >=20 > final result? Which tools are required? Is some manual place&route of=20 >=20 > the final logic cells (which are black boxes in our technology) still=20 >=20 > required? >=20 >=20 >=20 > Thanks for any input! >=20 >=20 >=20 > Pere Don't get taken for a ride buying tools. Best bet is to see if you can pay = the chip vendor to layout a block for you. If you are using a larger techno= logy for 3.3v CMOS, like .35 u, it is not too hard to synthesize a block us= ing some legacy tool like LEONARDO, then get the vendor to do clock inserti= on, layout and extraction plus a static timing run, find/fix antenna proble= ms and give you back the block for the top level layout. You don't want to buy all the tools just to do this. The vendor might charg= e you $5K if you give him the Verilog netlist and some idea of the block sh= ape. Synthesis and simulation should be done before this handoff, and clock gati= ng should be done if you care about power (who doesn't). It is best to keep= the synthesis under your control. Only if you are using a deep submicron p= rocess you should probably get the vendor to do this part too. Check http://opencircuitdesign.com, I think Tim has an open synthesis tool = but it might need Verilog input. From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.172.66 with SMTP id k2mr8552035qaz.4.1372639870766; Sun, 30 Jun 2013 17:51:10 -0700 (PDT) X-Received: by 10.50.4.38 with SMTP id h6mr680619igh.8.1372639870730; Sun, 30 Jun 2013 17:51:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.ripco.com!news.glorb.com!j2no3116085qak.0!news-out.google.com!f7ni121qai.0!nntp.google.com!j2no3116082qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 30 Jun 2013 17:51:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.240.61; posting-account=MCuIyAoAAABhyXJvMbOBS9PDz4_d4m08 NNTP-Posting-Host: 50.46.240.61 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: verification strategy with no specs From: Rob Anderson Injection-Date: Mon, 01 Jul 2013 00:51:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6726 On Wednesday, May 8, 2013 2:13:40 AM UTC-7, alb wrote: > Dear all, > > > > I've been appointed to review and verify a vhdl project of about 25k > > lines of code, *without* a specification document! > > > > There are various scattered notes/docs which describes somehow some > > details (*not all*), but there's no description of what the individual > > parts should do, even though there are only 4 types of FPGA in the system. > > > > It seems unbelievable to me that they got there without any spec but > > this is something I cannot change. My main question here is to > > understand if there exist strategies to face such type of situations and > > which one is more effective. > > > > I've started looking at the craziness at some implementation level (all > > code is practically uncommented!), but I'm at the level of firing a > > question to the designers for each line of code just to understand the > > reason behind! > > > > I know it sounds like a 'rescue' plan, but if anyone can point me to > > some - preferably documented - direction I would greatly appreciate. > > > > Al > > > > -- > > A: Because it fouls the order in which people normally read text. > > Q: Why is top-posting such a bad thing? > > A: Top-posting. > > Q: What is the most annoying thing on usenet and in e-mail? Sounds like you are working with some "IP". I had a IRDA block like that I think it was written by a summer student. The thing to do is run the test code, capture the output and assume it is a litmus test. Use DIFF on it. The problem is that if you change things, eg. reset or clocking, the output will not be identical. So change things slowly and keep it identical. From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED.caos.upc.es!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: Mon, 01 Jul 2013 20:37:47 +0200 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 1 Jul 2013 18:32:19 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="caos.upc.es:147.83.101.203"; logging-data="9096"; mail-complaints-to="abuse@eternal-september.org"; posting-account="oopere" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 In-Reply-To: Xref: mx05.eternal-september.org comp.lang.vhdl:6727 On 06/29/2013 03:06 AM, rickman wrote: > On 6/28/2013 12:21 PM, o pere o wrote: >> In the last months we have been designing an RF CMOS chip. The next step >> will be to integrate some functionality that now is run in an FPGA into >> the same chip. >> >> I guess there has to be a more or less straightforward way to translate >> a VHDL description into a layout, but don't know which software package >> we should be looking at. How straightforward is this? How good is the >> final result? Which tools are required? Is some manual place&route of >> the final logic cells (which are black boxes in our technology) still >> required? >> >> Thanks for any input! >> >> Pere > > Chip design is not my forte, but my understanding is that digital logic > and RF put different requirements on the process and are not often > combined on a single chip. There is typically a compelling need when > this is done, like sales of millions of chips. > > Are you designing a chip with a vendor in mind? They typically can > point you to tools and provide you with libraries. > We are targeting UMCs mixed-mode 180nm process. This should be a process able to put RF and digital stuff on the same chip. And yes, we get some libraries for digital parts, just black boxes that you may layout as you like. If you do this by hand, from RTL description for instance, this can be cumbersome if you have more than a few dozens of boxes... Pere From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!.POSTED.caos.upc.es!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: Mon, 01 Jul 2013 20:43:30 +0200 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 1 Jul 2013 18:38:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="caos.upc.es:147.83.101.203"; logging-data="11930"; mail-complaints-to="abuse@eternal-september.org"; posting-account="oopere" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 In-Reply-To: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> Xref: mx05.eternal-september.org comp.lang.vhdl:6728 On 07/01/2013 02:29 AM, react66@gmail.com wrote: > On Friday, June 28, 2013 9:21:51 AM UTC-7, o pere o wrote: >> In the last months we have been designing an RF CMOS chip. The next >> step >> >> will be to integrate some functionality that now is run in an FPGA >> into >> >> the same chip. >> >> >> >> I guess there has to be a more or less straightforward way to >> translate >> >> a VHDL description into a layout, but don't know which software >> package >> >> we should be looking at. How straightforward is this? How good is >> the >> >> final result? Which tools are required? Is some manual place&route >> of >> >> the final logic cells (which are black boxes in our technology) >> still >> >> required? >> >> >> >> Thanks for any input! >> >> >> >> Pere > > Don't get taken for a ride buying tools. Best bet is to see if you > can pay the chip vendor to layout a block for you. If you are using a > larger technology for 3.3v CMOS, like .35 u, it is not too hard to > synthesize a block using some legacy tool like LEONARDO, then get the > vendor to do clock insertion, layout and extraction plus a static > timing run, find/fix antenna problems and give you back the block for > the top level layout. > > You don't want to buy all the tools just to do this. The vendor might > charge you $5K if you give him the Verilog netlist and some idea of > the block shape. > > Synthesis and simulation should be done before this handoff, and > clock gating should be done if you care about power (who doesn't). It > is best to keep the synthesis under your control. Only if you are > using a deep submicron process you should probably get the vendor to > do this part too. > > Check http://opencircuitdesign.com, I think Tim has an open synthesis > tool but it might need Verilog input. > As this is for a non-profit research project, we may have the chip done and get access to some of the tools at a (hopefully) reasonable cost. I will have a look at the synthesis tool you mentioned -I wasn't aware of it. Thanks! Pere From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.86.200 with SMTP id t8mr29816040qal.0.1372747024415; Mon, 01 Jul 2013 23:37:04 -0700 (PDT) X-Received: by 10.49.25.36 with SMTP id z4mr808457qef.6.1372747024400; Mon, 01 Jul 2013 23:37:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!y2no78255qax.0!news-out.google.com!f7ni507qai.0!nntp.google.com!y2no82483qax.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Jul 2013 23:37:04 -0700 (PDT) In-Reply-To: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35aae9f9-58cc-433f-b3f1-73181416872a@googlegroups.com> Subject: Re: VHDL, Big RGB-generator - needs shortening, algorithms From: goouse99@gmail.com Injection-Date: Tue, 02 Jul 2013 06:37:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 5446 Xref: mx05.eternal-september.org comp.lang.vhdl:6729 Am Freitag, 28. Juni 2013 23:31:03 UTC+2 schrieb rik.w...@kpnplanet.nl: > So. I got this big lump of code. It generates up to 75 numbers (2 > > digits) on a screen. Now I have 8 rows of "stupid" code (no algorithms), > > and I'm sure there must be some easier way. > > (Notes: > > getalvec is an array (15 downto 0) of 8x8 ram for characters > > image is what I project on the screen (to be filtered with some > > rgb-values) > > index is the current number being drawn. It is used to read from a (75 > > downto 0) vector if that number should be highlighted or not > > ) > > > > Any thoughts would be much appreciated. > > It's purpose: to put on a FPGA attached to any RGB-monitor and > > game around. > > Here's a bit of the code: > > > > if(2x>=14 AND 2x<30) then > > if(2y >=140 AND 2y<156) then > > image := getalvec(0) (63-((x-7) + 8*(x-70) )); > > index := 1; > > elsif(2y >=166 AND 2y <182) then > > image := getalvec(0) (63-((x-7) + 8*(y-83) )); > > index := 2; > > elsif(2y >=192 AND 2y<208) then > > image := getalvec(0) (63-((x-7) + 8*(y-96) )); > > index := 3; > > elsif(2y >=218 AND 2y<234) then > > image := getalvec(0) (63-((x-7) + 8*(y-109) )); > > index := 4; > > elsif(2y >=244 AND 2y<260) then > > image := getalvec(0) (63-((x-7) + 8*(y-122) )); > > index := 5; > > elsif(2y >=270 AND 2y<286) then > > image := getalvec(0) (63-((x-7) + 8*(y-135) )); > > index := 6; > > elsif(2y >=296 AND 2y<312) then > > image := getalvec(0) (63-((x-7) + 8*(y-148) )); > > index := 7; > > elsif(2y >=322 AND 2y<338) then > > image := getalvec(0) (63-((x-7) + 8*(y-161) )); > > index := 8; > > else > > image := '0'; > > index := 0; > > end if; > > elsif(next) %etc.. Hi, there seems to be a typo in the third line. I think it should be (y-70) there. One thing that you can do to increase readability is replacing the inner if/elsif tree with a case-statement case 2y is when 140 to 155 => getalvec... index... when 166 to 181 => getalvec... index... --and so on another way would be to write some functions that do the calculation of the (y-offset) and index number parts. For that you need to develop some formula that does the calculations. Might be tricky because of the gaps but not impossible. It might be interesting to see which approach uses less ressources and runs faster. (comparators versus arithmetic blocks) One other solution would be another 9-bit adressable ROM that creates index and offset. This might be done with the case statement like shown above. If the synthesis tool does not do it that way immediately, you might separate the case for calculationg index and offset to create the ROM and then you just have a single getalvec assignment behind it. Similar thing s can be done with the 2x selection. Separate this into some process with the case statement, generating enable signals for the 2y ROMs That way you will have one Processes for the 2x rom N Processes for the 2y roms (or less if there are identical ones) And a final assignment image := getalvec(0) (63-((x-7) + 8*(y-y_offset) )); There may be even more usable approaches. But mainly you are handling and converting a huge number of constants. This "code converting" is done best with ROMs. you just have to decide how to structure them intelligently to make best use of the ressources. A number of small ROMs can be more efficient than one big thing that is 90% empty in the end. Look for further restrictions. e.g. if like in the example the 2y range is between 140 and 338 you just need a 8 bit-adressable ROM. just subtract 140 from y2 to eliminate the 9th bit. (maybe you need to disable the ROMs if 2y gets beyond 512-140) So there's a lot you can do to get rid of that nasty if-elsif tree. Just think about a good logic structure and let the ROM contents be calculated by some functions. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr18197852qag.7.1372756731080; Tue, 02 Jul 2013 02:18:51 -0700 (PDT) X-Received: by 10.49.4.136 with SMTP id k8mr809522qek.19.1372756731063; Tue, 02 Jul 2013 02:18:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!y2no90098qax.0!news-out.google.com!f7ni603qai.0!nntp.google.com!y2no90097qax.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Jul 2013 02:18:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.73.202.107; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 85.73.202.107 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Free evaluation of HercuLeS high-level synthesis now available from Ajax Compilers, Inc. From: Nikolaos Kavvadias Injection-Date: Tue, 02 Jul 2013 09:18:51 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6730 Athens, Greece =96 Jule 01, 2013 =96 Ajax Compilers, Inc., (http://www.ajax= compilers.com) announces the availability of a free evaluation version for = its flagship product, the HercuLeS high-level synthesis environment. The free evaluation is provided upon request; submit a request to info@ajax= compilers with "HercuLeS FREE evaluation" as part of the email subject. In = order for the request to be processed, do not forget to include the Etherne= t MAC address of your preferred machine, where HercuLeS HLS will be install= ed. Currently, a Windows XP SP2/SP3 release is available with support for W= indows 7 and 32-bit Linux due around July 20, 2013. According to Nikolaos Kavvadias, Ph.D., cofounder, CEO of Ajax Compilers: "= HercuLeS enables a seamless user experience from algorithm to hardware impl= ementation. HercuLeS uses a bit-accurate typed-assembly language for whole = program descriptions and supports the manipulation of a number of SSA-like = (Static Single Assignment) forms. It employs a modular, plug-in structure w= here frontends, analyses and optimizations can be added as self-contained e= xternal modules upon the core HLS engine. Further, HercuLeS does not rely o= n code templates since it uses a purely graph-based backend and utilizes op= en specifications such as Graphviz throughout the HLS process. The generate= d HDL code is completely vendor- and technology-independent. It is human-re= adable and allows for automatic third-party, IP integration through an open= process. As part of our overall marketing strategy, we decided to offer a free versi= on of HercuLeS in order to introduce our product to the users. There exist = three licensing plans for HercuLeS: FREE, BASIC and FULL, with increasing = number of features. It should be noted that we have not posed any time limi= tation to any version. The BASIC and FULL versions are available under comp= etitive pricing schemes, especially if you take account the extent of provi= ded support." The HercuLeS feature matrix listing all the supported features for each ver= sion can be downloaded in PDF format from http://www.ajaxcompilers.com/publ= ications/hercules/hercules-feature-matrix.pdf From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr19664255qag.7.1372784437381; Tue, 02 Jul 2013 10:00:37 -0700 (PDT) X-Received: by 10.50.83.100 with SMTP id p4mr1109448igy.15.1372784437295; Tue, 02 Jul 2013 10:00:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!y2no135624qax.0!news-out.google.com!f7ni623qai.0!nntp.google.com!y2no135623qax.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Jul 2013 10:00:36 -0700 (PDT) In-Reply-To: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.170.224.10; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 128.170.224.10 References: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <36a961ac-13cd-4236-af34-9d830aa3108d@googlegroups.com> Subject: Re: VHDL, Big RGB-generator - needs shortening, algorithms From: kevin.neilson@xilinx.com Injection-Date: Tue, 02 Jul 2013 17:00:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx05.eternal-september.org comp.lang.vhdl:6731 What is "2y"? That doesn't appear to be a legal expression. Are x and "2y" counters? If so, you could count modulo-13 or -26 so you don't need all these comparators. Otherwise, you should reorganize everything so things are stored on multiple-of-power-of-2 boundaries, not multiple-of-13 boundaries. From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!eweka.nl!lightspeed.eweka.nl!69.16.177.246.MISMATCH!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf03.am4!fx07.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL, Big RGB-generator - needs shortening, algorithms References: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> In-Reply-To: <3db742fd-1d4b-4f2e-af90-cd15e7888316@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130702-0, 02/07/2013), Outbound message X-Antivirus-Status: Clean Lines: 61 Message-ID: <7lTAt.11$0c4.1@fx07.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1372848579 86.29.12.221 (Wed, 03 Jul 2013 10:49:39 UTC) NNTP-Posting-Date: Wed, 03 Jul 2013 10:49:39 UTC Organization: virginmedia.com Date: Wed, 03 Jul 2013 11:49:37 +0100 X-Received-Bytes: 3213 Xref: mx05.eternal-september.org comp.lang.vhdl:6732 On 28/06/2013 22:31, rik.wilmer@kpnplanet.nl wrote: > So. I got this big lump of code. It generates up to 75 numbers (2 > digits) on a screen. Now I have 8 rows of "stupid" code (no algorithms), > and I'm sure there must be some easier way. > (Notes: > getalvec is an array (15 downto 0) of 8x8 ram for characters > image is what I project on the screen (to be filtered with some > rgb-values) > index is the current number being drawn. It is used to read from a (75 > downto 0) vector if that number should be highlighted or not > ) > > Any thoughts would be much appreciated. If you have the original algorithm in C/C++ then I would suggest you look into using a High Level Synthesis tool like Vivado-HLS. With HLS you can take your algorithm and do some architectural exploration (select number of pipeline stages, resource sharing etc) without changing the source. This might be easier than trying different strategies in VHDL. Good luck, Hans www.ht-lab.com > It's purpose: to put on a FPGA attached to any RGB-monitor and > game around. > Here's a bit of the code: > > if(2x>=14 AND 2x<30) then > if(2y >=140 AND 2y<156) then > image := getalvec(0) (63-((x-7) + 8*(x-70) )); > index := 1; > elsif(2y >=166 AND 2y <182) then > image := getalvec(0) (63-((x-7) + 8*(y-83) )); > index := 2; > elsif(2y >=192 AND 2y<208) then > image := getalvec(0) (63-((x-7) + 8*(y-96) )); > index := 3; > elsif(2y >=218 AND 2y<234) then > image := getalvec(0) (63-((x-7) + 8*(y-109) )); > index := 4; > elsif(2y >=244 AND 2y<260) then > image := getalvec(0) (63-((x-7) + 8*(y-122) )); > index := 5; > elsif(2y >=270 AND 2y<286) then > image := getalvec(0) (63-((x-7) + 8*(y-135) )); > index := 6; > elsif(2y >=296 AND 2y<312) then > image := getalvec(0) (63-((x-7) + 8*(y-148) )); > index := 7; > elsif(2y >=322 AND 2y<338) then > image := getalvec(0) (63-((x-7) + 8*(y-161) )); > index := 8; > else > image := '0'; > index := 0; > end if; > elsif(next) %etc.. > From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: [long] look up table for procedure call Date: Wed, 03 Jul 2013 14:21:22 +0200 Lines: 46 Message-ID: References: <557d87ae-fa33-4c14-8a15-73c9767c8a71@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ktv/pm2W8AE2V7rxgvLGjgDU4jyyrYQxWapCrNxLN+w/0Y4c8F Cancel-Lock: sha1:dedIJ9sZxPlXcc89CjHLbbThF8w= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <557d87ae-fa33-4c14-8a15-73c9767c8a71@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: mx05.eternal-september.org comp.lang.vhdl:6733 On 28/06/2013 17:02, Jim Lewis wrote: > I use a case statement. If you use procedures like you suggest and keep > the choice and procedure call on one line, it looks similar to a table. > > process > begin > wait ; > case to_srv.addr is > when ADDR1 => DO_ADDR1_ACTION(...) ; > when ADDR2 => DO_ADDR2_ACTION(...); Indeed it is actually quite easy to maintain as long as you use procedures to simplify the 'when' clause. Adding testcases to the server should be straight forward. > For most BFMs (TLM/server) that I do I don't bother with calling > procedures, I just write the code following the case target. I > suppose it depends on the complexity of the code. I'm somehow quite reluctant with writing code for the case target since it exposes too many details at the server level. Encapsulating the bus functional details in packaged procedures allows to hide and separate the physical interface a great deal. > A couple of things I do different: Rather than using a generalized > "exec", I put the operation name into the procedure. So I do > CpuWrite rather than CpuExec(WR, ... With writing, this means that > data can be a constant rather than a variable and you can pass a > value directly to the call. CpuWrite(reg0, X"A5", ...) ; I agree with that, my example was a bit oversimplified. The 'CpuWrite' name you suggest simplifies also the interface since you would not need an extra bit of information to pass along in order to distinguish between Write/Read. > I use a single record and resolution functions. The resolution > functions make it more complicated, but I prefer only one record in > the call. Could you elaborate on that? The 'client' call still passes only one register with the appropriate elements (data, address, to_srv, frm_srv) so there's only one register passed between the test cases and the test harness. Am I missing something? Why would you need resolution functions? From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr3789927qag.7.1372881741044; Wed, 03 Jul 2013 13:02:21 -0700 (PDT) X-Received: by 10.49.0.200 with SMTP id 8mr78339qeg.38.1372881740991; Wed, 03 Jul 2013 13:02:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!news2.arglkargh.de!news.litech.org!news.glorb.com!t19no17803qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no17798qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2013 13:02:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.46.91.14; posting-account=25JzRgoAAAC51EAXKmDbABLzTbNfYBFL NNTP-Posting-Host: 82.46.91.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: counting number of reports in the message window within Modelsim From: G buf thing Injection-Date: Wed, 03 Jul 2013 20:02:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6734 Hi, I am running a simulation in Modelsim and want to know have to read t= he number of "report severity warning messages" reported within the simulat= ion. The following format is used within the RTL code: report "CRC fail" se= verity warning; . The number of these warnings can be viewed in the message= window, I wish to be able to read this value within the simulation script = to ensure that the value does not change. The version of Modelsim being used is 5.0c. Thanks Jon From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.42.141 with SMTP id s13mr3894411qae.3.1372882503939; Wed, 03 Jul 2013 13:15:03 -0700 (PDT) X-Received: by 10.50.45.35 with SMTP id j3mr215910igm.3.1372882503810; Wed, 03 Jul 2013 13:15:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no19256qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no19253qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2013 13:15:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ec0079a-d59e-4f1b-878d-a4d373c8f446@googlegroups.com> Subject: Re: counting number of reports in the message window within Modelsim From: Jim Lewis Injection-Date: Wed, 03 Jul 2013 20:15:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: mx05.eternal-september.org comp.lang.vhdl:6735 I use UNIX utilities such as cygwin or mingw to post process the transcript window. The following will get you all occurrences of your text: grep -i "CRC fail" To get a count pass it to wc: grep -i "CRC fail" | wc This will give you three count values, such as 21 168 917 They are lines, words, and characters. From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr3843246qag.7.1372882544203; Wed, 03 Jul 2013 13:15:44 -0700 (PDT) X-Received: by 10.50.117.106 with SMTP id kd10mr209363igb.14.1372882543956; Wed, 03 Jul 2013 13:15:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!t19no19335qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no19333qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2013 13:15:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7889050b-0699-4112-9e21-2528f7c6d337@googlegroups.com> Subject: Re: counting number of reports in the message window within Modelsim From: Jim Lewis Injection-Date: Wed, 03 Jul 2013 20:15:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx05.eternal-september.org comp.lang.vhdl:6736 I use UNIX utilities such as cygwin or mingw to post process the transcript file. The following will get you all occurrences of your text: grep -i "CRC fail" To get a count pass it to wc: grep -i "CRC fail" | wc This will give you three count values, such as 21 168 917 They are lines, words, and characters. From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.55.200 with SMTP id v8mr4565208qag.7.1372893392836; Wed, 03 Jul 2013 16:16:32 -0700 (PDT) X-Received: by 10.50.13.105 with SMTP id g9mr1542667igc.9.1372893392760; Wed, 03 Jul 2013 16:16:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t19no36121qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no36114qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2013 16:16:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.76.39; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.76.39 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> <0ef4853d-9ee6-4299-93cb-9abe9719fb70@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1476103e-4800-45f9-a366-d1316c435888@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: lokesh kumar Injection-Date: Wed, 03 Jul 2013 23:16:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6737 Could you please help me to design a code from an algorithm? I found the al= gorithm but it is a bit confusing for me to design the code as I am new to = it.It would be a great help if you have a look on the algorithm and try to = help me out with it.Please provide my your email and I can send you the alg= orithm. Thank you From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.29.76 with SMTP id p12mr4657548qac.5.1372893683295; Wed, 03 Jul 2013 16:21:23 -0700 (PDT) X-Received: by 10.49.25.227 with SMTP id f3mr100459qeg.33.1372893683240; Wed, 03 Jul 2013 16:21:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no36556qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no36547qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Jul 2013 16:21:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.76.39; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.76.39 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77899cf5-cf5b-42c2-829f-b5e308e0e19d@googlegroups.com> Subject: Need help to design n bit Galois field multiplier From: lokesh kumar Injection-Date: Wed, 03 Jul 2013 23:21:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 9 Xref: mx05.eternal-september.org comp.lang.vhdl:6738 Hi, Is anyone please help me out to design a code for n bit Galois field multip= lier? I am new to VHDL design and I have limited time to work for my projec= t and its a part of my project. I have the algorithms but I need an idea ho= w to start it. Please let me know. It would be a really great help.Please p= rovide your email, so that I can send you the algorithm and you can have a = look. Many thanks. From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!multikabel.net!newsfeed20.multikabel.net!eweka.nl!lightspeed.eweka.nl!69.16.177.246.MISMATCH!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf03.am4!fx09.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: counting number of reports in the message window within Modelsim References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130703-1, 03/07/2013), Outbound message X-Antivirus-Status: Clean Lines: 21 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1372923763 86.29.12.221 (Thu, 04 Jul 2013 07:42:43 UTC) NNTP-Posting-Date: Thu, 04 Jul 2013 07:42:43 UTC Organization: virginmedia.com Date: Thu, 04 Jul 2013 08:42:41 +0100 X-Received-Bytes: 1676 Xref: mx05.eternal-september.org comp.lang.vhdl:6739 On 03/07/2013 21:02, G buf thing wrote: > Hi, > > I am running a simulation in Modelsim and want to know have to read the number of "report severity warning messages" reported within the simulation. The following format is used within the RTL code: report "CRC fail" severity warning; . The number of these warnings can be viewed in the message window, I wish to be able to read this value within the simulation script to ensure that the value does not change. Look up the "assertion count" command in the reference manual. > The version of Modelsim being used is 5.0c. 5.0c? Hans www.ht-lab.com > > Thanks > > Jon > From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.172.66 with SMTP id k2mr7416608qaz.4.1372942891292; Thu, 04 Jul 2013 06:01:31 -0700 (PDT) X-Received: by 10.50.110.103 with SMTP id hz7mr277996igb.17.1372942891216; Thu, 04 Jul 2013 06:01:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no341723qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no341717qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 4 Jul 2013 06:01:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.192.254.221; posting-account=Exvb2AoAAACa-sO6JvEzg442sHzmTXxH NNTP-Posting-Host: 203.192.254.221 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> Subject: New VHDL Project From: shankarmishra124@gmail.com Injection-Date: Thu, 04 Jul 2013 13:01:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx05.eternal-september.org comp.lang.vhdl:6740 hello all this is shankar mishra doing M Tech in Electronics can you suggest me some usefull project on VHDL based on current trend in VLSI industry. thanx in advance From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.172.66 with SMTP id k2mr7669604qaz.4.1372946554861; Thu, 04 Jul 2013 07:02:34 -0700 (PDT) X-Received: by 10.49.13.71 with SMTP id f7mr139716qec.31.1372946554805; Thu, 04 Jul 2013 07:02:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t19no337932qam.0!news-out.google.com!f7ni806qai.0!nntp.google.com!t19no348390qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 4 Jul 2013 07:02:34 -0700 (PDT) In-Reply-To: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.76.39; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.76.39 References: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12d92676-ab83-455d-b204-8acbf0dcc4f6@googlegroups.com> Subject: Re: New VHDL Project From: lokesh kumar Injection-Date: Thu, 04 Jul 2013 14:02:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx05.eternal-september.org comp.lang.vhdl:6741 you can work on Galois field to implement the ECC. Basically your work will= be to implement Galois field N bit multiplier, point addition and point do= ubling and then you can work on higher level of protocol implementation. I = am also working on the same project but as I am new to VHDL, so I am suffer= ing from it. May be we can help each other if you work on the same. From newsfish@newsfish Tue Dec 29 16:43:00 2015 Path: eternal-september.org!news.eternal-september.org!mx05.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail From: Theo Markettos Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: 05 Jul 2013 13:34:37 +0100 (BST) Organization: University of Cambridge, England Lines: 14 Message-ID: References: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> NNTP-Posting-Host: chiark.greenend.org.uk X-Trace: chiark.greenend.org.uk 1373027679 5944 212.13.197.229 (5 Jul 2013 12:34:39 GMT) X-Complaints-To: abuse@chiark.greenend.org.uk NNTP-Posting-Date: Fri, 5 Jul 2013 12:34:39 +0000 (UTC) User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.32-5-686-bigmem (i686)) Originator: theom@chiark.greenend.org.uk ([212.13.197.229]) Xref: mx05.eternal-september.org comp.lang.vhdl:6742 o pere o wrote: > As this is for a non-profit research project, we may have the chip done > and get access to some of the tools at a (hopefully) reasonable cost. I > will have a look at the synthesis tool you mentioned -I wasn't aware of > it. Thanks! Are you in academia? There may be a way to get cheap access to the tools through a national academic programme, for example Europractice in Europe: http://www.europractice.stfc.ac.uk/welcome.html But be aware that it may take a long time to become familiar with the tools - if you're only going to do this once, probably worth contracting it out. Theo From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.41.145 with SMTP id o17mr9510388qae.3.1373231612772; Sun, 07 Jul 2013 14:13:32 -0700 (PDT) X-Received: by 10.49.13.71 with SMTP id f7mr425816qec.31.1373231612757; Sun, 07 Jul 2013 14:13:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!t19no710229qam.0!news-out.google.com!f7ni1003qai.0!nntp.google.com!t19no710225qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Jul 2013 14:13:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.109.165; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.109.165 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: need help to design a VHDL code from an algorithm From: lokesh kumar Injection-Date: Sun, 07 Jul 2013 21:13:32 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6743 Hi, I am new to VHDL. I need to design a VHDL code from an algorithm. Can anyon= e please help me out with it? I am not getting the idea how to implement it= . I want to implement a 163 bit multiplier. So in this case m=3D 163, w =3D 3= 2 and=20 s=3D [m/w] =3D 6 (Because my aim is to design for 63 bit. So for I can tak= e 5, 32 bits and one 3 bit at MSB. Hence the value of S is 6 in total) Here is the algorithm below: INPUT: A=3D (As-1, As-2..., A1, A0) and B=3D (Bs-1, Bs-2,..., B1, B0) OUTPUT: Z=3DA.B=3D(Z2s_1, Z2s-2,..., Z1, Z0) (U,V) <- (0, 0) For i from 0 to s-1 do For j from 0 to s-1 do (U,V) <- (U,V) + Aj .Bi-j end for=20 Zi <- V V <- U, U <- 0 end for for i from s to 2s-2 do for j from i =96 s+1 to s-1 do (U,V) <- (U,V) + Aj . Bi-j end for Zi <- V V <- U, U <- 0 end for Z2s-1 <- V return Z =3D ( Z2s-1, Z2s-2, =85, Z1, Z0)=20 ---------------------------------------------------------------------------= =20 Variables used: m =3D Key length or length of finite field vector (163,233,283, 409, 57= 1) w =3D Digit size (32) s =3D Number of Digits =3D [m/w] i, j =3D Indexes=20 A(t), B(t), Z(t) =3D A finite field element in polynomial basis representat= ion; A(t) =3D (am_1, . . . ,a1,a0), where ai is binary, and similarly for B(t)= and Z(t) C(t) =3D Result of A(t) x B(t); has length 2m- 1 P(t) =3D Irreducible polynomial A =3D (As_1, . . . , A1, A0) Each Ai is a binary vector of size w and simi= larly for B and Z=20 U, V =3D Binary vectors of size w; (U, V) is the concatenation of the two v= ectors=20 T0, . . . , T3 =3D Temporary binary vectors of size w Really hope someone will help me out. Many thanks! From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.89.68 with SMTP id d4mr22886506qam.8.1373248822777; Sun, 07 Jul 2013 19:00:22 -0700 (PDT) X-Received: by 10.49.12.141 with SMTP id y13mr424528qeb.41.1373248822760; Sun, 07 Jul 2013 19:00:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!t19no699116qam.0!news-out.google.com!f7ni1512qai.0!nntp.google.com!t19no731654qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Jul 2013 19:00:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.185.6.233; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 24.185.6.233 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f7467db-d89f-4151-9acc-691d96c03a9b@googlegroups.com> Subject: The lookup table length is wrong in this description? From: fl Injection-Date: Mon, 08 Jul 2013 02:00:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6744 Hi, I read the following on a division algorithm. I cannot get the lookup table= length 4096 as it stated in the last. The first segment for LUT is 511. Is it right? Then, the second segment has the table words: (1023-511)/2=3D256 All the rest segments are the same 256 length. Thus, the total LUT has: 511+6*256=3D2047. It has said that it avoided LUT for negative division. I think the total LU= T is length 2047 (or 2048 for 2's power). What is your opinion on the LUT? 2047 or 4096? Thanks, ......................... Table 1: The optimum segmentation scheme. Segmentation Mapping ratio 1-511 1 : 1 512-1023 1 : 2 1024-2047 1 : 4 2048-4095 1 : 8 4096-8191 1 : 16 8192-16383 1 : 32 16384-32767 1 : 64 Absolute error is calculated by subtracting the true value of the inverse 1/b from the LUT output. Average error is the mean of the absolute error among the 32767 data. Since the value of 1/b retrieved from the LUT is later multiplied by a in order to generate the division result, any precision error in LUT will be eventually magnified by the multiplier. Therefore, the worst-case error is more critical than the average precision error. The worst-case error can be calculated as follows: worst-case error of 1/bk =3D absolute error of (1/bk) =D7 bk-1. The error analysis was performed to investigate both the absolute error in average and the worst-case. As a result of this analysis an optimum segmentation scheme, tabulated in Table 1, was determined. It provides the minimum precision required of a typical hardware-implemented matrix inversion operation. This was verified by means of simulation using Matlab-DSP blockset for a number of applications. The resulting LUT holds 4096 inverse values with a 26-bit word length in 16.10 data format. From newsfish@newsfish Tue Dec 29 16:43:00 2015 X-Received: by 10.224.41.145 with SMTP id o17mr12684598qae.3.1373298457466; Mon, 08 Jul 2013 08:47:37 -0700 (PDT) X-Received: by 10.50.66.208 with SMTP id h16mr2423118igt.11.1373298457418; Mon, 08 Jul 2013 08:47:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no792648qam.0!news-out.google.com!f7ni1559qai.0!nntp.google.com!t19no792643qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jul 2013 08:47:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e3625a2-4519-40cb-9535-f48374f97c8b@googlegroups.com> Subject: Webinar: VHDL Intelligent Coverage using Open Source VHDL Verification Methodology (OSVVM), July 18 From: Jim Lewis Injection-Date: Mon, 08 Jul 2013 15:47:37 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Lines: 49 Xref: news.eternal-september.org comp.lang.vhdl:6745 Date: Thursday, July 18, 2013 OSVVM Europe Session, 3-4 PM CEST (6-7 AM PDT) http://www.aldec.com/e= n/events/303 OSVVM US Session, 11 am - 12 Noon PDT http://www.aldec.com/e= n/events/302 Presented by: Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, = and OS-VVM Chief Architect Abstract: At the lowest level, Open Source VHDL Verification Methodology (OSVVM), is = a set of packages that provide concise and powerful methods to implement fu= nctional coverage and randomization. OS-VVM uses these packages to create a= n intelligent testbench methodology that allows mixing of "Intelligent Cove= rage=99" with directed, algorithmic, file based, or constrained random test= approaches. Having an intelligent testbench approach built into the covera= ge modeling puts OS-VVM a step ahead of other verification methodologies, s= uch as SystemVerilog and UVM. Attend this webinar and learn how to utilize OSVVM to add functional covera= ge, Intelligent Coverage, and constrained random methods to your current te= stbench. Agenda: What and Why OSVVM, Functional Coverage, and Randomization Writing Item (Point Coverage) Writing Cross Coverage Constrained Random is 5X or More Slower Intelligent Coverage OS-VVM is More Capable Additional Randomization in OS-VVM Weighted Intelligent Coverage Coverage Closure OS-VVM Loves any Testbench Additional Methods for Verification Benefits of OSVVM include: Faster Test Construction, focus is on functional coverage Faster simulations: O(Log N) faster than constrained random and no solv= er. Goes beyond other verification languages (SystemVerilog and 'e') Works with your current VHDL testbench Uses entity and architectures for structure (just like RTL). Is language accessible. Able to refine with code. Readable by ALL (Verification and RTL engineers). OSVVM is open-source package based. It compiles under VHDL-2008 or VHDL-200= 2(with minor adaptations), so you can use it today. See http://osvvm.org From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: Mon, 08 Jul 2013 19:35:18 +0200 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Jul 2013 17:29:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="23686"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193OFp+Ww1IUgPCGks85+G1" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130510 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:yDMMN9qpseA0DsWF91kD8MJuVhU= Xref: news.eternal-september.org comp.lang.vhdl:6746 On 07/05/2013 02:34 PM, Theo Markettos wrote: > o pere o wrote: >> As this is for a non-profit research project, we may have the chip done >> and get access to some of the tools at a (hopefully) reasonable cost. I >> will have a look at the synthesis tool you mentioned -I wasn't aware of >> it. Thanks! > > Are you in academia? There may be a way to get cheap access to the tools > through a national academic programme, for example Europractice in Europe: > http://www.europractice.stfc.ac.uk/welcome.html > > But be aware that it may take a long time to become familiar with the tools > - if you're only going to do this once, probably worth contracting it out. > > Theo > Yes, we are already members of Europractice. This was the only way to go in our previous design. And the tools we have been using were certainly a PITA. Now that the pain is slowly receding, I was wondering which tool would help us going on with the digital part :) Pere From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: structured VHDL Date: Tue, 09 Jul 2013 08:31:35 +0200 Lines: 25 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net sQkGegc7e9I8QposC5evlwcxX6pYVL18jriKakFAETP0ieXctR Cancel-Lock: sha1:IiCWO31DMZCoAwQrut9Su38o73M= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6747 Hi everyone, I'm trying to shift my implementation paradigm towards a more functional description and I found some good lectures/articles to structured VHDL (a Google search for 'structured vhdl design method' will provide a handful of links). Unfortunately I have only found a small bunch of examples in Mike Treseler's Folder (http://myplace.frontier.com/~miketreseler/ but be aware that links are referencing to the wrong url...) and not more. Can anyone here point me to some other code for real applications using the two process approach described in the above mentioned articles? Any open discussion on the methodology itself? Thanks a lot, Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.41.145 with SMTP id o17mr19827071qae.3.1373416088926; Tue, 09 Jul 2013 17:28:08 -0700 (PDT) X-Received: by 10.49.17.166 with SMTP id p6mr851865qed.18.1373416088867; Tue, 09 Jul 2013 17:28:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no946701qam.0!news-out.google.com!f7ni1805qai.0!nntp.google.com!t19no993207qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 9 Jul 2013 17:28:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> Subject: Re: structured VHDL From: KJ Injection-Date: Wed, 10 Jul 2013 00:28:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 32 Xref: news.eternal-september.org comp.lang.vhdl:6748 On Tuesday, July 9, 2013 2:31:35 AM UTC-4, alb wrote: > Unfortunately I have only found a small bunch of examples in Mike Tresele= r's=20 > Folder (http://myplace.frontier.com/~miketreseler/ but be aware that link= s > are referencing to the wrong url...) and not more. I'm assuming that you've been able to figure out the correct links to Mike'= s code. It looks like just his root path changed. > Can anyone here point me to some other code for real applications using t= he=20 > two process approach described in the above mentioned articles? Mike would gag if the 'above mentioned articles' that you're talking about = is Mike's stuff. Mike is all about one process, not two...literally. He e= xtensively uses variables shunning all use of signals except to tie togethe= r entities (i.e. he wouldn't use a signal within the architecture. > Any open discussion on the methodology itself? If the methodology you're talking about is what Mike uses, then the best so= urce I've found is Mike's code itself and his postings. You can search thi= s group for Mike's postings (he used to be a prolific poster...he has disap= peared for quite some time which is too bad). If you really *are* interested in 'two process' (i.e. one combinatorial pro= cess with the description of the logic and one clocked process to provide t= he storage of state) then you can pick up a bunch of textbooks. None of th= em would I recommend in this area because there is nothing to recommend abo= ut using the two process approach. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: structured VHDL Date: Wed, 10 Jul 2013 11:25:33 +0200 Lines: 87 Message-ID: References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit X-Trace: individual.net uVR3WLgSvQNUR99blZQZ4g27sbBsvup4TqmCfQk9pnH0qQ1t7F Cancel-Lock: sha1:2sKY9NCB29Jm/Ed31Q1de31FenY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6749 On 10/07/2013 02:28, KJ wrote: > On Tuesday, July 9, 2013 2:31:35 AM UTC-4, alb wrote: >> Unfortunately I have only found a small bunch of examples in Mike >> Treseler's Folder (http://myplace.frontier.com/~miketreseler/ but >> be aware that links are referencing to the wrong url...) and not >> more. > > I'm assuming that you've been able to figure out the correct links > to Mike's code. It looks like just his root path changed. Sure. I didn't know Mike has been out of this group since so long and I believed reporting would have triggered some actions... well I hope some other people will profit of this OT exchange. > >> Can anyone here point me to some other code for real applications >> using the two process approach described in the above mentioned >> articles? > > Mike would gag if the 'above mentioned articles' that you're talking > about is Mike's stuff. Mike is all about one process, not > two...literally. He extensively uses variables shunning all use of > signals except to tie together entities (i.e. he wouldn't use a > signal within the architecture. As a matter of fact here's a presentation where the 'two process approach' is described and Mike Treseler's code is reported as an example: http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl_2010.pdf I realize that Mike's code is all about one process, but I guess the main focus of the 'above mentioned articles' is to move from the haze of processes often found around to a more structured approach where registers and combinatorial logic are well separated: Quoting Ian Lang: (http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm) > What we’ve just done is prove to ourselves that all synchronous > designs can be thought of as two simple elements: > > The registers that hold its present state and The combinatorial logic > that determines its next state. The 'procedural template coding style' (as Mike calls it) is what I'm actually interested in because of its elegance, but I must admit that I will need to read more code to be able to write the same way. > >> Any open discussion on the methodology itself? > > If the methodology you're talking about is what Mike uses, then the > best source I've found is Mike's code itself and his postings. You > can search this group for Mike's postings (he used to be a prolific > poster...he has disappeared for quite some time which is too bad). Then I would be even more interested in reading more of his code, but I guess that is not as 'open' as the one published on the net. If somebody here happens to have GPL-like licensed code from Mike and you are willing to share it I would greatly appreciate. I believe that reading code is sometimes more important than writing it ;-). > > If you really *are* interested in 'two process' (i.e. one > combinatorial process with the description of the logic and one > clocked process to provide the storage of state) then you can pick > up a bunch of textbooks. None of them would I recommend in this > area because there is nothing to recommend about using the two > process approach. >From your words I understand that Mike's approach is not described in any textbook and it lives only in scattered presentations/articles/blogs on the net. Since this method doesn't seem so well spread, how do we know if there is any particular instance, or a particular set of cases, where the 'procedural template coding style' falls short? In the presentation referenced in this message there's a list of problems reported: > - Keep the code synthesizable > - Synthesis tool might choose wrong gate-level structure > - Problems to understand the algorithm for less skilled engineers They seems to me just speculations, but do they hint somehow a lack of 'acceptance' of this method? From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.37.3 with SMTP id v3mr27986488qad.2.1373458443209; Wed, 10 Jul 2013 05:14:03 -0700 (PDT) X-Received: by 10.49.48.201 with SMTP id o9mr941853qen.42.1373458443187; Wed, 10 Jul 2013 05:14:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t19no996518qam.0!news-out.google.com!f7ni1805qai.0!nntp.google.com!t19no1049409qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jul 2013 05:14:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: structured VHDL From: KJ Injection-Date: Wed, 10 Jul 2013 12:14:03 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4957 Xref: news.eternal-september.org comp.lang.vhdl:6750 On Wednesday, July 10, 2013 5:25:33 AM UTC-4, alb wrote: > On 10/07/2013 02:28, KJ wrote: > On Tuesday, July 9, 2013 2:31:35 AM UTC-= 4, alb wrote: >>> Can anyone here point me to some other code for real appl= ications=20 >>> using the two process approach described in the above mentioned=20 >>> articles?=20 >> Mike would gag if the 'above mentioned articles' that you're talking=20 >> about is Mike's stuff. Mike is all about one process, not=20 >> two...literally. He extensively uses variables shunning all use of=20 >> signals except to tie together entities (i.e. he wouldn't use a=20 >> signal within the architecture.=20 > As a matter of fact here's a presentation where the 'two process approach= '=20 > is described and Mike Treseler's code is reported as an example:=20 It's presented as an example called "Single process template program" > http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl_2010.p= df I=20 > realize that Mike's code is all about one process, but I guess the main f= ocus=20 > of the 'above mentioned articles' is to move from the haze of processes o= ften=20 > found around to a more structured approach where registers and combinator= ial=20 > logic are well separated: Quoting Ian Lang: > (http://www.designabstracti= on.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm) > What we=92ve just done is prove to ourselves that all synchronous=20 > designs can be thought of as two simple elements:=20 > The registers that hold its present state and The combinatorial logic=20 > that determines its next state All I have to say here is: - There is no 'haze of processes' - Ian states the obvious...that there is combinatorial logic and registers - Ian overplays this into stating that coding this way is somehow 'structur= ed' - The paper takes non-issues and presents 'solutions' and ignores actual is= sues as well as the new issues that get created by the proposed 'solution' > From your words I understand that Mike's approach is not described in any= textbook=20 > and it lives only in scattered presentations/articles/blogs on the net.= =20 You might be right. > Since this=20 > method doesn't seem so well spread, how do we know if there is any partic= ular=20 > instance, or a particular set of cases, where the 'procedural template co= ding style' > falls short? Any tool (or method) can be misused. The skill of the designer is the most= important element. > In the presentation referenced in this message there's a list of problems= =20 > reported:=20 > - Keep the code synthesizable=20 > - Synthesis tool might choose wrong gate-level structure=20 > - Problems to understand the algorithm for less skilled engineers The first two are laughably wrong, Mike is all about synthesizable code and= the supposed 'wrong gate-level structure' is claptrap. The last point aga= in relates back to the skill of the designer. However, assuming equally sk= illed designers, the supposed 'structured' approach given in the article is= even more likely to have 'Problems to understand the algorithm for less sk= illed engineers'. > They seems to me just speculations,=20 They are just speculating and drawing incorrect conclusions as well. > but do they hint somehow a lack of 'acceptance' of this method? They hint that simply because they wanted to write a paper about their own = method not somebody else. What would be the point of a paper about doing s= omething one way that the authors acknowledge is done better by some other = method? The authors believe there method to be better. I won't begrudge them their= beliefs nor try to convince them otherwise. It's a belief, not a fact. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.41.145 with SMTP id o17mr24251308qae.3.1373479039038; Wed, 10 Jul 2013 10:57:19 -0700 (PDT) X-Received: by 10.182.50.162 with SMTP id d2mr47308obo.3.1373479039001; Wed, 10 Jul 2013 10:57:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t19no1026817qam.0!news-out.google.com!f7ni1805qai.0!nntp.google.com!t19no1084270qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jul 2013 10:57:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: structured VHDL From: Andy Injection-Date: Wed, 10 Jul 2013 17:57:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3065 Xref: news.eternal-september.org comp.lang.vhdl:6751 The ET4351 authors' proposed style uses two processes and three copies of t= he record data type (2 signals and one variable).=20 A single process style like Treseler's uses only one variable of the record= .=20 The authors' style only allows all outputs to be combinatorial or registere= d together, rather than some outputs registered, some combinatorial. Treseler's style allows outputs to be registered or to be combinatorial fun= ctions of process register(s). The authors' style does allow pure combinatorial outputs (combinatorial fun= ction of inputs), which a single clocked process style does not allow. Tres= eler's style allows combinatorial functions of registers to be outputs. Pur= e in-to-out combinatorial functions should be avoided where possible. They = tend to create long timing paths through multiple modules that are difficul= t to detect and create timing problems during P&R. I do not share Treseler's single-process-per-entity preference. There are m= any cases where semi-independent functions in a single entity benefit from = being in separate processes (isolated from access to each other's variables= , except as allowed through signals), yet not needing the coding overhead o= f separate entities. I do use a lot of functions and procedures, but not if the only use is for = the template in Treseler's style (though this sometimes needs a 2nd variabl= e copy). Combinatorial processes waste simulation performance, since the entire proc= ess runs every time/delta cycle in which any input changes. Many simulators= merge processes that share the same sensitivity list for better performanc= e. Combinatorial processes rarely share the same sensitivity list, and ther= efore cannot take advantage of this optimization. Andy From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: structured VHDL Date: Wed, 10 Jul 2013 23:46:22 +0200 Lines: 135 Message-ID: References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit X-Trace: individual.net 6Oeways64Y/Mk/0PrjFNAwQdn8C5IeSYyqmYGUGF02WER5qDyO Cancel-Lock: sha1:aHDLn7vTDds4/FsboNyIIUZw3Rc= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6752 On 10/07/2013 14:14, KJ wrote: >> http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl_2010.pdf I >> realize that Mike's code is all about one process, but I guess the main focus >> of the 'above mentioned articles' is to move from the haze of processes often >> found around to a more structured approach where registers and combinatorial >> logic are well separated: Quoting Ian Lang: > (http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm) >> What we’ve just done is prove to ourselves that all synchronous >> designs can be thought of as two simple elements: >> The registers that hold its present state and The combinatorial logic >> that determines its next state > > All I have to say here is: > - There is no 'haze of processes' my apologies, I intended 'maze'. In this respect I must admit that the DUFF.vhd example (http://www.designabstraction.co.uk/EXAMPLE/HTML/duff.htm) pretty much reflects what I used to write and what I want *not* to repeat in my next projects. But how do you learn to write code at a higher level of abstraction? I guess reading lots of code written that way, but where could I find it? > - Ian states the obvious...that there is combinatorial logic and registers true. But the separation might be at the gate level or higher and this is where Ian style makes a difference (BTW Mike seems to have been strongly inspired by Ian's article, at least from the comments he puts in the uart.vhd example) > - Ian overplays this into stating that coding this way is somehow 'structured' If you think about 'structured programming' as in a paradigm where every computable function can be expressed as a combination of only three control structures, then Ian proposal pretty much follows the same line. Whether is overplayed or not I do not know. > - The paper takes non-issues and presents 'solutions' and ignores actual issues as well as the new issues that get created by the proposed 'solution' Could you be more specific on what kind of 'non-issues' and 'actual issues' you are referring to? Since I consider the talk rather to the point I may have missed/misunderstood an essential part of it. >> Since this >> method doesn't seem so well spread, how do we know if there is any particular >> instance, or a particular set of cases, where the 'procedural template coding style' >> falls short? > > Any tool (or method) can be misused. The skill of the designer is the most important element. Sure, but I guess you would probably agree that a practice which has been used by many will certainly be stressed to the point where pitfalls and benefits are better understood. IMHO a method used by one person only, no matter how skillful is that person, is possibly more prone to show weaknesses in several corner cases. > > >> In the presentation referenced in this message there's a list of problems >> reported: >> - Keep the code synthesizable >> - Synthesis tool might choose wrong gate-level structure >> - Problems to understand the algorithm for less skilled engineers > > The first two are laughably wrong, Mike is all about synthesizable > code and the supposed 'wrong gate-level structure' is claptrap. The > last point again relates back to the skill of the designer. However, > assuming equally skilled designers, the supposed 'structured' > approach given in the article is even more likely to have 'Problems > to understand the algorithm for less skilled engineers'. I may have misunderstood completely the talk but I do not read the 'increasing the abstraction level' slide as a critique to Mike's style w.r.t. their style. On the contrary it seems to me they're trying to give example of higher level of abstraction (including Mike's one process example) and warn about what they believe are weak points of these models. Considering the experience with the LEON vs the ERC32, both quite full fledged projects, it seems their warnings are not that unfounded (even though this is only my speculation). >> They seems to me just speculations, > > They are just speculating and drawing incorrect conclusions as well. Which one specifically? The first bullet qualifies the two-process approach as uniform and I believe rightly since all entities look the same and a designer only needs to look at the combinatorial process to understand the algorithm. Looking at their LEON vs ERC32 example, it seems the method claims less resources than an ad-hoc one, therefore improving development time. I must say that I do not know how simulation and synthesis performances increase with the approach proposed, but it would be nice to see some numbers on this. I doubt though that this lack of facts qualify the conclusion as incorrect. I personally believe the reading is improved by the fact that you do not need to trace several concurrent processes at the same time and your flow of reading the code is more or less sequential. I certainly believe that a readable code is easier to maintain, but I may doubt that this approach does increase the re-usability of the code, at least I consider this last point not more than the author's personal opinion. > >> but do they hint somehow a lack of 'acceptance' of this method? > > They hint that simply because they wanted to write a paper about > their own method not somebody else. What would be the point of a > paper about doing something one way that the authors acknowledge is > done better by some other method? > > The authors believe there method to be better. I won't begrudge them > their beliefs nor try to convince them otherwise. It's a belief, not > a fact. Here I need to urge you to go through the presentation again since I believe, with all due respect, you missed the point. IMO they are *not* proposing their two-processes approach vs Mike's one process approach. They actually use Mike's example to show how increasing the level of abstraction is a good thing. The whole point I got, which still might be wrong, is that their proposed style is way better than what the call 'traditional ad-hoc design style' (pag. 5). Their beliefs are well supported by the example they show (which still may have some peculiarities and hide larger flows of their approach) and it seems to me that Mike's style also supports their conclusions. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail From: Theo Markettos Newsgroups: comp.lang.vhdl Subject: Re: VHDL to CMOS Date: 10 Jul 2013 23:55:56 +0100 (BST) Organization: University of Cambridge, England Lines: 10 Message-ID: References: <8fc3d735-556b-4bb4-b5de-dfdac5ccedbc@googlegroups.com> NNTP-Posting-Host: chiark.greenend.org.uk X-Trace: chiark.greenend.org.uk 1373496958 4949 212.13.197.229 (10 Jul 2013 22:55:58 GMT) X-Complaints-To: abuse@chiark.greenend.org.uk NNTP-Posting-Date: Wed, 10 Jul 2013 22:55:58 +0000 (UTC) User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.32-5-686-bigmem (i686)) Originator: theom@chiark.greenend.org.uk ([212.13.197.229]) Xref: news.eternal-september.org comp.lang.vhdl:6753 o pere o wrote: > Yes, we are already members of Europractice. This was the only way to go > in our previous design. And the tools we have been using were certainly > a PITA. Now that the pain is slowly receding, I was wondering which tool > would help us going on with the digital part :) FWIW I've used Synopsys tools, where Design Compiler is the bit that synthesises verilog (and presumably VHDL too) into standard cells. Theo From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.89.68 with SMTP id d4mr39563340qam.8.1373519806177; Wed, 10 Jul 2013 22:16:46 -0700 (PDT) X-Received: by 10.50.40.104 with SMTP id w8mr3180887igk.1.1373519806102; Wed, 10 Jul 2013 22:16:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t19no1082359qam.0!news-out.google.com!f7ni1940qai.0!nntp.google.com!t19no1144990qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jul 2013 22:16:45 -0700 (PDT) In-Reply-To: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.9.12.125; posting-account=2-ZS5QoAAACNesDDHqcp94t4aGXA0TiD NNTP-Posting-Host: 103.9.12.125 References: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1572e033-18fd-43ee-b298-2e5cbeacc26b@googlegroups.com> Subject: Re: New VHDL Project From: virendra883@gmail.com Injection-Date: Thu, 11 Jul 2013 05:16:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6754 On Thursday, 4 July 2013 18:31:30 UTC+5:30, shankarm...@gmail.com wrote: > hello all this is shankar mishra doing M Tech in Electronics > > can you suggest me some usefull project on VHDL based on current trend in VLSI industry. > > thanx in advance Dear Shankar, You can work on 1. floating point system. 2. E-Stream Encryption and decryption 3. Processor design From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.66.70 with SMTP id m6mr5226060qai.6.1373523411467; Wed, 10 Jul 2013 23:16:51 -0700 (PDT) X-Received: by 10.50.127.239 with SMTP id nj15mr3189929igb.17.1373523411226; Wed, 10 Jul 2013 23:16:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1149593qam.0!news-out.google.com!f7ni1940qai.0!nntp.google.com!t19no1149589qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jul 2013 23:16:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.172.163.237; posting-account=zYWVCAoAAADYmtulAFLuKo_Ql31UzI-e NNTP-Posting-Host: 122.172.163.237 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Subject: Newbie question on combining if rising_edge(clk). From: mindentropy@gmail.com Injection-Date: Thu, 11 Jul 2013 06:16:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:6755 Hi, I am learning vhdl and found when writing a simple clock divider I did a if rising_edge(clk) and div=someval. ISE throws an error saying "The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." I rearranged it to do if(rising_edge(clk) then if (div = someval) .... and it works fine. I don't seem to understand what seems to be wrong? Thanks, Gautam. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: structured VHDL Date: Thu, 11 Jul 2013 08:49:38 +0200 Lines: 80 Message-ID: References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net h4dTs8xGRiap1HwTVcCJcgBWdhY10j3hMEzoztAswa0pvADWj2 Cancel-Lock: sha1:izCarzvOpW5r4mpzGNEjKA+th9U= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6756 On 10/07/2013 19:57, Andy wrote: > The ET4351 authors' proposed style uses two processes and three > copies of the record data type (2 signals and one variable). > > A single process style like Treseler's uses only one variable of the > record.. Does that imply any difference in terms of simulation/synthesis performances? I've always believed signals are much more intensive to process than variables. > > The authors' style only allows all outputs to be combinatorial or > registered together, rather than some outputs registered, some > combinatorial. Uhm, what does prevent us to write this: comb : process (sysif, r) variable v : reg_type; begin v := r; v.irq := '0'; for i in r.pend'range loop v.pend(i) := r.pend(i) or (sysif.irq(i) and r.mask(i)); v.irq := v.irq or r.pend(i); end loop; rin <= v; irqo.irq <= r.irq; -- registered irqo.mask <= v.mask -- not registered irqo.pend <= v.pend -- not registered end process; Isn't the above example a case where some elements of the record are registered and some are not? Maybe I missed your point. [] > The authors' style does allow pure combinatorial outputs > (combinatorial function of inputs), which a single clocked process > style does not allow. Treseler's style allows combinatorial functions > of registers to be outputs. Pure in-to-out combinatorial functions > should be avoided where possible. They tend to create long timing > paths through multiple modules that are difficult to detect and > create timing problems during P&R. that is definitely something one must keep in mind. I share your opinion about in-to-out combinatorial logic, but is not always possible to get rid of them. > I do not share Treseler's single-process-per-entity preference. There > are many cases where semi-independent functions in a single entity > benefit from being in separate processes (isolated from access to > each other's variables, except as allowed through signals), yet not > needing the coding overhead of separate entities. Agreed, but you could still use the template to code the semi-independent functions and connect them through signals in one entity. I believe that coding patterns do simplify a lot code readability since you can nearly skip all the repeated patterns and concentrate only on the differences (in software practices I think is called 'programming by difference'). > I do use a lot of functions and procedures, but not if the only use > is for the template in Treseler's style (though this sometimes needs > a 2nd variable copy). Do you know of any text/article/code which is openly accessible and uses lot of functions and procedures? I would appreciate any pointer. > Combinatorial processes waste simulation performance, since the > entire process runs every time/delta cycle in which any input > changes. Many simulators merge processes that share the same > sensitivity list for better performance. Combinatorial processes > rarely share the same sensitivity list, and therefore cannot take > advantage of this optimization. But if you have one combinatorial (and one sequential) process per entity then the amount of potential different sensitivity lists are just the amount of entities (which still can be large, you may say). In this respect I consider the /all/ keyword introduced in VHDL-2008 as a bad thing. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 09:59:04 +0200 Lines: 46 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net emwqFgInWiI+U9RhhamK9wuIqz7+yi7RhO05IsWOEiOghzG5Hu Cancel-Lock: sha1:fj7c/3Wm/TJex/dAmeDBnnyOXN8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6757 On 11/07/2013 08:16, mindentropy@gmail.com wrote: > Hi, > > I am learning vhdl and found when writing a simple clock divider I > did a if rising_edge(clk) and div=someval. ISE throws an error > saying "The description style you are using to describe a > synchronous element (register, memory, etc.) is not supported in the > current software release." I think it would be useful to know other details like which version of ISE and which technology you are targeting. Moreover the complete error reported by ISE is: > ERROR:Xst:827 - Signal *** cannot be synthesized, bad synchronous > description. The description style you are using to describe a > synchronous element (register, memory, etc.) is not supported in the > current software release. With such a long error message some people decide to post only the first sentence, some others only the second, some other again just a part of the two sentences. IMO either the full message should be reported or only the unique part which is essentially the error code. Searching with Google I nevertheless got this as *first* hit: http://forums.xilinx.com/t5/Archived-ISE-issues/Xst-827-Problem-please-help-me-thx/td-p/20673 which points to the solution: http://www.xilinx.com/support/answers/14047.htm > I rearranged it to do if(rising_edge(clk) then if (div = someval) > .... and it works fine. I don't seem to understand what seems to be > wrong? I would add a little context to the 'if' statement since it is possible that the error is hiding somewhere near it but nobody will ever know without the code. I always struggle a lot when I have to post code since sometimes simplified examples might be not representative of your actual case (therefore ending being just an academic discussion) while other times your actual case might need too much context to be understood and investigated. HTH. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 07:07:35 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 11 Jul 2013 11:02:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="8c4d614d2e42e4bca0d13c3657c4ed6c"; logging-data="2974"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+e2c/4CCbe4Xsi+GCNrGD1" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Cancel-Lock: sha1:zB4DsmM+MEIfqIHV+0gXwYKQVIw= Xref: news.eternal-september.org comp.lang.vhdl:6758 On 7/11/2013 2:16 AM, mindentropy@gmail.com wrote: > Hi, > > I am learning vhdl and found when writing a simple clock divider I did a > if rising_edge(clk) and div=someval. ISE throws an error saying "The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." > > I rearranged it to do > if(rising_edge(clk) then > if (div = someval) > .... > and it works fine. I don't seem to understand what seems to be wrong? > > Thanks, > Gautam. To write it out more clearly... if (A and B) then stuff; end if; compared to... if (A) then if (B) then stuff; end if; end if; Where A is rising_edge(). The second form is easier for tools to see what you intend. Synthesis does not necessarily result from function. It results from form. This is just a feature of the synthesis tool it is not really a language issue. But it does make the code easier for others to read as well. -- Rick From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 13:55:46 +0200 Lines: 29 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ky2KdG74wjvheCncsBpLDAzf9Ey6Duuyq10eakKMyB4dPUdjoo Cancel-Lock: sha1:oKy+ndk/69blVOi1tcH40CreJm0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6759 On 11/07/2013 13:07, rickman wrote: [] > To write it out more clearly... > > if (A and B) then > stuff; > end if; > > compared to... > > if (A) then > if (B) then > stuff; > end if; > end if; > > Where A is rising_edge(). > > The second form is easier for tools to see what you intend. Synthesis > does not necessarily result from function. It results from form. This > is just a feature of the synthesis tool it is not really a language > issue. But it does make the code easier for others to read as well. shouldn't the first form correspond to a gated clock, where the second to just a clock enable? If this is the case the difference between the two is *a lot*. If we are not talking about clocked processes than AFAIK the two forms should be completely equivalent. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 14:57:01 +0200 Lines: 52 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net ZYXVDUR6EgBWC6Qd3mLFJAjhGmPXT4au686HuT6zfwKrHDDFbp Cancel-Lock: sha1:b/Z+R5th3B5bUyZZ4Aa8Sc7+GLc= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:6760 rickman wrote: > To write it out more clearly... > > if (A and B) then > stuff; > end if; > > compared to... > > if (A) then > if (B) then > stuff; > end if; > end if; > > Where A is rising_edge(). > > The second form is easier for tools to see what you intend. Synthesis > does not necessarily result from function. It results from form. This > is just a feature of the synthesis tool it is not really a language > issue. But it does make the code easier for others to read as well. This is not just an issue of form. The two descriptions actually describe different things, since priorities are different. The second description first checks for A, and only if that is met is B even evaluated. So if A is rising_edge(), this forces the tool to synthesize an entity that reacts to EVERY rising_edge, and then does "stuff" if B is true. So this is basically a simple flip-flop or other synchronous element with a synchronous reset, set or a synchronous clock enable (depending on what "stuff" actually is); no problem there, since that is exactly what Xilinx' flipflops are. The first description on the other hand checks for A and B simultaneously. So if A is rising_edge(), that would mean you want to synthesize some entity that only reacts to clock edges under specific circumstances, resulting in something like an asynchronous clock enable, or a register with built-in clock gating or something. And that is something that does not exist per se in the Xilinx architecture and/or is highly recommended against (in the case of clock gating), so there's no way for XST to correctly automatically synthesize something that behaves in a way that matches what is described. Hence the error message, and since this is a common mistake, they warrant a guess as to what you really wanted to describe. Xilinx White Paper WP275 (http://www.xilinx.com/support/documentation/white_papers/wp275.pdf) is quite interesting, the topic is similar. Greetings, Sean From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.37.3 with SMTP id v3mr35064635qad.2.1373560581378; Thu, 11 Jul 2013 09:36:21 -0700 (PDT) X-Received: by 10.49.4.201 with SMTP id m9mr1190359qem.15.1373560581321; Thu, 11 Jul 2013 09:36:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t19no1138348qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1207080qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 09:36:21 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.109.165; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.109.165 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <663826fe-8b98-4efe-ae46-9de20dc42bf7@googlegroups.com> Subject: Can anyone help me to design a n bit input and n bit output shift register From: lokesh kumar Injection-Date: Thu, 11 Jul 2013 16:36:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6761 Hi, I need a help to understand how the shift register works. Suppose A and B are the 5-bit numbers. A= 10101 B=11001 1. B(i) = 1 is the MSB 1st bit of B input 2. B(i) = 1 is the MSB 2nd bit of B input 3. B(i) = 0 is the MSB 3rdst bit of B input 4. B(i) = 0 is the MSB 4thd bit of B input 5. B(i) = 1 is the MSB 5thbit of B input Basically the 1st MSB of B is multiplied with the 5-bit number A first. Then the 2nd MSB of B is multiplied with A and so on. So I want to know how can I insert the values of B in this case. Can anyone please help me out with the VHDL code? Many thanks! From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.41.145 with SMTP id o17mr30037300qae.3.1373563413046; Thu, 11 Jul 2013 10:23:33 -0700 (PDT) X-Received: by 10.182.75.136 with SMTP id c8mr55942obw.9.1373563413007; Thu, 11 Jul 2013 10:23:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1212128qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1212126qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 10:23:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2679b9df-732c-411b-a0cd-ccc8a550be1b@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: Jim Lewis Injection-Date: Thu, 11 Jul 2013 17:23:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 58 Xref: news.eternal-september.org comp.lang.vhdl:6762 Dear Xilinx, While, 1076.6-1999 (VHDL RTL Synthesis Standard) only requires that the fol= lowing is supported: process(clk) begin if rising_edge(Clk) then if (div =3D someval) then ... IEC 62050-2005 (was IEEE 1076.6-2004) requires that the following is suppor= ted as a flip-flop with load enable (gating on data path): process(clk) begin if rising_edge(Clk) and (div =3D someval) then ... =20 I disagree with @Sean's analysis. The "A and B" does not check them both s= imultaneously if the results are boolean. Instead, "and" is a short circui= t operator, and when it determines the rising edge is false it has determin= ed the result is false, does not analyze B. Hence, from a VHDL perspective= the code runs the same. You could make arguments about reversing the orde= r of the clock, however, IEC 62050-2005 still treats it as a flip-flop with= load enble. Historically ASIC vendors have use an attribute with the 1076.6-1999 style = to transform it from a data path enable to a clock gate.=20 What is happening here is called market driven support of standards. From = a vendors perspective, why spend money and support features unless their us= ers are asking for them. From a user's perspective, when a vendor takes th= is position, they stifle progress within the industry. =20 _If you are a Xilinx customer_, please submit a bug report on this and cite= IEC 62050-2005 (was IEEE 1076.6-2004) as a reference. Make sure to refere= nce the IEC standard as I think the IEEE version was deprecated. If you want to know more about some of the IEC 62050-2005 /1076.6-2004 codi= ng styles, check out my 2002 HDLCon paper, "Extensions to the VHDL RTL Synt= hesis Standard" on the page: http://www.synthworks.com/papers/ It really is shameful that 9 years have gone by since the standard was fina= lized and 11 since my paper and Xilinx still does not support these. Going further, there is so much more we should be able to do that has not b= een covered in the RTL synthesis standard yet. If anyone is interested in = this effort, I can advise you on working through the IEEE standards process= . You will need to get the synthesis vendors on board to insure it gets su= pported. Best Regards, Jim Lewis IEEE 1076 Working Group Chair Former IEEE 1076.6 Vice Chair VHDL Training Expert, SynthWorks From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.86.200 with SMTP id t8mr42617817qal.0.1373564586565; Thu, 11 Jul 2013 10:43:06 -0700 (PDT) X-Received: by 10.49.101.78 with SMTP id fe14mr1167148qeb.13.1373564586530; Thu, 11 Jul 2013 10:43:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.ripco.com!news.glorb.com!t19no1214093qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1214091qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 10:43:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5764a63f-7b15-4c15-beee-cf83ceb110c4@googlegroups.com> Subject: Re: structured VHDL From: Andy Injection-Date: Thu, 11 Jul 2013 17:43:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6763 Alb, Especially when signals are used to trigger combinatorial processes, there = is much more overhead than variables, and even moreso if the signal is assi= gned with a delay. I would expect decent simulators to significantly optimi= ze the overhead on a signal for which there are no delays or sensitive proc= esses. But there is still the overhead of separate execution (computing the= value to be assigned) and update (upon process suspension) for signals eve= n within a single process. Variables lack this duality and its associated o= verhead. In my experience, using integers where possible for numeric quanti= ties (counters, etc.) yields a far more significant simulation performance = improvement than variables vs signals. WRT combinatorial vs registered outputs from the authors' style, yes, one c= ould separately assign outputs from the corresponding elements of v or r. H= owever, in separate examples they assigned outputs either all from v, or al= l from r, with no mixing. If I was to use that style and wanted a mixture o= f r and v. I would probably assign the outputs en mass from the more common= , and re-assign only those that differ (to borrow your mention of 'programm= ing by difference'). I would expect the overhead of duplicate/overriding as= signments in simulation to be trivial. On the rare occasion that I need a combinatorial in-out path through an ent= ity, I would prefer that to be the only situation where I use a combinatori= al process (this tends to make such a practice stand out in the code, which= it should.) Common combinatorial logic feeding multiple sequential process= es can better be expressed by a function or procedure invoked in each proce= ss, IMHO. Synthesis is plenty smart enough to figure out if only one copy o= f the logic is really needed. I think maybe you do not understand the effects of the new "all" keyword in= a sensitivity list. It does NOT indicate that the process is sensitive to = all signals visible by the process. "All" indicates that the process is sen= sitive to any signal read by the process. Therefore, it has zero simulation= performance impact on a combinatorial RTL process. By embedding the combinatorial process functionality in the clocked process= , the level of control nesting is increased by one if-statement (or two if = asynchronous reset is used). If one really wants to avoid that increase, th= en follow Treseler's model and include the combinatorial functionality in a= procedure. However, the root of the limitation on levels of control is bas= ed on testability. Declaring and using a separate procedure does not improv= e testabiliy unless the procedure is externally accessible (e.g. in a packa= ge)for separate testing. However, a procedure declared in a package no long= er has implicit access to signals visible by the process in which it was or= iginally declared. Such signals would have to be passed through the procedu= re call explicitly, preferably through records. In practice, the reset and = clock controls are so ubiquitous in RTL that it is pointless to consider th= eir impact on testability. As for texts and examples on subprograms in RTL, I do not know of any exten= sive references. For synthesizable RTL, subprograms are prohibited from con= suming time/delta cycles (e.g. no wait statements within the subprogram.) F= unctions cannot contain wait statements anyway. This effectively limits sub= programs to describing combinatorial logic only. However, this allows repla= cing the second, combinatorial process in the authors' style with an equiva= lent procedure that can be called from the concurrent process. Thus one can= have their cake and eat it too: one clocked process, but with explicit sep= aration of register and combinatorial logic descriptions which some seem to= prefer.=20 I prefer an RTL style that emphasizes clock cycles of latency, and let the = synthesis tool determine where registers must be inserted to accomplish sai= d latency. If one uses retiming/pipelining optimizations during synthesis, = the input-output latency is the only aspect retained by the implementation = anyway. This style uses variables to describe function and latency by contr= olling the order of reading and writing a variable during the same clock cy= cle. Like Treseler, signals are only used for inter-process communication.= =20 A few tips on RTL subprograms. Concurrent procedure calls are allowed, but are easily confused with compon= ent instantiations (for a purely combinatorial component, which I rarely if= ever use). I avoid concurrent procedure calls in RTL altogether. If used c= oncurrently, procedures must use constant and/or signal class interfaces. On the other hand, do not use signal class interfaces on procedures called = in processes, use variable or constant classes instead. The delayed update = semantics of signals in processes becomes even more confusing when procedur= es are involved. When a subprogram is declared in a process, it has visibility to anything v= isible by the process. It also has visibility to any variables, types or su= bprograms declared before it in the process declarative region (before the = begin statement). When declared outside a process, a procedure cannot drive any signal not ex= plicitly passed to it. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 13:50:54 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 11 Jul 2013 17:45:14 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="b0148e4cca01347b609321a5e920da0f"; logging-data="3948"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+B0bW2A8rWVSOo5NGrjb9E" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:YAhL4UQWUTE6H6zTc3CTXc6+vM4= Xref: news.eternal-september.org comp.lang.vhdl:6764 On 7/11/2013 7:55 AM, alb wrote: > On 11/07/2013 13:07, rickman wrote: > [] >> To write it out more clearly... >> >> if (A and B) then >> stuff; >> end if; >> >> compared to... >> >> if (A) then >> if (B) then >> stuff; >> end if; >> end if; >> >> Where A is rising_edge(). >> >> The second form is easier for tools to see what you intend. Synthesis >> does not necessarily result from function. It results from form. This >> is just a feature of the synthesis tool it is not really a language >> issue. But it does make the code easier for others to read as well. > > shouldn't the first form correspond to a gated clock, where the second > to just a clock enable? If this is the case the difference between the > two is *a lot*. > > If we are not talking about clocked processes than AFAIK the two forms > should be completely equivalent. Even if you are talking about gated processes (A is rising_edge(x)), there is nothing functionally different about the two. They will simulate exactly the same. My point is that while simulation will show an equivalence between the two, the synthesis tools can make distinctions based on "form" meaning exactly how you write the code. Logically speaking, why would the first be a gated clock but not the second? There is nothing in the VHDL standard that mentions gated vs. enabled clocks. I think there is a standard for synthesis but I don't know if it covers gated clocks. Anyone know? -- Rick From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 13:55:15 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <2679b9df-732c-411b-a0cd-ccc8a550be1b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 11 Jul 2013 17:49:28 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="b0148e4cca01347b609321a5e920da0f"; logging-data="3999"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/uEb02t9tXB4BgEHur2hM" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <2679b9df-732c-411b-a0cd-ccc8a550be1b@googlegroups.com> Cancel-Lock: sha1:+zL/PpyZo7J0Znd86UiuuycbCFk= Xref: news.eternal-september.org comp.lang.vhdl:6765 On 7/11/2013 1:23 PM, Jim Lewis wrote: > Dear Xilinx, > While, 1076.6-1999 (VHDL RTL Synthesis Standard) only requires that the following is supported: > > process(clk) > begin > if rising_edge(Clk) then > if (div = someval) then > ... > > IEC 62050-2005 (was IEEE 1076.6-2004) requires that the following is supported as a flip-flop with load enable (gating on data path): > > process(clk) > begin > if rising_edge(Clk) and (div = someval) then > ... > > I disagree with @Sean's analysis. The "A and B" does not check them both simultaneously if the results are boolean. Instead, "and" is a short circuit operator, and when it determines the rising edge is false it has determined the result is false, does not analyze B. Hence, from a VHDL perspective the code runs the same. You could make arguments about reversing the order of the clock, however, IEC 62050-2005 still treats it as a flip-flop with load enble. > > Historically ASIC vendors have use an attribute with the 1076.6-1999 style to transform it from a data path enable to a clock gate. > > > What is happening here is called market driven support of standards. From a vendors perspective, why spend money and support features unless their users are asking for them. From a user's perspective, when a vendor takes this position, they stifle progress within the industry. > > _If you are a Xilinx customer_, please submit a bug report on this and cite IEC 62050-2005 (was IEEE 1076.6-2004) as a reference. Make sure to reference the IEC standard as I think the IEEE version was deprecated. > > > If you want to know more about some of the IEC 62050-2005 /1076.6-2004 coding styles, check out my 2002 HDLCon paper, "Extensions to the VHDL RTL Synthesis Standard" on the page: > http://www.synthworks.com/papers/ > > It really is shameful that 9 years have gone by since the standard was finalized and 11 since my paper and Xilinx still does not support these. > > Going further, there is so much more we should be able to do that has not been covered in the RTL synthesis standard yet. If anyone is interested in this effort, I can advise you on working through the IEEE standards process. You will need to get the synthesis vendors on board to insure it gets supported. > > Best Regards, > Jim Lewis > IEEE 1076 Working Group Chair > Former IEEE 1076.6 Vice Chair > VHDL Training Expert, SynthWorks Looks like you answered my questions from the post I just made. I should have finished reading the thread before I replied. Thanks for the info, this is just what I couldn't remember. -- Rick From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 11 Jul 2013 13:56:10 -0400 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 11 Jul 2013 17:50:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="b0148e4cca01347b609321a5e920da0f"; logging-data="3999"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+RRvRVp0kHI86Wa+c3le7j" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:x1TlA1UMyOMOIsUKMYRW3fw/jN4= Xref: news.eternal-september.org comp.lang.vhdl:6766 On 7/11/2013 1:50 PM, rickman wrote: > On 7/11/2013 7:55 AM, alb wrote: >> On 11/07/2013 13:07, rickman wrote: >> [] >>> To write it out more clearly... >>> >>> if (A and B) then >>> stuff; >>> end if; >>> >>> compared to... >>> >>> if (A) then >>> if (B) then >>> stuff; >>> end if; >>> end if; >>> >>> Where A is rising_edge(). >>> >>> The second form is easier for tools to see what you intend. Synthesis >>> does not necessarily result from function. It results from form. This >>> is just a feature of the synthesis tool it is not really a language >>> issue. But it does make the code easier for others to read as well. >> >> shouldn't the first form correspond to a gated clock, where the second >> to just a clock enable? If this is the case the difference between the >> two is *a lot*. >> >> If we are not talking about clocked processes than AFAIK the two forms >> should be completely equivalent. > > Even if you are talking about gated processes (A is rising_edge(x)), Correction......................^^^^^ should be "clocked"... > there is nothing functionally different about the two. They will > simulate exactly the same. > > My point is that while simulation will show an equivalence between the > two, the synthesis tools can make distinctions based on "form" meaning > exactly how you write the code. > > Logically speaking, why would the first be a gated clock but not the > second? There is nothing in the VHDL standard that mentions gated vs. > enabled clocks. I think there is a standard for synthesis but I don't > know if it covers gated clocks. Anyone know? > -- Rick From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.67.1.8 with SMTP id bc8mr3255017pad.35.1373595605003; Thu, 11 Jul 2013 19:20:05 -0700 (PDT) X-Received: by 10.50.108.47 with SMTP id hh15mr35645igb.12.1373595604734; Thu, 11 Jul 2013 19:20:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!weretis.net!feeder1.news.weretis.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!qx7no30482722pbc.1!news-out.google.com!b2ni61451pby.1!nntp.google.com!qx7no30482718pbc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 19:20:04 -0700 (PDT) In-Reply-To: <2679b9df-732c-411b-a0cd-ccc8a550be1b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.172.36.191; posting-account=zYWVCAoAAADYmtulAFLuKo_Ql31UzI-e NNTP-Posting-Host: 122.172.36.191 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <2679b9df-732c-411b-a0cd-ccc8a550be1b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question on combining if rising_edge(clk). From: mindentropy@gmail.com Injection-Date: Fri, 12 Jul 2013 02:20:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6767 On Thursday, July 11, 2013 10:53:32 PM UTC+5:30, Jim Lewis wrote: > Dear Xilinx, >=20 > While, 1076.6-1999 (VHDL RTL Synthesis Standard) only requires that the f= ollowing is supported: >=20 >=20 >=20 > process(clk) >=20 > begin >=20 > if rising_edge(Clk) then >=20 > if (div =3D someval) then >=20 > ... >=20 >=20 >=20 > IEC 62050-2005 (was IEEE 1076.6-2004) requires that the following is supp= orted as a flip-flop with load enable (gating on data path): >=20 >=20 >=20 > process(clk) >=20 > begin >=20 > if rising_edge(Clk) and (div =3D someval) then >=20 > ... =20 >=20 >=20 >=20 > I disagree with @Sean's analysis. The "A and B" does not check them both= simultaneously if the results are boolean. Instead, "and" is a short circ= uit operator, and when it determines the rising edge is false it has determ= ined the result is false, does not analyze B. Hence, from a VHDL perspecti= ve the code runs the same. You could make arguments about reversing the or= der of the clock, however, IEC 62050-2005 still treats it as a flip-flop wi= th load enble. >=20 >=20 >=20 > Historically ASIC vendors have use an attribute with the 1076.6-1999 styl= e to transform it from a data path enable to a clock gate.=20 >=20 >=20 >=20 >=20 >=20 > What is happening here is called market driven support of standards. Fro= m a vendors perspective, why spend money and support features unless their = users are asking for them. From a user's perspective, when a vendor takes = this position, they stifle progress within the industry. =20 >=20 >=20 >=20 > _If you are a Xilinx customer_, please submit a bug report on this and ci= te IEC 62050-2005 (was IEEE 1076.6-2004) as a reference. Make sure to refe= rence the IEC standard as I think the IEEE version was deprecated. >=20 >=20 >=20 >=20 >=20 > If you want to know more about some of the IEC 62050-2005 /1076.6-2004 co= ding styles, check out my 2002 HDLCon paper, "Extensions to the VHDL RTL Sy= nthesis Standard" on the page: >=20 > http://www.synthworks.com/papers/ >=20 >=20 >=20 > It really is shameful that 9 years have gone by since the standard was fi= nalized and 11 since my paper and Xilinx still does not support these. >=20 >=20 >=20 > Going further, there is so much more we should be able to do that has not= been covered in the RTL synthesis standard yet. If anyone is interested i= n this effort, I can advise you on working through the IEEE standards proce= ss. You will need to get the synthesis vendors on board to insure it gets = supported. >=20 >=20 >=20 > Best Regards, >=20 > Jim Lewis >=20 > IEEE 1076 Working Group Chair >=20 > Former IEEE 1076.6 Vice Chair >=20 > VHDL Training Expert, SynthWorks Thanks Jim for clarifying. From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.40.65 with SMTP id j1mr21357459qae.7.1373597628537; Thu, 11 Jul 2013 19:53:48 -0700 (PDT) X-Received: by 10.49.94.174 with SMTP id dd14mr1200614qeb.14.1373597628501; Thu, 11 Jul 2013 19:53:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!t19no1266265qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1266258qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 19:53:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3c79d346-5726-4628-97a9-2e80c4c06f68@googlegroups.com> Subject: Re: structured VHDL From: KJ Injection-Date: Fri, 12 Jul 2013 02:53:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6768 On Wednesday, July 10, 2013 5:46:22 PM UTC-4, alb wrote: > > - Ian states the obvious...that there is combinatorial logic and registers > > > true. But the separation might be at the gate level or higher and this > is where Ian style makes a difference What difference do you think it makes? The 'style' it is written in will make no difference. Synthesis will take the description and turn it into logic that is implemented in 'gates' (or connections to LUT) as well as flip flops (or memory). The tools really do not need any help from the user in figuring out which is which. > > > If you think about 'structured programming' as in a paradigm where every > computable function can be expressed as a combination of only three > control structures, then Ian proposal pretty much follows the same line. > Whether is overplayed or not I do not know. > That does not imply that the 'best' way to describe the code is in that form. The soft metrics for 'best' here should be maintainability. On the assumption that one can write code that meets the function and performance requirements in many different ways, then one looks towards source code maintainability which would be the ability for somebody (not necessarily the original designer) to get up to speed on the design. Clumping all of the unrelated code physically together because it describes the transfer function is rather pointless. Clumping parts of code together that are inter-related makes sense. > > > - The paper takes non-issues and presents 'solutions' and ignores actual issues as well as the new issues that get created by the proposed 'solution' > > > Could you be more specific on what kind of 'non-issues' and 'actual > issues' you are referring to? Since I consider the talk rather to the > point I may have missed/misunderstood an essential part of it. > I'll just nitpick on a few points in no particular priority, just the order that they are in the presentation. - Other than the last bullet about auto-generated code, nothing on the slide titled 'Traditional VHDL design methodology' is worth the time it took to type. It's all wrong. Maybe some people have done he says here but that doesn't make it 'Traditional'. The statement 'Hard to read = difficult to maintain' was written and made to seem important by coloring it in red by Capt. Obvious. - The next slide 'Traditional ad-hoc design style' is similarly biased and worthless. Taking the statement 'No unified signal naming convention' as one example. The upcoming 'unified' naming convention will not add anything useful (more later). The statement 'Coding is done at low RTL level' is laughable. Again some may code this way, but let's not make elevate those people to be considered the traditionalists. - Slide 'Unified signal naming example'. Only the convention for 'types' has any value and that is because use of the type name can frequently be used throughout the code and it can be of value sometimes to easily differentiate that xyz is a data type. Specific objections to the others are: * _in -- Yeah, I hadn't noticed that I only use the signal on the right hand side so it must be an input. If you use a compiler that doesn't complain about assigning to an input than maybe you need _in...or maybe you need to use a real tool. * _out -- Ditto * _s and _v -- Every signal and variable will have a logic meaning conveyed by the name of the signal/variable. When that logic meaning is conveyed I'll use the appropriate assignment operator and if I forget the compiler will cough. When I go to *use* that thing which is the more important thing then I really don't care that it is a signal or variable. * _pkg -- It would be better to use it as a prefix so that all the packages will list together if I needed to get at some signal in a package...but that's about it * p_ and i_ -- Why? These can never be referenced elsewhere...the authors clearly thought that they wouldn't have a complete unified example unless they had a scheme for naming everything, whether it has utility or not. Doing extra for no benefit is not a benefit. -- Conclusion on the naming convention...very little actual value since it doesn't help prevent design errors, it doesn't help debug problems it just causes more typing for no tangible benefit. If you doubt this, then state the tangible benefit in terms of productivity or maintainability since that is the only metric that could possibly be affected by this convention. Note: Stating 'I want to know that an object is a signal or a variable simply by looking at the name' doesn't cut it. Reason: Without stating the reason why knowing the object type helps your productivity means you're wondering pointlessly. - Slide 'The abstracted view in VHDL : the two-process scheme' and successors describing the method does not justify how productivity would increase with any of the schemes. Examples: * The collection of signals and/or ports into records groups together things that are logically completely unrelated other than by the fact that they are pieces of an entity/architecture. As an example, consider an entity that receives input data, processes it, and then outputs the data. Further the input data interface has some implementation protocol, the output has a different protocol, both protocols imposed by external forces (i.e. you can't change them, maybe they are external device I/O). The natural collection from my perspective is input interface signals, output interface signals and processing algorithm signals. The input and output interfaces likely have nothing at all to do with each other...so why should they be collected into a record together as if they are? Think about it. The input interface likely has some state machine, the output interface has another, the processing algorithm possibly a third. Do you think those three state machines should be all lumped together? No? Then what benefit is it to lump them into a record together? (Hint: None) But maybe you think there is no cost to doing so...think again. Try to follow the logic for a particular signal (because when you're debugging real designs that's what you do) and see how utterly useless you've made the Modelsim Dataflow window by collecting every possible thing into one process fed by one signal. Guess what? Almost every signal is a function of only a small handful of actual signals. By lumping this small handful in with a boatload of unrelated signals by putting them into some bigger record will not help you be more productive. - Slide 'Benefits'...every single supposed benefit except for 'Sequential coding is well known and understood' is wrong. How is the 'algorithm' easily extractable as stated? Take the example I mentioned earlier. There are at least three 'algorithms' going on: input protocol, output protocol and processing algorithm...and yet the proposed method will lump these together into one supposed 'algorithm'. What is stated by the author as an 'algorithm' is not really an algorithm, all it is is the combinatorial logic... - The other supposed benefits are merely unsubstantiated beliefs...I'll leave it to you to show in concrete terms how any of them are either generally true. Be specific. - Adding a port: While I do agree that the method does make it easier to add and subtract I/O, I'll counter with if you'd put more thought into using a consistent interface protocol in the first place (example: Avalon or Wishbone) you wouldn't find yourself adding and subtracting ports in the first place because you'd get it right (or very nearly right) the first time. So this becomes a benefit of small value over a superior method that mostly avoids the issue. - Adding a register: There simply is no benefit here. Use a single clocked process and the few concurrent statements where needed. - Slide 'Tracing signals during debugging' is ridiculous. This method makes it much harder to display the signals that are actually relevant to whatever debug you're trying to perform. Remember that most signals are NOT a function of every other signal that is in these records so by tracing the record you still have to hunt around and find the elements that you are actually interested in seeing...no help there, I can see those signals just as easily from the signal list window. No benefit, medium cost...no thanks. - Slide 'Stepping through code during debugging'. This is generally the last thing one needs to do unless you make heavy use of variables in which case you're stuck and forced to single step. If you use signals you can usually trace through the code without any single stepping and fix the problem. Remember: when a sim stops due to an assertion, the faulty behavior has already occurred, no amount of single stepping helps you here because the 'bad' thing (whatever that may be) has already happened. No benefit here. - Slide 'Comparison MEC/LEON'...has the skill of the designers involved been controlled for? If not then this is just a comparison of two different designs, so what? Maybe the LEON people were simply better designers than the MEC shleps. Not enough information here to determine anything but you're certainly entitled to infer whatever result you think you see here. - Slide 'Increasing the abstraction level' is a misnomer. The method described does not increase abstraction, it simply collects unrelated signals into a tidy (but more difficult to use) bucket. The supposed 'benefits' and 'problems' are completely unsubstantiated and are simply opinions presented as 'facts'. - Slide 'Conclusions'...all opinion presented as unsubstantiated fact. > > > > The first two are laughably wrong, Mike is all about synthesizable > > code and the supposed 'wrong gate-level structure' is claptrap. The > > last point again relates back to the skill of the designer. However, > > assuming equally skilled designers, the supposed 'structured' > > approach given in the article is even more likely to have 'Problems > > to understand the algorithm for less skilled engineers'. > > > I may have misunderstood completely the talk but I do not read the > 'increasing the abstraction level' slide as a critique to Mike's style > w.r.t. their style. > It sounds better to say 'higher abstration level' than 'collecting unrelated signals' doesn't it? > On the contrary it seems to me they're trying to give example of higher > level of abstraction (including Mike's one process example) and warn > about what they believe are weak points of these models. Considering the > experience with the LEON vs the ERC32, both quite full fledged projects, > it seems their warnings are not that unfounded (even though this is only > my speculation). > I don't know what they were trying to show with Mike's example. > > >> They seems to me just speculations, > > > > They are just speculating and drawing incorrect conclusions as well. > > > Which one specifically? > The first bullet qualifies the two-process approach as uniform and I > believe rightly since all entities look the same and a designer only > needs to look at the combinatorial process to understand the algorithm. > Only if you're implementing embarassingly simple entities I suppose. For anything real, you're making things worse (refer to my simple example stated earlier of a generic processing module). > Looking at their LEON vs ERC32 example, it seems the method claims less > resources than an ad-hoc one, therefore improving development time. > The most likely reason is more skilled designers rather than style...prove me wrong. > > I personally believe the reading is improved by the fact that you do not > need to trace several concurrent processes at the same time and your > flow of reading the code is more or less sequential. > The reading improvement won't be because of the proposed method. > I certainly believe that a readable code is easier to maintain, but I > may doubt that this approach does increase the re-usability of the code, > at least I consider this last point not more than the author's personal > opinion. > A designer's goal is to implement a specific function and meet a specific level of performance. A method that makes traceability of the function specification to the source code easier is 'good'. The seperation of that description into a collection of all combinatorial logic needed to implement the function and a seperate clocked process does absolutely nothing to define tracability back to the specification. The specification will most likely have no mention of combinatorial or storage, that is an implementation decision. Therefore the proposed seperation does not aid tracability and in fact makes it harder to follow. > > > > >> but do they hint somehow a lack of 'acceptance' of this method? > > > > > They hint that simply because they wanted to write a paper about > > their own method not somebody else. What would be the point of a > > paper about doing something one way that the authors acknowledge is > > done better by some other method? > > > > The authors believe there method to be better. I won't begrudge them > > their beliefs nor try to convince them otherwise. It's a belief, not > > a fact. > > > Here I need to urge you to go through the presentation again since I > believe, with all due respect, you missed the point. IMO they are *not* > proposing their two-processes approach vs Mike's one process approach. > They actually use Mike's example to show how increasing the level of > abstraction is a good thing. > Nope. Calling it a 'higher level abstraction' doesn't make it so. You've simply collected together unrelated signals into various records. Records are a good thing, collecting unrelated things into a record...not so good thing. > The whole point I got, which still might be wrong, is that their > proposed style is way better than what the call 'traditional ad-hoc > design style' (pag. 5). > Different, not better. > Their beliefs are well supported by the example they show (which still > may have some peculiarities and hide larger flows of their approach) and > it seems to me that Mike's style also supports their conclusions. > And you of course are entitled to your opinion as well and I mean that with absolutely no disrespect or sarcasm or anything else negative. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.29.76 with SMTP id p12mr45453930qac.5.1373604161648; Thu, 11 Jul 2013 21:42:41 -0700 (PDT) X-Received: by 10.50.9.40 with SMTP id w8mr63834iga.4.1373604161572; Thu, 11 Jul 2013 21:42:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!t19no1275076qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1275070qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Jul 2013 21:42:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.172.47.222; posting-account=zYWVCAoAAADYmtulAFLuKo_Ql31UzI-e NNTP-Posting-Host: 122.172.47.222 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Doubts on processes using a single clock. From: mindentropy@gmail.com Injection-Date: Fri, 12 Jul 2013 04:42:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6769 Hi, I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture. The code is as follows: sectimer: process(clk) is begin: if(rising_edge(clk)) then if(div = someval) increment counter; end if; end process; seven_seg_proc: process(clk) is begin: if(rising_edge(clk)) then end if; end process; The problem is the counter does not seem to increment fine. If I decrease the divider the counter does not increment faster. Can I have 2 processes driving the clock? From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.172.129 with SMTP id l1mr28718406qaz.4.1373616274353; Fri, 12 Jul 2013 01:04:34 -0700 (PDT) X-Received: by 10.49.35.195 with SMTP id k3mr1219552qej.2.1373616274341; Fri, 12 Jul 2013 01:04:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1290252qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1290251qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Jul 2013 01:04:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Doubts on processes using a single clock. From: goouse99@gmail.com Injection-Date: Fri, 12 Jul 2013 08:04:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 79 Xref: news.eternal-september.org comp.lang.vhdl:6770 Am Freitag, 12. Juli 2013 06:42:41 UTC+2 schrieb minde...@gmail.com: > Hi, > > I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture. > > > > The code is as follows: > > > > sectimer: process(clk) is > > begin: > > if(rising_edge(clk)) then > > if(div = someval) > > increment counter; > > end if; > > end process; > > > > seven_seg_proc: process(clk) is > > begin: > > if(rising_edge(clk)) then > > > > end if; > > end process; > > > > The problem is the counter does not seem to increment fine. If I decrease the > > divider the counter does not increment faster. Can I have 2 processes driving the clock? Hi, there's nothing wrong with having a number of processes using the same clock. But from the code snippet I found some strane thing: How do you set back the counter? Where does div come from? I there another process involved? How many clock cycles does div hold its value constant? If you have a proces that acts as a clock divider you should do the comparing there and generate a ClockEnable signal. clk_div: process(clk) is variable: div = natural range 0 to divmax+1 ; begin: if(rising_edge(clk)) then div:= div+1; ClockEnable <= '0'; if(div = divmax) then div:= 0; ClockEnable <= '1'; end if; end if; end process; sectimer: process(clk) is begin: if(rising_edge(clk)) then if(ClockEnable = '1') then --increment counter; end if; end process; This also saves you from having big comparators in every process which may reduce Fmax of the design. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.29.76 with SMTP id p12mr46300167qac.5.1373616930123; Fri, 12 Jul 2013 01:15:30 -0700 (PDT) X-Received: by 10.49.5.106 with SMTP id r10mr1221062qer.11.1373616930101; Fri, 12 Jul 2013 01:15:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1216269qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1291102qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Jul 2013 01:15:30 -0700 (PDT) In-Reply-To: <663826fe-8b98-4efe-ae46-9de20dc42bf7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <663826fe-8b98-4efe-ae46-9de20dc42bf7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51d4d11b-a42f-460d-be5c-a397b210601b@googlegroups.com> Subject: Re: Can anyone help me to design a n bit input and n bit output shift register From: goouse99@gmail.com Injection-Date: Fri, 12 Jul 2013 08:15:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 50 Xref: news.eternal-september.org comp.lang.vhdl:6771 Am Donnerstag, 11. Juli 2013 18:36:21 UTC+2 schrieb lokesh kumar: > Hi, > > > > I need a help to understand how the shift register works. > > > > Suppose A and B are the 5-bit numbers. > > > > A= 10101 > > B=11001 > > 1. B(i) = 1 is the MSB 1st bit of B input > > 2. B(i) = 1 is the MSB 2nd bit of B input > > 3. B(i) = 0 is the MSB 3rdst bit of B input > > 4. B(i) = 0 is the MSB 4thd bit of B input > > 5. B(i) = 1 is the MSB 5thbit of B input > > > > Basically the 1st MSB of B is multiplied with the 5-bit number A first. Then the 2nd MSB of B is multiplied with A and so on. > > > > So I want to know how can I insert the values of B in this case. Can anyone please help me out with the VHDL code? > > > > Many thanks! Hi lokesh, you are asking the wrong question. Your real question is : How does binary multiplikation work. Answer, Just the same as decimal multiplication, only that you have just to deal with '0' and '1' which make things simpler. Remember how you learned to do multiplication in elementary school using pen and paper? Now do the same with binary numbers and you will see what the shifting means and why you have forgotten to mention the adding of the shifted values. ;-) Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.66.70 with SMTP id m6mr13559557qai.6.1373645432990; Fri, 12 Jul 2013 09:10:32 -0700 (PDT) X-Received: by 10.49.39.9 with SMTP id l9mr1355308qek.3.1373645432936; Fri, 12 Jul 2013 09:10:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!xmission!news.glorb.com!t19no1255540qam.0!news-out.google.com!f7ni2066qai.0!nntp.google.com!t19no1335123qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Jul 2013 09:10:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.75.38.36; posting-account=hlMTUgoAAAAYQF-fMMTIOH4AXuHgGDg3 NNTP-Posting-Host: 206.75.38.36 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <14f01f7e-7eb5-4477-aa87-09dee18dfd44@googlegroups.com> Subject: Digital Logic Programmable Device Good Introductory Text with a FREE DOWNLOAD ! From: ken mckee Injection-Date: Fri, 12 Jul 2013 16:10:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6772 For those who may know someone just starting out learning digital logic from a programmable device perspective there is a free download of a good introductory text: Programmable Logic Essentials: Combinational Logic at: http://www.gettothepoint.ca/download-combinational.aspx This is the complete book in pdf form for individual use only, that uses Altera's Quartus II and the DE-2 kit. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: structured VHDL Date: Sat, 13 Jul 2013 01:47:48 +0200 Lines: 158 Message-ID: References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> <5764a63f-7b15-4c15-beee-cf83ceb110c4@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net GSE+xYtd3e3BcCIR7S5u7w8b6oqCPmy/mA1tl90UFDjwziK2/Z Cancel-Lock: sha1:YsZEEa1hsZ6E9ewoZPB4KArFcW0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <5764a63f-7b15-4c15-beee-cf83ceb110c4@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6773 On 11/07/2013 19:43, Andy wrote: [] > Especially when signals are used to trigger combinatorial processes, > there is much more overhead than variables, and even moreso if the > signal is assigned with a delay. I would expect decent simulators to > significantly optimize the overhead on a signal for which there are > no delays or sensitive processes. But there is still the overhead of > separate execution (computing the value to be assigned) and update > (upon process suspension) for signals even within a single process. > Variables lack this duality and its associated overhead. In my > experience, using integers where possible for numeric quantities > (counters, etc.) yields a far more significant simulation performance > improvement than variables vs signals. That is quite an interesting point, I did not know that the signal overhead could be optimized so much, I just knew signals had overhead w.r.t. variables and therefore assumed they required more CPU to simulate. Why instead integers do show such a performance difference? [] > > On the rare occasion that I need a combinatorial in-out path through > an entity, I would prefer that to be the only situation where I use a > combinatorial process (this tends to make such a practice stand out > in the code, which it should.) Common combinatorial logic feeding > multiple sequential processes can better be expressed by a function > or procedure invoked in each process, IMHO. Synthesis is plenty smart > enough to figure out if only one copy of the logic is really needed. I should be starting using subprograms far more than I do. > > I think maybe you do not understand the effects of the new "all" > keyword in a sensitivity list. It does NOT indicate that the process > is sensitive to all signals visible by the process. "All" indicates > that the process is sensitive to any signal read by the process. > Therefore, it has zero simulation performance impact on a > combinatorial RTL process. You are right, I did not know that. Nevertheless let me say that I value the sensitivity list because I can spot immediately what the process depends on without the need to go through it. On top of it when I write a process and I believe it should depend on something, then it *must* go in the sensitivity list, otherwise I take it as a hint that my mental model is so fragile that I cannot retain it until the 'end process;'. > > > By embedding the combinatorial process functionality in the clocked > process, the level of control nesting is increased by one > if-statement (or two if asynchronous reset is used). If one really > wants to avoid that increase, then follow Treseler's model and > include the combinatorial functionality in a procedure. However, the > root of the limitation on levels of control is based on testability. > Declaring and using a separate procedure does not improve testabiliy > unless the procedure is externally accessible (e.g. in a package)for > separate testing. However, a procedure declared in a package no > longer has implicit access to signals visible by the process in which > it was originally declared. Such signals would have to be passed > through the procedure call explicitly, preferably through records. In > practice, the reset and clock controls are so ubiquitous in RTL that > it is pointless to consider their impact on testability. I think I lost you here. Why are you saying that using a procedure does not improve testability unless the procedure is externally accessible? I assume the result of the procedure is readily accessible to the process and therefore can be tested (at least as a black box). What does make the procedure more testable if it lays in a package? > > As for texts and examples on subprograms in RTL, I do not know of any > extensive references. For synthesizable RTL, subprograms are > prohibited from consuming time/delta cycles (e.g. no wait statements > within the subprogram.) Functions cannot contain wait statements > anyway. This effectively limits subprograms to describing > combinatorial logic only. However, this allows replacing the second, > combinatorial process in the authors' style with an equivalent > procedure that can be called from the concurrent process. Thus one > can have their cake and eat it too: one clocked process, but with > explicit separation of register and combinatorial logic descriptions > which some seem to prefer. Uhm, in Treseler's uart example (http://myplace.frontier.com/~miketreseler/uart.vhd) if you look at the procedure called 'retime' it seems to me the logic described is sequential and not combinatorial. Am I missing your point? Why subprograms are limited to describe combinatorial logic? > > I prefer an RTL style that emphasizes clock cycles of latency, and > let the synthesis tool determine where registers must be inserted to > accomplish said latency. If one uses retiming/pipelining > optimizations during synthesis, the input-output latency is the only > aspect retained by the implementation anyway. This style uses > variables to describe function and latency by controlling the order > of reading and writing a variable during the same clock cycle. Like > Treseler, signals are only used for inter-process communication. Ian Lang calls it 'the rule of inference': > Within a block of clocked logic, if a variable (VHDL), signal (VHDL) > or reg (Verilog) is used before it is assigned, then it will > synthesise to a flip-flop. Conversely, if it is assigned before it is > used, then it will be optimised away by the synthesiser. I did not know that even a non-blocking assignment had this feature. I assume that 'a block of clocked logic' is an: if rising_edge(clk) then ... end if; but then what about the asynchronous reset part? The signal *is* assigned before it's used with a non-blocking assignment, should it be optimized away??? > > A few tips on RTL subprograms. > > Concurrent procedure calls are allowed, but are easily confused with > component instantiations (for a purely combinatorial component, which > I rarely if ever use). I avoid concurrent procedure calls in RTL > altogether. If used concurrently, procedures must use constant and/or > signal class interfaces. > > On the other hand, do not use signal class interfaces on procedures > called in processes, use variable or constant classes instead. The > delayed update semantics of signals in processes becomes even more > confusing when procedures are involved. Does the procedure need to wait for the signal to be updated to execute or it will execute with the not yet updated value of the signal? I would expect the procedure to execute immediately. What else could happen? > > When a subprogram is declared in a process, it has visibility to > anything visible by the process. It also has visibility to any > variables, types or subprograms declared before it in the process > declarative region (before the begin statement). > > When declared outside a process, a procedure cannot drive any signal > not explicitly passed to it. This is why I'm following the code example from Jannick Bergeron (Writing Testbenches) to design a test harness. If I want to encapsulate procedures in a package to allow reuse than I have no choice other than pass to it all the interface signals. Another option would be to make the signals globally visible, but I fell once in the trap and will never do it again! :-) > > Hope this helps, > A lot, thanks. Al From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: structured VHDL Date: Sat, 13 Jul 2013 01:47:55 +0200 Lines: 341 Message-ID: References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> <3c79d346-5726-4628-97a9-2e80c4c06f68@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net vmTZ7QVL7BXa+/OXaEbuNgqwhJaFqn9lDuQnoh7alxwieqZIJW Cancel-Lock: sha1:SwfshGgec8cApsfZT3rGoU+Vqqo= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <3c79d346-5726-4628-97a9-2e80c4c06f68@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6774 On 12/07/2013 04:53, KJ wrote: [] >>> - Ian states the obvious...that there is combinatorial logic and >>> registers >> >> >> true. But the separation might be at the gate level or higher and >> this is where Ian style makes a difference > > What difference do you think it makes? The 'style' it is written in > will make no difference. Synthesis will take the description and > turn it into logic that is implemented in 'gates' (or connections to > LUT) as well as flip flops (or memory). The tools really do not need > any help from the user in figuring out which is which. Certainly the tool is smart enough to figure that out, but writing code at a higher level does pay off. Higher level of abstraction has the purpose to describe the problem in a clearer way (I'm thinking of 'literate programming') for other people to read and maintain. The methods reported by the authors of ET4351, as well as Mike's and Ian's examples, have all one intent IMO, reduce the number of concurrent statements which need to interact. This intent is beneficial since it foster separation between blocks, reducing the amount of signals my head has to keep track of when I try to write/read/debug some code. >> If you think about 'structured programming' as in a paradigm where >> every computable function can be expressed as a combination of only >> three control structures, then Ian proposal pretty much follows the >> same line. Whether is overplayed or not I do not know. >> > > That does not imply that the 'best' way to describe the code is in > that form. Agreed, in the end 'best' is what fits the needs case by case and here's where the designer's experience matter. > The soft metrics for 'best' here should be maintainability. On the > assumption that one can write code that meets the function and > performance requirements in many different ways, then one looks > towards source code maintainability which would be the ability for > somebody (not necessarily the original designer) to get up to speed > on the design. Clumping all of the unrelated code physically > together because it describes the transfer function is rather > pointless. Clumping parts of code together that are inter-related > makes sense. I cannot agree more, both on the maintainability and the clumping. But having the 'best' subdivision between functional blocks in a design is another aspect that sits on top of the style you use. If your design doesn't have any partition it can easily turn into a mess, if your design is fragmented in micro blocks it does not make sense either. Grouping together signals into records which do make sense is certainly beneficial and still does not prevent the usage of the proposed approach. > >> >>> - The paper takes non-issues and presents 'solutions' and ignores >>> actual issues as well as the new issues that get created by the >>> proposed 'solution' >> >> >> Could you be more specific on what kind of 'non-issues' and 'actual >> issues' you are referring to? Since I consider the talk rather to >> the point I may have missed/misunderstood an essential part of it. >> >> > > I'll just nitpick on a few points in no particular priority, just the > order that they are in the presentation. I'll nitpick along... > - Other than the last bullet about auto-generated code, nothing on > the slide titled 'Traditional VHDL design methodology' is worth the > time it took to type. It's all wrong. Maybe some people have done > he says here but that doesn't make it 'Traditional'. I am certainly not in the position to say that I've seen *a lot* of code in my life, but certainly most of the time I've seen code it was pretty close to the description they provided (otherwise I wouldn't have needed to start this thread in the first place). Does this qualify it as 'traditional'? Maybe not, but it does not qualify it neither wrong. [] > - The next slide 'Traditional ad-hoc design style' is similarly > biased and worthless. Taking the statement 'No unified signal naming > convention' as one example. The upcoming 'unified' naming convention > will not add anything useful (more later). I find meaningless their proposed 'unified' naming convention, but I must say that too often I've seen a stunning negligence in the choice of names. IMO names should convey their purpose/function, rather than type and or direction. I remember we had once two sets of tx/rx cables going in and out a series of avionics boxes and people were convinced that labeling tx_out/rx_in on one end and tx_in/rx_out on the other would have been sufficient...we spent few hours before finding the right combination (ouch!). > The statement 'Coding is done at low RTL level' is laughable. Again > some may code this way, but let's not make elevate those people to be > considered the traditionalists. is laughable because 'level' is already part of the RTL acronym :-) My first supervisor used to design logic with a schematic entry tool, with gates and flops. I was asked to learn vhdl though, so I did learn the syntax (or part of it - at least), but the mindset when designing was still with gates and flops. Most of the people I know are still not far from there... I am slowly departing from that paradigm. > - Slide 'Unified signal naming example'. Only the convention for > 'types' has any value and that is because use of the type name can > frequently be used throughout the code and it can be of value > sometimes to easily differentiate that xyz is a data type. Indeed I ignored this slide entirely and only retained the suggestion to name a type as such (which is what I normally do in C). Since these guys are strongly linked to ESA, with a lot of bureaucratic non-sense written down on piles of documents, I guess this is a some sort of remnant of their complex yet proficuous partnership. [] > - Slide 'The abstracted view in VHDL : the two-process scheme' and successors describing the > method does not justify how productivity would increase with any of the schemes. Examples: > * The collection of signals and/or ports into records groups together things that are logically > completely unrelated other than by the fact that they are pieces of an entity/architecture. Couldn't agree more. > As an example, consider an entity that receives input data, processes it, and then outputs > the data. Further the input data interface has some implementation protocol, the output > has a different protocol, both protocols imposed by external forces (i.e. you can't change > them, maybe they are external device I/O). The natural collection from my perspective is > input interface signals, output interface signals and processing algorithm signals. The > input and output interfaces likely have nothing at all to do with each other...so why should > they be collected into a record together as if they are? nobody prevents you to combine the input/output/processing signals in three separate records, you would still benefit of the fact that adding a signal to a record definition does not have an impact on propagating the change throughout all the component/instantiation/entity definitions. > Think about it. The input > interface likely has some state machine, the output interface has another, the processing > algorithm possibly a third. Do you think those three state machines should be all lumped > together? No? Then what benefit is it to lump them into a record together? (Hint: None) but you could still have a three 'two-processes' or one-process exchanging the necessary information via signals. The interface separation you have at the entity level (with three different records) is kept throughout the architecture. I understand that what I'm saying *is not* what they are saying, but I can equally ask why should the three functions sit in the same entity? After all if they are only passing data through a well defined interface, they could equally sit on separate entities and keep a one record per interface. > - Slide 'Benefits'...every single supposed benefit except for 'Sequential coding is well known and > understood' is wrong. How is the 'algorithm' easily extractable as stated? Take the example > I mentioned earlier. There are at least three 'algorithms' going on: input protocol, output > protocol and processing algorithm...and yet the proposed method will lump these together into > one supposed 'algorithm'. What is stated by the author as an 'algorithm' is not really an > algorithm, all it is is the combinatorial logic... That is certainly one of the reasons why I would either break your example in smaller entities, or have three processes running concurrently and passing data to each other. > - The other supposed benefits are merely unsubstantiated beliefs...I'll leave it to you to show > in concrete terms how any of them are either generally true. Be specific. 'Uniform coding style simplify maintenance': the fact that you have a pattern in each entity of your code (see Mike's template) let's you read and maintain only the part where stuff happens, relying on the template to do its job together with the synthesis tool. Knowing 'a priori' that somebody else's code is following a logical separation as the one proposed does shorten the time I need to spend to understand how pieces are glued together. In your example I assume that data received from the input are 'passed' to the algorithm which 'passes' them eventually to the output. The three functions are concurrent and they need some sort of 'handshake' to pass the data around, maybe a couple of fifos to be monitored for 'full/empty' conditions... how many things should I know about this code while I read it? Where should this description go? With Mike's template something similar can be quite self explaining: procedure update_regs is begin receive_data; process_data; transmit_data; -- too bad receive/transmit have different word length! end procedure update_regs; A simple glance at this part already tells me a lot about what the code is doing, without the need to read through often not up to date comments scattered around. > - Adding a port: While I do agree that the method does make it easier to add and subtract I/O, > I'll counter with if you'd put more thought into using a consistent interface protocol in > the first place (example: Avalon or Wishbone) you wouldn't find yourself adding and subtracting > ports in the first place because you'd get it right (or very nearly right) the first time. So > this becomes a benefit of small value over a superior method that mostly avoids the issue. I do wish more of my colleagues understood the benefits coming from a standard interface, but unfortunately I've seen many wheels reinvented from scratch (and only few of them spinning as they should!). I would only add that adding/removing I/O from an entity takes a matter of a couple of key strokes with emacs, so I never found this to be a real problem. [] > - Slide 'Stepping through code during debugging'. This is generally the last thing one needs to > do unless you make heavy use of variables in which case you're stuck and forced to single step. AFAIK if variables are used in processes than you can still use 'add wave' with the process label and * for everything in the process, but if they are used in subprograms then it's needed to single step, since they are popped off the stack when the procedure exits. I try to design my logic such that is observable and controllable (which I normally lose the moment I 'transfer' the firmware on some piece of silicon). I try to keep functional blocks as separate as possible and with clear interfaces (often going through the entity boundaries), that I end up tracing. [] > - Slide 'Increasing the abstraction level' is a misnomer. The method described does not increase > abstraction, it simply collects unrelated signals into a tidy (but more difficult to use) bucket. How would you increase the level of abstraction instead? Any pointer to available code would be really useful. [] >>> The first two are laughably wrong, Mike is all about synthesizable >>> code and the supposed 'wrong gate-level structure' is claptrap. The >>> last point again relates back to the skill of the designer. However, >>> assuming equally skilled designers, the supposed 'structured' >>> approach given in the article is even more likely to have 'Problems >>> to understand the algorithm for less skilled engineers'. >> >> >> I may have misunderstood completely the talk but I do not read the >> 'increasing the abstraction level' slide as a critique to Mike's style >> w.r.t. their style. >> > > It sounds better to say 'higher abstration level' than 'collecting unrelated signals' > doesn't it? I must say that it does sound better! Jokes apart, I believe that style does play a big role in coding and any attempt to propose some is worth the effort. If, as you say, it does not help in increasing the level of abstraction, it does help to have the 'bucket tidy' instead of messy. [] >> The first bullet qualifies the two-process approach as uniform and I >> believe rightly since all entities look the same and a designer only >> needs to look at the combinatorial process to understand the algorithm. >> > > Only if you're implementing embarassingly simple entities I suppose. For anything > real, you're making things worse (refer to my simple example stated earlier of a > generic processing module). Mike's example is not so complex, but not so 'embarrassingly simple' either I suppose. > >> Looking at their LEON vs ERC32 example, it seems the method claims less >> resources than an ad-hoc one, therefore improving development time. >> > > The most likely reason is more skilled designers rather than style...prove me wrong. I cannot certainly prove you wrong, I can only say that both are 32bit RISC processors based on SPARC architecture. Temic (now Atmel) developed the ERC2 and ESTEC (part of ESA) the first versions of the LEON. A research center versus an established microcontroller manufacturer... I guess both had quite skilled designers (but this is not more than a guess). [] >> I certainly believe that a readable code is easier to maintain, but I >> may doubt that this approach does increase the re-usability of the code, >> at least I consider this last point not more than the author's personal >> opinion. >> > > A designer's goal is to implement a specific function and meet a specific level of > performance. A method that makes traceability of the function specification to the > source code easier is 'good'. The seperation of that description into a collection of > all combinatorial logic needed to implement the function and a seperate clocked process > does absolutely nothing to define tracability back to the specification. The specification > will most likely have no mention of combinatorial or storage, that is an implementation > decision. Therefore the proposed seperation does not aid tracability and in fact makes > it harder to follow. The separation is still left to the designer to make, sectioning the code in structural elements (entity, function, procedure, package), providing the traceability you referred to. If your entity is cluttered with small processes, which share signals all together, the traceability issue is not solved either. [] >> Here I need to urge you to go through the presentation again since I >> believe, with all due respect, you missed the point. IMO they are *not* >> proposing their two-processes approach vs Mike's one process approach. >> They actually use Mike's example to show how increasing the level of >> abstraction is a good thing. >> > > Nope. Calling it a 'higher level abstraction' doesn't make it so. You've > simply collected together unrelated signals into various records. Records are > a good thing, collecting unrelated things into a record...not so good thing. Would you qualify Mike's template as a hardware description at higher level of abstraction? if yes than I do not see where's the *big* difference w.r.t. Ian's example or the presentation examples. If not than I should ask you again to point me to some code example that you consider written at a higher level of abstraction, because there is where I aim to go. [] > And you of course are entitled to your opinion as well and I mean that with > absolutely no disrespect or sarcasm or anything else negative. I'm enjoying the ride. Al From newsfish@newsfish Tue Dec 29 16:43:01 2015 X-Received: by 10.224.37.3 with SMTP id v3mr44553654qad.2.1373702841785; Sat, 13 Jul 2013 01:07:21 -0700 (PDT) X-Received: by 10.50.126.67 with SMTP id mw3mr388180igb.15.1373702841578; Sat, 13 Jul 2013 01:07:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!t19no1353219qam.0!news-out.google.com!f7ni2314qai.0!nntp.google.com!t19no1440356qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Jul 2013 01:07:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.172.158.8; posting-account=zYWVCAoAAADYmtulAFLuKo_Ql31UzI-e NNTP-Posting-Host: 122.172.158.8 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5bf7ac08-e879-440b-af22-77c1c2d9664c@googlegroups.com> Subject: Re: Doubts on processes using a single clock. From: mindentropy@gmail.com Injection-Date: Sat, 13 Jul 2013 08:07:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6775 On Friday, July 12, 2013 1:34:34 PM UTC+5:30, goou...@gmail.com wrote: > Am Freitag, 12. Juli 2013 06:42:41 UTC+2 schrieb minde...@gmail.com: > > > Hi, > > > > > > I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture. > > > > > > > > > > > > The code is as follows: > > > > > > > > > > > > sectimer: process(clk) is > > > > > > begin: > > > > > > if(rising_edge(clk)) then > > > > > > if(div = someval) > > > > > > increment counter; > > > > > > end if; > > > > > > end process; > > > > > > > > > > > > seven_seg_proc: process(clk) is > > > > > > begin: > > > > > > if(rising_edge(clk)) then > > > > > > > > > > > > end if; > > > > > > end process; > > > > > > > > > > > > The problem is the counter does not seem to increment fine. If I decrease the > > > > > > divider the counter does not increment faster. Can I have 2 processes driving the clock? > > > > Hi, > > there's nothing wrong with having a number of processes using the same clock. > > But from the code snippet I found some strane thing: > > How do you set back the counter? > > Where does div come from? I there another process involved? > > How many clock cycles does div hold its value constant? > > > > If you have a proces that acts as a clock divider you should do the comparing there and generate a ClockEnable signal. > > > > clk_div: process(clk) is > > variable: div = natural range 0 to divmax+1 ; > > begin: > > if(rising_edge(clk)) then > > div:= div+1; > > ClockEnable <= '0'; > > if(div = divmax) then > > div:= 0; > > ClockEnable <= '1'; > > end if; > > end if; > > end process; > > > > > > sectimer: process(clk) is > > begin: > > if(rising_edge(clk)) then > > if(ClockEnable = '1') then > > --increment counter; > > end if; > > end process; > > > > This also saves you from having big comparators in every process which may reduce Fmax of the design. > > > > Have a nice synthesis > > Eilert Eilert, The design is here http://code.google.com/p/basys2-experiments/source/browse/seven_seg_disp/seven_seg_disp.vhd Its a simple second and minute counter. Its just my experiments with the board. So it might not be very efficient. I would like some comments if there are any mistakes and how to improve. Thanks. From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Doubts on processes using a single clock. Date: Sun, 14 Jul 2013 10:56:15 -0400 Organization: A noiseless patient Spider Lines: 171 Message-ID: References: <5bf7ac08-e879-440b-af22-77c1c2d9664c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 14 Jul 2013 14:50:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="741"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+eE7/9E5GGco+/F4eihPVF" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <5bf7ac08-e879-440b-af22-77c1c2d9664c@googlegroups.com> Cancel-Lock: sha1:d4MD+ASBCYz+2aj08nNUxG5CppY= Xref: news.eternal-september.org comp.lang.vhdl:6776 On 7/13/2013 4:07 AM, mindentropy@gmail.com wrote: > On Friday, July 12, 2013 1:34:34 PM UTC+5:30, goou...@gmail.com wrote: >> Am Freitag, 12. Juli 2013 06:42:41 UTC+2 schrieb minde...@gmail.com: >> >>> Hi, >> >>> >> >>> I am using a basys2 board and want to display a counter on 4 seven segment LED's. I have 2 processes one which is a counter and the other process the display logic in the same architecture. >> >>> The code is as follows: >> >>> sectimer: process(clk) is >>> begin: >>> if(rising_edge(clk)) then >>> if(div = someval) >>> increment counter; >>> end if; >>> end process; >> >>> seven_seg_proc: process(clk) is >>> begin: >>> if(rising_edge(clk)) then >>> >>> end if; >>> end process; >> >>> The problem is the counter does not seem to increment fine. If I decrease the >>> divider the counter does not increment faster. Can I have 2 processes driving the clock? >> >> Hi, >> there's nothing wrong with having a number of processes using the same clock. >> But from the code snippet I found some strane thing: >> How do you set back the counter? >> Where does div come from? I there another process involved? >> How many clock cycles does div hold its value constant? >> >> >> >> If you have a proces that acts as a clock divider you should do the comparing there and generate a ClockEnable signal. >> >> >> >> clk_div: process(clk) is >> >> variable: div = natural range 0 to divmax+1 ; >> >> begin: >> >> if(rising_edge(clk)) then >> >> div:= div+1; >> >> ClockEnable<= '0'; >> >> if(div = divmax) then >> >> div:= 0; >> >> ClockEnable<= '1'; >> >> end if; >> >> end if; >> >> end process; >> >> >> >> >> >> sectimer: process(clk) is >> >> begin: >> >> if(rising_edge(clk)) then >> >> if(ClockEnable = '1') then >> >> --increment counter; >> >> end if; >> >> end process; >> >> >> >> This also saves you from having big comparators in every process which may reduce Fmax of the design. >> >> >> >> Have a nice synthesis >> >> Eilert > > Eilert, > > The design is here http://code.google.com/p/basys2-experiments/source/browse/seven_seg_disp/seven_seg_disp.vhd > Its a simple second and minute counter. Its just my experiments with the board. So it might not be very efficient. I would like some comments if there are any mistakes and how to improve. > > Thanks. I don't see any obvious problems with your code. There are a few things I would change. In the seven segment process you assign dp a value outside of the clock if statement. Technically that may work fine, but it will differ in simulation from assigning a value in a concurrent statement an so your intent is not obvious. I would move it outside of the clocked process using a concurrent assignment. One of the things I learned in software design is in an IF structure, to put the smaller of the two clauses as the THEN and the larger as the ELSE. This makes it easier to associate each clause with it's IF condition. So here is how I would code the clock counters. sectimer: process(clk) is variable secdiv:secrange; begin if(rising_edge(clk)) then if(switches(0) = '1') then secdiv := 0; digit0 <= 0; digit1 <= 0; digit2 <= 0; digit3 <= 0; else if(secdiv /= 50000000) then secdiv := secdiv + 1; else secdiv := 0; if(digit0 /= 9) then digit0 <= digit0 + 1; else digit0 <= 0; if(digit1 = 5) then digit1 <= digit1 + 1; else digit1 <= 0; if(digit2 = 9) then digit2 <= digit2 + 1; else digit2 <= 0; if(digit3 = 5) then digit3 <= 0; else digit3 <= digit3 + 1; end if; end if; end if; end if; end if; end if; end if; end process; Same thing in the seven segment process. The else div := div + 1; is very far from the if(div=62500). Make it if(div/=62500) and the both clauses are easier to associate with the if condition. Finally process(clk,switches(0),switches(1)) really should be process(clk). The switch inputs are within the clock IF structure and so do not need to be in the sensitivity list. In fact, switches(1) is not used anywhere in the design. These are all small issues and will not prevent the code from simulating or synthesizing. -- Rick From newsfish@newsfish Tue Dec 29 16:43:01 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Doubts on processes using a single clock. Date: Sun, 14 Jul 2013 12:14:53 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <5bf7ac08-e879-440b-af22-77c1c2d9664c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 14 Jul 2013 16:09:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="25317"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/s/W2PaTYIDa8Q363pKC8h" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <5bf7ac08-e879-440b-af22-77c1c2d9664c@googlegroups.com> Cancel-Lock: sha1:9dSJYPnc18IVBiQX+a5t1mYaYdA= Xref: news.eternal-september.org comp.lang.vhdl:6777 On 7/13/2013 4:07 AM, mindentropy@gmail.com wrote: > > Eilert, > > The design is here http://code.google.com/p/basys2-experiments/source/browse/seven_seg_disp/seven_seg_disp.vhd > Its a simple second and minute counter. Its just my experiments with the board. So it might not be very efficient. I would like some comments if there are any mistakes and how to improve. > > Thanks. BTW, the seven segment process could be a combinatorial process. I don't think there is any reason why you need to register the decoder outputs. You don't even need the div and two bit anode counters. You can pick off a couple of bits from the secdiv counter to drive the segment mux. If you want to use a separate anode counter I would suggest that you make it a one-hot ring counter (one-cold in your case) which can be used to directly drive the anodes. That would save you a bit of logic. -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Simulating a bidirectional bus delay Date: Mon, 15 Jul 2013 16:52:50 +0100 Organization: A noiseless patient Spider Lines: 17 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 15 Jul 2013 15:46:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="07c5f96a9d179a2474c6de6e78e0c3e1"; logging-data="2762"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+DCwrKJOuwNUFWrFXVmdVd" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 Cancel-Lock: sha1:yncgE3G7BA8K/Y/sYtoRfS5ondY= Xref: news.eternal-september.org comp.lang.vhdl:6778 I've come to realise that VHDL is not sympathetic to bidirectional bus delays! I'm not au fait with Verilog though understand simulating this delay is less fraught in Verilog. I thought I would use Bidi_Dly.vhd that can be found at: http://tams-www.informatik.uni-hamburg.de/vhdl/index.php?content=06-models However it creates a Hi-Z region around the point of switching that causes annoying errors in a Micron DDR2 model. I've tried other means but they all seem to fall down when any signal goes to 'X'!! Can anyone help? From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.29.76 with SMTP id p12mr64965350qac.5.1373914758189; Mon, 15 Jul 2013 11:59:18 -0700 (PDT) X-Received: by 10.49.62.3 with SMTP id u3mr1714703qer.26.1373914758128; Mon, 15 Jul 2013 11:59:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t19no1611920qam.0!news-out.google.com!dk8ni0qab.0!nntp.google.com!t19no1716506qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jul 2013 11:59:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8781a259-e640-4083-aa2a-c6e8c4c8e66b@googlegroups.com> Subject: Re: Simulating a bidirectional bus delay From: KJ Injection-Date: Mon, 15 Jul 2013 18:59:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2505 Xref: news.eternal-september.org comp.lang.vhdl:6779 On Monday, July 15, 2013 11:52:50 AM UTC-4, Fredxx wrote: > I've come to realise that VHDL is not sympathetic to bidirectional bus > delays! > > I'm not au fait with Verilog though understand simulating this delay is > less fraught in Verilog. > Just curious, how are things any better in Verilog? > I thought I would use Bidi_Dly.vhd that can be found at: > > http://tams-www.informatik.uni-hamburg.de/vhdl/index.php?content=06-models > > However it creates a Hi-Z region around the point of switching that > causes annoying errors in a Micron DDR2 model. > Are you only using the bi-directional model on the true bi-directional signals and not, for example, clock? What exactly is the 'annoying error' that the Micron model is generating? Are you sure it's not a valid error message (like data changing during a write). > I've tried other means but they all seem to fall down when any signal > goes to 'X'!! You need to supply more information in order to get some help... 1. What 'other means' have you tried and in what way did they 'fall down'? 2. Did the Bidi_Dly.vhd model 'fall down'? If so, in what way? 3. I haven't used Bidi_Dly.vhd myself, I have my own home grown (not really at liberty to share) and didn't have any particular problems when using it with a Micron memory model. 4. Exactly what are you trying to model with Bidi_Dly.vhd and why? Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: Simulating a bidirectional bus delay Date: Tue, 16 Jul 2013 11:22:03 +0100 Organization: A noiseless patient Spider Lines: 78 Message-ID: References: <8781a259-e640-4083-aa2a-c6e8c4c8e66b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Jul 2013 10:16:03 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="07c5f96a9d179a2474c6de6e78e0c3e1"; logging-data="3179"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1811YBNhfX6oeoVZ3H7/+ZR" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <8781a259-e640-4083-aa2a-c6e8c4c8e66b@googlegroups.com> Cancel-Lock: sha1:NC5gfLa8BUOnWna/lTJvjevCyhk= Xref: news.eternal-september.org comp.lang.vhdl:6780 On 15/07/2013 19:59, KJ wrote: > On Monday, July 15, 2013 11:52:50 AM UTC-4, Fredxx wrote: >> I've come to realise that VHDL is not sympathetic to bidirectional bus >> delays! >> >> I'm not au fait with Verilog though understand simulating this delay is >> less fraught in Verilog. >> > > Just curious, how are things any better in Verilog? > >> I thought I would use Bidi_Dly.vhd that can be found at: >> >> http://tams-www.informatik.uni-hamburg.de/vhdl/index.php?content=06-models >> >> However it creates a Hi-Z region around the point of switching that >> causes annoying errors in a Micron DDR2 model. >> > > Are you only using the bi-directional model on the true bi-directional signals > and not, for example, clock? What exactly is the 'annoying error' that the > Micron model is generating? Are you sure it's not a valid error message (like > data changing during a write). > > >> I've tried other means but they all seem to fall down when any signal >> goes to 'X'!! > > You need to supply more information in order to get some help... > > 1. What 'other means' have you tried and in what way did they 'fall down'? > 2. Did the Bidi_Dly.vhd model 'fall down'? If so, in what way? > > 3. I haven't used Bidi_Dly.vhd myself, I have my own home grown (not really at liberty > to share) and didn't have any particular problems when using it with a Micron memory > model. > > 4. Exactly what are you trying to model with Bidi_Dly.vhd and why? > I have only used Bidi_Dly.vhd on bidirectional signals. Another model I used was based on: process (a) if (not(b = a) then b <= a after delay; end if; end process; process (b) if (not(a = b) then a <= b after delay; end if; end process; The issue as soon as one signal goes to X for any reason both become stuck at X. I'm tying to reconcile differences between a Post-Place and Route simulation model and real life, and hoping they might converge if add the small PCB and IO delays to the models. The DDR2 model I use is: * File Name: ddr2.v * Version: 5.83 * Model: BUS Functional * * Dependencies: ddr2_parameters.vh * * Description: Micron SDRAM DDR2 (Double Data Rate 2) It produces warnings: "Invalid latching edge on DQS_N bit" from having the DQS lines being tr-stated for 1.0ps during a transition, introduced by the Bidi_Dly.vhd. Many thanks for your insight. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Tue, 16 Jul 2013 15:47:49 +0300 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Jul 2013 12:41:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="14981"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+sibzsn+6VtNBo8aeBzGf6NvkSsAJPUMw=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Cancel-Lock: sha1:DVisDjZc5CdbRHBpp0AtmsCtpOU= Xref: news.eternal-september.org comp.lang.vhdl:6781 wait until clk = '1'; requires less typing than if clk = '1' then end if; and, furthremore, causes less confusion than the conditional. I wonder why people keep reproducing this awkward IF pattern instead of wait until. Single wait until synthesizes well, even in xilinx tools now. I've checked that may times. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Tue, 16 Jul 2013 12:02:24 -0400 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Jul 2013 15:56:56 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="14292"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18EkbU3t7437Ftr28R8tSBj" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:4FJigrbpV17GOIUE/5Be6xDSIlY= Xref: news.eternal-september.org comp.lang.vhdl:6782 On 7/16/2013 8:47 AM, valtih1978 wrote: > > wait until clk = '1'; > > requires less typing than > > if clk = '1' then > end if; > > and, furthremore, causes less confusion than the conditional. I wonder > why people keep reproducing this awkward IF pattern instead of wait > until. Single wait until synthesizes well, even in xilinx tools now. > I've checked that may times. What is the related code for an async resettable FF? -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.164.194 with SMTP id f2mr4370354qay.3.1373994380577; Tue, 16 Jul 2013 10:06:20 -0700 (PDT) X-Received: by 10.182.129.84 with SMTP id nu20mr55530obb.40.1373994380430; Tue, 16 Jul 2013 10:06:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1725742qam.0!news-out.google.com!ij2ni362qab.0!nntp.google.com!t19no1843456qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jul 2013 10:06:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <7cf83d04-3d09-4b8b-ab12-286caf69e4e6@googlegroups.com> <5764a63f-7b15-4c15-beee-cf83ceb110c4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: structured VHDL From: Andy Injection-Date: Tue, 16 Jul 2013 17:06:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 131 Xref: news.eternal-september.org comp.lang.vhdl:6783 On Friday, July 12, 2013 6:47:48 PM UTC-5, alb wrote: > Why instead integers do show such a performance difference?=20 SLV/unsigned/signed, etc. are arrays of enumerated values (for each bit). E= ven if the enumerated value is represented as a byte, each bit is then a by= te in memory, and the CPU's built-in arithmetic instructions cannot be used= on the vector directly. The best bet for the simulator (rather than the bo= olean implementations in the reference package bodies) is to convert it to = integer(s) where the integer(s) represent(s) the numerical value (assuming = there are no meta-values in the vector), and then use the CPU's arithmetic = instructions on those integers. Using integers directly where possible (within the range constraints availa= ble on integers) avoids all that conversion and memory usage.=20 MANY years ago, I replaced a widely-used 5 bit unsigned address bus with an= integer in a ~20K gate FPGA design, and that alone improved RTL simulation= runtimes by ~2.5X IIRC.=20 >Nevertheless let me say that I value the sensitivity list because I can sp= ot=20 >immediately what the process depends on without the need to go through it.= =20 If you limit signals to only that information that is communicated between = processses, and use local variables for everything else, then your benefit = from the explicit sensitivity list is minimal. If only some of many process= es share a group of signals, then enclose those few processes, and declarat= ions for their exclusively shared signals, in a block statement, so that th= e signals are not only hidden from outside access, but also declared in clo= se proximity to the processes that use them. >Why are you saying that using a procedure does not improve testability unl= ess the procedure is externally accessible?=20 Testability of the architecture that uses subprograms is improved by separa= tely testing each subprogram, without the process/architecture around it, h= indering access to it. If a subprogram is declared in an architecture or in= a process, how would you call the subprogram directly from a testbench to = test it? For it to be called by some other architecture (e.g. testbench) th= e subproram must be declared in a package accessible to the testbench. I'm not trying to say that all subprograms should be declared in packages. = There are many reasons to use subprograms, and improved testability is only= one of them. Localization of data (variables) and complexity is another. I= MHO, since I'm not a big fan of unit level testing FPGA designs anyway, imp= roved unit level testability is not as big a reason for using subprograms a= s is the localization. >Uhm, in Treseler's uart example >(http://myplace.frontier.com/~miketreseler/uart.vhd) if you look at the=20 >procedure called 'retime' it seems to me the logic described is sequential= and=20 >not combinatorial. Am I missing your point?=20 In synthesis, a suprogram cannot span time, and it cannot remember local va= riables' values from one subprogram call to the next. It can control the or= der of its access/update of its interface variables, so it could be conside= red as inferring registers. However, in Treseler's example the previous val= ues of the variables are assigned in a different (in time) call to the proc= edure. Thus it is also the surrounding process that infers the registers, a= nd the procedure could be considered as simply defining the combinatorial l= ogic (wires in this case) between them.=20 On the other hand, if the order of the variable assignment statements in th= at procedure were reversed, only one register would be inferred. So in that= sense, the procedure is the one inferring at least two of the registers. G= ood point! I had not thought of that.=20 The important thing to remember about variables in clocked processes is tha= t each reference to a variable, relative to its most recent update, determi= nes whether a register is inferred for that reference. Thus a single variab= le declaration can represent, through multiple references and assignments t= o it, both a register and combinatorial values. Naturally, if multiple refe= rences to the variable return the same previously stored value, only one re= gister is inferred for all of those references. Signals can be thought of as inferring registers in the same way (if the va= lue accessed was updated in a previous clock cycle). But since signal value= updates are always postponed until the process suspends, a reference to a = signal assigned on a clock edge is necessarily the value stored in a previo= us clock cycle, thus all references to said signal are to the registered va= lue. In that sense, variables and signals both infer registers for the same reas= on, but you have more control over that inference with variables. But don't= worry; the synthesis tool will generate hardware that behaves the same way= the RTL does (on a clock cycle basis), with or without registers as requir= ed. >Does the procedure need to wait for the signal to be updated to execute or= it >will execute with the not yet updated value of the signal?=20 Since a procedure in synthesis cannot wait (span time/delta), the not-yet-u= pdated value will be used. Similar confusion also arises when a statement f= ollowing the procedure call that assigned a signal also sees the non-yet-up= dated value. Signals assigned within the procedure are not automatically up= dated when the procedure exits, only when the calling process suspends. =20 >Another option would be to make the signals globally visible, but I fell o= nce=20 >in the trap and will never do it again!=20 Don't confuse accessibility/visibility of signals with driveability of sign= als from a procedure. The only way a procedure can DRIVE signals not passed= to it explicitly is if the procedure is declared in a process, regardless = of whether it can "see" the signals. If declared in a process, the procedur= e can drive any signal that can be driven from the process, whether the sig= nal is passed to the procedure or not. There are a couple of options to consider to make testbench procedures more= easily reusable. First, you can declare a procedure, with signal interfaces, in a package, a= nd then within each process that needs to call it, you can overload it with= a declaration that omits the signal interfaces, and that procedure simply = calls the full version procedure with signals. Then you can more easily cal= l the short-hand version procedure anywhere in that process, as many times = as needed. Second, you can declare records for the signal interface, either for separa= te in and out record ports, or for a combined inout record port, but the in= out record type must either be resolved (implement a custom resolution func= tion for it), or it must contain elements of resolved types (e.g. SL/SLV/Un= signed, etc.) The record makes calling the procedure over and over much simpler. Also, don't forget; in simulation (testbenches), procedures can have wait s= tatments, and therfore can span time during their execution. Andy From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.50.66 with SMTP id y2mr6578542qaf.7.1374025021942; Tue, 16 Jul 2013 18:37:01 -0700 (PDT) X-Received: by 10.49.120.67 with SMTP id la3mr220289qeb.35.1374025021906; Tue, 16 Jul 2013 18:37:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx02.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!209.85.216.88.MISMATCH!t19no1892497qam.0!news-out.google.com!ij2ni362qab.0!nntp.google.com!t19no1892495qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jul 2013 18:37:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <8781a259-e640-4083-aa2a-c6e8c4c8e66b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simulating a bidirectional bus delay From: KJ Injection-Date: Wed, 17 Jul 2013 01:37:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: news.eternal-september.org comp.lang.vhdl:6784 On Tuesday, July 16, 2013 6:22:03 AM UTC-4, Fredxx wrote: > I have only used Bidi_Dly.vhd on bidirectional signals. Here is a link to Ben Cohen's Zero ohm resistor model. I've used this model although it too will introduce glitches when the driver changs that might be similar to what you're seeing. http://www.google.com/url?sa=t&rct=j&q=&esrc=s&frm=1&source=web&cd=1&cad=rja&ved=0CC0QFjAA&url=http%3A%2F%2Fsystemverilog.us%2Fzohm0_ea.vhd&ei=HvTlUdGbCuTeyAGI14HIDA&usg=AFQjCNGRo17-UoryYGNS0CAAJGoG-o5cHA&sig2=GvajypCFjvbrRSoZ75PhWw&bvm=bv.49405654,d.aWc And here is a link to an alternative model written by someone who tried and did not like Ben's model. I haven't tried it http://www.edaboard.co.uk/would-you-like-the-alternative-to-zero-ohm-t517714.html Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.29.76 with SMTP id p12mr7583112qac.5.1374039920800; Tue, 16 Jul 2013 22:45:20 -0700 (PDT) X-Received: by 10.49.133.201 with SMTP id pe9mr255445qeb.34.1374039920785; Tue, 16 Jul 2013 22:45:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1911461qam.0!news-out.google.com!ij2ni362qab.0!nntp.google.com!t19no1911452qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jul 2013 22:45:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: goouse99@gmail.com Injection-Date: Wed, 17 Jul 2013 05:45:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 46 Xref: news.eternal-september.org comp.lang.vhdl:6785 Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: > wait until clk = '1'; > > > > requires less typing than > > > > if clk = '1' then > > end if; > > > > and, furthremore, causes less confusion than the conditional. I wonder > > why people keep reproducing this awkward IF pattern instead of wait > > until. Single wait until synthesizes well, even in xilinx tools now. > > I've checked that may times. Hi, wait until clk = '1'; actually creates latches, which most of us are trying to avoid. What you probably mean is: wait until rising_edge(clk); And to answer rickmans question too: Yes this coding style makes it hard, if not impossible to implement a (async) reset. However, there are many applications that neither need this. There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. But of course, if one needs it, the well known if reset then elsif rising_edge(clk) does the job pretty well, and for thos who whant to save time typing code: Use EMACS with VHDL mode. Then 90% of the code is writing itself. Just make sure you have a reliable TAB button on your keyboard. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 12:58:30 +0300 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Jul 2013 09:52:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="5071"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+sqEv+n5YBIp5Hr/5eDJCTJE2SuQJjfAI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:IHFECYRPYBg5AyvCRA2BxIIki20= Xref: news.eternal-september.org comp.lang.vhdl:6786 What is the problem? Can you be more specific? Should I care using the async pattern because async reset is depricated and I never use it? Why should I care about the related code? Is it the only argument you have? From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 14:20:29 +0300 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Jul 2013 11:14:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="29209"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mSP5Nqv+KgibFT9SWfWD2X2y4CsfnRUE=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> Cancel-Lock: sha1:+jgtqlTIoTCeIzv5H4pSpYnPXVM= Xref: news.eternal-september.org comp.lang.vhdl:6787 Rising_edge(clk) is basically equivalent to process wait on clk; -- implied by sensetivity list if clk'event and clk = '1' then end if; end process; whereas wait until clk='1' is equivalent to (see VHDL spec) process loop wait on Clk; exit when Clk = '1'; end loop; end process Tell me the difference. I see waiting for the edge in both cases. Does latch mean the edge-sensitive storage? So, might be it is your rising_edge that produces the latch? Why double standards? Do you say that bad style is popular because people mistakenly think that good style produces the latches? From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 10:36:46 -0400 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Jul 2013 14:31:48 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="27126"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18VA0uILTQ4ENVgurmH0sgO" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:klgnD+Fuwhvx0j5lqTIzynyfb9s= Xref: news.eternal-september.org comp.lang.vhdl:6788 On 7/17/2013 5:58 AM, valtih1978 wrote: > What is the problem? Can you be more specific? > > Should I care using the async pattern because async reset is depricated > and I never use it? Why should I care about the related code? > > Is it the only argument you have? I'm asking how you would use this form to generate an async reset on the FF. Who exactly has "deprecated" the async reset? If you never use it, that's fine, but I design FPGAs which use an async reset. If you don't specify a reset the register value is defaults to zero in most cases. I prefer to define a reset value because it can be useful and it makes the synthesis match the simulation. I see no advantage to this form. It may be fewer keystrokes, but my design process is not limited by the number keys I press. I type very fast. If I waw worried about the number of keys I press, I wouldn't be using VHDL at all. -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.54.73 with SMTP id p9mr9874641qag.1.1374072481881; Wed, 17 Jul 2013 07:48:01 -0700 (PDT) X-Received: by 10.50.27.74 with SMTP id r10mr197066igg.10.1374072481818; Wed, 17 Jul 2013 07:48:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t19no1828283qam.0!news-out.google.com!ij2ni362qab.0!nntp.google.com!t19no1964298qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jul 2013 07:48:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <37770732-7105-40ac-8672-709e02780613@googlegroups.com> Subject: Re: Doubts on processes using a single clock. From: Andy Injection-Date: Wed, 17 Jul 2013 14:48:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2029 Xref: news.eternal-september.org comp.lang.vhdl:6789 Eilert, This an important and valuable performance optimization, but it does not ha= ve to use a separate process with a signal to the first one. You can one process and use variables for div and clkEnable. Just insert th= e code for them after the digit counter code. The digit counter code will a= ccess the value of clkEnable a clock cycle after it is updated, and thus ac= cess the registered value, isolating them from the comparison delay. My personal preference, if direction of count is not important (as in the d= iv counter), is to count down and compare to zero, then reload with the per= iod value. For integer down counters, (count - 1 < 0) is true when the carr= y output of the down counter is '1'. Don't try this carry trick with unsign= ed counters; it won't work! Andy From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 18:04:36 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Jul 2013 14:58:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="3739"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+pq/OLocv1WOtVenF4LxOipoJvwDLn6IQ=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: Cancel-Lock: sha1:4/NS9/WsMeO9Hn14UeSxIm5zVzg= Xref: news.eternal-september.org comp.lang.vhdl:6790 It is not just a number of keystrokes. You have extra IF-then nest to handle, which complicates the structure of your code whereas wait until just makes the wait for clk edge explicit. But, thanks for the argument. From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.36.15 with SMTP id r15mr10314559qad.8.1374078321283; Wed, 17 Jul 2013 09:25:21 -0700 (PDT) X-Received: by 10.49.58.242 with SMTP id u18mr361417qeq.23.1374078321260; Wed, 17 Jul 2013 09:25:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!t19no1975214qam.0!news-out.google.com!ij2ni362qab.0!nntp.google.com!t19no1975212qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jul 2013 09:25:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.35 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question on combining if rising_edge(clk). From: Andy Injection-Date: Wed, 17 Jul 2013 16:25:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6791 On Wednesday, July 17, 2013 10:04:36 AM UTC-5, valtih1978 wrote: > It is not just a number of keystrokes. You have extra IF-then nest to han= dle, which complicates the structure of your code whereas wait until just m= akes the wait for clk edge explicit. But, thanks for the argument. It would be "safer" to use "wait until rising_edge(clk)", since "wait until= clk =3D '1';" will trigger if clk changes from 'H' to '1' (not a rising ed= ge), and will not trigger when clk changes from '0' to 'H' (a rising edge).= For the synthesis tool it won't matter, but the RTL simulation will matter= , potentially causing a simulation mismatch between RTL and gate level simu= lations. If you need asynchronous reset (not a matter of choice for some design doma= ins), then you'd have to wait for either/both of two events, and then you'd= have to use an if-statement to figure out which condition triggered the wa= it statement.=20 BTW, an exit statement with a condition is equivalent to an if statement co= ntaining an unconditional exit statement. There are no free lunches. Also, the implicit wait statement in a process with a sensitivity list is a= t the BOTTOM of the process, not at the top. No real difference for synthes= is, but there are differences in simulation: all processes run at startup, = regardless of the sensitivity list. Wait statements will not trigger at sta= rtup. Andy From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 09:29:38 -0700 Organization: Highland Technology, Inc. Lines: 82 Message-ID: <20130717092938.697ff2b6@rg.highlandtechnology.com> References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="12a680e0c6830149a6c062d3054a0196"; logging-data="9386"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+proTPPD0lfFMnyZ2Nc6oA" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:5Hk7ZaQbXHRWT0acHy55EuOh5og= Xref: news.eternal-september.org comp.lang.vhdl:6792 On Tue, 16 Jul 2013 22:45:20 -0700 (PDT) goouse99@gmail.com wrote: > Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: > > wait until clk = '1'; > > > > > > > > requires less typing than > > > > > > > > if clk = '1' then > > > > end if; > > > > > > > > and, furthremore, causes less confusion than the conditional. I wonder > > > > why people keep reproducing this awkward IF pattern instead of wait > > > > until. Single wait until synthesizes well, even in xilinx tools now. > > > > I've checked that may times. > > Hi, > wait until clk = '1'; > > actually creates latches, which most of us are trying to avoid. > > What you probably mean is: > > wait until rising_edge(clk); > > And to answer rickmans question too: > Yes this coding style makes it hard, if not impossible to implement a (async) reset. > However, there are many applications that neither need this. > There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. > But of course, if one needs it, the well known > if reset then > elsif rising_edge(clk) > does the job pretty well, and for thos who whant to save time typing code: > Use EMACS with VHDL mode. > Then 90% of the code is writing itself. > Just make sure you have a reliable TAB button on your keyboard. > > Have a nice synthesis > Eilert > I think this is one of the rare instances where you're wrong. wait until clk = '1'; is equivalent to wait on clk until clk = '1'; which is the same as wait until rising_edge(clk) if clk can only be '0' or '1'. Likewise the OP's if clk = '1' then in a process where clk was the only thing in the sensitivity list should have the same behavior as any of that, or of the more traditional if rising_edge(clk) then I've used the "wait until" form in synthesizable code a couple times. It seems to work, at least on modern synthesizers, and it's nice to save one level of indentation, but it's not a huge deal one way or another. It does make an async reset pretty impossible, for what that's worth in whichever circumstances. I think my biggest problem with it stylistically is that it's simply not canonical. The synthesizer can take in all manner of things that, handed off to someone who didn't write them, would cause consternation. The goal of writing code is to produce something that not only performs correctly, but is intuitively and obviously correct to anyone who sits down to read it. Part of that is doing commonly done things in the way they're commonly done. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Wed, 17 Jul 2013 13:19:27 -0400 Organization: A noiseless patient Spider Lines: 42 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 17 Jul 2013 17:14:33 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="18412"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Xn1fvuoheHl5kmYwWrSxn" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:AhmzdIDrkUvazxq0g+MrIhPCVGU= Xref: news.eternal-september.org comp.lang.vhdl:6793 On 7/17/2013 11:04 AM, valtih1978 wrote: > It is not just a number of keystrokes. You have extra IF-then nest to > handle, which complicates the structure of your code whereas wait until > just makes the wait for clk edge explicit. But, thanks for the argument. Yeah, I understand what you are saying. I just don't consider any of these advantages to be addressing problems I have when writing VHDL. process (clk, reset inputs) begin IF (reset condition) then reset assignments... ELSIF (rising_edge(clk)) then register assignments... ENDIF; end process; This is just a form that is so common and recognizable that I have never given any thought to the need to save a line or two or an indentation level. I have seen the form below used for simple FFs. data_out <= data_in when rising_edge(clk); This is the simplest form I am familiar with, one line, no indents! The problem with the concurrent FF statement is that it is harder to add much logic. The FF input signal would need to be defined by other statements if the logic is very complex at all. Of the three forms, I prefer to just use the clocked process and keep the form constant. No one is confused and the registers are always easily recognized. BTW, I have not read the synthesis standard. Does that mention all three of these forms? Does the standard say anything about initialization in the signal declaration? That might make a big difference in which forms are acceptable or preferred. -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.163.14 with SMTP id y14mr2429574qax.3.1374131912844; Thu, 18 Jul 2013 00:18:32 -0700 (PDT) X-Received: by 10.49.58.242 with SMTP id u18mr478530qeq.23.1374131912806; Thu, 18 Jul 2013 00:18:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!t19no1906519qam.0!news-out.google.com!dk8ni470qab.0!nntp.google.com!t19no2054674qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Jul 2013 00:18:32 -0700 (PDT) In-Reply-To: <20130717092938.697ff2b6@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: goouse99@gmail.com Injection-Date: Thu, 18 Jul 2013 07:18:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 204 Xref: news.eternal-september.org comp.lang.vhdl:6794 Am Mittwoch, 17. Juli 2013 18:29:38 UTC+2 schrieb Rob Gaddi: > On Tue, 16 Jul 2013 22:45:20 -0700 (PDT) > > goo...@.mail,com wrote: > > > > > Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: > > > > wait until clk = '1'; > > > > > > > > > > > > > > > > requires less typing than > > > > > > > > > > > > > > > > if clk = '1' then > > > > > > > > end if; > > > > > > > > > > > > > > > > and, furthremore, causes less confusion than the conditional. I wonder > > > > > > > > why people keep reproducing this awkward IF pattern instead of wait > > > > > > > > until. Single wait until synthesizes well, even in xilinx tools now. > > > > > > > > I've checked that may times. > > > > > > Hi, > > > wait until clk = '1'; > > > > > > actually creates latches, which most of us are trying to avoid. > > > > > > What you probably mean is: > > > > > > wait until rising_edge(clk); > > > > > > And to answer rickmans question too: > > > Yes this coding style makes it hard, if not impossible to implement a (async) reset. > > > However, there are many applications that neither need this. > > > There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. > > > But of course, if one needs it, the well known > > > if reset then > > > elsif rising_edge(clk) > > > does the job pretty well, and for thos who whant to save time typing code: > > > Use EMACS with VHDL mode. > > > Then 90% of the code is writing itself. > > > Just make sure you have a reliable TAB button on your keyboard. > > > > > > Have a nice synthesis > > > Eilert > > > > > > > I think this is one of the rare instances where you're wrong. > > wait until clk = '1'; > > is equivalent to > > wait on clk until clk = '1'; > > which is the same as > > wait until rising_edge(clk) > > if clk can only be '0' or '1'. > > > > Likewise the OP's > > if clk = '1' then > > in a process where clk was the only thing in the sensitivity list > > should have the same behavior as any of that, or of the more traditional > > if rising_edge(clk) then > > > > I've used the "wait until" form in synthesizable code a couple times. > > It seems to work, at least on modern synthesizers, and it's nice to save > > one level of indentation, but it's not a huge deal one way or another. > > It does make an async reset pretty impossible, for what that's worth in > > whichever circumstances. > > > > I think my biggest problem with it stylistically is that it's simply > > not canonical. The synthesizer can take in all manner of things that, > > handed off to someone who didn't write them, would cause > > consternation. The goal of writing code is to produce something that > > not only performs correctly, but is intuitively and obviously correct > > to anyone who sits down to read it. Part of that is doing commonly > > done things in the way they're commonly done. > > > > -- > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Email address domain is currently out of order. See above to fix. Hi Rob, just tested it in ISE 13.1. It really gives a FF, there's always more to learn about VHDL. I understand the reasoning behind the processes with only clock on the sensitivity list. But actually the synthesis tools ignore the sensitivity list, so it can not have any effect to the created logic. Moreover, VHDL-2008 just came up with "process(all)" to simplify things, and what if you want to have resets? What if you have just one input signal and want to create something purely combinatorical? As you pointed out wait until clk = '1'; is just a simplification of wait on clk until clk = '1'; The signals behind the "on" are a sensitivity list and therefore event triggered. So it makes some sense to create a FF. I just wonder why the sensitivity list here isn't ignored. Even this leads to a FF: wait until (Clock = '1' and Clock2 = '1'); A gated clock, that is! wait on Clock until (Clock = '1' and Clock2 = '1'); Gives the same gated clock. But Clock2 is not on the sensitivity list. Is this a clue that the sensitivity list is ignored here too? How to implement a Clock Enable with wait until? wait until rising_edge(Clock) and Clock2 = '1'; So, this works, but isn't this a contradiction? While the sole clk='1' is edge sensitive, and Clock2 ='1' before has been seen as a second clock input, now it is seen as a CE. Weird! Any logical explanation someone? wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE This again gives a FF with CE(clock2). So the Event triggering by the sensitivity list is truly ignored in synthesis. ___________ I agree, code readability for the common engineer should be a major concern. While the example of wait until clk = '1'; works, the majority, like me just lately, would be alerted since they would suspect Latches to appear. The alternative, if one chooses to use wait until for some reason, is much simpler recognized to be edge sensitive: wait until rising_edge(clk); So just a few characters more saves from much confusion when it comes to code maintainance etc. I wonder if someone who explicitely wanted to build a latch for some reason ever stumbled about this syntax and cursed the tools to hell since no latch would appear. :-) Kind regards Eilert From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Thu, 18 Jul 2013 14:20:26 -0400 Organization: A noiseless patient Spider Lines: 224 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 18 Jul 2013 18:14:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="1501"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GFPRKsWD63yMn0CWoTEm8" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> Cancel-Lock: sha1:NsLRKGLpZpff2psXrM8rPAcv4SA= Xref: news.eternal-september.org comp.lang.vhdl:6795 On 7/18/2013 3:18 AM, goouse99@gmail.com wrote: > Am Mittwoch, 17. Juli 2013 18:29:38 UTC+2 schrieb Rob Gaddi: >> On Tue, 16 Jul 2013 22:45:20 -0700 (PDT) >> >> goo...@.mail,com wrote: >> >> >> >>> Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: >> >>>> wait until clk = '1'; >> >>>> >> >>>> >> >>>> >> >>>> requires less typing than >> >>>> >> >>>> >> >>>> >> >>>> if clk = '1' then >> >>>> >> >>>> end if; >> >>>> >> >>>> >> >>>> >> >>>> and, furthremore, causes less confusion than the conditional. I wonder >> >>>> >> >>>> why people keep reproducing this awkward IF pattern instead of wait >> >>>> >> >>>> until. Single wait until synthesizes well, even in xilinx tools now. >> >>>> >> >>>> I've checked that may times. >> >>> >> >>> Hi, >> >>> wait until clk = '1'; >> >>> >> >>> actually creates latches, which most of us are trying to avoid. >> >>> >> >>> What you probably mean is: >> >>> >> >>> wait until rising_edge(clk); >> >>> >> >>> And to answer rickmans question too: >> >>> Yes this coding style makes it hard, if not impossible to implement a (async) reset. >> >>> However, there are many applications that neither need this. >> >>> There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. >> >>> But of course, if one needs it, the well known >> >>> if reset then >> >>> elsif rising_edge(clk) >> >>> does the job pretty well, and for thos who whant to save time typing code: >> >>> Use EMACS with VHDL mode. >> >>> Then 90% of the code is writing itself. >> >>> Just make sure you have a reliable TAB button on your keyboard. >> >>> >> >>> Have a nice synthesis >> >>> Eilert >> >>> >> >> >> >> I think this is one of the rare instances where you're wrong. >> >> wait until clk = '1'; >> >> is equivalent to >> >> wait on clk until clk = '1'; >> >> which is the same as >> >> wait until rising_edge(clk) >> >> if clk can only be '0' or '1'. >> >> >> >> Likewise the OP's >> >> if clk = '1' then >> >> in a process where clk was the only thing in the sensitivity list >> >> should have the same behavior as any of that, or of the more traditional >> >> if rising_edge(clk) then >> >> >> >> I've used the "wait until" form in synthesizable code a couple times. >> >> It seems to work, at least on modern synthesizers, and it's nice to save >> >> one level of indentation, but it's not a huge deal one way or another. >> >> It does make an async reset pretty impossible, for what that's worth in >> >> whichever circumstances. >> >> >> >> I think my biggest problem with it stylistically is that it's simply >> >> not canonical. The synthesizer can take in all manner of things that, >> >> handed off to someone who didn't write them, would cause >> >> consternation. The goal of writing code is to produce something that >> >> not only performs correctly, but is intuitively and obviously correct >> >> to anyone who sits down to read it. Part of that is doing commonly >> >> done things in the way they're commonly done. >> >> >> >> -- >> >> Rob Gaddi, Highland Technology -- www.highlandtechnology.com >> >> Email address domain is currently out of order. See above to fix. > > Hi Rob, > just tested it in ISE 13.1. > It really gives a FF, there's always more to learn about VHDL. > > I understand the reasoning behind the processes with only clock on the sensitivity list. But actually the synthesis tools ignore the sensitivity list, so it can not have any effect to the created logic. > Moreover, VHDL-2008 just came up with "process(all)" to simplify things, and what if you want to have resets? What if you have just one input signal and want to create something purely combinatorical? > > As you pointed out > wait until clk = '1'; > is just a simplification of > wait on clk until clk = '1'; > > The signals behind the "on" are a sensitivity list and therefore event triggered. So it makes some sense to create a FF. I just wonder why the sensitivity list here isn't ignored. Even this leads to a FF: > wait until (Clock = '1' and Clock2 = '1'); > A gated clock, that is! > wait on Clock until (Clock = '1' and Clock2 = '1'); > Gives the same gated clock. But Clock2 is not on the sensitivity list. > Is this a clue that the sensitivity list is ignored here too? > How to implement a Clock Enable with wait until? > wait until rising_edge(Clock) and Clock2 = '1'; > So, this works, but isn't this a contradiction? > While the sole clk='1' is edge sensitive, and Clock2 ='1' before has been seen as a second clock input, now it is seen as a CE. Weird! Any logical explanation someone? > > wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE > This again gives a FF with CE(clock2). So the Event triggering by the sensitivity list is truly ignored in synthesis. Do you know that these forms are synthesized the way you state? This last one does not actually describe a FF with CE. If Clock2 is asserted the wait will trigger, but unless Clock is rising at the same time it won't be true, will it? The simulation would not work, so if this works in synthesis you have a mismatch. > ___________ > > I agree, code readability for the common engineer should be a major concern. > While the example of > wait until clk = '1'; > works, the majority, like me just lately, would be alerted since they would suspect Latches to appear. > The alternative, if one chooses to use wait until for some reason, is much simpler recognized to be edge sensitive: > wait until rising_edge(clk); > So just a few characters more saves from much confusion when it comes to code maintainance etc. I would still find this form confusing. I don't actually "read" code for the most part. I speed read it like I read a book. It is only when I am looking for a bug that I go into second grade, "read every word" mode. So I am very used to seeing the visual clues from the white space used with the conventional structures. Like a stop sign being octagonal and a warning sign being a diamond, etc. > I wonder if someone who explicitely wanted to build a latch for some reason ever stumbled about this syntax and cursed the tools to hell since no latch would appear. :-) Yeah, that could be interesting. -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: Simulating a bidirectional bus delay Date: Fri, 19 Jul 2013 02:51:34 +0100 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <8781a259-e640-4083-aa2a-c6e8c4c8e66b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Jul 2013 01:45:26 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c52eb0a8e8cd1bdd45d93b94f841c8de"; logging-data="24909"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/C6XBhx8msCWYv1JdJSRQu" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: Cancel-Lock: sha1:pQ5b+MI9QcFMssoon31og3/PuwU= Xref: news.eternal-september.org comp.lang.vhdl:6796 On 17/07/2013 02:37, KJ wrote: > On Tuesday, July 16, 2013 6:22:03 AM UTC-4, Fredxx wrote: >> I have only used Bidi_Dly.vhd on bidirectional signals. > > Here is a link to Ben Cohen's Zero ohm resistor model. I've used > this model although it too will introduce glitches when the driver > changs that might be similar to what you're seeing. > http://www.google.com/url?sa=t&rct=j&q=&esrc=s&frm=1&source=web&cd=1&cad=rja&ved=0CC0QFjAA&url=http%3A%2F%2Fsystemverilog.us%2Fzohm0_ea.vhd&ei=HvTlUdGbCuTeyAGI14HIDA&usg=AFQjCNGRo17-UoryYGNS0CAAJGoG-o5cHA&sig2=GvajypCFjvbrRSoZ75PhWw&bvm=bv.49405654,d.aWc This model doesn't seem to have a delay associated, apart from a delta time so seems I'm missing something here. Like the model I use, there is this "Z" during a transition. > And here is a link to an alternative model written by someone who > tried and did not like Ben's model. I haven't tried it > http://www.edaboard.co.uk/would-you-like-the-alternative-to-zero-ohm-t517714.html This version doesn't cause the annoying "Z" during a transition, and has a generic to add the delay. It seems rather neat in discovering which port has control over the other. It also means I can undo the modifications to the Micron model! Many thanks for your ideas and links. From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.163.14 with SMTP id y14mr8457742qax.3.1374219257760; Fri, 19 Jul 2013 00:34:17 -0700 (PDT) X-Received: by 10.49.11.140 with SMTP id q12mr688935qeb.9.1374219257744; Fri, 19 Jul 2013 00:34:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t19no2185880qam.0!news-out.google.com!dk8ni601qab.0!nntp.google.com!t19no2185878qam.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jul 2013 00:34:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: goouse99@gmail.com Injection-Date: Fri, 19 Jul 2013 07:34:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 10486 Xref: news.eternal-september.org comp.lang.vhdl:6797 Am Donnerstag, 18. Juli 2013 20:20:26 UTC+2 schrieb rickman: > On 7/18/2013 3:18 AM, goo...@.mail,com wrote: > > > Am Mittwoch, 17. Juli 2013 18:29:38 UTC+2 schrieb Rob Gaddi: > > >> On Tue, 16 Jul 2013 22:45:20 -0700 (PDT) > > >> > > >> goo...@.mail,com wrote: > > >> > > >> > > >> > > >>> Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: > > >> > > >>>> wait until clk = '1'; > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> requires less typing than > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> if clk = '1' then > > >> > > >>>> > > >> > > >>>> end if; > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> and, furthremore, causes less confusion than the conditional. I wonder > > >> > > >>>> > > >> > > >>>> why people keep reproducing this awkward IF pattern instead of wait > > >> > > >>>> > > >> > > >>>> until. Single wait until synthesizes well, even in xilinx tools now. > > >> > > >>>> > > >> > > >>>> I've checked that may times. > > >> > > >>> > > >> > > >>> Hi, > > >> > > >>> wait until clk = '1'; > > >> > > >>> > > >> > > >>> actually creates latches, which most of us are trying to avoid. > > >> > > >>> > > >> > > >>> What you probably mean is: > > >> > > >>> > > >> > > >>> wait until rising_edge(clk); > > >> > > >>> > > >> > > >>> And to answer rickmans question too: > > >> > > >>> Yes this coding style makes it hard, if not impossible to implement a (async) reset. > > >> > > >>> However, there are many applications that neither need this. > > >> > > >>> There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. > > >> > > >>> But of course, if one needs it, the well known > > >> > > >>> if reset then > > >> > > >>> elsif rising_edge(clk) > > >> > > >>> does the job pretty well, and for thos who whant to save time typing code: > > >> > > >>> Use EMACS with VHDL mode. > > >> > > >>> Then 90% of the code is writing itself. > > >> > > >>> Just make sure you have a reliable TAB button on your keyboard. > > >> > > >>> > > >> > > >>> Have a nice synthesis > > >> > > >>> Eilert > > >> > > >>> > > >> > > >> > > >> > > >> I think this is one of the rare instances where you're wrong. > > >> > > >> wait until clk = '1'; > > >> > > >> is equivalent to > > >> > > >> wait on clk until clk = '1'; > > >> > > >> which is the same as > > >> > > >> wait until rising_edge(clk) > > >> > > >> if clk can only be '0' or '1'. > > >> > > >> > > >> > > >> Likewise the OP's > > >> > > >> if clk = '1' then > > >> > > >> in a process where clk was the only thing in the sensitivity list > > >> > > >> should have the same behavior as any of that, or of the more traditional > > >> > > >> if rising_edge(clk) then > > >> > > >> > > >> > > >> I've used the "wait until" form in synthesizable code a couple times. > > >> > > >> It seems to work, at least on modern synthesizers, and it's nice to save > > >> > > >> one level of indentation, but it's not a huge deal one way or another. > > >> > > >> It does make an async reset pretty impossible, for what that's worth in > > >> > > >> whichever circumstances. > > >> > > >> > > >> > > >> I think my biggest problem with it stylistically is that it's simply > > >> > > >> not canonical. The synthesizer can take in all manner of things that, > > >> > > >> handed off to someone who didn't write them, would cause > > >> > > >> consternation. The goal of writing code is to produce something that > > >> > > >> not only performs correctly, but is intuitively and obviously correct > > >> > > >> to anyone who sits down to read it. Part of that is doing commonly > > >> > > >> done things in the way they're commonly done. > > >> > > >> > > >> > > >> -- > > >> > > >> Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > >> > > >> Email address domain is currently out of order. See above to fix. > > > > > > Hi Rob, > > > just tested it in ISE 13.1. > > > It really gives a FF, there's always more to learn about VHDL. > > > > > > I understand the reasoning behind the processes with only clock on the sensitivity list. But actually the synthesis tools ignore the sensitivity list, so it can not have any effect to the created logic. > > > Moreover, VHDL-2008 just came up with "process(all)" to simplify things, and what if you want to have resets? What if you have just one input signal and want to create something purely combinatorical? > > > > > > As you pointed out > > > wait until clk = '1'; > > > is just a simplification of > > > wait on clk until clk = '1'; > > > > > > The signals behind the "on" are a sensitivity list and therefore event triggered. So it makes some sense to create a FF. I just wonder why the sensitivity list here isn't ignored. Even this leads to a FF: > > > wait until (Clock = '1' and Clock2 = '1'); > > > A gated clock, that is! > > > wait on Clock until (Clock = '1' and Clock2 = '1'); > > > Gives the same gated clock. But Clock2 is not on the sensitivity list. > > > Is this a clue that the sensitivity list is ignored here too? > > > How to implement a Clock Enable with wait until? > > > wait until rising_edge(Clock) and Clock2 = '1'; > > > So, this works, but isn't this a contradiction? > > > While the sole clk='1' is edge sensitive, and Clock2 ='1' before has been seen as a second clock input, now it is seen as a CE. Weird! Any logical explanation someone? > > > > > > wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE > > > This again gives a FF with CE(clock2). So the Event triggering by the sensitivity list is truly ignored in synthesis. > > > > Do you know that these forms are synthesized the way you state? This > > last one does not actually describe a FF with CE. If Clock2 is asserted > > the wait will trigger, but unless Clock is rising at the same time it > > won't be true, will it? The simulation would not work, so if this works > > in synthesis you have a mismatch. > > > > > > > ___________ > > > > > > I agree, code readability for the common engineer should be a major concern. > > > While the example of > > > wait until clk = '1'; > > > works, the majority, like me just lately, would be alerted since they would suspect Latches to appear. > > > The alternative, if one chooses to use wait until for some reason, is much simpler recognized to be edge sensitive: > > > wait until rising_edge(clk); > > > So just a few characters more saves from much confusion when it comes to code maintainance etc. > > > > I would still find this form confusing. I don't actually "read" code > > for the most part. I speed read it like I read a book. It is only when > > I am looking for a bug that I go into second grade, "read every word" > > mode. So I am very used to seeing the visual clues from the white space > > used with the conventional structures. Like a stop sign being octagonal > > and a warning sign being a diamond, etc. > > > > > > > I wonder if someone who explicitely wanted to build a latch for some reason ever stumbled about this syntax and cursed the tools to hell since no latch would appear. :-) > > > > Yeah, that could be interesting. > > > > -- > > > > Rick Hi Rick, yes, I've tested all the mentioned examples with ISE 13.4 XST and looked at the technology view to see the result. The last example : wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE surely would give the mentioned mismatch with simulation. But, and that's the point, this is the same as with a process with wrong sensitivity list. The equivalent process would be like this: process(Clock2) is begin if rising_edge(Clock) then if Clock2 = '1' then --the CE Dout <= Din; -- simple Datapath (Register) end if; end if; end process; Synthesis would give a nice FF with CE but simulation would just "trigger" the process on a Clock2 event. I just wanted to check wether synthesis ignores sensitivity lists in wait statements too, or not. __________ With confusing you mean the general use of wait statement synchronized processes? Basically I agree to that. While at (rare) times the wait-statement coding results in much simpler code one could well do without it for the sake of a uniform coding style. And if some "code-artist" insists on using this in a project, the source could be used as a simulation reference to verify a style conform recoded model. Kind regards Eilert From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Fri, 19 Jul 2013 13:03:19 -0400 Organization: A noiseless patient Spider Lines: 503 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Jul 2013 16:58:18 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="24038"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19UShreOpKhR27/mi/0hugx" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> Cancel-Lock: sha1:vO+xr+kFEyeHvuTAdOEQwXtxfek= Xref: news.eternal-september.org comp.lang.vhdl:6798 On 7/19/2013 3:34 AM, goouse99@gmail.com wrote: > Am Donnerstag, 18. Juli 2013 20:20:26 UTC+2 schrieb rickman: >> On 7/18/2013 3:18 AM, goo...@.mail,com wrote: >> >>> Am Mittwoch, 17. Juli 2013 18:29:38 UTC+2 schrieb Rob Gaddi: >> >>>> On Tue, 16 Jul 2013 22:45:20 -0700 (PDT) >> >>>> >> >>>> goo...@.mail,com wrote: >> >>>> >> >>>> >> >>>> >> >>>>> Am Dienstag, 16. Juli 2013 14:47:49 UTC+2 schrieb valtih1978: >> >>>> >> >>>>>> wait until clk = '1'; >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> requires less typing than >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> if clk = '1' then >> >>>> >> >>>>>> >> >>>> >> >>>>>> end if; >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> and, furthremore, causes less confusion than the conditional. I wonder >> >>>> >> >>>>>> >> >>>> >> >>>>>> why people keep reproducing this awkward IF pattern instead of wait >> >>>> >> >>>>>> >> >>>> >> >>>>>> until. Single wait until synthesizes well, even in xilinx tools now. >> >>>> >> >>>>>> >> >>>> >> >>>>>> I've checked that may times. >> >>>> >> >>>>> >> >>>> >> >>>>> Hi, >> >>>> >> >>>>> wait until clk = '1'; >> >>>> >> >>>>> >> >>>> >> >>>>> actually creates latches, which most of us are trying to avoid. >> >>>> >> >>>>> >> >>>> >> >>>>> What you probably mean is: >> >>>> >> >>>>> >> >>>> >> >>>>> wait until rising_edge(clk); >> >>>> >> >>>>> >> >>>> >> >>>>> And to answer rickmans question too: >> >>>> >> >>>>> Yes this coding style makes it hard, if not impossible to implement a (async) reset. >> >>>> >> >>>>> However, there are many applications that neither need this. >> >>>> >> >>>>> There's also this famous paper from Xilinx suggestiong to avoid async resets when possible. >> >>>> >> >>>>> But of course, if one needs it, the well known >> >>>> >> >>>>> if reset then >> >>>> >> >>>>> elsif rising_edge(clk) >> >>>> >> >>>>> does the job pretty well, and for thos who whant to save time typing code: >> >>>> >> >>>>> Use EMACS with VHDL mode. >> >>>> >> >>>>> Then 90% of the code is writing itself. >> >>>> >> >>>>> Just make sure you have a reliable TAB button on your keyboard. >> >>>> >> >>>>> >> >>>> >> >>>>> Have a nice synthesis >> >>>> >> >>>>> Eilert >> >>>> >> >>>>> >> >>>> >> >>>> >> >>>> >> >>>> I think this is one of the rare instances where you're wrong. >> >>>> >> >>>> wait until clk = '1'; >> >>>> >> >>>> is equivalent to >> >>>> >> >>>> wait on clk until clk = '1'; >> >>>> >> >>>> which is the same as >> >>>> >> >>>> wait until rising_edge(clk) >> >>>> >> >>>> if clk can only be '0' or '1'. >> >>>> >> >>>> >> >>>> >> >>>> Likewise the OP's >> >>>> >> >>>> if clk = '1' then >> >>>> >> >>>> in a process where clk was the only thing in the sensitivity list >> >>>> >> >>>> should have the same behavior as any of that, or of the more traditional >> >>>> >> >>>> if rising_edge(clk) then >> >>>> >> >>>> >> >>>> >> >>>> I've used the "wait until" form in synthesizable code a couple times. >> >>>> >> >>>> It seems to work, at least on modern synthesizers, and it's nice to save >> >>>> >> >>>> one level of indentation, but it's not a huge deal one way or another. >> >>>> >> >>>> It does make an async reset pretty impossible, for what that's worth in >> >>>> >> >>>> whichever circumstances. >> >>>> >> >>>> >> >>>> >> >>>> I think my biggest problem with it stylistically is that it's simply >> >>>> >> >>>> not canonical. The synthesizer can take in all manner of things that, >> >>>> >> >>>> handed off to someone who didn't write them, would cause >> >>>> >> >>>> consternation. The goal of writing code is to produce something that >> >>>> >> >>>> not only performs correctly, but is intuitively and obviously correct >> >>>> >> >>>> to anyone who sits down to read it. Part of that is doing commonly >> >>>> >> >>>> done things in the way they're commonly done. >> >>>> >> >>>> >> >>>> >> >>>> -- >> >>>> >> >>>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com >> >>>> >> >>>> Email address domain is currently out of order. See above to fix. >> >>> >> >>> Hi Rob, >> >>> just tested it in ISE 13.1. >> >>> It really gives a FF, there's always more to learn about VHDL. >> >>> >> >>> I understand the reasoning behind the processes with only clock on the sensitivity list. But actually the synthesis tools ignore the sensitivity list, so it can not have any effect to the created logic. >> >>> Moreover, VHDL-2008 just came up with "process(all)" to simplify things, and what if you want to have resets? What if you have just one input signal and want to create something purely combinatorical? >> >>> >> >>> As you pointed out >> >>> wait until clk = '1'; >> >>> is just a simplification of >> >>> wait on clk until clk = '1'; >> >>> >> >>> The signals behind the "on" are a sensitivity list and therefore event triggered. So it makes some sense to create a FF. I just wonder why the sensitivity list here isn't ignored. Even this leads to a FF: >> >>> wait until (Clock = '1' and Clock2 = '1'); >> >>> A gated clock, that is! >> >>> wait on Clock until (Clock = '1' and Clock2 = '1'); >> >>> Gives the same gated clock. But Clock2 is not on the sensitivity list. >> >>> Is this a clue that the sensitivity list is ignored here too? >> >>> How to implement a Clock Enable with wait until? >> >>> wait until rising_edge(Clock) and Clock2 = '1'; >> >>> So, this works, but isn't this a contradiction? >> >>> While the sole clk='1' is edge sensitive, and Clock2 ='1' before has been seen as a second clock input, now it is seen as a CE. Weird! Any logical explanation someone? >> >>> >> >>> wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE >> >>> This again gives a FF with CE(clock2). So the Event triggering by the sensitivity list is truly ignored in synthesis. >> >> >> >> Do you know that these forms are synthesized the way you state? This >> >> last one does not actually describe a FF with CE. If Clock2 is asserted >> >> the wait will trigger, but unless Clock is rising at the same time it >> >> won't be true, will it? The simulation would not work, so if this works >> >> in synthesis you have a mismatch. >> >> >> >> >> >>> ___________ >> >>> >> >>> I agree, code readability for the common engineer should be a major concern. >> >>> While the example of >> >>> wait until clk = '1'; >> >>> works, the majority, like me just lately, would be alerted since they would suspect Latches to appear. >> >>> The alternative, if one chooses to use wait until for some reason, is much simpler recognized to be edge sensitive: >> >>> wait until rising_edge(clk); >> >>> So just a few characters more saves from much confusion when it comes to code maintainance etc. >> >> >> >> I would still find this form confusing. I don't actually "read" code >> >> for the most part. I speed read it like I read a book. It is only when >> >> I am looking for a bug that I go into second grade, "read every word" >> >> mode. So I am very used to seeing the visual clues from the white space >> >> used with the conventional structures. Like a stop sign being octagonal >> >> and a warning sign being a diamond, etc. >> >> >> >> >> >>> I wonder if someone who explicitely wanted to build a latch for some reason ever stumbled about this syntax and cursed the tools to hell since no latch would appear. :-) >> >> >> >> Yeah, that could be interesting. >> >> >> >> -- >> >> >> >> Rick > > Hi Rick, > yes, I've tested all the mentioned examples with ISE 13.4 XST and looked at the technology view to see the result. > > The last example : > wait on Clock2 until rising_edge(Clock) and Clock2 = '1'; --FF with CE > surely would give the mentioned mismatch with simulation. > But, and that's the point, this is the same as with a process with wrong sensitivity list. > The equivalent process would be like this: > > process(Clock2) is > begin > if rising_edge(Clock) then > if Clock2 = '1' then --the CE > Dout<= Din; -- simple Datapath (Register) > end if; > end if; > end process; > > Synthesis would give a nice FF with CE but simulation would just "trigger" the process on a Clock2 event. > > I just wanted to check wether synthesis ignores sensitivity lists in wait statements too, or not. I see. Interesting even if perhaps not useful. I typically don't dig into how the tools work beyond what I want to do with them, but this can be useful info when chasing bugs. The more you know how the tools work, the better you will know how they don't work. > __________ > > With confusing you mean the general use of wait statement synchronized processes? > Basically I agree to that. > While at (rare) times the wait-statement coding results in much simpler code one could well do without it for the sake of a uniform coding style. > And if some "code-artist" insists on using this in a project, the source could be used as a simulation reference to verify a style conform recoded model. I don't follow that last sentence. Yes, I'm talking about the general use of wait statements for FF inference. But then I make use of the async reset in nearly all clocked processes so maybe I'm a little biased. :) I don't typically deal with any "code artists". I work alone and even when I get code from vendors they nearly always use more conventional forms. BTW, working alone has its down side. That is one of the main reasons I post in newsgroups. Without communications here I would get nearly no cross-fertilization. Even if I don't use an idea that others provide, I might well be inspired by it. So thanks for your comments and ideas. -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.236.63.37 with SMTP id z25mr9120377yhc.49.1374254857219; Fri, 19 Jul 2013 10:27:37 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr747876qeg.5.1374254857092; Fri, 19 Jul 2013 10:27:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!u2no44433qao.0!news-out.google.com!dk8ni705qab.0!nntp.google.com!f1no49804qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jul 2013 10:27:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Squaring of a binary number From: lokesh kumar Injection-Date: Fri, 19 Jul 2013 17:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6799 Hi, Can anyone help me to design a code to square binary number? Suppose "A" is a 5 bit number (a4a3a2a1a0) If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0 " ( a 10 bit number) For example : Suppose A= 11111 Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for the adding to get the final result). Could anyone please help me out how to make a generalized code for squaring of a 5-bit number to get an output like this? Many Thanks! From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.36.15 with SMTP id r15mr22952513qad.8.1374259139467; Fri, 19 Jul 2013 11:38:59 -0700 (PDT) X-Received: by 10.49.94.174 with SMTP id dd14mr765258qeb.14.1374259139413; Fri, 19 Jul 2013 11:38:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!f1no56557qae.0!news-out.google.com!dk8ni705qab.0!nntp.google.com!f1no56553qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jul 2013 11:38:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Squaring of a binary number From: 1999outback@gmail.com Injection-Date: Fri, 19 Jul 2013 18:38:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6800 You might want to check your math! 11111 * 11111 = 1111000001. Assuming use of proper types from numeric_std, try this: result <= a * a; Here is an excellent reference for VHDL math: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.236.41.103 with SMTP id g67mr9372020yhb.45.1374260897233; Fri, 19 Jul 2013 12:08:17 -0700 (PDT) X-Received: by 10.49.25.227 with SMTP id f3mr802164qeg.33.1374260897091; Fri, 19 Jul 2013 12:08:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!u2no52850qao.0!news-out.google.com!dk8ni752qab.0!nntp.google.com!u2no52842qao.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jul 2013 12:08:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Fri, 19 Jul 2013 19:08:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 Xref: news.eternal-september.org comp.lang.vhdl:6801 On Saturday, July 20, 2013 12:08:59 AM UTC+5:30, 1999o...@gmail.com wrote: > You might want to check your math! 11111 * 11111 = 1111000001. > > > > Assuming use of proper types from numeric_std, try this: > > > > result <= a * a; > > > > Here is an excellent reference for VHDL math: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp3-2.free.fr!not-for-mail Date: Fri, 19 Jul 2013 23:15:33 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number References: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> In-Reply-To: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 13 Message-ID: <51e9ac75$0$3733$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 19 Jul 2013 23:15:34 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1374268534 news-1.free.fr 3733 88.185.146.198:1498 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:6802 Le 19/07/2013 21:08, lokesh kumar a écrit : > Do not consider a simple binary addition. It is an XOR operation. > You did the simple binary operation to get the result. But if you > do XOR operation to add then you will get the same result as mine. No matter how you do it, a multiplication is a multiplication and the result doesn't change. You squared 31 (written in binary), the result IS 961 no matter how you got it. Either your result is wrong, or what you want is not a square. Nicolas From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Fri, 19 Jul 2013 17:16:16 -0400 Organization: Alacron, Inc. Lines: 32 Message-ID: References: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Jul 2013 21:11:10 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="11568"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bbNQT+yRtB3BPnOd52gtoNadWv2Zib5U=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> Cancel-Lock: sha1:bOpCsc6rRdTQLDoDwiTMtTXETmo= Xref: news.eternal-september.org comp.lang.vhdl:6803 lokesh kumar wrote: > Do not consider a simple binary addition. It is an XOR operation. You did the simple binary operation to get the result. But if you do XOR operation to add then you will get the same result as mine. So in other words, you are doing _everything_ the same as a normal multiplication _except_ using bitwise XOR instead of adding? In other words as you add each column you throw away any carry bits? So for your example you have: 11111 11111 11111 11111 11111 ___________ 101010101 What if I have a non-trivial case like 10110? Are you doing this as a typical multiply like: 00000 10110 10110 00000 10110 __________ 100010100 Where only my final "addition" becomes an XOR? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Fri, 19 Jul 2013 23:13:10 +0100 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Jul 2013 22:07:01 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c52eb0a8e8cd1bdd45d93b94f841c8de"; logging-data="1485"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX196buaJele9Bs/2SemWubS6" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> Cancel-Lock: sha1:wbOPi+uqJbHajLQ3u8UUn6VI/64= Xref: news.eternal-september.org comp.lang.vhdl:6804 On 19/07/2013 08:34, goouse99@gmail.com wrote: >> Rick > > Hi Rick, yes, I've tested all the mentioned examples with ISE 13.4 > XST and looked at the technology view to see the result. > > The last example : wait on Clock2 until rising_edge(Clock) and Clock2 > = '1'; --FF with CE surely would give the mentioned mismatch with > simulation. But, and that's the point, this is the same as with a > process with wrong sensitivity list. The equivalent process would be > like this: > > process(Clock2) is begin if rising_edge(Clock) then if Clock2 = '1' > then --the CE Dout <= Din; -- simple Datapath (Register) end if; end > if; end process; > > Synthesis would give a nice FF with CE but simulation would just > "trigger" the process on a Clock2 event. > > I just wanted to check wether synthesis ignores sensitivity lists in > wait statements too, or not. > I didn't think you could have a sensitivity list to a process using "wait" statements. Or should I say Modelsym throws wobblies if you do? From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.86.200 with SMTP id t8mr23840748qal.0.1374272074563; Fri, 19 Jul 2013 15:14:34 -0700 (PDT) X-Received: by 10.49.16.163 with SMTP id h3mr829928qed.24.1374272074537; Fri, 19 Jul 2013 15:14:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!u2no115067qao.0!news-out.google.com!dk8ni705qab.0!nntp.google.com!f1no123084qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jul 2013 15:14:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <032d467e-aa54-46bd-857a-6015a969b455@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <948885a5-4c47-420b-90d1-1cc3484c13dc@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Fri, 19 Jul 2013 22:14:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 72 Xref: news.eternal-september.org comp.lang.vhdl:6805 On Saturday, July 20, 2013 2:46:16 AM UTC+5:30, Gabor Sz wrote: > lokesh kumar wrote: >=20 >=20 >=20 > > Do not consider a simple binary addition. It is an XOR operation. You d= id the simple binary operation to get the result. But if you do XOR operati= on to add then you will get the same result as mine. >=20 >=20 >=20 > So in other words, you are doing _everything_ the same as a normal >=20 > multiplication _except_ using bitwise XOR instead of adding? In >=20 > other words as you add each column you throw away any carry bits? >=20 > So for your example you have: >=20 >=20 >=20 > 11111 >=20 > 11111 >=20 > 11111 >=20 > 11111 >=20 > 11111 >=20 > ___________ >=20 > 101010101 >=20 >=20 >=20 > What if I have a non-trivial case like 10110? Are you doing this >=20 > as a typical multiply like: >=20 >=20 >=20 > 00000 >=20 > 10110 >=20 > 10110 >=20 > 00000 >=20 > 10110 >=20 > __________ >=20 > 100010100 >=20 >=20 >=20 > Where only my final "addition" becomes an XOR? >=20 >=20 >=20 > --=20 >=20 > Gabor Yes, the final addition becomes XOR all the times. Because I am working on = Galois field. So if I take a 5-bit number and do the square of it. Then I w= ill get a 10 bit number. But I again I will have to use the irreducible pol= ynomial to the 10 bit number to convert it to 5 bit. That is the concept of= Galois field. So basically I want to know how to make this 10 bit number b= y taking the square of a 5-bit number in VHDL. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Fri, 19 Jul 2013 23:23:49 +0100 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Jul 2013 22:17:40 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c52eb0a8e8cd1bdd45d93b94f841c8de"; logging-data="4566"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199I+BXcZ1qIm/hTktF4564" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: Cancel-Lock: sha1:CtS+1fWdg51e1TsW9lIKxbbcBFI= Xref: news.eternal-september.org comp.lang.vhdl:6806 On 19/07/2013 18:27, lokesh kumar wrote: > Hi, > > Can anyone help me to design a code to square binary number? > > Suppose "A" is a 5 bit number (a4a3a2a1a0) > > If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0 " ( a 10 bit number) All these numbers look bigger than 5 or 10 bits! > > For example : Suppose A= 11111 > Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for the adding to get the final result). 31 x 31 = 961 (11 1100 0001) So clearly XORing is incorrect. > Could anyone please help me out how to make a generalized code for squaring of a 5-bit number to get an output like this? > A square operation is precisely that, A * A. Most FPGAs have some pretty good multipliers, best to use them. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Fri, 19 Jul 2013 23:38:53 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 03:32:53 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="66a2e787fc3f714a7a69821e525a4489"; logging-data="16156"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX197C3r9QCq7kKhsQxQ8GSHQ" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: Cancel-Lock: sha1:EXylKM66ensaikh1o9BQzBcmLjs= Xref: news.eternal-september.org comp.lang.vhdl:6807 On 7/19/2013 6:23 PM, Fredxx wrote: > On 19/07/2013 18:27, lokesh kumar wrote: >> Hi, >> >> Can anyone help me to design a code to square binary number? >> >> Suppose "A" is a 5 bit number (a4a3a2a1a0) >> >> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 >> a0 " ( a 10 bit number) > > All these numbers look bigger than 5 or 10 bits! > The syntax is not VHDL. He means for A to be a 5-bit vector and the result ended up as: '0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0) >> >> For example : Suppose A= 11111 >> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for >> the adding to get the final result). > > 31 x 31 = 961 (11 1100 0001) > > So clearly XORing is incorrect. > For the OP clearly "multiplication" or "squaring" is incorrect. He apparently wants a different function that is similar to multiplication but lacks any carries on the intermediate addition. >> Could anyone please help me out how to make a generalized code for >> squaring of a 5-bit number to get an output like this? >> > > A square operation is precisely that, A * A. Most FPGAs have some > pretty good multipliers, best to use them. From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 04:09:08 -0400 Organization: A noiseless patient Spider Lines: 84 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 08:03:20 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="6641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nJrh1ZyDdfeQm2VfY7aiW" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:FpDmeBPZaIRvAtqC5Zw0Il3mAkM= Xref: news.eternal-september.org comp.lang.vhdl:6808 On 7/19/2013 11:38 PM, Gabor wrote: > On 7/19/2013 6:23 PM, Fredxx wrote: >> On 19/07/2013 18:27, lokesh kumar wrote: >>> Hi, >>> >>> Can anyone help me to design a code to square binary number? >>> >>> Suppose "A" is a 5 bit number (a4a3a2a1a0) >>> >>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 >>> a0 " ( a 10 bit number) >> >> All these numbers look bigger than 5 or 10 bits! >> > > The syntax is not VHDL. He means for A to be a 5-bit vector > and the result ended up as: > '0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0) > >>> >>> For example : Suppose A= 11111 >>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for >>> the adding to get the final result). >> >> 31 x 31 = 961 (11 1100 0001) >> >> So clearly XORing is incorrect. >> > > For the OP clearly "multiplication" or "squaring" is incorrect. He > apparently wants a different function that is similar to multiplication > but lacks any carries on the intermediate addition. > >>> Could anyone please help me out how to make a generalized code for >>> squaring of a 5-bit number to get an output like this? >>> >> >> A square operation is precisely that, A * A. Most FPGAs have some >> pretty good multipliers, best to use them. If he is doing a calculation on a polynomial, I understand why he wants a multiply with no carries. Each term of the polynomial has a coefficient which is all the terms of the same value summed together mod 2 (XOR). But I don't understand his other statements. As you showed earlier his general form above for the product is not accurate. Or he is saying something we don't understand. From what I understand (or think I understand) this should be code he could use. subtype binary_num_5 is std_logic_vector (4 downto 0); signal A : binary_num_5; signal B : binary_num_5; function square (arg : std_logic_vector) return std_logic_vector is constant arg_Hi : integer := arg'HIGH; constant arg_Lo : integer := arg'LOW; constant arg_Len : integer := arg'LENGTH; variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) := (others => '0'); begin for i in arg'range loop prod := prod XOR std_logic_vector ( SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); end loop; return prod; end square; ... B <= square (A); I think this will do the job but I haven't tested it, so many errors can be present! If nothing else, it should give a good idea on how to proceed. I will say the whole thing is a little bit simpler if it is done with unsigned type signals rather than std_logic_vector. This would eliminate the type casts in the loop assignment statement. prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); -- Rick From newsfish@newsfish Tue Dec 29 16:43:02 2015 X-Received: by 10.224.171.72 with SMTP id g8mr12447334qaz.7.1374323832785; Sat, 20 Jul 2013 05:37:12 -0700 (PDT) X-Received: by 10.49.3.104 with SMTP id b8mr877721qeb.25.1374323832755; Sat, 20 Jul 2013 05:37:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!u2no169729qao.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no185202qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 05:37:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sat, 20 Jul 2013 12:37:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 6144 Xref: news.eternal-september.org comp.lang.vhdl:6809 On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: > On 7/19/2013 11:38 PM, Gabor wrote: > > > On 7/19/2013 6:23 PM, Fredxx wrote: > > >> On 19/07/2013 18:27, lokesh kumar wrote: > > >>> Hi, > > >>> > > >>> Can anyone help me to design a code to square binary number? > > >>> > > >>> Suppose "A" is a 5 bit number (a4a3a2a1a0) > > >>> > > >>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 > > >>> a0 " ( a 10 bit number) > > >> > > >> All these numbers look bigger than 5 or 10 bits! > > >> > > > > > > The syntax is not VHDL. He means for A to be a 5-bit vector > > > and the result ended up as: > > > '0' & A(4) $ '0' & A(3) $ '0' & A(2) $ '0' & A(1) $ '0' & A(0) > > > > > >>> > > >>> For example : Suppose A= 11111 > > >>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for > > >>> the adding to get the final result). > > >> > > >> 31 x 31 = 961 (11 1100 0001) > > >> > > >> So clearly XORing is incorrect. > > >> > > > > > > For the OP clearly "multiplication" or "squaring" is incorrect. He > > > apparently wants a different function that is similar to multiplication > > > but lacks any carries on the intermediate addition. > > > > > >>> Could anyone please help me out how to make a generalized code for > > >>> squaring of a 5-bit number to get an output like this? > > >>> > > >> > > >> A square operation is precisely that, A * A. Most FPGAs have some > > >> pretty good multipliers, best to use them. > > > > If he is doing a calculation on a polynomial, I understand why he wants > > a multiply with no carries. Each term of the polynomial has a > > coefficient which is all the terms of the same value summed together mod > > 2 (XOR). But I don't understand his other statements. As you showed > > earlier his general form above for the product is not accurate. Or he > > is saying something we don't understand. > > > > From what I understand (or think I understand) this should be code he > > could use. > > > > subtype binary_num_5 is std_logic_vector (4 downto 0); > > signal A : binary_num_5; > > signal B : binary_num_5; > > > > function square (arg : std_logic_vector) return std_logic_vector is > > constant arg_Hi : integer := arg'HIGH; > > constant arg_Lo : integer := arg'LOW; > > constant arg_Len : integer := arg'LENGTH; > > variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) > > := (others => '0'); > > begin > > for i in arg'range loop > > prod := prod XOR std_logic_vector ( > > SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); > > end loop; > > return prod; > > end square; > > > > ... > > > > B <= square (A); > > > > > > I think this will do the job but I haven't tested it, so many errors can > > be present! If nothing else, it should give a good idea on how to > > proceed. I will say the whole thing is a little bit simpler if it is > > done with unsigned type signals rather than std_logic_vector. This > > would eliminate the type casts in the loop assignment statement. > > > > prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); > > > > -- > > > > Rick library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; --use work.my_package.all; entity square_163_7_6_3 is port ( a: in std_logic_vector(162 downto 0); z: out std_logic_vector(162 downto 0) ); end square_163_7_6_3; architecture circuit of square_163_7_6_3 is signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); signal xor1, xor2: std_logic; begin vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate; s(162) <= a(81); vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate; t(7) <= a(82); vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+78); t(2*i + 1) <= a(i+79); end generate; t(162) <= a(159); xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162); u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1; u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1; u(7) <= '0'; u(8) <= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2; u(11) <= '0'; u(12) <= a(86) xor a(162); u(13) <= '0'; vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate; u(162) <= a(161); xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate; xor_gates2: for j in 0 to 162 generate z(j) <= s_plus_t(j) xor u(j); end generate; end circuit; This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? Many Thanks! From newsfish@newsfish Tue Dec 29 16:43:02 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 10:20:20 -0400 Organization: A noiseless patient Spider Lines: 283 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 14:14:42 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="7567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ibLHKq9Kko7BRYJQhioc9" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:AAN1XIV6n31tuVY39MvLBKoDW78= Xref: news.eternal-september.org comp.lang.vhdl:6810 On 7/20/2013 8:37 AM, lokesh kumar wrote: > On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: >> On 7/19/2013 11:38 PM, Gabor wrote: >> >>> On 7/19/2013 6:23 PM, Fredxx wrote: >> >>>> On 19/07/2013 18:27, lokesh kumar wrote: >> >>>>> Hi, >> >>>>> >> >>>>> Can anyone help me to design a code to square binary number? >> >>>>> >> >>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) >> >>>>> >> >>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 >> >>>>> a0 " ( a 10 bit number) >> >>>> >> >>>> All these numbers look bigger than 5 or 10 bits! >> >>>> >> >>> >> >>> The syntax is not VHDL. He means for A to be a 5-bit vector >> >>> and the result ended up as: >> >>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) >> >>> >> >>>>> >> >>>>> For example : Suppose A= 11111 >> >>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for >> >>>>> the adding to get the final result). >> >>>> >> >>>> 31 x 31 = 961 (11 1100 0001) >> >>>> >> >>>> So clearly XORing is incorrect. >> >>>> >> >>> >> >>> For the OP clearly "multiplication" or "squaring" is incorrect. He >> >>> apparently wants a different function that is similar to multiplication >> >>> but lacks any carries on the intermediate addition. >> >>> >> >>>>> Could anyone please help me out how to make a generalized code for >> >>>>> squaring of a 5-bit number to get an output like this? >> >>>>> >> >>>> >> >>>> A square operation is precisely that, A * A. Most FPGAs have some >> >>>> pretty good multipliers, best to use them. >> >> >> >> If he is doing a calculation on a polynomial, I understand why he wants >> a multiply with no carries. Each term of the polynomial has a >> coefficient which is all the terms of the same value summed together mod >> 2 (XOR). But I don't understand his other statements. As you showed >> earlier his general form above for the product is not accurate. Or he >> is saying something we don't understand. >> >> From what I understand (or think I understand) this should be code he >> could use. >> >> subtype binary_num_5 is std_logic_vector (4 downto 0); >> signal A : binary_num_5; >> signal B : binary_num_5; >> >> function square (arg : std_logic_vector) return std_logic_vector is >> constant arg_Hi : integer := arg'HIGH; >> constant arg_Lo : integer := arg'LOW; >> constant arg_Len : integer := arg'LENGTH; >> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) >> := (others => '0'); >> begin >> for i in arg'range loop >> prod := prod XOR std_logic_vector ( >> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); >> end loop; >> return prod; >> end square; >> >> ... >> >> B<= square (A); >> >> >> I think this will do the job but I haven't tested it, so many errors can >> be present! If nothing else, it should give a good idea on how to >> proceed. I will say the whole thing is a little bit simpler if it is >> done with unsigned type signals rather than std_logic_vector. This >> would eliminate the type casts in the loop assignment statement. >> >> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); >> >> -- >> >> Rick > library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; --use work.my_package.all; entity square_163_7_6_3 is port ( a: in std_logic_vector(162 downto 0); z: out std_logic_vector(162 downto 0) ); end square_163_7_6_3; architecture circuit of square_163_7_6_3 is signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); signal xor1, xor2: std_logic; begin vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate; s(162)<= a(81); vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate; t(7) <= a(82); vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+78); t(2*i + 1) <= a(i+79); end generate; t(162) <= a(159); xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162); u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1; u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1; u(7) <= '0'; u(8) <= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2; u(11) <= '0'; u(12) <= a(86) xor a(162); u(13) <= '0'; vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate; u(162)<= a(161); xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate; xor_gates2: for j in 0 to 162 generate z(j)<= s_plus_t(j) xor u(j); end generate; end circuit; > > This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? > > Many Thanks! Hmmm... I don't think I can help you understand the code above. The purpose of the code you posted, or at least how it was derived, is not clear to me. If it helps you any, I have replaced it with a version containing more white space for clarity. Polynomial arithmetic is not my strong suit, but it seems familiar, so I must have done it somewhere, sometime. Maybe it was that class in multivalued logic which was actually a thinly disguised course in abstract algebra taught in the EE department. Or more likely it is just familiar from working with CRC calculations. Here is my take on why you came up with the description of the formula that you did. I am assuming that multiplication is the AND operation and addition is the XOR operation. So '*' really means AND while '+' really means XOR. With that in mind here are some identities... a(n) * a(n) = a(n) a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 a(4 downto 0) is your input and z(8 downto 0) is your output. a4, a3, a2, a1, a0 * a0 a4, a3, a2, a1, a0 * a1 a4, a3, a2, a1, a0 * a2 a4, a3, a2, a1, a0 * a3 a4, a3, a2, a1, a0 * a4 + ---------------------------------- z8, z7, z6, z5, z4, z3, z2, z1, z0 z0 = a0 * a0 = a0 z1 = a0 * a1 + a1 * a0 = 0 z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 z7 = a3 * a4 + a4 * a3 = 0 z8 = a4 * a4 = a4 So this shows (at least for this case) the square of a polynomial *is* represented by the formula you gave at the beginning (which includes one more bit than needed). 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' So here is the code for your square... output_even: for i in 0 to 4 generate z(2*i-1) <= a(i); end generate; output_odd: for i in 0 to 3 generate z(2*i) <= '0'; end generate; Replace the constants with the appropriate parameters and I expect you can make a general function. function poly_square (arg : std_logic_vector) return std_logic_vector is constant arg_Hi : integer := arg'HIGH; constant arg_Lo : integer := arg'LOW; constant arg_Len : integer := arg'LENGTH; variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) := (others => '0'); begin for i in arg'range loop prod(2*(i-arg_Lo)-1) := arg(i); end loop; return prod; end poly_square; ... signal A : std_logic_vector (4 downto 0); signal B : std_logic_vector (8 downto 0); ... B <= poly_square (A); Again, not tested so there are likely errors. -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 11:14:47 -0400 Organization: A noiseless patient Spider Lines: 290 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 15:09:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="23838"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX197RGGNMNZlDxdrMeckwbZd" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:YvjCEduvvKOAo7UJK1dFosAVe00= Xref: news.eternal-september.org comp.lang.vhdl:6811 On 7/20/2013 10:20 AM, rickman wrote: > On 7/20/2013 8:37 AM, lokesh kumar wrote: >> On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: >>> On 7/19/2013 11:38 PM, Gabor wrote: >>> >>>> On 7/19/2013 6:23 PM, Fredxx wrote: >>> >>>>> On 19/07/2013 18:27, lokesh kumar wrote: >>> >>>>>> Hi, >>> >>>>>> >>> >>>>>> Can anyone help me to design a code to square binary number? >>> >>>>>> >>> >>>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) >>> >>>>>> >>> >>>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 >>> >>>>>> a0 " ( a 10 bit number) >>> >>>>> >>> >>>>> All these numbers look bigger than 5 or 10 bits! >>> >>>>> >>> >>>> >>> >>>> The syntax is not VHDL. He means for A to be a 5-bit vector >>> >>>> and the result ended up as: >>> >>>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) >>> >>>> >>> >>>>>> >>> >>>>>> For example : Suppose A= 11111 >>> >>>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for >>> >>>>>> the adding to get the final result). >>> >>>>> >>> >>>>> 31 x 31 = 961 (11 1100 0001) >>> >>>>> >>> >>>>> So clearly XORing is incorrect. >>> >>>>> >>> >>>> >>> >>>> For the OP clearly "multiplication" or "squaring" is incorrect. He >>> >>>> apparently wants a different function that is similar to multiplication >>> >>>> but lacks any carries on the intermediate addition. >>> >>>> >>> >>>>>> Could anyone please help me out how to make a generalized code for >>> >>>>>> squaring of a 5-bit number to get an output like this? >>> >>>>>> >>> >>>>> >>> >>>>> A square operation is precisely that, A * A. Most FPGAs have some >>> >>>>> pretty good multipliers, best to use them. >>> >>> >>> >>> If he is doing a calculation on a polynomial, I understand why he wants >>> a multiply with no carries. Each term of the polynomial has a >>> coefficient which is all the terms of the same value summed together mod >>> 2 (XOR). But I don't understand his other statements. As you showed >>> earlier his general form above for the product is not accurate. Or he >>> is saying something we don't understand. >>> >>> From what I understand (or think I understand) this should be code he >>> could use. >>> >>> subtype binary_num_5 is std_logic_vector (4 downto 0); >>> signal A : binary_num_5; >>> signal B : binary_num_5; >>> >>> function square (arg : std_logic_vector) return std_logic_vector is >>> constant arg_Hi : integer := arg'HIGH; >>> constant arg_Lo : integer := arg'LOW; >>> constant arg_Len : integer := arg'LENGTH; >>> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) >>> := (others => '0'); >>> begin >>> for i in arg'range loop >>> prod := prod XOR std_logic_vector ( >>> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); >>> end loop; >>> return prod; >>> end square; >>> >>> ... >>> >>> B<= square (A); >>> >>> >>> I think this will do the job but I haven't tested it, so many errors can >>> be present! If nothing else, it should give a good idea on how to >>> proceed. I will say the whole thing is a little bit simpler if it is >>> done with unsigned type signals rather than std_logic_vector. This >>> would eliminate the type casts in the loop assignment statement. >>> >>> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); >>> >>> -- >>> >>> Rick >> > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > --use work.my_package.all; > entity square_163_7_6_3 is > port ( > a: in std_logic_vector(162 downto 0); > z: out std_logic_vector(162 downto 0) > ); > end square_163_7_6_3; > > architecture circuit of square_163_7_6_3 is > > signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); > signal xor1, xor2: std_logic; > > begin > > vector_s: for i in 0 to 80 generate > s(2*i)<= a(i); > s(2*i + 1)<= a(i+82); > end generate; > s(162)<= a(81); > > vector_t1: for j in 0 to 6 generate > t(j) <= '0'; > end generate; > t(7) <= a(82); > > vector_t2: for i in 4 to 80 generate > t(2*i) <= a(i+78); > t(2*i + 1) <= a(i+79); > end generate; > t(162) <= a(159); > > xor1 <= a(160) xor a(161); > xor2 <= a(161) xor a(162); > > u(0) <= a(160); > u(1) <= a(160) xor a(162); > u(2) <= a(161); > u(3) <= xor1; > u(4) <= a(82) xor a(160); > u(5) <= xor2; > u(6) <= a(83) xor xor1; > u(7) <= '0'; > u(8) <= a(84) xor xor1; > u(9) <= '0'; > u(10) <= a(85) xor xor2; > u(11) <= '0'; > u(12) <= a(86) xor a(162); > u(13) <= '0'; > vector_u: for i in 7 to 80 generate > u(2*i) <= a(i+80); > u(2*i + 1) <= '0'; > end generate; > u(162)<= a(161); > > xor_gates1: for j in 0 to 162 generate > s_plus_t(j) <= s(j) xor t(j); > end generate; > > xor_gates2: for j in 0 to 162 generate > z(j)<= s_plus_t(j) xor u(j); > end generate; > > end circuit; >> >> This the the exact code I found online, I think. But it is for >> 163-bit. So it is difficult to test and verify. Can you please help me >> to convert it for a 5-bit to make me understand it? >> >> Many Thanks! > > Hmmm... I don't think I can help you understand the code above. The > purpose of the code you posted, or at least how it was derived, is not > clear to me. If it helps you any, I have replaced it with a version > containing more white space for clarity. > > Polynomial arithmetic is not my strong suit, but it seems familiar, so I > must have done it somewhere, sometime. Maybe it was that class in > multivalued logic which was actually a thinly disguised course in > abstract algebra taught in the EE department. Or more likely it is just > familiar from working with CRC calculations. > > Here is my take on why you came up with the description of the formula > that you did. I am assuming that multiplication is the AND operation and > addition is the XOR operation. So '*' really means AND while '+' really > means XOR. > > With that in mind here are some identities... > > a(n) * a(n) = a(n) > a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 > > a(4 downto 0) is your input and z(8 downto 0) is your output. > > a4, a3, a2, a1, a0 * a0 > a4, a3, a2, a1, a0 * a1 > a4, a3, a2, a1, a0 * a2 > a4, a3, a2, a1, a0 * a3 > a4, a3, a2, a1, a0 * a4 > + ---------------------------------- > z8, z7, z6, z5, z4, z3, z2, z1, z0 > > z0 = a0 * a0 = a0 > z1 = a0 * a1 + a1 * a0 = 0 > z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 > z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 > z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 > z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 > z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 > z7 = a3 * a4 + a4 * a3 = 0 > z8 = a4 * a4 = a4 > > So this shows (at least for this case) the square of a polynomial *is* > represented by the formula you gave at the beginning (which includes one > more bit than needed). > > 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' > > So here is the code for your square... > > output_even: for i in 0 to 4 generate > z(2*i-1) <= a(i); > end generate; > > output_odd: for i in 0 to 3 generate > z(2*i) <= '0'; > end generate; Sure enough, there is an error (at least one). I found it by reading my labels... output_even: for i in 0 to 4 generate z(2*i) <= a(i); end generate; output_odd: for i in 0 to 3 generate z(2*i+1) <= '0'; end generate; --- Same error in this code --- function poly_square (arg : std_logic_vector) return std_logic_vector is constant arg_Hi : integer := arg'HIGH; constant arg_Lo : integer := arg'LOW; constant arg_Len : integer := arg'LENGTH; variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) := (others => '0'); begin for i in arg'range loop prod(2*(i-arg_Lo)) := arg(i); end loop; return prod; end poly_square; -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.54.73 with SMTP id p9mr28217107qag.1.1374335178621; Sat, 20 Jul 2013 08:46:18 -0700 (PDT) X-Received: by 10.49.16.163 with SMTP id h3mr912483qed.24.1374335178595; Sat, 20 Jul 2013 08:46:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!u2no182004qao.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no199336qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 08:46:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sat, 20 Jul 2013 15:46:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6812 On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote: > On 7/20/2013 8:37 AM, lokesh kumar wrote: > > > On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: > > >> On 7/19/2013 11:38 PM, Gabor wrote: > > >> > > >>> On 7/19/2013 6:23 PM, Fredxx wrote: > > >> > > >>>> On 19/07/2013 18:27, lokesh kumar wrote: > > >> > > >>>>> Hi, > > >> > > >>>>> > > >> > > >>>>> Can anyone help me to design a code to square binary number? > > >> > > >>>>> > > >> > > >>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) > > >> > > >>>>> > > >> > > >>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 > > >> > > >>>>> a0 " ( a 10 bit number) > > >> > > >>>> > > >> > > >>>> All these numbers look bigger than 5 or 10 bits! > > >> > > >>>> > > >> > > >>> > > >> > > >>> The syntax is not VHDL. He means for A to be a 5-bit vector > > >> > > >>> and the result ended up as: > > >> > > >>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) > > >> > > >>> > > >> > > >>>>> > > >> > > >>>>> For example : Suppose A= 11111 > > >> > > >>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for > > >> > > >>>>> the adding to get the final result). > > >> > > >>>> > > >> > > >>>> 31 x 31 = 961 (11 1100 0001) > > >> > > >>>> > > >> > > >>>> So clearly XORing is incorrect. > > >> > > >>>> > > >> > > >>> > > >> > > >>> For the OP clearly "multiplication" or "squaring" is incorrect. He > > >> > > >>> apparently wants a different function that is similar to multiplication > > >> > > >>> but lacks any carries on the intermediate addition. > > >> > > >>> > > >> > > >>>>> Could anyone please help me out how to make a generalized code for > > >> > > >>>>> squaring of a 5-bit number to get an output like this? > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>> A square operation is precisely that, A * A. Most FPGAs have some > > >> > > >>>> pretty good multipliers, best to use them. > > >> > > >> > > >> > > >> If he is doing a calculation on a polynomial, I understand why he wants > > >> a multiply with no carries. Each term of the polynomial has a > > >> coefficient which is all the terms of the same value summed together mod > > >> 2 (XOR). But I don't understand his other statements. As you showed > > >> earlier his general form above for the product is not accurate. Or he > > >> is saying something we don't understand. > > >> > > >> From what I understand (or think I understand) this should be code he > > >> could use. > > >> > > >> subtype binary_num_5 is std_logic_vector (4 downto 0); > > >> signal A : binary_num_5; > > >> signal B : binary_num_5; > > >> > > >> function square (arg : std_logic_vector) return std_logic_vector is > > >> constant arg_Hi : integer := arg'HIGH; > > >> constant arg_Lo : integer := arg'LOW; > > >> constant arg_Len : integer := arg'LENGTH; > > >> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) > > >> := (others => '0'); > > >> begin > > >> for i in arg'range loop > > >> prod := prod XOR std_logic_vector ( > > >> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); > > >> end loop; > > >> return prod; > > >> end square; > > >> > > >> ... > > >> > > >> B<= square (A); > > >> > > >> > > >> I think this will do the job but I haven't tested it, so many errors can > > >> be present! If nothing else, it should give a good idea on how to > > >> proceed. I will say the whole thing is a little bit simpler if it is > > >> done with unsigned type signals rather than std_logic_vector. This > > >> would eliminate the type casts in the loop assignment statement. > > >> > > >> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); > > >> > > >> -- > > >> > > >> Rick > > > > > library IEEE; > > use IEEE.std_logic_1164.all; > > use IEEE.std_logic_arith.all; > > use IEEE.std_logic_unsigned.all; > > --use work.my_package.all; > > entity square_163_7_6_3 is > > port ( > > a: in std_logic_vector(162 downto 0); > > z: out std_logic_vector(162 downto 0) > > ); > > end square_163_7_6_3; > > > > architecture circuit of square_163_7_6_3 is > > > > signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); > > signal xor1, xor2: std_logic; > > > > begin > > > > vector_s: for i in 0 to 80 generate > > s(2*i)<= a(i); > > s(2*i + 1)<= a(i+82); > > end generate; > > s(162)<= a(81); > > > > vector_t1: for j in 0 to 6 generate > > t(j) <= '0'; > > end generate; > > t(7) <= a(82); > > > > vector_t2: for i in 4 to 80 generate > > t(2*i) <= a(i+78); > > t(2*i + 1) <= a(i+79); > > end generate; > > t(162) <= a(159); > > > > xor1 <= a(160) xor a(161); > > xor2 <= a(161) xor a(162); > > > > u(0) <= a(160); > > u(1) <= a(160) xor a(162); > > u(2) <= a(161); > > u(3) <= xor1; > > u(4) <= a(82) xor a(160); > > u(5) <= xor2; > > u(6) <= a(83) xor xor1; > > u(7) <= '0'; > > u(8) <= a(84) xor xor1; > > u(9) <= '0'; > > u(10) <= a(85) xor xor2; > > u(11) <= '0'; > > u(12) <= a(86) xor a(162); > > u(13) <= '0'; > > vector_u: for i in 7 to 80 generate > > u(2*i) <= a(i+80); > > u(2*i + 1) <= '0'; > > end generate; > > u(162)<= a(161); > > > > xor_gates1: for j in 0 to 162 generate > > s_plus_t(j) <= s(j) xor t(j); > > end generate; > > > > xor_gates2: for j in 0 to 162 generate > > z(j)<= s_plus_t(j) xor u(j); > > end generate; > > > > end circuit; > > > > > > This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? > > > > > > Many Thanks! > > > > Hmmm... I don't think I can help you understand the code above. The > > purpose of the code you posted, or at least how it was derived, is not > > clear to me. If it helps you any, I have replaced it with a version > > containing more white space for clarity. > > > > Polynomial arithmetic is not my strong suit, but it seems familiar, so I > > must have done it somewhere, sometime. Maybe it was that class in > > multivalued logic which was actually a thinly disguised course in > > abstract algebra taught in the EE department. Or more likely it is just > > familiar from working with CRC calculations. > > > > Here is my take on why you came up with the description of the formula > > that you did. I am assuming that multiplication is the AND operation > > and addition is the XOR operation. So '*' really means AND while '+' > > really means XOR. > > > > With that in mind here are some identities... > > > > a(n) * a(n) = a(n) > > a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 > > > > a(4 downto 0) is your input and z(8 downto 0) is your output. > > > > a4, a3, a2, a1, a0 * a0 > > a4, a3, a2, a1, a0 * a1 > > a4, a3, a2, a1, a0 * a2 > > a4, a3, a2, a1, a0 * a3 > > a4, a3, a2, a1, a0 * a4 > > + ---------------------------------- > > z8, z7, z6, z5, z4, z3, z2, z1, z0 > > > > z0 = a0 * a0 = a0 > > z1 = a0 * a1 + a1 * a0 = 0 > > z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 > > z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 > > z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 > > z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 > > z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 > > z7 = a3 * a4 + a4 * a3 = 0 > > z8 = a4 * a4 = a4 > > > > So this shows (at least for this case) the square of a polynomial *is* > > represented by the formula you gave at the beginning (which includes one > > more bit than needed). > > > > 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' > > > > So here is the code for your square... > > > > output_even: for i in 0 to 4 generate > > z(2*i-1) <= a(i); > > end generate; > > > > output_odd: for i in 0 to 3 generate > > z(2*i) <= '0'; > > end generate; > > > > Replace the constants with the appropriate parameters and I expect you > > can make a general function. > > > > function poly_square (arg : std_logic_vector) return std_logic_vector is > > constant arg_Hi : integer := arg'HIGH; > > constant arg_Lo : integer := arg'LOW; > > constant arg_Len : integer := arg'LENGTH; > > variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) > > := (others => '0'); > > begin > > for i in arg'range loop > > prod(2*(i-arg_Lo)-1) := arg(i); > > end loop; > > return prod; > > end poly_square; > > ... > > signal A : std_logic_vector (4 downto 0); > > signal B : std_logic_vector (8 downto 0); > > ... > > B <= poly_square (A); > > > > Again, not tested so there are likely errors. > > > > -- > > > > Rick It is a bit confusing to me. Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it. vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate; s(162) <= a(81); vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate; t(7) <= a(82); vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+78); t(2*i + 1) <= a(i+79); end generate; t(162) <= a(159); For a 163-bit circuit, especially I do not understand this part. So please help me out. Thanks! From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 15:23:23 -0400 Organization: A noiseless patient Spider Lines: 615 Message-ID: References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 19:17:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="1503"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vXd2YxgIlxR9KU0qQlOXv" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> Cancel-Lock: sha1:kpi/12pbgcosHON8HF4zxtO+Ba4= Xref: news.eternal-september.org comp.lang.vhdl:6813 On 7/20/2013 11:46 AM, lokesh kumar wrote: > On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote: >> On 7/20/2013 8:37 AM, lokesh kumar wrote: >> >>> On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: >> >>>> On 7/19/2013 11:38 PM, Gabor wrote: >> >>>> >> >>>>> On 7/19/2013 6:23 PM, Fredxx wrote: >> >>>> >> >>>>>> On 19/07/2013 18:27, lokesh kumar wrote: >> >>>> >> >>>>>>> Hi, >> >>>> >> >>>>>>> >> >>>> >> >>>>>>> Can anyone help me to design a code to square binary number? >> >>>> >> >>>>>>> >> >>>> >> >>>>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) >> >>>> >> >>>>>>> >> >>>> >> >>>>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 >> >>>> >> >>>>>>> a0 " ( a 10 bit number) >> >>>> >> >>>>>> >> >>>> >> >>>>>> All these numbers look bigger than 5 or 10 bits! >> >>>> >> >>>>>> >> >>>> >> >>>>> >> >>>> >> >>>>> The syntax is not VHDL. He means for A to be a 5-bit vector >> >>>> >> >>>>> and the result ended up as: >> >>>> >> >>>>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) >> >>>> >> >>>>> >> >>>> >> >>>>>>> >> >>>> >> >>>>>>> For example : Suppose A= 11111 >> >>>> >> >>>>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for >> >>>> >> >>>>>>> the adding to get the final result). >> >>>> >> >>>>>> >> >>>> >> >>>>>> 31 x 31 = 961 (11 1100 0001) >> >>>> >> >>>>>> >> >>>> >> >>>>>> So clearly XORing is incorrect. >> >>>> >> >>>>>> >> >>>> >> >>>>> >> >>>> >> >>>>> For the OP clearly "multiplication" or "squaring" is incorrect. He >> >>>> >> >>>>> apparently wants a different function that is similar to multiplication >> >>>> >> >>>>> but lacks any carries on the intermediate addition. >> >>>> >> >>>>> >> >>>> >> >>>>>>> Could anyone please help me out how to make a generalized code for >> >>>> >> >>>>>>> squaring of a 5-bit number to get an output like this? >> >>>> >> >>>>>>> >> >>>> >> >>>>>> >> >>>> >> >>>>>> A square operation is precisely that, A * A. Most FPGAs have some >> >>>> >> >>>>>> pretty good multipliers, best to use them. >> >>>> >> >>>> >> >>>> >> >>>> If he is doing a calculation on a polynomial, I understand why he wants >> >>>> a multiply with no carries. Each term of the polynomial has a >> >>>> coefficient which is all the terms of the same value summed together mod >> >>>> 2 (XOR). But I don't understand his other statements. As you showed >> >>>> earlier his general form above for the product is not accurate. Or he >> >>>> is saying something we don't understand. >> >>>> >> >>>> From what I understand (or think I understand) this should be code he >> >>>> could use. >> >>>> >> >>>> subtype binary_num_5 is std_logic_vector (4 downto 0); >> >>>> signal A : binary_num_5; >> >>>> signal B : binary_num_5; >> >>>> >> >>>> function square (arg : std_logic_vector) return std_logic_vector is >> >>>> constant arg_Hi : integer := arg'HIGH; >> >>>> constant arg_Lo : integer := arg'LOW; >> >>>> constant arg_Len : integer := arg'LENGTH; >> >>>> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) >> >>>> := (others => '0'); >> >>>> begin >> >>>> for i in arg'range loop >> >>>> prod := prod XOR std_logic_vector ( >> >>>> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); >> >>>> end loop; >> >>>> return prod; >> >>>> end square; >> >>>> >> >>>> ... >> >>>> >> >>>> B<= square (A); >> >>>> >> >>>> >> >>>> I think this will do the job but I haven't tested it, so many errors can >> >>>> be present! If nothing else, it should give a good idea on how to >> >>>> proceed. I will say the whole thing is a little bit simpler if it is >> >>>> done with unsigned type signals rather than std_logic_vector. This >> >>>> would eliminate the type casts in the loop assignment statement. >> >>>> >> >>>> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); >> >>>> >> >>>> -- >> >>>> >> >>>> Rick >> >>> >> >> library IEEE; >> >> use IEEE.std_logic_1164.all; >> >> use IEEE.std_logic_arith.all; >> >> use IEEE.std_logic_unsigned.all; >> >> --use work.my_package.all; >> >> entity square_163_7_6_3 is >> >> port ( >> >> a: in std_logic_vector(162 downto 0); >> >> z: out std_logic_vector(162 downto 0) >> >> ); >> >> end square_163_7_6_3; >> >> >> >> architecture circuit of square_163_7_6_3 is >> >> >> >> signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); >> >> signal xor1, xor2: std_logic; >> >> >> >> begin >> >> >> >> vector_s: for i in 0 to 80 generate >> >> s(2*i)<= a(i); >> >> s(2*i + 1)<= a(i+82); >> >> end generate; >> >> s(162)<= a(81); >> >> >> >> vector_t1: for j in 0 to 6 generate >> >> t(j)<= '0'; >> >> end generate; >> >> t(7)<= a(82); >> >> >> >> vector_t2: for i in 4 to 80 generate >> >> t(2*i)<= a(i+78); >> >> t(2*i + 1)<= a(i+79); >> >> end generate; >> >> t(162)<= a(159); >> >> >> >> xor1<= a(160) xor a(161); >> >> xor2<= a(161) xor a(162); >> >> >> >> u(0)<= a(160); >> >> u(1)<= a(160) xor a(162); >> >> u(2)<= a(161); >> >> u(3)<= xor1; >> >> u(4)<= a(82) xor a(160); >> >> u(5)<= xor2; >> >> u(6)<= a(83) xor xor1; >> >> u(7)<= '0'; >> >> u(8)<= a(84) xor xor1; >> >> u(9)<= '0'; >> >> u(10)<= a(85) xor xor2; >> >> u(11)<= '0'; >> >> u(12)<= a(86) xor a(162); >> >> u(13)<= '0'; >> >> vector_u: for i in 7 to 80 generate >> >> u(2*i)<= a(i+80); >> >> u(2*i + 1)<= '0'; >> >> end generate; >> >> u(162)<= a(161); >> >> >> >> xor_gates1: for j in 0 to 162 generate >> >> s_plus_t(j)<= s(j) xor t(j); >> >> end generate; >> >> >> >> xor_gates2: for j in 0 to 162 generate >> >> z(j)<= s_plus_t(j) xor u(j); >> >> end generate; >> >> >> >> end circuit; >> >>> >> >>> This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? >> >>> >> >>> Many Thanks! >> >> >> >> Hmmm... I don't think I can help you understand the code above. The >> >> purpose of the code you posted, or at least how it was derived, is not >> >> clear to me. If it helps you any, I have replaced it with a version >> >> containing more white space for clarity. >> >> >> >> Polynomial arithmetic is not my strong suit, but it seems familiar, so I >> >> must have done it somewhere, sometime. Maybe it was that class in >> >> multivalued logic which was actually a thinly disguised course in >> >> abstract algebra taught in the EE department. Or more likely it is just >> >> familiar from working with CRC calculations. >> >> >> >> Here is my take on why you came up with the description of the formula >> >> that you did. I am assuming that multiplication is the AND operation >> >> and addition is the XOR operation. So '*' really means AND while '+' >> >> really means XOR. >> >> >> >> With that in mind here are some identities... >> >> >> >> a(n) * a(n) = a(n) >> >> a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 >> >> >> >> a(4 downto 0) is your input and z(8 downto 0) is your output. >> >> >> >> a4, a3, a2, a1, a0 * a0 >> >> a4, a3, a2, a1, a0 * a1 >> >> a4, a3, a2, a1, a0 * a2 >> >> a4, a3, a2, a1, a0 * a3 >> >> a4, a3, a2, a1, a0 * a4 >> >> + ---------------------------------- >> >> z8, z7, z6, z5, z4, z3, z2, z1, z0 >> >> >> >> z0 = a0 * a0 = a0 >> >> z1 = a0 * a1 + a1 * a0 = 0 >> >> z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 >> >> z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 >> >> z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 >> >> z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 >> >> z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 >> >> z7 = a3 * a4 + a4 * a3 = 0 >> >> z8 = a4 * a4 = a4 >> >> >> >> So this shows (at least for this case) the square of a polynomial *is* >> >> represented by the formula you gave at the beginning (which includes one >> >> more bit than needed). >> >> >> >> 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' >> >> >> >> So here is the code for your square... >> >> >> >> output_even: for i in 0 to 4 generate >> >> z(2*i-1)<= a(i); >> >> end generate; >> >> >> >> output_odd: for i in 0 to 3 generate >> >> z(2*i)<= '0'; >> >> end generate; >> >> >> >> Replace the constants with the appropriate parameters and I expect you >> >> can make a general function. >> >> >> >> function poly_square (arg : std_logic_vector) return std_logic_vector is >> >> constant arg_Hi : integer := arg'HIGH; >> >> constant arg_Lo : integer := arg'LOW; >> >> constant arg_Len : integer := arg'LENGTH; >> >> variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) >> >> := (others => '0'); >> >> begin >> >> for i in arg'range loop >> >> prod(2*(i-arg_Lo)-1) := arg(i); >> >> end loop; >> >> return prod; >> >> end poly_square; >> >> ... >> >> signal A : std_logic_vector (4 downto 0); >> >> signal B : std_logic_vector (8 downto 0); >> >> ... >> >> B<= poly_square (A); >> >> >> >> Again, not tested so there are likely errors. >> >> >> >> -- >> >> >> >> Rick > It is a bit confusing to me. > Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it. > > vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate; > s(162)<= a(81); Do you understand what this code is doing? It is generating the signal s() from the signal a(). Is that clear? > vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate; > t(7)<= a(82); > vector_t2: for i in 4 to 80 generate t(2*i)<= a(i+78); t(2*i + 1)<= a(i+79); end generate; > t(162)<= a(159); This code generates t() from a(). > For a 163-bit circuit, especially I do not understand this part. So please help me out. > Thanks! I don't get it either. What are a(), s(), t() and z()? Is this supposed to be squaring a() to get z()? If so, why is a() the same length as z()? I can't find any of this code using Google. I got your other email which was largely the same as your earlier post I think. I prefer to discuss this here. There may be others who would like to understand this or who can explain it. In fact, you might try explaining what you are doing and ask how to do this in other groups such as comp.dsp. Working from an undocumented code section is not a great way to understand an algorithm. I can't tell you anything about the code you posted. I have no idea why they are doing all the calculations they are doing. I can read the VHDL, but I can't read the mind of the person who wrote it. I might be able to help you figure this out if you give more background. What are you trying to do? What is the bigger picture? There is often more than one way to skin a cat. If I understand what you are trying to do with polynomials I think I have already explained what you need to do to square a() and given you code to do it. If I don't understand, perhaps you can explain better? BTW, when you use Google Groups to post in newsgroups you need to fix your quoted lines. Google Groups adds blank lines between the lines of the quoted material and after a couple of quotes becomes unreadable. -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 20:50:23 +0100 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 19:44:12 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c52eb0a8e8cd1bdd45d93b94f841c8de"; logging-data="9328"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/t4PoPz71gslC+74NIRTig" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: Cancel-Lock: sha1:uT8zBgSNklNYI51XhB60SkXdm+s= Xref: news.eternal-september.org comp.lang.vhdl:6814 On 20/07/2013 20:23, rickman wrote: > On 7/20/2013 11:46 AM, lokesh kumar wrote: >> On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote: >>> On 7/20/2013 8:37 AM, lokesh kumar wrote: >>> Rick >> It is a bit confusing to me. Can I have your email id please? I can >> send you a relevant paper for the circuit with the algorithm. May >> be you will be able to understand it. I am unable to find more >> information related to it. >> >> vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= >> a(i+82); end generate; s(162)<= a(81); > > Do you understand what this code is doing? It is generating the > signal s() from the signal a(). Is that clear? > >> vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate; >> t(7)<= a(82); vector_t2: for i in 4 to 80 generate t(2*i)<= >> a(i+78); t(2*i + 1)<= a(i+79); end generate; t(162)<= a(159); > > This code generates t() from a(). > >> For a 163-bit circuit, especially I do not understand this part. So >> please help me out. Thanks! > > I don't get it either. What are a(), s(), t() and z()? Is this > supposed to be squaring a() to get z()? If so, why is a() the same > length as z()? I can't find any of this code using Google. > > I got your other email which was largely the same as your earlier > post I think. I prefer to discuss this here. There may be others > who would like to understand this or who can explain it. In fact, > you might try explaining what you are doing and ask how to do this in > other groups such as comp.dsp. Working from an undocumented code > section is not a great way to understand an algorithm. > > I can't tell you anything about the code you posted. I have no idea > why they are doing all the calculations they are doing. I can read > the VHDL, but I can't read the mind of the person who wrote it. > > I might be able to help you figure this out if you give more > background. What are you trying to do? What is the bigger picture? > There is often more than one way to skin a cat. If I understand what > you are trying to do with polynomials I think I have already > explained what you need to do to square a() and given you code to do > it. If I don't understand, perhaps you can explain better? > > BTW, when you use Google Groups to post in newsgroups you need to fix > your quoted lines. Google Groups adds blank lines between the lines > of the quoted material and after a couple of quotes becomes > unreadable. > Agreed re Google! This all looks like polynomials to me which are an art in themselves. Without the writers intention it feels we're going to remain in the dark. I confess that whenever I've need a polynomial to calculate or check a CRC, I've used this rather invaluable site: http://www.easics.be/webtools/crctool Perhaps this might give Lokesh some insight? From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.36.15 with SMTP id r15mr29509548qad.8.1374353521586; Sat, 20 Jul 2013 13:52:01 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr891894qeg.5.1374353521558; Sat, 20 Jul 2013 13:52:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!u2no204911qao.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no224999qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 13:52:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sat, 20 Jul 2013 20:52:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1282 Xref: news.eternal-september.org comp.lang.vhdl:6815 On Sunday, July 21, 2013 12:53:23 AM UTC+5:30, rickman wrote: > On 7/20/2013 11:46 AM, lokesh kumar wrote: > > > On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote: > > >> On 7/20/2013 8:37 AM, lokesh kumar wrote: > > >> > > >>> On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: > > >> > > >>>> On 7/19/2013 11:38 PM, Gabor wrote: > > >> > > >>>> > > >> > > >>>>> On 7/19/2013 6:23 PM, Fredxx wrote: > > >> > > >>>> > > >> > > >>>>>> On 19/07/2013 18:27, lokesh kumar wrote: > > >> > > >>>> > > >> > > >>>>>>> Hi, > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> Can anyone help me to design a code to square binary number? > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 > > >> > > >>>> > > >> > > >>>>>>> a0 " ( a 10 bit number) > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> All these numbers look bigger than 5 or 10 bits! > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>> The syntax is not VHDL. He means for A to be a 5-bit vector > > >> > > >>>> > > >> > > >>>>> and the result ended up as: > > >> > > >>>> > > >> > > >>>>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> For example : Suppose A= 11111 > > >> > > >>>> > > >> > > >>>>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for > > >> > > >>>> > > >> > > >>>>>>> the adding to get the final result). > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> 31 x 31 = 961 (11 1100 0001) > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> So clearly XORing is incorrect. > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>> For the OP clearly "multiplication" or "squaring" is incorrect. He > > >> > > >>>> > > >> > > >>>>> apparently wants a different function that is similar to multiplication > > >> > > >>>> > > >> > > >>>>> but lacks any carries on the intermediate addition. > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>>>> Could anyone please help me out how to make a generalized code for > > >> > > >>>> > > >> > > >>>>>>> squaring of a 5-bit number to get an output like this? > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> A square operation is precisely that, A * A. Most FPGAs have some > > >> > > >>>> > > >> > > >>>>>> pretty good multipliers, best to use them. > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> If he is doing a calculation on a polynomial, I understand why he wants > > >> > > >>>> a multiply with no carries. Each term of the polynomial has a > > >> > > >>>> coefficient which is all the terms of the same value summed together mod > > >> > > >>>> 2 (XOR). But I don't understand his other statements. As you showed > > >> > > >>>> earlier his general form above for the product is not accurate. Or he > > >> > > >>>> is saying something we don't understand. > > >> > > >>>> > > >> > > >>>> From what I understand (or think I understand) this should be code he > > >> > > >>>> could use. > > >> > > >>>> > > >> > > >>>> subtype binary_num_5 is std_logic_vector (4 downto 0); > > >> > > >>>> signal A : binary_num_5; > > >> > > >>>> signal B : binary_num_5; > > >> > > >>>> > > >> > > >>>> function square (arg : std_logic_vector) return std_logic_vector is > > >> > > >>>> constant arg_Hi : integer := arg'HIGH; > > >> > > >>>> constant arg_Lo : integer := arg'LOW; > > >> > > >>>> constant arg_Len : integer := arg'LENGTH; > > >> > > >>>> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) > > >> > > >>>> := (others => '0'); > > >> > > >>>> begin > > >> > > >>>> for i in arg'range loop > > >> > > >>>> prod := prod XOR std_logic_vector ( > > >> > > >>>> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); > > >> > > >>>> end loop; > > >> > > >>>> return prod; > > >> > > >>>> end square; > > >> > > >>>> > > >> > > >>>> ... > > >> > > >>>> > > >> > > >>>> B<= square (A); > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> I think this will do the job but I haven't tested it, so many errors can > > >> > > >>>> be present! If nothing else, it should give a good idea on how to > > >> > > >>>> proceed. I will say the whole thing is a little bit simpler if it is > > >> > > >>>> done with unsigned type signals rather than std_logic_vector. This > > >> > > >>>> would eliminate the type casts in the loop assignment statement. > > >> > > >>>> > > >> > > >>>> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); > > >> > > >>>> > > >> > > >>>> -- > > >> > > >>>> > > >> > > >>>> Rick > > >> > > >>> > > >> > > >> library IEEE; > > >> > > >> use IEEE.std_logic_1164.all; > > >> > > >> use IEEE.std_logic_arith.all; > > >> > > >> use IEEE.std_logic_unsigned.all; > > >> > > >> --use work.my_package.all; > > >> > > >> entity square_163_7_6_3 is > > >> > > >> port ( > > >> > > >> a: in std_logic_vector(162 downto 0); > > >> > > >> z: out std_logic_vector(162 downto 0) > > >> > > >> ); > > >> > > >> end square_163_7_6_3; > > >> > > >> > > >> > > >> architecture circuit of square_163_7_6_3 is > > >> > > >> > > >> > > >> signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); > > >> > > >> signal xor1, xor2: std_logic; > > >> > > >> > > >> > > >> begin > > >> > > >> > > >> > > >> vector_s: for i in 0 to 80 generate > > >> > > >> s(2*i)<= a(i); > > >> > > >> s(2*i + 1)<= a(i+82); > > >> > > >> end generate; > > >> > > >> s(162)<= a(81); > > >> > > >> > > >> > > >> vector_t1: for j in 0 to 6 generate > > >> > > >> t(j)<= '0'; > > >> > > >> end generate; > > >> > > >> t(7)<= a(82); > > >> > > >> > > >> > > >> vector_t2: for i in 4 to 80 generate > > >> > > >> t(2*i)<= a(i+78); > > >> > > >> t(2*i + 1)<= a(i+79); > > >> > > >> end generate; > > >> > > >> t(162)<= a(159); > > >> > > >> > > >> > > >> xor1<= a(160) xor a(161); > > >> > > >> xor2<= a(161) xor a(162); > > >> > > >> > > >> > > >> u(0)<= a(160); > > >> > > >> u(1)<= a(160) xor a(162); > > >> > > >> u(2)<= a(161); > > >> > > >> u(3)<= xor1; > > >> > > >> u(4)<= a(82) xor a(160); > > >> > > >> u(5)<= xor2; > > >> > > >> u(6)<= a(83) xor xor1; > > >> > > >> u(7)<= '0'; > > >> > > >> u(8)<= a(84) xor xor1; > > >> > > >> u(9)<= '0'; > > >> > > >> u(10)<= a(85) xor xor2; > > >> > > >> u(11)<= '0'; > > >> > > >> u(12)<= a(86) xor a(162); > > >> > > >> u(13)<= '0'; > > >> > > >> vector_u: for i in 7 to 80 generate > > >> > > >> u(2*i)<= a(i+80); > > >> > > >> u(2*i + 1)<= '0'; > > >> > > >> end generate; > > >> > > >> u(162)<= a(161); > > >> > > >> > > >> > > >> xor_gates1: for j in 0 to 162 generate > > >> > > >> s_plus_t(j)<= s(j) xor t(j); > > >> > > >> end generate; > > >> > > >> > > >> > > >> xor_gates2: for j in 0 to 162 generate > > >> > > >> z(j)<= s_plus_t(j) xor u(j); > > >> > > >> end generate; > > >> > > >> > > >> > > >> end circuit; > > >> > > >>> > > >> > > >>> This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? > > >> > > >>> > > >> > > >>> Many Thanks! > > >> > > >> > > >> > > >> Hmmm... I don't think I can help you understand the code above. The > > >> > > >> purpose of the code you posted, or at least how it was derived, is not > > >> > > >> clear to me. If it helps you any, I have replaced it with a version > > >> > > >> containing more white space for clarity. > > >> > > >> > > >> > > >> Polynomial arithmetic is not my strong suit, but it seems familiar, so I > > >> > > >> must have done it somewhere, sometime. Maybe it was that class in > > >> > > >> multivalued logic which was actually a thinly disguised course in > > >> > > >> abstract algebra taught in the EE department. Or more likely it is just > > >> > > >> familiar from working with CRC calculations. > > >> > > >> > > >> > > >> Here is my take on why you came up with the description of the formula > > >> > > >> that you did. I am assuming that multiplication is the AND operation > > >> > > >> and addition is the XOR operation. So '*' really means AND while '+' > > >> > > >> really means XOR. > > >> > > >> > > >> > > >> With that in mind here are some identities... > > >> > > >> > > >> > > >> a(n) * a(n) = a(n) > > >> > > >> a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 > > >> > > >> > > >> > > >> a(4 downto 0) is your input and z(8 downto 0) is your output. > > >> > > >> > > >> > > >> a4, a3, a2, a1, a0 * a0 > > >> > > >> a4, a3, a2, a1, a0 * a1 > > >> > > >> a4, a3, a2, a1, a0 * a2 > > >> > > >> a4, a3, a2, a1, a0 * a3 > > >> > > >> a4, a3, a2, a1, a0 * a4 > > >> > > >> + ---------------------------------- > > >> > > >> z8, z7, z6, z5, z4, z3, z2, z1, z0 > > >> > > >> > > >> > > >> z0 = a0 * a0 = a0 > > >> > > >> z1 = a0 * a1 + a1 * a0 = 0 > > >> > > >> z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 > > >> > > >> z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 > > >> > > >> z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 > > >> > > >> z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 > > >> > > >> z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 > > >> > > >> z7 = a3 * a4 + a4 * a3 = 0 > > >> > > >> z8 = a4 * a4 = a4 > > >> > > >> > > >> > > >> So this shows (at least for this case) the square of a polynomial *is* > > >> > > >> represented by the formula you gave at the beginning (which includes one > > >> > > >> more bit than needed). > > >> > > >> > > >> > > >> 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' > > >> > > >> > > >> > > >> So here is the code for your square... > > >> > > >> > > >> > > >> output_even: for i in 0 to 4 generate > > >> > > >> z(2*i-1)<= a(i); > > >> > > >> end generate; > > >> > > >> > > >> > > >> output_odd: for i in 0 to 3 generate > > >> > > >> z(2*i)<= '0'; > > >> > > >> end generate; > > >> > > >> > > >> > > >> Replace the constants with the appropriate parameters and I expect you > > >> > > >> can make a general function. > > >> > > >> > > >> > > >> function poly_square (arg : std_logic_vector) return std_logic_vector is > > >> > > >> constant arg_Hi : integer := arg'HIGH; > > >> > > >> constant arg_Lo : integer := arg'LOW; > > >> > > >> constant arg_Len : integer := arg'LENGTH; > > >> > > >> variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) > > >> > > >> := (others => '0'); > > >> > > >> begin > > >> > > >> for i in arg'range loop > > >> > > >> prod(2*(i-arg_Lo)-1) := arg(i); > > >> > > >> end loop; > > >> > > >> return prod; > > >> > > >> end poly_square; > > >> > > >> ... > > >> > > >> signal A : std_logic_vector (4 downto 0); > > >> > > >> signal B : std_logic_vector (8 downto 0); > > >> > > >> ... > > >> > > >> B<= poly_square (A); > > >> > > >> > > >> > > >> Again, not tested so there are likely errors. > > >> > > >> > > >> > > >> -- > > >> > > >> > > >> > > >> Rick > > > It is a bit confusing to me. > > > Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it. > > > > > > vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate; > > > s(162)<= a(81); > > > > Do you understand what this code is doing? It is generating the signal > > s() from the signal a(). Is that clear? > > > > > vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate; > > > t(7)<= a(82); > > > vector_t2: for i in 4 to 80 generate t(2*i)<= a(i+78); t(2*i + 1)<= a(i+79); end generate; > > > t(162)<= a(159); > > > > This code generates t() from a(). > > > > > For a 163-bit circuit, especially I do not understand this part. So please help me out. > > > Thanks! > > > > I don't get it either. What are a(), s(), t() and z()? Is this > > supposed to be squaring a() to get z()? If so, why is a() the same > > length as z()? I can't find any of this code using Google. > > > > I got your other email which was largely the same as your earlier post I > > think. I prefer to discuss this here. There may be others who would > > like to understand this or who can explain it. In fact, you might try > > explaining what you are doing and ask how to do this in other groups > > such as comp.dsp. Working from an undocumented code section is not a > > great way to understand an algorithm. > > > > I can't tell you anything about the code you posted. I have no idea why > > they are doing all the calculations they are doing. I can read the > > VHDL, but I can't read the mind of the person who wrote it. > > > > I might be able to help you figure this out if you give more background. > > What are you trying to do? What is the bigger picture? There is > > often more than one way to skin a cat. If I understand what you are > > trying to do with polynomials I think I have already explained what you > > need to do to square a() and given you code to do it. If I don't > > understand, perhaps you can explain better? > > > > BTW, when you use Google Groups to post in newsgroups you need to fix > > your quoted lines. Google Groups adds blank lines between the lines of > > the quoted material and after a couple of quotes becomes unreadable. > > > > -- > > > > Rick Lets consider a 5 bit number, A = 10100 If we do the squaring of it then we will get, A = 10100 x 10100 ------------- 00000 00000 10100 00000 10100 ------------------- c= 100010000 (XOR operation is performed to add) Now Irreducible polynomial is used to reduce it to 5-bit. (The aim is: if the input is out 5-bit then we need to reduce the output to 5-bit) So for a 5-bit number the irreducible polynomial is , F(x) = x^5 + x^2 + 1 (we can write it in binary form as 100101) (It is a standard value) Now both c and F(x) are added to reduce it to 5-bit. (from the MSB) 100010000 (value of c that we got after the squaring) xor 100101 ( value of F(x) that we calculated) ------------------- 000111000 ( it is not 5-bit) So now again do the xor operation to the result with the irreducible polynomial. 111000 (Do not consider 3 zeros from the left) xor 100101 (irreducible polynomial) --------------- 011101 ( now it is reduced to a 5-bit number,(do not consider the zero at left side)) If you take a close look on the result then, we have taken A = 10100 and we got c = 100010000 (before reduction) so simply we insert one zero between all the bits of A, then we will also get the same result. c = 0 1 0 0 0 1 0 0 0 0 ( zeros are indicated) | | | | | If you remove the indicated zeros then tht value is equal to "A" So now my main aim is to design a generalised code for 5-bit. Suppose I am giving a 5-bit input, A = a4 a3 a2 a1 a0 Then after squaring, I am getting a result C = 0-a4-0-a3-0-a2-0-a1-0-a0 ( zeros are added between all the bits of A) Now I have to use same irreducible polynomial (100101) to reduce it to 5-bit. How can I design this code? Please help me out. Hope everything is clear now. From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.163.14 with SMTP id y14mr17904057qax.3.1374353609785; Sat, 20 Jul 2013 13:53:29 -0700 (PDT) X-Received: by 10.50.4.99 with SMTP id j3mr2019990igj.6.1374353609745; Sat, 20 Jul 2013 13:53:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f1no225130qae.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no225129qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 13:53:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <003cbaf2-921c-4f66-a352-abe2248d1f52@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sat, 20 Jul 2013 20:53:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 19182 Xref: news.eternal-september.org comp.lang.vhdl:6816 On Sunday, July 21, 2013 12:53:23 AM UTC+5:30, rickman wrote: > On 7/20/2013 11:46 AM, lokesh kumar wrote: > > > On Saturday, July 20, 2013 7:50:20 PM UTC+5:30, rickman wrote: > > >> On 7/20/2013 8:37 AM, lokesh kumar wrote: > > >> > > >>> On Saturday, July 20, 2013 1:39:08 PM UTC+5:30, rickman wrote: > > >> > > >>>> On 7/19/2013 11:38 PM, Gabor wrote: > > >> > > >>>> > > >> > > >>>>> On 7/19/2013 6:23 PM, Fredxx wrote: > > >> > > >>>> > > >> > > >>>>>> On 19/07/2013 18:27, lokesh kumar wrote: > > >> > > >>>> > > >> > > >>>>>>> Hi, > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> Can anyone help me to design a code to square binary number? > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> Suppose "A" is a 5 bit number (a4a3a2a1a0) > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> If we do A x A then the output result will be "0 a4 0 a3 0 a2 0 a1 0 > > >> > > >>>> > > >> > > >>>>>>> a0 " ( a 10 bit number) > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> All these numbers look bigger than 5 or 10 bits! > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>> The syntax is not VHDL. He means for A to be a 5-bit vector > > >> > > >>>> > > >> > > >>>>> and the result ended up as: > > >> > > >>>> > > >> > > >>>>> '0'& A(4) $ '0'& A(3) $ '0'& A(2) $ '0'& A(1) $ '0'& A(0) > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>>> For example : Suppose A= 11111 > > >> > > >>>> > > >> > > >>>>>>> Then A x A = 11111 x 11111 = 0101010101 ( Xor operation is done for > > >> > > >>>> > > >> > > >>>>>>> the adding to get the final result). > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> 31 x 31 = 961 (11 1100 0001) > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> So clearly XORing is incorrect. > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>> For the OP clearly "multiplication" or "squaring" is incorrect. He > > >> > > >>>> > > >> > > >>>>> apparently wants a different function that is similar to multiplication > > >> > > >>>> > > >> > > >>>>> but lacks any carries on the intermediate addition. > > >> > > >>>> > > >> > > >>>>> > > >> > > >>>> > > >> > > >>>>>>> Could anyone please help me out how to make a generalized code for > > >> > > >>>> > > >> > > >>>>>>> squaring of a 5-bit number to get an output like this? > > >> > > >>>> > > >> > > >>>>>>> > > >> > > >>>> > > >> > > >>>>>> > > >> > > >>>> > > >> > > >>>>>> A square operation is precisely that, A * A. Most FPGAs have some > > >> > > >>>> > > >> > > >>>>>> pretty good multipliers, best to use them. > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> If he is doing a calculation on a polynomial, I understand why he wants > > >> > > >>>> a multiply with no carries. Each term of the polynomial has a > > >> > > >>>> coefficient which is all the terms of the same value summed together mod > > >> > > >>>> 2 (XOR). But I don't understand his other statements. As you showed > > >> > > >>>> earlier his general form above for the product is not accurate. Or he > > >> > > >>>> is saying something we don't understand. > > >> > > >>>> > > >> > > >>>> From what I understand (or think I understand) this should be code he > > >> > > >>>> could use. > > >> > > >>>> > > >> > > >>>> subtype binary_num_5 is std_logic_vector (4 downto 0); > > >> > > >>>> signal A : binary_num_5; > > >> > > >>>> signal B : binary_num_5; > > >> > > >>>> > > >> > > >>>> function square (arg : std_logic_vector) return std_logic_vector is > > >> > > >>>> constant arg_Hi : integer := arg'HIGH; > > >> > > >>>> constant arg_Lo : integer := arg'LOW; > > >> > > >>>> constant arg_Len : integer := arg'LENGTH; > > >> > > >>>> variable prod : std_logic_vector ((arg_Hi + arg_Len) downto arg_L) > > >> > > >>>> := (others => '0'); > > >> > > >>>> begin > > >> > > >>>> for i in arg'range loop > > >> > > >>>> prod := prod XOR std_logic_vector ( > > >> > > >>>> SHIFT_LEFT (RESIZE (unsigned(arg), 2*arg_Len), i)); > > >> > > >>>> end loop; > > >> > > >>>> return prod; > > >> > > >>>> end square; > > >> > > >>>> > > >> > > >>>> ... > > >> > > >>>> > > >> > > >>>> B<= square (A); > > >> > > >>>> > > >> > > >>>> > > >> > > >>>> I think this will do the job but I haven't tested it, so many errors can > > >> > > >>>> be present! If nothing else, it should give a good idea on how to > > >> > > >>>> proceed. I will say the whole thing is a little bit simpler if it is > > >> > > >>>> done with unsigned type signals rather than std_logic_vector. This > > >> > > >>>> would eliminate the type casts in the loop assignment statement. > > >> > > >>>> > > >> > > >>>> prod := prod XOR SHIFT_LEFT (RESIZE (arg, 2*arg_Len), i)); > > >> > > >>>> > > >> > > >>>> -- > > >> > > >>>> > > >> > > >>>> Rick > > >> > > >>> > > >> > > >> library IEEE; > > >> > > >> use IEEE.std_logic_1164.all; > > >> > > >> use IEEE.std_logic_arith.all; > > >> > > >> use IEEE.std_logic_unsigned.all; > > >> > > >> --use work.my_package.all; > > >> > > >> entity square_163_7_6_3 is > > >> > > >> port ( > > >> > > >> a: in std_logic_vector(162 downto 0); > > >> > > >> z: out std_logic_vector(162 downto 0) > > >> > > >> ); > > >> > > >> end square_163_7_6_3; > > >> > > >> > > >> > > >> architecture circuit of square_163_7_6_3 is > > >> > > >> > > >> > > >> signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); > > >> > > >> signal xor1, xor2: std_logic; > > >> > > >> > > >> > > >> begin > > >> > > >> > > >> > > >> vector_s: for i in 0 to 80 generate > > >> > > >> s(2*i)<= a(i); > > >> > > >> s(2*i + 1)<= a(i+82); > > >> > > >> end generate; > > >> > > >> s(162)<= a(81); > > >> > > >> > > >> > > >> vector_t1: for j in 0 to 6 generate > > >> > > >> t(j)<= '0'; > > >> > > >> end generate; > > >> > > >> t(7)<= a(82); > > >> > > >> > > >> > > >> vector_t2: for i in 4 to 80 generate > > >> > > >> t(2*i)<= a(i+78); > > >> > > >> t(2*i + 1)<= a(i+79); > > >> > > >> end generate; > > >> > > >> t(162)<= a(159); > > >> > > >> > > >> > > >> xor1<= a(160) xor a(161); > > >> > > >> xor2<= a(161) xor a(162); > > >> > > >> > > >> > > >> u(0)<= a(160); > > >> > > >> u(1)<= a(160) xor a(162); > > >> > > >> u(2)<= a(161); > > >> > > >> u(3)<= xor1; > > >> > > >> u(4)<= a(82) xor a(160); > > >> > > >> u(5)<= xor2; > > >> > > >> u(6)<= a(83) xor xor1; > > >> > > >> u(7)<= '0'; > > >> > > >> u(8)<= a(84) xor xor1; > > >> > > >> u(9)<= '0'; > > >> > > >> u(10)<= a(85) xor xor2; > > >> > > >> u(11)<= '0'; > > >> > > >> u(12)<= a(86) xor a(162); > > >> > > >> u(13)<= '0'; > > >> > > >> vector_u: for i in 7 to 80 generate > > >> > > >> u(2*i)<= a(i+80); > > >> > > >> u(2*i + 1)<= '0'; > > >> > > >> end generate; > > >> > > >> u(162)<= a(161); > > >> > > >> > > >> > > >> xor_gates1: for j in 0 to 162 generate > > >> > > >> s_plus_t(j)<= s(j) xor t(j); > > >> > > >> end generate; > > >> > > >> > > >> > > >> xor_gates2: for j in 0 to 162 generate > > >> > > >> z(j)<= s_plus_t(j) xor u(j); > > >> > > >> end generate; > > >> > > >> > > >> > > >> end circuit; > > >> > > >>> > > >> > > >>> This the the exact code I found online, I think. But it is for 163-bit. So it is difficult to test and verify. Can you please help me to convert it for a 5-bit to make me understand it? > > >> > > >>> > > >> > > >>> Many Thanks! > > >> > > >> > > >> > > >> Hmmm... I don't think I can help you understand the code above. The > > >> > > >> purpose of the code you posted, or at least how it was derived, is not > > >> > > >> clear to me. If it helps you any, I have replaced it with a version > > >> > > >> containing more white space for clarity. > > >> > > >> > > >> > > >> Polynomial arithmetic is not my strong suit, but it seems familiar, so I > > >> > > >> must have done it somewhere, sometime. Maybe it was that class in > > >> > > >> multivalued logic which was actually a thinly disguised course in > > >> > > >> abstract algebra taught in the EE department. Or more likely it is just > > >> > > >> familiar from working with CRC calculations. > > >> > > >> > > >> > > >> Here is my take on why you came up with the description of the formula > > >> > > >> that you did. I am assuming that multiplication is the AND operation > > >> > > >> and addition is the XOR operation. So '*' really means AND while '+' > > >> > > >> really means XOR. > > >> > > >> > > >> > > >> With that in mind here are some identities... > > >> > > >> > > >> > > >> a(n) * a(n) = a(n) > > >> > > >> a(n) * a(m) + a(m) * a(n) = a(n) * a(m) + a(n) * a(m) = 0 > > >> > > >> > > >> > > >> a(4 downto 0) is your input and z(8 downto 0) is your output. > > >> > > >> > > >> > > >> a4, a3, a2, a1, a0 * a0 > > >> > > >> a4, a3, a2, a1, a0 * a1 > > >> > > >> a4, a3, a2, a1, a0 * a2 > > >> > > >> a4, a3, a2, a1, a0 * a3 > > >> > > >> a4, a3, a2, a1, a0 * a4 > > >> > > >> + ---------------------------------- > > >> > > >> z8, z7, z6, z5, z4, z3, z2, z1, z0 > > >> > > >> > > >> > > >> z0 = a0 * a0 = a0 > > >> > > >> z1 = a0 * a1 + a1 * a0 = 0 > > >> > > >> z2 = a0 * a2 + a1 * a1 + a2 * a0 = a1 > > >> > > >> z3 = a0 * a3 + a1 * a2 + a2 * a1 + a3 * a0 = 0 > > >> > > >> z4 = a0 * a4 + a1 * a3 + a2 * a2 + a3 * a1 + a4 * a0 = a2 > > >> > > >> z5 = a1 * a4 + a2 * a3 + a3 * a2 + a4 * a1 = 0 > > >> > > >> z6 = a2 * a4 + a3 * a3 + a4 * a2 = a3 > > >> > > >> z7 = a3 * a4 + a4 * a3 = 0 > > >> > > >> z8 = a4 * a4 = a4 > > >> > > >> > > >> > > >> So this shows (at least for this case) the square of a polynomial *is* > > >> > > >> represented by the formula you gave at the beginning (which includes one > > >> > > >> more bit than needed). > > >> > > >> > > >> > > >> 'If we do AxA then the output result will be "0 a4 0 a3 0 a2 0 a1 0 a0"' > > >> > > >> > > >> > > >> So here is the code for your square... > > >> > > >> > > >> > > >> output_even: for i in 0 to 4 generate > > >> > > >> z(2*i-1)<= a(i); > > >> > > >> end generate; > > >> > > >> > > >> > > >> output_odd: for i in 0 to 3 generate > > >> > > >> z(2*i)<= '0'; > > >> > > >> end generate; > > >> > > >> > > >> > > >> Replace the constants with the appropriate parameters and I expect you > > >> > > >> can make a general function. > > >> > > >> > > >> > > >> function poly_square (arg : std_logic_vector) return std_logic_vector is > > >> > > >> constant arg_Hi : integer := arg'HIGH; > > >> > > >> constant arg_Lo : integer := arg'LOW; > > >> > > >> constant arg_Len : integer := arg'LENGTH; > > >> > > >> variable prod : std_logic_vector ((2 * (arg_Len - 1)) downto 0) > > >> > > >> := (others => '0'); > > >> > > >> begin > > >> > > >> for i in arg'range loop > > >> > > >> prod(2*(i-arg_Lo)-1) := arg(i); > > >> > > >> end loop; > > >> > > >> return prod; > > >> > > >> end poly_square; > > >> > > >> ... > > >> > > >> signal A : std_logic_vector (4 downto 0); > > >> > > >> signal B : std_logic_vector (8 downto 0); > > >> > > >> ... > > >> > > >> B<= poly_square (A); > > >> > > >> > > >> > > >> Again, not tested so there are likely errors. > > >> > > >> > > >> > > >> -- > > >> > > >> > > >> > > >> Rick > > > It is a bit confusing to me. > > > Can I have your email id please? I can send you a relevant paper for the circuit with the algorithm. May be you will be able to understand it. I am unable to find more information related to it. > > > > > > vector_s: for i in 0 to 80 generate s(2*i)<= a(i); s(2*i + 1)<= a(i+82); end generate; > > > s(162)<= a(81); > > > > Do you understand what this code is doing? It is generating the signal > > s() from the signal a(). Is that clear? > > > > > vector_t1: for j in 0 to 6 generate t(j)<= '0'; end generate; > > > t(7)<= a(82); > > > vector_t2: for i in 4 to 80 generate t(2*i)<= a(i+78); t(2*i + 1)<= a(i+79); end generate; > > > t(162)<= a(159); > > > > This code generates t() from a(). > > > > > For a 163-bit circuit, especially I do not understand this part. So please help me out. > > > Thanks! > > > > I don't get it either. What are a(), s(), t() and z()? Is this > > supposed to be squaring a() to get z()? If so, why is a() the same > > length as z()? I can't find any of this code using Google. > > > > I got your other email which was largely the same as your earlier post I > > think. I prefer to discuss this here. There may be others who would > > like to understand this or who can explain it. In fact, you might try > > explaining what you are doing and ask how to do this in other groups > > such as comp.dsp. Working from an undocumented code section is not a > > great way to understand an algorithm. > > > > I can't tell you anything about the code you posted. I have no idea why > > they are doing all the calculations they are doing. I can read the > > VHDL, but I can't read the mind of the person who wrote it. > > > > I might be able to help you figure this out if you give more background. > > What are you trying to do? What is the bigger picture? There is > > often more than one way to skin a cat. If I understand what you are > > trying to do with polynomials I think I have already explained what you > > need to do to square a() and given you code to do it. If I don't > > understand, perhaps you can explain better? > > > > BTW, when you use Google Groups to post in newsgroups you need to fix > > your quoted lines. Google Groups adds blank lines between the lines of > > the quoted material and after a couple of quotes becomes unreadable. > > > > -- > > > > Rick Lets consider a 5 bit number, A = 10100 If we do the squaring of it then we will get, A = 10100 x 10100 ------------- 00000 00000 10100 00000 10100 ------------------- c= 100010000 (XOR operation is performed to add) Now Irreducible polynomial is used to reduce it to 5-bit. (The aim is: if the input is out 5-bit then we need to reduce the output to 5-bit) So for a 5-bit number the irreducible polynomial is , F(x) = x^5 + x^2 + 1 (we can write it in binary form as 100101) (It is a standard value) Now both c and F(x) are added to reduce it to 5-bit. (from the MSB) 100010000 (value of c that we got after the squaring) xor 100101 ( value of F(x) that we calculated) ------------------- 000111000 ( it is not 5-bit) So now again do the xor operation to the result with the irreducible polynomial. 111000 (Do not consider 3 zeros from the left) xor 100101 (irreducible polynomial) --------------- 011101 ( now it is reduced to a 5-bit number,(do not consider the zero at left side)) If you take a close look on the result then, we have taken A = 10100 and we got c = 100010000 (before reduction) so simply we insert one zero between all the bits of A, then we will also get the same result. c = 0 1 0 0 0 1 0 0 0 0 ( zeros are indicated) | | | | | If you remove the indicated zeros then tht value is equal to "A" So now my main aim is to design a generalised code for 5-bit. Suppose I am giving a 5-bit input, A = a4 a3 a2 a1 a0 Then after squaring, I am getting a result C = 0-a4-0-a3-0-a2-0-a1-0-a0 ( zeros are added between all the bits of A) Now I have to use same irreducible polynomial (100101) to reduce it to 5-bit. How can I design this code? Please help me out. Hope everything is clear now. From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 18:58:57 -0400 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Jul 2013 22:53:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="2976"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/wcZ6hKrxoZmcq9Vvbcq8j" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:RF5wBhzNR+l6RbvYG5BHSuzjHw0= Xref: news.eternal-september.org comp.lang.vhdl:6817 Ok, we seem to be getting somewhere with this post. I am snipping everything above because it is unreadable due to the Google Groups formatting problems. On 7/20/2013 4:52 PM, lokesh kumar wrote: > > Lets consider a 5 bit number, A = 10100 > > If we do the squaring of it then we will get, > > A = 10100 > x 10100 > ------------- > 00000 > 00000 > 10100 > 00000 > 10100 > ------------------- > c= 100010000 (XOR operation is performed to add) This agrees with what we covered before. > Now Irreducible polynomial is used to reduce it to 5-bit. (The aim is: if the input is out 5-bit then we need to reduce the output to 5-bit) Ah! That's the part that was missing. > So for a 5-bit number the irreducible polynomial is , F(x) = x^5 + x^2 + 1 (we can write it in binary form as 100101) (It is a standard value) > > Now both c and F(x) are added to reduce it to 5-bit. (from the MSB) Is this the same as dividing? I'd like to understand the theory behind this... or maybe not... ;^) lol But seriously, this rings a bell that division and multiplication are similar if not the same in polynomial arithmetic. > > 100010000 (value of c that we got after the squaring) > xor 100101 ( value of F(x) that we calculated) > ------------------- > 000111000 ( it is not 5-bit) > > So now again do the xor operation to the result with the irreducible polynomial. > > > 111000 (Do not consider 3 zeros from the left) > xor 100101 (irreducible polynomial) > --------------- > 011101 ( now it is reduced to a 5-bit number,(do not consider the zero at left side)) > > If you take a close look on the result then, we have taken A = 10100 and we got c = 100010000 (before reduction) > > so simply we insert one zero between all the bits of A, then we will also get the same result. > > c = 0 1 0 0 0 1 0 0 0 0 ( zeros are indicated) > | | | | | Yes, this part actually doesn't require any hardware, just a bit of code to assign different wires. > If you remove the indicated zeros then tht value is equal to "A" > > So now my main aim is to design a generalised code for 5-bit. Suppose I am giving a 5-bit input, A = a4 a3 a2 a1 a0 > > Then after squaring, I am getting a result C = 0-a4-0-a3-0-a2-0-a1-0-a0 ( zeros are added between all the bits of A) > > Now I have to use same irreducible polynomial (100101) to reduce it to 5-bit. > > How can I design this code? Please help me out. Hope everything is clear now. Yes, more or less. Applying the irreducible polynomial (ip) to the result is not hard to do, but the iteration can be done a couple of ways. Is there a way to *know* how many times it must be applied? Obviously this is what the code you provided is doing. I'm guessing there must be some way of knowing how many times the ip must be applied and perhaps even it is always the same number? If so, I can easily generate the code similar to the 163 bit wide solution. If not, the code will have to loop on applying the ip I think. We could have a value of c = 101010101 applying the ip 101010101 100101 - once 001111101 100101 - twice 0110111 100101 - three times 010010 result! This took three iterations and the number is not fixed although I think we can set a max limit at three. So we will need to loop and either exit conditionally or loop for the max count and conditionally execute the XOR. Better, just make the 1's in each ip the value of the msb in the appropriate bit of each intermediate c value. I bet if you dig into the 163 bit version that is what they are doing. I can't figure it out myself. First thing they do is to fold the input vector so the msbs are in the bit positions that would be filled with zeros. Then they generate vectors s, t and u which are all then XOR'd together to produce the output. Do you have a preference about whether this is clocked in a register and takes multiple clock cycles or goes through successive stages of logic without registers or clocks? Any reason to generalize this for N bit wide inputs? I think we have all the pieces now so we could do that as long as we can define the ip for each value of N. Just doing it for N=5 is simpler of course. If you do this normalization on a few test values to make sure it gives the right answer and tell me if you want it as straight logic, registered iteratively or pipelined, I'll give you an implementation. -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.180.37.143 with SMTP id y15mr9383460wij.2.1374364662700; Sat, 20 Jul 2013 16:57:42 -0700 (PDT) X-Received: by 10.49.11.140 with SMTP id q12mr951945qeb.9.1374364662245; Sat, 20 Jul 2013 16:57:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.212.215.MISMATCH!cw2no5040529wib.0!news-out.google.com!md6ni70957wic.0!nntp.google.com!cw2no5040525wib.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 16:57:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sat, 20 Jul 2013 23:57:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6818 Yes, I am also thinking there must be some ways to know about the number of= loops. We can calculate small numbers like 5-bit or 6-bit by using our han= d. But it is very hard to calculate for 163-bit.=20 In your last message you told that, 3 loops are used to reduced. But it is = not correct. After the first loop, you are getting two zeros in the beginni= ng. So we do not need to apply the reduction polynomial value.So the 2nd lo= op is not needed. We can directly consider 1111101 and XOR with 100101 to g= et the 5-bit number. http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/KumarSandeepS/diss.p= df I am quite not sure if you can access this link. If you are unable, then please google "elliptic curve cryptography for cons= trained devices" and check out the first link. On page number 132 (figure 8= .2), the multiplier circuit for 163 bit is given. The reduction polynomial = for 163 bit is, F(x) =3D x^163 + x^7 + x^6 + x^3 +1 So if you closely take a look on the circuit, then you can see that almost = all the parts are similar. But there are 3 extra XOR gates are connected. T= he first extra XOR gate is connected after C2 register ( it is for x^3 whic= h is a part of irreducible polynomial). The second extra XOR gate is connec= ted after C5 register ( for x^6 which is a part of irreducible polynomial) = and the third extra XOR gate is connected after C6 register ( for x^7 term = in the polynomial). The output of C162 is directly connected to the XOR gat= e before C0. Because we do not need to add XOR gates for x^162 and 1.=20 Similarly for a 5-bit number, the reduction polynomial is F(x) =3D x^5 + x^= 2 + 1 So in this case we need to connect only one extra XOR gate after C1 (or bef= ore C0). And the output from c4 is directly connected to the XOR gate befor= e C0. In this case the reduction polynomial is attached. So the result if we take= both A and B are of 5-bit numbers, then we will get the 5-bit number as an= output. This is the basic operation for the multiplier. Now please look at the squaring circuit on page 133 (figure 8.3). I am unab= le to understand the circuit. I am not sure if the reduction polynomial is = attached here. Please have a look on it and let me know if you understand. - Lokesh From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.64.202 with SMTP id f10mr13861361qai.2.1374365063843; Sat, 20 Jul 2013 17:04:23 -0700 (PDT) X-Received: by 10.49.82.50 with SMTP id f18mr918885qey.22.1374365063828; Sat, 20 Jul 2013 17:04:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!f1no239773qae.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no239771qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jul 2013 17:04:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sun, 21 Jul 2013 00:04:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 245 Xref: news.eternal-september.org comp.lang.vhdl:6819 On Sunday, July 21, 2013 4:28:57 AM UTC+5:30, rickman wrote: > Ok, we seem to be getting somewhere with this post. I am snipping > > everything above because it is unreadable due to the Google Groups > > formatting problems. > > > > > > On 7/20/2013 4:52 PM, lokesh kumar wrote: > > > > > > Lets consider a 5 bit number, A = 10100 > > > > > > If we do the squaring of it then we will get, > > > > > > A = 10100 > > > x 10100 > > > ------------- > > > 00000 > > > 00000 > > > 10100 > > > 00000 > > > 10100 > > > ------------------- > > > c= 100010000 (XOR operation is performed to add) > > > > This agrees with what we covered before. > > > > > > > Now Irreducible polynomial is used to reduce it to 5-bit. (The aim is: if the input is out 5-bit then we need to reduce the output to 5-bit) > > > > Ah! That's the part that was missing. > > > > > > > So for a 5-bit number the irreducible polynomial is , F(x) = x^5 + x^2 + 1 (we can write it in binary form as 100101) (It is a standard value) > > > > > > Now both c and F(x) are added to reduce it to 5-bit. (from the MSB) > > > > Is this the same as dividing? I'd like to understand the theory behind > > this... or maybe not... ;^) lol > > > > But seriously, this rings a bell that division and multiplication are > > similar if not the same in polynomial arithmetic. > > > > > > > > > > 100010000 (value of c that we got after the squaring) > > > xor 100101 ( value of F(x) that we calculated) > > > ------------------- > > > 000111000 ( it is not 5-bit) > > > > > > So now again do the xor operation to the result with the irreducible polynomial. > > > > > > > > > 111000 (Do not consider 3 zeros from the left) > > > xor 100101 (irreducible polynomial) > > > --------------- > > > 011101 ( now it is reduced to a 5-bit number,(do not consider the zero at left side)) > > > > > > If you take a close look on the result then, we have taken A = 10100 and we got c = 100010000 (before reduction) > > > > > > so simply we insert one zero between all the bits of A, then we will also get the same result. > > > > > > c = 0 1 0 0 0 1 0 0 0 0 ( zeros are indicated) > > > | | | | | > > > > Yes, this part actually doesn't require any hardware, just a bit of code > > to assign different wires. > > > > > > > If you remove the indicated zeros then tht value is equal to "A" > > > > > > So now my main aim is to design a generalised code for 5-bit. Suppose I am giving a 5-bit input, A = a4 a3 a2 a1 a0 > > > > > > Then after squaring, I am getting a result C = 0-a4-0-a3-0-a2-0-a1-0-a0 ( zeros are added between all the bits of A) > > > > > > Now I have to use same irreducible polynomial (100101) to reduce it to 5-bit. > > > > > > How can I design this code? Please help me out. Hope everything is clear now. > > > > Yes, more or less. Applying the irreducible polynomial (ip) to the > > result is not hard to do, but the iteration can be done a couple of > > ways. Is there a way to *know* how many times it must be applied? > > Obviously this is what the code you provided is doing. I'm guessing > > there must be some way of knowing how many times the ip must be applied > > and perhaps even it is always the same number? If so, I can easily > > generate the code similar to the 163 bit wide solution. If not, the > > code will have to loop on applying the ip I think. > > > > We could have a value of c = 101010101 > > > > applying the ip > > 101010101 > > 100101 - once > > 001111101 > > 100101 - twice > > 0110111 > > 100101 - three times > > 010010 result! > > > > This took three iterations and the number is not fixed although I think > > we can set a max limit at three. So we will need to loop and either > > exit conditionally or loop for the max count and conditionally execute > > the XOR. Better, just make the 1's in each ip the value of the msb in > > the appropriate bit of each intermediate c value. I bet if you dig into > > the 163 bit version that is what they are doing. I can't figure it out > > myself. First thing they do is to fold the input vector so the msbs are > > in the bit positions that would be filled with zeros. Then they > > generate vectors s, t and u which are all then XOR'd together to produce > > the output. > > > > Do you have a preference about whether this is clocked in a register and > > takes multiple clock cycles or goes through successive stages of logic > > without registers or clocks? > > > > Any reason to generalize this for N bit wide inputs? I think we have > > all the pieces now so we could do that as long as we can define the ip > > for each value of N. Just doing it for N=5 is simpler of course. > > > > If you do this normalization on a few test values to make sure it gives > > the right answer and tell me if you want it as straight logic, > > registered iteratively or pipelined, I'll give you an implementation. > > > > -- > > > > Rick I think it is possible. We can use the shift registers and then using the irreducible polynomial. From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 23:24:06 -0400 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Jul 2013 03:18:46 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="29944"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1916knL6FQKxQIaumTnLjvV" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> Cancel-Lock: sha1:TMyeh3GA2eIT/EYyiA8gFI0EdAA= Xref: news.eternal-september.org comp.lang.vhdl:6820 On 7/20/2013 7:57 PM, lokesh kumar wrote: > Yes, I am also thinking there must be some ways to know about the number of loops. We can calculate small numbers like 5-bit or 6-bit by using our hand. But it is very hard to calculate for 163-bit. > > In your last message you told that, 3 loops are used to reduced. But it is not correct. After the first loop, you are getting two zeros in the beginning. So we do not need to apply the reduction polynomial value.So the 2nd loop is not needed. We can directly consider 1111101 and XOR with 100101 to get the 5-bit number. I think you didn't look at my example carefully enough. If a = 11111 then c = 101010101 which is 9 bits. The IP is used once which removes the one in the msb and as you say, the next bit is a zero which is not changed. So we get two bits in the first step. But that still leaves us with a seven bit number and each further application of the IP only removes a single bit from the resulting value of c. > http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/KumarSandeepS/diss.pdf > > I am quite not sure if you can access this link. Yes, I downloaded it and can open it, just not in Acrobat, I have an older copy which won't open this file, I have to use SumatraPDF reader. > If you are unable, then please google "elliptic curve cryptography for constrained devices" and check out the first link. On page number 132 (figure 8..2), the multiplier circuit for 163 bit is given. The reduction polynomial for 163 bit is, F(x) = x^163 + x^7 + x^6 + x^3 +1 I think you mean figure 8.1 on page 132? That is what I am seeing. > So if you closely take a look on the circuit, then you can see that almost all the parts are similar. But there are 3 extra XOR gates are connected. The first extra XOR gate is connected after C2 register ( it is for x^3 which is a part of irreducible polynomial). The second extra XOR gate is connected after C5 register ( for x^6 which is a part of irreducible polynomial) and the third extra XOR gate is connected after C6 register ( for x^7 term in the polynomial). The output of C162 is directly connected to the XOR gate before C0. Because we do not need to add XOR gates for x^162 and 1. > > Similarly for a 5-bit number, the reduction polynomial is F(x) = x^5 + x^2 + 1 > So in this case we need to connect only one extra XOR gate after C1 (or before C0). And the output from c4 is directly connected to the XOR gate before C0. > > In this case the reduction polynomial is attached. So the result if we take both A and B are of 5-bit numbers, then we will get the 5-bit number as an output. > This is the basic operation for the multiplier. > > Now please look at the squaring circuit on page 133 (figure 8.3). I am unable to understand the circuit. I am not sure if the reduction polynomial is attached here. Please have a look on it and let me know if you understand. I assume you mean figure 8.2 on page 133. Sorry, I can follow your directions above, but I understand this less than you do. However, I think there is a lot not shown in Figure 8.2 on page 133. I guess most, if not each output bit has at least one XOR gate. I am guessing that they have manually "unrolled" the loop of the calculation and it distills to a series of XOR gates on each output. In fact, I seem to recall doing exactly that with a CRC computation once. We had to calculate CRC on some 32 bits of input at a time. I took the single bit calculation and applied it 32 times algebraically to produce a fairly messy, but accurate result. We can do that in VHDL without manually calculating the coefficients. We just apply the IP ANDed with the corresponding bit of the temp variable and the calculations will be implemented. So if you want a fully combinatorial circuit like they are describing in the squaring circuit of Figure 8.2 I will write a loop of combinatorial logic. I can only think the complication of the code you provided where they copy other higher order bits into the "zero" bits of c must be a way to simplify the circuit and save the logic of the zero bits. Although things like zero inputs are often optimized automatically in FPGA design tools making this unnecessary. -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Squaring of a binary number Date: Sat, 20 Jul 2013 23:25:35 -0400 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Jul 2013 03:20:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="29944"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IOxcXm46rUOzAjBL++4vN" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> Cancel-Lock: sha1:m9qIlSw00Koah8DGkcf4o6HWh8Y= Xref: news.eternal-september.org comp.lang.vhdl:6821 On 7/20/2013 7:57 PM, lokesh kumar wrote: > > Now please look at the squaring circuit on page 133 (figure 8.3). I am unable to understand the circuit. I am not sure if the reduction polynomial is attached here. Please have a look on it and let me know if you understand. I almost forgot. To test the circuit will require that some examples be provided with solutions. Can you come up with enough examples that testing with those will give you confidence the circuit works correctly? -- Rick From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.36.15 with SMTP id r15mr32558944qad.8.1374402399228; Sun, 21 Jul 2013 03:26:39 -0700 (PDT) X-Received: by 10.49.35.68 with SMTP id f4mr990043qej.0.1374402399208; Sun, 21 Jul 2013 03:26:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!u2no256371qao.0!news-out.google.com!dk8ni860qab.0!nntp.google.com!f1no279851qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Jul 2013 03:26:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Sun, 21 Jul 2013 10:26:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 39 Xref: news.eternal-september.org comp.lang.vhdl:6822 On Sunday, July 21, 2013 8:55:35 AM UTC+5:30, rickman wrote: > On 7/20/2013 7:57 PM, lokesh kumar wrote: >=20 > > >=20 > > Now please look at the squaring circuit on page 133 (figure 8.3). I am = unable to understand the circuit. I am not sure if the reduction polynomial= is attached here. Please have a look on it and let me know if you understa= nd. >=20 >=20 >=20 > I almost forgot. To test the circuit will require that some examples be= =20 >=20 > provided with solutions. Can you come up with enough examples that=20 >=20 > testing with those will give you confidence the circuit works correctly? >=20 >=20 >=20 > --=20 >=20 >=20 >=20 > Rick I think we can start with a small number like a 5-bit number. It would be e= asy to check.But for 163-bit, it is very difficult to check the result.So i= f we get an appropriate result for 5-bit then we can design 163-bit by usin= g the same logic.As per your last message, if you can design a full combina= torial circuit for a 5-bit number by using the squaring circuit of figure 8= .2, then we can check the results with several examples.If the circuit work= s fine then we can proceed for the implementation of 163-bit.=20 We can take the reduction polynomial as F(x)=3D x^5 + x^2 + 1 for a 5-bit = number. --- Lokesh From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.163.14 with SMTP id y14mr25649917qax.3.1374471966788; Sun, 21 Jul 2013 22:46:06 -0700 (PDT) X-Received: by 10.49.1.112 with SMTP id 16mr1012590qel.20.1374471966762; Sun, 21 Jul 2013 22:46:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gh1no36949qab.0!news-out.google.com!dk8ni1022qab.0!nntp.google.com!f1no367686qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Jul 2013 22:46:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <10669e48-5b88-4db9-8e1c-6d6e09892101@googlegroups.com> <20130717092938.697ff2b6@rg.highlandtechnology.com> <12947688-afc4-49c1-b62e-d20c98ad3299@googlegroups.com> <1b23a6a8-80a2-478d-ac51-03db55fbab81@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <91234e61-6b0f-4c02-80b3-948eb3cc3ed3@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: goouse99@gmail.com Injection-Date: Mon, 22 Jul 2013 05:46:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 80 Xref: news.eternal-september.org comp.lang.vhdl:6823 Am Samstag, 20. Juli 2013 00:13:10 UTC+2 schrieb Fredxx: > On 19/07/2013 08:34, goo...@.mail,com wrote: > > > > > > > > > > >> Rick > > > > > > Hi Rick, yes, I've tested all the mentioned examples with ISE 13.4 > > > XST and looked at the technology view to see the result. > > > > > > The last example : wait on Clock2 until rising_edge(Clock) and Clock2 > > > = '1'; --FF with CE surely would give the mentioned mismatch with > > > simulation. But, and that's the point, this is the same as with a > > > process with wrong sensitivity list. The equivalent process would be > > > like this: > > > > > > process(Clock2) is begin if rising_edge(Clock) then if Clock2 = '1' > > > then --the CE Dout <= Din; -- simple Datapath (Register) end if; end > > > if; end process; > > > > > > Synthesis would give a nice FF with CE but simulation would just > > > "trigger" the process on a Clock2 event. > > > > > > I just wanted to check wether synthesis ignores sensitivity lists in > > > wait statements too, or not. > > > > > > > > > I didn't think you could have a sensitivity list to a process using > > "wait" statements. Or should I say Modelsym throws wobblies if you do? Hi Fred, if you carefully read the last postings again or look up the wait-statement syntax you would know what I'm refering to. e.g. here: http://www.nt-nv.fh-koeln.de/Labor/VhdlEnglish/Kap8/k8211.html Of course you can't have: process()... ... wait ... But there is: process is... ... wait on until ... And the last one was being under discussion. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.172.129 with SMTP id l1mr40469508qaz.4.1374517306515; Mon, 22 Jul 2013 11:21:46 -0700 (PDT) X-Received: by 10.49.0.200 with SMTP id 8mr1113843qeg.38.1374517306489; Mon, 22 Jul 2013 11:21:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!cb17no10155qab.0!news-out.google.com!dk8ni1201qab.0!nntp.google.com!cb17no10153qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Jul 2013 11:21:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> <4b6df5f6-f0ba-4dc6-a66f-6423536636c7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <921bda65-2cf8-4546-9a6a-7bd79134ed29@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Mon, 22 Jul 2013 18:21:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6824 Hi Rick, Finally I got the logic properly. And as per your comment I am sending you = some more examples. Please have a look on the logic. ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------------ Example (Part-1) ---------------- Suppose we consider a 5-bit number, A =3D 11010 If we do the square of the number then, AxA =3D 11010 11010 ---------=20 00000 11010 00000 11010 11010 --------------- C=3D 101000100 (9-bit) (XOR operation is performed to add in this case, = NOT the binary addition ) But we can make it a 10-bit number by adding a zero as MSB. Hence we can write, C=3D 0101000100 (Now its a 10-bit number and the value = is not changed) Now if we can obtain the same value of C, only by adding adding zeros betwe= en all the bits of A. In the example, A =3D 11010 So after adding zeros between all the bits, then we will get 1 0 1 0 0 0 1 0 0 | | | | It is the value of C that we calculated earlier. Its of 9-bit. But we can add one extra zero at the MSB to make it 0101000100 ( Now it is = of 10-bits) Or we can directly write =20 0 1 0 1 0 0 0 1 0 0 | | | | | Like this we do not need to multiply A, 2 times if we need to calculate the= square. We can simply add zeros between all the bits of A to get the square. ---------------------------------------------------------------------------= ----- =20 Step-1 (For design) So in general lets take A =3D a4a3a2a1a0 ( 5-bit number) If we take the square of the number, then we will get =20 C =3D c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 ( it is of 10 bit) C =3D 0 a4 0 a3 0 a2 0 a1 0 a0 ( This is how zeros are added and v= alue of C is calculate) ---------------------------------------------------------------------------= -------------------- Example (part-2) ---------------- Now our main aim is to reduce the 10-bit result to 5-bit. For that purpose, we use reduction polynomial (it is a standard value) The reduction polynomial for a 5-bit number is : F(x) =3D x^5 + x^2 + 1 We can write the reduction polynomial as 100101 in binary form. To reduce, 0101000100 (10-bit number, that we obtained) 10101 (reduction polynomial) --------------- 0000010100 (XOR operation) Hence the first five MSB are zero, then if we do not consider these bits. T= hen it is a 5-bit number. It is our final result ---------------------------------------------------------------------------= ----------------------------- Step-2 (For design) The value of reduction polynomial is =3D 100101 We have already got the 10-bit result. We have to do the XOR operation of the 10-bit result with the reduction pol= ynomial in the same way (as shown is the example) For that purpose, we need to see if the MSB of the 10-bit result is "1" or = not. If it is "1" then we will do the XOR operation with the reduction poly= nomial. If the MSB of 10-bit number is zero, then we need to check the second MSB o= f it. If the second MSB is "1" then we need to do the XOR operation there. We need to do this loop till we obtain the 5-bit result. Now this is the final result. ---------------------------------------------------------------------------= ----- I have explained you the logic with an example. I have started with an exam= ple. I have used example (1st part) to show the result after squaring. And = in Step-1, I have described the general logic. In example (part-2) , I have= shown the reduction of the result to 5-bit. And in Step-2, I have provided= the general logic. So basically we need to follow both step-1 and step-2. Now I hope everything is clear. Please help me to design the code for it no= w. Hope this time we will be able to do it. Many Thanks! Lokesh From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.169.1 with SMTP id w1mr149520qay.4.1374520643005; Mon, 22 Jul 2013 12:17:23 -0700 (PDT) X-Received: by 10.49.1.112 with SMTP id 16mr1132057qel.20.1374520642987; Mon, 22 Jul 2013 12:17:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cb17no15727qab.0!news-out.google.com!dk8ni1201qab.0!nntp.google.com!cb17no15722qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Jul 2013 12:17:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <74fdc3ba-4385-49bf-b8a6-904f0df85a35@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <575e0ff7-86a5-455c-a422-3732529d79e9@googlegroups.com> Subject: Re: Squaring of a binary number From: lokesh kumar Injection-Date: Mon, 22 Jul 2013 19:17:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4344 Xref: news.eternal-september.org comp.lang.vhdl:6825 Example (Part-1) ---------------- Suppose we consider a 5-bit number, A = 11010 If we do the square of the number then, AxA = 11010 11010 --------- 00000 11010 00000 11010 11010 --------------- C= 101000100 (9-bit) (XOR operation is performed to add in this case, NOT the binary addition ) But we can make it a 10-bit number by adding a zero as MSB. Hence we can write, C= 0101000100 (Now its a 10-bit number and the value is not changed) Now if we can obtain the same value of C, only by adding adding zeros between all the bits of A. In the example, A = 11010 So after adding zeros between all the bits, then we will get 1 0 1 0 0 0 1 0 0 | | | | It is the value of C that we calculated earlier. Its of 9-bit. But we can add one extra zero at the MSB to make it 0101000100 ( Now it is of 10-bits) Like this we do not need to multiply A, 2 times if we need to calculate the square. We can simply add zeros between all the bits of A to get the square. -------------------------------------------------------------------------------- Step-1 (For design) So in general lets take A = a4a3a2a1a0 ( 5-bit number) If we take the square of the number, then we will get C = c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 ( it is of 10 bit) C = 0 a4 0 a3 0 a2 0 a1 0 a0 ( This is how zeros are added and value of C is calculate) ----------------------------------------------------------------------------------------------- Example (part-2) ---------------- Now our main aim is to reduce the 10-bit result to 5-bit. For that purpose, we use reduction polynomial (it is a standard value) The reduction polynomial for a 5-bit number is : F(x) = x^5 + x^2 + 1 We can write the reduction polynomial as 100101 in binary form. To reduce, 0101000100 (10-bit number, that we obtained) 10101 (reduction polynomial) --------------- 0000010100 (XOR operation) Hence the first five MSB are zero, then if we do not consider these bits. Then it is a 5-bit number. It is our final result -------------------------------------------------------------------------------------------------------- Step-2 (For design) The value of reduction polynomial is = 100101 We have already got the 10-bit result. We have to do the XOR operation of the 10-bit result with the reduction polynomial in the same way (as shown is the example) For that purpose, we need to see if the MSB of the 10-bit result is "1" or not. If it is "1" then we will do the XOR operation with the reduction polynomial. If the MSB of 10-bit number is zero, then we need to check the second MSB of it. If the second MSB is "1" then we need to do the XOR operation there. We need to do this loop till we obtain the 5-bit result. Now this is the final result. How can I design the code? Please help me to implement. Many Thanks! Lokesh From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.54.73 with SMTP id p9mr46662982qag.1.1374606026071; Tue, 23 Jul 2013 12:00:26 -0700 (PDT) X-Received: by 10.49.17.166 with SMTP id p6mr1351798qed.18.1374606026053; Tue, 23 Jul 2013 12:00:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!news.glorb.com!cb17no124851qab.0!news-out.google.com!dk8ni1310qab.0!nntp.google.com!cb17no124849qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Jul 2013 12:00:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> Subject: if statement problem From: lokesh kumar Injection-Date: Tue, 23 Jul 2013 19:00:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6826 How can I use the "if statement"? I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial). If the MSB is zero then I have skip the bit. My main aim is to reduce the 9-bit number to 5-bit. For example: Here m = 5 Loop 1 (2m-2 = 8) 101010100 (MSB is the 9th bit) 100101 --------- x01111100 MSB = 1 (true), XOR with reduction polynomial. Result: 01111100 (8 bit result, removed the 9th bit) Loop 2 (7) 01111100 (MSB is the 8th bit) 100101 -------- MSB = 0 (false), skip and end the loop. Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop) Loop 3 (6) 1111100 (MSB is the 7th bit) 100101 ------- x110110 MSB = 1 (true), XOR with reduction polynomial. Result: 0110110 (7 bit result) Loop 4 (m = 5) 110110 (MSB is the 6th bit) 100101 ------ x10011 (Final result) MSB = 1 (true), XOR with reduction polynomial. Final result: 010011 (6 bit result, but we can discard the MSB) Could you please help me to design the code to give me an idea about "if statement"? Many Thanks! From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: if statement problem Date: Tue, 23 Jul 2013 16:45:17 -0400 Organization: Alacron, Inc. Lines: 59 Message-ID: References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Jul 2013 20:39:08 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9915"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18LzxycDGc2I/GQKNhIX9p2sl6s6aYt7MA=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> Cancel-Lock: sha1:NAg41vT8g+lUZKOh9A0/Ka+8YFc= Xref: news.eternal-september.org comp.lang.vhdl:6827 lokesh kumar wrote: > How can I use the "if statement"? > > I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial). > > If the MSB is zero then I have skip the bit. > > My main aim is to reduce the 9-bit number to 5-bit. > > For example: > Here m = 5 > > Loop 1 (2m-2 = 8) > 101010100 (MSB is the 9th bit) > 100101 > --------- > x01111100 > > MSB = 1 (true), XOR with reduction polynomial. > Result: 01111100 (8 bit result, removed the 9th bit) > > Loop 2 (7) > 01111100 (MSB is the 8th bit) > 100101 > -------- > > MSB = 0 (false), skip and end the loop. > Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop) > > Loop 3 (6) > 1111100 (MSB is the 7th bit) > 100101 > ------- > x110110 > > MSB = 1 (true), XOR with reduction polynomial. > Result: 0110110 (7 bit result) > > Loop 4 (m = 5) > 110110 (MSB is the 6th bit) > 100101 > ------ > x10011 (Final result) > > MSB = 1 (true), XOR with reduction polynomial. > Final result: 010011 (6 bit result, but we can discard the MSB) > > Could you please help me to design the code to give me an idea about "if statement"? > > Many Thanks! Start with a 9-bit vector set to "100000000" then in each loop first AND this with your number and then check for not zero, then shift the 9-bit vector right by 1 (divide by 2). So on the second loop it will become "010000000" on the third loop "001000000", etc. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.224.172.200 with SMTP id m8mr25667387qaz.5.1374614062308; Tue, 23 Jul 2013 14:14:22 -0700 (PDT) X-Received: by 10.49.41.101 with SMTP id e5mr316712qel.7.1374614062293; Tue, 23 Jul 2013 14:14:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!gh1no207810qab.0!news-out.google.com!dk8ni1310qab.0!nntp.google.com!cb17no137611qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Jul 2013 14:14:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: if statement problem From: lokesh kumar Injection-Date: Tue, 23 Jul 2013 21:14:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6828 On Wednesday, July 24, 2013 2:15:17 AM UTC+5:30, Gabor Sz wrote: > lokesh kumar wrote: > > > How can I use the "if statement"? > > > > > > I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial). > > > > > > If the MSB is zero then I have skip the bit. > > > > > > My main aim is to reduce the 9-bit number to 5-bit. > > > > > > For example: > > > Here m = 5 > > > > > > Loop 1 (2m-2 = 8) > > > 101010100 (MSB is the 9th bit) > > > 100101 > > > --------- > > > x01111100 > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > Result: 01111100 (8 bit result, removed the 9th bit) > > > > > > Loop 2 (7) > > > 01111100 (MSB is the 8th bit) > > > 100101 > > > -------- > > > > > > MSB = 0 (false), skip and end the loop. > > > Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop) > > > > > > Loop 3 (6) > > > 1111100 (MSB is the 7th bit) > > > 100101 > > > ------- > > > x110110 > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > Result: 0110110 (7 bit result) > > > > > > Loop 4 (m = 5) > > > 110110 (MSB is the 6th bit) > > > 100101 > > > ------ > > > x10011 (Final result) > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > Final result: 010011 (6 bit result, but we can discard the MSB) > > > > > > Could you please help me to design the code to give me an idea about "if statement"? > > > > > > Many Thanks! > > > > Start with a 9-bit vector set to "100000000" then in each loop > > first AND this with your number and then check for not zero, > > then shift the 9-bit vector right by 1 (divide by 2). So > > on the second loop it will become "010000000" on the third > > loop "001000000", etc. > > > > -- > > Gabor Sorry, did not get you properly. I am a beginner. Could you please help me to implement it? From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.66.252.9 with SMTP id zo9mr6818472pac.28.1374647050674; Tue, 23 Jul 2013 23:24:10 -0700 (PDT) X-Received: by 10.49.64.37 with SMTP id l5mr686322qes.32.1374647050616; Tue, 23 Jul 2013 23:24:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!qx7no52449790pbc.1!news-out.google.com!b2ni84403pby.1!nntp.google.com!ko2no95613488pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Jul 2013 23:24:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> Subject: Re: if statement problem From: goouse99@gmail.com Injection-Date: Wed, 24 Jul 2013 06:24:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6829 Am Dienstag, 23. Juli 2013 23:14:22 UTC+2 schrieb lokesh kumar: > On Wednesday, July 24, 2013 2:15:17 AM UTC+5:30, Gabor Sz wrote: > > > lokesh kumar wrote: > > > > > > > How can I use the "if statement"? > > > > > > > > > > > > > > I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial). > > > > > > > > > > > > > > If the MSB is zero then I have skip the bit. > > > > > > > > > > > > > > My main aim is to reduce the 9-bit number to 5-bit. > > > > > > > > > > > > > > For example: > > > > > > > Here m = 5 > > > > > > > > > > > > > > Loop 1 (2m-2 = 8) > > > > > > > 101010100 (MSB is the 9th bit) > > > > > > > 100101 > > > > > > > --------- > > > > > > > x01111100 > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > Result: 01111100 (8 bit result, removed the 9th bit) > > > > > > > > > > > > > > Loop 2 (7) > > > > > > > 01111100 (MSB is the 8th bit) > > > > > > > 100101 > > > > > > > -------- > > > > > > > > > > > > > > MSB = 0 (false), skip and end the loop. > > > > > > > Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop) > > > > > > > > > > > > > > Loop 3 (6) > > > > > > > 1111100 (MSB is the 7th bit) > > > > > > > 100101 > > > > > > > ------- > > > > > > > x110110 > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > Result: 0110110 (7 bit result) > > > > > > > > > > > > > > Loop 4 (m = 5) > > > > > > > 110110 (MSB is the 6th bit) > > > > > > > 100101 > > > > > > > ------ > > > > > > > x10011 (Final result) > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > Final result: 010011 (6 bit result, but we can discard the MSB) > > > > > > > > > > > > > > Could you please help me to design the code to give me an idea about "if statement"? > > > > > > > > > > > > > > Many Thanks! > > > > > > > > > > > > Start with a 9-bit vector set to "100000000" then in each loop > > > > > > first AND this with your number and then check for not zero, > > > > > > then shift the 9-bit vector right by 1 (divide by 2). So > > > > > > on the second loop it will become "010000000" on the third > > > > > > loop "001000000", etc. > > > > > > > > > > > > -- > > > > > > Gabor > > > > Sorry, did not get you properly. I am a beginner. Could you please help me to implement it? Hi Lokesh, if you need work to be done, hire someone. People here will give you hints and tips if you get stuck with some problem, but they won't do (your) work for free. (They are mostly busy with their own stuff) The other option is to learn the things for yourself, but you should begin with something simple and not so complicated mathematical problems. First focus on the HDL, and once you have mastered it you can focus on the complex problems. So you either have to spend money or time, which is said to be equivalent. Kind regards Eilert From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.66.144.37 with SMTP id sj5mr7508201pab.23.1374659000600; Wed, 24 Jul 2013 02:43:20 -0700 (PDT) X-Received: by 10.49.71.173 with SMTP id w13mr1417594qeu.21.1374659000531; Wed, 24 Jul 2013 02:43:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!qx7no52724870pbc.1!news-out.google.com!b2ni84402pby.1!nntp.google.com!qx7no52724866pbc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 02:43:20 -0700 (PDT) In-Reply-To: <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3be5b173-8210-4910-b251-36180fac9efd@googlegroups.com> Subject: Re: if statement problem From: lokesh kumar Injection-Date: Wed, 24 Jul 2013 09:43:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 532 Xref: news.eternal-september.org comp.lang.vhdl:6830 On Wednesday, July 24, 2013 11:54:10 AM UTC+5:30, goou...@gmail.com wrote: > Am Dienstag, 23. Juli 2013 23:14:22 UTC+2 schrieb lokesh kumar: >=20 > > On Wednesday, July 24, 2013 2:15:17 AM UTC+5:30, Gabor Sz wrote: >=20 > >=20 >=20 > > > lokesh kumar wrote: >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > How can I use the "if statement"? >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > I have a 9-bit number. I need to check the MSB. If the MSB is "1" t= hen I have to do the XOR operation with "100101" (reduction polynomial). >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > If the MSB is zero then I have skip the bit. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > My main aim is to reduce the 9-bit number to 5-bit. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > For example: >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Here m =3D 5 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Loop 1 (2m-2 =3D 8) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 101010100 (MSB is the 9th bit) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 100101 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > --------- >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > x01111100 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > MSB =3D 1 (true), XOR with reduction polynomial. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Result: 01111100 (8 bit result, removed the 9th bit) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Loop 2 (7) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 01111100 (MSB is the 8th bit) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 100101 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > -------- >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > MSB =3D 0 (false), skip and end the loop. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Result: 01111100 (still 8 bit result, but we are not using the MSB = for the next loop) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Loop 3 (6) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 1111100 (MSB is the 7th bit) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 100101 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > ------- >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > x110110 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > MSB =3D 1 (true), XOR with reduction polynomial. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Result: 0110110 (7 bit result) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Loop 4 (m =3D 5) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 110110 (MSB is the 6th bit) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > 100101 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > ------ >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > x10011 (Final result) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > MSB =3D 1 (true), XOR with reduction polynomial. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Final result: 010011 (6 bit result, but we can discard the MSB) >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Could you please help me to design the code to give me an idea abou= t "if statement"? >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > > Many Thanks! >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > Start with a 9-bit vector set to "100000000" then in each loop >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > first AND this with your number and then check for not zero, >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > then shift the 9-bit vector right by 1 (divide by 2). So >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > on the second loop it will become "010000000" on the third >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > loop "001000000", etc. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > --=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > Gabor >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Sorry, did not get you properly. I am a beginner. Could you please help= me to implement it? >=20 >=20 >=20 > Hi Lokesh, >=20 > if you need work to be done, hire someone. >=20 > People here will give you hints and tips if you get stuck with some probl= em, but they won't do (your) work for free. (They are mostly busy with thei= r own stuff) >=20 >=20 >=20 > The other option is to learn the things for yourself, but you should begi= n with something simple and not so complicated mathematical problems. First= focus on the HDL, and once you have mastered it you can focus on the compl= ex problems. >=20 >=20 >=20 > So you either have to spend money or time, which is said to be equivalent= . >=20 >=20 >=20 > Kind regards >=20 > Eilert I did not force anyone to do the code either. I know you are right. But thi= ng is that it is not always possible to solve the problem just by reading t= he books. Its a part of my project and I need to finish by the end of this = month. Hiring someone for it, is not a big deal. But I want to learn someth= ing.As a computer science student, I do not have much idea about VHDL codin= g. And it 2 months are not enough to learn everything in VHDL. So I posted = my query here, believing that someone might reply to it. There are a lot of= people who have passion about programming and they love to solve the probl= ems. May be not like you, who just can give a hint or something. Sometimes = the hints are not enough. I have been trying, still I am unable to solve th= e query. After all the query is not directly related to my project because = it is difficult to put all the details of my project here. I wanted to know= how the implementation is going on, So that I can relate it to my original= project. Some people have time to log on to the group, reading questions and giving = the hints. But I would suggest they should reply to the appropriate questio= n what they can answer. Regards From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.68.202.3 with SMTP id ke3mr7354255pbc.5.1374659188727; Wed, 24 Jul 2013 02:46:28 -0700 (PDT) X-Received: by 10.49.99.65 with SMTP id eo1mr275986qeb.3.1374659188630; Wed, 24 Jul 2013 02:46:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!qx7no52729263pbc.1!news-out.google.com!b2ni84403pby.1!nntp.google.com!ko2no95892083pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 02:46:28 -0700 (PDT) In-Reply-To: <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> Subject: Re: if statement problem From: lokesh kumar Injection-Date: Wed, 24 Jul 2013 09:46:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6831 On Wednesday, July 24, 2013 11:54:10 AM UTC+5:30, goou...@gmail.com wrote: > Am Dienstag, 23. Juli 2013 23:14:22 UTC+2 schrieb lokesh kumar: > > > On Wednesday, July 24, 2013 2:15:17 AM UTC+5:30, Gabor Sz wrote: > > > > > > > lokesh kumar wrote: > > > > > > > > > > > > > > > How can I use the "if statement"? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I have a 9-bit number. I need to check the MSB. If the MSB is "1" then I have to do the XOR operation with "100101" (reduction polynomial). > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > If the MSB is zero then I have skip the bit. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > My main aim is to reduce the 9-bit number to 5-bit. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > For example: > > > > > > > > > > > > > > > Here m = 5 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Loop 1 (2m-2 = 8) > > > > > > > > > > > > > > > 101010100 (MSB is the 9th bit) > > > > > > > > > > > > > > > 100101 > > > > > > > > > > > > > > > --------- > > > > > > > > > > > > > > > x01111100 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > > > > > > > > > Result: 01111100 (8 bit result, removed the 9th bit) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Loop 2 (7) > > > > > > > > > > > > > > > 01111100 (MSB is the 8th bit) > > > > > > > > > > > > > > > 100101 > > > > > > > > > > > > > > > -------- > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > MSB = 0 (false), skip and end the loop. > > > > > > > > > > > > > > > Result: 01111100 (still 8 bit result, but we are not using the MSB for the next loop) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Loop 3 (6) > > > > > > > > > > > > > > > 1111100 (MSB is the 7th bit) > > > > > > > > > > > > > > > 100101 > > > > > > > > > > > > > > > ------- > > > > > > > > > > > > > > > x110110 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > > > > > > > > > Result: 0110110 (7 bit result) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Loop 4 (m = 5) > > > > > > > > > > > > > > > 110110 (MSB is the 6th bit) > > > > > > > > > > > > > > > 100101 > > > > > > > > > > > > > > > ------ > > > > > > > > > > > > > > > x10011 (Final result) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > MSB = 1 (true), XOR with reduction polynomial. > > > > > > > > > > > > > > > Final result: 010011 (6 bit result, but we can discard the MSB) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Could you please help me to design the code to give me an idea about "if statement"? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Many Thanks! > > > > > > > > > > > > > > > > > > > > > > > > > > > > Start with a 9-bit vector set to "100000000" then in each loop > > > > > > > > > > > > > > first AND this with your number and then check for not zero, > > > > > > > > > > > > > > then shift the 9-bit vector right by 1 (divide by 2). So > > > > > > > > > > > > > > on the second loop it will become "010000000" on the third > > > > > > > > > > > > > > loop "001000000", etc. > > > > > > > > > > > > > > > > > > > > > > > > > > > > -- > > > > > > > > > > > > > > Gabor > > > > > > > > > > > > Sorry, did not get you properly. I am a beginner. Could you please help me to implement it? > > > > Hi Lokesh, > > if you need work to be done, hire someone. > > People here will give you hints and tips if you get stuck with some problem, but they won't do (your) work for free. (They are mostly busy with their own stuff) > > > > The other option is to learn the things for yourself, but you should begin with something simple and not so complicated mathematical problems. First focus on the HDL, and once you have mastered it you can focus on the complex problems. > > > > So you either have to spend money or time, which is said to be equivalent. > > > > Kind regards > > Eilert Eliert: I would say please do not post any comment on anyone's profile (who really wants to learn something) if you really can not help him.It is disappointing. From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Fredxx Newsgroups: comp.lang.vhdl Subject: Re: if statement problem Date: Wed, 24 Jul 2013 11:04:51 +0100 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <3be5b173-8210-4910-b251-36180fac9efd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Jul 2013 09:58:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c52eb0a8e8cd1bdd45d93b94f841c8de"; logging-data="29984"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xeiOCZQXzntatBWiqCSDv" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <3be5b173-8210-4910-b251-36180fac9efd@googlegroups.com> Cancel-Lock: sha1:2XHHjdW9HY2JS6MGZSyTpvTHMWI= Xref: news.eternal-september.org comp.lang.vhdl:6832 On 24/07/2013 10:43, lokesh kumar wrote: > I did not force anyone to do the code either. I know you are right. > But thing is that it is not always possible to solve the problem just > by reading the books. Its a part of my project and I need to finish > by the end of this month. Hiring someone for it, is not a big deal. > But I want to learn something.As a computer science student, I do not > have much idea about VHDL coding. And it 2 months are not enough to > learn everything in VHDL. So I posted my query here, believing that > someone might reply to it. There are a lot of people who have passion > about programming and they love to solve the problems. May be not > like you, who just can give a hint or something. Sometimes the hints > are not enough. I have been trying, still I am unable to solve the > query. After all the query is not directly related to my project > because it is difficult to put all the details of my project here. I > wanted to know how the implementation is going on, So that I can > relate it to my original project. > > Some people have time to log on to the group, reading questions and > giving the hints. But I would suggest they should reply to the > appropriate question what they can answer. > > Regards > I learnt VHDL the hard way, and I still have to lookup old designs for reference. There is much example VHDL on the net and there is also Ashenden's cookbook on the 'net to give you ideas of what you can do. Good luck, it seems you have much to do in the next week. From newsfish@newsfish Tue Dec 29 16:43:03 2015 X-Received: by 10.66.150.164 with SMTP id uj4mr8409483pab.19.1374683647827; Wed, 24 Jul 2013 09:34:07 -0700 (PDT) X-Received: by 10.49.40.167 with SMTP id y7mr1491051qek.36.1374683647586; Wed, 24 Jul 2013 09:34:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!qx7no53397156pbc.1!news-out.google.com!b2ni87844pby.1!nntp.google.com!cb17no147660qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 09:34:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> Subject: Conditional Compile Generate statements From: Cory Shol Injection-Date: Wed, 24 Jul 2013 16:34:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6833 I have a project that Two FPGA's use the same VHDL code. I have a Global constant that if: SIDE_DEFINE = '0' it will compile FPGA one logic. SIDE_DEFINE = '1' it will compile FPGA two logic. Can I instantiate multiple components in a single generate? i.e. generate_FPGA1 : if(SIDE_DEFINE='0') generate comp1 : component_one port map( clk => clk1, input => input1, output => output1 ); comp2 : component_2 port map( clk => clk2, input => input2, output => output2 ); end generate generate_FPGA1; generate_FPGA1 : if(SIDE_DEFINE='1') generate comp1 : component_one port map( clk => clk2, input => input2, output => output2 ); comp2 : component_2 port map( clk => clk1, input => input1, output => output1 ); end generate generate_FPGA1; or do i have to: generate_FPGA1_comp1 : if(SIDE_DEFINE='0') generate comp1 : component_one port map( clk => clk1, input => input1, output => output1 ); end generate generate_FPGA1_comp1; generate_FPGA1_comp2 : if(SIDE_DEFINE='0') generate comp2 : component_2 port map( clk => clk2, input => input2, output => output2 ); end generate generate_FPGA1_comp2; Thanks From newsfish@newsfish Tue Dec 29 16:43:03 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Wed, 24 Jul 2013 18:51:56 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: if statement problem References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 11 Message-ID: <51f00628$0$2411$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 24 Jul 2013 18:51:52 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1374684712 news-3.free.fr 2411 88.185.146.198:1146 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:6834 Le 23/07/2013 23:14, lokesh kumar wrote (but he quoted a lot of stuff and empty lines before) : > Sorry, did not get you properly. I am a beginner. Could you please help me to implement it? It would be realy nice if you trimmed your posts so that readers wouldn't have to scroll several pages to read the one sentence you've added at the bottom Nicolas From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!transit3.readnews.com!news-out.readnews.com!s09-01.readnews.com!not-for-mail X-Trace: DXC=4K;DWHlk>F2_c:Yg62n9f<@lWf8?fSK:1jS@R6]oDiI?[j;g`C24>V;o=iH@LQP`98mQ`SH?2Y?:4h_SaT7FPI;Y6?]07= X-Complaints-To: abuse@gradwell.net Date: Wed, 24 Jul 2013 18:17:00 +0100 From: Andy Botterill User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: if statement problem References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> In-Reply-To: <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 15 Message-ID: <51f00c0c$0$26779$862e30e2@ngroups.net> NNTP-Posting-Host: f63969db.ngroups.net Xref: news.eternal-september.org comp.lang.vhdl:6835 On 07/24/2013 10:46 AM, lokesh kumar wrote: > On Wednesday, July 24, 2013 11:54:10 AM UTC+5:30, goou...@gmail.com wrote: > > Eliert: I would say please do not post any comment on anyone's profile (who really wants to learn something) if you really can not help him.It is disappointing. lokesh You say you are trying to learn. Post the code you have written and say where you are stuck. It is unfair and unreasonable to expect someone else to do your work for you. Andy > From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.66.155.227 with SMTP id vz3mr7275751pab.13.1374686613543; Wed, 24 Jul 2013 10:23:33 -0700 (PDT) X-Received: by 10.49.101.34 with SMTP id fd2mr1511112qeb.12.1374686613306; Wed, 24 Jul 2013 10:23:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!qx7no53480421pbc.1!news-out.google.com!b2ni87844pby.1!nntp.google.com!cb17no148701qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 10:23:33 -0700 (PDT) In-Reply-To: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> Subject: Re: Conditional Compile Generate statements From: Andy Injection-Date: Wed, 24 Jul 2013 17:23:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6836 A generate statement may contain any number of concurrent statements: compo= nent/entity instantiations, concurrent signal assignment statements, proces= s statements, etc. BTW, the VHDL generate statement does not accomplish "conditional compilati= on". The contained statements are always compiled, but if the conditional i= s false, they are not elaborated (in SW terms, they are not "linked"). Any = statements must be legal VHDL, and all referenced objects must exist. If your tools support vhdl-2008, enhanced generate statements are available= :=20 You can now include "else generate" and "elsif generate" in if-= generate statements.=20 "Case generate ... end generate;" is also available.=20 Consult your tools' reference guides to see what vhdl-2008 features are sup= ported. If a 2008 feature you want to use is not supported, then let your v= endor(s) know you want it!=20 Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.66.144.37 with SMTP id sj5mr7897521pab.23.1374687448608; Wed, 24 Jul 2013 10:37:28 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr1445195qeg.5.1374687448371; Wed, 24 Jul 2013 10:37:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!ko2no96663836pbb.0!news-out.google.com!b2ni87844pby.1!nntp.google.com!cb17no148986qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 10:37:28 -0700 (PDT) In-Reply-To: <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> Subject: Re: Conditional Compile Generate statements From: Cory Shol Injection-Date: Wed, 24 Jul 2013 17:37:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6837 On Wednesday, July 24, 2013 12:23:33 PM UTC-5, Andy wrote: > A generate statement may contain any number of concurrent statements: com= ponent/entity instantiations, concurrent signal assignment statements, proc= ess statements, etc. >=20 >=20 >=20 > BTW, the VHDL generate statement does not accomplish "conditional compila= tion". The contained statements are always compiled, but if the conditional= is false, they are not elaborated (in SW terms, they are not "linked"). An= y statements must be legal VHDL, and all referenced objects must exist. >=20 >=20 >=20 > If your tools support vhdl-2008, enhanced generate statements are availab= le:=20 >=20 >=20 >=20 > You can now include "else generate" and "elsif generate" in i= f-generate statements.=20 >=20 >=20 >=20 > "Case generate ... end generate;" is also available.=20 >=20 >=20 >=20 > Consult your tools' reference guides to see what vhdl-2008 features are s= upported. If a 2008 feature you want to use is not supported, then let your= vendor(s) know you want it!=20 >=20 >=20 >=20 > Andy If SIDE_DEFINE is a constant, will the tools compile out the unused logic??= =20 If you have two generate and one will never be true since the constant is i= nitialized, the tools should never include the logic in the final design th= erefore isn't it a conditional compile?? From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.66.248.129 with SMTP id ym1mr1819634pac.6.1374687523705; Wed, 24 Jul 2013 10:38:43 -0700 (PDT) X-Received: by 10.182.105.165 with SMTP id gn5mr427946obb.27.1374687523375; Wed, 24 Jul 2013 10:38:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!ko2no96666096pbb.0!news-out.google.com!b2ni87844pby.1!nntp.google.com!cb17no149008qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 10:38:42 -0700 (PDT) In-Reply-To: <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5094b50b-fdb7-497a-ab5a-bc4be32142bc@googlegroups.com> Subject: Re: Conditional Compile Generate statements From: Cory Shol Injection-Date: Wed, 24 Jul 2013 17:38:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6838 On Wednesday, July 24, 2013 12:37:28 PM UTC-5, Cory Shol wrote: > On Wednesday, July 24, 2013 12:23:33 PM UTC-5, Andy wrote: >=20 > > A generate statement may contain any number of concurrent statements: c= omponent/entity instantiations, concurrent signal assignment statements, pr= ocess statements, etc. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > BTW, the VHDL generate statement does not accomplish "conditional compi= lation". The contained statements are always compiled, but if the condition= al is false, they are not elaborated (in SW terms, they are not "linked"). = Any statements must be legal VHDL, and all referenced objects must exist. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > If your tools support vhdl-2008, enhanced generate statements are avail= able:=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > You can now include "else generate" and "elsif generate" in= if-generate statements.=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > "Case generate ... end generate;" is also available.=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Consult your tools' reference guides to see what vhdl-2008 features are= supported. If a 2008 feature you want to use is not supported, then let yo= ur vendor(s) know you want it!=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Andy >=20 >=20 >=20 > If SIDE_DEFINE is a constant, will the tools compile out the unused logic= ??=20 >=20 >=20 >=20 > If you have two generate and one will never be true since the constant is= initialized, the tools should never include the logic in the final design = therefore isn't it a conditional compile?? How else do you do a conditional compile in VHDL? From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.66.121.169 with SMTP id ll9mr8502520pab.38.1374689836353; Wed, 24 Jul 2013 11:17:16 -0700 (PDT) X-Received: by 10.49.81.208 with SMTP id c16mr131881qey.34.1374689836081; Wed, 24 Jul 2013 11:17:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!qx7no53571393pbc.1!news-out.google.com!b2ni87844pby.1!nntp.google.com!cb17no149710qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 11:17:15 -0700 (PDT) In-Reply-To: <51f00c0c$0$26779$862e30e2@ngroups.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> <51f00c0c$0$26779$862e30e2@ngroups.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> Subject: Re: if statement problem From: lokesh kumar Injection-Date: Wed, 24 Jul 2013 18:17:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6839 for i in 8 downto 5 loop if b(i) = '1' then (temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101"; else if b(i) = '0'; null; end if; end loop; c <= (temp(4) downto temp(0)); -------- This is the code that I tried to write. But I am getting some unexpected errors. could anyone please help me out with it? From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: if statement problem Date: Wed, 24 Jul 2013 23:03:21 +0200 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> <51f00c0c$0$26779$862e30e2@ngroups.net> <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Jul 2013 20:57:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="cbcd9919a45968926335024bf65e2b8d"; logging-data="27444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/2iv5edMmYvVu3alQi8M3r" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130509 Thunderbird/17.0.6 In-Reply-To: <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> Cancel-Lock: sha1:ra+5d20kUDH0fL+loSIsAEgr2Tk= Xref: news.eternal-september.org comp.lang.vhdl:6840 Am 24.07.13 20:17, schrieb lokesh kumar: > for i in 8 downto 5 loop > if b(i) = '1' then > (temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101"; > else if b(i) = '0'; > null; > end if; > end loop; > c <= (temp(4) downto temp(0)); $ ghdl -a test.vhd test.vhd:1:2: entity, architecture, package or configuration keyword expected test.vhd:1:2: design file is empty (no design unit found) There's a lot missing on your code. My vhdl code start with 'library ieee' and ends with 'end architechture' regards, Bart From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.54.73 with SMTP id p9mr53031611qag.1.1374707050754; Wed, 24 Jul 2013 16:04:10 -0700 (PDT) X-Received: by 10.49.1.6 with SMTP id 6mr835782qei.8.1374707050517; Wed, 24 Jul 2013 16:04:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gh1no230380qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no164066qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 16:04:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> <51f00c0c$0$26779$862e30e2@ngroups.net> <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <283d00b6-af51-4a80-a075-21233d37327a@googlegroups.com> Subject: Re: if statement problem From: lokesh kumar Injection-Date: Wed, 24 Jul 2013 23:04:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 47 Xref: news.eternal-september.org comp.lang.vhdl:6841 entity squr_5bit is Port ( a : in STD_LOGIC_VECTOR (4 downto 0); c : out STD_LOGIC_VECTOR (8 downto 0)); end squr_5bit; architecture Behavioral of squr_5bit is signal b : STD_LOGIC_VECTOR (8 downto 0); signal temp : STD_LOGIC_VECTOR (8 downto 0); begin position_even_b: for i in 0 to 4 generate b(2*i) <=3D a(i);=20 end generate; c <=3D b; position_odd_b: for i in 0 to 3 generate b(2*i+1) <=3D '0'; end generate; -- position_c:for i in 8 downto 5 loop --if b(i) =3D '1' then --(temp(i) downto temp (i-5)) <=3D (b(i) downto b(i-5)) xor "100101"; -- else if b(i) =3D '0'; --null; --end if; --end loop; --c <=3D (temp(4) downto temp(0)); end Behavioral; ---------------------------------- This is the full code. I am taking a 5-bit number. And making its square. (= Please note that the final addition is not a simple binary addition, its an= XOR operation). So the output will be a 9-bit number. It suppose, A =3D a4= a3 a2 a1 a0 then then output always come as, C =3D a4 0 a3 0 a2 0 a1 0 a0 = (in this manner) Now I need to reduce the output to 5-bit number.=20 suppose the square is, 101010101 For reduction, I have to use 100101. 101010101 100101 --------- 001111101 (XOR operation) Now I have to check if the MSB is "1" or not. If the MSB is "1" then I hav= e to do the XOR operation in same way. But if the MSB is zero, then I have = to check the second MSB. Like that I have to do the loop for 4-times to get the 5-bit reduction resu= lt. ----- I am getting an error. It shows "Unexpected error For loop" Please help! From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.171.72 with SMTP id g8mr38081927qaz.7.1374707877670; Wed, 24 Jul 2013 16:17:57 -0700 (PDT) X-Received: by 10.49.2.36 with SMTP id 4mr327225qer.29.1374707877600; Wed, 24 Jul 2013 16:17:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gh1no230946qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no164760qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 16:17:57 -0700 (PDT) In-Reply-To: <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1b99d9d9-ac95-4e26-8d65-cec84934c149@googlegroups.com> Subject: Re: Conditional Compile Generate statements From: Andy Injection-Date: Wed, 24 Jul 2013 23:17:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 4 Xref: news.eternal-september.org comp.lang.vhdl:6842 Cory, All generics are elaboration-time constants, and therefore their effects are optimized. Any circuit description that is dependent upon a generic-based condition is not implemented by the synthesis tool if the condition is not true. Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.171.72 with SMTP id g8mr38104068qaz.7.1374708217528; Wed, 24 Jul 2013 16:23:37 -0700 (PDT) X-Received: by 10.49.36.199 with SMTP id s7mr1516105qej.17.1374708217507; Wed, 24 Jul 2013 16:23:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cb17no165040qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no165038qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 16:23:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=NAghUwoAAABTd1967OqsgyjFTnwEIH1o NNTP-Posting-Host: 95.150.78.97 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Want to understand the logic of a code From: lkp Injection-Date: Wed, 24 Jul 2013 23:23:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 45 Xref: news.eternal-september.org comp.lang.vhdl:6843 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; --use work.my_package.all; entity square_163_7_6_3 is port ( a: in std_logic_vector(162 downto 0); z: out std_logic_vector(162 downto 0) ); end square_163_7_6_3; architecture circuit of square_163_7_6_3 is signal s, t, u, s_plus_t: std_logic_vector(162 downto 0); signal xor1, xor2: std_logic; begin vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate; s(162) <= a(81); vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate; t(7) <= a(82); vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+78); t(2*i + 1) <= a(i+79); end generate; t(162) <= a(159); xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162); u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1; u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1; u(7) <= '0'; u(8) <= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2; u(11) <= '0'; u(12) <= a(86) xor a(162); u(13) <= '0'; vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate; u(162) <= a(161); xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate; xor_gates2: for j in 0 to 162 generate z(j) <= s_plus_t(j) xor u(j); end generate; end circuit; --------------------------------------- Hi, I want to understand the logic of the code. I want to design the same code for 193-bit. Could anyone please make me understand, how the code is working? :) Thank you! From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.7.7 with SMTP id b7mr1461316qab.5.1374708943129; Wed, 24 Jul 2013 16:35:43 -0700 (PDT) X-Received: by 10.49.4.136 with SMTP id k8mr1573822qek.19.1374708943085; Wed, 24 Jul 2013 16:35:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gh1no231905qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no165801qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 16:35:42 -0700 (PDT) In-Reply-To: <5094b50b-fdb7-497a-ab5a-bc4be32142bc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <8b86642b-65dd-4add-abcb-d8d2624dc81f@googlegroups.com> <5b464072-b34d-40d0-b9ae-36ec0f638455@googlegroups.com> <6a45b68e-2785-49ef-96e6-881bd679ce5f@googlegroups.com> <5094b50b-fdb7-497a-ab5a-bc4be32142bc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82f7fb59-7adb-4395-87b6-18d0c04b87cc@googlegroups.com> Subject: Re: Conditional Compile Generate statements From: Andy Injection-Date: Wed, 24 Jul 2013 23:35:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 28 Xref: news.eternal-september.org comp.lang.vhdl:6844 Cory, Conditional compilation for most languages is accomplished through a text p= reprocessor that alters the source code before it gets to the compiler. The= refore the pre-altered source code need not even be legal syntax for the co= mpiler, so long as the pre-processor makes it legal (or removes it). This i= s how C and Verilog do conditional compilation, using 'define macros, etc. Do not confuse synthesis with compilation. Compilation is only the first sy= nthesis step, fallowed by one or more mapping and optimization stages. All = VHDL code is compiled, but some of the compiled code may be optimized or ma= pped to nothing, depending on static (known at synthesis time) values. For Synplify Pro, if you have if-generate statements, their effects (e.g. m= ultiplexers and controlling ciruitry) are shown in the RTL-level view of t= he design, but they are optimized out during mapping, and are not present i= n the Technology (gate-level) view, nor in the gate level netlist. So at Sy= nplify performs the elaboration phase during mapping. This may not be true = for other synthesis tools, which may combine elaboration with compilation. A good example of the difference between a "static" value in VHDL simulatio= n(usually a constant, generic, literal, etc.) and a "static" value in synth= esis is in the index of a for-loop. For VHDL simulation, the loop index is = a dynamic value that takes on different values at different times. For synt= hesis, loops are always automatically unrolled, and therefore each referenc= e to the loop index after unrolling is a static value which is then optimiz= ed.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.54.73 with SMTP id p9mr53234127qag.1.1374710137298; Wed, 24 Jul 2013 16:55:37 -0700 (PDT) X-Received: by 10.49.71.173 with SMTP id w13mr1566687qeu.21.1374710137236; Wed, 24 Jul 2013 16:55:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!cb17no166910qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no166903qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jul 2013 16:55:37 -0700 (PDT) In-Reply-To: <283d00b6-af51-4a80-a075-21233d37327a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> <51f00c0c$0$26779$862e30e2@ngroups.net> <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> <283d00b6-af51-4a80-a075-21233d37327a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <372d542c-4685-4979-8be3-5044e5731d48@googlegroups.com> Subject: Re: if statement problem From: Andy Injection-Date: Wed, 24 Jul 2013 23:55:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6845 Every entry-level VHDL text book states that for-loops are sequential statements and must be in a process or subprogram (function/procedure). Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.169.1 with SMTP id w1mr14219144qay.4.1374736222812; Thu, 25 Jul 2013 00:10:22 -0700 (PDT) X-Received: by 10.50.27.74 with SMTP id r10mr105655igg.10.1374736222723; Thu, 25 Jul 2013 00:10:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cb17no190943qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no190930qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 00:10:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=153.20.95.70; posting-account=mREnAAoAAADstS3CsETjeZOKWEIhqZHt NNTP-Posting-Host: 153.20.95.70 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <411365a9-5544-4e8a-accd-a16a828df74a@googlegroups.com> Subject: elevator controller From: asuraseed@gmail.com Injection-Date: Thu, 25 Jul 2013 07:10:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1503 Xref: news.eternal-september.org comp.lang.vhdl:6846 A building has an elevator accessing 3 levels. You are to design an elevator controller with the following specifications: 1) The elevator has 2 switches for user to select either up or down. The seven-segment should display the count until the level is reached. 2) When in the elevator, the user selects the desired level. The seven-segment should display the count until the selected level is reached. 3) A reset button in the elevator if activated, will take the elevator to level 1. 4) An emergency switch if pressed, will activate a light From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.171.72 with SMTP id g8mr39774079qaz.7.1374736683407; Thu, 25 Jul 2013 00:18:03 -0700 (PDT) X-Received: by 10.50.62.103 with SMTP id x7mr108023igr.16.1374736683214; Thu, 25 Jul 2013 00:18:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!cb17no191471qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no191466qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 00:18:02 -0700 (PDT) In-Reply-To: <411365a9-5544-4e8a-accd-a16a828df74a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=153.20.95.70; posting-account=mREnAAoAAADstS3CsETjeZOKWEIhqZHt NNTP-Posting-Host: 153.20.95.70 References: <411365a9-5544-4e8a-accd-a16a828df74a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9eab1a07-776d-4139-8b94-dadac79b2558@googlegroups.com> Subject: Re: elevator controller From: asuraseed@gmail.com Injection-Date: Thu, 25 Jul 2013 07:18:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6847 Anyone keen to help out? From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.36.15 with SMTP id r15mr54887499qad.8.1374737257833; Thu, 25 Jul 2013 00:27:37 -0700 (PDT) X-Received: by 10.50.30.226 with SMTP id v2mr111880igh.17.1374737257636; Thu, 25 Jul 2013 00:27:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!gh1no256569qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no192113qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 00:27:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=153.20.95.70; posting-account=mREnAAoAAADstS3CsETjeZOKWEIhqZHt NNTP-Posting-Host: 153.20.95.70 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: *URGENT* Anyone keen to helpout to design a Elevator controller VHDL file using altera *URGENT* From: asuraseed@gmail.com Injection-Date: Thu, 25 Jul 2013 07:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6848 The following requirement need to be designed in Quartus and Max EPM7128SLC84-7 A building has an elevator accessing 3 levels. You are to design an elevator controller with the following specifications: 1) The elevator has 2 switches for user to select either up or down. The seven-segment should display the count until the level is reached. 2) When in the elevator, the user selects the desired level. The seven-segment should display the count until the selected level is reached. 3) A reset button in the elevator if activated, will take the elevator to level 1. 4) An emergency switch if pressed, will activate a light Thanks in advance! From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: *URGENT* Anyone keen to helpout to design a Elevator controller VHDL file using altera *URGENT* Date: Thu, 25 Jul 2013 10:26:47 +0200 Lines: 81 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net NBt8/BF3u/bzIx1ihXTdVwdF7SuzeRvd5HOHvM7alwun7nk6m5 Cancel-Lock: sha1:xWX3+NHF8TIWQ1rxCNbZLKaOAQI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6849 On 25/07/2013 09:27, asuraseed@gmail.com wrote: > The following requirement need to be designed in Quartus and Max > EPM7128SLC84-7 > > A building has an elevator accessing 3 levels. You are to design an > elevator controller with the following specifications: Please include the name of the institute/course/professor so I can send the solution to her/him directly. No worries I'll mention your name as well... > > 1) The elevator has 2 switches for user to select either up or down. > The seven-segment should display the count until the level is > reached. Does it mean the elevator has to stop at each floor? Quite an unconventional elevator I'd say... > > 2) When in the elevator, the user selects the desired level. The > seven-segment should display the count until the selected level is > reached. So the elevator has more than two switches... If there are 'buttons' for desired level than what is the purpose for the two switches 'up' and 'down'? What happens if you press the 'down' switch and then desire to go at a higher level? > > 3) A reset button in the elevator if activated, will take the > elevator to level 1. Have you ever seen a reset button in an elevator??? Are all the switches reset by the same reset? > > 4) An emergency switch if pressed, will activate a light quoting Wikipedia: > In electrical engineering, a switch is an electrical component that > can break an electrical circuit, interrupting the current or > diverting it from one conductor to another By its definition a 'switch' is a component that has *at least* two _states_, which can be chosen by one or a series of _actions_. So what does reset the light (as opposed to the button that 'sets' it on)? (I bet the fire brigade...or maybe a power cut) After you gather all this information you can at least start to think each piece of your design on a piece of paper. All the blocks that you need to have and how these blocks 'talk' to each other. After you have that you can start implementing it for whatever target. At the same time you would need to design a testbench for your design and have a test plan in order to be sure that your piece of elevator controller does what it is asked for (I didn't have a testbench in my first elevator controller task and because of a bug it hit the roof at max speed, causing 16 people to die...likely was just an homework! Hint, do check boundary cases). If it is an *urgent* task than you better hurry... As a side note, why do you think posting the same message three times in within 17 minutes would increase your chance to get a reply? Did you consider at all that people on this group have their own jobs/lives and may read this message after hours you posted? If you really manage to get somebody to make your homework making you gaining some 'free' time, I'll suggest you to spend it reading the following articles: http://www.catb.org/esr/faqs/smart-questions.html http://www.ou.edu/research/electron/internet/use-faq.htm http://en.wikipedia.org/wiki/Eternal_September I hope you enjoy the readings... Al From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: OS-VVM crosscoverage vs directed testing Date: Thu, 25 Jul 2013 11:12:25 +0200 Lines: 63 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net oGHaBIUAg/Wk8U2MSo/FRAuRsuEfAZRO2YPtvExxfJJzAsmHbb Cancel-Lock: sha1:b75upKqFh+kL5SrAhP1lXrvGtKw= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6850 Hi everyone, I'm not sure this is the best place to post this thread since is more related to verification than vhdl itself, but since the OS-VVM is a vhdl package I figured people here might also be interested in the topic (please direct me elsewhere if needed). I've followed the Aldec webinar on OS-VVM (see: http://www.aldec.com/en/support/resources/multimedia/webinars) and found it quite interesting, to the point that I'll definitely give OS-VVM a try. I nevertheless have some doubts/comments about the cross coverage part. The webinar presents an ALU design as a DUT to introduce the concept of cross coverage of the two input registers in order to test all the combinations, but why then not a two 'for loop' to generate all the cases: -- ACov is variable of CovPType for i in reg1'range loop for j in reg2'range loop DoAluOp(i, j); -- do transaction ACov.ICover((reg1, reg2)); -- collect coverage end loop; end loop; The webinar goes on on how you can optimize the coverage using what they call 'intelligent coverage' which focuses on holes coverage. Would the for loop above be less efficient than the intelligent cross coverage proposed (in terms of simulation cycles)? Moreover the 'intelligent coverage' is fulfilled with the call: ACov.AddCross(2, GenBin(0,7), GenBin(0,7) ); where the first parameter is an 'AtLeast' parameter. Shouldn't it be 'AtMost'??? If you want each cross case to be hit not more than a certain amount of time (to reduce the 'logN' factor of a randomly generated pair of values) than I do not see why you have to specify an 'AtLeast' parameter... Am I missing something? As a general comment, wouldn't it be more appropriate to find a better suited example to show the real power of cross coverage [1]? Any pointer to freely available code that illustrates the usage of OS-VVM is extremely helpful. Cheers, Al [1] I do not have any to provide and I'm willing to see what is the real advantage about having the bins randomly filled instead of sequentially filled with direct cases. -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.171.72 with SMTP id g8mr40428537qaz.7.1374749587838; Thu, 25 Jul 2013 03:53:07 -0700 (PDT) X-Received: by 10.49.82.50 with SMTP id f18mr1565057qey.22.1374749587821; Thu, 25 Jul 2013 03:53:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gh1no268747qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no205044qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 03:53:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> Subject: Re: OS-VVM crosscoverage vs directed testing From: goouse99@gmail.com Injection-Date: Thu, 25 Jul 2013 10:53:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8228 Xref: news.eternal-september.org comp.lang.vhdl:6851 Am Donnerstag, 25. Juli 2013 11:12:25 UTC+2 schrieb alb: > Hi everyone, >=20 >=20 >=20 > I'm not sure this is the best place to post this thread since is more >=20 > related to verification than vhdl itself, but since the OS-VVM is a vhdl >=20 > package I figured people here might also be interested in the topic >=20 > (please direct me elsewhere if needed). >=20 >=20 >=20 > I've followed the Aldec webinar on OS-VVM (see: >=20 > http://www.aldec.com/en/support/resources/multimedia/webinars) and found >=20 > it quite interesting, to the point that I'll definitely give OS-VVM a try= . >=20 >=20 >=20 > I nevertheless have some doubts/comments about the cross coverage part. >=20 > The webinar presents an ALU design as a DUT to introduce the concept of >=20 > cross coverage of the two input registers in order to test all the >=20 > combinations, but why then not a two 'for loop' to generate all the cases= : >=20 >=20 >=20 > >=20 >=20 >=20 > -- ACov is variable of CovPType >=20 > for i in reg1'range loop >=20 > for j in reg2'range loop >=20 > DoAluOp(i, j); -- do transaction >=20 > ACov.ICover((reg1, reg2)); -- collect coverage >=20 > end loop; >=20 > end loop; >=20 >=20 >=20 > >=20 >=20 >=20 > The webinar goes on on how you can optimize the coverage using what they >=20 > call 'intelligent coverage' which focuses on holes coverage. >=20 >=20 >=20 > Would the for loop above be less efficient than the intelligent cross >=20 > coverage proposed (in terms of simulation cycles)? >=20 >=20 >=20 > Moreover the 'intelligent coverage' is fulfilled with the call: >=20 >=20 >=20 > ACov.AddCross(2, GenBin(0,7), GenBin(0,7) ); >=20 >=20 >=20 > where the first parameter is an 'AtLeast' parameter. Shouldn't it be >=20 > 'AtMost'??? If you want each cross case to be hit not more than a >=20 > certain amount of time (to reduce the 'logN' factor of a randomly >=20 > generated pair of values) than I do not see why you have to specify an >=20 > 'AtLeast' parameter... Am I missing something? >=20 >=20 >=20 > As a general comment, wouldn't it be more appropriate to find a better >=20 > suited example to show the real power of cross coverage [1]? >=20 >=20 >=20 > Any pointer to freely available code that illustrates the usage of >=20 > OS-VVM is extremely helpful. >=20 >=20 >=20 > Cheers, >=20 >=20 >=20 > Al >=20 >=20 >=20 > [1] I do not have any to provide and I'm willing to see what is the real >=20 > advantage about having the bins randomly filled instead of sequentially >=20 > filled with direct cases. >=20 >=20 >=20 > --=20 >=20 > A: Because it fouls the order in which people normally read text. >=20 > Q: Why is top-posting such a bad thing? >=20 > A: Top-posting. >=20 > Q: What is the most annoying thing on usenet and in e-mail? Hi Al, doing verification with Constraint Random Stimuli and Coverage Methods some= times needs a second thought to fully understand it. So let's do some discussion of the things you pointed out. In your nested loop example you iterate over all possible input combination= s. For some small ALU this might be acceptable. But how about some wide input = device (e.g. >64 bit).=20 It takes just too much time to create all the stimuli, not to mention the s= imulation time to get the results. While in most cases only a certain (hopefully small) ammount of stimuli wou= ld be sufficient for a full coverage, the problem is always to find these. Constraint Random Stmuli generation and Coverage are one approach to reduce= the ammount of stimuli that a simulation has to use. Especially Cross-Coverage can be a mighty tool, since the bining can be mul= tidimensional. According to the number of hits in selected bins the tesbench can adapt the= randomisation of the stimuli patterns. So if it becomes obvious that some = part of the circuit has been excessively stimulated, the randomization cons= traints can be modified to reduce the probabillity of triggering that circu= it. Therefore the chance that other parts of the circuit are triggered by s= ome stimuli pattern rise. Still it can not be excluded that the already tested circuit part becomes t= riggered again onvce in a while. That also explains why there is just a definition for a minimum number of h= its in the AddCross function. You simply can't help to get additional hits = in that bin (except for defined disabling, but that's a badly chosen constr= aint). =20 Here we are currently working with SystemVerilog and using some OpenCores F= PU model as DUT. This FPU has an Operator Selection and a Rounding Mode Selection. The Operations do not use the full possible set of binary combinations the = input offers. So there are several unused opcodes. If you do a cross-coverage of the stimuli there might appear hits for the b= ins defined for the unused opcodes. While these have to be tested, for full coverage (actually the original FPU= stalls when that happens) you won't want to waste too much stimuli on thes= e cases. So you can reduce the probability to generate unused opcodes, after a defin= ed number of hits have been recognized. One might ask, why not set the constraints that way from the beginning. A possible answer could be: To acheive as many simple test cases in the tes= t plan as early as possible. And like the ALU even the FPU is some very straightforward functioning devi= ce. More complex systems might switch into differnt states during runtime at a = hardly predictable rate. So the testbench might need to be able to adapt to= this. But these would be quite difficult examples, hardly suited to grasp = the concepts. Back to the loop-example from the beginning: You asked about the efficiency compared to CR and coverage. Well. due to the random properties of the stimuli generation this can not b= e said in a determinable way. Just some dumb example (because every case is different). If i-max and j-max are needed to acheive full coverage the loop has to run = to his very end, which can take a looooong time. With some luck the random stimulis create this combination very early and y= ou acheive full coverage after ridiculously short simulation time. But with Murphy as your team mate it may also happen that this stimuli neve= r ever appears. (e.g. due to bad constraints)=20 So Constraind Random Testing gives you a chance (but not a guarantee) to ac= heive full coverage faster.=20 One way to improve your luck could be to start the testbench on multiple co= mputers using different randomisation seeds.=20 You might observe that the acheived goals of the testplan appear in a diffe= rent sequence and at different times on the multiple machines, and actually= you can merge the coverage results to acheive full coverage and thus fulfi= lling your test plan. I hope you could find some useful ideas in my explanations. Have a nice simulation (or should I say verification here?) Eilert From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.64.202 with SMTP id f10mr39277292qai.2.1374752775322; Thu, 25 Jul 2013 04:46:15 -0700 (PDT) X-Received: by 10.49.63.162 with SMTP id h2mr326186qes.26.1374752775267; Thu, 25 Jul 2013 04:46:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!gh1no272253qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no208580qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 04:46:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 95.150.78.97 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Can anyone help me out to implement some VHDL codes for some cash. From: chris.waugh190490@gmail.com Injection-Date: Thu, 25 Jul 2013 11:46:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6852 Hi all. I want someone who is good in VHDL programming and can help me out to implement some VHDL codes. I am ready to pay for it because it is important for me. Reply me as soon as possible. Chris From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.54.73 with SMTP id p9mr56317338qag.1.1374764214873; Thu, 25 Jul 2013 07:56:54 -0700 (PDT) X-Received: by 10.50.4.38 with SMTP id h6mr223711igh.8.1374764214649; Thu, 25 Jul 2013 07:56:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.glorb.com!cb17no224770qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no224768qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 07:56:54 -0700 (PDT) In-Reply-To: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: OS-VVM crosscoverage vs directed testing From: Andy Injection-Date: Thu, 25 Jul 2013 14:56:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6853 Al, To fit in the time allowed, examples and demonstrations are often simplifie= d, which in this case also means that a simple directed test would have bee= n just as easy and effective to exhaustively test the same features of the = DUT (register selection).=20 In a real verification effort, the test would also need to test different v= alues in the registers, along with different operations performed by the AL= U. Exhaustively testing every possible combination of these conditions migh= t take too long to be practical.=20 When exhaustively covering every possible condition is not practical, CRS a= llows you to cover more or fewer conditions by just running the simulation = for longer or shorter times (trying more or fewer random stimuli along the = way), rather than having to modify the stimulus generation code to generate= more or fewer different stimuli.=20 The advantage of Constrained Random Stimulus is not usually a reduced numbe= r of stimuli generated and simulated.=20 Rather, especially for complex DUTs, the advantage of CRS is the relative e= ase of defining LOTS of stimuli in different orders, with different values = and combinations of values, etc., without defining (and running) ALL possib= le stimuli. I look at CRS as being kind of like when your spouse sends you to the store= to buy some milk: You could get in your car and drive to the store, get th= e milk, and bring it home quickly and efficiently: mission accomplished. Or= you could walk to the store, not necessarily by the shortest path, and yo= u might find some nice flowers along the way, and take them home too: missi= on also accomplished, but with a bonus!* =20 CRS is about exposing unexpected conditions on your way to testing the expe= cted conditions. Where intelligent coverage hepls is reducing the total number of stimuli (a= nd therefore runtime) from Nlog(N) to just N, to reach the desired coverage= , by shaping the random generation of future stimuli to avoid generating ad= ditional stimuli that exceed already covered goals. Just running the same directed tests over and over on the same DUT does not= tell you anything. Running CRS tests over and over (with new randomization= seeds) on the same DUT keeps testing new conditions, and therefore provide= s new and valuable information. And those multiple tests can be run in para= llel on multiple machines, or in series over nights and weekends on one or = more machines. *Unless your spouse is allergic to the flowers, or REALLY wanted the milk N= OW! Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.7.7 with SMTP id b7mr6699752qab.5.1374795317634; Thu, 25 Jul 2013 16:35:17 -0700 (PDT) X-Received: by 10.49.4.201 with SMTP id m9mr1738114qem.15.1374795317598; Thu, 25 Jul 2013 16:35:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gh1no331893qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no273795qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Jul 2013 16:35:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.159; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.159 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07c56789-b3b4-41cf-a6e1-a29c4b76d18e@googlegroups.com> Subject: Re: OS-VVM crosscoverage vs directed testing From: Jim Lewis Injection-Date: Thu, 25 Jul 2013 23:35:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5754 Xref: news.eternal-september.org comp.lang.vhdl:6854 Hi Al, > I'm not sure this is the best place to post this thread since is more ... Here is fine. Two other good resources: http://osvvm.org/ -- has a bulletin board and such for Q & A http://www.synthworks.com/blog/osvvm/ -- blog focused on OSVVM by Me (the = Principal OSVVM developer). > I've followed the Aldec webinar on OS-VVM (see: > http://www.aldec.com/en/support/resources/multimedia/webinars) and found > it quite interesting, to the point that I'll definitely give OS-VVM a try= . Note, there are several there OSVVM webinars and the recent one from July 1= 8, 2013 is on page 2. =20 > The webinar presents an ALU design as a DUT to introduce the concept of > cross coverage ... =20 >=20 The ALU example is intended to be simple and quick to understand. Your cod= e with loops is just as efficient as the Intelligent Coverage. One differe= nce is that if you change the coverage goal to 10, then your test repeats t= he same pattern, however, Intelligent Coverage does not. For designs that = potentially have order dependencies, this is important. For testing an ALU= , this is not so important. =20 An ALU is just one example. Each bin had only one value in each range. Si= nce OSVVM allows functional coverage to be defined incrementally with seque= ntial code, creating a non-symmetric functional coverage model is simple. = Consider the weighted coverage example. I can further extend it to allow a= dditional parameters, such as a ranged data value. The intent of this para= meter is solely for test generation. =20 Bin1.AddBins( 70, GenBin(0), GenBin(1, 255, 1) ) ; -- Normal Handling, 70% Bin1.AddBins( 20, GenBin(1), GenBin(10, 15, 1) ) ;=20 Bin1.AddBins( 10, GenBin(2), GenBin(21, 32, 1) ) ; See Matthias Alles blog post http://osvvm.org/archives/550 for how he is us= ing it and why the randomization provides a more realistic test than loopin= g. Intelligent Coverage is a step up from SystemVerilog's Constrained Random. = For the same problem, Constrained Random will take on average N*LogN itera= tions. Even in this little problem, my constrained random example took 315= iterations vs the 64 iterations of Intelligent Coverage (or of your loopin= g). =20 > Moreover the 'intelligent coverage' is fulfilled with the call: > ACov.AddCross(2, GenBin(0,7), GenBin(0,7) ); > where the first parameter is an 'AtLeast' parameter. Shouldn't it be=20 > 'AtMost'???=20 AtLeast means a coverage model needs to see a value in the bin at least tha= t number of times to consider the model covered. The term is borrowed from= SystemVerilog and 'e'. From a constrained random perspective, to consider= a coverage model "covered", all bins must have >=3D their AtLeast value. = Since constrained random approach generates extra values (approximately Log= N of them), some bins will have more than their AtLeast value. =20 >From a Intelligent Coverage perspective, the bins get exactly the AtLeast v= alue. So perhaps it would have been more appropriate to name it CoverageGo= al. Hard to have that hind sight. The OSVVM functional coverage has evolv= ed over several years now and it did not originally have the Intelligent Co= verage feature. Instead, it used the Constrained Random based on sequentia= l code and randomization (similar to the constrained random pattern shown i= n the presentation). =20 Note that @Eilert's response is based on a SystemVerilog perspective that o= nly has Constrained Random. In OSVVM, we don't do a random trial of differ= ent seeds to try to improve our coverage. =20 > Any pointer to freely available code that illustrates the usage of > OS-VVM is extremely helpful. What you saw in the presentation is just the tip of the iceberg. =20 Here is the "sell" part. =20 OSVVM is based on methodology and packages SynthWorks developed for our VHD= L Testbenches and Verification class. In this class, we provide a superset= of the OSVVM packages that facilitate transaction level modeling (tlm), se= lf-checking, scoreboards, memory modeling, synchronization methods, functio= nal coverage, and randomization. Our modeling approach is accessible by bot= h verification and RTL designers. Class details are here: http://www.synthworks.com/vhdl_testbench_verification.htm We offer the class online, at a public venue, or on-site. Our class schedu= le is below. You can also find links to more information about our instruc= tor led online classes. =20 http://www.synthworks.com/public_vhdl_courses.htm#VHDL_Test_Bench_Trainin= g=20 Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: OS-VVM crosscoverage vs directed testing Date: Fri, 26 Jul 2013 12:36:15 +0200 Lines: 159 Message-ID: References: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net l+RdIgATDiyge/azryqWGgVCg2RrnDJva9BW6xnTTWX7EcWNS4 Cancel-Lock: sha1:uWhBoHnYmBoauQ4wV7Mk6Ez+FiM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6855 Hi Eilert, On 25/07/2013 12:53, goouse99@gmail.com wrote: [] > In your nested loop example you iterate over all possible input > combinations. For some small ALU this might be acceptable. But how > about some wide input device (e.g. >64 bit). It takes just too much > time to create all the stimuli, not to mention the simulation time to > get the results. While in most cases only a certain (hopefully small) > ammount of stimuli would be sufficient for a full coverage, the > problem is always to find these. I agree with you that the number of combinations do explode if the length of the registers increase. But you can still do binning without any extra package just by manipulating on the ranges of the aforementioned for loop. Certainly if you do not randomly select an input you end up simulating only one 'edge' of the bin (with bin size larger than one value only), while with multiple simulation runs and a randomly generated input you can cover the bin more uniformly. But in the end this does not matter that much since the choice of binning should be driven by the test plan and if you have covered a bin (even once) you should be happy. > > Constraint Random Stmuli generation and Coverage are one approach to > reduce the ammount of stimuli that a simulation has to use. Do we agree that binning can be done with directed cases as well as CR? If this is so then as long as you hit each bin once (or whatever number of times) than you are done. I do not see how having selected a random number in a bin (that I define) makes me reduce the amount of stimuli... I am clearly missing something. > Especially Cross-Coverage can be a mighty tool, since the bining can > be multidimensional. According to the number of hits in selected bins > the tesbench can adapt the randomisation of the stimuli patterns. So > if it becomes obvious that some part of the circuit has been > excessively stimulated, the randomization constraints can be modified > to reduce the probabillity of triggering that circuit. Therefore the > chance that other parts of the circuit are triggered by some stimuli > pattern rise. Still it can not be excluded that the already tested > circuit part becomes triggered again onvce in a while. That also > explains why there is just a definition for a minimum number of hits > in the AddCross function. You simply can't help to get additional > hits in that bin (except for defined disabling, but that's a badly > chosen constraint). I guess I was wrong in calling the 'AtLeast' parameter 'AtMost', being 0 a value included in an 'AtMost' condition while excluded in an 'AtLeast' condition. But I should add that since 'intelligent' coverage constrains values to be randomly selected across _holes_ in the coverage matrix, you are actually saying: "once bin (k,l) has been hit N times than exclude it from the set of available bins". There's no 'AtLeast' since you cannot hit the fulfilled bin again. Can you trace which input registers have 'triggered' a certain portion of a circuit/code? If this is the case I see your point, but if you need to do it manually varying the weights (first with a uniform weighting and then changing bin weights one by one) than is still a real PITA. I was not aware that code coverage could be somehow 'linked' to functional coverage since the two metrics are (in principle) completely independent. > > Here we are currently working with SystemVerilog and using some > OpenCores FPU model as DUT. This FPU has an Operator Selection and a > Rounding Mode Selection. The Operations do not use the full possible > set of binary combinations the input offers. So there are several > unused opcodes. If you do a cross-coverage of the stimuli there might > appear hits for the bins defined for the unused opcodes. While these > have to be tested, for full coverage (actually the original FPU > stalls when that happens) you won't want to waste too much stimuli on > these cases. So you can reduce the probability to generate unused > opcodes, after a defined number of hits have been recognized. Isn't the weighting process as tedious as writing 'directed' test cases? And if you *have* to run a simulation to verify the unused opcode is hit, than the amount of simulations you need is the same. The main difference I see is on a parallel/multiple simulation runs, since a directed testcase will always test the same case, while a CR will likely test different cases every time, adding coverage on the long run. > One might ask, why not set the constraints that way from the > beginning. A possible answer could be: To acheive as many simple test > cases in the test plan as early as possible. In this respect binning is as crucial as looking for the minimum set of test cases. What I do believe though is that with CR you may inadvertently hit a corner case faster than in directed testing, but I can argue that if this is the case than your testplan was missing corner cases. [] > Back to the loop-example from the beginning: You asked about the > efficiency compared to CR and coverage. Well. due to the random > properties of the stimuli generation this can not be said in a > determinable way. Not determinable but predictable with some level of confidence. The webinar refers to an N * log(N) number of iterations to cover every bin (where N is the number of bins) but I need to mention that this is valid for a certain level of confidence, meaning you still may have statistical fluctuations. > > Just some dumb example (because every case is different). If i-max > and j-max are needed to acheive full coverage the loop has to run to > his very end, which can take a looooong time. If they are needed why don't you have a direct test case for that instead of running till the very end? Again here what I said on parallel simulations may apply. In directed testing you'll always test the same cases, without adding any new coverage if you do not change/add test cases. This is not true for CR. > With some luck the > random stimulis create this combination very early and you acheive > full coverage after ridiculously short simulation time. I may say ridiculously long and I bet our chances are exactly the same, unless you cheat and use weighting ;-) > But with > Murphy as your team mate it may also happen that this stimuli never > ever appears. (e.g. due to bad constraints) Uhm... I don't seem to see the point. You need to have i-max and j-max in your test plan and you decide to play dices to hit that case. Why not simply have a direct case instead? [] > One way to improve your luck could be to start the testbench on > multiple computers using different randomisation seeds. You might > observe that the acheived goals of the testplan appear in a different > sequence and at different times on the multiple machines, and > actually you can merge the coverage results to acheive full coverage > and thus fulfilling your test plan. In this case I fully agree with you. And as of now it is the only convincing argument to go for CR. Running on multiple computers (i.e. running on the same computer multiple times) will certainly shorten verification because your simulations are incrementally covering more without the need to add test cases. > I hope you could find some useful ideas in my explanations. I hope you find my counter arguments as interesting as I found yours. Al From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: OS-VVM crosscoverage vs directed testing Date: Fri, 26 Jul 2013 16:39:50 +0200 Lines: 87 Message-ID: References: <07c56789-b3b4-41cf-a6e1-a29c4b76d18e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qyUmNS04g0RRzH06QXSJYwP6gPq2CchkhSzeq8/PCrJg3chXo6 Cancel-Lock: sha1:ncCeZyuraH6pBULJDn0lsbzl2IM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <07c56789-b3b4-41cf-a6e1-a29c4b76d18e@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6856 Hi Jim, On 26/07/2013 01:35, Jim Lewis wrote: [] >> I've followed the Aldec webinar on OS-VVM (see: >> http://www.aldec.com/en/support/resources/multimedia/webinars) and found >> it quite interesting, to the point that I'll definitely give OS-VVM a try.. > Note, there are several there OSVVM webinars and the recent one from July 18, 2013 is on page 2. > Thanks for the hint! To be honest I superficially thought the order was such that new stuff would appear on the first page... > >> The webinar presents an ALU design as a DUT to introduce the >> concept of cross coverage ... >> > The ALU example is intended to be simple and quick to understand. > Your code with loops is just as efficient as the Intelligent > Coverage. Ok, now we are on the same page! > One difference is that if you change the coverage goal to 10, then > your test repeats the same pattern, however, Intelligent Coverage > does not. For designs that potentially have order dependencies, this > is important. For testing an ALU, this is not so important. Shouldn't designs that have potential order dependency have a test plan that explicitly cover the case? Your example actually suits perfectly my mental model, i.e. CR may find 'bugs' in the verification plan since it broadens the scenarios w.r.t. directed testing. [] > See Matthias Alles blog post http://osvvm.org/archives/550 for how he > is using it and why the randomization provides a more realistic test > than looping. The post is extremely useful indeed. When your device needs to operate in randomly changing conditions then I agree that directed cases are limiting the scenarios, effectively missing possible critical ones (again a hole in your verification plan though). > Intelligent Coverage is a step up from SystemVerilog's Constrained > Random. For the same problem, Constrained Random will take on > average N*LogN iterations. Even in this little problem, my > constrained random example took 315 iterations vs the 64 iterations > of Intelligent Coverage (or of your looping). I'm trying to understand from a statistical standpoint where the N * logN comes from, but I have a storm of physicists around me and I'm sure I'll get a reasonable answer on that ;-) [] > From a Intelligent Coverage perspective, the bins get exactly the > AtLeast value. So perhaps it would have been more appropriate to > name it CoverageGoal. Hard to have that hind sight. The OSVVM > functional coverage has evolved over several years now and it did not > originally have the Intelligent Coverage feature. Instead, it used > the Constrained Random based on sequential code and randomization > (similar to the constrained random pattern shown in the > presentation). Getting the correct naming is not always straight forward. Now I see the heritage behind the name and changing the name result in lack of back compatibility. > Note that @Eilert's response is based on a SystemVerilog perspective > that only has Constrained Random. In OSVVM, we don't do a random > trial of different seeds to try to improve our coverage. I'm sorry but I believe that is a counter argument against the case you previously suggested though. When randomly changing conditions matter then I believe that full coverage changes meaning (and this is also valid for Matthias Alles's example): covering a set of bins is not sufficient anymore. You need to include sequencing. Increasing the number of trials certainly increase the 'list of sequences' that your DUT is experiencing, therefore does increase coverage, simply the test plan was not enough detailed to specify how critical might have been a certain set of sequences. Bare in mind though that, considering the state of your DUT depends on the Mth previous state and you have N possible (unique) bins, the number of possible 'sequences' which might experience your device is N!/(N-M)!... I guess you'll need more than just 'intelligent' coverage to handle that ;-) From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.54.73 with SMTP id p9mr61495691qag.1.1374849604838; Fri, 26 Jul 2013 07:40:04 -0700 (PDT) X-Received: by 10.49.41.101 with SMTP id e5mr742674qel.7.1374849604784; Fri, 26 Jul 2013 07:40:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!gh1no400215qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no346306qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Jul 2013 07:40:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <478cc314-d611-4538-84ef-5c65104532ee@googlegroups.com> Subject: Re: Can anyone help me out to implement some VHDL codes for some cash. From: Cory Shol Injection-Date: Fri, 26 Jul 2013 14:40:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 13 Xref: news.eternal-september.org comp.lang.vhdl:6857 On Thursday, July 25, 2013 6:46:15 AM UTC-5, chris.wa...@gmail.com wrote: > Hi all. > > > > I want someone who is good in VHDL programming and can help me out to implement some VHDL codes. I am ready to pay for it because it is important for me. Reply me as soon as possible. > > > > > > Chris I could. From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.7.7 with SMTP id b7mr10000446qab.5.1374852646296; Fri, 26 Jul 2013 08:30:46 -0700 (PDT) X-Received: by 10.49.41.101 with SMTP id e5mr756638qel.7.1374852646263; Fri, 26 Jul 2013 08:30:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gh1no405089qab.0!news-out.google.com!dk8ni1677qab.0!nntp.google.com!gh1no405086qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Jul 2013 08:30:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <14ce4f66-5d2d-4a9e-a666-f63571664882@googlegroups.com> Subject: Re: OS-VVM crosscoverage vs directed testing From: Andy Injection-Date: Fri, 26 Jul 2013 15:30:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2751 Xref: news.eternal-september.org comp.lang.vhdl:6858 Al,=20 Yes, as long as you meet your coverage goals, you can generate the stimulus= any way you want, and achieve the same results.=20 Now, lets look at ways to generate such stimulus. You could use a directed = loop to generate your stimulus. It is simple enough to do, assuming you wan= t/need (and have the time to simulate) complete coverage (all possible comb= inations).=20 If you only have time to simulate partial coverage, how do you decide, and = then code a stimulus generator to produce, the coverage you seek? How do yo= u verify that it is giving you the coverage that you want? You might want a= coverage model for that...=20 You could use constrained random methods to generate the stimulus, independ= ently of the coverage model. It may a little more time to code (especially = if you are seeking 100% coverage), and maybe a bit more time to sim (genera= ting random numbers is fast, but not as fast as a loop counter). But at lea= st it would run in different orders (in case there is some dependency on or= der). And then you really do need a coverage model to verify that your rand= om stimulus is covering what you wanted.=20 Why can't we just define the desired coverage in the first place, and then = somehow use the coverage model to generate stimulus to meet the coverage?= =20 We can! To me, this is the HUGE benefit of OSVVM-style intelligent coverage: OSVVM = provides the ability to use the coverage model itself to generate the stimu= lus, efficiently and randomly. Andy From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news1.as3257.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-b.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Fri, 26 Jul 2013 19:13:24 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Can anyone help me out to implement some VHDL codes for some cash. References: <478cc314-d611-4538-84ef-5c65104532ee@googlegroups.com> In-Reply-To: <478cc314-d611-4538-84ef-5c65104532ee@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 9 Message-ID: <51f2ae2f$0$2287$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 26 Jul 2013 19:13:19 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1374858799 news-1.free.fr 2287 88.185.146.198:1895 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:6859 Le 26/07/2013 16:40, Cory Shol a écrit : > On Thursday, July 25, 2013 6:46:15 AM UTC-5, chris.wa...@gmail.com wrote: >> Hi all. >> I want someone who is good in VHDL programming and can help me out to implement some VHDL codes. I am ready to pay for it because it is important for me. Reply me as soon as possible. > I could. So could I but could the OP afford the cost ? Nicolas From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.86.200 with SMTP id t8mr62108926qal.0.1374859382642; Fri, 26 Jul 2013 10:23:02 -0700 (PDT) X-Received: by 10.49.82.50 with SMTP id f18mr1794022qey.22.1374859382584; Fri, 26 Jul 2013 10:23:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!gh1no415454qab.0!news-out.google.com!dk8ni1421qab.0!nntp.google.com!cb17no362852qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 26 Jul 2013 10:23:02 -0700 (PDT) In-Reply-To: <478cc314-d611-4538-84ef-5c65104532ee@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=95.150.78.97; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 95.150.78.97 References: <478cc314-d611-4538-84ef-5c65104532ee@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f79ad77-261a-44dd-a3fb-3fa58a905fac@googlegroups.com> Subject: Re: Can anyone help me out to implement some VHDL codes for some cash. From: chris.waugh190490@gmail.com Injection-Date: Fri, 26 Jul 2013 17:23:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1311 Xref: news.eternal-september.org comp.lang.vhdl:6860 Please email me at chris.waugh190490@gmail.com As soon as possible. We can discuss about rest of the things. From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: OS-VVM crosscoverage vs directed testing Date: Mon, 29 Jul 2013 09:26:32 +0200 Lines: 47 Message-ID: References: <82d8c40f-ddf8-4140-aee1-195da91686ed@googlegroups.com> <14ce4f66-5d2d-4a9e-a666-f63571664882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net SEevpRVrk0Q6ZrNd6zmnzwG8pxcv0h6xLkpyDXPw9segrKN5zy Cancel-Lock: sha1:xUcHF+Imec8Hzlfh2otD0z/FVnQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <14ce4f66-5d2d-4a9e-a666-f63571664882@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6861 Hi Andy, On 26/07/2013 17:30, Andy wrote: [] > If you only have time to simulate partial coverage, how do you > decide, and then code a stimulus generator to produce, the coverage > you seek? How do you verify that it is giving you the coverage that > you want? You might want a coverage model for that... Now things get a little bit more interesting... It's not just a matter of implementation, rather a definition of a model to meet the ultimate goal: is the DUT performing per the specifications? >From specs to coverage model is yet another piece of the verification process that is fundamentally critical. If in the coverage model there's no item/point for 'out of order' packets/configurations/states, then we might mistakenly reach full coverage without having tested the device fully. > You could use constrained random methods to generate the stimulus, > independently of the coverage model. It may a little more time to > code (especially if you are seeking 100% coverage), and maybe a bit > more time to sim (generating random numbers is fast, but not as fast > as a loop counter). But at least it would run in different orders (in > case there is some dependency on order). And then you really do need > a coverage model to verify that your random stimulus is covering what > you wanted. Are you saying that no matter what the coverage model is I could forget about it and just throw random stimuli at my device? Uhm, but as you said I would need a coverage model to understand what did I cover, therefore I better have a coverage model in the first place. > > Why can't we just define the desired coverage in the first place, and > then somehow use the coverage model to generate stimulus to meet the > coverage? > > We can! > > To me, this is the HUGE benefit of OSVVM-style intelligent coverage: > OSVVM provides the ability to use the coverage model itself to > generate the stimulus, efficiently and randomly. Please don't take me wrong, I'm not advocating against OSVVM's intelligent coverage, I'm just trying to understand what is the advantage of a random stimuli w.r.t. directed cases if you have _fully_ specified the desired coverage. From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.137.137 with SMTP id w9mr47525896qat.6.1375086962622; Mon, 29 Jul 2013 01:36:02 -0700 (PDT) X-Received: by 10.49.116.243 with SMTP id jz19mr223070qeb.6.1375086962556; Mon, 29 Jul 2013 01:36:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cb17no1041186qab.0!news-out.google.com!ce7ni255qab.0!nntp.google.com!cb17no962824qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 01:36:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <84b244e3-80b5-4699-aee8-09ea67abe99a@googlegroups.com> Subject: Change record elements From: hssig Injection-Date: Mon, 29 Jul 2013 08:36:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 17 Xref: news.eternal-september.org comp.lang.vhdl:6862 Hi, I want to divide all elements of a record by 2. How can I perform that in a kind of loop? type typeMine is record a : natural; b : natural; c : positive; d : integer ... end record; Thank you for your suggestion. Cheers, hssig From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: painting a chair [was Re: OS-VVM crosscoverage vs directed testing] Date: Mon, 29 Jul 2013 10:58:16 +0200 Lines: 103 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net jACQ+7E8778W2RHXMS896g+vqLgmxznIpdrYM9xaIYOnGHXV0F Cancel-Lock: sha1:EHOn06PCrv1JMlGt8+AQ6eC8VQg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6863 Hi everyone, sorry for top posting my own post, but during the weekend I guess I figured something on this topic that might be worth sharing. You may ignore this message if you're not interested in metaphors or analogies with real life experience or parabolas... :-) Last saturday I bought a nice set of teak chairs for my little terrace and the clerk at the shop warned me about painting them with protective oil to make them more resistant to moisture, rain, stains... I grabbed a bucket of teak oil and stared at my chair wondering where to start from (I was making my 'plan'), in the end I wanted to have my chair fully painted ('covered') with oil, that was my 'goal'. I was thinking that maybe I could have sketched down the chair elements (sit, arm rests, legs, ...) and paint them one by one, but I figured that it would have been a little too much for such a task, therefore I started 'randomly' painting here and there. I probably ended up in passing multiple times on the same spots and after a visual inspection I realized I missed a couple of spots which were then carefully painted. I was done, my set of chairs fully painted, my back a little bit sore and my wife happily smiling. In the end I realized that if I had sketched down the elements and had painted them one by one, I would have used a lot less paint and maybe even less time, but certainly the sketch itself would have taken some extra time w.r.t. what I did. I also figured that if I had the chance to 'randomly select' only the non painted spots, I would have used the same amount of paint as for the sketched solution, with the huge benefit of not having to spend time in silly planning... In conclusion I guess that a random approach has had some benefits over a 'directed' approach since there was no need to list all the parts and check them out, but a more 'intelligent' random selection would have certainly been as efficient (in terms of amount of paint used) as the directed case and as easy as the random one... I'm not sure if I'm close to a paradigm shift in my verification methodology (is I ever had one...), but certainly this discussion is helping me a lot. On 25/07/2013 11:12, alb wrote: > Hi everyone, > > I'm not sure this is the best place to post this thread since is more > related to verification than vhdl itself, but since the OS-VVM is a vhdl > package I figured people here might also be interested in the topic > (please direct me elsewhere if needed). > > I've followed the Aldec webinar on OS-VVM (see: > http://www.aldec.com/en/support/resources/multimedia/webinars) and found > it quite interesting, to the point that I'll definitely give OS-VVM a try. > > I nevertheless have some doubts/comments about the cross coverage part. > The webinar presents an ALU design as a DUT to introduce the concept of > cross coverage of the two input registers in order to test all the > combinations, but why then not a two 'for loop' to generate all the cases: > > > > -- ACov is variable of CovPType > for i in reg1'range loop > for j in reg2'range loop > DoAluOp(i, j); -- do transaction > ACov.ICover((reg1, reg2)); -- collect coverage > end loop; > end loop; > > > > The webinar goes on on how you can optimize the coverage using what they > call 'intelligent coverage' which focuses on holes coverage. > > Would the for loop above be less efficient than the intelligent cross > coverage proposed (in terms of simulation cycles)? > > Moreover the 'intelligent coverage' is fulfilled with the call: > > ACov.AddCross(2, GenBin(0,7), GenBin(0,7) ); > > where the first parameter is an 'AtLeast' parameter. Shouldn't it be > 'AtMost'??? If you want each cross case to be hit not more than a > certain amount of time (to reduce the 'logN' factor of a randomly > generated pair of values) than I do not see why you have to specify an > 'AtLeast' parameter... Am I missing something? > > As a general comment, wouldn't it be more appropriate to find a better > suited example to show the real power of cross coverage [1]? > > Any pointer to freely available code that illustrates the usage of > OS-VVM is extremely helpful. > > Cheers, > > Al > > [1] I do not have any to provide and I'm willing to see what is the real > advantage about having the bins randomly filled instead of sequentially > filled with direct cases. > From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <51f666c0$0$1691$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: if statement problem Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 14:57:36 +0200 References: <3f9492bc-923a-4001-a108-e81cb1c5bc1f@googlegroups.com> <154e7549-a314-4806-8425-4d53b2e1cc27@googlegroups.com> <41e401e0-86eb-4e75-b592-b0c1b7511e36@googlegroups.com> <51f00c0c$0$26779$862e30e2@ngroups.net> <5730aa0e-dc1d-4c03-9e6d-364bf3913363@googlegroups.com> <283d00b6-af51-4a80-a075-21233d37327a@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 34 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1375102656 dreader35.news.xs4all.nl 1691 puiterl/195.242.97.150:58100 Xref: news.eternal-september.org comp.lang.vhdl:6864 lokesh kumar wrote: > > entity squr_5bit is > Port ( a : in STD_LOGIC_VECTOR (4 downto 0); > c : out STD_LOGIC_VECTOR (8 downto 0)); > end squr_5bit; > > architecture Behavioral of squr_5bit is > signal b : STD_LOGIC_VECTOR (8 downto 0); > signal temp : STD_LOGIC_VECTOR (8 downto 0); > begin > position_even_b: for i in 0 to 4 generate b(2*i) <= a(i); > end generate; > c <= b; > position_odd_b: for i in 0 to 3 generate b(2*i+1) <= '0'; > end generate; > > -- position_c:for i in 8 downto 5 loop > --if b(i) = '1' then > --(temp(i) downto temp (i-5)) <= (b(i) downto b(i-5)) xor "100101"; > -- else if b(i) = '0'; > --null; > --end if; > --end loop; > --c <= (temp(4) downto temp(0)); > end Behavioral; If you want a slice of a vector, it is temp(4 downto 0) instead of (temp(4) downto temp(0)). -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:04 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <51f66808$0$1710$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: elevator controller Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 15:03:04 +0200 References: <411365a9-5544-4e8a-accd-a16a828df74a@googlegroups.com> <9eab1a07-776d-4139-8b94-dadac79b2558@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 15 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1375102984 dreader35.news.xs4all.nl 1710 puiterl/195.242.97.150:58134 Xref: news.eternal-september.org comp.lang.vhdl:6865 asuraseed@gmail.com wrote: > Anyone keen to help out? No. Since firstly you did not pose a question in your first post and secondly the relevance with VHDL is missing. We are not here to do your homework. Please start digging in into this assignment yourself and if you have any problems regarding your implementation in VHDL feel free to come back. -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.137.137 with SMTP id w9mr51714493qat.6.1375151721005; Mon, 29 Jul 2013 19:35:21 -0700 (PDT) X-Received: by 10.49.81.208 with SMTP id c16mr831011qey.34.1375151720978; Mon, 29 Jul 2013 19:35:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no95615qan.0!news-out.google.com!ce7ni20qab.0!nntp.google.com!fx3no95866qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 19:35:20 -0700 (PDT) In-Reply-To: <84b244e3-80b5-4699-aee8-09ea67abe99a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <84b244e3-80b5-4699-aee8-09ea67abe99a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Change record elements From: KJ Injection-Date: Tue, 30 Jul 2013 02:35:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2408 Xref: news.eternal-september.org comp.lang.vhdl:6866 On Monday, July 29, 2013 4:36:02 AM UTC-4, hssig wrote: > Hi, I want to divide all elements of a record by 2. How can I perform tha= t=20 > in a kind of loop?=20 > type typeMine is record=20 > a : natural; > b : natural; > c : positive; > d : integer > ... end record; You can't iterate through the elements of a record so you can't do exactly = what you're asking. However, if all of your elements are integers of the same range (yours are = all integers but not of the same range), then you could consider that your = 'record' is simply a vector of integers. If you're using the record type a= s a way to make the usage clearer (i.e. xx.a means something whereas xx(0) = isn't quite so informative) then there is another approach... type t_my_thing_of_integers is(a, b, c, d); type arr_my_integers is array(t_my_thing_of_integers); signal xx: arr_my_integers; Then you would access the elements as xx(a) which from the perspective self= documenting is equivalent to xx.a where xx is a signal of your record type= . Not sure if this alternate usage is along the lines you were looking for or= not since your record elements weren't of the same integer ranges but thou= ght I'd toss it out as food for thought. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:04 2015 X-Received: by 10.224.64.202 with SMTP id f10mr63678747qai.2.1375151819571; Mon, 29 Jul 2013 19:36:59 -0700 (PDT) X-Received: by 10.49.28.66 with SMTP id z2mr2161432qeg.5.1375151819493; Mon, 29 Jul 2013 19:36:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no95822qan.0!news-out.google.com!ce7ni54qab.0!nntp.google.com!f7no95816qan.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 19:36:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <84b244e3-80b5-4699-aee8-09ea67abe99a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2714a4dd-b3d4-4c08-8c5e-e4cfef6cb8ba@googlegroups.com> Subject: Re: Change record elements From: KJ Injection-Date: Tue, 30 Jul 2013 02:36:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6867 On Monday, July 29, 2013 10:35:20 PM UTC-4, KJ wrote: In the above post, should be type arr_my_integers is array(t_my_thing_of_integers) of integer; From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.137.137 with SMTP id w9mr52573514qat.6.1375166921934; Mon, 29 Jul 2013 23:48:41 -0700 (PDT) X-Received: by 10.49.13.169 with SMTP id i9mr851026qec.18.1375166921874; Mon, 29 Jul 2013 23:48:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news1.as3257.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit4.readnews.com!209.85.216.87.MISMATCH!f7no119473qan.0!news-out.google.com!ce7ni20qab.0!nntp.google.com!fx3no120642qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jul 2013 23:48:41 -0700 (PDT) In-Reply-To: <2714a4dd-b3d4-4c08-8c5e-e4cfef6cb8ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <84b244e3-80b5-4699-aee8-09ea67abe99a@googlegroups.com> <2714a4dd-b3d4-4c08-8c5e-e4cfef6cb8ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3aaba28c-6203-4e02-b921-01a15f333b4e@googlegroups.com> Subject: Re: Change record elements From: hssig Injection-Date: Tue, 30 Jul 2013 06:48:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6868 Hi Kevin, thank you for your solution. Cheers, hssig From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: managing vhdl projects with Makefiles Date: Fri, 02 Aug 2013 15:52:24 +0200 Lines: 39 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Wtz5RfiVm4P9dEFnZJHgyQsZtAx2m5V2KkDVSfZ1dhfOEhjr7E Cancel-Lock: sha1:gOdg5ZQkZiJfLNQc76de5daW98o= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6869 Hi everyone, this is another attempt to switch to a completely batched mode to manage my vhdl projects. The rationale behind is that I'd like to get a directory structure for my projects that is tool independent and I'd like to use Makefiles to handle vhdl dependencies and development phases (simulation, synthesis, p&r, ...). I have read several articles on this subject but none of them was presenting an end-to-end flow for an example design and I every time struggled a lot trying to put everything together [1]. I know about 'vmk' tool, but to be honest I haven't found any additional information on top of the man page. If anyone here is regularly using it I'd appreciate some examples. At Cern it has been developed an 'hdlmake' tool to generate makefiles and much more (like downloading stuff from remote repositories or launching simulations/synthesis on remote servers), but to be honest I prefer tools that "do one thing and to it well". I know that OpenCores.org is striving for a standard structure for projects and it qualifies some of them as 'Certified Projects' (OCCP) if they obey to certain rules, including having make-scripts. But to be honest I lost my way several times in the past. Any suggestion/comment is welcome. Al [1] OT: I have to say that I've been lacking 'laziness' recently and this is one of the main reasons why I'm still stuck with this silly business! -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: Fri, 2 Aug 2013 09:01:55 -0700 Organization: Highland Technology, Inc. Lines: 48 Message-ID: <20130802090155.57dc27d8@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="12223"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18mSQtpuuAQTyicANFNXxdq" X-Newsreader: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Cancel-Lock: sha1:ToIl5vURdCDcq7VQz+Q0z5G4rhQ= Xref: news.eternal-september.org comp.lang.vhdl:6870 On Fri, 02 Aug 2013 15:52:24 +0200 alb wrote: > Hi everyone, > > this is another attempt to switch to a completely batched mode to manage > my vhdl projects. The rationale behind is that I'd like to get a > directory structure for my projects that is tool independent and I'd > like to use Makefiles to handle vhdl dependencies and development phases > (simulation, synthesis, p&r, ...). > > I have read several articles on this subject but none of them was > presenting an end-to-end flow for an example design and I every time > struggled a lot trying to put everything together [1]. > > I know about 'vmk' tool, but to be honest I haven't found any additional > information on top of the man page. If anyone here is regularly using it > I'd appreciate some examples. > > At Cern it has been developed an 'hdlmake' tool to generate makefiles > and much more (like downloading stuff from remote repositories or > launching simulations/synthesis on remote servers), but to be honest I > prefer tools that "do one thing and to it well". > > I know that OpenCores.org is striving for a standard structure for > projects and it qualifies some of them as 'Certified Projects' (OCCP) if > they obey to certain rules, including having make-scripts. But to be > honest I lost my way several times in the past. > > Any suggestion/comment is welcome. > I've seen those same tools, and given them brief consideration, but at the end of the day I go back to GNU make. I don't want some specialized make tool that cares whether I'm writing HDL, C, or anything else. That said, dependencies are a horror, and I've found no consistent way to do it across target platforms; my Xilinx makefiles look entirely different than my Altera ones, and both of them have serious limitations relating the source files to the project. The Altera stuff is particularly touchy; I've found that in order to do anything meaningful with makefiles I wind up needing to have supplemental Tcl scripts that my makefile calls through quartus_sh. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail From: Theo Markettos Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: 02 Aug 2013 17:51:42 +0100 (BST) Organization: University of Cambridge, England Lines: 37 Message-ID: References: NNTP-Posting-Host: chiark.greenend.org.uk X-Trace: chiark.greenend.org.uk 1375462304 22721 212.13.197.229 (2 Aug 2013 16:51:44 GMT) X-Complaints-To: abuse@chiark.greenend.org.uk NNTP-Posting-Date: Fri, 2 Aug 2013 16:51:44 +0000 (UTC) User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.32-5-686-bigmem (i686)) Originator: theom@chiark.greenend.org.uk ([212.13.197.229]) Xref: news.eternal-september.org comp.lang.vhdl:6871 alb wrote: > Hi everyone, > > this is another attempt to switch to a completely batched mode to manage > my vhdl projects. The rationale behind is that I'd like to get a > directory structure for my projects that is tool independent and I'd > like to use Makefiles to handle vhdl dependencies and development phases > (simulation, synthesis, p&r, ...). What vendor are you using? That's the biggest question here, rather than the HDL side. We have makefiles for Altera that will: Checkout any component repositories needed by the project Build Bluespec -> Verilog [or run the Bluespec simulator] Run Qsys to generate Altera's Verilog IP (including some of the B->V output) Synthesise the Verilog in Quartus Download to an FPGA Load the FPGA memory/flash/etc Each step is only a few lines, so don't need a special tool, but they're fairly Altera- and project- specific. Up to source code level the directory structure isn't really important, and then the structure is set by the synthesis tools. Bluespec figures out the children of a component so we don't have to list them in the makefile, and the Altera project files (either Qsys or Quartus) itemise the components, so we don't have to specify that in the makefile either. The main part of the work is working out the incantations to run tools from the command line not via the GUI (and make them obey dependencies). I'm not as familiar with VHDL as I am with Verilog, but I don't think there's much different that would apply to VHDL here (some of Altera's IP is in VHDL, but it doesn't affect the build process). Theo From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.103.68 with SMTP id j4mr12848928qao.8.1375493995955; Fri, 02 Aug 2013 18:39:55 -0700 (PDT) X-Received: by 10.49.117.165 with SMTP id kf5mr324712qeb.12.1375493995911; Fri, 02 Aug 2013 18:39:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no560888qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no596607qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Aug 2013 18:39:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question on combining if rising_edge(clk). From: KJ Injection-Date: Sat, 03 Aug 2013 01:39:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3107 Xref: news.eternal-september.org comp.lang.vhdl:6872 On Wednesday, July 17, 2013 12:25:21 PM UTC-4, Andy wrote: > Also, the implicit wait statement in a process with a sensitivity list is= at the=20 > BOTTOM of the process, not at the top. No real difference for synthesis, = but there > are differences in simulation: all processes run at startup, regardless o= f the > sensitivity list. Wait statements will not trigger at startup.=20 Don't think so. Consider this simple case Original code... ORIG_PROC : process(clock) begin if rising_edge(clock) then a <=3D '0'; end if; end process; Implemented with the wait at the start of the process where it belongs... WAIT_AT_TOP_PROC : process begin wait until rising_edge(clock); a <=3D '0'; end process; Implemented with the wait at the bottom where you said it belongs... WAIT_AT_END_PROC : process begin a <=3D '0'; wait until rising_edge(clock); end process; At t=3D0, all three processes trigger. ORIG_PROC and WAIT_AT_TOP_PROC will= not assign any new value to signal 'a' so it will remain 'U' because even = though there is an implicit 'event' to cause the process to trigger, the co= ndition 'rising_edge(clock)' will not be true so ORIG_PROC will complete an= d exit, 'WAIT_AT_TOP_PROC' will suspend until the rising edge condition is = met. Both processes will wake up at the next event on 'clock'. However, W= AIT_AT_END_PROC will assign '0' to signal 'a' and then suspend therefore WA= IT_AT_END_PROC is not equivalent to the original 'ORIG_PROC'. As you stated, there will be no synthesis differences and there will be sim= ulation differences but the incorrect one is when you put the wait statemen= t at the end of the process. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Sat, 03 Aug 2013 00:37:36 -0400 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 3 Aug 2013 04:31:08 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="e9e50b53612a5b684d85b5a1aa7c3313"; logging-data="20049"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+1GNeGxwxpi1dgA1hl8yb8" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:qIHjlHgl/LTNbrqyheeU9gkHLLY= Xref: news.eternal-september.org comp.lang.vhdl:6873 On 8/2/2013 9:39 PM, KJ wrote: > On Wednesday, July 17, 2013 12:25:21 PM UTC-4, Andy wrote: >> Also, the implicit wait statement in a process with a sensitivity list is at the >> BOTTOM of the process, not at the top. No real difference for synthesis, but there >> are differences in simulation: all processes run at startup, regardless of the >> sensitivity list. Wait statements will not trigger at startup. > > Don't think so. Consider this simple case > > Original code... > > ORIG_PROC : process(clock) > begin > if rising_edge(clock) then > a<= '0'; > end if; > end process; > > Implemented with the wait at the start of the process where it belongs... > > WAIT_AT_TOP_PROC : process > begin > wait until rising_edge(clock); > a<= '0'; > end process; > > Implemented with the wait at the bottom where you said it belongs... > > WAIT_AT_END_PROC : process > begin > a<= '0'; > wait until rising_edge(clock); > end process; Your analysis is faulty. The wait until rising_edge statement is not equivalent to the if rising_edge statement in the process with a sensitivity list. This can be seen in the case where the process includes a second trigger in the sensitivity list like a reset. The IF statement prevents the code within from being executed when the process runs unless the process was triggered by the rising edge of the clock. > At t=0, all three processes trigger. ORIG_PROC and WAIT_AT_TOP_PROC will not assign any new value to signal 'a' so it will remain 'U' because even though there is an implicit 'event' to cause the process to trigger, the condition 'rising_edge(clock)' will not be true so ORIG_PROC will complete and exit, 'WAIT_AT_TOP_PROC' will suspend until the rising edge condition is met. Both processes will wake up at the next event on 'clock'. However, WAIT_AT_END_PROC will assign '0' to signal 'a' and then suspend therefore WAIT_AT_END_PROC is not equivalent to the original 'ORIG_PROC'. The WAIT_AT_TOP_PROC and WAIT_AT_END_PROC processes still need an IF statement wrapping the assignment statement. > As you stated, there will be no synthesis differences and there will be simulation differences but the incorrect one is when you put the wait statement at the end of the process. I think there will be no differences seen in simulation. Am I wrong with my view? -- Rick From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.64.202 with SMTP id f10mr14670657qai.2.1375522044922; Sat, 03 Aug 2013 02:27:24 -0700 (PDT) X-Received: by 10.49.36.199 with SMTP id s7mr339645qej.17.1375522044898; Sat, 03 Aug 2013 02:27:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no581398qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no619026qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Aug 2013 02:27:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.210.142.162; posting-account=iESOMQoAAACXEEKUmGCCRrNO_51JL7Al NNTP-Posting-Host: 85.210.142.162 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2f642689-8058-43b2-ba83-d6d8f4dceb03@googlegroups.com> Subject: Re: managing vhdl projects with Makefiles From: pault.eg@googlemail.com Injection-Date: Sat, 03 Aug 2013 09:27:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 43 Xref: news.eternal-september.org comp.lang.vhdl:6874 Yes, batch mode and tool independence, that's something I'd like as well. B= ut not make files. You can see my efforts in this area here: http://pdt.github.io/ttask.html and more details (with GHDL, but mostly applies to other sims) here: http://pdt.github.io/ghdl_extension.html ttask is something that I'm currently working on, and at the moment it only= supports simulation, (Modelsim, Xilinx, GHDL, iverilog), although my plan = is to add support for other phases in FPGA development as well. Basically, you tell it type of project (e.g. modelsim, xilinx-isim, etc), w= here your source files are (i.e. you don't have to conform to a pre-defined= layout), and you tell it some build properties (e.g. build directory, numb= er of simulation threads (which has an impact on how many licenses get chec= ked out **)), then you run tasks for running simulations. Note that it is only version 0.5, so I'm still adding functionality and I'd= wager it has plenty of rough edges as well.=20 For other phases of FPGA development, I did start to add support for Xilinx= ISE, but I abandoned it to focus my efforts on the simulators. There is xi= linx-ise.tcl file in the source tree, but that's way, way out of date, to t= he extent that it's completely broken, hence you won't find any documentati= on for it. My plan is to fix it, and add support for altera tools, etc.=20 Paul. ** for paid tools, the free ones including modelsim altera and Xilinx webpa= ck are happy to run parallel simulations. Note also that I'm primarily developing this under Linux, and all my tests = work there. I do run it under Windows however as well, but just the Windows= version of Vivado has a bug in it which currently stops my scripts working= with it... but I'll fix that and get round to reporting the Vivado bug (xv= hdl -work lib=3Ddir doesn't seem to work). =20 From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.163.14 with SMTP id y14mr15841556qax.3.1375541544063; Sat, 03 Aug 2013 07:52:24 -0700 (PDT) X-Received: by 10.49.86.39 with SMTP id m7mr159219qez.37.1375541544026; Sat, 03 Aug 2013 07:52:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no598133qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no637021qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Aug 2013 07:52:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6dcdf12a-0a2c-447c-a63b-5e701fb4fc43@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: KJ Injection-Date: Sat, 03 Aug 2013 14:52:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 57 Xref: news.eternal-september.org comp.lang.vhdl:6875 On Saturday, August 3, 2013 12:37:36 AM UTC-4, rickman wrote: > Your analysis is faulty. The wait until rising_edge statement is not=20 > equivalent to the if rising_edge statement in the process with a=20 > sensitivity list. =20 My analysis is correct, you're misreading the post. The point that I was r= esponding to from Andy is simply his statement about the placement of the w= ait statement being at the bottom of the process rather than the top (that = portion of Andy's post is the only thing shown in my post, the rest of his = post was snipped). To prove, I offered up a sample process 'ORIG_PROC' and= two alternate processes, one with the wait statement at the top, the other= at the bottom. I believe I fairly represented what Andy was proposing wit= h his statement about 'top' and 'bottom' of the process as being the locati= on of the wait statement. If either alternate behaves differently from 'ORIG_PROC', then it is not eq= uivalent to 'ORIG_PROC' process. I then went on to explain why the two alt= ernatives simulate differently to prove that one way is equivalent to 'ORIG= _PROC' and the other one is not. If you don't believe it then don't debate= the point, simply copy/paste my code and simulate it. > This can be seen in the case where the process=20 > includes a second trigger in the sensitivity list like a reset. The IF= =20 > statement prevents the code within from being executed when the process= =20 > runs unless the process was triggered by the rising edge of the clock.=20 That's your point not mine. > > At t=3D0, all three processes trigger. ORIG_PROC and WAIT_AT_TOP_PROC= =20 > > will not assign > any new value to signal 'a' so it will remain 'U'=20 > > because even though there is an > implicit 'event' to cause the=20 > > process to trigger, the condition 'rising_edge(clock)' will not be=20 > > true so ORIG_PROC will complete and exit, 'WAIT_AT_TOP_PROC' will=20 > > suspend until the rising edge condition is met. Both processes will=20 > > wake up at the next event on 'clock'. However, WAIT_AT_END_PROC will > > assign '0' to signal 'a' and then suspend therefore WAIT_AT_END_PROC=20 > > is not equivalent to the original 'ORIG_PROC'.=20 > The WAIT_AT_TOP_PROC and WAIT_AT_END_PROC processes still need an IF=20 > statement wrapping the assignment statement.=20 No they do not. > > As you stated, there will be no synthesis differences and there will be= simulation differences but the incorrect one is when you put the wait stat= ement at the end of the process.=20 > I think there will be no differences seen in simulation. Am I wrong=20 > with my view?=20 Yes you are wrong. Try it in a simulator if you're curious. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Newbie question on combining if rising_edge(clk). Date: Sat, 03 Aug 2013 22:47:28 -0400 Organization: A noiseless patient Spider Lines: 67 Message-ID: References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <6dcdf12a-0a2c-447c-a63b-5e701fb4fc43@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 4 Aug 2013 02:41:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="24888"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dAXRqRQQhshAzEu+1Y5V8" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <6dcdf12a-0a2c-447c-a63b-5e701fb4fc43@googlegroups.com> Cancel-Lock: sha1:pUiIYXwV+XCWY5+fUIm/JC2Ut94= Xref: news.eternal-september.org comp.lang.vhdl:6876 On 8/3/2013 10:52 AM, KJ wrote: > On Saturday, August 3, 2013 12:37:36 AM UTC-4, rickman wrote: >> Your analysis is faulty. The wait until rising_edge statement is not >> equivalent to the if rising_edge statement in the process with a >> sensitivity list. > > My analysis is correct, you're misreading the post. The point that I was responding to from Andy is simply his statement about the placement of the wait statement being at the bottom of the process rather than the top (that portion of Andy's post is the only thing shown in my post, the rest of his post was snipped). To prove, I offered up a sample process 'ORIG_PROC' and two alternate processes, one with the wait statement at the top, the other at the bottom. I believe I fairly represented what Andy was proposing with his statement about 'top' and 'bottom' of the process as being the location of the wait statement. > > If either alternate behaves differently from 'ORIG_PROC', then it is not equivalent to 'ORIG_PROC' process. I then went on to explain why the two alternatives simulate differently to prove that one way is equivalent to 'ORIG_PROC' and the other one is not. If you don't believe it then don't debate the point, simply copy/paste my code and simulate it. > >> This can be seen in the case where the process >> includes a second trigger in the sensitivity list like a reset. The IF >> statement prevents the code within from being executed when the process >> runs unless the process was triggered by the rising edge of the clock. > > That's your point not mine. The point illustrates a case where the process was run other than on the rising edge of the clock and the code within the IF rising_edge... was not executed. If you can't explain how this is not like the situation you are describing then you point must not be correct. >>> At t=0, all three processes trigger. ORIG_PROC and WAIT_AT_TOP_PROC >>> will not assign> any new value to signal 'a' so it will remain 'U' >>> because even though there is an> implicit 'event' to cause the >>> process to trigger, the condition 'rising_edge(clock)' will not be >>> true so ORIG_PROC will complete and exit, 'WAIT_AT_TOP_PROC' will >>> suspend until the rising edge condition is met. Both processes will >>> wake up at the next event on 'clock'. However, WAIT_AT_END_PROC will >>> assign '0' to signal 'a' and then suspend therefore WAIT_AT_END_PROC >>> is not equivalent to the original 'ORIG_PROC'. > > >> The WAIT_AT_TOP_PROC and WAIT_AT_END_PROC processes still need an IF >> statement wrapping the assignment statement. > > No they do not. "No they do not"? Taht's the sum total of your explanation? The location of the wait statement does not alter the rest of the logic. Why would the effective location of the wait statement alter the effect of the IF statement? That makes no sense and contradicts everything I have learned about the language. >>> As you stated, there will be no synthesis differences and there will be simulation differences but the incorrect one is when you put the wait statement at the end of the process. > > >> I think there will be no differences seen in simulation. Am I wrong >> with my view? > > Yes you are wrong. Try it in a simulator if you're curious. I will try this when I get the chance. But you have explained nothing that would make me think you are right. The IF statement will always operate. The fact that the process is run has nothing to do with the execution of the code within the IF statement when the process was not run because of a rising edge on the clock. Just tell me how the assignment statements within the IF (rising_edge(clock)) THEN ... ENDIF will be executed if rising_edge(clock) does not return TRUE? -- Rick From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.64.202 with SMTP id f10mr21076392qai.2.1375629536679; Sun, 04 Aug 2013 08:18:56 -0700 (PDT) X-Received: by 10.49.5.162 with SMTP id t2mr444267qet.24.1375629536631; Sun, 04 Aug 2013 08:18:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no685156qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no729018qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 08:18:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> <6dcdf12a-0a2c-447c-a63b-5e701fb4fc43@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <002082de-202f-409c-8842-b78d51b3ae4f@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: KJ Injection-Date: Sun, 04 Aug 2013 15:18:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 6246 Xref: news.eternal-september.org comp.lang.vhdl:6877 On Saturday, August 3, 2013 10:47:28 PM UTC-4, rickman wrote: >>> This can be seen in the case where the process=20 >>> includes a second trigger in the sensitivity list like a reset. The IF= =20 >>> statement prevents the code within from being executed when the process= =20 >>> runs unless the process was triggered by the rising edge of the clock.= =20 >>=20 >> That's your point not mine.=20 > > >The point illustrates a case where the process was run other than on the= =20 >rising edge of the clock and the code within the IF rising_edge... was=20 >not executed. Again, that is your point not mine. The entire scope of my point was simpl= y correcting a statement that Andy had made regarding the placement of a wa= it statement in a process. You keep wanting to expand it into something el= se entirely. =20 > If you can't explain how this is not like the situation=20 > you are describing then you point must not be correct.=20 > Wow...you have a low standard of proof if someone describing something (or = not) is the differentiator for whether or not a point "must not be correct"= . Andy made a point. I provided working example code snippet that anyone with= a simulator can test and verify refutes his statement. I quoted only Andy= 's statement that I was refuting, not the entire rest of the post to give t= he proper context. That's the way the scientific method works. Your stand= ard of "If you can't explain how..." is the art of politics. But in any ca= se, my first posting did describe exactly why as well. > >>>> At t=3D0, all three processes trigger. ORIG_PROC and WAIT_AT_TOP_PROC= =20 >>>> will not assign any new value to signal 'a' so it will remain 'U'=20 >>>> because even though there is an> implicit 'event' to cause the=20 >>>> process to trigger, the condition 'rising_edge(clock)' will not be=20 >>>> true so ORIG_PROC will complete and exit, 'WAIT_AT_TOP_PROC' will=20 >>>> suspend until the rising edge condition is met. Both processes will= =20 >>>> wake up at the next event on 'clock'. However, WAIT_AT_END_PROC will= =20 >>>> assign '0' to signal 'a' and then suspend therefore WAIT_AT_END_PROC= =20 >>>> is not equivalent to the original 'ORIG_PROC'.=20 >>=20 >>=20 >>> The WAIT_AT_TOP_PROC and WAIT_AT_END_PROC processes still need an IF=20 >>> statement wrapping the assignment statement.=20 >>=20 >> No they do not.=20 > > >"No they do not"? Taht's the sum total of your explanation? The=20 >location of the wait statement does not alter the rest of the logic.=20 >Why would the effective location of the wait statement alter the effect=20 >of the IF statement? That makes no sense and contradicts everything I=20 >have learned about the language.=20 > Do you even read what you're quoting from someone else before you decide to= post? Please read what is quoted with all the ">>>>" above that you yours= elf included as part of your post. THAT is a pretty fair explanation. Tha= t was in my first post. >>=20 >> I think there will be no differences seen in simulation. Am I wrong=20 >> with my view?=20 >=20 > Yes you are wrong. Try it in a simulator if you're curious.=20 >I will try this when I get the chance. But you have explained nothing=20 >that would make me think you are right. I have explained it, you don't understand the explanation. I'm not going t= o explain again since I also provided working code to demonstrate the point= so that anyone can test it out to verify. I also clearly stated that it w= ould be better to simply simulate it rather than debate the point, but appa= rently you would rather debate. I'm done debating since you won't take the= minimal amount of time it would take to actually verify using the live wor= king code snippets that I provided. Stop being lazy. If you would take the time, what you would find is that between t=3D0 and t= he time of the first rising edge of the clock, the process with the wait st= atement at the end of the process (as I believe Andy would claim it should = be placed) would not behave the same as the original process ('ORIG_PROC').= The process with the wait statement at the begining (which Andy in his po= st was saying was wrong) does behave the same. My example disproves his statement. It doesn't go any further. Maybe you = don't care between t=3D0 and the first rising edge, but that's not relevant= . =20 >Just tell me how the assignment statements within the IF=20 >(rising_edge(clock)) THEN ... ENDIF will be executed if=20 >rising_edge(clock) does not return TRUE?=20 You have posted no code, I'm not going to write it for you. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.64.202 with SMTP id f10mr21462306qai.2.1375636222675; Sun, 04 Aug 2013 10:10:22 -0700 (PDT) X-Received: by 10.49.30.135 with SMTP id s7mr262403qeh.19.1375636222621; Sun, 04 Aug 2013 10:10:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no736359qab.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no736356qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 10:10:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> Subject: Both transitions of CLOCK From: Christiano Injection-Date: Sun, 04 Aug 2013 17:10:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 29 Xref: news.eternal-september.org comp.lang.vhdl:6878 In the book of Volnei pedroni in section 6.9 (bad Clocking) it shows that the optimal code for a circuit that works for Both transitions of CLOCK is the one below: process(clk) begin if(clk'event and clk='1') then x <= d; end if; end process; process(clk) begin if(clk'event and clk='0') then y <= d; end if; end process; However, it would not be correct to write the form below? process(clk) begin if(clk'event and clk='1') then x <= d; end if; if(clk'event and clk='0') then y <= d; end if; end process; From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.69.6 with SMTP id x6mr21710305qai.0.1375640099064; Sun, 04 Aug 2013 11:14:59 -0700 (PDT) X-Received: by 10.49.97.72 with SMTP id dy8mr10315qeb.11.1375640098977; Sun, 04 Aug 2013 11:14:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no696117qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no740491qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 11:14:58 -0700 (PDT) In-Reply-To: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> Subject: Re: Both transitions of CLOCK From: KJ Injection-Date: Sun, 04 Aug 2013 18:14:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6879 On Sunday, August 4, 2013 1:10:22 PM UTC-4, Christiano wrote: > However, it would not be correct to write the form below? Yes, both forms are equivalent. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.171.72 with SMTP id g8mr22200602qaz.7.1375648892402; Sun, 04 Aug 2013 13:41:32 -0700 (PDT) X-Received: by 10.50.101.110 with SMTP id ff14mr261972igb.9.1375648892254; Sun, 04 Aug 2013 13:41:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!f7no706016qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no751152qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 13:41:31 -0700 (PDT) In-Reply-To: <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.137.27.140; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.137.27.140 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Both transitions of CLOCK From: Daniel Kho Injection-Date: Sun, 04 Aug 2013 20:41:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6880 I have been trying to get at least one synthesis tool vendor to support the= following equivalent forms: /* Alternate form 1. */ process(clk) is begin if rising_edge(clk) then x<=3Dd; end if; end process; process(clk) is begin if falling_edge(clk) then y<=3Dd; end if; end process; q<=3Dx xor y; OR /* Alternate form 2. */ process(clk) is begin if rising_edge(clk) or falling_edge(clk) then q<=3Dd; end if; end process; You already mentioned 2 other equivalent forms (and confirmed by KJ). My "A= lternate Form 1" is similar to the first code you posted (there's a paper b= y Ralf Hildebrandt that described this in detail). I believe there may be o= ther forms as well. However AFAIK, only these forms (Alt Form 1 & your firs= t code) are supported well by all major synthesis vendors. The rest may be = supported by some but not supported by others. However, for simulation, all= of these forms should work fine. If you plan to synthesize your code, then help request your synthesis vendo= rs to support these alternative forms of dual-edge clocking. :) -daniel From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.163.14 with SMTP id y14mr22250802qax.3.1375649281246; Sun, 04 Aug 2013 13:48:01 -0700 (PDT) X-Received: by 10.50.40.103 with SMTP id w7mr186005igk.7.1375649281213; Sun, 04 Aug 2013 13:48:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no706507qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no751704qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 13:48:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.137.27.140; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.137.27.140 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a769f64-3eb6-4b7b-9565-7c20f97e0e39@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Daniel Kho Injection-Date: Sun, 04 Aug 2013 20:48:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6881 On Monday, 5 August 2013 04:41:31 UTC+8, Daniel Kho wrote: > I have been trying to get at least one synthesis tool vendor to support t= he following equivalent forms: >=20 Sorry, I meant I've been trying to get them to support Alternate Form 2 - t= he first form I posted (Alternate Form 1) is already well supported. They s= hould also support multiple clock statements within the same process (like = the example you posted), but I did not have much luck convincing them the l= ast time. Things might have changed since then - I haven't took the time to= see if the latest tools work, but my gut tells me the tools are pretty muc= h the same as they were a few years ago (in this regard). From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.172.68 with SMTP id k4mr22854975qaz.1.1375659881190; Sun, 04 Aug 2013 16:44:41 -0700 (PDT) X-Received: by 10.49.127.207 with SMTP id ni15mr464519qeb.15.1375659881175; Sun, 04 Aug 2013 16:44:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no718387qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no764625qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 16:44:41 -0700 (PDT) In-Reply-To: <0a769f64-3eb6-4b7b-9565-7c20f97e0e39@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <0a769f64-3eb6-4b7b-9565-7c20f97e0e39@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <23640ab5-f3fb-4a7c-81fa-ec8a73d6d7dd@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Christiano Injection-Date: Sun, 04 Aug 2013 23:44:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 19 Xref: news.eternal-september.org comp.lang.vhdl:6882 On Sunday, August 4, 2013 5:48:00 PM UTC-3, Daniel Kho wrote: > On Monday, 5 August 2013 04:41:31 UTC+8, Daniel Kho wrote: >=20 > > I have been trying to get at least one synthesis tool vendor to support= the following equivalent forms: >=20 > >=20 >=20 >=20 >=20 > Sorry, I meant I've been trying to get them to support Alternate Form 2 -= the first form I posted (Alternate Form 1) is already well supported. They= should also support multiple clock statements within the same process (lik= e the example you posted), but I did not have much luck convincing them the= last time. Things might have changed since then - I haven't took the time = to see if the latest tools work, but my gut tells me the tools are pretty m= uch the same as they were a few years ago (in this regard). Your Alternate form 2 has a problem that is described in the book of Pedron= i. The technology of the flip flop usually only allows one edge. From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.64.202 with SMTP id f10mr22983633qai.2.1375661968095; Sun, 04 Aug 2013 17:19:28 -0700 (PDT) X-Received: by 10.49.127.207 with SMTP id ni15mr465509qeb.15.1375661968051; Sun, 04 Aug 2013 17:19:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no720525qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no766768qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 17:19:27 -0700 (PDT) In-Reply-To: <23640ab5-f3fb-4a7c-81fa-ec8a73d6d7dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <0a769f64-3eb6-4b7b-9565-7c20f97e0e39@googlegroups.com> <23640ab5-f3fb-4a7c-81fa-ec8a73d6d7dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <586613f6-8b7e-4d02-b013-63f7d1ca6f70@googlegroups.com> Subject: Re: Both transitions of CLOCK From: KJ Injection-Date: Mon, 05 Aug 2013 00:19:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 11 Xref: news.eternal-september.org comp.lang.vhdl:6883 On Sunday, August 4, 2013 7:44:41 PM UTC-4, Christiano wrote: > Your Alternate form 2 has a problem that is described in the book of Pedr= oni.=20 > The technology of the flip flop usually only allows one edge. Not true. All of the descriptions so far are assigning to two different si= gnals (x, y). Two signals clocked by different clocks (or different edges = of a single clock) will always be implemented totally independent of each o= ther. Both x and y will be synthesized as simple flip flops. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.103.68 with SMTP id j4mr23296927qao.8.1375668433279; Sun, 04 Aug 2013 19:07:13 -0700 (PDT) X-Received: by 10.49.13.10 with SMTP id d10mr267704qec.28.1375668433256; Sun, 04 Aug 2013 19:07:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no726959qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no773576qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 19:07:13 -0700 (PDT) In-Reply-To: <586613f6-8b7e-4d02-b013-63f7d1ca6f70@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.143.11.80; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.143.11.80 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <0a769f64-3eb6-4b7b-9565-7c20f97e0e39@googlegroups.com> <23640ab5-f3fb-4a7c-81fa-ec8a73d6d7dd@googlegroups.com> <586613f6-8b7e-4d02-b013-63f7d1ca6f70@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Both transitions of CLOCK From: Daniel Kho Injection-Date: Mon, 05 Aug 2013 02:07:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2066 Xref: news.eternal-september.org comp.lang.vhdl:6884 Yes, the "problem" you are talking about really lies with the tools. If too= ls are smart enough to be able to infer dual-edge-triggered flip-flops, or = pseudo-dual-edge-triggered flip-flops using single-edge-triggered ones, the= n we will have no problems using Alternate Form 2 (or any other alternate f= orms for that matter). In fact, the 2nd code you posted also has the same "= problems" mentioned by Pedroni, but again this problem can be solved if too= l vendors spend more time improving their synthesis engine. If there are any of these forms that you like to use, then request them fro= m your tool vendors. :) From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Both transitions of CLOCK Date: Sun, 04 Aug 2013 23:45:49 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Aug 2013 03:39:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="20431"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/07+0bZmxQaGqvh9cq6SWy" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:7CwYaFOVUEGpbtRt9PvgzSHq8OI= Xref: news.eternal-september.org comp.lang.vhdl:6885 On 8/4/2013 4:41 PM, Daniel Kho wrote: > I have been trying to get at least one synthesis tool vendor to support the following equivalent forms: > > /* Alternate form 1. */ > process(clk) is begin > if rising_edge(clk) then x<=d; end if; > end process; > > process(clk) is begin > if falling_edge(clk) then y<=d; end if; > end process; > > q<=x xor y; There is a problem with this last statement. Using an XOR of x and y does not make q the same as a clocked version of d which would seem to be your goal as shown in the alternate form 2 below. > OR > > /* Alternate form 2. */ > process(clk) is begin > if rising_edge(clk) or falling_edge(clk) then > q<=d; > end if; > end process; > > You already mentioned 2 other equivalent forms (and confirmed by KJ). My "Alternate Form 1" is similar to the first code you posted (there's a paper by Ralf Hildebrandt that described this in detail). I believe there may be other forms as well. However AFAIK, only these forms (Alt Form 1& your first code) are supported well by all major synthesis vendors. The rest may be supported by some but not supported by others. However, for simulation, all of these forms should work fine. > > If you plan to synthesize your code, then help request your synthesis vendors to support these alternative forms of dual-edge clocking. :) The trouble is that there is nothing similar between these two forms. Form 1 registers two signals from the same input signal, but at different times. The XOR operation is a logical function. Form 2 registers the signal d at two edges of the clock to the signal q, but this is not synthesizable directly in a single FF. -- Rick From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.66.218.7 with SMTP id pc7mr6589864pac.18.1375679911149; Sun, 04 Aug 2013 22:18:31 -0700 (PDT) X-Received: by 10.49.6.40 with SMTP id x8mr164637qex.5.1375679910706; Sun, 04 Aug 2013 22:18:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!os3no10688060pbb.0!news-out.google.com!rn2ni9189pbc.1!nntp.google.com!qx7no10997158pbc.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 4 Aug 2013 22:18:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.143.11.80; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.143.11.80 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59aa4fd3-565c-4941-b340-98df840664fc@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Daniel Kho Injection-Date: Mon, 05 Aug 2013 05:18:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6886 > The trouble is that there is nothing similar between these two forms.=20 >=20 Sure, but the first form _emulates_ dual clocking behaviour, though yes, it= is being described as combinatorial logic. This is what is called pseudo-d= ual-edge triggering (as described by Ralf Hildebrandt). If synthesis tools = can infer dual-triggered flip-flops from this (pseudo) description, that wo= uld be nice. (Of course, warn the user that it has optimized the design). The second form assumes there are dual-triggered flip-flops available for u= se, and the synthesis tool is smart enough to be able to instantiate these = resources. Both descriptions are different, but have the same intention (dual-edge clo= cking). -daniel From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: Mon, 05 Aug 2013 12:15:27 +0200 Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net MIhKPapKAGDlbFZdi9UOKQ2zadcXe58SpywDdj3G47HDDHamjz Cancel-Lock: sha1:VwoJ5I7FJzHW3kmtkUi+AX1m4JQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6887 On 02/08/2013 18:51, Theo Markettos wrote: > alb wrote: >> Hi everyone, >> >> this is another attempt to switch to a completely batched mode to manage >> my vhdl projects. The rationale behind is that I'd like to get a >> directory structure for my projects that is tool independent and I'd >> like to use Makefiles to handle vhdl dependencies and development phases >> (simulation, synthesis, p&r, ...). > > What vendor are you using? That's the biggest question here, rather than > the HDL side. I use the Libero-Soc workflow which is using ModelSim and Synplify Pro for simulation and synthesis, while is using Designer for the p&r. In my simple approach I would have rather had a simple Makefile (GNU Make) to handle dependencies but use tcl scripts to handle tool options and the like. Unfortunately I'm not very skilled in tcl yet (read: I do not know tcl yet!) and I would have liked to start from an example rather than starting from scratch. > > We have makefiles for Altera that will: > Checkout any component repositories needed by the project > Build Bluespec -> Verilog > [or run the Bluespec simulator] > Run Qsys to generate Altera's Verilog IP (including some of the B->V output) > Synthesise the Verilog in Quartus > Download to an FPGA > Load the FPGA memory/flash/etc Is you makefile available somewhere? Or any simplified version of it? I understand the steps are pretty tool-dependent but I guess I can skim that part out and fit my need in...hopefully. [] > The main part of the work is working out the incantations to run tools from > the command line not via the GUI (and make them obey dependencies). I've found this article on Microsemi knowledge-base page: http://www.actel.com/kb/article.aspx?id=SL5619 I'll give it a try and see how it goes. From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: Mon, 05 Aug 2013 12:37:09 +0200 Lines: 37 Message-ID: References: <20130802090155.57dc27d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net yFbF4xqXofcaM+tKKPSx0wraCVuA5ldVudTmqek59ey8yAu8kw Cancel-Lock: sha1:b+mIWqgjwbX89RdDN4z4pehW8Rk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <20130802090155.57dc27d8@rg.highlandtechnology.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6888 On 02/08/2013 18:01, Rob Gaddi wrote: [] >> this is another attempt to switch to a completely batched mode to manage >> my vhdl projects. The rationale behind is that I'd like to get a >> directory structure for my projects that is tool independent and I'd >> like to use Makefiles to handle vhdl dependencies and development phases >> (simulation, synthesis, p&r, ...). [] > > I've seen those same tools, and given them brief consideration, but at > the end of the day I go back to GNU make. I don't want some > specialized make tool that cares whether I'm writing HDL, C, or > anything else. IMO what makes vmk interesting is that it analyzes your code base and generates a GNU Makefile to handle dependencies. I'm not sure then how does it handle simulations/synthesis and so on. Well, in my case I should say that I'm not dealing with hundreds of files and I could potentially do a dependency tree by hand, without any additional hassle. But I guess that my laziness prevents me from doing something manually if I can automate it :-). > That said, dependencies are a horror, and I've found no consistent way > to do it across target platforms; my Xilinx makefiles look entirely > different than my Altera ones, and both of them have serious > limitations relating the source files to the project. The Altera stuff > is particularly touchy; I've found that in order to do anything > meaningful with makefiles I wind up needing to have supplemental Tcl > scripts that my makefile calls through quartus_sh. I would imagine though that while dependencies are handled by Makefile rules, then actual tasks can be done by external tcl scripts. Already something similar would make my life way easier than pushing buttons on that silly GUI. From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Both transitions of CLOCK Newsgroups: comp.lang.vhdl References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 05 Aug 2013 11:11:21 GMT Lines: 17 Message-ID: <51ff8859$0$11117$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 162fb103.news.astraweb.com X-Trace: DXC=]mgC@jeV8@C7dZd0V0aUXKL?0kYOcDh@JW\:Hm@YlDbJ\Z=oIO[;=mDA>P\D1Q5L7Hg72:egnKKkA Xref: news.eternal-september.org comp.lang.vhdl:6889 On Sun, 04 Aug 2013 11:14:58 -0700, KJ wrote: > On Sunday, August 4, 2013 1:10:22 PM UTC-4, Christiano wrote: >> However, it would not be correct to write the form below? > > Yes, both forms are equivalent. Whist both forms are equivalent from the point of view of the VHDL language, I recently came across a problem in XST in which it would not give the correct results if both edges were used in the same process. It didn't even give a warning message. It just generated bad code. :( Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Both transitions of CLOCK Date: Mon, 05 Aug 2013 13:14:19 +0200 Lines: 38 Message-ID: References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <59aa4fd3-565c-4941-b340-98df840664fc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 66KjAPFAJJOLBKDFpW07pArG0QjJQqX0TtVpr5ENAoYJdNXjPM Cancel-Lock: sha1:53SG7UmzRFN09PHiiXhuQSCG9cI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <59aa4fd3-565c-4941-b340-98df840664fc@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6890 On 05/08/2013 07:18, Daniel Kho wrote: > Sure, but the first form _emulates_ dual clocking behaviour, though > yes, it is being described as combinatorial logic. This is what is > called pseudo-dual-edge triggering (as described by Ralf > Hildebrandt). I urge you read again the paper you mentioned. The code you posted has nothing to do with pseudo-dual-edge flip-flop (pde_dff). BTW, be aware that in pde_dff timing might be an issue due to the asymmetries between the two paths. Anyway you could write your own procedure to handle this and eventually have something like: pde_dff(clk, nrst, din, dout); If a synthesis tool will be smart enough you'll have it optimized, otherwise you'll have the functional equivalent, enhancing your portability. Consider also that a dual edge triggered clock has a limited use case and it is possible that cost to support such a small niche is not worth the candle... > If synthesis tools can infer dual-triggered flip-flops > from this (pseudo) description, that would be nice. (Of course, warn > the user that it has optimized the design). BTW the FM0 encoding use case presented in the article is rather naive. You need to do phase lock or guarantee your tx and rx are synchronous, so why bothering? Except DDR use, where else is a dual-edge ff nice to have? > Both descriptions are different, but have the same intention > (dual-edge clocking). A xor operation on the same signal clocked at different moment is not the same as presented by RH. From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.7.7 with SMTP id b7mr25587335qab.5.1375706069093; Mon, 05 Aug 2013 05:34:29 -0700 (PDT) X-Received: by 10.49.70.170 with SMTP id n10mr490051qeu.22.1375706069054; Mon, 05 Aug 2013 05:34:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no815349qab.0!news-out.google.com!he10ni633qab.0!nntp.google.com!f7no766586qan.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Aug 2013 05:34:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39c4fa23-6091-4a1f-a110-a7f54ef82245@googlegroups.com> Subject: Re: Newbie question on combining if rising_edge(clk). From: Andy Injection-Date: Mon, 05 Aug 2013 12:34:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2135 Xref: news.eternal-september.org comp.lang.vhdl:6891 Kevin, See ieee std 1076-2008 p.171: If a process sensitivity list appears following the reserved word process, = then the process statement is assumed to contain an implicit wait statement= as the last statement of the process statement part; this implicit wait st= atement is of the form wait on sensitivity_list ; Andy Note that "wait on clk;" and "wait until rising_edge(clk);" are NOT equival= ent. "Wait until rising_edge(clk)" is equivalent to "wait on clk; if rising_edge= (clk) then ... end if;". Since the implicit "wait on clk" is the last state= ment of the process (see above) the if risin_edge(clk) statement would corr= ectly be at the top of the process. Andy From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.69.6 with SMTP id x6mr25639404qai.0.1375706553626; Mon, 05 Aug 2013 05:42:33 -0700 (PDT) X-Received: by 10.49.30.135 with SMTP id s7mr328719qeh.19.1375706553545; Mon, 05 Aug 2013 05:42:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no767270qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no816027qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Aug 2013 05:42:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Andy Injection-Date: Mon, 05 Aug 2013 12:42:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 Xref: news.eternal-september.org comp.lang.vhdl:6892 On Sunday, August 4, 2013 3:41:31 PM UTC-5, Daniel Kho wrote: > I have been trying to get at least one synthesis tool vendor to support the following equivalent forms: I think you meant: Process (clk) begin if rising_edge(clk) then x <= y XOR d; end if; if falling_edge(clk) then y <= x XOR d; end if; end process; q <= x XOR y; Andy From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Both transitions of CLOCK Date: Mon, 05 Aug 2013 10:37:16 -0400 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <59aa4fd3-565c-4941-b340-98df840664fc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Aug 2013 14:30:41 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="2289"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19W362CKd/SA7DG7SbVtRFz" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <59aa4fd3-565c-4941-b340-98df840664fc@googlegroups.com> Cancel-Lock: sha1:4zfLmQE0p3yVHVQDEnbv9FICnyk= Xref: news.eternal-september.org comp.lang.vhdl:6893 On 8/5/2013 1:18 AM, Daniel Kho wrote: >> The trouble is that there is nothing similar between these two forms. >> > Sure, but the first form _emulates_ dual clocking behaviour, though yes, it is being described as combinatorial logic. This is what is called pseudo-dual-edge triggering (as described by Ralf Hildebrandt). If synthesis tools can infer dual-triggered flip-flops from this (pseudo) description, that would be nice. (Of course, warn the user that it has optimized the design). > > The second form assumes there are dual-triggered flip-flops available for use, and the synthesis tool is smart enough to be able to instantiate these resources. > > Both descriptions are different, but have the same intention (dual-edge clocking). I think there is something I am missing in this conversation. I don't know what a dual-triggered flip-flop is. If you mean a single FF that is triggered on both edges of the clock, then this does not exist to the best of my knowledge. If you mean a double data rate circuit like used in memory configurations - that does not combine the data into a single data stream because there is no 2x clock to process the resulting data. +-----+ +-----+ ! Data --+----->|D Q|-------| mux | ! +-----+ | | | | |-------|D Q|---- Data' | +--|> | +--| s | ! | | | | +-----+ | +-----+ ! +-|> | | | | | ! | +-----+ | +-------------(-----+ ! | | | +-----+ | ! | +---(->|D Q|----+ ! | | | | ! | CLK--------+-o|> | ! | +-----+ ! | 2xCLK-----------------------------------+ The logic to the left of the ! line is effectively what your dual-triggered flip-flop would accomplish. But since there is no 2x clock to work with the output from that device, what use is it? You seem to be focusing on synthesis of this dual-triggered flip-flop or pseudo-dual-triggered flip-flop without a context. At least I'm not following how they would be of any value. What is normally done is to clock the two phases of data into two separate streams which are then processed in parallel, much like using a SERDES. The serial data is very high speed, it is shifted into a set of registers and processed in the FPGA as parallel words. -- Rick From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.7.7 with SMTP id b7mr26205728qab.5.1375714931300; Mon, 05 Aug 2013 08:02:11 -0700 (PDT) X-Received: by 10.50.66.134 with SMTP id f6mr414248igt.13.1375714931223; Mon, 05 Aug 2013 08:02:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!f7no778445qan.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no828292qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Aug 2013 08:02:10 -0700 (PDT) In-Reply-To: <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.137.27.140; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.137.27.140 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Daniel Kho Injection-Date: Mon, 05 Aug 2013 15:02:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6894 > I think you meant: > > > > Process (clk) > > begin > > if rising_edge(clk) then x <= y XOR d; end if; > > if falling_edge(clk) then y <= x XOR d; end if; > > end process; > > > > q <= x XOR y; > > > > Andy Andy, yes you got me. :) regards, daniel From newsfish@newsfish Tue Dec 29 16:43:05 2015 X-Received: by 10.224.163.14 with SMTP id y14mr26250683qax.3.1375715243984; Mon, 05 Aug 2013 08:07:23 -0700 (PDT) X-Received: by 10.49.132.5 with SMTP id oq5mr511272qeb.29.1375715243927; Mon, 05 Aug 2013 08:07:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!fx3no828770qab.0!news-out.google.com!a13ni157qay.0!nntp.google.com!fx3no828764qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Aug 2013 08:07:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <070acbc5-612c-4edb-895b-2f246ebbd882@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Newbie question on combining if rising_edge(clk). From: KJ Injection-Date: Mon, 05 Aug 2013 15:07:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6895 On Wednesday, July 17, 2013 12:25:21 PM UTC-4, Andy wrote: > Note that "wait on clk;" and "wait until rising_edge(clk);" are NOT equiv= alent. All of the discussion in the thread had been about using some form of "wait= until rising_edge(clk);" not "wait on clk;" as a replacement for "if risin= g_edge(clk)". What it comes down to then is the code that I posted for 'WA= IT_AT_TOP_PROC' is not what you had intended with your last paragraph "Also= , the implicit wait statement in a process..." which is why posting code is= a 'good' thing. Thanks for clarifying your intent. Kevin From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Both transitions of CLOCK Date: Mon, 05 Aug 2013 12:02:33 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Aug 2013 15:55:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="e9e50b53612a5b684d85b5a1aa7c3313"; logging-data="31619"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/FIt8UlfrESB5wh9PSwWXU" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> Cancel-Lock: sha1:88ZqE5BAUDUbXWI1773Z1NMtEmI= Xref: news.eternal-september.org comp.lang.vhdl:6896 On 8/5/2013 11:02 AM, Daniel Kho wrote: >> I think you meant: >> >> >> >> Process (clk) >> >> begin >> >> if rising_edge(clk) then x<= y XOR d; end if; >> >> if falling_edge(clk) then y<= x XOR d; end if; >> >> end process; >> >> >> >> q<= x XOR y; >> >> >> >> Andy > > > Andy, yes you got me. :) > > regards, daniel How is this useful though? You now have an internal signal which is the same as the external signal based on a clock that is twice the rate of the internal clock in your FPGA. Is this just a thought experiment? -- Rick From newsfish@newsfish Tue Dec 29 16:43:05 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail From: Theo Markettos Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: 05 Aug 2013 21:37:52 +0100 (BST) Organization: University of Cambridge, England Lines: 35 Message-ID: <4sA*inaGu@news.chiark.greenend.org.uk> References: NNTP-Posting-Host: chiark.greenend.org.uk X-Trace: chiark.greenend.org.uk 1375735074 2379 212.13.197.229 (5 Aug 2013 20:37:54 GMT) X-Complaints-To: abuse@chiark.greenend.org.uk NNTP-Posting-Date: Mon, 5 Aug 2013 20:37:54 +0000 (UTC) User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.32-5-686-bigmem (i686)) Originator: theom@chiark.greenend.org.uk ([212.13.197.229]) Xref: news.eternal-september.org comp.lang.vhdl:6897 alb wrote: > On 02/08/2013 18:51, Theo Markettos wrote: > > We have makefiles for Altera that will: > > Checkout any component repositories needed by the project > > Build Bluespec -> Verilog > > [or run the Bluespec simulator] > > Run Qsys to generate Altera's Verilog IP (including some of the B->V > > output) > > Synthesise the Verilog in Quartus > > Download to an FPGA > > Load the FPGA memory/flash/etc > > Is you makefile available somewhere? Or any simplified version of it? > I understand the steps are pretty tool-dependent but I guess I can skim > that part out and fit my need in...hopefully. Here's the toplevel makefile: http://www.cl.cam.ac.uk/~atm26/ephemeral/cheri-toplevel-Makefile There are child makefiles for building Bluespec, ROMs, etc, but they're not that interesting... Bluespec does its own dependency handling, so the essence of the build is a single line (with a few alternatives for varieties of simulator), and the ROMs are standard software build makefiles. > I've found this article on Microsemi knowledge-base page: > > http://www.actel.com/kb/article.aspx?id=SL5619 > > I'll give it a try and see how it goes. Hmm... I see what you mean. Altera's version of same can be driven from shell (and so Makefile) rather than TCL. So it's much easier to plumb into existing infrastructure. Theo From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: managing vhdl projects with Makefiles Date: Tue, 06 Aug 2013 01:10:55 +0200 Lines: 39 Message-ID: References: <4sA*inaGu@news.chiark.greenend.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net h6U7FVvuv0ExNPYPCpJLfg2PtU4/ezeQhaCEOrtWDlKLP50KXf Cancel-Lock: sha1:JMIAdpva1D9MsMVWQa7RiAcudBs= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <4sA*inaGu@news.chiark.greenend.org.uk> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6898 Hi Theo, On 05/08/2013 22:37, Theo Markettos wrote: [] >> Is you makefile available somewhere? Or any simplified version of it? >> I understand the steps are pretty tool-dependent but I guess I can skim >> that part out and fit my need in...hopefully. > > Here's the toplevel makefile: > http://www.cl.cam.ac.uk/~atm26/ephemeral/cheri-toplevel-Makefile thank you loads! There are quite interesting points in this file. I like the overall structure and it seems quite user friendly. As a top level makefile it can recursively enter in all subdir and have everything done. My directory tree is essentially the following: constraints/ -- constraint files rtl/ -- vhdl code simulation/ -- simulation scripts synthesis/ -- synthesis scripts stimuli/ -- testbench with cases and so on Your example would be perfect as a top level calling each of the Makefiles present in each subdir. Currently I've started using 'vmk' and I find it quite interesting. I'm trying to understand some more details regarding predefined tools and how to configure new ones. Apparently it exists also an 'lmk' tool for libraries, but I still haven't found it anywhere on the net (so far). One big bit I learned through this quest is that if entities and architectures are split on separate files (as well as packages' declarations and packages' bodies), then modifying an architecture (or a package body), does not trigger a recompilation of any other unit, which may be quite beneficial for large projects. From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.103.68 with SMTP id j4mr2846340qao.8.1375792322984; Tue, 06 Aug 2013 05:32:02 -0700 (PDT) X-Received: by 10.49.104.44 with SMTP id gb12mr20571qeb.4.1375792322946; Tue, 06 Aug 2013 05:32:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!f7no1343982qan.0!news-out.google.com!he10ni733qab.0!nntp.google.com!fx3no1400861qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 Aug 2013 05:32:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81d8649d-5124-4ddd-955f-c3be2883f8fb@googlegroups.com> Subject: Re: Both transitions of CLOCK From: Andy Injection-Date: Tue, 06 Aug 2013 12:32:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6899 On Monday, August 5, 2013 11:02:33 AM UTC-5, rickman wrote: > How is this useful though? You now have an internal signal=20 > which is the same as the external signal based on a clock=20 > that is twice the rate of the internal clock in your FPGA.=20 > Is this just a thought experiment?=20 I have not found too many useful internal uses for DDR in general, or this = implementation of DDR. However, if you need to use a double-data-rate output from a low cost/power= device that does not support DDR outputs or have an available PLL/DLL, thi= s is one way you can safely (glitchlessly) do that. If your device does support built-in DDR outputs, they are very useful for = driving clock signals out (with the same timing as the data driven from the= same global clock), and/or for a gated clock, etc.=20 Some architectures do not provide dedicated low-skew routing from global cl= ock nets to output pins (e.g. through an output buffer), so using DDR outpu= t registers is a good way to generate multiple in-phase (or 180 out) clock = outputs at very low skew, at the same rate as the global clock. And it's not a bad thought experiment either. Andy From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: vmk and simulation Date: Thu, 08 Aug 2013 01:11:51 +0200 Lines: 47 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /KVPNjuIl4fSpWwRGEVWDgeANA+jVIl6dCxZTQjtJ7Yf//LR9y Cancel-Lock: sha1:8V6jC906++0DiprRmkHO/x50m7I= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6900 NOTE: If you are not using 'vmk' utility and are not interested in using it you can safely discard this article. Hi everyone, on the wave of a previous article posted here (), I am continuing my quest to put together a Makefile to handle my vhdl projects. Thanks to 'vmk' I managed to generate a fairly neat Makefile which now is happily compiling my set of files in the proper order. The 'vmk' utility supports several toolsets to perform compilation and simulation (it also supports an 'elaboration' phase...) but when I generated the Makefile specific for my toolset (ModelSim), it didn't seem to include any target for the simulation. In the generated Makefile there are three 'hooks'[1] which are primarily meant to do the following: 1. add a default target or macros 2. redefine macros or add targets 3. add additional rules and I could potentially use 1 or 2 to add a simulation target with all the necessary steps. But I was wondering why the heck 'vmk' has a defined macro for a simulation target and it doesn't use it. Maybe I'm missing something. Since I would like to use my Makefile for synthesis and place&route as well, I'm looking at using the 2nd hook to add those additional steps. It seems to me there's no way you can define a toolset with a complete workflow (compile, simulate, synthesize, place&route) and you need to rely on external hooks to do so. Any pointer is appreciated. Al [1] They are indeed /include/ files passed via an external configuration file. -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.66.188.37 with SMTP id fx5mr1903533pac.45.1375967837317; Thu, 08 Aug 2013 06:17:17 -0700 (PDT) X-Received: by 10.49.5.162 with SMTP id t2mr224924qet.24.1375967836970; Thu, 08 Aug 2013 06:17:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!qx7no18312820pbc.1!news-out.google.com!b4ni17019pbu.0!nntp.google.com!f7no1595847qan.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Aug 2013 06:17:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Label is required when instantiating a component From: Christiano Injection-Date: Thu, 08 Aug 2013 13:17:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6901 When using process, the label is optional. Is there any justification for the the label is required when instantiating a component? Thank you! From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: [cross-post] vlib, vmap, vcom, how it all works... Date: Thu, 08 Aug 2013 15:19:27 +0200 Lines: 91 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net RorDiiih9xNGxgEV+o1y1gFhO9TT4GGtH5cPgZr+4NQBXsDns1 Cancel-Lock: sha1:1iBoR7B2AvSQ0TkEoHY20/IN/Kc= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6902 comp.arch.fpga:19596 Hi everyone, I'm trying to understand the details of each individual step from my source code to a running a postlayout simulation with ModelSim. I've read several articles on what are the steps, I've also checked the default run.do script which ModelSim uses to do everything, but on top of *what* I need to do I'd appreciate to understand *why* I need to do so and *which* are the control files I need to know. The workflow I'm interested in is the following: 1. editing vhdl code 2. compilation 3. presynthesis simulation 4. synthesis 5. postsynthensis simulation 6. place&route 7. postlayout simulation Step 1. is fairly easy, a text editor and I'm done (better be emacs!). In order to perform 2. I need to use 'vcom' from ModelSim, but before doing that I need to specify which is my library. In order to do that, in the default run.do the following commands are executed: $ vlib presynth $ vmap presynth presynt $ vmap igloo /path/to/igloo/library/from/actel Now. While I understand the need to 'create' a library (BTW, what happened to 'work'!) I was puzzled on the need to map the library, but then I figured that when running vmap a modelsim.ini file is created for ModelSim to look at at startup in order to know where to look for libraries. To be more precise it would be 'vcom' that needs that piece of information, correct? If this is the case, when I need to run 5. I will need to grab the vhd generated by the synthesis (why do I need a vhd and not the edf/edn file?), create a postsynth library, map it and then compile in there the file with all the necessary files for the testbench. Is that correct? If this is correct, when moving on to 7. it seems that I need to get the backannotated vhdl from the p&r tool, create a postlayout library, map it and compile the vhdl in it with the associated testbench. If I'm on track with this, then I'd like to continue with simulating in batch mode (I'm mainly interested in regression tests automatically started). Here's is one hit I've found on running vsim in batch mode: https://ece.uwaterloo.ca/~ece327/protected/modelsim/htmldocs/mgchelp.htm#context=modelsim_se_user&id=16&tab=0&topic=NoNespecified What is strange is the use of a test.do script which may severely affect everything since I can ran whatever command in a do script... I'm not sure how much I want to depend on that. The default run.do instead has the following part: [skip compilation section] > vsim -L igloo -L presynth -t 1ps presynth.testbench > add wave /testbench/* > run 1000ns > log testbench/* > exit where I presume testbench is my top level testbench entity (what about the architecture!?!). And I also presume that this run.do is called from the ModelSim terminal, therefore I need to understand a little bit how can I pass it through command line (-c option??). It seems to me that these instructions could also be passed to vsim in batch mode and have it logging waveforms in external files (http://research.cs.berkeley.edu/class/cs/61c/modelsim/). For regression testing maybe waveforms are not so much interesting and a report is more useful, maybe with a coverage report as well, but before hitting that phase I believe I'll be looking a lot at waves and I better be prepared for being able to have them somewhere. After all this rant I think I bored you already to death, but believe me that while writing this article I checked and verified all my stupid thoughts, ending up with knowing much more than what I did yesterday night when I started writing... I guess I will continue to post my reasoning as I proceed with this quest, hoping not to annoy anyone :-). And of course if anybody notices I'm falling off track please give me a shout! Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Label is required when instantiating a component Date: Thu, 08 Aug 2013 10:18:40 -0400 Organization: Alacron, Inc. Lines: 22 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 8 Aug 2013 14:19:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="29586"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188GT/m+mSkVJkMFJ4znrgnuiAHi9veld8=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:a1APfZ0F76fuFluslibxrwqwBLA= Xref: news.eternal-september.org comp.lang.vhdl:6903 Christiano wrote: > When using process, the label is optional. > Is there any justification for the the label is required when instantiating a component? > > Thank you! What would you expect the instance name for a component to be if you don't give it a label? Suppose this was legal. Imagine that the tools just assigned a name like $I265 to some component. Then you make a change to the design and next time around the component is called $I267. How are you going to deal with the changing names in your hierarchy when you need to tell the back-end tools some attribute like placement? By the way, this is just the sort of thing that happens in automatically generated code like schematics translated to VHDL, or System Generator. Also other places that control hierarchical naming like generate statements require a label. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Label is required when instantiating a component Date: Thu, 08 Aug 2013 17:07:33 +0200 Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qCicmdWRmNh5JynSoCjhdAlkv1XoCLUJmBO7NsLdd9LGjByufk Cancel-Lock: sha1:T03/2IkHcZdEwJhpRdrzGCba8O0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6904 On 08/08/2013 16:18, GaborSzakacs wrote: > Christiano wrote: >> When using process, the label is optional. >> Is there any justification for the the label is required when >> instantiating a component? >> >> Thank you! > > What would you expect the instance name for a component to be if you > don't give it a label? Suppose this was legal. Imagine that the > tools just assigned a name like $I265 to some component. Then you > make a change to the design and next time around the component is > called $I267. How are you going to deal with the changing names > in your hierarchy when you need to tell the back-end tools some > attribute like placement? Well, why the changing name should bother me? Maybe it can facilitate waveform tracing, but in the end I wouldn't give a care if my component is called $I275 or $I1232, since I never refer to that label in my design. > By the way, this is just the sort of thing that happens in automatically > generated code like schematics translated to VHDL, or System Generator. As long as it is correctly generated, why should I care? (BTW I never use schematics anyway) > Also other places that control hierarchical naming like generate > statements require a label. Funny enough though I haven't find any place in the LRM a note or clause or sentence regarding 'required labels'. It then must be something about the tool. Maybe I should read harder... From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. Date: Thu, 08 Aug 2013 19:05:45 +0200 Lines: 48 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net GFmlX//H7mOozqkSShh8oAAXvLKy2x/vGfwMoULSE0Bs3PS5LC Cancel-Lock: sha1:OyNAUO3CyUaZcFQUWcqHAcuvwUM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6905 Hi everyone, my Modelsim version is: > pol@pcalb:firmware$ vsim -version > Model Technology ModelSim ACTEL vsim 10.1b Simulator 2012.04 Apr 27 2012 and I get the following warning when compiling my code: > ** Warning: foo.vhd(123): Choice in CASE statement alternative must be locally static. A reduced snippet of my code is here: > constant COMMAND_GET_EVENT : std_logic_vector(4 downto 0) := '0' & x"4"; > state_machine : process(clk, rst) > begin > > if (rst = '1') then > LVDS_STATE <= IDLE; > -- more stuff here ... > elsif rising_edge(clk) then > case LVDS_STATE is > when IDLE => > -- some code here > when DECODE_COMMAND => > case LVDS_DATA_IN_COMMAND(4 downto 0) is > when COMMAND_GET_EVENT => -- WARNING referring here! > -- some code here I've seen in this post somebody else had a similar issue: https://groups.google.com/forum/#!msg/comp.lang.vhdl/S9sRjLJbdqA/XUXdgnwY-c8J but I do not have a to_unsigned function in my code and the constant *is* locally static because is defined in the same architecture, therefore I do not see the issue. I will test with vhdl-2008 and report. But any clarification would be appreciated. Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.171.72 with SMTP id g8mr7814228qaz.7.1375990846814; Thu, 08 Aug 2013 12:40:46 -0700 (PDT) X-Received: by 10.50.4.38 with SMTP id h6mr42396igh.8.1375990846746; Thu, 08 Aug 2013 12:40:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!f7no1627396qan.0!news-out.google.com!he10ni1155qab.0!nntp.google.com!fx3no1704520qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Aug 2013 12:40:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> Subject: Re: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. From: Jim Lewis Injection-Date: Thu, 08 Aug 2013 19:40:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6906 Prior to VHDL-2008, a locally static expression required the operands and result to be scalar. VHDL-2008 drops the scalar requirement and explicitly adds some IEEE packages (see text below). In short, it should work in VHDL-2008. >From VHDL-2002, 7.4.1 P113 "7.4.1 Locally static primaries An expression is said to be locally static if and only if every operator in the expression denotes an implicitly defined operator whose operands and result are _scalar_ and" >From VHDL-2008, 7.4.2, P139 "9.4.2 Locally static primaries An expression is said to be locally static if and only if every operator in the expression denotes an implicitly defined operator or an operator defined in one of the packages STD_LOGIC_1164, NUMERIC_BIT, NUMERIC_STD, NUMERIC_BIT_UNSIGNED, or NUMERIC_STD_UNSIGNED in library IEEE, and if every primary in the expression is a locally static primary, where a locally static primary is defined to be one of the following:" Jim From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.172.68 with SMTP id k4mr7898412qaz.1.1375991983512; Thu, 08 Aug 2013 12:59:43 -0700 (PDT) X-Received: by 10.50.107.10 with SMTP id gy10mr46145igb.7.1375991983460; Thu, 08 Aug 2013 12:59:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!f7no1629212qan.0!news-out.google.com!he10ni1155qab.0!nntp.google.com!fx3no1706449qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Aug 2013 12:59:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Label is required when instantiating a component From: Jim Lewis Injection-Date: Thu, 08 Aug 2013 19:59:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6907 @Christiano > Is there any justification for the the label is required when > instantiating a component? In the language, anything that creates a level of hierarchy requires a labe= l. Hence, component instances, blocks, generates all require a label. I t= ry to create these algorithmically based on the component name. So for a c= omponent named comp, I use comp_1 as its label. =20 Processes do not create a level of hierarchy, so the name is not required. = I name longer processes with starting and ending labels (end process _myPr= oc_) when they span most of a screen or page. =20 Note I followed a convention like this even in the old days when we did sch= ematic capture. The reason comes back to what @alb noted, when you trace s= ignals through a design, it helps to have these named. Before I used this= convention for gate-level designs, I used lots of post-it notes to remembe= r the component names. =20 I suppose the language could let tools do this, but it does not - after all= , gate-level tools did figure this out. Of all the things in the language = that need to evolve, this is would be low, low priority. From a business p= erspective, every language change costs EDA vendors money to implement it -= this is one that I do not think is worth the cost. > from @alb > Funny enough though I haven't find any place in the LRM a note or clause > or sentence regarding 'required labels'. It then must be something about > the tool. Maybe I should read harder... You must read between the text - ie: the BNF. =20 >From IEEE-2008, 11.7.1, P176: component_instantiation_statement ::=3D instantiation_label : instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; You will note that "instantiation_label" is not surrounded by "[]", and hen= ce, is required. =20 Jim From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.236.169.196 with SMTP id n44mr4299638yhl.9.1375992081505; Thu, 08 Aug 2013 13:01:21 -0700 (PDT) X-Received: by 10.50.62.20 with SMTP id u20mr44991igr.11.1375992081417; Thu, 08 Aug 2013 13:01:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!fx3no1706665qab.0!news-out.google.com!he10ni1155qab.0!nntp.google.com!fx3no1706656qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Aug 2013 13:01:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a17f376-ba07-464f-8e09-f3b22813fca5@googlegroups.com> Subject: Re: Label is required when instantiating a component From: Jim Lewis Injection-Date: Thu, 08 Aug 2013 20:01:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6908 @Christiano > Is there any justification for the the label is required when > instantiating a component? In the language, anything that creates a level of hierarchy requires a labe= l. Hence, component instances, blocks, generates all require a label. I t= ry to create these algorithmically based on the component name. So for a c= omponent named comp, I use comp_1 as its label. =20 Processes do not create a level of hierarchy, so the name is not required. = I name longer processes with starting and ending labels (end process myPro= c) when they span most of a screen or page. =20 Note I followed a convention like this even in the old days when we did sch= ematic capture. The reason comes back to what @alb noted, when you trace s= ignals through a design, it helps to have these named. Before I used this= convention for gate-level designs, I used lots of post-it notes to remembe= r the component names. =20 I suppose the language could let tools do this, but it does not - after all= , gate-level tools did figure this out. Of all the things in the language = that need to evolve, this is would be low, low priority. From a business p= erspective, every language change costs EDA vendors money to implement it -= this is one that I do not think is worth the cost. > from @alb > Funny enough though I haven't find any place in the LRM a note or clause > or sentence regarding 'required labels'. It then must be something about > the tool. Maybe I should read harder... You must read between the text - ie: the BNF. =20 >From IEEE-2008, 11.7.1, P176: component_instantiation_statement ::=3D instantiation_label : instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; You will note that "instantiation_label" is not surrounded by "[]", and hen= ce, is required. =20 Jim From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.173.4 with SMTP id n4mr6301138qaz.3.1376004667768; Thu, 08 Aug 2013 16:31:07 -0700 (PDT) X-Received: by 10.49.11.134 with SMTP id q6mr328357qeb.0.1376004667731; Thu, 08 Aug 2013 16:31:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!f7no1646778qan.0!news-out.google.com!he10ni1155qab.0!nntp.google.com!fx3no1725416qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Aug 2013 16:31:07 -0700 (PDT) In-Reply-To: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4fa6914c-c08c-424e-9f01-7e67e4f2fb34@googlegroups.com> Subject: Re: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. From: Andy Injection-Date: Thu, 08 Aug 2013 23:31:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6909 If your tools support vhdl-2008, it really helps. Modelsim's tools do support 2008, but 2008 has new reserved words that, if used in your pre-2008 written code, also cause a failure. If for some reason you cannot use 2008, then you still have a couple of good options. Initialize the constant with "00100" (not as readable) Convert the case expression to an integer, and store it in a variable, then used that variable in the case statement. Then define your target expression constants as integers. There are probably others... Note that 2008 would also allow you to skip the variable for the converted case expression. Andy From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: vmk and simulation Date: Fri, 09 Aug 2013 07:11:10 +0200 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Aug 2013 05:11:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="b06946fed0cfa3bd21771adf886f75bf"; logging-data="1540"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/JLJgMAG3zH6hbLfA8Mw3j" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:32Bp4+qbuw6HwjvUQOtcRByqLd0= Xref: news.eternal-september.org comp.lang.vhdl:6910 I use vmk too, but only for simulation. > Since I would like to use my Makefile for synthesis and place&route as > well, I'm looking at using the 2nd hook to add those additional steps. > It seems to me there's no way you can define a toolset with a complete > workflow (compile, simulate, synthesize, place&route) and you need to I use a second makefile for synthesis and all the stuff. Here you can find a nice starting point: https://xess.com/appnotes/makefile.php Bart From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Both transitions of CLOCK Date: Fri, 09 Aug 2013 15:20:16 -0400 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> <81d8649d-5124-4ddd-955f-c3be2883f8fb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Aug 2013 19:20:29 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="8919"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/J+j1X4PagJ6ctJTQ6dyG0" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: <81d8649d-5124-4ddd-955f-c3be2883f8fb@googlegroups.com> Cancel-Lock: sha1:kkyPlVJ9OFjM55YLroZQn+TPcew= Xref: news.eternal-september.org comp.lang.vhdl:6911 On 8/6/2013 8:32 AM, Andy wrote: > On Monday, August 5, 2013 11:02:33 AM UTC-5, rickman wrote: >> How is this useful though? You now have an internal signal >> which is the same as the external signal based on a clock >> that is twice the rate of the internal clock in your FPGA. >> Is this just a thought experiment? > > I have not found too many useful internal uses for DDR in general, or this implementation of DDR. > > However, if you need to use a double-data-rate output from a low cost/power device that does not support DDR outputs or have an available PLL/DLL, this is one way you can safely (glitchlessly) do that. I don't follow. The circuit we are discussing pulls in a signal that changes data at twice the clock rate. It then combined the two data streams (rising edge, falling edge data) into a single data stream which should be the same as the corresponding external data stream... at TWICE the clock rate of your internal clock. That does nothing for interfacing to DDR signals. This circuit is for input, not output. In addition there can be problems trying to generate a combinatorial signal from FF outputs unless you can appropriately control the path delays. > If your device does support built-in DDR outputs, they are very useful for driving clock signals out (with the same timing as the data driven from the same global clock), and/or for a gated clock, etc. I'm not following how you would use this circuit to generate a clock. All it can do is to generate the same frequency clock as the system clock in the chip. I think you are saying this clock would have the same phasing as data which I supposed is true, but I'm not sure how that would help. There is always going to be skew between the clock and data. Normally one clock is an input to multiple chips on a board with virtually no skew if you match the path lengths. Then the problem is just a matter of meeting the chip to chip delay requirements. By outputting the clock from the FPGA you have an unknown skew (to the best of my knowledge). Is this parameter specified for FPGAs? > Some architectures do not provide dedicated low-skew routing from global clock nets to output pins (e.g. through an output buffer), so using DDR output registers is a good way to generate multiple in-phase (or 180 out) clock outputs at very low skew, at the same rate as the global clock. I don't remember seeing the output skew specified for FPGAs. Do they do that? > And it's not a bad thought experiment either. I won't argue that. -- Rick From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: vmk and simulation Date: Sat, 10 Aug 2013 00:37:26 +0200 Lines: 39 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 1gHLuCG0Wl8tQhZ7FwOr0QI0HAm/X54NlzxUKol1raMjd5mTnq Cancel-Lock: sha1:saigGrmm+D7buImU8nxhHO/cjfI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6912 Hi Bart, On 09/08/2013 07:11, Bart Fox wrote: [] >> Since I would like to use my Makefile for synthesis and place&route as >> well, I'm looking at using the 2nd hook to add those additional steps. >> It seems to me there's no way you can define a toolset with a complete >> workflow (compile, simulate, synthesize, place&route) and you need to > > I use a second makefile for synthesis and all the stuff. > Here you can find a nice starting point: > > https://xess.com/appnotes/makefile.php Believe it or not I already had this page open since quite few days, waiting the right moment to carefully go through, even though I was trying to understand how vmk works. Regarding the page you referred to, I have a couple of comments: 1. in your commented section of makefile.mk I guess svf and bit targets are swapped. 2. When you talk about project makefile you mention about overriding a PART variable by doing: PART = xc2s100-5-tq144 include xilinx_rules.mk where I believe that this cannot be since PART is going to take the *last* assignment to it, not the first. Still you could do overriding via command line (see GNU make: http://www.gnu.org/software/make/manual/html_node/Overriding.html). Same applies for the constraint file variable few lines below. A 'similar' Makefile was also pointed out by Theo Markettos in this message . From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. Date: Sat, 10 Aug 2013 02:05:40 +0200 Lines: 19 Message-ID: References: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net lrxGa5hdWXem+6FOJuKNiQdaAb7HJ5oS0Y/QuANLtzua3M9VIA Cancel-Lock: sha1:PtWyq3f63X0k4nHh/X3MlhAkflI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6913 Hi Jim, On 08/08/2013 21:40, Jim Lewis wrote: > Prior to VHDL-2008, a locally static expression required the operands > and result to be scalar. VHDL-2008 drops the scalar requirement and > explicitly adds some IEEE packages (see text below). In short, it > should work in VHDL-2008. eheh, I had to look up the definition of a 'scalar type' in the LRM, I didn't know an enumeration was a scalar... But I got your point. > From VHDL-2002, 7.4.1 P113 "7.4.1 Locally static primaries An > expression is said to be locally static if and only if every operator > in the expression denotes an implicitly defined operator whose > operands and result are _scalar_ and" I wonder what was the reason for that... as long as it is a constant it shouldn't really matter for a case statement, am I missing something? From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. Date: Sat, 10 Aug 2013 02:15:52 +0200 Lines: 19 Message-ID: References: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> <4fa6914c-c08c-424e-9f01-7e67e4f2fb34@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net VtRhpeBtv7KFuPgzXlJwBwtH9MnkGZXKmNMzHDoYHXgbb0Y36P Cancel-Lock: sha1:E1oZkTCZwlx5qIWRddL3l3bZHyk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <4fa6914c-c08c-424e-9f01-7e67e4f2fb34@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6914 On 09/08/2013 01:31, Andy wrote: > If your tools support vhdl-2008, it really helps. Modelsim's tools do > support 2008, but 2008 has new reserved words that, if used in your > pre-2008 written code, also cause a failure. it doesn't seem to be the case, it compiles without warnings. [] > Initialize the constant with "00100" (not as readable) true, even though not so dramatic either. I guess I may specify the constant as a wider signal (say 8 bits) and then do some gymnastic with the ranges when comparing, but I guess that also won't improve readability. > Convert the case expression to an integer, and store it in a > variable, then used that variable in the case statement. Then define > your target expression constants as integers. That is quite more attractive indeed. And having the constants as integers will bu much more readable than what we currently have. From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.169.1 with SMTP id w1mr15178034qay.4.1376102908009; Fri, 09 Aug 2013 19:48:28 -0700 (PDT) X-Received: by 10.49.101.114 with SMTP id ff18mr449546qeb.32.1376102907950; Fri, 09 Aug 2013 19:48:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no1767859qan.0!news-out.google.com!he10ni1155qab.0!nntp.google.com!fx3no1854925qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2013 19:48:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5669bc95-c852-4362-bab2-00809dfd3f6a@googlegroups.com> Subject: Testbench is not working properly in GHDL From: Christiano Injection-Date: Sat, 10 Aug 2013 02:48:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6915 Hi I made a testbench, but is not working properly. The testbench code is here: http://pastebin.com/jJgjrpp7 The code of the "target" is here: http://pastebin.com/Y0aRG85N When the program runs, it shows this: 0010 ---> 0=d, 0=clk, 1=rst, 0=q Ok, now I will enter the new set of entries that I want. 000 ------> 0=d, 0=clk, 0=rst The program shows this: test ----> Means that went where it should. 000 -----> The value entered 0010 ----> Not changed!! This may be a bug GHDL? Or did I do something wrong? From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.69.6 with SMTP id x6mr15552202qai.0.1376110024041; Fri, 09 Aug 2013 21:47:04 -0700 (PDT) X-Received: by 10.49.64.72 with SMTP id m8mr450773qes.20.1376110023992; Fri, 09 Aug 2013 21:47:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no1862490qab.0!news-out.google.com!he10ni1391qab.0!nntp.google.com!fx3no1862489qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Aug 2013 21:47:03 -0700 (PDT) In-Reply-To: <5669bc95-c852-4362-bab2-00809dfd3f6a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 References: <5669bc95-c852-4362-bab2-00809dfd3f6a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4fd0e346-7ecd-4a5c-8c49-0e7382cb8969@googlegroups.com> Subject: Re: Testbench is not working properly in GHDL From: Christiano Injection-Date: Sat, 10 Aug 2013 04:47:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 43 Xref: news.eternal-september.org comp.lang.vhdl:6916 On Friday, August 9, 2013 11:48:27 PM UTC-3, Christiano wrote: > Hi I made a testbench, but is not working properly. > > > > The testbench code is here: > > http://pastebin.com/jJgjrpp7 > > > > The code of the "target" is here: > > http://pastebin.com/Y0aRG85N > > > > When the program runs, it shows this: > > 0010 ---> 0=d, 0=clk, 1=rst, 0=q > > > > Ok, now I will enter the new set of entries that I want. > > 000 ------> 0=d, 0=clk, 0=rst > > > > The program shows this: > > test ----> Means that went where it should. > > 000 -----> The value entered > > 0010 ----> Not changed!! > > > > This may be a bug GHDL? Or did I do something wrong? In added a wait for 50 ns; Early in the process that everything worked correctly, simulators need to put a wait, and wait is not real, if I put 5000000 us he will not stand 5 seconds, is all virtual. From newsfish@newsfish Tue Dec 29 16:43:06 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: vmk and simulation Date: Sat, 10 Aug 2013 14:58:07 +0200 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 10 Aug 2013 12:58:08 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="2dde14b20c8bf5759d9ef90ced0c9e4e"; logging-data="29902"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fywV7AWu+Pt104jzMkNMA" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:w1AvH4FQBmXYTxuvhT59s1JguYY= Xref: news.eternal-september.org comp.lang.vhdl:6917 Hello Al, >> https://xess.com/appnotes/makefile.php > > 1. in your commented section of makefile.mk I guess svf and bit targets > are swapped. It's not my makefile, but a suggestion for you. And yes you are right, the comments are swapped. Maybe you can drop a mail to xess. > 2. When you talk about project makefile you mention about overriding a > PART variable by doing: > > > PART = xc2s100-5-tq144 > include xilinx_rules.mk > > > where I believe that this cannot be since PART is going to take the > *last* assignment to it, not the first. Still you could do overriding > via command line (see GNU make: > http://www.gnu.org/software/make/manual/html_node/Overriding.html). There is a '?=' in xilinx_rules.mk See http://www.gnu.org/software/make/manual/html_node/Setting.html#Setting for explanation. Bart From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.103.68 with SMTP id j4mr17722901qao.8.1376152529051; Sat, 10 Aug 2013 09:35:29 -0700 (PDT) X-Received: by 10.49.95.233 with SMTP id dn9mr472980qeb.35.1376152529032; Sat, 10 Aug 2013 09:35:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!f7no1812624qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no1901868qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2013 09:35:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Label is required when instantiating a component From: Andy Injection-Date: Sat, 10 Aug 2013 16:35:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6918 On Thursday, August 8, 2013 10:07:33 AM UTC-5, alb wrote: > Well, why the changing name should bother me? Maybe it=20 > can facilitate waveform tracing, but in the end I wouldn't > give a care if my component is called $I275 or $I1232, > since I never refer to that label in my design.=20 ... > As long as it is correctly generated, why should I care?=20 > (BTW I never use schematics anyway)=20 There are other important uses of component instance names besides waveform= s and schematics. For example, some constraints can/should be handled in a constraint file, i= nstead of in the source, especially if the constraints are specific to a to= ol or target device. To make constraint files work reliably, you need the design hierarchy to re= main stable, preferably even if the design code does not. Allowing the tool= to automatically generate instance names often causes seemingly unrelated = code modifications to change implied instance labels, invalidating any cons= traints that reference the instances or any other instances below them. If a process declares a variable that is implemented as a register, then it= is a good idea to label the process. Also, if you ever use 2008's hierarchical references to access internal sig= nals from a testbench (e.g. white-box testing), you will also need to make = sure the hierachical references don't change unexpectedly. Andy From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.171.72 with SMTP id g8mr18496862qaz.7.1376165474317; Sat, 10 Aug 2013 13:11:14 -0700 (PDT) X-Received: by 10.49.6.40 with SMTP id x8mr484881qex.5.1376165474303; Sat, 10 Aug 2013 13:11:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no1829073qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no1919166qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2013 13:11:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.186.192; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.186.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Textchio - Improvised tests From: Christiano Injection-Date: Sat, 10 Aug 2013 20:11:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 6165 Xref: news.eternal-september.org comp.lang.vhdl:6919 I made a program that makes rapid tests in VHDL using textio. For example if you have this flip flop to test: Dff.vhdl: library ieee; use ieee.std_logic_1164.all; entity dffx is port( d, clk, rst: in std_logic; q: out std_logic); end dffx; architecture behaviour of dffx is begin process(rst,clk) begin if(rst='1') then q <= '0'; elsif(clk'event and clk='1') then q <= d; end if; end process; end behaviour; Just do this: $ ghdl -a Dff.vhdl $ ./testchio dffx d,clk,rst q > testchio.vhdl $ ghdl -a testchio.vhdl $ ghdl -e testchio_tb $ ghdl -r testchio_tb The first argument is the name of the entity you want to test, the second is a list of inputs separated by commas, and the third is a list of outputs separated by commas. Then typing the values and go changing inputs improvised, example: d,clk,rst,q=1110 000 000 d,clk,rst,q=0000 100 100 d,clk,rst,q=1000 110 110 d,clk,rst,q=1101 001 001 d,clk,rst,q=0010 It will show the values and you have the option to change the entries in an improvised way. It's pretty cool to teaching and so on. For now this works only with std_logic, is very limited. The code is presented below: #!/usr/bin/perl my @ins1 = split(',', $ARGV[1]); my @ins2 = split(',', $ARGV[2]); my $subst1 = ''; foreach my $val (@ins1) { $subst1 = $subst1."$val: in std_logic;"; } my $subst2 = ''; foreach my $val (@ins2) { $subst2 = $subst2."$val: out std_logic;"; } $subst2 = substr $subst2, 0, length($subst2)-1; my $subst3 = ''; foreach my $val (@ins1) { $subst3 = $subst3."signal $val: std_logic :='1';"; } my $subst4 = ''; foreach my $val (@ins2) { $subst4 = $subst4."signal $val: std_logic;"; } my $subst5 = ''; foreach my $val (@ins1) { $subst5 = $subst5." if($val='1') then write(dados, string'(\"1\")); else write(dados, string'(\"0\")); end if; "; } my $subst6 = ''; foreach my $val (@ins2) { $subst6 = $subst6." if($val='1') then write(dados, string'(\"1\")); else write(dados, string'(\"0\")); end if; "; } my $subst7 = ''; my $jk=0; foreach my $val (@ins1) { $subst7 = $subst7." elsif(j=$jk) then $val <= '0'; "; $jk = $jk+1; } my $subst8 = ''; my $jk=0; foreach my $val (@ins1) { $subst8 = $subst8." elsif(j=$jk) then $val <= '1'; "; $jk = $jk+1; } my $subst9 = ''; foreach my $val (@ins1) { $subst9 = $subst9."$val,"; } foreach my $val (@ins2) { $subst9 = $subst9."$val,"; } $subst9 = substr $subst9, 0, length($subst9)-1; print 'library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity testchio_tb is end entity testchio_tb; architecture behaviour of testchio_tb is component '.$ARGV[0].' port ( '.$subst1.$subst2.' ); end component; '.$subst3.$subst4.' begin UQ1: dffx port map ('.$ARGV[1].','.$ARGV[2].' ); -- Stimulus: main: -- main process -- Requires ghdl -r --stop-time=ns variable dados: line; variable erro: line; variable j : integer ; begin -- to stop model execution. wait for 50 ns; writeline(output, dados); write(dados, string\'("'.$subst9.'=")); '.$subst5.$subst6.' writeline(output, dados); readline(input, dados); j := 0; for i in dados\'range loop case(dados(i)) is when \'0\' => if(j=-1) then '.$subst7.' else end if; j := j +1; when \'1\' => if(j=-1) then '.$subst8.' else end if; j := j+1; when others => NULL; end case; end loop; end process main; end behaviour;'; From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.173.4 with SMTP id n4mr16369380qaz.3.1376171689723; Sat, 10 Aug 2013 14:54:49 -0700 (PDT) X-Received: by 10.49.30.135 with SMTP id s7mr500155qeh.19.1376171689701; Sat, 10 Aug 2013 14:54:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no1836142qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no1926422qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 Aug 2013 14:54:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <65c28903-9183-4b7a-9dcf-3d338bcff203@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56024e5e-fcf5-4010-864f-045228dbbde8@googlegroups.com> Subject: Re: ModelSim ** Warning: Choice in CASE statement alternative must be locally static. From: Andy Injection-Date: Sat, 10 Aug 2013 21:54:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 29 Xref: news.eternal-september.org comp.lang.vhdl:6920 On Friday, August 9, 2013 7:05:40 PM UTC-5, alb wrote: > I wonder what was the reason for that... as long as > it is a constant it shouldn't really matter for a case > statement, am I missing something? The idea is for the compiler to catch such errors at compile time, before e= laboration has occurred. This allows a module to be compiled into a library= and known to be good (WRT those things that had to be locally static) long= before anyone had used it. Things like unconstrained ports, deferred constants and generics get define= d during elaboration, which is often transparent in today's tools. Synthesi= s usually combines compilation ("analysis" per LRM) and elaboration in one = step. Most simulators combine elaboration and execution in one step. Some o= f Cadence's older simulators (NC and Leapfrog) separated the analysis, elab= oration and execution into separate steps (I have no exprience with their l= ater tools).=20 If an aspect of a module, such as the completeness and exclusiveness of a c= ase statement, could be verified at compilation, then no matter how the mod= ule was instantiated or connected, it could not cause a future problem with= that aspect. This has been somewhat relaxed in 2008 with the allowance of = the case expression (but not the target expressions!) to be globally static= . The resulting, reduced benefit of the target expressions being locally st= atic is to ensure that no target expression values are repeated, whereas be= fore they could also be ensured to be complete. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.69.6 with SMTP id x6mr21369444qai.0.1376221007019; Sun, 11 Aug 2013 04:36:47 -0700 (PDT) X-Received: by 10.49.12.47 with SMTP id v15mr509598qeb.39.1376221006964; Sun, 11 Aug 2013 04:36:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!fx3no1976478qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no1976476qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 Aug 2013 04:36:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.175.37.81; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 94.175.37.81 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Any one who can help me out to implement 3 short algorithms in VHDL? I am ready to pay From: Chris Waugh Injection-Date: Sun, 11 Aug 2013 11:36:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6921 I have done around 60% of the project. I need someone who can help me to ve= rify it and test it. May be a bit modification is required on my current wo= rk. I need to implement 3 short algorithms after that. I am aiming to finis= h it in 2 days. It will not take more than that. Please email me at chris.= waugh190490@gmail.com if you could help me out. I am ready to pay whatever you want for your time= . Reply ASAP. Thanks! From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.2.202 with SMTP id 10mr57773qak.8.1376327291881; Mon, 12 Aug 2013 10:08:11 -0700 (PDT) X-Received: by 10.50.13.105 with SMTP id g9mr764715igc.9.1376327291816; Mon, 12 Aug 2013 10:08:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2143285qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2143283qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 10:08:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: <73a369f9-3801-4960-bb0c-f993c17bf579@googlegroups.com> <73c5f849-cc01-4cc5-b928-552cd4389fff@googlegroups.com> <133d76b0-4d83-4f2a-9693-018539d43842@googlegroups.com> <677178b0-6611-4952-b033-aa0e1c7de41c@googlegroups.com> <81d8649d-5124-4ddd-955f-c3be2883f8fb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Both transitions of CLOCK From: Andy Injection-Date: Mon, 12 Aug 2013 17:08:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3396 Xref: news.eternal-september.org comp.lang.vhdl:6922 Rick, I was referring to Daniel Kho's description which was for a DDR type output= , whether used internally or externally. The worst case output skew is either reported in or can be deduced from the= timing reports. As an example, I had a project with an FPGA that needed to provide multiple= low-skew clock output signals at the same frequency as an available clock = signal. The FPGA did not provide dedicated connections from the global clock net to= any port on the IOB except for the clock input(s) of the IOB. If you wante= d to drive the globally routed clock out on a pad, you had to use local rou= ting near the IOB to get off the global clock net and into the out port of = the IOB (so that the IOB would buffer the signal to the pad). This local ro= uting is very unpredictable in between P&R runs if there are any changes to= the design, and there is a significant delay in that routing.=20 To solve the problem, I configured the IOBs as a DDR output registers, with= '1' on the rising edge data input, and '0' on the falling edge data input = (to replicate the clock on the output). Since the global clock net has a di= rect connection to the IOB clock ports, the skew is very low and controllab= le among multiple outputs driven the same way. In this example, we drove 7 = identical clock output signals. All were routed point-point with matched le= ngths to control timing and signal integrity.=20 Granted, all the low skew features fly out the window if you have to emulat= e the DDR output register. But you can safely (glitchlessly) enable and dis= able a single clock output driven from an emulated DDR, since the enable/di= sable signals are inputs to the registers, and thus the output can only cha= nge as a result of the clock changing. The XOR gates are glitchless since t= he two inputs cannot change at the same time. And the design is STA-friendl= y. Andy From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.64.202 with SMTP id f10mr2824796qai.2.1376368302683; Mon, 12 Aug 2013 21:31:42 -0700 (PDT) X-Received: by 10.50.98.4 with SMTP id ee4mr111663igb.5.1376368302634; Mon, 12 Aug 2013 21:31:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2251464qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2251457qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 21:31:42 -0700 (PDT) In-Reply-To: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <0692b51d-216e-43c8-817d-7e66736667a3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <099de447-788a-4023-a73d-6e4e0dc67573@googlegroups.com> Subject: Re: New VHDL Project From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 04:31:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2040 Xref: news.eternal-september.org comp.lang.vhdl:6923 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7=99= =D7=A9=D7=99, 4 =D7=91=D7=99=D7=95=D7=9C=D7=99 2013 16:01:30 UTC+3, =D7=9E= =D7=90=D7=AA shankarm...@gmail.com: > hello all this is shankar mishra doing M Tech in Electronics >=20 > can you suggest me some usefull project on VHDL based on current trend in= VLSI industry. >=20 > thanx in advance IP TTL spoofed packet block in VHDL "This project implements an IP TTL filter in hardware. If an IPV4 packet is= identified, the machine checks its TTL field. Based on previous values of = TTL data collected and analyzed from former packets, the machine decides if= the packet is spoofed or not. ..." http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_main.html "...compiles and runs simulation, using GHDL, on a UART transmit module, wh= ich I found on ..." http://bknpk.no-ip.biz/my_web/MiscellaneousHW/UART/uart_tx_1.html From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.64.202 with SMTP id f10mr2843285qai.2.1376368580070; Mon, 12 Aug 2013 21:36:20 -0700 (PDT) X-Received: by 10.50.98.4 with SMTP id ee4mr112532igb.5.1376368579863; Mon, 12 Aug 2013 21:36:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2252124qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2252109qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 21:36:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Is a block spoof IP filter in hardware (VHDL design) is required From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 04:36:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 21 Xref: news.eternal-september.org comp.lang.vhdl:6924 IP TTL spoofed packet block in VHDL I read recently, that some linux kernels have the ability to block spoofed = packets. Some hackers attack servers by sending many packets. They also put= some fake data in the offending packets. The arrival of multiple packets, = with a well known source IP, in the spoofed packet, causes many interrupts = in the server. This, in the best case, results with a degraded performance.= Some kernels try to counter attack with an IP TTL block spoofed filter. I = have decided to build such a filter in hardware. I would like to do the job= in hardware (VHDL design), therefor offloading the kernel from this job. T= he idea is to have two main states in hardware machine, per each incoming I= P namely: learning and check. In the former the hardware machine will build= a table, per each incoming source IP, where it will average the TTL values= of the packet. Once a programmable number of TTL values, for a given packe= t, have been studied, the hardware (VHDL design) machine switches to check = mode. During check mode, if a packet arrives and its TTL is outside an allo= wable range, a block packet indication is set. Such an implementation requi= res memory. With the way the design is implemented any memory smaller than = 32 bits addressable, for IPV4, can be used. Is a block spoof IP filter in hardware (VHDL design) is required. Please share your thoughts. From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.137.137 with SMTP id w9mr2857169qat.6.1376369135010; Mon, 12 Aug 2013 21:45:35 -0700 (PDT) X-Received: by 10.50.29.72 with SMTP id i8mr113806igh.1.1376369134963; Mon, 12 Aug 2013 21:45:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2253377qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2253364qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 21:45:34 -0700 (PDT) In-Reply-To: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9b60f856-2eae-4f05-a384-97781b5c8138@googlegroups.com> Subject: Re: ethernet on spartan 3an From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 04:45:35 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 55 Xref: news.eternal-september.org comp.lang.vhdl:6925 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A9=D7=99=D7=A9= =D7=99, 1 =D7=91=D7=9E=D7=A8=D7=A5 2013 15:32:35 UTC+2, =D7=9E=D7=90=D7=AA = revkarol: > Hi, >=20 >=20 >=20 > I've a starter kit board for the Spartan 3an. This includes and RJ45 Eth= ernet jack. I'd like to use this to send data down the line to my PC. To = simplify matters somewhat, I have an extra network card so it's not on the = general LAN. All I want to do is send some (ideally UDP) data, in one dire= ction down the line from the FPGA to the PC. Speed is not an issue as this= is mostly a training exercise to 10Mbps is fine. On the PC end I can use = some data capture/snooping tool to grab the data. >=20 >=20 >=20 > Not sure, but perhaps I need a crossover cable or switch between the two? >=20 >=20 >=20 > My current feeble attempt suggests that I need to use some IP core for Et= hernet. Since I've mostly be writing raw VHDL from scratch so far this is = new. But also a good thing since I'd like learn how to add various IP core= s to a project. >=20 >=20 >=20 > I've managed to get a temporary licence for the TEMAC (TriMode Ethernet M= AC) and generate a core using the Xilinx CORE generator with the MII settin= g which seems fine for 10Mbps. =20 >=20 >=20 >=20 > I've managed to get the shipped example synthesized and generate the firm= ware. However I don't think it's working as I don't see any link activity = on the RJ45 LEDs. >=20 >=20 >=20 > Basically, I'm not sure if this is the right way to attack the problem. = Nor where to go next. Should I add the UDP layer in VHDL? >=20 >=20 >=20 > Advance thanks for any help/advice given, >=20 > Karol. You may be interested to look on: "...project implements an IP TTL filter in hardware. If an IPV4 packet is i= dentified, the machine checks its TTL field. Based on previous values of TT= L data collected and analyzed from former packets, the machine decides if t= he packet is spoofed or not..." http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_main.html From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.169.1 with SMTP id w1mr2885272qay.4.1376369355457; Mon, 12 Aug 2013 21:49:15 -0700 (PDT) X-Received: by 10.50.13.105 with SMTP id g9mr115906igc.9.1376369355408; Mon, 12 Aug 2013 21:49:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2150209qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2253840qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 21:49:15 -0700 (PDT) In-Reply-To: <7693d0d5-48c3-46e9-8137-ade7c970fbc0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <494a4976-8a3b-4008-beb2-19fd31e5c4d3@googlegroups.com> <7693d0d5-48c3-46e9-8137-ade7c970fbc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e63c7ed-8d00-42f1-9d5b-59246d6ad013@googlegroups.com> Subject: Re: VHDL Help From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 04:49:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4992 Xref: news.eternal-september.org comp.lang.vhdl:6926 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7=99= =D7=A9=D7=99, 26 =D7=91=D7=99=D7=95=D7=9C=D7=99 2012 09:02:44 UTC+3, =D7=9E= =D7=90=D7=AA goou...@googlemail.com: > Am Donnerstag, 26. Juli 2012 04:02:42 UTC+2 schrieb Bruno Carvalho: >=20 > > Hello, >=20 > >=20 >=20 > > I'm having difficulties to understand a modelsim simulation of a vh= dl component written by me. >=20 > > I have a vhdl component which name is tx_controller. This component has= a simple logic. It reads the number of words stored in a buffer (dc_fifo a= ltera ip core). If the number of words stored in buffer < 376, so i send= to the output data_out the value 0xFF. When the words store in buffer >= =3D 376, i send to the data_out the value of input data_in which is values = came from buffer.=20 >=20 > > In this simulation the behavior of tx_controller is correct. >=20 > > But when i use the same module integrated in my system through port map= s the component has a strange behavior. E.g.: When the data_in has the valu= e 0x40, data_out should receive the value 0x40, but it keeps with the last = value (0x00) and the value is changed to 0x40 only in the next rising edge = in clock signal.=20 >=20 > >=20 >=20 > > Bellow is my code >=20 > >=20 >=20 > > -------------------------------------------------------------- >=20 > > library IEEE; >=20 > > use IEEE.std_logic_1164.all; >=20 > > use IEEE.numeric_std.all; >=20 > > -------------------------------------------------------------- >=20 > >=20 >=20 > > ENTITY tx_controller IS >=20 > > GENERIC(WR_USED_MIN: integer :=3D 376; >=20 > > NULL_PACKET: integer :=3D 255); >=20 > > PORT (clk, rst: IN STD_LOGIC; >=20 > > data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER >=20 > > fifo_is_empty: IN STD_LOGIC; =20 >=20 > > wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS I= N BUFFER >=20 > > fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING =20 >=20 > > data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE >=20 > > ); >=20 > > END tx_controller; >=20 > >=20 >=20 > > ARCHITECTURE behav OF tx_controller IS >=20 > > CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) :=3D STD_LOGIC_VEC= TOR(to_unsigned(WR_USED_MIN, 9)); >=20 > > BEGIN >=20 > >=20 >=20 > > MAIN: PROCESS(rst, clk, data_in, wr_used) >=20 > > BEGIN >=20 > > IF (rst =3D '1') THEN >=20 > > fifo_rd_enable <=3D '0'; >=20 > > data_out <=3D (others =3D> '0'); >=20 > > ELSIF (rising_edge(clk)) THEN >=20 > > IF (wr_used < fifo_min) THEN >=20 > > data_out <=3D (OTHERS =3D> '1'); >=20 > > fifo_rd_enable <=3D '0'; >=20 > > ELSE >=20 > > fifo_rd_enable <=3D '1'; >=20 > > data_out <=3D data_in; >=20 > > END IF; >=20 > > END IF; >=20 > > END PROCESS; >=20 > > END behav; >=20 > >=20 >=20 > >=20 >=20 > > Somebody can identify some problem analysing my vhdl code ? >=20 > >=20 >=20 > > Thanks for any help. >=20 >=20 >=20 > Hi, >=20 > how have you simulated your code? >=20 > With a separate testbench, or together with the rest of the design, espec= ially that FIFO-IP simulation model? >=20 >=20 >=20 > Without the FIFO-IP model your testbench might behave different and so yo= ur code may have some +/-1 Error in the comparator numbers due to some sign= al latency. >=20 >=20 >=20 > Have a nice simulation >=20 > Eilert You may want to start with small VHDL examples. Make them work and then con= tinue. For instance see what I did at: http://bknpk.no-ip.biz/my_web/SDIO/vhdl_wait_process_select.html From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.169.1 with SMTP id w1mr2926861qay.4.1376369963194; Mon, 12 Aug 2013 21:59:23 -0700 (PDT) X-Received: by 10.50.20.3 with SMTP id j3mr120338ige.2.1376369962928; Mon, 12 Aug 2013 21:59:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2255041qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2255036qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 21:59:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0428f283-dfe9-49e8-8a01-e12d5d056d0f@googlegroups.com> Subject: AHB/APB graduate project From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 04:59:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:6927 An AHB VHDL project, built of two AHB masters, one arbiter, one AHB to APB bridge and one simple APB slave. If you are interested in this project as a graduate project,... Please visit bknpk VHDL site From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.13.136 with SMTP id c8mr2944811qaa.0.1376374237936; Mon, 12 Aug 2013 23:10:37 -0700 (PDT) X-Received: by 10.50.49.11 with SMTP id q11mr129799ign.12.1376374237890; Mon, 12 Aug 2013 23:10:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2263727qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2263725qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 23:10:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: random numbers From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 06:10:37 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 76 Xref: news.eternal-september.org comp.lang.vhdl:6928 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A9=D7=A0=D7=99,= 16 =D7=91=D7=A1=D7=A4=D7=98=D7=9E=D7=91=D7=A8 2002 17:55:02 UTC+2, =D7=9E= =D7=90=D7=AA itsme: > Hi, > I like to write a techbench which > uses random numbers for input data > to test my hardware. > Does VHDL has a built in random number generator? > Is there any library? > thanks, > peter You may find this helpful "... --random numbers generation signal rand_ttl_delta : std_logic_vector(3 downto 0) :=3D "1000"; signal rand_ttl_deltai : integer :=3D 8; ... rand_ttl_delta <=3D f_my_rand (4, rand_ttl_delta); -- 3 2 1 -- 109876543210987654321098765 if(o_tot_cnt(31 downto 5) =3D "000000000000000000000000000") = then=20 --small changes during average calculation (learning state) gen_rand :=3D "00" & rand_ttl_delta(1 downto 0); else gen_rand :=3D rand_ttl_delta; end if; tmp_ptr.data :=3D tmp_ptr.data + gen_rand; -- write(my_line, string'("gen_rand ")); hwrite(my_line, tmp_ptr.data); write(my_line, string'(" ")); --write(my_line, gen_ipv4); hwrite(my_line, o_tot_cnt); write(my_line, string'(" ")); write(my_line, now); writeline(output, my_line); ..." "... --random number function f_my_rand(width : integer; temp_2 : std_logic_vector)=20 return std_logic_vector is constant temp_c : std_logic_vector(width-2 downto 0):=3D=20 temp_2(width-2 downto 0); variable rand_temp : std_logic_vector(width-1 downto 0):=3D '1' & temp_c; variable temp : std_logic :=3D '0'; variable random_num : std_logic_vector(width-1 downto 0); variable my_line : line; begin temp :=3D rand_temp(width-1) xor rand_temp(width-2); rand_temp(width-1 downto 1) :=3D rand_temp(width-2 downto 0); rand_temp(0) :=3D temp; random_num :=3D rand_temp; --if(DEBUG =3D '1') then --write(my_line, string'("f_my_rand ")); --hwrite(my_line, random_num); --writeline(output, my_line); --end if; return random_num; end f_my_rand; ..." http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_func_rand.html This was done as part of IP filter VHDL bench and design: "... how I randomize the TTL field values. In this project I have already discus= sed the issue of generating random numbers. While previous case was merely = delay between packets, this one is a little bit complex. When the DUT is in= learning state (see FSM description), small changes in the TTL are require= d. Later an attack scenario is presented to the DUT, by vhdl bench. ..." From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.2.202 with SMTP id 10mr3152268qak.8.1376374437271; Mon, 12 Aug 2013 23:13:57 -0700 (PDT) X-Received: by 10.50.82.40 with SMTP id f8mr129394igy.17.1376374437095; Mon, 12 Aug 2013 23:13:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2160138qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2264144qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 23:13:56 -0700 (PDT) In-Reply-To: <3607E0C6.A5C4C4D8@dsccc.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <3607E0C6.A5C4C4D8@dsccc.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Generating "random" bytes From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 06:13:57 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3200 Xref: news.eternal-september.org comp.lang.vhdl:6929 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A9=D7=9C=D7=99= =D7=A9=D7=99, 22 =D7=91=D7=A1=D7=A4=D7=98=D7=9E=D7=91=D7=A8 1998 09:00:00 U= TC+2, =D7=9E=D7=90=D7=AA Chris Plachta: > Hello, >=20 > I've been looking for a simple way to generate random (or pseudorandom) > std_logic_vectors. I haven't found any standard random number > generation command in VHDL. All I really need to do is crank out bytes > of random data for simulation purposes. >=20 > Suggestions? >=20 > -- > Chris Plachta > Alcatel USA > Phone: 707-792-7271 > FAX: 707-792-6310 Take a look at bknpk vhdl: "... This page explains how I randomize the TTL field values. In this project I = have already discussed the issue of generating random numbers. While previo= us case was merely delay between packets, this one is a little bit complex.= When the DUT is in learning state (see FSM description), small changes in = the TTL are required. Later an attack scenario is presented to the DUT, by = vhdl bench. --random numbers generation signal rand_ttl_delta : std_logic_vector(3 downto 0) :=3D "1000"; signal rand_ttl_deltai : integer :=3D 8; ... rand_ttl_delta <=3D f_my_rand (4, rand_ttl_delta); -- 3 2 1 -- 109876543210987654321098765 if(o_tot_cnt(31 downto 5) =3D "000000000000000000000000000") = then=20 --small changes during average calculation (learning state) gen_rand :=3D "00" & rand_ttl_delta(1 downto 0); else gen_rand :=3D rand_ttl_delta; end if; tmp_ptr.data :=3D tmp_ptr.data + gen_rand; -- write(my_line, string'("gen_rand ")); hwrite(my_line, tmp_ptr.data); write(my_line, string'(" ")); --write(my_line, gen_ipv4); hwrite(my_line, o_tot_cnt); write(my_line, string'(" ")); write(my_line, now); writeline(output, my_line); ..." http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.64.202 with SMTP id f10mr3181321qai.2.1376374525643; Mon, 12 Aug 2013 23:15:25 -0700 (PDT) X-Received: by 10.50.111.48 with SMTP id if16mr133244igb.3.1376374525596; Mon, 12 Aug 2013 23:15:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2264342qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2264334qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Aug 2013 23:15:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Random Number Generator From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 06:15:25 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 48 Xref: news.eternal-september.org comp.lang.vhdl:6930 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7=99= =D7=A9=D7=99, 10 =D7=91=D7=99=D7=95=D7=9C=D7=99 1997 10:00:00 UTC+3, =D7=9E= =D7=90=D7=AA Tim Holmes: > Could anyone tell me how to create a "random" number generator in > VHDL. I imagine that the only method is to use a LFSR approach with > a seed. >=20 > If there are any other ideas, then please let me know. >=20 > Cheers. >=20 > Tim > Hewlett Packard Take a look at bknpk vhdl: "... This page explains how I randomize the TTL field values. In this project I = have already discussed the issue of generating random numbers. While previo= us case was merely delay between packets, this one is a little bit complex.= When the DUT is in learning state (see FSM description), small changes in = the TTL are required. Later an attack scenario is presented to the DUT, by = vhdl bench. --random numbers generation signal rand_ttl_delta : std_logic_vector(3 downto 0) :=3D "1000"; signal rand_ttl_deltai : integer :=3D 8; ... rand_ttl_delta <=3D f_my_rand (4, rand_ttl_delta); -- 3 2 1 -- 109876543210987654321098765 if(o_tot_cnt(31 downto 5) =3D "000000000000000000000000000") = then=20 --small changes during average calculation (learning state) gen_rand :=3D "00" & rand_ttl_delta(1 downto 0); else gen_rand :=3D rand_ttl_delta; end if; tmp_ptr.data :=3D tmp_ptr.data + gen_rand; -- write(my_line, string'("gen_rand ")); hwrite(my_line, tmp_ptr.data); write(my_line, string'(" ")); --write(my_line, gen_ipv4); hwrite(my_line, o_tot_cnt); write(my_line, string'(" ")); write(my_line, now); writeline(output, my_line); ..." http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_ttl_rand.html From newsfish@newsfish Tue Dec 29 16:43:06 2015 X-Received: by 10.224.169.1 with SMTP id w1mr3340915qay.4.1376377766316; Tue, 13 Aug 2013 00:09:26 -0700 (PDT) X-Received: by 10.50.83.6 with SMTP id m6mr147971igy.1.1376377766269; Tue, 13 Aug 2013 00:09:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no2167757qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2271992qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2013 00:09:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <23fa72ef-83b5-4805-82e6-84174baa1c3d@googlegroups.com> Subject: Re: Convert time to string for textio? From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 07:09:26 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6931 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7=99= =D7=A9=D7=99, 17 =D7=91=D7=99=D7=A0=D7=95=D7=90=D7=A8 2002 15:10:08 UTC+2, = =D7=9E=D7=90=D7=AA Pamm: > How can I solve this problem? code example: First call the text library:=20 use STD.textio.all; use IEEE.STD_LOGIC_TEXTIO.all;=20 In the process declare a line variable like this:=20 variable my_line : line;=20 Now you can print in your code. Here is an example: write(my_line, string'(" HMASTER_q ")); STD.textio.hwrite(my_line, HMASTER_q); write(my_line, string'(" at ")); write(my_line, now); writeline(output, my_line); taken from bknpk vhdl http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_print_debug_tip.html From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.171.72 with SMTP id g8mr3347826qaz.7.1376378253602; Tue, 13 Aug 2013 00:17:33 -0700 (PDT) X-Received: by 10.50.153.39 with SMTP id vd7mr138487igb.9.1376378253555; Tue, 13 Aug 2013 00:17:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2272966qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2272959qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2013 00:17:33 -0700 (PDT) In-Reply-To: <3ql5hdFeh5vgU1@individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <1128590449.113793.270000@g47g2000cwa.googlegroups.com> <3ql5hdFeh5vgU1@individual.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33ca5b71-81b5-44c2-967e-ac00c624fb6a@googlegroups.com> Subject: Re: Opening and closing a file in a testbench From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 07:17:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2674 Xref: news.eternal-september.org comp.lang.vhdl:6932 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7=99= =D7=A9=D7=99, 6 =D7=91=D7=90=D7=95=D7=A7=D7=98=D7=95=D7=91=D7=A8 2005 19:34= :37 UTC+2, =D7=9E=D7=90=D7=AA Mike Treseler: > Nemesis wrote: > > I'm writing a testbench for a project, I need to read the input data fr= om > > a file. I'd need to repeat the same sequence more than once. > > Any hints? >=20 > http://groups.google.com/groups?q=3Dvhdl++file_open+char_file >=20 > -- Mike Treseler Here is a very simple example to read a file: ... process file fp : text; variable line_content : string(1 to 4); variable line_num : line; variable j : integer :=3D 0; variable char : character:=3D'0'; begin --0001 --0010 file_open(fp,"stim.txt", READ_MODE);=20 while not endfile(fp) loop=20 readline (fp, line_num);=20 READ (line_num, line_content); for j in 1 to 4 loop=20 char :=3D line_content(j); if(char =3D '0') then bin_value(4-j) <=3D '0'; else bin_value(4-j) <=3D '1'; end if; end loop;=20 wait for 10 ns; --after reading each line wait for 10ns. end loop; file_close(fp); --after reading all the lines close the file.=20 wait for 10 ns; assert false report "end of test" severity error; end process; ... taken from bknpk vhdl http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_read_text_file.html From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.173.4 with SMTP id n4mr3382312qaz.3.1376378421480; Tue, 13 Aug 2013 00:20:21 -0700 (PDT) X-Received: by 10.50.122.100 with SMTP id lr4mr139930igb.0.1376378421433; Tue, 13 Aug 2013 00:20:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2273343qab.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2273340qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2013 00:20:21 -0700 (PDT) In-Reply-To: <6j450l$217$1@diana.bcn.ibernet.es> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <6j450l$217$1@diana.bcn.ibernet.es> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: textio functions From: bknpk@hotmail.com Injection-Date: Tue, 13 Aug 2013 07:20:21 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 80 Xref: news.eternal-september.org comp.lang.vhdl:6933 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A8=D7=90=D7=A9= =D7=95=D7=9F, 10 =D7=91=D7=9E=D7=90=D7=99 1998 10:00:00 UTC+3, =D7=9E=D7=90= =D7=AA Oscar F.: > Hello : >=20 > Where can I find information about TEXTIO functions ? (read, readline, et= c) >=20 > -- > ------------------------------ > Saludos, > Oscar Ferrero. > E-mail : oscarf@jet.es > Web : http://web.jet.es/~oscarf Here is a simple read file example =20 =20 Very simple, VHDL standalone bench, to demonstrate text file read, from a = VHDL bench.=20 In this site I put many articles that help me in the assorted projects (des= ign, verification). This site is also targeted to help student. Most of the= stuff is free, but some are not. Projects=20 People who saw this page were also interested in the following work: IP TTL= filter where to use and why is it required This VHDL shows how to read text from a file. The file contains nibble in A= SCII text (1101) in each line. LIBRARY ieee; USE ieee.std_logic_1164.ALL; use STD.textio.all; ENTITY tb_read IS END tb_read; ARCHITECTURE beha OF tb_read IS signal bin_value : std_logic_vector(3 downto 0):=3D"0000"; BEGIN --Read process process file fp : text; variable line_content : string(1 to 4); variable line_num : line; variable j : integer :=3D 0; variable char : character:=3D'0'; begin --0001 --0010 file_open(fp,"stim.txt", READ_MODE);=20 while not endfile(fp) loop=20 readline (fp, line_num);=20 READ (line_num, line_content); for j in 1 to 4 loop=20 char :=3D line_content(j); if(char =3D '0') then bin_value(4-j) <=3D '0'; else bin_value(4-j) <=3D '1'; end if; end loop;=20 wait for 10 ns; --after reading each line wait for 10ns. end loop; file_close(fp); --after reading all the lines close the file.=20 wait for 10 ns; assert false report "end of test" severity error; end process; =20 taken from bknpk vhdl http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_read_text_file.html From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Random Number Generator Date: Tue, 13 Aug 2013 10:06:44 -0700 Organization: Highland Technology, Inc. Lines: 17 Message-ID: <20130813100644.513ac72a@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="8500"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19llISL53epSIsdaQkzb3Nf" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.13; x86_64-pc-linux-gnu) Cancel-Lock: sha1:wrYAEfjUfdVYrYCwCYB3OnuKvLo= Xref: news.eternal-september.org comp.lang.vhdl:6934 On Mon, 12 Aug 2013 23:15:25 -0700 (PDT) bknpk@hotmail.com wrote: > =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=97=D7=9E=D7= =99=D7=A9=D7=99, 10 =D7=91=D7=99=D7=95=D7=9C=D7=99 1997 10:00:00 UTC+3, =D7= =9E=D7=90=D7=AA Tim Holmes: While your efforts to try to help out in the community are appreciated, you just replied to a string of threads ranging in date from 1998 to 2005. I'm going to go out on a limb and say that those people either solved those problems already, or have moved on to where they no longer require solutions. --=20 Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.171.72 with SMTP id g8mr5628562qaz.7.1376414084021; Tue, 13 Aug 2013 10:14:44 -0700 (PDT) X-Received: by 10.49.97.72 with SMTP id dy8mr77175qeb.11.1376414083967; Tue, 13 Aug 2013 10:14:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2234951qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2343951qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2013 10:14:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1da8f819-a80f-4ecb-bb9c-c5cacc2f7ed0@googlegroups.com> Subject: Re: random numbers From: Andy Injection-Date: Tue, 13 Aug 2013 17:14:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1984 Xref: news.eternal-september.org comp.lang.vhdl:6935 On Monday, September 16, 2002 10:55:02 AM UTC-5, itsme wrote: > Hi,I like to write a techbench whichuses random numbers for > input data to test my hardware.Does VHDL has a built in > random number generator? Is there any library? Peter, There is a new vhdl library called Open Source VHDL Verification Methodolog= y availabe at OSVVM.org, along with user guides, and a support blog & forum= . The library provides mechanisms (protected type function/procedure calls) f= or constrained random stimulus generation, and functional coverage manageme= nt. You can even use the coverage management to directly control the random= ization constraints in the stimulus generation if desired. It is a great al= ternative to SystemVerilog UVM. OSVVM is written and supported by Jim Lewis of Synthworks, who is a frequen= t poster here, and an ardent supporter of VHDL. Andy From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.169.1 with SMTP id w1mr5662711qay.4.1376414325639; Tue, 13 Aug 2013 10:18:45 -0700 (PDT) X-Received: by 10.49.131.65 with SMTP id ok1mr62429qeb.33.1376414325556; Tue, 13 Aug 2013 10:18:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no2235449qan.0!news-out.google.com!he10ni1415qab.0!nntp.google.com!fx3no2344416qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Aug 2013 10:18:45 -0700 (PDT) In-Reply-To: <3607E0C6.A5C4C4D8@dsccc.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <3607E0C6.A5C4C4D8@dsccc.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e183406-7d37-4e49-b899-abe88875eb33@googlegroups.com> Subject: Re: Generating "random" bytes From: Andy Injection-Date: Tue, 13 Aug 2013 17:18:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6936 Try the Open Source VHDL Verification Methodology library, available at OSVVM.org. Written and supported by Jim Lewis. It facilitates constrained random stimulus generation and functional coverage to make sure you generated what you needed. Andy From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.137.137 with SMTP id w9mr11874798qat.6.1376509698612; Wed, 14 Aug 2013 12:48:18 -0700 (PDT) X-Received: by 10.49.127.132 with SMTP id ng4mr548087qeb.2.1376509698558; Wed, 14 Aug 2013 12:48:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!fx3no2489900qab.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2489897qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 12:48:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.175.37.81; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 94.175.37.81 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> Subject: How to give one clock cycle in VHDL testbench? From: Chris Waugh Injection-Date: Wed, 14 Aug 2013 19:48:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6937 Can anyone please tell me how to give one clock cycle in VHDL testbench? The output result some come with one clock cycle. How can I do that? From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.173.4 with SMTP id n4mr11986859qaz.3.1376510852615; Wed, 14 Aug 2013 13:07:32 -0700 (PDT) X-Received: by 10.49.132.5 with SMTP id oq5mr90540qeb.29.1376510852549; Wed, 14 Aug 2013 13:07:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!f7no2374589qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2491663qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 13:07:32 -0700 (PDT) In-Reply-To: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.179.193; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.179.193 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to give one clock cycle in VHDL testbench? From: Christiano Injection-Date: Wed, 14 Aug 2013 20:07:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6938 On Wednesday, August 14, 2013 4:48:18 PM UTC-3, Chris Waugh wrote: > Can anyone please tell me how to give one clock cycle in VHDL testbench? The output result some come with one clock cycle. How can I do that? Inside architecture: clock <= not clock after 5ns; OR process clk <= not clk; -- clk initialized with 0 or 1 wait for 5ns; end process; ---------------- if only one clock cycle: process clk<= '0'; wait for 5ns; clk <= '1'; wait for 5ns; clk <= '0'; end process; From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.58.96.77 with SMTP id dq13mr3389305veb.2.1376512217331; Wed, 14 Aug 2013 13:30:17 -0700 (PDT) X-Received: by 10.49.132.5 with SMTP id oq5mr94408qeb.29.1376512217247; Wed, 14 Aug 2013 13:30:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2493784qab.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2493779qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 13:30:17 -0700 (PDT) In-Reply-To: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.175.37.81; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 94.175.37.81 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> Subject: Re: How to give one clock cycle in VHDL testbench? From: Chris Waugh Injection-Date: Wed, 14 Aug 2013 20:30:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: news.eternal-september.org comp.lang.vhdl:6939 clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 5 ns; reset <= '1'; wait for 10 ns; reset <= '0'; wait for 10 ns; a <= "1011011111101110000001010101111111100001101010000111111000000111100000011110101010101100111010011100101010111101011110001010111100101011000010101101011010101111010"; -- insert stimulus here wait; end process; ------ This is the testbench. I am using a 163-bit data to get a result of 163-bit output. But the whole output result must take only one clock cycle. Could you please tell me what are the modification I need here? From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.2.202 with SMTP id 10mr12185350qak.8.1376513900045; Wed, 14 Aug 2013 13:58:20 -0700 (PDT) X-Received: by 10.49.134.37 with SMTP id ph5mr127504qeb.4.1376513900009; Wed, 14 Aug 2013 13:58:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2496577qab.0!news-out.google.com!he10ni2010qab.0!nntp.google.com!f7no2379249qan.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 13:58:19 -0700 (PDT) In-Reply-To: <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.179.193; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.179.193 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8f858808-ca94-471f-881f-7b673102d6e0@googlegroups.com> Subject: Re: How to give one clock cycle in VHDL testbench? From: Christiano Injection-Date: Wed, 14 Aug 2013 20:58:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2628 Xref: news.eternal-september.org comp.lang.vhdl:6940 On Wednesday, August 14, 2013 5:30:17 PM UTC-3, Chris Waugh wrote: > clk_process :process > > begin > > clk <= '0'; > > wait for clk_period/2; > > clk <= '1'; > > wait for clk_period/2; > > end process; > > > > > > -- Stimulus process > > stim_proc: process > > begin > > -- hold reset state for 100 ns. > > wait for 5 ns; > > reset <= '1'; > > wait for 10 ns; > > reset <= '0'; > > wait for 10 ns; > > a <= "1011011111101110000001010101111111100001101010000111111000000111100000011110101010101100111010011100101010111101011110001010111100101011000010101101011010101111010"; > > > > -- insert stimulus here > > > > wait; > > end process; > > > > ------ > > This is the testbench. I am using a 163-bit data to get a result of 163-bit output. But the whole output result must take only one clock cycle. Could you please tell me what are the modification I need here? The data will be ready in time 25 ns, so is so raise of 0 to 1 at time 30 ns. clk_process :process begin clk <= '0'; wait for 30ns; clk <= '1'; wait for 30ns; wait; end process; But the code you wrote for ghdl work, you simply write: ghdl -r testbench --stop-time=50ns --vcd=out.vcd gtkwave out.vcd From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.169.1 with SMTP id w1mr13006640qay.4.1376525513626; Wed, 14 Aug 2013 17:11:53 -0700 (PDT) X-Received: by 10.49.121.162 with SMTP id ll2mr217505qeb.0.1376525513563; Wed, 14 Aug 2013 17:11:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!fx3no2512905qab.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2512900qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 17:11:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.179.193; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.179.193 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> Subject: Generic, Ports, this '=>' is optional? From: Christiano Injection-Date: Thu, 15 Aug 2013 00:11:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6941 In some codes that exist component instantiation, sometimes it's like this: X: Gate generic map (N => 5) port map (a, b); and other times as well: X: Gate generic map (5) port map (a, b); Is there any difference or particular reason to use one or the other? From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.127.70 with SMTP id f6mr5818554qas.5.1376532325223; Wed, 14 Aug 2013 19:05:25 -0700 (PDT) X-Received: by 10.49.11.195 with SMTP id s3mr3887qeb.10.1376532325209; Wed, 14 Aug 2013 19:05:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no2522633qab.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2522628qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 19:05:25 -0700 (PDT) In-Reply-To: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.179.193; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.179.193 References: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <53dd754a-b012-40e1-b4bf-ac47420afa79@googlegroups.com> Subject: Re: Generic, Ports, this '=>' is optional? From: Christiano Injection-Date: Thu, 15 Aug 2013 02:05:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:6942 On Wednesday, August 14, 2013 9:11:53 PM UTC-3, Christiano wrote: > In some codes that exist component instantiation, sometimes it's like this: > > X: Gate generic map (N => 5) port map (a, b); > > and other times as well: > > X: Gate generic map (5) port map (a, b); > > > > Is there any difference or particular reason to use one or the other? Solved, The book The Designer's Guide to VHDL, 3rd Edition, gives all the syntax rules in detail: http://www.ashenden.com.au/vhdl-book/DG3E.html http://img829.imageshack.us/img829/9758/ppci.png From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.137.68 with SMTP id v4mr10193518qat.1.1376545052152; Wed, 14 Aug 2013 22:37:32 -0700 (PDT) X-Received: by 10.49.122.2 with SMTP id lo2mr1685qeb.14.1376545052126; Wed, 14 Aug 2013 22:37:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2418263qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2537880qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 22:37:32 -0700 (PDT) In-Reply-To: <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to give one clock cycle in VHDL testbench? From: goouse99@gmail.com Injection-Date: Thu, 15 Aug 2013 05:37:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3027 Xref: news.eternal-september.org comp.lang.vhdl:6943 Am Mittwoch, 14. August 2013 22:30:17 UTC+2 schrieb Chris Waugh: > clk_process :process > > begin > clk <= '0'; > wait for clk_period/2; > clk <= '1'; > wait for clk_period/2; > end process; > > > -- Stimulus process > stim_proc: process > begin > -- hold reset state for 100 ns. > wait for 5 ns; > reset <= '1'; > wait for 10 ns; > reset <= '0'; > wait for 10 ns; > a <= "1011011111101110000001010101111111100001101010000111111000000111100000011110101010101100111010011100101010111101011110001010111100101011000010101101011010101111010"; > > -- insert stimulus here > wait; > end process; > ------ > > This is the testbench. I am using a 163-bit data to get a result of 163-bit output. But the whole output result must take only one clock cycle. Could you please tell me what are the modification I need here? Hi Chris, you wrote "the whole output result must take only one clock cycle", but what does that mean? Do you want the result to appear after one clock cycle, or do you want the result to appear for one clock cycle and then...???? Your testbench provides a clock signal and after a short reset assigns a value for a. Since you did not mention anything about your DUT, noone can say what will happen at the DUTs output and when. The most simple synchronous device would be a register. This would produce an output after one clock cycle but hold it as long as the input value is stable. (Which actally means, the register output is only changing after the active clock edge, and assuming the input changes are synchronous to that too.) Is that what you want or something else? please be more specific about the problem and the projects background. Have a nice simulation Eilert From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.171.72 with SMTP id g8mr14213764qaz.7.1376546347370; Wed, 14 Aug 2013 22:59:07 -0700 (PDT) X-Received: by 10.49.97.72 with SMTP id dy8mr3223qeb.11.1376546347316; Wed, 14 Aug 2013 22:59:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!f7no2419556qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2539307qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Aug 2013 22:59:07 -0700 (PDT) In-Reply-To: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b5feceb-319c-40cc-8563-72980a6b6f81@googlegroups.com> Subject: Re: Generic, Ports, this '=>' is optional? From: goouse99@gmail.com Injection-Date: Thu, 15 Aug 2013 05:59:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 32 Xref: news.eternal-september.org comp.lang.vhdl:6944 Am Donnerstag, 15. August 2013 02:11:53 UTC+2 schrieb Christiano: > In some codes that exist component instantiation, sometimes it's like this: > > X: Gate generic map (N => 5) port map (a, b); > > and other times as well: > > X: Gate generic map (5) port map (a, b); > > > > Is there any difference or particular reason to use one or the other? Hi Christiano, so you already learned about Positional assignment and Named assignment. :-) While Positional assignment saves you some typing (which emacs would do automatically) it is error prone and badly maintainable. See what you can do with named association. (Most of this can be done wit positional association too, but imagine Models with high numbers of generics and ports. Can you handle all these anonymous values.) X: Gate generic map (-- select by comment and document differrent usages this way --N => 5 -- use for simulation N => 54 -- use in implementation --N => 65 -- use in some special case ) port map (putout_this => b -- place for usefull comments something_in => a); -- don't worry about the order This is just to give you an idea what's possible. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.64.202 with SMTP id f10mr14622653qai.2.1376552701014; Thu, 15 Aug 2013 00:45:01 -0700 (PDT) X-Received: by 10.50.87.40 with SMTP id u8mr69849igz.4.1376552700962; Thu, 15 Aug 2013 00:45:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2546616qab.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2546614qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 00:45:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <794d77a0-95b3-4c81-a829-c95fafdf4284@googlegroups.com> Subject: verify the IP filter using vhdl linked lists From: bknpk@hotmail.com Injection-Date: Thu, 15 Aug 2013 07:45:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3078 Xref: news.eternal-september.org comp.lang.vhdl:6945 IP TTL spoofed packet block implemented, design and verification, using vhd= l To verify the IP filter a reference model has to be build. Due to the DUT s= pecific memory model, which allows any memory size (first packets to arrive= are stored and served), the exact timing of DUT analysis is hardly predict= able. Cycle accurate verification models are not good practice anyways. Therefore an easy way to implement the reference model is to use some sort = of lists.=20 At work, using c++ and DPI, I have a lot of flexibility of STL containers, = vector, double ended queue, list etc... Where speed is traded with access f= eatures. This project is coded, design and verification, using only VHDL. So I decid= ed to use VHDL linked list feature.=20 --scorebaord item (IPV4) type scbd_item; type scbd_item_ptr is access scbd_item; -- pointer to item type scbd_item is record -- full definition of item --ignore flag if a packet starts and DUT is in freeze mode, ignore that pac= ket ignore : boolean;=20 ttl : std_logic_vector( 7 downto 0); --ttl ips : std_logic_vector(31 downto 0); --source ip cnt : std_logic_vector( 3 downto 0); --count learning : boolean; pkt_in_t : time; --packet in time (debug) next_rec : scbd_item_ptr; end record; ... if(scbd_start) then --add to scoreboard if(scbd_first) then new_sbd.learning :=3D true; new_sbd.cnt :=3D (others =3D>gt; '0'); scbd_ptr :=3D new_sbd; scbd_first :=3D false; else tmp_ptr :=3D scbd_ptr; scbd_found :=3D false; scbd_loop :=3D true; while(scbd_loop) loop --find last --check if this ip was stored before if(not scbd_found) then if(new_sbd.ips =3D tmp_ptr.ips) then scbd_found :=3D true; Please take a look at the link and give comments. http://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_main.html From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.13.136 with SMTP id c8mr15068270qaa.0.1376563027896; Thu, 15 Aug 2013 03:37:07 -0700 (PDT) X-Received: by 10.49.134.37 with SMTP id ph5mr254569qeb.4.1376563027816; Thu, 15 Aug 2013 03:37:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!f7no2437771qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2558184qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 03:37:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.175.37.81; posting-account=RBm2vQoAAADxh2j4PdlrXYbQCsr1K3m9 NNTP-Posting-Host: 94.175.37.81 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to give one clock cycle in VHDL testbench? From: Chris Waugh Injection-Date: Thu, 15 Aug 2013 10:37:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6946 The whole result should come in one clock cycle only. I am taking a 163-bit= input and doing the squaring after after reduction using irreducible polyn= omial,I am getting a 163-bit output. So I want the result of that 163-bit i= n one clock duration only. How can I do that? From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.2.202 with SMTP id 10mr15287003qak.8.1376563482107; Thu, 15 Aug 2013 03:44:42 -0700 (PDT) X-Received: by 10.50.13.105 with SMTP id g9mr94483igc.9.1376563481907; Thu, 15 Aug 2013 03:44:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2438222qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2558613qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 03:44:41 -0700 (PDT) In-Reply-To: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.166.32.218; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 82.166.32.218 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6330399e-ecc4-44a3-878e-ef962d2fea1e@googlegroups.com> Subject: Re: How to give one clock cycle in VHDL testbench? From: bknpk@hotmail.com Injection-Date: Thu, 15 Aug 2013 10:44:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2356 Xref: news.eternal-september.org comp.lang.vhdl:6947 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A8=D7=91=D7=99= =D7=A2=D7=99, 14 =D7=91=D7=90=D7=95=D7=92=D7=95=D7=A1=D7=98 2013 22:48:18 U= TC+3, =D7=9E=D7=90=D7=AA Chris Waugh: > Can anyone please tell me how to give one clock cycle in VHDL testbench? = The output result some come with one clock cycle. How can I do that? Here is an example: p_2 : process variable cnt : integer :=3D 0; variable j : integer :=3D 0; begin wait until clk_int'event and clk_int =3D '1'; if(not fifo_read_en) then wait; end if; assert false report "start fifo drive" severity warning; =20 for j in 1 to 31 loop wait until clk_int'event and clk_int =3D '1'; end loop; reset_1 <=3D '1'; for j in 1 to 9 loop wait until clk_int'event and clk_int =3D '1'; end loop; reset_1 <=3D '0'; for j in 1 to 4 loop wait until clk_int'event and clk_int =3D '1'; end loop; =20 mac_tx_tready_1 <=3D '0'; mac_rx_tvalid_1 <=3D '0'; mac_rx_tlast_1 <=3D '0'; for j in 1 to 7 loop wait until clk_int'event and clk_int =3D '1'; end loop; =20 while(fifo_done =3D '1') loop http://bknpk.no-ip.biz/my_web/SDIO/vhdl_p_2_test_control.html From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.171.72 with SMTP id g8mr16617379qaz.7.1376582779305; Thu, 15 Aug 2013 09:06:19 -0700 (PDT) X-Received: by 10.50.62.20 with SMTP id u20mr174625igr.11.1376582779256; Thu, 15 Aug 2013 09:06:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2461515qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2583882qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 09:06:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:250:1006:8239:10c9:6369:777e:ca8a; posting-account=7fT-_goAAACVOx4hsYbj89kZcA6qketZ NNTP-Posting-Host: 2001:250:1006:8239:10c9:6369:777e:ca8a User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> Subject: confusion about delta time From: sensor Injection-Date: Thu, 15 Aug 2013 16:06:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4166 Xref: news.eternal-september.org comp.lang.vhdl:6948 Hi. When I was simulating a design of cripple adder using Modelsim, I found the list output hard to understand. Code of the design was copied from <> by Volnei A. Pedroni. -- adder_cripple.vhd library ieee; use ieee.std_logic_1164.all; ------------------------------------------------- entity adder_cripple is generic(n: integer := 4); port (a, b: in std_logic_vector(n-1 downto 0); cin: in std_logic; s: out std_logic_vector(n-1 downto 0); cout: out std_logic); end adder_cripple; ------------------------------------------------- architecture adder of adder_cripple is signal c: std_logic_vector(n downto 0); begin c(0) <= cin; g1: for i in 0 to n-1 generate s(i) <= a(i) xor b(i) xor c(i); c(i+1) <= ( a(i) and b(i) ) or ( a(i) and c(i) ) or ( b(i) and c(i) ); end generate g1; cout <= c(n); end adder; ------------------------------------------------- -- testbench ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------- entity adder_tb is generic (m: integer := 4); end; ------------------------------------------------- architecture adder_tb1 of adder_tb is component adder_cripple is generic(n: integer := 4); port(a, b: in std_logic_vector(n-1 downto 0); cin: in std_logic; s: out std_logic_vector(n-1 downto 0); cout: out std_logic); end component adder_cripple; signal a, b: std_logic_vector(m-1 downto 0); signal cin: std_logic; signal s: std_logic_vector(m-1 downto 0); signal cout: std_logic; begin UUT: adder_cripple generic map(n => m) port map( a => a, b => b, cin => cin, s => s, cout => cout); a_proc: process begin a <= "0011"; wait for 200 ns; a <= "0110"; wait; end process a_proc; b_proc: process begin b <= "1000"; wait for 120 ns; b <= "1100"; wait; end process b_proc; cin_proc: process begin cin <= '0'; wait for 200 ns; cin <= '1'; wait; end process cin_proc; end adder_tb1; ------------------------------------------------- list output: ns | delta | a | b | cin | s | cout | ----|--------|------|------|-----|------|------| 0 | +0 | UUUU | UUUU | U | UUUU | U | 0 | +1 | 0011 | 1000 | 0 | UUUU | U | 0 | +3 | 0011 | 1000 | 0 | 1UU1 | U | 0 | +4 | 0011 | 1000 | 0 | 1U11 | 0 | 0 | +5 | 0011 | 1000 | 0 | 1011 | 0 | 120 | +1 | 0011 | 1100 | 0 | 1011 | 0 | 120 | +2 | 0011 | 1100 | 0 | 1111 | 0 | 200 | +1 | 0110 | 1100 | 1 | 1111 | 0 | 200 | +2 | 0110 | 1100 | 1 | 1010 | 0 | 200 | +3 | 0110 | 1100 | 1 | 0011 | 0 | 200 | +4 | 0110 | 1100 | 1 | 0011 | 1 | ----|--------|------|------|-----|------|------| Why s(3) is computed together with s(0) at 0 ns + 3 delta? Any help will be appretiated. Thx. From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.137.137 with SMTP id w9mr17426183qat.6.1376593738242; Thu, 15 Aug 2013 12:08:58 -0700 (PDT) X-Received: by 10.49.134.37 with SMTP id ph5mr362618qeb.4.1376593738214; Thu, 15 Aug 2013 12:08:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2477879qan.0!news-out.google.com!he10ni1979qab.0!nntp.google.com!fx3no2601299qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 12:08:58 -0700 (PDT) In-Reply-To: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=130.164.70.95; posting-account=eXbFJAoAAABriPnun6OC0tna1YW0cE7G NNTP-Posting-Host: 130.164.70.95 References: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> Subject: Re: confusion about delta time From: centeno.jose.manuel@gmail.com Injection-Date: Thu, 15 Aug 2013 19:08:58 +0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2725 Xref: news.eternal-september.org comp.lang.vhdl:6949 Hi. The answer is probably short -circuit operators. "The operators and, or, nand and nor are called =93short-circuit=94 operato= rs, as they only evaluate the right operand if the left operand does not de= termine the result. For example, if the left operand of the and operator is= false, we know that the result is false, so we do not need to consider the= other operand." Ashenden, Peter J. (2010-10-07). The Designer's Guide to VHDL (p. 46). Else= vier Science (book series). Kindle Edition.=20 Your test case has something special on a(2) and b(2) at delta 0.=20 On Thursday, August 15, 2013 11:06:18 AM UTC-5, sensor wrote: > c(i+1) <=3D ( a(i) and b(i) ) or >=20 > ( a(i) and c(i) ) or >=20 > ( b(i) and c(i) ); -- On delta 1 a b and cin are already assigned. Most c(i) values need other c values to be calculated, except for c(0) and = c(2).c(0) can be calculated from cin. c(2) can be calculated directly from = a(2) and b(2). Let's take a look. c(i+1) <=3D ( a(i) and b(i) ) or ( a(i) and c(i) ) or ( b(i) and c(i) ); -- For i =3D 2 c(3) <=3D ( a(2) and b(2) ) or ( a(2) and c(2) ) or ( b(2) and c(2) ); -- Substitute a and b since those are known at delta 1. c(3) <=3D ( 0 and 0 ) or ( 0 and c(2) ) or ( 0 and c(2) ); -- Values on c(2) are ignored by the "and" operator because the left parame= ter is 0. c(3) <=3D 0; -- Delta cycle 1 ends. c(3) gets a 0 on delta cycle 2 and triggers other as= signments, such as s(3) <=3D a(3) xor b(3) xor c(3);=20 I hope this helps.=20 From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 15 Aug 2013 15:44:39 -0500 Date: Thu, 15 Aug 2013 21:44:39 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: confusion about delta time References: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> In-Reply-To: <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 20 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-DkND6oTWTc7H6EPTLKXVQQiZO/EQagmm/uaNft0YZkQaeH/LldwSpJqFEiR9UtGKO9K/5DNSrS6/o16!/XoN6QViQ9dQdU1egm7UYtmv37Nb89GfZ4lFrIvaGiGNYsvJ8M1PtSzlUXCb5XUQ4Ox6oc4lWkSW!J5/dxa8sUwPMckcuQ4eDkILCl44= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1628 Xref: news.eternal-september.org comp.lang.vhdl:6950 On 15/08/13 20:08, centeno.jose.manuel@gmail.com wrote: > Hi. > > The answer is probably short -circuit operators. > Also if you don't want to see the deltas, you can use the List options in Modelsim and set "Collapse deltas". That will show you the last value of the signal just before time advances - in other words what you see on a typical waveform viewer, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.127.70 with SMTP id f6mr10428816qas.5.1376601678697; Thu, 15 Aug 2013 14:21:18 -0700 (PDT) X-Received: by 10.50.77.105 with SMTP id r9mr262032igw.13.1376601678653; Thu, 15 Aug 2013 14:21:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f7no2497940qan.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2622773qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 14:21:17 -0700 (PDT) In-Reply-To: <2b5feceb-319c-40cc-8563-72980a6b6f81@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.179.193; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.179.193 References: <494cd320-c3ea-4aca-b214-8d6edc9591a9@googlegroups.com> <2b5feceb-319c-40cc-8563-72980a6b6f81@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Generic, Ports, this '=>' is optional? From: Christiano Injection-Date: Thu, 15 Aug 2013 21:21:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2782 Xref: news.eternal-september.org comp.lang.vhdl:6951 On Thursday, August 15, 2013 2:59:07 AM UTC-3, goou...@gmail.com wrote: > Am Donnerstag, 15. August 2013 02:11:53 UTC+2 schrieb Christiano: > > > In some codes that exist component instantiation, sometimes it's like this: > > > > > > X: Gate generic map (N => 5) port map (a, b); > > > > > > and other times as well: > > > > > > X: Gate generic map (5) port map (a, b); > > > > > > > > > > > > Is there any difference or particular reason to use one or the other? > > > > Hi Christiano, > > so you already learned about Positional assignment and Named assignment. :-) > > While Positional assignment saves you some typing (which emacs would do automatically) it is error prone and badly maintainable. > > > > See what you can do with named association. > > (Most of this can be done wit positional association too, but imagine Models with high numbers of generics and ports. Can you handle all these anonymous values.) > > > > X: Gate > > generic map (-- select by comment and document differrent usages this way > > --N => 5 -- use for simulation > > N => 54 -- use in implementation > > --N => 65 -- use in some special case > > ) > > port map (putout_this => b -- place for usefull comments > > something_in => a); -- don't worry about the order > > > > This is just to give you an idea what's possible. > > > > Have a nice synthesis > > Eilert Excellent, thank you. From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.4.138 with SMTP id 10mr187222qar.8.1376620482816; Thu, 15 Aug 2013 19:34:42 -0700 (PDT) X-Received: by 10.50.92.100 with SMTP id cl4mr317484igb.8.1376620482649; Thu, 15 Aug 2013 19:34:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!fx3no2647062qab.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2647054qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 19:34:42 -0700 (PDT) In-Reply-To: <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=113.140.80.210; posting-account=7fT-_goAAACVOx4hsYbj89kZcA6qketZ NNTP-Posting-Host: 113.140.80.210 References: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f0839b1-0990-4b77-8564-1fbb92ba1db6@googlegroups.com> Subject: Re: confusion about delta time From: sensor Injection-Date: Fri, 16 Aug 2013 02:34:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6952 =E5=9C=A8 2013=E5=B9=B48=E6=9C=8816=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=94UTC+= 8=E4=B8=8A=E5=8D=883=E6=97=B608=E5=88=8658=E7=A7=92=EF=BC=8Ccenteno.j...@gm= ail.com=E5=86=99=E9=81=93=EF=BC=9A > Hi. The answer is probably short -circuit operators. "The operators and, = or, nand and nor are called =E2=80=9Cshort-circuit=E2=80=9D operators, as t= hey only evaluate the right operand if the left operand does not determine = the result. For example, if the left operand of the and operator is false, = we know that the result is false, so we do not need to consider the other o= perand." Ashenden, Peter J. (2010-10-07). The Designer's Guide to VHDL (p. = 46). Elsevier Science (book series). Kindle Edition. Your test case has som= ething special on a(2) and b(2) at delta 0. On Thursday, August 15, 2013 11= :06:18 AM UTC-5, sensor wrote: > c(i+1) <=3D ( a(i) and b(i) ) or > > ( a(i= ) and c(i) ) or > > ( b(i) and c(i) ); -- On delta 1 a b and cin are alread= y assigned. Most c(i) values need other c values to be calculated, except f= or c(0) and c(2).c(0) can be calculated from cin. c(2) can be calculated di= rectly from a(2) and b(2). Let's take a look. c(i+1) <=3D ( a(i) and b(i) )= or ( a(i) and c(i) ) or ( b(i) and c(i) ); -- For i =3D 2 c(3) <=3D ( a(2)= and b(2) ) or ( a(2) and c(2) ) or ( b(2) and c(2) ); -- Substitute a and = b since those are known at delta 1. c(3) <=3D ( 0 and 0 ) or ( 0 and c(2) )= or ( 0 and c(2) ); -- Values on c(2) are ignored by the "and" operator bec= ause the left parameter is 0. c(3) <=3D 0; -- Delta cycle 1 ends. c(3) gets= a 0 on delta cycle 2 and triggers other assignments, such as s(3) <=3D a(3= ) xor b(3) xor c(3); I hope this helps. I've got it. Thanks a lot. From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.74.72 with SMTP id t8mr734302qaj.4.1376620600565; Thu, 15 Aug 2013 19:36:40 -0700 (PDT) X-Received: by 10.50.62.20 with SMTP id u20mr317943igr.11.1376620600342; Thu, 15 Aug 2013 19:36:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!f7no2521356qan.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2647196qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 19:36:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=113.140.80.210; posting-account=7fT-_goAAACVOx4hsYbj89kZcA6qketZ NNTP-Posting-Host: 113.140.80.210 References: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d818bf3-50de-41ba-a2d4-ce233015d854@googlegroups.com> Subject: Re: confusion about delta time From: sensor Injection-Date: Fri, 16 Aug 2013 02:36:40 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6953 =E5=9C=A8 2013=E5=B9=B48=E6=9C=8816=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=94UTC+= 8=E4=B8=8A=E5=8D=884=E6=97=B644=E5=88=8639=E7=A7=92=EF=BC=8CAlan Fitch=E5= =86=99=E9=81=93=EF=BC=9A > On 15/08/13 20:08, centeno.jose.manuel@gmail.com wrote: > Hi. > > The ans= wer is probably short -circuit operators. > Also if you don't want t= o see the deltas, you can use the List options in Modelsim and set "Collaps= e deltas". That will show you the last value of the signal just before time= advances - in other words what you see on a typical waveform viewer, regar= ds Alan -- Alan Fitch Thank you for replying. From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.4.138 with SMTP id 10mr679205qar.8.1376628592324; Thu, 15 Aug 2013 21:49:52 -0700 (PDT) X-Received: by 10.49.97.72 with SMTP id dy8mr281qeb.11.1376628592254; Thu, 15 Aug 2013 21:49:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f7no2531246qan.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2657465qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 21:49:52 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.52.158.163; posting-account=C-UyLQoAAADjYG8ra6MknghJGuUbJ7Mu NNTP-Posting-Host: 121.52.158.163 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Fixed Point + Math Package/Library Verilog/VHDL From: abdkahnz@gmail.com Injection-Date: Fri, 16 Aug 2013 04:49:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:6954 Dear Every one ! Is there any library available for Fixed point plus a math Package for Verilog/VHDL. (synthesizeable) Kindly need that urgent. Regards abdkhan@hotmail.com From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.4.138 with SMTP id 10mr742933qar.8.1376629822842; Thu, 15 Aug 2013 22:10:22 -0700 (PDT) X-Received: by 10.49.59.35 with SMTP id w3mr1327qeq.8.1376629822777; Thu, 15 Aug 2013 22:10:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!xmission!news.glorb.com!f7no2532614qan.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2659022qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 22:10:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95a6fb9e-0fdd-4cea-af51-4de360420952@googlegroups.com> Subject: Re: Fixed Point + Math Package/Library Verilog/VHDL From: goouse99@gmail.com Injection-Date: Fri, 16 Aug 2013 05:10:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6955 Am Freitag, 16. August 2013 06:49:52 UTC+2 schrieb Abdullah Khan: > Dear Every one ! > > > > > > Is there any library available for Fixed point plus a math Package for Verilog/VHDL. (synthesizeable) > > > > Kindly need that urgent. > > > > Regards > > abd...@.mail... Hi, just google for "fixed point VHDL" and you will find it all. If your tools support VHDL 2008 it is part of the standard. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.173.4 with SMTP id n4mr1360906qaz.3.1376631320177; Thu, 15 Aug 2013 22:35:20 -0700 (PDT) X-Received: by 10.49.70.138 with SMTP id m10mr2321qeu.9.1376631320160; Thu, 15 Aug 2013 22:35:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no2660648qab.0!news-out.google.com!he10ni2163qab.0!nntp.google.com!fx3no2660640qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Aug 2013 22:35:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <2d3dfb9b-1bac-4e22-95d7-4d81f9a06c7c@googlegroups.com> <14ad5c01-7a44-4eb1-9bf4-8e11b802c4d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <156a22d5-c57f-4eaf-ac2a-6fdc6946addb@googlegroups.com> Subject: Re: How to give one clock cycle in VHDL testbench? From: goouse99@gmail.com Injection-Date: Fri, 16 Aug 2013 05:35:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3097 Lines: 31 Xref: news.eternal-september.org comp.lang.vhdl:6956 Am Donnerstag, 15. August 2013 12:37:07 UTC+2 schrieb Chris Waugh: [SUGGESTED CORRECTIONS IN CAPITAL LETTERS by Eilert] > The whole result should come WITHin one clock cycle only. I am taking a 1= 63-bit input and doing the squaring after after reduction using irreducible= polynomial,I am getting a 163-bit output. So I want the result of that 163= -bit AFTER one clock duration only. How can I do that? Hi Chris, so the question is not about the testbench but rather how to implement some= (synthesizable) algorithm that performs its task in just one clock cycle. Theoretically possible, but at what cost? Complex algorithms fully unrolled (no feedbacks) and fully combinatorical g= row big, really big! Which means there will be a high combinatorical delay = causing F_max of the design to be so low that it will be barely usable. Act= ually it might create the result slower compared to a highly pipelined desi= gn running for a number of clock cycles at a high clock frequency. =20 You are talking about some squaring (x^2=3Dx*x) which means a multiplicatio= n and also about a irreducible polinom which hints that you are working wit= h Galois fields (e.g. for some cryptographic design). While the GF-Multipli= cation might become quite simple, the polinomal reduction (which is some mo= dulo function in the end) can become more difficult.=20 If there is any hope for your approach it might be in the numerical propert= ies of your GF-sqaring function. You will find many such threads in the forums here and at comp.arch.fpga. And all get a similar answer like the one above. So spend some thoughts about the requirements you have for the design and i= f there's some more reasonable approach. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed1.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <520e0a39$0$26874$e4fe514c@dreader37.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: confusion about delta time Newsgroups: comp.lang.vhdl Date: Fri, 16 Aug 2013 13:17:13 +0200 References: <82253b01-52c7-4aed-8cae-5b0d8ea8e0bb@googlegroups.com> <51d140c0-80f0-4579-a38e-45fb162326f7@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 20 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1376651833 dreader37.news.xs4all.nl 26874 puiterl/195.242.97.150:60091 Xref: news.eternal-september.org comp.lang.vhdl:6957 Alan Fitch wrote: > On 15/08/13 20:08, centeno.jose.manuel@gmail.com wrote: >> Hi. >> >> The answer is probably short -circuit operators. >> > > > > Also if you don't want to see the deltas, you can use the List options > in Modelsim and set "Collapse deltas". That will show you the last value > of the signal just before time advances - in other words what you see on > a typical waveform viewer, And if you do want to see deltas but find the list window a bit awkward, you can expand deltas in the wave from viewer (at least in ModelSim). -- P@u! From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: abstracting the client/server protocol Date: Tue, 20 Aug 2013 00:54:57 +0200 Lines: 50 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net EOhigUWh1utPZQunTwMAfgAeZRdHhyIJxjWJQrw6dw5ierCuZ6 Cancel-Lock: sha1:Q29htbNm28YpmtPdmgqaDXk5P2k= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6958 Hi everyone, I'm trying to implement a testbench with a client/server abstraction [1], but I have a little problem implementing a serial protocol with bit stuffing. In my 'client' side I'd like to write/read to the serial link, but /someone/ should take care about bit stuffing. Considering that on my client I may need to do some write/read ops which are interleaved with other types of activities (say on different interfaces), I presume the 'bit stuffing' mechanism should be entirely handled on the server side. The way I split the code is the following: a test case file (testcase.vhd) which instantiate the harness and issue all necessary commands to cover the intended functions, an harness file (harness.vhd) which contains the DUT instantiation and the server instantiation (with signal mapping and so on) with a clock process, a server file (server.vhd) with the translation between the 'virtual interface' used in the test case file and the physical interface of the DUT. In testcase.vhd I have one unique process which performs the necessary ops: main: process begin init(); -- set defaults state to all DUT input signals serial_set(..., ..., to_srv, fr_srv); serial_get(..., ..., to_srv, fr_srv); ... end process; I presume that only in my server I can perform the necessary operations *with* 'bit stuffing' and I should take care about 'bit stuffing' when there's no transaction on the serial interface (serial_set/serial_get). Am I too off road? What about having a testcase where the bit stuffing is either wrong or absent? Should I use a separate server for that? Thanks for any suggestion/comment, Al [1] see 'Writing Testbenches: functional verification of HDL Models' - 2nd Edition, Janick Bergeron -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.68.138.163 with SMTP id qr3mr627549pbb.6.1377007539274; Tue, 20 Aug 2013 07:05:39 -0700 (PDT) X-Received: by 10.49.99.65 with SMTP id eo1mr70560qeb.3.1377007538845; Tue, 20 Aug 2013 07:05:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!qx7no38632490pbc.1!news-out.google.com!z6ni984pbu.0!nntp.google.com!pt2no18866581pbb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Aug 2013 07:05:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> Subject: Re: abstracting the client/server protocol From: Andy Injection-Date: Tue, 20 Aug 2013 14:05:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6959 This is the essence of transaction based modelling.=20 Simply being able to abstract the transaction data from the bit stuffing is= very useful, especially if you want to layer constrained random transactio= n generation on top of that.=20 If the interface supports it, you can also layer message-level transactions= on top of byte-level transactions. If you do this, then any arbitration be= tween multiple clients needs to occur at a point where messages from differ= ent clients do not get inter-mingled. The transaction data can include information about error injection (incorre= ctly stuffing the bits) as needed.=20 You can also use a single bidirectional record port with resolved element t= ypes (including your own resolved types, since this is not synthesizable) f= or communications in both directions with the server, simplifying the send/= receive subprogram calls. Andy From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: abstracting the client/server protocol Date: Wed, 21 Aug 2013 00:45:04 +0200 Lines: 98 Message-ID: References: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4uV9D2nt4oUIvIOmnsVFpgbrikm3MuKpe3WPbJ+lw+UjpONfc+ Cancel-Lock: sha1:+LadCfk3ugsUu5MPf9+c3nEu+pk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6960 Hi Andy, On 20/08/2013 16:05, Andy wrote: [] > Simply being able to abstract the transaction data from the bit > stuffing is very useful, especially if you want to layer constrained > random transaction generation on top of that. that is a personal goal and be sure I'll post something on the topic as soon as I get there! > > If the interface supports it, you can also layer message-level > transactions on top of byte-level transactions. If you do this, then > any arbitration between multiple clients needs to occur at a point > where messages from different clients do not get inter-mingled. For the time being my model is extremely simple: one test case -> one client -> one file. My testcases will leverage the first one which is aiming to test the interface. I've seen a paper [1] presenting a similar approach with cases specified in different architectures of the same unit. I do not really see the advantage of doing this, but I do not have a strong opinion either. Having multiple clients all accessing the server may require an extra layer to ensure message integrity. But I do not see the point of having multiple clients interacting unless the 'message integrity' is a feature of the device under test and has to be verified. > The transaction data can include information about error injection > (incorrectly stuffing the bits) as needed. This is certainly part of the verification plan, even though I have no idea as of now on how to implement that. At the moment I have a write/read abstract procedures that initiate the transaction from the client and a 'dispatcher' process on the server side that calls the appropriate subprograms to interact with the DUT. Bit stuffing instead should be something that occurs independently from the client transmitting anything (I need to stuff a bit when no transaction is occurring as well). This means that a concurrent process should monitor the 'wire' and inject a '1' each N '0's. While I could potentially disrupt the bit stuffing during a transaction (with a special flag in the record port?), I still cannot see how I could do this when no transaction is occurring... > > You can also use a single bidirectional record port with resolved > element types (including your own resolved types, since this is not > synthesizable) for communications in both directions with the server, > simplifying the send/receive subprogram calls. well, indeed I do not favor too much the choice of having two separate record ports to handle the two directions. In the end the two records have great similarities and the main difference is simply the 'direction' (to or from the server). Currently this is what I have: type kind is (RD, WR); type to_srv_ctrl is record -- abstract register to server it : integer range 0 to 20; -- interface type ad : integer range 0 to 65535; -- address dt : integer range 0 to 65535; -- data op : kind; -- read/write operation go : boolean; -- initiate operation end record; type fr_srv_ctrl is record -- abstract register from server ad : integer range 0 to 65535; -- address dt : integer; -- return data from server op : kind; -- read/write operation go : boolean; -- data ready end record; with the interface type 'it' I select an heterogeneous set of interfaces, and the 'go' flag is used to initiate the transaction. In principle I should be able to merge most of the elements. It is not too much overhead in the subprogram call interface (only two signals more), but it is annoying to have structures which do seem quite similar. While these record types are extremely generic and can suit several type of transactions, they suffer from the possibility to add 'ad hoc features' in the transaction that are 'it' specific (like the bit-stuffing error injection). Any suggestion/comments? Al [1] Accelerating Verification Through Pre-Use of System-Level, Transaction Based Testbench Components From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.13.136 with SMTP id c8mr8004590qaa.0.1377067608907; Tue, 20 Aug 2013 23:46:48 -0700 (PDT) X-Received: by 10.50.2.74 with SMTP id 10mr297084igs.15.1377067608830; Tue, 20 Aug 2013 23:46:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!f7no3685146qan.0!news-out.google.com!he10ni2777qab.0!nntp.google.com!fx3no3851161qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Aug 2013 23:46:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.204.200.243; posting-account=NvmkYAoAAAD7N7ZOW9N96-sKRY-ATgMN NNTP-Posting-Host: 49.204.200.243 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Matrix multiplication From: himu8055@gmail.com Injection-Date: Wed, 21 Aug 2013 06:46:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6961 Hello, i am trying to write verilog code for matrix multiplication 3X3 using memory can i get from u the state machine which u had for matrix multiplication From newsfish@newsfish Tue Dec 29 16:43:07 2015 X-Received: by 10.224.137.68 with SMTP id v4mr9639158qat.1.1377095097605; Wed, 21 Aug 2013 07:24:57 -0700 (PDT) X-Received: by 10.49.1.112 with SMTP id 16mr290964qel.7.1377095097579; Wed, 21 Aug 2013 07:24:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!q10no9803qai.0!news-out.google.com!he10ni2777qab.0!nntp.google.com!fx3no3890010qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Aug 2013 07:24:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2e5d79c5-37d5-4d2e-9a9c-9a6690971e69@googlegroups.com> Subject: Re: abstracting the client/server protocol From: Andy Injection-Date: Wed, 21 Aug 2013 14:24:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6962 Al, The referenced paper is from Synthworks, which offers an EXCELLENT testbenc= h & verification course. I have taken it, and I strongly recommend it. The = course also covers the OSVVM library for constrained random stimulus genera= tion and functional coverage models. Jim Lewis also provides a lot of usefu= l packages and example code in addition to OSVVM for his students. One thing to consider about test cases is whether or not there may be inter= action between test case scenarios. Simultaneous testing of multiple test c= ases helps verify expected or expose unexpected interactions. If you only have one or a few simulator licenses available, simultaneous te= sting is more efficient, since it often takes less time than two separate t= ests run sequentially. Unless you go to great lenghts to configure empty a= rchitectures for unused RTL entities in each specific test, simulation time= correlates with the number of clock cycles pretty well, no matter how many= things the RTL model is doing in each of those clock cycles. On the other hand, if you have access to a sim farm with lots of licenses, = running separate test cases on separate machines in parallel is faster. Depending on where your "test case code" is (at the top level architecture,= or in a test controller entity at a lower level), using separate architect= ures for one common entity may or may not make that much difference. Creating resolved types for integers and booleans is pretty simple: pick a = value that is "off" (does not interfere with the results), and drive that v= alue (e.g. 0 or false) when you want to use it as an input. The resolution = function can assert a warning (or worse) if more than one driver value is n= on-off (contention should not occur), and then it can simply return any non= -off value in the received array.=20 If I understand your situation, the BFM that turns transactions into bits o= n its "physical" interface is cranking out some bits whether or not a "real= transaction" is in progress. You could have a separate interface for an er= ror injection transaction that simply tells the BFM to create specific erro= rs while not generating bits related to real transactions. You can also add= argument(s) to your real transaction procedures (defaulted to off) that ca= use the transaction to be executed with errors injected. Andy From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Possible Quartus Bug Date: Thu, 22 Aug 2013 16:57:49 -0700 Organization: Highland Technology, Inc. Lines: 23 Message-ID: <20130822165749.7c3649a4@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="381"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+roXdF4EW+LkcCdN8adBdn" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:bz1H0nvghm88C0Gtre6cnHRuXdU= Xref: news.eternal-september.org comp.lang.vhdl:6963 Just wanted to make sure this is an actual bug before I report it to Altera. I'm compiling as VHDL-2008, and I'm getting the error message: type of identifier "A_i" does not agree with its usage as "std_logic_vector" What I've got is (in various and correct places): port A: inout std_logic_vector(31 downto 1); signal A_i: std_ulogic_vector(31 downto 1); A <= A_i when drive_addr else (others => 'Z'); The error goes away when I forcibly cast A_i to std_logic_vector, but aren't they supposed to be compatible without a cast? Interestingly, I'm doing the same thing with some std_(u)logic signals, and they're working fine. Thanks, Rob -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:07 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer02.iad.highwinds-media.com!feed-me.highwinds-media.com!peer01.fr7!news.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx29.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Possible Quartus Bug References: <20130822165749.7c3649a4@rg.highlandtechnology.com> In-Reply-To: <20130822165749.7c3649a4@rg.highlandtechnology.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130822-1, 22/08/2013), Outbound message X-Antivirus-Status: Clean Lines: 69 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1377242786 86.29.12.221 (Fri, 23 Aug 2013 07:26:26 UTC) NNTP-Posting-Date: Fri, 23 Aug 2013 07:26:26 UTC Organization: virginmedia.com Date: Fri, 23 Aug 2013 08:26:23 +0100 X-Received-Bytes: 3535 Xref: news.eternal-september.org comp.lang.vhdl:6964 On 23/08/2013 00:57, Rob Gaddi wrote: > Just wanted to make sure this is an actual bug before I report it to > Altera. > > I'm compiling as VHDL-2008, and I'm getting the error message: > type of identifier "A_i" does not agree with its usage as > "std_logic_vector" > > What I've got is (in various and correct places): > port A: inout std_logic_vector(31 downto 1); > signal A_i: std_ulogic_vector(31 downto 1); > A <= A_i when drive_addr else (others => 'Z'); > > The error goes away when I forcibly cast A_i to std_logic_vector, but > aren't they supposed to be compatible without a cast? Interestingly, > I'm doing the same thing with some std_(u)logic signals, and they're > working fine. > > Thanks, > Rob > This might be related to a recent conversation on the P1076 reflector list (see below). I hope Paul & Jerry don't mind me reposting this, Hans. www.ht-lab.com Paul, This change was intentional and its main purpose was to reduce code bloat in standard and user packages. Typically, both implementations of function 'f' you have mentioned would be almost identical, the only difference being resolved/unresolved argument and/or result types. There are numerous examples in standard packages providing arithmetic operators and conversion functions where 2008 versions are less than half the size of previous versions. The best practical (although not exactly standard) solution to your problem would be to use pragmas to exclude offending definitions from compilation in 2008 mode. I'm talking about something like this: --vhdl_comp_off -2008 function f(x : std_logic_vector) return integer; --vhdl_comp_on function f(x : std_ulogic_vector) return integer; Otherwise, separate code base must be maintained for older versions of the standard. Thank you, Jerry On Thu, Aug 22, 2013 at 10:34 AM, Paul wrote: The vhdl-2008 std_logic_1164 package changes the definition of std_logic_vector. Previously it was a distinct type from std_ulogic_vector. In vhdl-2008 it is a subtype of std_ulogic_vector. This change is not backwards compatible as it can result in homograph conflicts. For instance: function f(x : std_logic_vector) return integer; function f(x : std_ulogic_vector) return integer; Pre-2008 these functions could coexist. In vhdl-2008 they are homographs and cannot coexist. Is this a known and expected incompatibility? Paul From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.137.68 with SMTP id v4mr20457qat.1.1377276327962; Fri, 23 Aug 2013 09:45:27 -0700 (PDT) X-Received: by 10.49.30.8 with SMTP id o8mr30697qeh.36.1377276327917; Fri, 23 Aug 2013 09:45:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!xmission!news.glorb.com!fx3no4136911qab.0!news-out.google.com!he10ni3061qab.0!nntp.google.com!fx3no4136902qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Aug 2013 09:45:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <20130822165749.7c3649a4@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72b28675-211c-4d94-818f-928bd517ac3a@googlegroups.com> Subject: Re: Possible Quartus Bug From: Andy Injection-Date: Fri, 23 Aug 2013 16:45:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6965 These are two separate issues from the same language change. For 2008 (and on) the VHDL standard defines std_logic_vector as a resolved = subtype of std_ulogic_vector. Before 2008, they were separate (albeit "clos= ely related") types of arrays of std_logic and std_ulogic, respectively. This means that, for 2008-compliant tools, you can directly assign a std_ul= ogic_vector to/from a std_logic_vector. In short, SLV and SULV are now inte= roperable just like SL and SUL always have been. It also means that, for 2008-compliant tools, the signature recognition for= two subprograms with the same signature except one uses SLV and the other = SULV, now fails, causing an error if two such subprograms are available to = choose from. This is because VHDL subprogram signature recognition uses the= types of the arguments and return values, instead of the subtypes. Note th= at even in pre-2008 language versions, you could not have two subprograms w= ith the only difference between them being of SL vs SUL arguments either. B= ut since that restriction has been in place for a very long time, there are= n't too many designs that violate it. The only thing I would make sure of in Rob's case is that 2008 compatibilit= y is enabled for his quartus project. Most tools will continue to default t= o older versions of the standard for quite some time, since there are (mino= r) backward compatibility issues (2008 also added new reserved words, inclu= ding some PSL keywords). If it is enabled, then this sure looks like a bug = to me.=20 Some simulators will allow you to compile different modules in the same sim= ulation with different version settings, and still interoperate. I don't kn= ow if there is a way to do that for any synthesis tools, but it is becoming= more important. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Possible Quartus Bug Date: Fri, 23 Aug 2013 10:27:34 -0700 Organization: Highland Technology, Inc. Lines: 22 Message-ID: <20130823102734.2d3b5334@rg.highlandtechnology.com> References: <20130822165749.7c3649a4@rg.highlandtechnology.com> <72b28675-211c-4d94-818f-928bd517ac3a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="22532"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kmFwVC7kj9d7luDvvwKoj" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:iGVTfZdwwn4XoaDYn0oaoPmvtkI= Xref: news.eternal-september.org comp.lang.vhdl:6966 On Fri, 23 Aug 2013 09:45:27 -0700 (PDT) Andy wrote: > > It also means that, for 2008-compliant tools, the signature recognition for two subprograms with the same signature except one uses SLV and the other SULV, now fails, causing an error if two such subprograms are available to choose from. This is because VHDL subprogram signature recognition uses the types of the arguments and return values, instead of the subtypes. Note that even in pre-2008 language versions, you could not have two subprograms with the only difference between them being of SL vs SUL arguments either. But since that restriction has been in place for a very long time, there aren't too many designs that violate it. > > The only thing I would make sure of in Rob's case is that 2008 compatibility is enabled for his quartus project. Most tools will continue to default to older versions of the standard for quite some time, since there are (minor) backward compatibility issues (2008 also added new reserved words, including some PSL keywords). If it is enabled, then this sure looks like a bug to me. > > Some simulators will allow you to compile different modules in the same simulation with different version settings, and still interoperate. I don't know if there is a way to do that for any synthesis tools, but it is becoming more important. > > Hope this helps, > > Andy Thanks, it does. Quartus's VHDL-2008 support is lacking in a bunch of ways. There's no support for *_vector, no ?? operator, no automatic ?? when using std_logic in an if statement, no unary logic reduction operators, the list goes on. Basically, they got the fixed point package working and called it a day. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.36.198 with SMTP id u6mr699257qad.6.1377290116267; Fri, 23 Aug 2013 13:35:16 -0700 (PDT) X-Received: by 10.49.13.10 with SMTP id d10mr69830qec.28.1377290116208; Fri, 23 Aug 2013 13:35:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no4160214qab.0!news-out.google.com!he10ni3256qab.0!nntp.google.com!fx3no4160212qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Aug 2013 13:35:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=199.61.25.252; posting-account=9w-4kgoAAADAzdzx7OyyRPaT1vGO9fwG NNTP-Posting-Host: 199.61.25.252 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ac4915e-bce4-4fdc-b118-0905db19a66c@googlegroups.com> Subject: Equations in Vector Range Definitions From: guyanalog@gmail.com Injection-Date: Fri, 23 Aug 2013 20:35:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 23 Xref: news.eternal-september.org comp.lang.vhdl:6967 Is it acceptable to use equations in the vector range description of a signal where the parameters are generics, or does this adversely affect synthesis? What I have now: generic( BYTE_NUM : natural range 10 downto 1 := 3; -- # bytes (used somewhere else) BYTE_BITS : natural range 10 downto 1 := 24 -- # bits for above bytes ); signal vec_int : std_logic_vector(BYTE_BITS - 1 downto 0); What I was thinking of changing it to (eliminates a generic): generic( BYTE_NUM : natural range 10 downto 1 := 3 -- # bytes (used somewhere else) ); signal vec_int : std_logic_vector(8*BYTE_NUM - 1 downto 0); Does the multiplier generate unwanted logic? Thanks. From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Equations in Vector Range Definitions Date: Fri, 23 Aug 2013 17:33:46 -0400 Organization: Alacron, Inc. Lines: 36 Message-ID: References: <1ac4915e-bce4-4fdc-b118-0905db19a66c@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 23 Aug 2013 21:33:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="2266"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ebcRXzDLwmRMf2WP1eWvT/1mnNRzq/9k=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <1ac4915e-bce4-4fdc-b118-0905db19a66c@googlegroups.com> Cancel-Lock: sha1:ovKQ5VXB6z+cm4sCbqbX0OjU1/Y= Xref: news.eternal-september.org comp.lang.vhdl:6968 guyanalog@gmail.com wrote: > Is it acceptable to use equations in the vector range description of a signal where the parameters are generics, or does this adversely affect synthesis? > > > What I have now: > > generic( > BYTE_NUM : natural range 10 downto 1 := 3; -- # bytes (used somewhere else) > BYTE_BITS : natural range 10 downto 1 := 24 -- # bits for above bytes > ); > > signal vec_int : std_logic_vector(BYTE_BITS - 1 downto 0); > > > What I was thinking of changing it to (eliminates a generic): > > generic( > BYTE_NUM : natural range 10 downto 1 := 3 -- # bytes (used somewhere else) > ); > > signal vec_int : std_logic_vector(8*BYTE_NUM - 1 downto 0); > > Does the multiplier generate unwanted logic? > > Thanks. 1) Multiplying by a power of 8 doesn't add logic. 2) Any amount of arithmetic that evaluates to a constant at synthesis time doesn't add logic. 3) I can't imagine what sort of logic could be created to end up with a variable width std_logic_vector! 4) Wouldn't it be easier and faster to try this on your synthesis tool rather than posting code to a newsgroup? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.74.72 with SMTP id t8mr1544521qaj.4.1377302115995; Fri, 23 Aug 2013 16:55:15 -0700 (PDT) X-Received: by 10.49.11.195 with SMTP id s3mr90362qeb.10.1377302115978; Fri, 23 Aug 2013 16:55:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!q10no277688qai.0!news-out.google.com!he10ni3256qab.0!nntp.google.com!fx3no4178840qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Aug 2013 16:55:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.27.151.26; posting-account=pWVc5woAAAArSjofm5evqScWGS6yHZfr NNTP-Posting-Host: 83.27.151.26 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> Subject: addition not work in vhdl From: marcin00022@gmail.com Injection-Date: Fri, 23 Aug 2013 23:55:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 66 Xref: news.eternal-september.org comp.lang.vhdl:6969 Hello I want to draw squere 50 x 50 pixel on the screen (640 x 480) begining in mouse position but it change size .. somtimes it is (20 x 50) or (50 x 30) or (30 x 30) and i don't have slightest idea what is wrong ... code: librarposy IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.ALL; entitposy ACursor is port ( clk: in STD_LOGIC; posy: in STD_LOGIC_VECTOR (9 downto 0); posx: in STD_LOGIC_VECTOR (9 downto 0) ; cursor_posy_in: in STD_LOGIC_VECTOR (7 downto 0); cursor_posx_in: in STD_LOGIC_VECTOR (7 downto 0) ; ro : out STD_LOGIC_VECTOR (2 downto 0); go : out STD_LOGIC_VECTOR (2 downto 0); bo : out STD_LOGIC_VECTOR (2 downto 0); ri : in STD_LOGIC_VECTOR (2 downto 0); gi : in STD_LOGIC_VECTOR (2 downto 0); bi : in STD_LOGIC_VECTOR (2 downto 0) ); end ACursor; architecture behaviour of ACursor is signal cursor_posy: unsigned (9 downto 0); signal cursor_posx: unsigned (9 downto 0) ; begin cursor_posy <= unsigned(cursor_posy_in(6 downto 0) & "000"); cursor_posx <= unsigned(cursor_posx_in(6 downto 0) & "000"); process(posx,posy) begin if(rising_edge(clk)) then if (unsigned(posx) < 4) or (unsigned(posx) > 636) or (unsigned(posy) < 5) or (unsigned(posy) > 477) then ro <= "000"; go <= "000"; bo <= "000"; elsif (( unsigned(posx) = cursor_posx) OR (unsigned(posx) = ((cursor_posx) + x"32")) or (unsigned(posy) = cursor_posy) OR (unsigned(posy) = ((cursor_posy)+ x"32" ))) and (( unsigned(posx) >= cursor_posx) and (unsigned(posx) <= ((cursor_posx) + x"33")) and (unsigned(posy) >= cursor_posy) and (unsigned(posy) <= ((cursor_posy)+ x"33" ))) then ro <= "111"; go <= "000"; bo <= "000"; else ro <= ri; go <= gi; bo <= bi; end if; end if; end process; end behaviour; It feels like it's not adding properly From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: addition not work in vhdl Date: Sat, 24 Aug 2013 04:54:57 +0200 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 24 Aug 2013 02:54:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="814911dd99403fa1ae68f04371b03153"; logging-data="25893"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/1NqdE1lPwh6CbXqrvQVsC" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> Cancel-Lock: sha1:GWC6/keiUuypzNN7PLSh2VrbcFQ= Xref: news.eternal-september.org comp.lang.vhdl:6970 > Hello > I want to draw squere 50 x 50 pixel on the screen (640 x 480) begining in mouse position > > but it change size .. somtimes it is (20 x 50) or (50 x 30) or (30 x 30) and i don't have slightest idea what is wrong ... > > code: [...] > It feels like it's not adding properly Change feelings with knowledge! Just write a testbench. regards Bart From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.13.136 with SMTP id c8mr3143542qaa.0.1377327346744; Fri, 23 Aug 2013 23:55:46 -0700 (PDT) X-Received: by 10.50.80.78 with SMTP id p14mr33725igx.6.1377327346668; Fri, 23 Aug 2013 23:55:46 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!q10no659187qai.0!news-out.google.com!he10ni3256qab.0!nntp.google.com!fx3no4562142qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 23 Aug 2013 23:55:46 -0700 (PDT) In-Reply-To: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=223.227.97.97; posting-account=hwy8AQoAAAAXhrq-2rjjmxyei7PRsYAW NNTP-Posting-Host: 223.227.97.97 References: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: addition not work in vhdl From: Vipin Lal Injection-Date: Sat, 24 Aug 2013 06:55:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 4 Xref: news.eternal-september.org comp.lang.vhdl:6971 Instead of process(posx,posy) , Use process(clk). Not sure whether it will change the mentioned error, but you need to change the sensitivity list anyway. From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.13.136 with SMTP id c8mr6032413qaa.0.1377373960232; Sat, 24 Aug 2013 12:52:40 -0700 (PDT) X-Received: by 10.49.104.148 with SMTP id ge20mr234400qeb.2.1377373960177; Sat, 24 Aug 2013 12:52:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q10no712804qai.0!news-out.google.com!he10ni3256qab.0!nntp.google.com!fx3no4619010qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 24 Aug 2013 12:52:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.27.151.26; posting-account=pWVc5woAAAArSjofm5evqScWGS6yHZfr NNTP-Posting-Host: 83.27.151.26 References: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48449d99-19b5-45e5-a343-746e7602c9dd@googlegroups.com> Subject: Re: addition not work in vhdl From: marcin00022@gmail.com Injection-Date: Sat, 24 Aug 2013 19:52:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1572 Xref: news.eternal-september.org comp.lang.vhdl:6972 the sensitivity list can't be the case becoiuse is only for symulator anyway. and I vreated the test bench like sugest Bart and everything is fine ... so my feelings based on knowledge is that some optimalization or place and route behave different than i asume ... And that is not the first time when orginal project not work but symulation does That why i am asking if I broke some rule in this code ... From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: addition not work in vhdl Date: Sun, 25 Aug 2013 18:41:36 +0200 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> <48449d99-19b5-45e5-a343-746e7602c9dd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 25 Aug 2013 16:41:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="b4e166bc2801bcb8b0857ab71d01814c"; logging-data="25961"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+UOCs9V8HO0UM1G+nbqrNu" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <48449d99-19b5-45e5-a343-746e7602c9dd@googlegroups.com> Cancel-Lock: sha1:LfinrJPtk/zJyX/duNwnC0oljk8= Xref: news.eternal-september.org comp.lang.vhdl:6973 Hello Marcin! > and I vreated the test bench like sugest Bart and everything is fine ... Can you publish your testbench? So maybe others (and I) are able to check it. regards, Bart From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.223.198 with SMTP id il6mr6335454qab.7.1377509170874; Mon, 26 Aug 2013 02:26:10 -0700 (PDT) X-Received: by 10.49.11.195 with SMTP id s3mr28292qeb.10.1377509170852; Mon, 26 Aug 2013 02:26:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q10no895172qai.0!news-out.google.com!he10ni3465qab.0!nntp.google.com!fx3no4808378qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Aug 2013 02:26:10 -0700 (PDT) In-Reply-To: <48449d99-19b5-45e5-a343-746e7602c9dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <8b8ae991-977c-4afe-9082-ed01f6239d97@googlegroups.com> <48449d99-19b5-45e5-a343-746e7602c9dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <496437d9-fd58-45f1-a55d-5e302b585b9a@googlegroups.com> Subject: Re: addition not work in vhdl From: Thomas Stanka Injection-Date: Mon, 26 Aug 2013 09:26:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2780 Xref: news.eternal-september.org comp.lang.vhdl:6974 Am Samstag, 24. August 2013 21:52:40 UTC+2 schrieb marci...@gmail.com: > the sensitivity list can't be the case becoiuse is only for symulator an= yway. > > and I vreated the test bench like sugest Bart and everything is fine ...= =20 If you build testbench and compare simualtion result to real behavior and s= ee differences, you have sensitivity list as one possible source of differe= nces. I would eliminate all obvious problems first before starting to spen= d time with debug of the high sophisticated bugs. =20 > so my feelings based on knowledge is that some optimalization or place an= d route behave different than i asume ...=20 > And that is not the first time when orginal project not work but symulati= on does=20 > That why i am asking if I broke some rule in this code ... The code itself seems fine to me when it comes to differences between simul= ation and real world if you would correct the sensitivity list. But this is only half of physical design. A major source of differences between simulation and real device are wrong = treated asynchronous interfaces. Next source would be wrong application of = timing analysis.=20 Maybe there is an input in your design asynchronous to clock that is not pr= oper handled(eg 2stage FF)?=20 Are you sure you did static timing analysis (STA) correct? Did you perform backannotated simulation with this design and is that equiv= alent to behavioral simulation? best regards=20 Thomas From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Active sources Date: Mon, 26 Aug 2013 15:45:12 +0300 Organization: A noiseless patient Spider Lines: 42 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 26 Aug 2013 12:45:14 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="7799"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nFixzRNSmE5viGycXMXXyZHKniIqpni4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 Cancel-Lock: sha1:B0VG8pvotMLpTob5fvT7bIJmRUY= Xref: news.eternal-september.org comp.lang.vhdl:6975 I read in http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_12.HTM that signal is active during simulation cycle - If one of its sources is active or - the signal is named in the formal part of an association element in a port association list and the the corresponding actual is active. =1= This immediately raises the question: how is the activity status propagated? We see that the source or active port's actual causes formal to be active. I do not understand why activity propagates down the hierarchy: when you have active parent module signal then, connected as input to the children, submodules will see it's activity as formal part activity. Why activity should not propagate in the opposite direction, through the output ports, from formal part to the actual? I see a similar double standard in the driving value definition. It says that if signal source is a port then formal part driver is used. You cannot drive the input port this way but this is not necessary - effective values are rather propagated downwards. We first propagate info upwards through output ports by driving values and then signals propagate downwards as effective values. Right? I see no such bi-directional mechanism for the signal activity propagation. =2= Moreover, I do not see how the signal activity flag is connected to anything else. For instance, I see how driver's value originates from the transaction, how this determines the driving values of signals and, furthermore, the effective values. However, I see that all what determines the signal activity flag is the activity flag of another signal! I want to know how is the first active signal can ever appear in such system? =3= Ports are also sources. Why sources and ports are treated separately? BTW, why not to instantiate the drivers for the ports also? To avoid delta-cycle delays in ports? =4= BTW, is slice a signal? I have such a mess in my head. Will Ashenden fix it? From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.236.63.165 with SMTP id a25mr5183417yhd.43.1377525351717; Mon, 26 Aug 2013 06:55:51 -0700 (PDT) X-Received: by 10.182.75.232 with SMTP id f8mr6725obw.0.1377525351676; Mon, 26 Aug 2013 06:55:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!q10no920340qai.0!news-out.google.com!he10ni3465qab.0!nntp.google.com!fx3no4836221qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Aug 2013 06:55:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <1ac4915e-bce4-4fdc-b118-0905db19a66c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <143f0c37-5687-4edd-9838-75a0ca693f04@googlegroups.com> Subject: Re: Equations in Vector Range Definitions From: Andy Injection-Date: Mon, 26 Aug 2013 13:55:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 18 Xref: news.eternal-september.org comp.lang.vhdl:6976 Gabor's points are very good. However, multiply/divide (of unsigned quantities) by a constant power of 2 = generates a simple shift, usually resulting in zero additional logic. The concept of constant values is different for simulation and synthesis. I= n synthesis, it includes such things as for-loop indices. When the for-loop= is unrolled, the index value is known for each unrolled iteration. Thus an= y calculation of index and other constant values is also a constant. It is possible to describe VHDL functions/procedures which return variable = width results, but the width must be constant (see above). As an example, t= o_unsigned() takes a size argument to determine the size of the result. One= could define a to_unsigned(natural) function that just returned enough bit= s to hold the result, based on the value being converted. However, it would= likely not be synthesizable unless it was called with a constant (see abov= e) value, which would severely limit its usefulness.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.165.82 with SMTP id h18mr10880406qay.3.1377527603828; Mon, 26 Aug 2013 07:33:23 -0700 (PDT) X-Received: by 10.49.24.132 with SMTP id u4mr22399qef.17.1377527603686; Mon, 26 Aug 2013 07:33:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!q10no924257qai.0!news-out.google.com!he10ni3465qab.0!nntp.google.com!fx3no4841052qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Aug 2013 07:33:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9c6f413d-2781-49b8-a3c6-b49285837bcc@googlegroups.com> Subject: Re: Active sources From: Andy Injection-Date: Mon, 26 Aug 2013 14:33:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 36 Xref: news.eternal-september.org comp.lang.vhdl:6977 Ashendon may have been thinking that "one of its sources is active" covers = output signal "propagating" (see 3 below) back up through the hierarchy (fr= om submodule to module). Is he using "sources" synonymously with "drivers"? =3D2=3D Signals are not the only things that cause events in simulation. De= lays on "wait ... for" statements also cause events to be directly schedul= ed, with the process owning the wait statement being sensitive to the sched= uled event. I remember being confused by a waveform at the end of one of my= simulations. The clock and all signal activity had stopped a long time bef= ore the simulation actually stopped. Then I realized my testbench had a tim= eout on a wait statement that had not yet expired when I killed the clock (= and thus all signal activity) in the testbench. The simulation had continue= d to "run" even though the wait statement had already triggered. Also, ever= y process is executed at time zero. =3D3=3D Instead of a signal "propagating up through the hierachy", think of= ports as just a short-hand way of aliasing external signals (or aliasing e= xternal aliases to external signals). In 1076-2008, with the addition of re= ferences to external signals, one could do the same thing as ports and port= maps with aliases to signals/aliases up or down the hierachical chain. The modality of ports allows the compiler to verify the appropriateness of = driving and/or reading those aliases. And since an alias is nothing but ano= ther reference to an existing signal, there is no delta cycle propagation d= elay associated with the ports/maps between driver and reader. Note also that 2008 allows expressions in port maps (beyond type conversion= s). These break the implicit aliases before and after the expression, and a= n implied process (concurrent statement) is inserted between the two aliase= s/signals. The same delta cycle happened before when type conversions were = used on port maps. I do not know if a built-in type conversion between "clo= sely related" ports/actuals (really just a compile-time accounting trick) i= nserts a delta delay or not. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: abstracting the client/server protocol Date: Mon, 26 Aug 2013 23:18:05 +0200 Lines: 100 Message-ID: References: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> <2e5d79c5-37d5-4d2e-9a9c-9a6690971e69@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Ur2WDSQMQJG+oLuZJHgS+wuAmBNK3hG/ae51+CiNsQDA1rUNPa Cancel-Lock: sha1:St1d+7sE8gm/deFJ3P9unnNwvIY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: <2e5d79c5-37d5-4d2e-9a9c-9a6690971e69@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6978 Hi Andy, sorry for the late reply, I was offline for few days... On 21/08/2013 16:24, Andy wrote: [] > The referenced paper is from Synthworks, which offers an EXCELLENT > testbench & verification course. I have taken it, and I strongly > recommend it. I'm trying to build up a crew of people interested in the course here at Cern, in order to get an on-site course and maybe with a 'discount' considering that we are part of an international organization ;-) > > One thing to consider about test cases is whether or not there may be > interaction between test case scenarios. Simultaneous testing of > multiple test cases helps verify expected or expose unexpected > interactions. I see your point. For what concern the serial protocol in the OP each transaction is atomic and there's no 'memory' in the system to induce any interaction. OTOH there are other interfaces which are 'active' simultaneously and may have an impact when stimulated concurrently. If I need to have a simultaneous testing than I would need to rework the test case a little bit. Since currently I have one sequence of transactions in one process, I may think about using two processes which run concurrently and see what is the interaction. > > If you only have one or a few simulator licenses available, > simultaneous testing is more efficient, since it often takes less > time than two separate tests run sequentially. Unless you go to > great lenghts to configure empty architectures for unused RTL > entities in each specific test, simulation time correlates with the > number of clock cycles pretty well, no matter how many things the RTL > model is doing in each of those clock cycles. I agree and moreover I do not have a set of configurations to play with, therefore I would need to manually remove/add components along the way (too painful). > > On the other hand, if you have access to a sim farm with lots of > licenses, running separate test cases on separate machines in > parallel is faster. At Cern we have several licenses and I'm planning to run simulations in batch mode through our batch system. Unfortunately I haven't spent enough time on this part yet and so far I'm running simulations one after the other one on a single license machine. > > Depending on where your "test case code" is (at the top level > architecture, or in a test controller entity at a lower level), using > separate architectures for one common entity may or may not make that > much difference. As of now my 'test case' is at the top level. The harness instantiate the most of the common parts (DUT, BFM, clock generation) and the 'test case' instantiate the harness. > > Creating resolved types for integers and booleans is pretty simple: > pick a value that is "off" (does not interfere with the results), and > drive that value (e.g. 0 or false) when you want to use it as an > input. The resolution function can assert a warning (or worse) if > more than one driver value is non-off (contention should not occur), > and then it can simply return any non-off value in the received > array. I guess I didn't get it. What is 'worse than a warning'? If I get an error how can the simulation continue? > > If I understand your situation, the BFM that turns transactions into > bits on its "physical" interface is cranking out some bits whether or > not a "real transaction" is in progress. that is correct, because of the 'bit-stuffing' property of the protocol. > You could have a separate > interface for an error injection transaction that simply tells the > BFM to create specific errors while not generating bits related to > real transactions. meaning the BFM should 'listen' continuously the interface to check if errors need to occur or not. This will require a concurrent interface to the BFM which adds errors on top of the one which creates 'good transactions'. > You can also add argument(s) to your real > transaction procedures (defaulted to off) that cause the transaction > to be executed with errors injected. That is indeed yet another type of error, which acts at the level of packet format (wrong CRC, ...). I guess with the combination of the two I can expose many unwanted 'features' of the code. The main question here would be: for how long should I simulate? I guess here I'm stuck with building a coverage model (out of a non existing requirements' document!). From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.13.136 with SMTP id c8mr18010577qaa.0.1377555938156; Mon, 26 Aug 2013 15:25:38 -0700 (PDT) X-Received: by 10.49.48.17 with SMTP id h17mr1012qen.40.1377555937109; Mon, 26 Aug 2013 15:25:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!q10no1034278qai.0!news-out.google.com!c19ni621qak.0!nntp.google.com!fx3no4959148qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 26 Aug 2013 15:25:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <5996a797-6690-49d0-ad90-f22733d0ef66@googlegroups.com> <2e5d79c5-37d5-4d2e-9a9c-9a6690971e69@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94a77708-d93f-4c82-aea1-5d1c6d90ae5a@googlegroups.com> Subject: Re: abstracting the client/server protocol From: Andy Injection-Date: Mon, 26 Aug 2013 22:25:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 21 Xref: news.eternal-september.org comp.lang.vhdl:6979 Al,=20 WRT "warnings or worse", most simulators can: 1) print a message and keep going (e.g. note or warning) 2) stop (breakpoint from which you can continue, e.g. error) 3) quit (cannot continue e.g. failure) based on the severity level (NOTE, WARNING, ERROR, etc) of the assert or re= port statement. Most simulators allow changing the specified behavior for e= ach severity level as well, but that becomes a global behavior change for a= ll assertions/reports of that severity level. Also, assuming you have a package for your resolved types and their resolut= ion functions, you can use a constant in that package for the severity used= by the assertions in your resolution functions. While debugging your testb= ench, you can set the constant to WARNING or ERROR, but later on, when runn= ing regression simulations "for the record" you can change that constant to= FAILURE so that there is no possibility of continuing on from a resolution= function problem in a record run simulation. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Tue, 27 Aug 2013 11:08:03 +0300 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 27 Aug 2013 08:08:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="5732"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190vAiRC2EKlqvhFC4OPVJ98rbRavVveSs=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:5ktbK6uOdzgfwTc6N9/DDFPuUpI= Xref: news.eternal-september.org comp.lang.vhdl:6980 On 26.08.2013 15:45, valtih1978 wrote: > This immediately raises the question: how is the activity status propagated Ok, I have realized that driver is a source and active driver is the originator of signal activity. But, I still do not understand how does the activity propagate downwards. From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: concurrent signal assignment in a process Date: Tue, 27 Aug 2013 12:14:36 +0200 Lines: 71 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 8K272wYdS/Zql3EdwWutwgoFMT4IOBX1hzyOodq6HH4zQo6EMa Cancel-Lock: sha1:aQsW9erTEh/5UVjmY1F/O3aGLL0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6981 Hi everyone, I generally use the vcom to analyze and build libraries and units for presynth simulation and only after I'm happy with it I proceed with synthesis. Yesterday, though, I tried to compile the following code [1] with synplify_pro without success (while vcom happily went through): > architecture tfsm_arch of tfsm is > -- Note: No signal declarations. > begin -- tfsm_arch > > main : process (CLK, RST) is > -- control wires > subtype ctr_t is std_ulogic; > variable nrd_v : ctr_t; > variable nwr_v : ctr_t; > variable auto : boolean; > ------------------------------------------------------------------------------- > procedure update_ports is > begin -- purpose: synthesize a wire from the register to the port > nRD_o <= nrd_v when auto = true else nrd_i; -- ***Synplify Pro AE Error > nWR_o <= nwr_v when auto = true else nwr_i; > add_o <= add_v when auto = true else add_i; > > end procedure update_ports; > ------------------------------------------------------------------------------- > -- some more procedures here... > ------------------------------------------------------------------------------- > begin -- process main > case template_g is > when a_rst => template_a_rst; > when s_rst => template_s_rst; > when so_rst => template_so_rst; > when others => template_v_rst; > end case; > end process main; Synplify Pro AE (integrated in LiberoSoC) barf something like this: @E: CD242 :"/home/pol/polar_svn/firmware/obox/frontend_alb/firmware/hdl/tfsm.vhd":116:21:116:24|Expecting ; @E: CD204 :"/home/pol/polar_svn/firmware/obox/frontend_alb/firmware/hdl/tfsm.vhd":116:21:116:24|Expecting sequential statement Being the procedure defined in a process I may understand why it 'expects a sequential statement', but is this something related to synthesis only? Why vcom does not complain? It looks like I cannot have a concurrent signal assignment in a process (which makes sense since signal assignment is 'scheduled'). Moreover I'm quite confused when it comes to the various steps involved in synthesis. It seems the tool is failing during 'parsing' which is something I expected to be part of the 'analysis', therefore equivalent to the 'vcom' result. Anyway I changed the conditional signal assignment statement with a sequential one (if/then/else) and everything works fine. Still I'd appreciate if someone can enlighten me on this topic. Al [1] some of you may have recognized Mike Treseler's template. -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.66.160.36 with SMTP id xh4mr6372234pab.11.1377611207415; Tue, 27 Aug 2013 06:46:47 -0700 (PDT) X-Received: by 10.49.56.7 with SMTP id w7mr11509qep.16.1377611207154; Tue, 27 Aug 2013 06:46:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!n2no3526017pbg.1!news-out.google.com!z6ni19504pbu.0!nntp.google.com!fx3no5824734qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Aug 2013 06:46:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> Subject: Re: Active sources From: Andy Injection-Date: Tue, 27 Aug 2013 13:46:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6982 On Tuesday, August 27, 2013 3:08:03 AM UTC-5, valtih1978 wrote: > But, I still do not understand how does the activity propagate downwards. You mean downwards through a hierachy via a series of in or inout ports/map= s? Again, if you think of ports and port maps as a shorthand way to define ali= ases to signals "on the other side" of the entity interface, there is no "p= ropagation" of values involved (unless expressions are used in the port map= s). Aliases are not copies of signals that are manipulated by the simulator= to always keep the same values. They are new references to the same origin= al signal (like an access type, but not dynamically associable with differe= nt signals). There is but one signal for an entire series of mappings through a hierachy= of entity/architecture pairs (defined at the uppermost level in the port c= hain), with many references to it in different entity/architectures. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: parametric vector slices Date: Tue, 27 Aug 2013 15:56:05 +0200 Lines: 34 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net s8+Ykj3oCMZPw7QF1m+BcQOZTOYBfwQlI5nExmnP+g6epG/eRj Cancel-Lock: sha1:H0gJwrFlaic+6OIwuBlVVtmzDg4= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6983 Hi everyone, I'm not sure if the 'subject' is correctly formulated but I'll try anyway. Assume an array of bits 'a' which has N number of bits. Now assume M < N where N/M = k is an integer number. I'd like to slice a in k pieces in such a way that I can assign each slice to another array of bits with M bits. Something like this: --not tested variable a : my_array_of_bits(N-1 downto 0); type list is array (0 to k) of my_array_of_bits(M-1 downto 0); variable l : list; for i in 0 to l'range - 1 loop l(i) <= a((i+1)*M - 1 downto i*M); end loop; Is there any better way to do this? Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.66.163.6 with SMTP id ye6mr5984390pab.17.1377612577935; Tue, 27 Aug 2013 07:09:37 -0700 (PDT) X-Received: by 10.49.12.47 with SMTP id v15mr6718qeb.39.1377612577688; Tue, 27 Aug 2013 07:09:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!n2no3574928pbg.1!news-out.google.com!z6ni19504pbu.0!nntp.google.com!fx3no5826158qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Aug 2013 07:09:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: concurrent signal assignment in a process From: Andy Injection-Date: Tue, 27 Aug 2013 14:09:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6984 Al, Turn on the 2008 VHDL option in Synplify Pro. BTW, those are not "concurrent assignment statements in a process". They ar= e "conditional assignment statements" (LRM 10.5.3), which, under 2008 are a= lso allowed in sequential (process/subprogram) regions, as are selected ass= ignment statements. In a sequential statement region, these can also be var= iable assignments.=20 However, they are statements, and do NOT create a new form of conditional/s= elected expression, and are therefore not usable as, say, an initializer on= a constant/signal/variable declaration. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: concurrent signal assignment in a process Date: Tue, 27 Aug 2013 16:27:35 +0200 Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net NNgqzP8PIWd+0M5AZuIwmwND0Cp4rKgU3Xs/f8k2rtEtHE7YQ3 Cancel-Lock: sha1:t3uMySFDnweECpEESxPz/xncvX0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130620 Thunderbird/17.0.7 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6985 On 27/08/2013 16:09, Andy wrote: [] > Turn on the 2008 VHDL option in Synplify Pro. Uhm, apparently the 2008 VHDL switch is on... > > BTW, those are not "concurrent assignment statements in a process". > They are "conditional assignment statements" (LRM 10.5.3), which, > under 2008 are also allowed in sequential (process/subprogram) > regions, as are selected assignment statements. In a sequential > statement region, these can also be variable assignments. crap I mixed them: I should have said 'conditional signal assignment statement' which used to be a 'concurrent statement' (LRM IEEE1076-1993 9.5.1). > However, they are statements, and do NOT create a new form of > conditional/selected expression, and are therefore not usable as, > say, an initializer on a constant/signal/variable declaration. I'm puzzled now. Do you mean that I cannot use this statement to infer a logic which allows me to 'select' one of two constant/signal/variable and assign it to another variable/signal? (like a multiplexer) From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.66.152.164 with SMTP id uz4mr6417775pab.24.1377614499823; Tue, 27 Aug 2013 07:41:39 -0700 (PDT) X-Received: by 10.50.8.42 with SMTP id o10mr636331iga.3.1377614499516; Tue, 27 Aug 2013 07:41:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!usenet-its.stanford.edu!usenet.stanford.edu!n2no3632961pbg.1!news-out.google.com!z6ni19504pbu.0!nntp.google.com!fx3no5828276qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Aug 2013 07:41:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: parametric vector slices From: Andy Injection-Date: Tue, 27 Aug 2013 14:41:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6986 Al, For vhdl-2008 compliant tools, you can declare a type that is an unconstrained array of unconstrained arrays, so it is possible to write a "slice(input, M)" function that would return such a type. You may want a function that does the reverse too. Check your tools' documentation to see which 2008 features they support. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.66.27.42 with SMTP id q10mr5905314pag.14.1377615319621; Tue, 27 Aug 2013 07:55:19 -0700 (PDT) X-Received: by 10.49.28.97 with SMTP id a1mr762455qeh.0.1377615319320; Tue, 27 Aug 2013 07:55:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!usenet-its.stanford.edu!usenet.stanford.edu!n2no3665041pbg.1!news-out.google.com!z6ni19504pbu.0!nntp.google.com!fx3no5829055qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 Aug 2013 07:55:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: concurrent signal assignment in a process From: Andy Injection-Date: Tue, 27 Aug 2013 14:55:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6987 Al, Oops, As of June 2012 the Synplify Reference manual did not list sequential conditional/selected assignments as being a 2008 feature that is supported yet. If you want it, let them know! That's the only way they know what is important to their users. If enough of us let them know these features that we want supported, they will support them. WRT expressions, what I meant is you CANNOT do something like the following: constant foo_flag : std_logic := '1' when foo = 0 else '0'; Conditional/selected assignment statements are their own kind of statement, not a new kind of expression that can be used anywhere an expression can be used. Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Wed, 28 Aug 2013 16:24:48 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Aug 2013 13:24:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="342"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/yk8Bh5IQgQECJmoGeT5JFud4XgYWwwL8=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> Cancel-Lock: sha1:GCVL5Ik/DUulpDOt7oF29C0eUc4= Xref: news.eternal-september.org comp.lang.vhdl:6988 Again, specification specifies the activity propagation pretty concretely and without any notion of the alias. Check the LRM excerpts that what I quoted in my question. From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Thu, 29 Aug 2013 10:54:34 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Aug 2013 07:54:37 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="11685"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Ti1YqKGFw4kRs0PeISXEGfYNmRNLUsgU=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> Cancel-Lock: sha1:IwDQ/p9C7tZLUrq0MDAXGcoeZQ4= Xref: news.eternal-september.org comp.lang.vhdl:6989 Basically, my question is how does LRM specify the aliasing you are talking about. The notion of alias implies that activity is propagated up and down. However, in the spec I see only upward propagation. Port source is active if actual is active. This implies downward propagation. From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.66.172.79 with SMTP id ba15mr1903343pac.26.1377796317120; Thu, 29 Aug 2013 10:11:57 -0700 (PDT) X-Received: by 10.49.48.197 with SMTP id o5mr118943qen.31.1377796316870; Thu, 29 Aug 2013 10:11:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!n2no9100676pbg.1!news-out.google.com!z6ni22734pbu.0!nntp.google.com!fx3no6097561qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Aug 2013 10:11:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> Subject: Re: Active sources From: Andy Injection-Date: Thu, 29 Aug 2013 17:11:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:6990 The LRM is silent WRT ports/maps being aliases. It is just my observation o= f the overall effects of ports and port maps (specifically that there are n= o delta-delays associated with ports/maps, only with associated expressions= .) If you don't like my observation, you are free to ignore it, and substit= ute your own, or anyone else's, so long as it satisfies the LRM definitions= of ports and port maps. Propagation is a loosely defined term. I believe you are referring to how a= driven value on a submodule's OUT port is made available outside that modu= le, or how an instantiating module's driven value on a signal associated wi= th a submodule's IN port is made available inside the submodule. That is explained by the fact that only one signal exists in either of thos= e cases. The compiler controls, by scope, map(s) and mode(s), where that si= gnal's value can be legally read or driven. With only one signal, what is t= here to propagate? Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Thu, 29 Aug 2013 22:40:25 +0300 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Aug 2013 19:40:29 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="3427"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19VC+1EjRy77OAfrp4yOZsnKWywltGHiTM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> Cancel-Lock: sha1:U7fLg4Dkz6lcIGiGhbBLcNLte2U= Xref: news.eternal-september.org comp.lang.vhdl:6991 On 29.08.2013 20:11, Andy wrote: > Propagation is a loosely defined term. I believe you are referring to how a driven value on a submodule's OUT port is made available outside that module, or how an instantiating module's driven value on a signal associated with a submodule's IN port is made available inside the submodule. I believe that I am talking about the signal activity propagation, that I have quoted " signal is active during simulation cycle - If one of its sources is active or - the signal is named in the formal part of an association element in a port association list and the the corresponding actual is active. " and hyperlinked, http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_12.HTM, in the very beginning of my question! From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.124.131 with SMTP id u3mr7457801qar.5.1377828351986; Thu, 29 Aug 2013 19:05:51 -0700 (PDT) X-Received: by 10.49.94.39 with SMTP id cz7mr1216qeb.26.1377828351907; Thu, 29 Aug 2013 19:05:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!fx3no6133474qab.0!news-out.google.com!he10ni3964qab.0!nntp.google.com!fx3no6133469qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Aug 2013 19:05:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.113.180.209; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 99.113.180.209 References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7e33d036-d57c-4992-bee6-148e18bb1f0f@googlegroups.com> Subject: Re: Active sources From: Andy Injection-Date: Fri, 30 Aug 2013 02:05:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: news.eternal-september.org comp.lang.vhdl:6992 See notes 2 and 3 of 12.6.2 Andy From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Fri, 30 Aug 2013 12:29:32 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> <7e33d036-d57c-4992-bee6-148e18bb1f0f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Aug 2013 09:29:37 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="23697"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ncKmp/F80DvSH7RvRIcX3KQlVwIo8Nfo=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <7e33d036-d57c-4992-bee6-148e18bb1f0f@googlegroups.com> Cancel-Lock: sha1:8ZHIuG2CJiXbpBBVLwn4x4O1qgU= Xref: news.eternal-september.org comp.lang.vhdl:6993 Yes, that's it. I just do not understand how do they follow from the definition. I believe that notes just repeat the points that are hard-to-spot, yet present in the definition. I do not see how the upward activity propagation follows from the downward. From newsfish@newsfish Tue Dec 29 16:43:08 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: data type choice Date: Fri, 30 Aug 2013 16:19:12 +0200 Lines: 56 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net hP+VOQ7R8u+DuGDihcIDwATHkDYHG6CMYIMVA4/kRwt+0v5IK/ Cancel-Lock: sha1:ulggEDLwzAhO+eKlDm0eOYcQbvU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6994 Hi everyone, I'm trying to define my own set of types in order to have a more readable code and try to represent my data structures at a higher level. This code is used for testbench only and I'm using it to define my packets to be transmitted on my serial link. Eventually somewhere there is a procedure handling these data types and 'sending' a std_logic signal to a DUT. constant WORD_LENGTH : natural := 16; constant MAX_BUF_LEN : natural := 1024; -- data word over the link interface are 16 bit wide. subtype data_word_t is bit_vector (WORD_LENGTH - 1 downto 0); type buff_t is array (0 to MAX_BUF_LEN - 1) of data_word_t; type data_buffer_t is record len : natural; -- length of the data buf : buff_t; -- data buffer end record; the intent of this gymnastic is to deal with bits and non negative integers for packet lengths, but I'm facing lots of troubles when I start to manipulate these datatypes because of conversion. Since the header of my packets include the length I thought that simply doing: variable data_buffer : data_buffer_t; variable data_word : data_word_t; data_word := some_conversion_function(data_buffer.len); would have been enough, but it seems to me I'm too stupid to find the right combination of conversions. Moreover I start to think that maybe my original choice of types is not optimal and some people around here can direct me to a better choice of types. Should I build a set of functions that allow me to manipulate these types? Any suggestion is welcome. Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:08 2015 X-Received: by 10.224.4.138 with SMTP id 10mr10789057qar.8.1377881950782; Fri, 30 Aug 2013 09:59:10 -0700 (PDT) X-Received: by 10.49.24.161 with SMTP id v1mr51068qef.37.1377881950741; Fri, 30 Aug 2013 09:59:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder01.blueworldhosting.com!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!fx3no6209170qab.0!news-out.google.com!he10ni4101qab.0!nntp.google.com!q10no2190543qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Aug 2013 09:59:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> Subject: Re: data type choice From: Jim Lewis Injection-Date: Fri, 30 Aug 2013 16:59:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2012 Xref: news.eternal-september.org comp.lang.vhdl:6995 Hi Al, If I were not using std_logic_vector, I would be using integer. I am planning on migrating toward using integers in my testbenches. Especially if we can get larger than 32 bit integers in the next revision of the language. OSVVM likers integers. If you continue using bit_vector, math operations are in numeric_bit_unsigned and numeric_bit. Conversions to between std_logic family are in std_logic_1164: function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT; function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR; function To_StdULogic (b : BIT) return STD_ULOGIC; function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR; In my testbenches, I like communicating through a single record. Bit_vector does not work with this approach since it does not have a resolution function. Of course, you could write one. I did this for integer, time, and real. Jim From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Sat, 31 Aug 2013 12:03:07 +0300 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 31 Aug 2013 09:03:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="1216"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18B2QPbP/igZ7t5FyZO0M42LMbbgnUobFg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:kBxS4uzI3xmKAVakl8fWTX57jzM= Xref: news.eternal-september.org comp.lang.vhdl:6996 > =4= BTW, is slice a signal? It must be, since signal is an object and http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_4.HTM#4.3.2.2 says A named object one of the following: -- AN OBJECT DECLARED BY OBJECT DECLARATION, -- Formal parts and etc In addition, the following are objects, but are not named entities: -- implicit signals -- AN ELEMENT OR SLICE OF ANOTHER OBJECT -- targets of access objects From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Active sources Date: Sat, 31 Aug 2013 12:15:54 +0300 Organization: A noiseless patient Spider Lines: 5 Message-ID: References: <40a4d132-c7b4-4080-ba0e-0eab461cde7a@googlegroups.com> <5786b550-3920-4e49-a56d-dbda37106223@googlegroups.com> <7e33d036-d57c-4992-bee6-148e18bb1f0f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 31 Aug 2013 09:15:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4512"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1881A5Gi5Kv/FsLkCyAcFgfCasRd0KLbI4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <7e33d036-d57c-4992-bee6-148e18bb1f0f@googlegroups.com> Cancel-Lock: sha1:shfs04gRWGn85H0FCJtyyXVG6ZM= Xref: news.eternal-september.org comp.lang.vhdl:6997 Ok, it seems that ports are a kind of source. Therefore, activity will spread both upwards and downwards. But, then I do not understand why did they stipulate the active -> formal activity propagation right in the definition if it follows from the notion of source? Why not just pick this in the notes as it is done with formal -> actual output ports? From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: data type choice Date: Mon, 02 Sep 2013 12:40:52 +0200 Lines: 42 Message-ID: References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net wu5qEjjbMm57SFUImDjnrggyxyYlFsLUB0w50zmBVQ4KhGVGf8 Cancel-Lock: sha1:JxtKnAbLoXktDYHju5sn79R10I8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:6998 On 30/08/2013 18:59, Jim Lewis wrote: > Hi Al, If I were not using std_logic_vector, I would be using > integer. I am planning on migrating toward using integers in my > testbenches. Especially if we can get larger than 32 bit integers in > the next revision of the language. OSVVM likers integers. unfortunately I cannot get rid of the slv since this is how the DUT interface is defined. It seems to me that slv is a common choice with RTL. I may understand why OSVVM likes integers and I would like to profit of that as well, but sooner or later you need to face with the conversion to slv and this is where I hoped for the bv to be more friendly. > > If you continue using bit_vector, math operations are in numeric_bit_unsigned and numeric_bit. Conversions to between std_logic family are in std_logic_1164: > function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT; > function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR; > > function To_StdULogic (b : BIT) return STD_ULOGIC; > function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR; > thanks for the hint. My choice for bv is that it seems to me well representing bit fields in the protocol. What I'm doing is breaking down the packet format to each individual field, so I can randomly set each field and see how this effects my DUT. How do you eventually convert the integers into your '16bit word header' for example? > In my testbenches, I like communicating through a single record. I have not yet moved to the single record transaction and therefore keep using two (one to the server and one from the server). As of now I do not have a case for that need. > Bit_vector does not work with this approach since it does not have a > resolution function. Of course, you could write one. I did this for > integer, time, and real. Writing the resolution function shouldn't be complex. I'll postpone this effort though since I'm not yet convinced I need it :-) From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.66.161.100 with SMTP id xr4mr8120269pab.3.1378134944185; Mon, 02 Sep 2013 08:15:44 -0700 (PDT) X-Received: by 10.49.24.132 with SMTP id u4mr2172qef.17.1378134944083; Mon, 02 Sep 2013 08:15:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder02.blueworldhosting.com!news.glorb.com!n2no16258280pbg.1!news-out.google.com!rn2ni53289pbc.1!nntp.google.com!n2no16258273pbg.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Sep 2013 08:15:43 -0700 (PDT) In-Reply-To: <20130823102734.2d3b5334@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.152.150.0; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 82.152.150.0 References: <20130822165749.7c3649a4@rg.highlandtechnology.com> <72b28675-211c-4d94-818f-928bd517ac3a@googlegroups.com> <20130823102734.2d3b5334@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4769ff32-c203-437b-b564-9ffa60066798@googlegroups.com> Subject: Re: Possible Quartus Bug From: Tricky Injection-Date: Mon, 02 Sep 2013 15:15:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:6999 > Thanks, it does. Quartus's VHDL-2008 support is lacking in a bunch of > ways. There's no support for *_vector, no ?? operator, no automatic ?? > when using std_logic in an if statement, no unary logic reduction > operators, the list goes on. Basically, they got the fixed point > package working and called it a day. > I think its worse than that - David Bishop got it working by creating a 1993 compatible version of the library. The Quartus 2008 VHDL "support" is a joke. From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.236.209.103 with SMTP id r67mr10883269yho.35.1378200446706; Tue, 03 Sep 2013 02:27:26 -0700 (PDT) X-Received: by 10.49.3.134 with SMTP id c6mr377999qec.0.1378200446516; Tue, 03 Sep 2013 02:27:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!209.85.216.88.MISMATCH!j7no122568qai.0!news-out.google.com!p7ni567qas.0!nntp.google.com!j7no122565qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Sep 2013 02:27:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.105.3.246; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 213.105.3.246 References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> Subject: Re: data type choice From: Tricky Injection-Date: Tue, 03 Sep 2013 09:27:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7000 Its not quite clear to me - is this data_buffer_t a single packet, or does = it contain multiple packets?=20 If its the latter, wouldnt it be better to make a single packet type, and t= hen have some sort of controller to convert the packet into your serial dat= a stream, rather than have a big fixed bus in your testbench, that isnt eas= ily seperable into packets (if you wanted to inspect them in modelsim). What I have done before in a homemade BFM for PCIe over an avalon streaming= bus was to create a linked list of packets (acting as my event queue) hand= led by a protected type, and a wraparound entity controlled the data flow (= with random wait times between packets to try and simulate some form of wor= se case or reality. Meant I could pump thounsands of PCIe packets into my c= ontroller, and from the top level all I needed were procedures like send_rd= _req(addr) send_wr_req(addr, data), and never worry about overflowing any c= ontrollers in the testbench (only in the design). From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: data type choice Date: Tue, 03 Sep 2013 12:01:28 +0200 Lines: 62 Message-ID: References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net os/O7WzXjbMdH0k5UvwcpQRjpEw0kjryGz2lIXoRQ6cmoKkzuW Cancel-Lock: sha1:OrYZJ8awZsJEJBYXQkZt2sPSHk8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7001 On 03/09/2013 11:27, Tricky wrote: > Its not quite clear to me - is this data_buffer_t a single packet, or > does it contain multiple packets? data_buffer_t is a single packet. I intend to break down the fields more clearly but for the time being you can assume that the packet is just a sequence of data_word_t types. The 'controller', as you call it, does the job of converting the sequence into the appropriate bits (I call it server). > If its the latter, wouldnt it be better to make a single packet type, > and then have some sort of controller to convert the packet into your > serial data stream, rather than have a big fixed bus in your > testbench, that isnt easily seperable into packets (if you wanted to > inspect them in modelsim). this is indeed my intent. The client simply sends a random sequence of packets, varying randomly the various fields of the packet. Since OSVVM allows you to do so very easily I intended to profit of this. The fact is that in the stream of serial data out I need to 'merge' information coming from data_buffer_t elements and combine them in a sequence of bits on a std_logic port. This 'merging' is now very awkward due to the casting (from/to integers, bit and std_logic). > What I have done before in a homemade BFM for PCIe over an avalon > streaming bus was to create a linked list of packets (acting as my > event queue) handled by a protected type, and a wraparound entity > controlled the data flow (with random wait times between packets to > try and simulate some form of worse case or reality. Meant I could > pump thounsands of PCIe packets into my controller, and from the top > level all I needed were procedures like send_rd_req(addr) > send_wr_req(addr, data), and never worry about overflowing any > controllers in the testbench (only in the design). My issue is not 'overflowing' the controller on the testbench. I simply need to stick to a selection of datatypes which are coherent with the number of conversion to and from std_logic. If I use integers *and* bits than I'm kind of stuck when I want to combine them, if I use only integers than it is not quite readable when you need to deal with words which have various fields, if I use only bits than a length field may appear not so readable (101011110 instead of 350, with unsigned representation). Assume you have a data word which is split in some fields like the following: - add(15 downto 12) - crc(11) - ext(10) - len(9 downto 0) a second word of length comes if ext is set. A crc flag indicates the presence of crc at the end of the message. If all the fields are integers (better be natural in this case) then my word to be sent will look like this: data_word = (add * 2**12) + (crc * 2**11) + (ext * 2**10) + len which I find rather ugly. And again at a certain point I should convert the data_word integer to a std_logic (passing through an unsigned). From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.224.137.68 with SMTP id v4mr100649qat.1.1378207953706; Tue, 03 Sep 2013 04:32:33 -0700 (PDT) X-Received: by 10.49.25.83 with SMTP id a19mr1150374qeg.1.1378207953683; Tue, 03 Sep 2013 04:32:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!j7no129586qai.0!news-out.google.com!p7ni567qas.0!nntp.google.com!j7no129581qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Sep 2013 04:32:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <009c0a98-9519-4b47-a542-cccf4b0f3e13@googlegroups.com> Subject: Re: data type choice From: KJ Injection-Date: Tue, 03 Sep 2013 11:32:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 47 Xref: news.eternal-september.org comp.lang.vhdl:7002 On Tuesday, September 3, 2013 6:01:28 AM UTC-4, alb wrote: > Assume you have a data word which > is split in some fields like the following: > > - add(15 downto 12) > - crc(11) > - ext(10) > - len(9 downto 0) Then presumably you would have defined a record like this... type t_packet is record add: std_ulogic_vector(15 downto 12); crc: std_ulogic_vector(11 downto 11); ext: std_ulogic_vector(10 downto 10); len: std_ulogic_vector(9 downto 0); end record; Then I would define functions to convert between records and std_ulogic_vectors like this... function to_std_ulogic_vector(L: t_packet) return std_ulogic_vector is variable RetVal: std_ulogic_vector(15 downto 0); begin RetVal(L.add'range) := L.add; RetVal(L.crc'range) := L.crc; RetVal(L.ext'range) := L.ext; RetVal(L.len'range) := L.len; return(RetVal); end function to_std_ulogic_vector; function from_std_ulogic_vector(L: std_ulogic_vector) return t_packet; -- Left as an exercise for the reader, but similar in style with to_std_ulogic_vector > > a second word of length comes if ext is set. A crc flag indicates the > presence of crc at the end of the message. If all the fields are > integers (better be natural in this case) then my word to be sent will > look like this: > > data_word = (add * 2**12) + (crc * 2**11) + (ext * 2**10) + len > > which I find rather ugly. And again at a certain point I should convert > the data_word integer to a std_logic (passing through an unsigned). But data_word <= to_std_ulogic_vector(L); looks much better. If you want to convert it to integer than wrap to_integer(unsigned()) around it. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: data type choice Date: Tue, 03 Sep 2013 14:33:16 +0200 Lines: 62 Message-ID: References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> <009c0a98-9519-4b47-a542-cccf4b0f3e13@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net SKEeEQ2s8MKUWikid0Y59A7snUjIcyWDYJAeT8FeluYBvBl6B4 Cancel-Lock: sha1:gSAeY1XMqfLUV1mJAmgu9Njj6eo= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <009c0a98-9519-4b47-a542-cccf4b0f3e13@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7003 Hi KJ, On 03/09/2013 13:32, KJ wrote: > On Tuesday, September 3, 2013 6:01:28 AM UTC-4, alb wrote: >> Assume you have a data word which >> is split in some fields like the following: >> >> - add(15 downto 12) >> - crc(11) >> - ext(10) >> - len(9 downto 0) > > Then presumably you would have defined a record like this... > > type t_packet is record > add: std_ulogic_vector(15 downto 12); > crc: std_ulogic_vector(11 downto 11); > ext: std_ulogic_vector(10 downto 10); > len: std_ulogic_vector(9 downto 0); > end record; That is more or less where I was aiming to, but I would have preferred to define the len element as an integer (or even better a natural) instead. At that point I believe that in to_std_ulogic_vector I could change this: - RetVal(L.len'range) := L.len; into something along these lines: - RetVal(log2(L.len'length) downto 0) := to_unsigned(L.len, ???); uhm... I'm again lost! :-) Actually your example triggers another question: why std_ulogic_vector and not a bit_vector? At the packet definition level I do not really need the 'Z', 'W', 'L'... values of the type. I may blindly adopt the std_ulogic (and why not std_logic instead?), I just would like to know what is important and what might be neglected when deciding what type of data we choose. > Then I would define functions to convert between records and std_ulogic_vectors like this... > function to_std_ulogic_vector(L: t_packet) return std_ulogic_vector is > variable RetVal: std_ulogic_vector(15 downto 0); > begin > RetVal(L.add'range) := L.add; > RetVal(L.crc'range) := L.crc; > RetVal(L.ext'range) := L.ext; > RetVal(L.len'range) := L.len; > return(RetVal); > end function to_std_ulogic_vector; > > function from_std_ulogic_vector(L: std_ulogic_vector) return t_packet; > -- Left as an exercise for the reader, but similar in style with to_std_ulogic_vector I think I got your message, by writing a to/from pair of functions which hides the nuances of the type casting and formatting I can simply manipulate my records. BTW I did not know the 'range attribute would return (15 downto 12) for L.add, I was convinced it would simply return a generic (3 downto 0)...thanks for the hint. From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.224.223.198 with SMTP id il6mr208143qab.7.1378252897357; Tue, 03 Sep 2013 17:01:37 -0700 (PDT) X-Received: by 10.49.48.17 with SMTP id h17mr331qen.40.1378252897302; Tue, 03 Sep 2013 17:01:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!q10no2562068qai.0!news-out.google.com!p7ni567qas.0!nntp.google.com!j7no190505qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Sep 2013 17:01:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.191.72; posting-account=rnO7mgoAAADaZXkRcWozSS6TqEwZ6fz- NNTP-Posting-Host: 187.36.191.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> Subject: Process to combinational circuits? From: Christiano Injection-Date: Wed, 04 Sep 2013 00:01:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7004 I see many codes that use VHDL process in the combinational. Why is this so common? Why not use constructs suitable for combinational circuits instead of using process as often? Everything that can be done with the process can be done without the process when it comes to combinational, is not it? So what is the justification? From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.224.52.6 with SMTP id f6mr1934011qag.2.1378283184817; Wed, 04 Sep 2013 01:26:24 -0700 (PDT) X-Received: by 10.49.14.170 with SMTP id q10mr61291qec.5.1378283184794; Wed, 04 Sep 2013 01:26:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!j7no231359qai.0!news-out.google.com!p7ni567qas.0!nntp.google.com!j7no231357qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Sep 2013 01:26:24 -0700 (PDT) In-Reply-To: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7018150e-b9bc-4b6f-bb7e-440cb5e59465@googlegroups.com> Subject: Re: Process to combinational circuits? From: Thomas Stanka Injection-Date: Wed, 04 Sep 2013 08:26:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7005 Am Mittwoch, 4. September 2013 02:01:37 UTC+2 schrieb Christiano: > Everything that can be done with the process can be done without the =20 > process when it comes to combinational, is not it? So what is the=20 > justification? I use seldom combinatorical process for RTL, but sometimes the code is easi= er written, maintained or read when using combinatorial process instead of = concurrent statements. Especially, if you use intermediate variables for ty= pe conversions that are used on several lines within a process you can ease= code with process instead of inlining these type conversions at each occur= ency in a concurrent statement. And often I like to increase readablitiy by= using nested if, which is impossible in concurrent statements. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Process to combinational circuits? Date: Wed, 04 Sep 2013 15:11:22 +0200 Lines: 42 Message-ID: References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net FDexsCm78IaGIQ/Q8+jnsQsKc7XsCyyT0OnAUfDwwW1u6MnOB7 Cancel-Lock: sha1:nYtGKqzaaYaXpIUt9CF/8fS7Lf0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7006 On 04/09/2013 02:01, Christiano wrote: > I see many codes that use VHDL process in the combinational. Why is this > so common? Why not use constructs suitable for combinational circuits > instead of using process as often? You may use one single process for the entire entity or have multiple processes sharing signals with a sparse collection of concurrent statements or processes to infer combinatorial logic. There's no one single way to describe your hardware, even though some of them will reduce the amount of time spent in debugging. > > Everything that can be done with the process can be done without the > process when it comes to combinational, is not it? So what is the > justification? When it comes to hardware *description* you are not only describing it to an analysis tool but also to a human being, meaning that the more readable and accurate is your description the easier would be for people within your team (or for yourself within few weeks from the coding) to understand your code and possibly fix it! Synthesis tools are not so picky as human beings and they have no particular reluctance to accept an insane combination of styles, but a human being can potentially get lost in your code if the style is not consistent. Depending on your working environment it is possible that there are guidelines with naming conventions, structure, preferred syntax forms... AFAIK there's no one particular style which is superior to others, but a consistent style may help you (and your teammates) to spot problems sooner. Of course you might have equally been unlucky and confronted only with people who did not know about the possibility to infer combinatorial logic with concurrent signal assignment statements. IMHO every effort spent in making the code more readable is good, every effort spent in reducing the amount of code is good, nearly every effort spent in optimizing your code is wasted unless proven necessary with clear metrics and benchmarks. Al From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.66.160.36 with SMTP id xh4mr1079199pab.11.1378305461646; Wed, 04 Sep 2013 07:37:41 -0700 (PDT) X-Received: by 10.49.99.37 with SMTP id en5mr121260qeb.8.1378305461208; Wed, 04 Sep 2013 07:37:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!y3no1024633pbx.0!news-out.google.com!z6ni33955pbu.0!nntp.google.com!q10no2625691qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Sep 2013 07:37:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.168.74.141; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 81.168.74.141 References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39631b0e-c190-475f-b72c-c1e731f5faf9@googlegroups.com> Subject: Re: Process to combinational circuits? From: Tricky Injection-Date: Wed, 04 Sep 2013 14:37:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7007 To expand on Al's point, I thought I would just give 3 examples of a mux. Which one is "best" is really up to the designer, but it is consistancy and readability that are important: op <= ip0 when sel = "00" else ip1 when sel = "01" else ip2 when sel = "10" else ip3 when sel = "11" else 'X'; ------- mux : with sel select op <= ip0 when "00", ip1 when "01", ip2 when "10", ip3 when "11", 'X' when others; ------- mux_proc : process(sel, ip0, ip1, ip2, ip3) begin case sel is when "00" => op <= ip0; when "01" => op <= ip1; when "10" => op <= ip2; report "Case 2 selected for output" severity NOTE; when "11" => op <= ip3; when others => op <= 'X'; end case; end process; Notice how the process version also allows for extra debug informaton, or any other code that fits in with that logic (maybe you want to combine 3 muxes into 1 process) From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.180.91.17 with SMTP id ca17mr1420815wib.3.1378321729978; Wed, 04 Sep 2013 12:08:49 -0700 (PDT) X-Received: by 10.50.109.165 with SMTP id ht5mr270351igb.11.1378321729456; Wed, 04 Sep 2013 12:08:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!newsfeed.fsmpi.rwth-aachen.de!proxad.net!feeder1-2.proxad.net!209.85.212.215.MISMATCH!g3no20163604wic.0!news-out.google.com!v3ni6602wiv.1!nntp.google.com!g3no20163598wic.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Sep 2013 12:08:49 -0700 (PDT) In-Reply-To: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> Subject: Re: Process to combinational circuits? From: Jim Lewis Injection-Date: Wed, 04 Sep 2013 19:08:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7008 > Everything that can be done with the process can be done without the=20 > process when it comes to combinational, is not it? So what is the=20 > justification? Yes. For small logic, I use concurrent assignments. For larger more compl= ex code, I use a process. =20 Furthermore, the following is a flip-flop. We just need to make sure to fi= le bug reports against synthesis vendors who do not support it: AReg <=3D A when rising_edge(Clk) ;=20 There are lots of coding preferences out there. Some say use only a single= clocked process per architecture. My preference is piecewise using smalle= r pieces of code. However, the only thing that really matters is readable = code that gives us insight into the hardware being created. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer03.iad.highwinds-media.com!feed-me.highwinds-media.com!peer02.fr7!news.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx09.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Process to combinational circuits? References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> In-Reply-To: <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130904-0, 04/09/2013), Outbound message X-Antivirus-Status: Clean Lines: 19 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1378325285 86.29.12.221 (Wed, 04 Sep 2013 20:08:05 UTC) NNTP-Posting-Date: Wed, 04 Sep 2013 20:08:05 UTC Organization: virginmedia.com Date: Wed, 04 Sep 2013 21:08:04 +0100 X-Received-Bytes: 1991 Xref: news.eternal-september.org comp.lang.vhdl:7009 On 04/09/2013 20:08, Jim Lewis wrote: >> Everything that can be done with the process can be done without the >> process when it comes to combinational, is not it? So what is the >> justification? > Yes. For small logic, I use concurrent assignments. For larger more complex code, I use a process. > > Furthermore, the following is a flip-flop. We just need to make sure to file bug reports against synthesis vendors who do not support it: > AReg <= A when rising_edge(Clk) ; Just checked Mentor's Precision, seems to work fine, Hans www.ht-lab.com > > There are lots of coding preferences out there. Some say use only a single clocked process per architecture. My preference is piecewise using smaller pieces of code. However, the only thing that really matters is readable code that gives us insight into the hardware being created. > From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx04.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Process to combinational circuits? References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130904-0, 04/09/2013), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: <6XMVt.36976$Wl2.14623@fx04.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1378327362 86.29.12.221 (Wed, 04 Sep 2013 20:42:42 UTC) NNTP-Posting-Date: Wed, 04 Sep 2013 20:42:42 UTC Organization: virginmedia.com Date: Wed, 04 Sep 2013 21:42:40 +0100 X-Received-Bytes: 2144 Xref: news.eternal-september.org comp.lang.vhdl:7010 On 04/09/2013 21:08, HT-Lab wrote: > On 04/09/2013 20:08, Jim Lewis wrote: >>> Everything that can be done with the process can be done without the >>> process when it comes to combinational, is not it? So what is the >>> justification? >> Yes. For small logic, I use concurrent assignments. For larger more >> complex code, I use a process. >> >> Furthermore, the following is a flip-flop. We just need to make sure >> to file bug reports against synthesis vendors who do not support it: >> AReg <= A when rising_edge(Clk) ; > > Just checked Mentor's Precision, seems to work fine, > > Hans > www.ht-lab.com I just checked ISE14.4 which is happy as well, I like this constructs as it is short and sweet ;-) Thanks, Hans www.ht-lab.com > > >> >> There are lots of coding preferences out there. Some say use only a >> single clocked process per architecture. My preference is piecewise >> using smaller pieces of code. However, the only thing that really >> matters is readable code that gives us insight into the hardware being >> created. >> > From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.66.168.198 with SMTP id zy6mr26793pab.46.1378381470585; Thu, 05 Sep 2013 04:44:30 -0700 (PDT) X-Received: by 10.49.83.199 with SMTP id s7mr40649qey.11.1378381470360; Thu, 05 Sep 2013 04:44:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!n2no22481203pbg.1!news-out.google.com!z6ni33820pbu.0!nntp.google.com!j7no295448qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Sep 2013 04:44:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <3d76aac8-b478-4696-867f-a52d76b46225@googlegroups.com> <418899f7-09c7-439e-a821-26b9fbb3a9f6@googlegroups.com> <009c0a98-9519-4b47-a542-cccf4b0f3e13@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9c9c3e2f-6933-493a-af4f-97b8ef1421b7@googlegroups.com> Subject: Re: data type choice From: KJ Injection-Date: Thu, 05 Sep 2013 11:44:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7011 On Tuesday, September 3, 2013 8:33:16 AM UTC-4, alb wrote: > On 03/09/2013 13:32, KJ wrote: > > On Tuesday, September 3, 2013 6:01:28 AM UTC-4, alb wrote: > > Then presumably you would have defined a record like this... > > > > type t_packet is record > > add: std_ulogic_vector(15 downto 12); > > crc: std_ulogic_vector(11 downto 11); > > ext: std_ulogic_vector(10 downto 10); > > len: std_ulogic_vector(9 downto 0); > > end record; > > > That is more or less where I was aiming to, but I would have preferred > to define the len element as an integer (or even better a natural) instead. > At that point I believe that in to_std_ulogic_vector I could change this: > > - RetVal(L.len'range) := L.len; > > into something along these lines: > > - RetVal(log2(L.len'length) downto 0) := to_unsigned(L.len, ???); > > uhm... I'm again lost! :-) > While you can put other data types in, one of the whole points of this is to come up with a generic type that can be passsed through any conduit. In this case, the generic type is 'std_ulogic_vector'. The 'conduit' is anything that you want that is generic in nature but you need for your application. A couple examples would be memory or a fifo or even an interconnect interface. You don't need to write the code for a memory to store your t_packets when you already have one that is debugged and works for std_logic_vector or std_ulogic_vector. All you have to do to reuse that working component is convert to a vector. If you put those to/from vector conversion functions right at the input/output of that conduit you would typically not need to worry very often about just which bit in the memory is used to represent a particular field. Even something simple like 'ext' which you have as a one bit field. Normally, one would think to first use 'std_logic/std_ulogic' rather than a one bit wide vector for this field. However, try writing the to/from functions where you change 'ext' to something else and you'll find yourself having some trouble expressing the proper bit position. You can do it, but it won't be as clean as what I've shown. By making it a vector and putting that right in the record you've documented it precisely and portably. The only manual check you have here is that you don't double up and assign the same bit to multiple fields. A big plus is that the to/from conversion functions get written once and would be put into the same package as the record so when the bits in that record get packed differently you're editing one file. No edits are needed when simply changing the bit definitions, only if you add/remove fields. > Actually your example triggers another question: why std_ulogic_vector > and not a bit_vector? At the packet definition level I do not really > need the 'Z', 'W', 'L'... values of the type. I like std_ulogic because of the metavalues. You never know where you're going to reuse something and debugging why some signal is unknown will almost always be fixing a design error. Using bit_vector you can fool yourself into thinking that something is designed correctly when you're actually dependent on the simulator's initialization of that bit_vector which may or may not agree with what the hardware is actually doing. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.224.137.68 with SMTP id v4mr3974337qat.1.1378478447609; Fri, 06 Sep 2013 07:40:47 -0700 (PDT) X-Received: by 10.49.129.65 with SMTP id nu1mr5016qeb.41.1378478447576; Fri, 06 Sep 2013 07:40:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!j7no383319qai.0!news-out.google.com!p7ni1016qas.0!nntp.google.com!j7no383313qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Sep 2013 07:40:47 -0700 (PDT) In-Reply-To: <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> <1cc05599-5aeb-49c2-808f-5619b8a62f2a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Process to combinational circuits? From: Andy Injection-Date: Fri, 06 Sep 2013 14:40:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7012 Here are my thoughts on concurrent vs sequential descriptions... Humans are sequential thinkers. We understand sequential instructions best.= Imagine trying to bake a cake, following a recipe written in concurrent st= atements that are written in an arbitrary order.=20 Furthermore, the synthesis tool is perfectly capable of inferring concurren= cy from a sequential description where applicable. That being said, complexity often dictates breaking down the description of= a complex behavior into multiple concurrent islands of sequential behavior= . This is sometimes useful to clearly indicate independence of behavior (no= matter what that process over there is doing, this process here is doing t= his...) So, here are some loose rules I try to follow: Avoid concurrent assignments that depend on each other, or if necessary, st= ate the assignments in order of their dependency (in to out, top to bottom)= . If two or more signals are controlled by the same set of inputs, use a proc= ess to make that joint relationship (e.g. the same case statement) more cle= ar. Concurrent assignments can only affect one signal unless you use aggreg= ate data types and functions or a concurrent procedure call, which, if you = are not going to reuse it, is a waste of time and code bulk. Anytime combinatorial logic is described in the same architecture as the re= gister it drives, it should be described in the process that assigns the re= gister. Since my preference is to have all outputs from an entity registere= d, I do not often have combinatorial logic that does not drive a register i= n the same architecture. Cominatorial logic in a clocked process can be described as: 1) an expression which is assigned to the register,=20 2) as a variable written before being assigned to the register,=20 3) as a function in an expression being assinged to the register 4) as a procedure with an output variable #3 & #4 are useful when the same combinatorial function feeds register sign= als or variables in separate clocked processes (since the subprogram can be= re-used.) If you are relying on code coverage to help define your verification scope/= effort, beware that combinatorial processes and concurrent assignments ofte= n execute more than once before their value is actually used on the next cl= ock cycle. This can cause lots of false-positive code coverage hits. Andy From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: return the (value of) assignment Date: Fri, 06 Sep 2013 18:55:06 +0300 Organization: A noiseless patient Spider Lines: 34 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 6 Sep 2013 15:55:07 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4251"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18px1QOO1HA9xoxxqx8lwTwuTtMPTgpPS0=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 Cancel-Lock: sha1:61xCKDgwdTgJpPgKB+G7HKQWnyo= Xref: news.eternal-september.org comp.lang.vhdl:7013 Here is a funny code that I have Modelsimed process function COMPUTE return boolean is constant STR: string := "abc"; begin -- Error1: Target of signal assignment -- is not a signal. --STR <= STR; -- Error2: Constant "STR" cannot be target of -- variable assignment statement. --STR := STR; -- Return assignment is OK! return STR <= "xyz"; end function; -- Error3: Type error resolving function call -- "COMPUTE" as type std.STANDARD.STRING. --constant STR: string := COMPUTE; constant B2:boolean := COMPUTE; begin report "Computed b2 = " & boolean'image(B2); wait; end process; I am getting "Computed b2 = true" in the output despite I do not see anywhere how the assignment in the end of COMPUTE function evaluates to a boolean. A stand-alone assignment would violate checks marked with error1 and error2. From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.224.137.68 with SMTP id v4mr4571464qat.1.1378486953012; Fri, 06 Sep 2013 10:02:33 -0700 (PDT) X-Received: by 10.49.27.138 with SMTP id t10mr49806qeg.33.1378486952975; Fri, 06 Sep 2013 10:02:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!j7no422477qai.0!news-out.google.com!p7ni1134qas.0!nntp.google.com!j7no422472qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Sep 2013 10:02:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1565e7c9-53e7-4f76-befd-9430c0efa317@googlegroups.com> Subject: Re: return the (value of) assignment From: Andy Injection-Date: Fri, 06 Sep 2013 17:02:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7014 There is no assignment statement in your (uncommented) example code. The statement here is "return " and the expression returns true if STR is less than or equal to "xyz". VHDL defines the <= operator for l,r operands of the same type. The evaluation is based on the size of the arrays. VHDL operators can be overloaded, to implement more complex operations, such as is done in numeric_std for function "<=" (unsigned, unsigned) return boolean; Which evaluates the contents of the arrays to determine the result. A less ambiguous example would have been: return STR := "xyz"; Since ":=" is not also a vhdl operator. Andy From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed-00.mathworks.com!news.mathworks.com!not-for-mail From: Tim McBrayer Newsgroups: comp.lang.vhdl Subject: Re: return the (value of) assignment Date: Fri, 06 Sep 2013 13:04:56 -0400 Organization: The MathWorks, Inc. Lines: 43 Message-ID: References: NNTP-Posting-Host: tmcbraye-deb6-64.dhcp.mathworks.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: newscl01ah.mathworks.com 1378487096 22016 172.28.219.131 (6 Sep 2013 17:04:56 GMT) X-Complaints-To: news@mathworks.com NNTP-Posting-Date: Fri, 6 Sep 2013 17:04:56 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130119 Icedove/10.0.12 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:7015 On 09/06/13 11:55, valtih1978 wrote: > > Here is a funny code that I have Modelsimed > > process > function COMPUTE return boolean is > constant STR: string := "abc"; > begin > -- Error1: Target of signal assignment > -- is not a signal. > --STR <= STR; > > -- Error2: Constant "STR" cannot be target of > -- variable assignment statement. > --STR := STR; > > -- Return assignment is OK! > return STR <= "xyz"; > end function; > > > -- Error3: Type error resolving function call > -- "COMPUTE" as type std.STANDARD.STRING. > --constant STR: string := COMPUTE; > > constant B2:boolean := COMPUTE; > begin > report "Computed b2 = " & boolean'image(B2); > wait; > end process; > > I am getting "Computed b2 = true" in the output despite I do not see anywhere how the > assignment in the end of COMPUTE function evaluates to a boolean. A stand-alone assignment > would violate checks marked with error1 and error2. In your example, '<=' is getting interpreted as 'less than or equal to', not 'signal assignment' here. It is true that "abc" <= "xyz", thus the returned boolean value. Regards, -- Tim McBrayer MathWorks From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: autonomous monitors Date: Sat, 07 Sep 2013 15:39:47 +0200 Lines: 39 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net My4NBT/r9xIA/caDgYFdNQWSfO4RYRgCUyNiefMubvVeRieAOy Cancel-Lock: sha1:BaBda636tfn5UPKZkUTMmi6ZSlg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7016 Hi everyone, I've started to appreciate the benefits of TLM and the usage of bus functional models but I'm facing a small 'design' issue related to the implementation of an autonomous monitor. I have a full-duplex interface where both ends can initiate a packet transfer almost independently from each other. The 'master' may send a command which may or may not result in a reply from the 'slave', but there are a number of packets which are spontaneously sent from the 'slave' without the need to be prompted [1]. IMO this sort of interaction calls for the implementation of a 'monitor' which sense the output of the DUT and performs all sorts of protocol checks. This can be instantiated as part of the BFM but now what to do with the data? Dump the data in a file for later usage is kind of cumbersome especially if some packets are replies to the commands sent by the testbench. Better approach would be to put packets in a fifo to allow the testbench to retrieve them when needed, but how to 'match' commands and replies in order to verify correctness? Any idea/suggestion/hint is appreciated. Al [1] strictly speaking the protocol cannot be qualified as a master/slave one but in /most/ of the cases it is. p.s.: I know most of this stuff is part of a course offered by SynthWorks but unfortunately I do not have currently the resources to afford it... :-( -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.68.196.35 with SMTP id ij3mr3659219pbc.6.1378736936294; Mon, 09 Sep 2013 07:28:56 -0700 (PDT) X-Received: by 10.49.13.10 with SMTP id d10mr12915qec.28.1378736936059; Mon, 09 Sep 2013 07:28:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y3no11675692pbx.0!news-out.google.com!z6ni42760pbu.0!nntp.google.com!j4no14655qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Sep 2013 07:28:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f3de6cb-ecc5-4322-bbdf-ca5a2cceb658@googlegroups.com> Subject: Re: autonomous monitors From: Andy Injection-Date: Mon, 09 Sep 2013 14:28:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7017 You need what is called a scoreboard. If you are using directed tests (where the expected results are known when = you generate the stimulus) then the "master" transaction generator can also= generate "transactions" for expected results from the slave, and send thos= e to the scoreboard. The monitor can also generate transactions based on wh= at it saw on the bus coming from the slave. The scoreboard compares these e= xpected vs actual transactions. Scoreboards can be written to handle in-ord= er or out-of-order transactions. The scoreboard can report any expected or = actual transactions that were not matched up with their counterpart.=20 Random stimulus usually requires a reference (behavioral) model of the DUT = (or reasonable portion thereof) that can generate the expected slave transa= ctions from the master's generated transactions.=20 I'm assuming requirements exist for the slave to generate the non-requested= packets. Therefore, an additional transaction generator might push expecte= d transactions (per the requirements) into the scoreboard to match up with = the actual non-requested slave responses. You can also set up different scoreboards for different types of transactio= ns (e.g. requested vs non-requested slave responses), and handle them separ= ately using a router that inspects transactions and sends them to the appro= priate scoreboard.=20 Lacking resources for Synthworks' TB course, Janick Bergeron's "Writing Tes= tbenches: Functional Verification of HDL Models" is an excellent reference.= I have the first edition (light blue cover), which is strictly VHDL/Verilo= g, whereas the 2nd edition (red cover) also addresses 'e' and Open Vera tec= hniques. I do not know if the 2nd edition covers as much in VHDL/Verilog as= the 1st edition.=20 Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: autonomous monitors Date: Mon, 09 Sep 2013 17:07:36 +0200 Lines: 69 Message-ID: References: <4f3de6cb-ecc5-4322-bbdf-ca5a2cceb658@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 3zRlGzX4TRXhe+uRTekCGgBp62XSXuFUQORIdrMLvykSTbmXit Cancel-Lock: sha1:gGJZWdmWmasVq6Bpdno641+3x74= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <4f3de6cb-ecc5-4322-bbdf-ca5a2cceb658@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7018 On 09/09/2013 16:28, Andy wrote: > If you are using directed tests (where the expected results are known > when you generate the stimulus) then the "master" transaction > generator can also generate "transactions" for expected results from > the slave, and send those to the scoreboard. The monitor can also > generate transactions based on what it saw on the bus coming from the > slave. The scoreboard compares these expected vs actual transactions. > Scoreboards can be written to handle in-order or out-of-order > transactions. The scoreboard can report any expected or actual > transactions that were not matched up with their counterpart. Since the actual transactions might include spontaneous transactions from the DUT, I probably would need to handle 'out of order' transactions and the lookup function may not be so trivial. What about timing though? I presume at this point the 'master' cannot wait for the reply and should simply work as a sequencer. But what if my test depends on values that I read back from the DUT? True I can intentionally avoid these situations on purpose if they are not needed to achieve functional coverage. > > Random stimulus usually requires a reference (behavioral) model of > the DUT (or reasonable portion thereof) that can generate the > expected slave transactions from the master's generated transactions. A random stimulus would be preferable especially when simulating the whole system together since apparently the real hardware is showing lots of problems when integrated. Unfortunately a behavioral model does not exist and even if the investment is certainly worth it I believe the 'management' won't understand the reason for it... (sigh!) > I'm assuming requirements exist for the slave to generate the > non-requested packets. Therefore, an additional transaction generator > might push expected transactions (per the requirements) into the > scoreboard to match up with the actual non-requested slave > responses. This is true indeed for some cases, in some others though the requirement will simply state 'send packet of type blabla every 2 seconds', which can be translated in amount of clock cycles in principle and then looked for at the right time window... but it seems a bit cumbersome. > You can also set up different scoreboards for different types of > transactions (e.g. requested vs non-requested slave responses), and > handle them separately using a router that inspects transactions and > sends them to the appropriate scoreboard. That's interesting indeed, the router should be able to distinguish the transactions based on some identifier (maybe a field in the packet format...) and route them appropriately. > > Lacking resources for Synthworks' TB course, Janick Bergeron's > "Writing Testbenches: Functional Verification of HDL Models" is an > excellent reference. I have the first edition (light blue cover), > which is strictly VHDL/Verilog, whereas the 2nd edition (red cover) > also addresses 'e' and Open Vera techniques. I do not know if the 2nd > edition covers as much in VHDL/Verilog as the 1st edition. I read the 2nd edition and found it extremely inspiring, even though is a bit crowded of 'e' and 'OpenVera' which are not of my interest for the time being (and the foreseeable future). A small section on 'scoreboarding' is presented but not many details are given and it lacks of examples. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: vhdl & verilog simulation Date: Mon, 09 Sep 2013 23:53:57 +0200 Lines: 18 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net pIsX0/4OuhA1JKUBHcdWKAAiwub8xaGO8rqR2rbuzfGOfvsxUU Cancel-Lock: sha1:HziG1cuPYZEGlpNnV4JwbTg9+5o= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7019 Hi everyone, I sadly found that my Actel Modelsim (10.1b) only supports single language simulation (groan!) and I have some verilog modules that I need to use in my vhdl testbench. The verilog modules are not synthesizable. Any suggestion on how to proceed? I know there are some converters out there but wanted to check whether there was any other potential path. Thanks, Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: vhdl & verilog simulation Date: Mon, 9 Sep 2013 15:01:05 -0700 Organization: Highland Technology, Inc. Lines: 29 Message-ID: <20130909150105.3dad1396@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="20523"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PTHPSFvnefqXEOeDGSjTi" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:WeNIfXTuTrMHHrlm1ZmBKYiMZEY= Xref: news.eternal-september.org comp.lang.vhdl:7020 On Mon, 09 Sep 2013 23:53:57 +0200 alb wrote: > Hi everyone, > > I sadly found that my Actel Modelsim (10.1b) only supports single > language simulation (groan!) and I have some verilog modules that I need > to use in my vhdl testbench. The verilog modules are not synthesizable. > > Any suggestion on how to proceed? I know there are some converters out > there but wanted to check whether there was any other potential path. > > Thanks, > > Al > > -- > A: Because it fouls the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? That was when I shelled out for a license for a paid simulator. Aldec Active-HDL cost me $2K a year, and has generally been pretty worth it versus the free version of ModelSim. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx18.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: vhdl & verilog simulation References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 130909-1, 09/09/2013), Outbound message X-Antivirus-Status: Clean Lines: 33 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1378797915 86.29.12.221 (Tue, 10 Sep 2013 07:25:15 UTC) NNTP-Posting-Date: Tue, 10 Sep 2013 07:25:15 UTC Organization: virginmedia.com Date: Tue, 10 Sep 2013 08:25:13 +0100 X-Received-Bytes: 2175 Xref: news.eternal-september.org comp.lang.vhdl:7021 On 09/09/2013 22:53, alb wrote: > Hi everyone, > > I sadly found that my Actel Modelsim (10.1b) only supports single > language simulation (groan!) and I have some verilog modules that I need > to use in my vhdl testbench. The verilog modules are not synthesizable. > > Any suggestion on how to proceed? I know there are some converters out > there but wanted to check whether there was any other potential path. > > Thanks, > > Al > Yes, unfortunately all OEM releases of Modelsim are single language. If you don't use any Actel primitives you could try the free Xilinx ISIM which is dual language. It is a pity your Verilog modules are not synthesizable otherwise you could have used a VHDL generated netlist out of Designer (or Precision/Synplify). Converters are also out of the game because of this. If you are working on a commercial product then I would suggest you bite the bullet and get the commercial Modelsim+ version. It will save you a lot of hassle. Also, if you look at the price of commercial simulators against the cost of an engineer per day it doesn't look so bad any more. Remember all prices are negotiable :-) Good luck, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.66.193.199 with SMTP id hq7mr6943645pac.5.1378802644551; Tue, 10 Sep 2013 01:44:04 -0700 (PDT) X-Received: by 10.50.73.132 with SMTP id l4mr570672igv.0.1378802644266; Tue, 10 Sep 2013 01:44:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!y3no13564183pbx.0!news-out.google.com!z6ni37714pbu.0!nntp.google.com!y3no13564178pbx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 Sep 2013 01:44:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.239.245.27; posting-account=67dTegoAAABp5a3J5Tw7ROLuJO6nAkqt NNTP-Posting-Host: 117.239.245.27 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40d5a7a1-15b8-46a3-99c6-a0a43f7d1f7f@googlegroups.com> Subject: Re: I want get to the fir or iir filter VHDL source. From: aniaccet88@gmail.com Injection-Date: Tue, 10 Sep 2013 08:44:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7022 On Tuesday, 14 March 2000 13:30:00 UTC+5:30, Cheol-Min Han wrote: > Hi all. > > I want get to fir or iir VHDL source. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: vhdl & verilog simulation Date: Tue, 10 Sep 2013 11:32:44 +0200 Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net BUFQRqd2Boeosdz4RrVicAJgx6/jF76AQn3vFvFpOWm1RGuEhf Cancel-Lock: sha1:6/YhEmiooid05Sm3OrU0QWAeXO0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7023 On 10/09/2013 09:25, HT-Lab wrote: [] > If you don't use any Actel primitives you could try the free Xilinx ISIM > which is dual language. Unfortunately that is not the case, another reason why I hate vendor's primitives... (but let me not continue with this rant!) > It is a pity your Verilog modules are not synthesizable otherwise you > could have used a VHDL generated netlist out of Designer (or > Precision/Synplify). Converters are also out of the game because of this. This option indeed was also considered, I'm trying to profit of various modules written for a verilog testbench which was intended for simulation only. I was looking specifically for a 1-wire slave model and after some search I managed to find it. That said I'm a bit confused about why is so complex to make a dual language simulation environment... > If you are working on a commercial product then I would suggest you bite > the bullet and get the commercial Modelsim+ version. It will save you a > lot of hassle. Also, if you look at the price of commercial simulators > against the cost of an engineer per day it doesn't look so bad any more. > Remember all prices are negotiable :-) The project is not commercial (it's a scientific payload), but your considerations about costs do certainly apply also in this case. From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Updating implicit signal Date: Tue, 10 Sep 2013 21:04:24 +0300 Organization: A noiseless patient Spider Lines: 28 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 Sep 2013 18:04:28 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="14251"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+g2L/GbLA39UidTNq7Keyxv7YUF5lmfzE=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 Cancel-Lock: sha1:XudNQGR7FV65D7pfgvv/VJEJsAE= Xref: news.eternal-september.org comp.lang.vhdl:7024 In the http://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_12.HTM#12.6.3 I read
For any implicit signal S'Stable(T), the current value of the signal (and likewise the current state of the corresponding driver) is modified if and only if one of the following statements is true: -- An event has occurred on S in this simulation cycle. -- The driver of S'Stable(T) is active. If an event has occurred on signal S, then S'Stable(T) is updated by assigning the value FALSE to the variable representing the current value of S'Stable(T), and the driver of S'Stable(T) is assigned the waveform TRUE after T. Otherwise, if the driver of S'Stable(T) is active, then S'Stable(T) is updated by assigning the current value of the driver to the variable representing the current value of S'Stable(T). Otherwise, neither the variable nor the driver is modified.
Suppose I have activity at S at 0 an 0.5 ns. The first activity makes S'Stable(1) FALSE in (0, 1 ns) and TRUE after 1 ns on. Second activity comes at 0.5 ns. I expect that S'Stable will be FALSE up to 1.5 ns. However, there is S'Stable=>TRUE schedule at 1.0 ns. I do not see anything in the LRM (or it was a Tutorial?) than cleans up this schedule. So, when I am 1 ns since start, S'Stable(1 ns) will report TRUE, despite event half second before. From newsfish@newsfish Tue Dec 29 16:43:09 2015 X-Received: by 10.66.160.36 with SMTP id xh4mr1913418pab.11.1378919879535; Wed, 11 Sep 2013 10:17:59 -0700 (PDT) X-Received: by 10.50.16.111 with SMTP id f15mr973859igd.2.1378919879422; Wed, 11 Sep 2013 10:17:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b4no11804919pbq.1!news-out.google.com!rn2ni76262pbc.1!nntp.google.com!b4no11804913pbq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Sep 2013 10:17:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Updating implicit signal From: Andy Injection-Date: Wed, 11 Sep 2013 17:17:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7025 Don't forget transport vs. inertial. Inertial is the default. Andy From newsfish@newsfish Tue Dec 29 16:43:09 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Updating implicit signal Date: Thu, 12 Sep 2013 11:15:55 +0300 Organization: A noiseless patient Spider Lines: 2 Message-ID: <5231783B.2080107@not.email.me> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10407"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kSAQh34Nmq1MvWCNtVUO+KwALxmfinqs=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:8fdjMxTpp5JXPmyMQLzWWTLr2HA= Xref: news.eternal-september.org comp.lang.vhdl:7026 By default, inertial delay = transport delay = 0. I want to understand this case first. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: bit slice in vectors Date: Thu, 12 Sep 2013 14:53:27 +0200 Lines: 52 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net MhzqKUJisFiy+IO2JDKk3gsm84LM7n9KS155SEwDz0iSQiXa50 Cancel-Lock: sha1:/xRprOsWAJv4fd+rbT+Jw4lKrXQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7027 Hi everyone, I have declared a set of constants in the following way: constant AB : unsigned(data_t'range) := x"01"; constant CD : unsigned(data_t'range) := x"02"; constant EF : unsigned(data_t'range) := x"04"; constant GH : unsigned(data_t'range) := x"08"; constant IJ : unsigned(data_t'range) := x"10"; constant KL : unsigned(data_t'range) := x"20"; constant MN : unsigned(data_t'range) := x"40"; constant OP : unsigned(data_t'range) := x"80"; where data_t is a constrained std_logic_vector(7 downto 0) type. If we declare a signal/variable foo of data_t type and we want to test if bit 'IJ' is set or not, what I'm currently doing is the following: if foo(to_integer(IJ) - 1) then -- do stuff end if; which I find rather ugly... And if the constant is an slv than I would need to do something like if foo(to_integer(unsigned(IJ) - 1)) then -- do stuff end if; which is even uglier! Is there a more readable way to do that? True I can write my function to handle the conversions and return a natural, but I didn't want to reinvent the wheel :-) On top of this, the limitation of this approach is that if data_t change bus width the constants definitions will not work anymore. Any idea? Thanks a lot, Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.66.229.6 with SMTP id sm6mr3702570pac.30.1379001367129; Thu, 12 Sep 2013 08:56:07 -0700 (PDT) X-Received: by 10.50.66.101 with SMTP id e5mr1157177igt.12.1379001367057; Thu, 12 Sep 2013 08:56:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!rahul.net!wasp.rahul.net!rahul.net!news.kjsl.com!usenet.stanford.edu!b4no13944399pbq.1!news-out.google.com!rn2ni78905pbc.1!nntp.google.com!b4no13944395pbq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Sep 2013 08:56:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: bit slice in vectors From: KJ Injection-Date: Thu, 12 Sep 2013 15:56:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7028 On Thursday, September 12, 2013 8:53:27 AM UTC-4, alb wrote: It's not clear to me why 'IJ' is anything other than an integer in your exa= mple. That would clean up most of what you seem to not like. As for a cleaner overall approach, presumably the reason that you're defini= ng all of those constants is because the data should really be defined as a= record and there is a need to convert between the record type and std_logi= c_vectors. There probably isn't much value in your current definition of '= data_t' type as being just another vector. Take a look at this post... https://groups.google.com/forum/?hl=3Den#!searchin/comp.lang.vhdl/to_std_ul= ogic_vector$20jennings/comp.lang.vhdl/9s7wXZUWqrQ/-K2fqq-YfGkJ Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.66.26.5 with SMTP id h5mr4009279pag.1.1379007039609; Thu, 12 Sep 2013 10:30:39 -0700 (PDT) X-Received: by 10.50.92.100 with SMTP id cl4mr425901igb.8.1379007039510; Thu, 12 Sep 2013 10:30:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b4no14129206pbq.1!news-out.google.com!z6ni48021pbu.0!nntp.google.com!y3no19572523pbx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Sep 2013 10:30:39 -0700 (PDT) In-Reply-To: <5231783B.2080107@not.email.me> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <5231783B.2080107@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Updating implicit signal From: Andy Injection-Date: Thu, 12 Sep 2013 17:30:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7029 On Thursday, September 12, 2013 3:15:55 AM UTC-5, valtih1978 wrote: > By default, inertial delay = transport delay = 0. I want to understand this case first. No, the default pulse rejection limit for inertial delay is the time expression associated with the first waveform element. Therefore: S <= reject 0 ns inertial not S after 10 ns; is equivalent to: S <= transport not S after 10 ns; but is NOT equivalent to: S <= inertial not S after 10 ns; -- with or without "inertial" Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.66.145.162 with SMTP id sv2mr3904190pab.15.1379007980982; Thu, 12 Sep 2013 10:46:20 -0700 (PDT) X-Received: by 10.50.36.67 with SMTP id o3mr436625igj.1.1379007980853; Thu, 12 Sep 2013 10:46:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!easy.in-chemnitz.de!news2.arglkargh.de!news.litech.org!lnsnews.lns.cornell.edu!usenet.stanford.edu!y3no19607700pbx.0!news-out.google.com!rn2ni78905pbc.1!nntp.google.com!b4no14158636pbq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Sep 2013 10:46:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ca276c4-8f60-4754-8021-8805619ff3d7@googlegroups.com> Subject: Re: bit slice in vectors From: Andy Injection-Date: Thu, 12 Sep 2013 17:46:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7030 Al, I would encourage to you to use integers (or subtypes thereof) wherever possible, particularly in places where unknown or tri-state representation is not needed, and the representation size is <= 31 bits unsigned or 32 bits signed. And as Kevin said, especialy for your constants. If the constants are also needed in unsigned/slv form, consider which is easier or less common in your application: converting slv/unsigned to integer, or integer to slv/unsigned? Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: bit slice in vectors Date: Fri, 13 Sep 2013 11:43:07 +0200 Lines: 39 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net mhh+cuHxOmT93yo94gD5qA/vZL9TTAyd6grW2aN0cYjufdzlUh Cancel-Lock: sha1:osRNhXWC397zCjSr4koPw9Rg6wk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7031 Hi KJ, On 12/09/2013 17:56, KJ wrote: > It's not clear to me why 'IJ' is anything other than an integer in > your example. That would clean up most of what you seem to not > like. because sometimes your 'emergency exit might be located just behind you'! > As for a cleaner overall approach, presumably the reason that you're > defining all of those constants is because the data should really be > defined as a record and there is a need to convert between the record > type and std_logic_vectors. There probably isn't much value in your > current definition of 'data_t' type as being just another vector. Constants definition is used, for example, in an interrupt enable register assignment which can be easily performed this way: interrupt_reg := PD or PDE or TBE; or equivalently in the case of integer defined constants: interrupt_reg(PD) := '1'; interrupt_reg(PDE) := '1'; interrupt_reg(TBE) := '1'; And by the way I just found that in the OP there's a mistake in the conversion, since it will only work for bit 1 and 2...!!! > Take a look at this post... > > https://groups.google.com/forum/?hl=en#!searchin/comp.lang.vhdl/to_std_ulogic_vector$20jennings/comp.lang.vhdl/9s7wXZUWqrQ/-K2fqq-YfGkJ That post inspired me a great deal and now I do have conversion functions from/to my record types. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Updating implicit signal Date: Fri, 13 Sep 2013 15:45:05 +0300 Organization: A noiseless patient Spider Lines: 1 Message-ID: References: <5231783B.2080107@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 13 Sep 2013 12:45:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="22533"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18HWHZkYoj7fs9eBjzdyo0l9HhXyCL4owI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:zEDH6uPYUp3ZGk603YLDKXtCOLM= Xref: news.eternal-september.org comp.lang.vhdl:7032 I feel it is the time to unveil how is this is related with my question From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.66.27.67 with SMTP id r3mr5813507pag.27.1379086731631; Fri, 13 Sep 2013 08:38:51 -0700 (PDT) X-Received: by 10.49.26.225 with SMTP id o1mr37648qeg.37.1379086731442; Fri, 13 Sep 2013 08:38:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!y3no22308331pbx.0!news-out.google.com!z6ni49901pbu.0!nntp.google.com!z6no85377pbz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Sep 2013 08:38:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=187.36.242.49; posting-account=jbpDJQoAAADx89uRmr2r3pvexn0LkuHT NNTP-Posting-Host: 187.36.242.49 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Subject: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" From: Christiano Injection-Date: Fri, 13 Sep 2013 15:38:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7033 If anyone has had this problem, just do this: ghdl -a --ieee=synopsys x.vhd From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" Date: Sun, 15 Sep 2013 06:49:28 +0200 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 15 Sep 2013 04:49:28 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="be76bc5c4fc46899d8aeb595072e9b2c"; logging-data="2461"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/yAGbTAVWjysGAomDhfzw+" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Cancel-Lock: sha1:wBH6Q9KMoxUY5uvijlDZ8THp/N8= Xref: news.eternal-september.org comp.lang.vhdl:7034 > If anyone has had this problem, just do this: > ghdl -a --ieee=synopsys x.vhd I avoid the proprietary and obsolete std_logic_arith/std_logic_unsigned everywhere. I use the "official" ieee.numeric_std.all for arithmetic. Don't mix the librarys. So unsigned and signed types are usable on ports without headaches. regards, Bart Fox From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: How did Ashenden know about STD_INPUT? Date: Mon, 16 Sep 2013 18:42:14 +0300 Organization: A noiseless patient Spider Lines: 5 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 16 Sep 2013 15:42:21 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="16505"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1//i6UwEVkw1Kc4ZXcamrsu2pba4S+TuNk=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 Cancel-Lock: sha1:KdHgOCC9XBo7FhW5Xa4/VoRqiDs= Xref: news.eternal-september.org comp.lang.vhdl:7035 I see that VHDL2008 provides std.textio package, which defines file INPUT: TEXT open READ_MODE is "STD_INPUT". But, this is the only one occurence of STD_INPUT in the whole document. So, nowhere 2008 specifies that files named STD_INPUT must be mapped to something special. Why do Ashenden and modelsim do that? From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.96.136 with SMTP id h8mr319790qan.8.1379352260008; Mon, 16 Sep 2013 10:24:20 -0700 (PDT) X-Received: by 10.49.48.38 with SMTP id i6mr1428640qen.4.1379352259948; Mon, 16 Sep 2013 10:24:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!d5no170040qap.0!news-out.google.com!gv3ni309qab.0!nntp.google.com!d5no197025qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Sep 2013 10:24:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4b16df79-7ccc-485b-b2cb-82cce72ccaef@googlegroups.com> Subject: Re: bit slice in vectors From: Andy Injection-Date: Mon, 16 Sep 2013 17:24:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 11 Xref: news.eternal-september.org comp.lang.vhdl:7036 Al, Assuming the integer constants are locally static: interrupt_reg := (PD | PDE | TBE => '1', others => '0'); would also work. Where there is a will, there is a way. Circumstances dictate whether the will is worth the way. Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.5.5 with SMTP id 5mr482852qat.4.1379355544909; Mon, 16 Sep 2013 11:19:04 -0700 (PDT) X-Received: by 10.50.35.228 with SMTP id l4mr2233601igj.15.1379355544779; Mon, 16 Sep 2013 11:19:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!d5no175585qap.0!news-out.google.com!gv3ni309qab.0!nntp.google.com!d5no202730qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Sep 2013 11:19:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> Subject: Re: How did Ashenden know about STD_INPUT? From: Jim Lewis Injection-Date: Mon, 16 Sep 2013 18:19:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: news.eternal-september.org comp.lang.vhdl:7037 Being defined concisely in one place (std.textio) is sufficient! ... So if you really like brain teasers, where in the standard does it say the following parentheses are required: Y <= (A and B) or C ; From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.137.67 with SMTP id v3mr606895qat.0.1379358936924; Mon, 16 Sep 2013 12:15:36 -0700 (PDT) X-Received: by 10.49.48.38 with SMTP id i6mr1445278qen.4.1379358936851; Mon, 16 Sep 2013 12:15:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no208452qap.0!news-out.google.com!gv3ni309qab.0!nntp.google.com!d5no208443qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Sep 2013 12:15:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <5231783B.2080107@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Updating implicit signal From: Andy Injection-Date: Mon, 16 Sep 2013 19:15:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7038 On Friday, September 13, 2013 7:45:05 AM UTC-5, valtih1978 wrote: > I feel it is the time to unveil how is this is related with my question "You can lead a horse to water, but you cannot make it drink." Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.5.5 with SMTP id 5mr5107701qat.4.1379498888636; Wed, 18 Sep 2013 03:08:08 -0700 (PDT) X-Received: by 10.50.111.200 with SMTP id ik8mr992244igb.7.1379498888600; Wed, 18 Sep 2013 03:08:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!d5no394509qap.0!news-out.google.com!gv3ni456qab.0!nntp.google.com!d5no394505qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Sep 2013 03:08:08 -0700 (PDT) In-Reply-To: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.134.193; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.134.193 References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> Subject: Re: How did Ashenden know about STD_INPUT? From: Dio Gratia Injection-Date: Wed, 18 Sep 2013 10:08:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2285 Xref: news.eternal-september.org comp.lang.vhdl:7039 On Tuesday, September 17, 2013 6:19:04 AM UTC+12, Jim Lewis wrote: > > So if you really like brain teasers, where in the standard does it say the following parentheses are required: > > > > Y <= (A and B) or C ; 9.1 General ... expression ::= relation { and relation } | relation { or relation } | relation { xor relation } | relation [ nand relation ] | relation [ nor relation ] | relation { xnor relation } relation ::= shift_expression [ relational_operator shift_expression ] shift_expression ::= simple_expression [ shift_operator simple_expression ] simple_expression ::= [ sign ] term { adding_operator term } term ::= factor { multiplying_operator factor } factor ::= primary [ ** primary ] | abs primary | not primary primary ::= name | literal | aggregate | function_call | qualified_expression | type_conversion | allocator | ( expression ) <== RIGHT HERE From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How did Ashenden know about STD_INPUT? Date: Wed, 18 Sep 2013 14:01:09 +0300 Organization: A noiseless patient Spider Lines: 2 Message-ID: References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Sep 2013 11:01:16 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="8911"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+DMEON9g85+t/CrsAs5hBVCmybY1C31FY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> Cancel-Lock: sha1:yHjkelXJ6SY1jIJ/ninoxmG9GGg= Xref: news.eternal-september.org comp.lang.vhdl:7040 +1 From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.126.137 with SMTP id c9mr5934786qas.2.1379524315559; Wed, 18 Sep 2013 10:11:55 -0700 (PDT) X-Received: by 10.49.13.10 with SMTP id d10mr109496qec.28.1379524315532; Wed, 18 Sep 2013 10:11:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no391370qap.0!news-out.google.com!gv3ni566qab.0!nntp.google.com!d5no391366qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Sep 2013 10:11:55 -0700 (PDT) In-Reply-To: <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> Subject: Re: How did Ashenden know about STD_INPUT? From: Andy Injection-Date: Wed, 18 Sep 2013 17:11:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7041 On Wednesday, September 18, 2013 5:08:08 AM UTC-5, Dio Gratia wrote: > | ( expression ) <== RIGHT HERE Not exactly... Jim asked where the standard REQUIRES the parentheses in his example. If that chain of definitions actually REQUIRED parentheses in his example, then they would also be required in the following example, in which they are not required: Y <= A and B and C; So either that chain can be interpreted to allow, but not require, parentheses around every pair of operands with a logic operator, or it is incorrectly stated. The intent of that chain was to define operator precedence, and to establish that logical operators do not have a defined precedence over each other. Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How did Ashenden know about STD_INPUT? Date: Wed, 18 Sep 2013 21:49:14 +0300 Organization: A noiseless patient Spider Lines: 7 Message-ID: <5239F5AA.4030606@not.email.me> References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="20974"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/oSdLARheV1paN0vbRqwKBrOsUmritrZI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> Cancel-Lock: sha1:Tledh2FfRBGN2eHyYYW/tl51UvM= Xref: news.eternal-september.org comp.lang.vhdl:7042 At first, my example of "not specified" is more correct than Jim's because meaning of parenthis is discussed in the operator precedence: "parentheses can be used to control the association of operators and operands." (9.2.1 Operators General). Secondly, if you insist that there is no requirement in (A or B) or C then there is no requirement for STD_INPUT to be mapped to console or whatever. Please do not overcomplicate matters with useless examples. From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.66.20.100 with SMTP id m4mr15673221pae.36.1379543345658; Wed, 18 Sep 2013 15:29:05 -0700 (PDT) X-Received: by 10.50.9.33 with SMTP id w1mr1113720iga.12.1379543345617; Wed, 18 Sep 2013 15:29:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no10132878pbz.1!news-out.google.com!z6ni59312pbu.0!nntp.google.com!z6no10132871pbz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Sep 2013 15:29:05 -0700 (PDT) In-Reply-To: <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.134.193; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.134.193 References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3c3f9cf2-3e65-4d39-b8fd-24d6e0f4c61a@googlegroups.com> Subject: Re: How did Ashenden know about STD_INPUT? From: Dio Gratia Injection-Date: Wed, 18 Sep 2013 22:29:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7043 On Thursday, September 19, 2013 5:11:55 AM UTC+12, Andy wrote: > On Wednesday, September 18, 2013 5:08:08 AM UTC-5, Dio Gratia wrote: >=20 > > | ( expression ) <=3D=3D RIGHT HERE >=20 >=20 >=20 > Not exactly... Jim asked where the standard REQUIRES the parentheses in h= is example.=20 >=20 > If that chain of definitions actually REQUIRED parentheses in his example= , then they would also be required in the following example, in which they = are not required: >=20 >=20 > Y <=3D A and B and C; >=20 > So either that chain can be interpreted to allow, but not require, parent= heses around every pair of operands with a logic operator, or it is incorre= ctly stated.=20 >=20 > The intent of that chain was to define operator precedence, and to establ= ish that logical operators do not have a defined precedence over each other= .=20 >=20 (Clause references are from IEEE Std 1076-2008) The right hand side first production for expression allows A and B and C = to be in the same expression, not requiring parenthesis. { and relation } 1.3.2 Syntactic description "f) Braces { } enclose a repeated item or items on the right-hand side of a= production. The items may appear zero or more times; the repetitions occur= from left to right as with an equivalent left-recursive rule." You'll also note from the BNF that nand and nor require single instances in= an expression, (also from 1.3.2): "c) Square brackets [ ] enclose optional items on the right-hand side of a = production;"=20 with no provision for repetition, because nand and nor aren't associative. = The BNF found in Clause 9. Expressions is normative. The point is to insu= re parenthesis are used where the are required. And yes, I'm aware that Jim's signal assignment statement is capable of pro= ducing the right answer without parenthesis due to occurrence left to right= in a left recursion production if it weren't forced to be comprised of two= expressions in a left recursion. Note Y <=3D (A and B and C) or D; is 'legal' while Y <=3D A and B and C or D; isn't, according to the BNF. While I don't have access to a lot of different VHDL analyzers currently, t= here are those that devolve expressions according to the BNF from 9.1, or s= ay 7.1 Expressions, from 1076-1993 as in the case of ghdl with it's awkward= error message for Jim's signal assignment: only one type of logical operators may be used to combine relation I'd think operators should be singular while relation should be pluralized.= =20 ghdl also 'correctly' requires single occurrences of nand and nor with pars= e error messages: sequence of 'nor' or 'nand' not allowed and ('nor' and 'nand' are not associative) There's a subtle message here, that the BNF found in the standard other tha= n in an appendix is normative. And try as you might there doesn't appear t= o be another place in the standard that requires the parenthesis.=20 You can look in non-authoritative texts such as Mentor Graphics VHDL Refere= nce Manual from 1994, which tells you somewhere between pages 2-3 and 2-9 (= PDF pages 47-53) that the parenthesis are required in discussing expression= s.=20 My historical pet peeve along the line of Frank's STD_INPUT is IR1045, disa= mbiguating single quotes from character literals lexically, as in: b <=3D std_logic_vector'('0','1','1','0'); While the standard similarly (to the parenthesis issue) gives permission (1= 5.3): "In some cases an explicit separator is required to separate adjacent lexic= al elements (namely when, without separation, interpretation as a single le= xical element is possible)." Issue Report 1045 was never adopted but explains how to disambiguate. The = technique is widely used (I did a survey) but not expressed in the standard= , where a natural tendency to a certain paranoia expressed itself as viewin= g the lack as supporting a zero sum competition stance. There was a similar issue for Ada95, widely publicized although I don't rec= all the AI number. In actuality there aren't enough tool authors especiall= y as the standards increase in volume over time, to oil all the small squea= ks. We see the disgruntled start up competing HDL language standards inste= ad although some large number of those efforts fall the wayside. From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.58.255.74 with SMTP id ao10mr170864ved.38.1379608527383; Thu, 19 Sep 2013 09:35:27 -0700 (PDT) X-Received: by 10.50.40.103 with SMTP id w7mr125773igk.7.1379608527114; Thu, 19 Sep 2013 09:35:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no511375qap.0!news-out.google.com!gv3ni711qab.0!nntp.google.com!d5no462413qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Sep 2013 09:35:26 -0700 (PDT) In-Reply-To: <3c3f9cf2-3e65-4d39-b8fd-24d6e0f4c61a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <95f85dc8-41dc-4544-ab0c-1cbbdac8cd4c@googlegroups.com> <5863dc7b-fd3b-4bbb-a468-498381a4eac4@googlegroups.com> <6940d0c4-8adf-4bdc-a80f-eef21abd4d73@googlegroups.com> <3c3f9cf2-3e65-4d39-b8fd-24d6e0f4c61a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8a390dd5-6f07-4769-a3c2-50bd9f83e60b@googlegroups.com> Subject: Re: How did Ashenden know about STD_INPUT? From: Andy Injection-Date: Thu, 19 Sep 2013 16:35:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7044 Thanks, Dio Gratia. I missed the distinction between [] and {} in the BNF. Your response is most helpful and informative. Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: combinational loops Date: Fri, 20 Sep 2013 12:33:43 +0200 Lines: 64 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net XzYEIUKN3WMwnlapRjsAHgRywcSgnKYhQFRVljYFN9l7DRiS0a Cancel-Lock: sha1:oQbYvQRrdKuY1fmkYjAiQlMMvMo= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7045 Dear all, during P&R Actel Designer barfs this information (not a warning): > While analyzing gated clock network, ambiguities have been found on gates > temperature_1/tfsm_1/main.nwr_v_RNI3GSJ:Y, temperature_1/tfsm_1/main.nwr_v_RNIOVCF:Y, > master_clock_routing_RNO:Y, temperature_1/tfsm_1/main.nrd_v_RNI12QJ:Y. > The timing models of these gates have been simplified for Static Timing Analysis. All gates except 'master_clock_routing' are defined in the following code and they are the ones I'm interested into: begin -- procedure autoread case state_v is when IDLE => cnt_v := 0; state_v := SET_CLKRATE; when READ_BGN => state_v := READ_END; -- this is one clock cycle nRD_v := '0'; when READ_END => state_v := nstate_v; nRD_v := '1'; DATA_v := DATA; when WRITE_BGN => state_v := WRITE_END; -- this is one clock cycle nWR_v := '0'; when WRITE_END => state_v := nstate_v; nWR_v := '1'; DATA_v := (others => 'Z'); -- release the bus and the procedure is called at each clock cycle in a template like this: ------------------------------------------------------------------------------- procedure update_regs is begin -- purpose: call the procedures above in the desired order autoread; end procedure update_regs; ------------------------------------------------------------------------------- begin if RST = '1' then init_regs; elsif rising_edge(CLK) then update_regs; end if; update_ports; end process main; It sim'ed ok, both pre/post-synthesis and post-layout. STA does not report timing violations. Why there're combinational loops??? Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 20 Sep 2013 12:42:31 +0200 Lines: 8 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net UY1vE51iRScalxZis1sJzQroCze21m0IkW6PwoMNSJE27bCAR6 Cancel-Lock: sha1:axZxBnNABT4xPiAYGXbBGHzfncI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7046 Correction to my previous post in this thread: On 20/09/2013 12:33, alb wrote: [] > It sim'ed ok, both pre/post-synthesis and post-layout. STA does not > report timing violations. STA *does* report timing violations. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 20 Sep 2013 16:56:46 -0400 Organization: A noiseless patient Spider Lines: 74 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 20 Sep 2013 20:56:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="2f1d56cc32a64948e21bd8c19c258ccf"; logging-data="22246"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ksb3rZZ2L3wjQbqSAZkIM" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:8H+8t7NYSXE1rXxeNRx9yjG+03s= Xref: news.eternal-september.org comp.lang.vhdl:7047 On 9/20/2013 6:33 AM, alb wrote: > Dear all, > > during P&R Actel Designer barfs this information (not a warning): > >> While analyzing gated clock network, ambiguities have been found on gates >> temperature_1/tfsm_1/main.nwr_v_RNI3GSJ:Y, temperature_1/tfsm_1/main.nwr_v_RNIOVCF:Y, >> master_clock_routing_RNO:Y, temperature_1/tfsm_1/main.nrd_v_RNI12QJ:Y. >> The timing models of these gates have been simplified for Static Timing Analysis. > > All gates except 'master_clock_routing' are defined in the following > code and they are the ones I'm interested into: > > > begin -- procedure autoread > case state_v is > when IDLE => > cnt_v := 0; > state_v := SET_CLKRATE; > > when READ_BGN => > state_v := READ_END; -- this is one clock cycle > nRD_v := '0'; > when READ_END => > state_v := nstate_v; > nRD_v := '1'; > DATA_v := DATA; > when WRITE_BGN => > state_v := WRITE_END; -- this is one clock cycle > nWR_v := '0'; > when WRITE_END => > state_v := nstate_v; > nWR_v := '1'; > DATA_v := (others => 'Z'); -- release the bus > > > and the procedure is called at each clock cycle in a template like this: > > > ------------------------------------------------------------------------------- > procedure update_regs is > begin -- purpose: call the procedures above in the desired order > autoread; > end procedure update_regs; > ------------------------------------------------------------------------------- > begin > if RST = '1' then > init_regs; > elsif rising_edge(CLK) then > update_regs; > end if; > update_ports; > end process main; > > > It sim'ed ok, both pre/post-synthesis and post-layout. STA does not > report timing violations. Why there're combinational loops??? I'm not very happy with the way you have separated the register code from the output code. For example the procedure autoread is invoked from the registered section of the clocked process. This means any signals assigned a value in this procedure will be registered. The last line shown in this procedure assigns a high impedance value to what I assume is a signal, that's not realizable, or at least it isn't the way I would do it. Unless you show us all your code it will be hard to pin point your combinatorial loop. The problem is most likely in init_regs or update_ports as these are not registered. -- Rick From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 23 Sep 2013 10:03:41 +0200 Lines: 510 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net GJuEhuaRN3CcG4tMlENqswuyIdIWYJM9GqPiOti12oYXQt5e1L Cancel-Lock: sha1:+jHOEJNIxfEiFzr13vLKsv4pngA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7048 On 20/09/2013 22:56, rickman wrote: [see end of this post for the entire code] > > I'm not very happy with the way you have separated the register code > from the output code. For example the procedure autoread is invoked > from the registered section of the clocked process. This means any > signals assigned a value in this procedure will be registered. I do not have signals, I have only variables and they are synthesized to registers or wires according to whether they need to retain a value or not. > The last line shown in this procedure assigns a high impedance value to > what I assume is a signal, that's not realizable, or at least it isn't > the way I would do it. The DATA_v variable is not the main issue here, I'm concerned about combinational loops on nRD_v and nWR_v. OT, on the 'Z' assignment, it is clear that while internal resources of an FPGA do not provide tri-state logic, they can easily be transformed to a set of multiplexers which logically provide the same functionality. It is clear that no condition should exist for multiple drivers on the line. On a side note, shouldn't be better to use std_ulogic_vector to spot multiple drivers on the bus instead of std_logic_vector? I'm naively assuming that an unresolved type would help me spotting multiple drivers at compilation time... > > Unless you show us all your code it will be hard to pin point your > combinatorial loop. The problem is most likely in init_regs or > update_ports as these are not registered. I believe that not posting the whole code was a bad idea so it follows at the end of this post, but let me add that init_regs does not mean they are 'not registered'. The clocked process has an asynchronous reset which triggers the 'initialization' of everything needs to be initialized, while the update_ports only 'connects' the variables to the entity ports (no register involved here). While I cannot be 100% sure that the problem is in the snippet I previously posted, I'm quite confident that the rest of the code should not play an important role. In 'pkg_temp' there are some constant definitions only. > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > use ieee.numeric_std.all; > > library work; > use work.pkg_temp.all; > > ------------------------------------------------------------------------------- > > entity tfsm is > port ( > ADD_i : in std_logic_vector(2 downto 0); > nRD_i : in std_logic; > nWR_i : in std_logic; > ADD_o : out std_logic_vector(2 downto 0); > nRD_o : out std_logic; > nWR_o : out std_logic; > DATA : inout std_logic_vector(7 downto 0); > TEMP : out std_logic_vector(15 downto 0); > SRNO : out std_logic_vector(63 downto 0); > ST : in std_logic; > CLK : in std_logic; > RST : in std_logic); > > end tfsm; > > ------------------------------------------------------------------------------- > > architecture tfsm_arch of tfsm is > -- Note: No signal declarations. > begin -- tfsm_arch > > main : process (CLK, RST) is > ------------------------------------------------------------------------------- > type state_t is ( > SET_CLKRATE, > SET_CTRLREG, > CLR_INTREG, > SET_INEREG, > SEND_READ_ROM, > SEND_SKIP_ROM, > SEND_WRITE_SCRATCHPAD, > SEND_CONVERT, > SEND_READ_SCRATCH, > > -- reusable states > SEND_RESET, > TEST_PRESENCE, > > SEND_CMD, > TEST_CMD, > > SEND_DATA, > TEST_DATA, > > WRITE_BGN, > WRITE_END, > > READ_BGN, > READ_END, > IDLE > ); > > variable state_v : state_t; -- current state > variable nstate_v : state_t; -- next state after write/read > variable mstate_v : state_t; -- next state after macro command > variable lstate_v : state_t; -- next state after skip rom > > variable cmd_v : integer; -- command to send > variable dat_v : integer; -- data to send > variable cnt_v : integer; -- counter > > ------------------------------------------------------------------------------- > -- Data Registers > subtype bus_t is std_logic_vector(DATA'range); -- match port width > variable DATA_v : bus_t; > > -- Address registers > subtype add_t is std_logic_vector(ADD_i'range); -- match port width > variable ADD_v : add_t; > > -- control wires > subtype ctr_t is std_logic; > variable nRD_v : ctr_t; > variable nWR_v : ctr_t; > > -- sensor id type > type sens_t is array (7 downto 0) of std_logic_vector (7 downto 0); > > -- sensor temperature type > type temp_t is array (1 downto 0) of std_logic_vector (7 downto 0); > > -- scratchpad type > type scratch_t is array (2 downto 0) of integer; > > -- temperature registers > -- temp_count_v: will count each time there's a new temperature available > -- temp_valid_v: will be set to one when ID AND first temperature readout > -- are both valid > > variable temp_count_v : std_logic_vector(2 downto 0); > variable temp_valid_v : std_logic; > variable temp_value_v : temp_t; > > -- sensor id register > variable sens_id_v : sens_t; > > -- scratchpad register > variable scratchpad_v : scratch_t; > > ------------------------------------------------------------------------------- > procedure bus_init is -- used in init_regs > begin > DATA_v := (others => 'Z'); > ADD_v := (others => '0'); > nRD_v := '1'; -- inactive > nWR_v := '1'; -- inactive > > temp_count_v := "000"; > temp_valid_v := '0'; > temp_value_v(0) := x"00"; > temp_value_v(1) := x"00"; > > sens_id_v(0) := x"28"; -- for test only > sens_id_v(1) := x"DE"; -- for test only > sens_id_v(2) := x"D5"; -- for test only > sens_id_v(3) := x"45"; -- for test only > sens_id_v(4) := x"03"; -- for test only > sens_id_v(5) := x"00"; -- for test only > sens_id_v(6) := x"00"; -- for test only > sens_id_v(7) := x"C0"; -- crc > > end procedure bus_init; > > ------------------------------------------------------------------------------- > procedure fsm_init is -- used in init_regs > begin > state_v := IDLE; > nstate_v := IDLE; > mstate_v := IDLE; > lstate_v := IDLE; > > cmd_v := 0; > cnt_v := 0; > dat_v := 0; > > scratchpad_v (0) := 40; -- x"28" -> +40 degrees > scratchpad_v (1) := 226; -- x"E2" -> -30 degrees > scratchpad_v (2) := 127; -- x"7F" -> I have no idea! > end procedure fsm_init; > > ------------------------------------------------------------------------------- > procedure init_regs is > begin > bus_init; > fsm_init; > end procedure init_regs; > > ------------------------------------------------------------------------------- > procedure update_ports is > begin -- purpose: synthesize a wire from the register to the port > > -- ST is a register bit that allows start/stop of the automatic > -- temperature readout procedure. It is set in the control register of > -- the DS1WM and propagated up to here (see one_wire_interface.vhd) > > mux : if ST then > DATA <= DATA_v; > nRD_o <= nRD_v; > nWR_o <= nWR_v; > ADD_o <= ADD_v; > else > DATA <= (others => 'Z'); > nRD_o <= nRD_i; > nWR_o <= nWR_i; > ADD_o <= ADD_i; > end if; > > TEMP <= temp_count_v & > temp_valid_v & > temp_value_v(1)(3 downto 0) & > temp_value_v(0); > > sensor_id : for i in 0 to 7 loop > SRNO(8*(i+1)-1 downto 8*i) <= sens_id_v(i); > end loop sensor_id; > > end procedure update_ports; > ------------------------------------------------------------------------------- > procedure autoread is > -- local procedures for statements used more than once: > procedure write_ds1wm ( > add : in add_t; > val : in integer) is > begin > state_v := WRITE_BGN; > ADD_v := add; > DATA_v := std_logic_vector(to_unsigned(val, DATA_v'length)); > end write_ds1wm; > -- > procedure read_ds1wm ( > add : in add_t) is > begin > state_v := READ_BGN; > ADD_v := add; > DATA_v := (others => 'Z'); > end read_ds1wm; > > procedure inc_tic_count is > begin > cnt_v := cnt_v + 1; > end procedure inc_tic_count; > > procedure inc_tem_count is > begin > temp_count_v := temp_count_v + '1'; > end procedure inc_tem_count; > > begin -- procedure autoread > if ST then > case state_v is > when IDLE => > cnt_v := 0; > state_v := SET_CLKRATE; > > ------------------------------------------------------------------------------- > -- Write and Read states are special ones since they are called several times > -- by every other state, it is therefore necessary to store the value of the > -- next state once the write/read steps have been completed, in order to > -- continue with the fsm. > ------------------------------------------------------------------------------- > when READ_BGN => > state_v := READ_END; -- this is one clock cycle > nRD_v := not nRD_v; > when READ_END => > state_v := nstate_v; > nRD_v := not nRD_v; > DATA_v := DATA; > when WRITE_BGN => > state_v := WRITE_END; -- this is one clock cycle > nWR_v := not nWR_v; > when WRITE_END => > state_v := nstate_v; > nWR_v := not nWR_v; > DATA_v := (others => 'Z'); -- release the bus > > ------------------------------------------------------------------------------- > -- Init part for the DS1WM. Set clock rate, control register, clean > -- interrupt register and configure interrupt enable register > ------------------------------------------------------------------------------- > when SET_CLKRATE => > nstate_v := SET_CTRLREG; > write_ds1wm(CLKREG, 138); -- clock enabled + 20 MHz > when SET_CTRLREG => > nstate_v := CLR_INTREG; > write_ds1wm(CTLREG, 2**STB); -- keep STB active! > when CLR_INTREG => > nstate_v := SET_INEREG; > read_ds1wm(INFREG); > when SET_INEREG => > nstate_v := SEND_RESET; > mstate_v := SEND_READ_ROM; > write_ds1wm(INEREG, 2**EPD + 2**ETBE + 2**ERBF); > > ------------------------------------------------------------------------------- > -- Start DS1WM transactions with a 1wire reset. Each 1-wire transaction has > -- always three phases: > -- 1. initialization (RESET) > -- 2. ROM command > -- 3. FUNCTION command > ------------------------------------------------------------------------------- > > when SEND_RESET => > nstate_v := TEST_PRESENCE; > write_ds1wm(CMDREG, 2**OneWR); > > when TEST_PRESENCE => > -- we should foresee a timeout...!!! > if DATA_v(PD) and not DATA_v(PDR) then > state_v := mstate_v; > else > nstate_v := state_v; > read_ds1wm(INFREG); > end if; > > ------------------------------------------------------------------------------- > -- SEND command cmd_v. This sequence of states is referenced as a 'macro' as it > -- will depend on the mstate_v defined by the calling state. > ------------------------------------------------------------------------------- > when SEND_CMD => > nstate_v := TEST_CMD; > write_ds1wm(DATBUF, cmd_v); > > when TEST_CMD => > -- we should foresee a timeout...!!! > if DATA_v(RBF) then > nstate_v := mstate_v; > read_ds1wm(DATBUF); -- empty data buffer! > else > nstate_v := state_v; > read_ds1wm(INFREG); > end if; > > ------------------------------------------------------------------------------- > -- Read cnt_v data times to register. This sequence of states is references as > -- a 'macro' as it will depend on the mstate_v defined by the calling state. > ------------------------------------------------------------------------------- > > when SEND_DATA => > nstate_v := TEST_DATA; > write_ds1wm(DATBUF, dat_v); > > when TEST_DATA => > -- we should foresee a timeout...!!! > if DATA_v(RBF) then > nstate_v := mstate_v; > read_ds1wm(DATBUF); > else > nstate_v := state_v; > read_ds1wm(INFREG); > end if; > > ------------------------------------------------------------------------------- > > when SEND_READ_ROM => > mstate_v := SEND_READ_ROM; > -- read data after the first SEND_DATA is over (cnt_v = 2) > if cnt_v > 1 then > sens_id_v(cnt_v - 2) := DATA_v; > end if; > > if cnt_v = 0 then > cmd_v := READ_ROM; > state_v := SEND_CMD; > inc_tic_count; > elsif cnt_v <= 8 then > dat_v := GET_DATA; > state_v := SEND_DATA; > inc_tic_count; > else > cnt_v := 0; > state_v := SEND_WRITE_SCRATCHPAD; > end if; > > ------------------------------------------------------------------------------- > > when SEND_WRITE_SCRATCHPAD => > mstate_v := SEND_WRITE_SCRATCHPAD; > if cnt_v = 0 then > cmd_v := WRITE_SCRATCH; > state_v := SEND_CMD; > inc_tic_count; > elsif cnt_v <= 3 then > dat_v := scratchpad_v(cnt_v - 1); > state_v := SEND_DATA; > inc_tic_count; > else > cnt_v := 0; > mstate_v := SEND_SKIP_ROM; > lstate_v := SEND_CONVERT; > state_v := SEND_RESET; > end if; > > ------------------------------------------------------------------------------- > > when SEND_SKIP_ROM => > cmd_v := SKIP_ROM; > state_v := SEND_CMD; > mstate_v := lstate_v; > > ------------------------------------------------------------------------------- > > when SEND_CONVERT => > mstate_v := SEND_CONVERT; > > if cnt_v = 0 then > cmd_v := CONVERT; > state_v := SEND_CMD; > inc_tic_count; > elsif cnt_v = WAIT_CONVERSION_TIME then > dat_v := GET_DATA; > state_v := SEND_DATA; > inc_tic_count; > elsif cnt_v = WAIT_CONVERSION_TIME+1 then > cnt_v := 1; > if DATA_v = x"FF" then > cnt_v := 0; > mstate_v := SEND_SKIP_ROM; > lstate_v := SEND_READ_SCRATCH; > state_v := SEND_RESET; > end if; > else > inc_tic_count; > end if; > > ------------------------------------------------------------------------------- > > when SEND_READ_SCRATCH => > mstate_v := SEND_READ_SCRATCH; > -- read data after the first SEND_DATA is over (cnt_v = 2) > if cnt_v > 1 then > temp_value_v(cnt_v - 2) := DATA_v; > end if; > > if cnt_v = 0 then > cmd_v := READ_SCRATCH; > state_v := SEND_CMD; > inc_tic_count; > elsif cnt_v <= 2 then > dat_v := GET_DATA; > state_v := SEND_DATA; > inc_tic_count; > else > inc_tem_count; > temp_valid_v := '1'; > cnt_v := 0; > mstate_v := SEND_SKIP_ROM; > lstate_v := SEND_CONVERT; > state_v := SEND_RESET; > end if; > > when others => null; > end case; > else > state_v := IDLE; > end if; > end procedure autoread; > > ------------------------------------------------------------------------------- > procedure update_regs is > begin -- purpose: call the procedures above in the desired order > autoread; > end procedure update_regs; > > ------------------------------------------------------------------------------- > -- Synchronous Templates for Synthesis: The following templates use > -- all of the declarations above to make a UART. With other > -- declarations, the template could make anything else. Relative > -- synthesis performance will be compared below for each template. > -- If I were not making comparisons, the first template would be > -- pasted into the main process. > ------------------------------------------------------------------------------- > procedure template_v_rst is > begin -- a_rst is logically equivalent > if RST = '1' then -- Assumes synched trailing edge RST pulse > init_regs; -- reg_v := init_c; Variables only, ports below. > elsif rising_edge(CLK) then > update_regs; -- reg_v := f(reg_v);Variables only, ports below. > end if; -- Synchronous init optional (state_v = idle_c) > update_ports; -- will infer port wires ok for RST and CLK > end procedure template_v_rst; -- out_port <= reg_v; ports only, no signals > > ------------------------------------------------------------------------------- > begin -- process main > template_v_rst; > end process main; > > ------------------------------------------------------------------------------- > > end tfsm_arch; From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 23 Sep 2013 09:20:50 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Sep 2013 13:20:55 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1f290bac804f6cd54e3c0a5f7ad6fb70"; logging-data="10295"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX195FvUqdG4dUEYjYxxmratb" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:C+ZNIsKV4L8H1XsBHSP9i+lWr/g= Xref: news.eternal-september.org comp.lang.vhdl:7049 On 9/23/2013 4:03 AM, alb wrote: > nRD_v := not nRD_v; Is this your culpret? I didn't read all your code because of the volume, but if nRD_v is not registered, this statement creates a latch. You seem to understand this stuff pretty well, so it puzzles me that you missed this. Or is there something else I didn't catch about your code? -- Rick From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 23 Sep 2013 16:34:02 +0200 Lines: 84 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net FJsFQM56Ahwd9WhYmONYPwRlC7ZkYDrr5hZ8m5CProkQqH+PhK Cancel-Lock: sha1:iXzdtYDl5t4SEkU/+hQ4CU+7vIQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7050 On 23/09/2013 15:20, rickman wrote: > On 9/23/2013 4:03 AM, alb wrote: >> nRD_v := not nRD_v; > > Is this your culpret? Not really, considering the way the procedure is called (in update_regs) it will be like doing: process (clk, rst) begin if rst = '1' then nRD_s <= '1'; -- nRD_s is a signal instead of a variable elsif rising_edge(clk) then if then nRD_s <= not nRD_s; end if; end if; end process; Indeed even if I change the previous variable assignment to the following: nRD_v := '0'; -- or '1' according to conditions the P&R still complains for combinational loops. Variables can be used to infer flip-flop just as well as signals. I like the following code example (from Martin Thompson): > process (clk) > variable something : std_logic; > if rising_edge(clk) then > if reset = '1' then > something := '0'; > else > output_b <= something or input c; -- using the previous clock's value of 'something' infers a register > something := input_a and input_b; -- comb. logic for a new value > output_a <= something or input_c; -- which is used immediately, not registered here > end if; > end if; > end process; > I didn't read all your code because of the volume, but if nRD_v is not > registered, this statement creates a latch. I can imagine, that was the reason why I didn't want to post it all in the first place. A latch is inferred if you write a process where an output is not assigned under all possible input conditions: process (clk, rst) begin if rst = '1' then nRD_s <= '1'; -- nRD_s is a signal instead of a variable foo_s <= nRD_s; -- foo_s is not assigned under all possible inputs -- of the process therefore a latch is needed to -- retain its value. elsif rising_edge(clk) then if then nRD_s <= not nRD_s; end if; end if; end process; So my code should not infer a latch (and indeed it does not). > > You seem to understand this stuff pretty well, so it puzzles me that you > missed this. Or is there something else I didn't catch about your code? Believe me, if I knew this stuff 'pretty well' I won't be asking ;-). I'm actually exploring the usage of variables to a greater extent, together with a new 'procedural' approach and I'm afraid I'm misusing it somehow. Funny enough the code simulates just as I want it, maybe I've only been lucky... From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 23 Sep 2013 11:11:43 -0400 Organization: A noiseless patient Spider Lines: 128 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Sep 2013 15:11:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1f290bac804f6cd54e3c0a5f7ad6fb70"; logging-data="20229"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GjuR+9Lw0J3zrA88N0tmK" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:qBedPtJXBsNDNedp9DQoA9k/JtI= Xref: news.eternal-september.org comp.lang.vhdl:7051 On 9/23/2013 10:34 AM, alb wrote: > On 23/09/2013 15:20, rickman wrote: >> On 9/23/2013 4:03 AM, alb wrote: >>> nRD_v := not nRD_v; >> >> Is this your culpret? > > Not really, considering the way the procedure is called (in update_regs) > it will be like doing: > > > process (clk, rst) > begin > if rst = '1' then > nRD_s<= '1'; -- nRD_s is a signal instead of a variable > elsif rising_edge(clk) then > if then > nRD_s<= not nRD_s; > end if; > end if; > end process; > > > Indeed even if I change the previous variable assignment to the following: > > nRD_v := '0'; -- or '1' according to conditions > > the P&R still complains for combinational loops. > Variables can be used to infer flip-flop just as well as signals. I like > the following code example (from Martin Thompson): > > >> process (clk) >> variable something : std_logic; >> if rising_edge(clk) then >> if reset = '1' then >> something := '0'; >> else >> output_b<= something or input c; -- using the previous clock's value of 'something' infers a register >> something := input_a and input_b; -- comb. logic for a new value >> output_a<= something or input_c; -- which is used immediately, not registered here >> end if; >> end if; >> end process; > > >> I didn't read all your code because of the volume, but if nRD_v is not >> registered, this statement creates a latch. > > I can imagine, that was the reason why I didn't want to post it all in > the first place. But if you omit the full code, you can't expect anyone to even begin finding the problem, too many possibilities. > A latch is inferred if you write a process where an output is not > assigned under all possible input conditions: > > > process (clk, rst) > begin > if rst = '1' then > nRD_s<= '1'; -- nRD_s is a signal instead of a variable > foo_s<= nRD_s; -- foo_s is not assigned under all possible inputs > -- of the process therefore a latch is needed to > -- retain its value. > elsif rising_edge(clk) then > if then > nRD_s<= not nRD_s; > end if; > end if; > end process; > > > So my code should not infer a latch (and indeed it does not). Your premise is not complete. A latch is inferred as well if you create a feedback loop. nRD_v := not nRD_v; creates feedback if it is not registered. It appears it should be registered however. So the questions are, 1) Is it registered? 2) If it is registered, how is the message being generated? 3) If it is not registered, why? BTW, you *don't* assign a value to nRD_v under all conditions. when IDLE => cnt_v := 0; state_v := SET_CLKRATE; when READ_BGN => state_v := READ_END; -- this is one clock cycle nRD_v := not nRD_v; So if nRD_v is not registered, it will be a latch anyway. You need to focus on why nRD_v is not registered I would say. >> You seem to understand this stuff pretty well, so it puzzles me that you >> missed this. Or is there something else I didn't catch about your code? > > Believe me, if I knew this stuff 'pretty well' I won't be asking ;-). > I'm actually exploring the usage of variables to a greater extent, > together with a new 'procedural' approach and I'm afraid I'm misusing it > somehow. Yes, I have never used variables so much myself. That's why I missed that nRD_v was a variable. I missed both the := and the _v ... duh! I also don't use procedures so much. I should try to work with them more so I understand them better. There are times when they are useful for decomposition of code into reusable modules. > Funny enough the code simulates just as I want it, maybe I've only been > lucky... *Something* is amiss. Has this error message been generated all along? If not, see what you changed. If it has I would say simplify the code to something that doesn't give the error and figure out what is different. -- Rick From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 23 Sep 2013 11:22:39 -0400 Organization: A noiseless patient Spider Lines: 526 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Sep 2013 15:22:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1f290bac804f6cd54e3c0a5f7ad6fb70"; logging-data="24358"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hurbTrUXf/HbUyZy59MV7" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:i4DujoPhvCusAdJZW3mB+2pQwA0= Xref: news.eternal-september.org comp.lang.vhdl:7052 Ok, timeout! This is the first time you have compiled the code isn't it? So you have not done any testing on the code at all so far? Where are your parameter lists for the procedures such as update_ports? Rick On 9/23/2013 4:03 AM, alb wrote: > On 20/09/2013 22:56, rickman wrote: > [see end of this post for the entire code] >> >> I'm not very happy with the way you have separated the register code >> from the output code. For example the procedure autoread is invoked >> from the registered section of the clocked process. This means any >> signals assigned a value in this procedure will be registered. > > I do not have signals, I have only variables and they are synthesized to > registers or wires according to whether they need to retain a value or not. > >> The last line shown in this procedure assigns a high impedance value to >> what I assume is a signal, that's not realizable, or at least it isn't >> the way I would do it. > > The DATA_v variable is not the main issue here, I'm concerned about > combinational loops on nRD_v and nWR_v. > OT, on the 'Z' assignment, it is clear that while internal resources of > an FPGA do not provide tri-state logic, they can easily be transformed > to a set of multiplexers which logically provide the same functionality. > > It is clear that no condition should exist for multiple drivers on the > line. On a side note, shouldn't be better to use std_ulogic_vector to > spot multiple drivers on the bus instead of std_logic_vector? I'm > naively assuming that an unresolved type would help me spotting multiple > drivers at compilation time... > >> >> Unless you show us all your code it will be hard to pin point your >> combinatorial loop. The problem is most likely in init_regs or >> update_ports as these are not registered. > > I believe that not posting the whole code was a bad idea so it follows > at the end of this post, but let me add that init_regs does not mean > they are 'not registered'. The clocked process has an asynchronous reset > which triggers the 'initialization' of everything needs to be > initialized, while the update_ports only 'connects' the variables to the > entity ports (no register involved here). > > While I cannot be 100% sure that the problem is in the snippet I > previously posted, I'm quite confident that the rest of the code should > not play an important role. In 'pkg_temp' there are some constant > definitions only. > > >> library ieee; >> use ieee.std_logic_1164.all; >> use ieee.std_logic_unsigned.all; >> use ieee.numeric_std.all; >> >> library work; >> use work.pkg_temp.all; >> >> ------------------------------------------------------------------------------- >> >> entity tfsm is >> port ( >> ADD_i : in std_logic_vector(2 downto 0); >> nRD_i : in std_logic; >> nWR_i : in std_logic; >> ADD_o : out std_logic_vector(2 downto 0); >> nRD_o : out std_logic; >> nWR_o : out std_logic; >> DATA : inout std_logic_vector(7 downto 0); >> TEMP : out std_logic_vector(15 downto 0); >> SRNO : out std_logic_vector(63 downto 0); >> ST : in std_logic; >> CLK : in std_logic; >> RST : in std_logic); >> >> end tfsm; >> >> ------------------------------------------------------------------------------- >> >> architecture tfsm_arch of tfsm is >> -- Note: No signal declarations. >> begin -- tfsm_arch >> >> main : process (CLK, RST) is >> ------------------------------------------------------------------------------- >> type state_t is ( >> SET_CLKRATE, >> SET_CTRLREG, >> CLR_INTREG, >> SET_INEREG, >> SEND_READ_ROM, >> SEND_SKIP_ROM, >> SEND_WRITE_SCRATCHPAD, >> SEND_CONVERT, >> SEND_READ_SCRATCH, >> >> -- reusable states >> SEND_RESET, >> TEST_PRESENCE, >> >> SEND_CMD, >> TEST_CMD, >> >> SEND_DATA, >> TEST_DATA, >> >> WRITE_BGN, >> WRITE_END, >> >> READ_BGN, >> READ_END, >> IDLE >> ); >> >> variable state_v : state_t; -- current state >> variable nstate_v : state_t; -- next state after write/read >> variable mstate_v : state_t; -- next state after macro command >> variable lstate_v : state_t; -- next state after skip rom >> >> variable cmd_v : integer; -- command to send >> variable dat_v : integer; -- data to send >> variable cnt_v : integer; -- counter >> >> ------------------------------------------------------------------------------- >> -- Data Registers >> subtype bus_t is std_logic_vector(DATA'range); -- match port width >> variable DATA_v : bus_t; >> >> -- Address registers >> subtype add_t is std_logic_vector(ADD_i'range); -- match port width >> variable ADD_v : add_t; >> >> -- control wires >> subtype ctr_t is std_logic; >> variable nRD_v : ctr_t; >> variable nWR_v : ctr_t; >> >> -- sensor id type >> type sens_t is array (7 downto 0) of std_logic_vector (7 downto 0); >> >> -- sensor temperature type >> type temp_t is array (1 downto 0) of std_logic_vector (7 downto 0); >> >> -- scratchpad type >> type scratch_t is array (2 downto 0) of integer; >> >> -- temperature registers >> -- temp_count_v: will count each time there's a new temperature available >> -- temp_valid_v: will be set to one when ID AND first temperature readout >> -- are both valid >> >> variable temp_count_v : std_logic_vector(2 downto 0); >> variable temp_valid_v : std_logic; >> variable temp_value_v : temp_t; >> >> -- sensor id register >> variable sens_id_v : sens_t; >> >> -- scratchpad register >> variable scratchpad_v : scratch_t; >> >> ------------------------------------------------------------------------------- >> procedure bus_init is -- used in init_regs >> begin >> DATA_v := (others => 'Z'); >> ADD_v := (others => '0'); >> nRD_v := '1'; -- inactive >> nWR_v := '1'; -- inactive >> >> temp_count_v := "000"; >> temp_valid_v := '0'; >> temp_value_v(0) := x"00"; >> temp_value_v(1) := x"00"; >> >> sens_id_v(0) := x"28"; -- for test only >> sens_id_v(1) := x"DE"; -- for test only >> sens_id_v(2) := x"D5"; -- for test only >> sens_id_v(3) := x"45"; -- for test only >> sens_id_v(4) := x"03"; -- for test only >> sens_id_v(5) := x"00"; -- for test only >> sens_id_v(6) := x"00"; -- for test only >> sens_id_v(7) := x"C0"; -- crc >> >> end procedure bus_init; >> >> ------------------------------------------------------------------------------- >> procedure fsm_init is -- used in init_regs >> begin >> state_v := IDLE; >> nstate_v := IDLE; >> mstate_v := IDLE; >> lstate_v := IDLE; >> >> cmd_v := 0; >> cnt_v := 0; >> dat_v := 0; >> >> scratchpad_v (0) := 40; -- x"28" -> +40 degrees >> scratchpad_v (1) := 226; -- x"E2" -> -30 degrees >> scratchpad_v (2) := 127; -- x"7F" -> I have no idea! >> end procedure fsm_init; >> >> ------------------------------------------------------------------------------- >> procedure init_regs is >> begin >> bus_init; >> fsm_init; >> end procedure init_regs; >> >> ------------------------------------------------------------------------------- >> procedure update_ports is >> begin -- purpose: synthesize a wire from the register to the port >> >> -- ST is a register bit that allows start/stop of the automatic >> -- temperature readout procedure. It is set in the control register of >> -- the DS1WM and propagated up to here (see one_wire_interface.vhd) >> >> mux : if ST then >> DATA<= DATA_v; >> nRD_o<= nRD_v; >> nWR_o<= nWR_v; >> ADD_o<= ADD_v; >> else >> DATA<= (others => 'Z'); >> nRD_o<= nRD_i; >> nWR_o<= nWR_i; >> ADD_o<= ADD_i; >> end if; >> >> TEMP<= temp_count_v& >> temp_valid_v& >> temp_value_v(1)(3 downto 0)& >> temp_value_v(0); >> >> sensor_id : for i in 0 to 7 loop >> SRNO(8*(i+1)-1 downto 8*i)<= sens_id_v(i); >> end loop sensor_id; >> >> end procedure update_ports; >> ------------------------------------------------------------------------------- >> procedure autoread is >> -- local procedures for statements used more than once: >> procedure write_ds1wm ( >> add : in add_t; >> val : in integer) is >> begin >> state_v := WRITE_BGN; >> ADD_v := add; >> DATA_v := std_logic_vector(to_unsigned(val, DATA_v'length)); >> end write_ds1wm; >> -- >> procedure read_ds1wm ( >> add : in add_t) is >> begin >> state_v := READ_BGN; >> ADD_v := add; >> DATA_v := (others => 'Z'); >> end read_ds1wm; >> >> procedure inc_tic_count is >> begin >> cnt_v := cnt_v + 1; >> end procedure inc_tic_count; >> >> procedure inc_tem_count is >> begin >> temp_count_v := temp_count_v + '1'; >> end procedure inc_tem_count; >> >> begin -- procedure autoread >> if ST then >> case state_v is >> when IDLE => >> cnt_v := 0; >> state_v := SET_CLKRATE; >> >> ------------------------------------------------------------------------------- >> -- Write and Read states are special ones since they are called several times >> -- by every other state, it is therefore necessary to store the value of the >> -- next state once the write/read steps have been completed, in order to >> -- continue with the fsm. >> ------------------------------------------------------------------------------- >> when READ_BGN => >> state_v := READ_END; -- this is one clock cycle >> nRD_v := not nRD_v; >> when READ_END => >> state_v := nstate_v; >> nRD_v := not nRD_v; >> DATA_v := DATA; >> when WRITE_BGN => >> state_v := WRITE_END; -- this is one clock cycle >> nWR_v := not nWR_v; >> when WRITE_END => >> state_v := nstate_v; >> nWR_v := not nWR_v; >> DATA_v := (others => 'Z'); -- release the bus >> >> ------------------------------------------------------------------------------- >> -- Init part for the DS1WM. Set clock rate, control register, clean >> -- interrupt register and configure interrupt enable register >> ------------------------------------------------------------------------------- >> when SET_CLKRATE => >> nstate_v := SET_CTRLREG; >> write_ds1wm(CLKREG, 138); -- clock enabled + 20 MHz >> when SET_CTRLREG => >> nstate_v := CLR_INTREG; >> write_ds1wm(CTLREG, 2**STB); -- keep STB active! >> when CLR_INTREG => >> nstate_v := SET_INEREG; >> read_ds1wm(INFREG); >> when SET_INEREG => >> nstate_v := SEND_RESET; >> mstate_v := SEND_READ_ROM; >> write_ds1wm(INEREG, 2**EPD + 2**ETBE + 2**ERBF); >> >> ------------------------------------------------------------------------------- >> -- Start DS1WM transactions with a 1wire reset. Each 1-wire transaction has >> -- always three phases: >> -- 1. initialization (RESET) >> -- 2. ROM command >> -- 3. FUNCTION command >> ------------------------------------------------------------------------------- >> >> when SEND_RESET => >> nstate_v := TEST_PRESENCE; >> write_ds1wm(CMDREG, 2**OneWR); >> >> when TEST_PRESENCE => >> -- we should foresee a timeout...!!! >> if DATA_v(PD) and not DATA_v(PDR) then >> state_v := mstate_v; >> else >> nstate_v := state_v; >> read_ds1wm(INFREG); >> end if; >> >> ------------------------------------------------------------------------------- >> -- SEND command cmd_v. This sequence of states is referenced as a 'macro' as it >> -- will depend on the mstate_v defined by the calling state. >> ------------------------------------------------------------------------------- >> when SEND_CMD => >> nstate_v := TEST_CMD; >> write_ds1wm(DATBUF, cmd_v); >> >> when TEST_CMD => >> -- we should foresee a timeout...!!! >> if DATA_v(RBF) then >> nstate_v := mstate_v; >> read_ds1wm(DATBUF); -- empty data buffer! >> else >> nstate_v := state_v; >> read_ds1wm(INFREG); >> end if; >> >> ------------------------------------------------------------------------------- >> -- Read cnt_v data times to register. This sequence of states is references as >> -- a 'macro' as it will depend on the mstate_v defined by the calling state. >> ------------------------------------------------------------------------------- >> >> when SEND_DATA => >> nstate_v := TEST_DATA; >> write_ds1wm(DATBUF, dat_v); >> >> when TEST_DATA => >> -- we should foresee a timeout...!!! >> if DATA_v(RBF) then >> nstate_v := mstate_v; >> read_ds1wm(DATBUF); >> else >> nstate_v := state_v; >> read_ds1wm(INFREG); >> end if; >> >> ------------------------------------------------------------------------------- >> >> when SEND_READ_ROM => >> mstate_v := SEND_READ_ROM; >> -- read data after the first SEND_DATA is over (cnt_v = 2) >> if cnt_v> 1 then >> sens_id_v(cnt_v - 2) := DATA_v; >> end if; >> >> if cnt_v = 0 then >> cmd_v := READ_ROM; >> state_v := SEND_CMD; >> inc_tic_count; >> elsif cnt_v<= 8 then >> dat_v := GET_DATA; >> state_v := SEND_DATA; >> inc_tic_count; >> else >> cnt_v := 0; >> state_v := SEND_WRITE_SCRATCHPAD; >> end if; >> >> ------------------------------------------------------------------------------- >> >> when SEND_WRITE_SCRATCHPAD => >> mstate_v := SEND_WRITE_SCRATCHPAD; >> if cnt_v = 0 then >> cmd_v := WRITE_SCRATCH; >> state_v := SEND_CMD; >> inc_tic_count; >> elsif cnt_v<= 3 then >> dat_v := scratchpad_v(cnt_v - 1); >> state_v := SEND_DATA; >> inc_tic_count; >> else >> cnt_v := 0; >> mstate_v := SEND_SKIP_ROM; >> lstate_v := SEND_CONVERT; >> state_v := SEND_RESET; >> end if; >> >> ------------------------------------------------------------------------------- >> >> when SEND_SKIP_ROM => >> cmd_v := SKIP_ROM; >> state_v := SEND_CMD; >> mstate_v := lstate_v; >> >> ------------------------------------------------------------------------------- >> >> when SEND_CONVERT => >> mstate_v := SEND_CONVERT; >> >> if cnt_v = 0 then >> cmd_v := CONVERT; >> state_v := SEND_CMD; >> inc_tic_count; >> elsif cnt_v = WAIT_CONVERSION_TIME then >> dat_v := GET_DATA; >> state_v := SEND_DATA; >> inc_tic_count; >> elsif cnt_v = WAIT_CONVERSION_TIME+1 then >> cnt_v := 1; >> if DATA_v = x"FF" then >> cnt_v := 0; >> mstate_v := SEND_SKIP_ROM; >> lstate_v := SEND_READ_SCRATCH; >> state_v := SEND_RESET; >> end if; >> else >> inc_tic_count; >> end if; >> >> ------------------------------------------------------------------------------- >> >> when SEND_READ_SCRATCH => >> mstate_v := SEND_READ_SCRATCH; >> -- read data after the first SEND_DATA is over (cnt_v = 2) >> if cnt_v> 1 then >> temp_value_v(cnt_v - 2) := DATA_v; >> end if; >> >> if cnt_v = 0 then >> cmd_v := READ_SCRATCH; >> state_v := SEND_CMD; >> inc_tic_count; >> elsif cnt_v<= 2 then >> dat_v := GET_DATA; >> state_v := SEND_DATA; >> inc_tic_count; >> else >> inc_tem_count; >> temp_valid_v := '1'; >> cnt_v := 0; >> mstate_v := SEND_SKIP_ROM; >> lstate_v := SEND_CONVERT; >> state_v := SEND_RESET; >> end if; >> >> when others => null; >> end case; >> else >> state_v := IDLE; >> end if; >> end procedure autoread; >> >> ------------------------------------------------------------------------------- >> procedure update_regs is >> begin -- purpose: call the procedures above in the desired order >> autoread; >> end procedure update_regs; >> >> ------------------------------------------------------------------------------- >> -- Synchronous Templates for Synthesis: The following templates use >> -- all of the declarations above to make a UART. With other >> -- declarations, the template could make anything else. Relative >> -- synthesis performance will be compared below for each template. >> -- If I were not making comparisons, the first template would be >> -- pasted into the main process. >> ------------------------------------------------------------------------------- >> procedure template_v_rst is >> begin -- a_rst is logically equivalent >> if RST = '1' then -- Assumes synched trailing edge RST pulse >> init_regs; -- reg_v := init_c; Variables only, ports below. >> elsif rising_edge(CLK) then >> update_regs; -- reg_v := f(reg_v);Variables only, ports below. >> end if; -- Synchronous init optional (state_v = idle_c) >> update_ports; -- will infer port wires ok for RST and CLK >> end procedure template_v_rst; -- out_port<= reg_v; ports only, no signals >> >> ------------------------------------------------------------------------------- >> begin -- process main >> template_v_rst; >> end process main; >> >> ------------------------------------------------------------------------------- >> >> end tfsm_arch; > > > > -- Rick From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.2.68 with SMTP id 4mr10652666qai.1.1379954687307; Mon, 23 Sep 2013 09:44:47 -0700 (PDT) X-Received: by 10.182.29.196 with SMTP id m4mr22566obh.2.1379954687267; Mon, 23 Sep 2013 09:44:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1558911qap.0!news-out.google.com!gv3ni1252qab.0!nntp.google.com!d5no1631011qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Sep 2013 09:44:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> Subject: Re: combinational loops From: Andy Injection-Date: Mon, 23 Sep 2013 16:44:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7053 Al, I have had problems in synthesis (synplify pro) when calling the same proce= dure under multiple conditions (e.g. states in a state machine) from a cloc= ked process.=20 Synthesizer did not complain, but the HW did not work, and the post-synth n= etlist simulation did not match the RTL simulation. The post-synth simulati= on was consistent with behavior observed in the lab (we could not observe t= he exact failure in the lab, but the overall results were consistent). P&R = STA passed with no errors/warnings. To work around it, I created a variable flag that was set anytime I needed = to run the procedure, then below the fsm code (in the same clocked process = or update_regs procedure in your case), I called the procedure within an if= -statement when the flag was set. Note that since the flag was written ever= y clock cycle before read to determine whether to run the procedure, the fl= ag was combinatorial, and the procedure ran in the same clock cycle that se= t the flag. I have not tried to create a boiled-down test case to submit to Synopsys ye= t. My procedure used an inout variable parameter, and updated a CRC checksu= m based on data provided in the procedure call. Updating an inout variable = parameter would behave identically to updating an external (but in-scope) v= ariable. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:10 2015 X-Received: by 10.224.51.68 with SMTP id c4mr1995865qag.7.1379955076434; Mon, 23 Sep 2013 09:51:16 -0700 (PDT) X-Received: by 10.182.44.198 with SMTP id g6mr9900obm.35.1379955076281; Mon, 23 Sep 2013 09:51:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1559557qap.0!news-out.google.com!gv3ni1252qab.0!nntp.google.com!d5no1631786qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Sep 2013 09:51:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> Subject: Re: combinational loops From: Mike Treseler Injection-Date: Mon, 23 Sep 2013 16:51:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7054 On Friday, September 20, 2013 3:42:31 AM UTC-7, alb wrote: > > It sim'ed ok, both pre/post-synthesis and post-layout. In an init,update,output single process design using variables, you can ignore warnings about variable reuse if synthesis completes without error and sim is ok. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 24 Sep 2013 09:32:07 +0200 Lines: 31 Message-ID: References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 59iOFlpFgEkHSU5wc4fHugath27JyTHQ/8BHa6tzJt6ZsPZlg+ Cancel-Lock: sha1:953B47GzASmoWFDiLd47yFUSRgA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7055 Hi Mike, On 23/09/2013 18:51, Mike Treseler wrote: > On Friday, September 20, 2013 3:42:31 AM UTC-7, alb wrote: >>> It sim'ed ok, both pre/post-synthesis and post-layout. > > > In an init,update,output single process design using variables, > you can ignore warnings about variable reuse if synthesis completes without error and sim is ok. there are a couple of things that do not make me feel happy even if sim is ok: 1. the amount of logic inferred is exceeding my predictions (this is just an FSM with some registers and a couple of counters and it takes 12% of a 250k gates FPGA!). 2. in the lab it does not work. Concerning 1. I'll need to investigate the RTL and see if there's something wrong going on (the Synplify Pro RTL viewer should be sufficient to do so). About 2., this is an FSM to read out a 1-wire bus in an infinite loop and I believe that at power up the 'Reset' on the 1-wire is sent too early (the line is still not stable at 'H') and the presence pulse is not sampled properly, causing the FSM to loop indefinitely in a state waiting for the presence bit to show up. I think this can be easily fixed waiting for the line to be stable first. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 24 Sep 2013 10:19:58 +0200 Lines: 101 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net II+xpois7mOx/CZECmlFfAmhlb2TxfB0OqZFtRj68+6CGRUArV Cancel-Lock: sha1:u8AylJ1VyNEII/jUB/wKMDWb2GU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7056 On 23/09/2013 17:11, rickman wrote: [] >> A latch is inferred if you write a process where an output is not >> assigned under all possible input conditions: >> >> >> process (clk, rst) >> begin >> if rst = '1' then >> nRD_s<= '1'; -- nRD_s is a signal instead of a variable >> foo_s<= nRD_s; -- foo_s is not assigned under all possible inputs >> -- of the process therefore a latch is needed to >> -- retain its value. >> elsif rising_edge(clk) then >> if then >> nRD_s<= not nRD_s; >> end if; >> end if; >> end process; >> >> >> So my code should not infer a latch (and indeed it does not). > > Your premise is not complete. A latch is inferred as well if you create > a feedback loop. nRD_v := not nRD_v; creates feedback if it is not > registered. On a clocked process the assignment you quote is perfectly legal and does not create any latch (it may still create a feedback mux if nRD_v is not reset). > It appears it should be registered however. So the > questions are, > > 1) Is it registered? yes > > 2) If it is registered, how is the message being generated? Assuming the message you refer to is the OP's note issued by Designer, that is an unfair question to ask since I asked it first ;-) > BTW, you *don't* assign a value to nRD_v under all conditions. > > when IDLE => > cnt_v := 0; > state_v := SET_CLKRATE; > when READ_BGN => > state_v := READ_END; -- this is one clock cycle > nRD_v := not nRD_v; I know the code is a bit long to go through, but the 'autorun' procedure is executed during 'update_reg', which is called in the 'if rising_edge(clk)' branch of the -only - process. The variable is also properly initialized in bus_init, called during init_regs, in the 'other' branch of the clocked process. Therefore the variable nRD_v *is* assigned under all possible conditions which will trigger the process to run. [] >> Believe me, if I knew this stuff 'pretty well' I won't be asking ;-). >> I'm actually exploring the usage of variables to a greater extent, >> together with a new 'procedural' approach and I'm afraid I'm misusing it >> somehow. > > Yes, I have never used variables so much myself. That's why I missed > that nRD_v was a variable. I missed both the := and the _v ... duh! I keep the _v reminder in the name which may seem redundant since it is clear that I cannot assign a variable with a non-blocking assignment. But generally I tend to use no reminders for the entity ports to increase readability and therefore I find it natural to use the _v internally. > I also don't use procedures so much. I should try to work with them > more so I understand them better. There are times when they are useful > for decomposition of code into reusable modules. After having been contaminated by software development for three years I started to see the power of using subprograms and IMO VHDL has all the language constructs to allow a high level of abstraction, resulting in fewer lines of code (-> less bugs [1]), greater readability and reuse. > >> Funny enough the code simulates just as I want it, maybe I've only been >> lucky... > > *Something* is amiss. Has this error message been generated all along? > If not, see what you changed. If it has I would say simplify the code > to something that doesn't give the error and figure out what is different. I can indeed start to remove bits and pieces to see what really fools the tool, but I'm not happy about the flow. How can it be that only the P&R has noticed the combinational loop? [1] Halstead, Maurice H. (1977). Elements of Software Science. Amsterdam: Elsevier North-Holland, Inc. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 24 Sep 2013 10:29:48 +0200 Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net xSdjMaSdfvn4tbUZM76ZLwldxovLRWdDy0vJJWW8/rRBhvM6pa Cancel-Lock: sha1:B7f9q4evIJUIyJtOe6tREZl5hcE= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7057 Hi Rick, On 23/09/2013 17:22, rickman wrote: [] > This is the first time you have compiled the code isn't it? So you have > not done any testing on the code at all so far? As I mentioned in the beginning the code has been sim'ed and it works properly in post-synth and post-layout (even though STA shows timing violations on unrelated parts of the code). Unfortunately it does not work in the lab, but I think is more related to the power-up rather than a functional problem (at power-up the 1-wire line is pulled 'H' through a pull-up resistor and the sequence to talk on the line starts too early). > Where are your parameter lists for the procedures such as update_ports? No parameter lists. All variables have global scope in the process. This is indeed something I do not completely like about this approach since I haven't found a way to 'protect' the access to variables and you may end up with variable assignments all scattered, killing the benefit of subprogram partitioning. From newsfish@newsfish Tue Dec 29 16:43:10 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 24 Sep 2013 10:56:25 +0200 Lines: 68 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net nddNUWsLUjNCikS4wdPvGgihrHbT6ZrLUlDf8kSklqpWex2OXf Cancel-Lock: sha1:tIZJ4vKYyAYZtjGO/n7NPYVVaIs= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7058 Hi Andy, On 23/09/2013 18:44, Andy wrote: [] > I have had problems in synthesis (synplify pro) when calling the same > procedure under multiple conditions (e.g. states in a state machine) > from a clocked process. This is no good news! :-/ > Synthesizer did not complain, but the HW did not work, and the > post-synth netlist simulation did not match the RTL simulation. The > post-synth simulation was consistent with behavior observed in the > lab (we could not observe the exact failure in the lab, but the > overall results were consistent). P&R STA passed with no > errors/warnings. The HW does not work for me as well, but I'm afraid for a different reason. Conversely to your case, my code sim ok, post-synth and post-layout. P&R STA reports issues but on a different part of the design. What about the RTL viewer? Did it show something reasonable or not? > To work around it, I created a variable flag that was set anytime I > needed to run the procedure, then below the fsm code (in the same > clocked process or update_regs procedure in your case), I called the > procedure within an if-statement when the flag was set. Note that > since the flag was written every clock cycle before read to determine > whether to run the procedure, the flag was combinatorial, and the > procedure ran in the same clock cycle that set the flag. something similar to this: -- declarative part of global variables: variable flag: std_logic; -- ... ------------------------------------------------------------------------------- procedure update_regs is begin -- purpose: call the procedures above in the desired order if flag then autoread; flag := '0'; -- reset flag. end if; end procedure update_regs; ------------------------------------------------------------------------------- procedure template_v_rst is begin -- a_rst is logically equivalent if RST = '1' then init_regs; elsif rising_edge(CLK) then flag := '1'; -- set flag. update_regs; end if; update_ports; end procedure template_v_rst; -- ... I'll try it and post results. > > I have not tried to create a boiled-down test case to submit to > Synopsys yet. I'll see what I can come up with, but I'm a bit under pressure to complete and I'm not sure I'll have the time to find a test case. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 24 Sep 2013 14:55:26 +0200 Lines: 28 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 3KS35BYgSqqUXzlHdcs5tQGCxiPmF5GC31DTjv8aOgU8Cj2oBn Cancel-Lock: sha1:9+6nd0uSf7COq4igoWcOR/8PdN4= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7059 This is a correction to my previous post. On 24/09/2013 10:19, alb wrote: [] >> BTW, you *don't* assign a value to nRD_v under all conditions. >> >> when IDLE => >> cnt_v := 0; >> state_v := SET_CLKRATE; >> when READ_BGN => >> state_v := READ_END; -- this is one clock cycle >> nRD_v := not nRD_v; > > I know the code is a bit long to go through, but the 'autorun' procedure > is executed during 'update_reg', which is called in the 'if > rising_edge(clk)' branch of the -only - process. > > The variable is also properly initialized in bus_init, called during > init_regs, in the 'other' branch of the clocked process. Therefore the > variable nRD_v *is* assigned under all possible conditions which will > trigger the process to run. You are right, the variable nRD_v *is not* assigned under all possible branches, but it is assigned in a clocked process therefore is synthesized to a dff. Sorry for the confusion. From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.97.1 with SMTP id j1mr7273967qan.6.1380038951600; Tue, 24 Sep 2013 09:09:11 -0700 (PDT) X-Received: by 10.182.237.13 with SMTP id uy13mr130300obc.4.1380038951568; Tue, 24 Sep 2013 09:09:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1680013qap.0!news-out.google.com!9ni111qaf.0!nntp.google.com!d5no1758246qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Sep 2013 09:09:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> Subject: Re: combinational loops From: Mike Treseler Injection-Date: Tue, 24 Sep 2013 16:09:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7060 On Tuesday, September 24, 2013 12:32:07 AM UTC-7, alb wrote: > > there are a couple of things that do not make me feel happy even if sim > is ok: > 1. the amount of logic inferred is exceeding my predictions (this is > just an FSM with some registers and a couple of counters and it takes > 12% of a 250k gates FPGA!). Have a look on the rtl viewer. Some variable array is too large or some block ram does not fit the device. If you don't have a viewer, start out with the free quartus tools. > 2. in the lab it does not work. Start with with just the reset procedure check the reset pulse and all static outputs. Add a clock and counter and check that. etc. > Concerning 1. I'll need to investigate the RTL and see if there's > something wrong going on (the Synplify Pro RTL viewer should be > sufficient to do so). I never go near the bench until the RTL view is as expected. > About 2., this is an FSM to read out a 1-wire bus in an infinite loop > and I believe that at power up the 'Reset' on the 1-wire is sent too > early (the line is still not stable at 'H') and the presence pulse is > not sampled properly, causing the FSM to loop indefinitely in a state > waiting for the presence bit to show up. I think this can be easily > fixed waiting for the line to be stable first. I would read a burst at at time and check sims that the bus port has Z,1,0 at the right times. Good Luck, -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.96.136 with SMTP id h8mr1343824qan.8.1380043261614; Tue, 24 Sep 2013 10:21:01 -0700 (PDT) X-Received: by 10.49.13.10 with SMTP id d10mr152522qec.28.1380043261590; Tue, 24 Sep 2013 10:21:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1766278qap.0!news-out.google.com!9ni111qaf.0!nntp.google.com!d5no1766277qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Sep 2013 10:21:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Subject: Re: combinational loops From: Andy Injection-Date: Tue, 24 Sep 2013 17:21:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7061 Al,=20 I think you need flags to control calling the sub-procedures within autorea= d, not calling autoread itself. It looks like you would also need variables= to hold the parameters you are going to pass to some of your sub-procedure= s. After reviewing your FSM though, I think you might do better with separate,= smaller state machine(s) for the reusable states, and implement a hierarch= ical state machine. There is no point in combining all the reusable and uni= que states into the same FSM. Does Synplify actually recognize your FSM as an FSM (what does it look like= in the RTL viewer or FSM explorer)? Sometimes if you assign the next state= from the contents of a register other than the current state, Synplify wil= l not treat it as a state machine, which then excludes optimizations normal= ly performed on FSMs.=20 As for my example that illuminated the synthesis problem, the procedure's l= ogic was complex enough that any abnormalities would not have been easy to = spot in RTL view. Unfortunately, Synplify unrolls functions and procedures = for RTL view. Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.126.137 with SMTP id c9mr13863647qas.2.1380053430741; Tue, 24 Sep 2013 13:10:30 -0700 (PDT) X-Received: by 10.182.237.13 with SMTP id uy13mr213315obc.4.1380053430672; Tue, 24 Sep 2013 13:10:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1704849qap.0!news-out.google.com!9ni111qaf.0!nntp.google.com!d5no1784048qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Sep 2013 13:10:30 -0700 (PDT) In-Reply-To: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: <228b9f01-6833-4df3-ab6d-10b4a51a202b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b1c122d-0f51-41f9-9570-0261b117e5ab@googlegroups.com> Subject: Re: Process to combinational circuits? From: Mike Treseler Injection-Date: Tue, 24 Sep 2013 20:10:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7062 > Everything that can be done with the process can be done without the > process when it comes to combinational, is not it? So what is the > justification? Tradition. I prefer to write a function. That can be tested out of time using assertions. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 00:52:25 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 25 Sep 2013 04:52:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="31030"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Pj7+ZOVj+7iWysp5lCZy9" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:uruwUzvwIXAGbGQYzoEynPBO1Gc= Xref: news.eternal-september.org comp.lang.vhdl:7063 On 9/24/2013 4:29 AM, alb wrote: > Hi Rick, > > On 23/09/2013 17:22, rickman wrote: > [] >> This is the first time you have compiled the code isn't it? So you have >> not done any testing on the code at all so far? > > As I mentioned in the beginning the code has been sim'ed and it works > properly in post-synth and post-layout (even though STA shows timing > violations on unrelated parts of the code). > > Unfortunately it does not work in the lab, but I think is more related > to the power-up rather than a functional problem (at power-up the 1-wire > line is pulled 'H' through a pull-up resistor and the sequence to talk > on the line starts too early). > >> Where are your parameter lists for the procedures such as update_ports? > > No parameter lists. All variables have global scope in the process. > > This is indeed something I do not completely like about this approach > since I haven't found a way to 'protect' the access to variables and you > may end up with variable assignments all scattered, killing the benefit > of subprogram partitioning. Ok, at this point I am showing my ignorance of using procedures in VHDL. I never realized that scope would work this way. In fact, this sounds very unlike VHDL. I'm still a bit confused about a couple of things. The procedures init_regs and update_ports may be in a clocked process, but they are *not* in the clocked region of the clocked process and so can generate combinatorial logic. Again, I have not looked at the code in detail as that would require me to copy to a text file and open it in a decent editor rather than this limited newsreader. Are you sure there are no issues in one of those two procedures? As to the scope issue, I don't think you *have* to use the global scope. You can pass parameters into the procedures if you choose to. It seems to me that using procedures provides limited advantages over non-modular code by not using parameters. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 13:05:26 +0200 Lines: 59 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net wL/AO5CEI9FIjoJHOlasXgumfJx7qzMA7T+v00x7LkqBwXYuVF Cancel-Lock: sha1:v4AloZYXp0R9NCEJhWzy2F9Ozeg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7064 Hi Rick, On 25/09/2013 06:52, rickman wrote: [] >>> Where are your parameter lists for the procedures such as update_ports? >> >> No parameter lists. All variables have global scope in the process. >> >> This is indeed something I do not completely like about this approach >> since I haven't found a way to 'protect' the access to variables and you >> may end up with variable assignments all scattered, killing the benefit >> of subprogram partitioning. > > Ok, at this point I am showing my ignorance of using procedures in VHDL. > I never realized that scope would work this way. In fact, this sounds > very unlike VHDL. I'm still a bit confused about a couple of things. There's only one process in the entire entity. Variables have local scope in the process, but since there's nothing except one process they can be considered 'global' in the entity. Moreover every procedure defined within the process has access to all local variables as well. > The procedures init_regs and update_ports may be in a clocked process, > but they are *not* in the clocked region of the clocked process and so > can generate combinatorial logic. the init_regs procedure is called in the reset branch of the clocked process, therefore will run to 'reset' all initial states of any locally defined variable. In update_ports all appropriate variables are 'wired' to ports (no signals). Meaning that every time the process is triggered they will be assigned to a port. Since update_ports is only called when the process is triggered I'm not sure if you can have an output port which is mapped to a pure combinatorial logic of a set of inputs. > Again, I have not looked at the code > in detail as that would require me to copy to a text file and open it in > a decent editor rather than this limited newsreader. Are you sure there > are no issues in one of those two procedures? Yeah I apologize for the code format, I try to keep everything under 80 characters for this very purpose but I'm not always so strict :-/ I'm trying to remove most of the stuff and synthesize piece by piece. Honestly I do not see how the init_regs and update_ports procedures can be broken. > > As to the scope issue, I don't think you *have* to use the global scope. > You can pass parameters into the procedures if you choose to. It seems > to me that using procedures provides limited advantages over non-modular > code by not using parameters. AFAIK vhdl passes arguments by value, making a local copy of the parameter which has local scope to the subprogram, in this case I do not know how I can have my 'state' variable retaining the value through clock cycles. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 13:34:52 +0200 Lines: 41 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net QCVG7Wc+LgVItic3sGdMqgSkm44UgKKBypWR9MGrawPka0kPVr Cancel-Lock: sha1:z7ic71hT1M6mikdKuuTOg7Q+CQ8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7065 On 24/09/2013 19:21, Andy wrote: > Al, > > I think you need flags to control calling the sub-procedures within > autoread, not calling autoread itself. It looks like you would also > need variables to hold the parameters you are going to pass to some > of your sub-procedures. flags to control sub-procedures calling are just the state of the FSM, while sub-procedures operate on global variables. > > After reviewing your FSM though, I think you might do better with > separate, smaller state machine(s) for the reusable states, and > implement a hierarchical state machine. There is no point in > combining all the reusable and unique states into the same FSM. I started off by 'encapsulating' the reusable states in separate procedures, but I was not sure how to 'wait' the end of it, that is why I ended up putting everything under a single FSM. > Does Synplify actually recognize your FSM as an FSM (what does it > look like in the RTL viewer or FSM explorer)? Sometimes if you assign > the next state from the contents of a register other than the current > state, Synplify will not treat it as a state machine, which then > excludes optimizations normally performed on FSMs. That is true indeed. Apparently the FSM explorer does not recognize an FSM. Definitely not good, a hierarchical approach becomes definitely mandatory. > > As for my example that illuminated the synthesis problem, the > procedure's logic was complex enough that any abnormalities would not > have been easy to spot in RTL view. Unfortunately, Synplify unrolls > functions and procedures for RTL view. The fact that my RTL looks messier than what I think should have been a clear hint that something is wrong. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 13:59:04 +0200 Lines: 57 Message-ID: References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 1pcI8ClEXO+axkDgHwwF4wevZi4ffqr1q0DxCv2edfc05JIAeP Cancel-Lock: sha1:Old0OjhEraeJWMHtwh3GjL1Yjr8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7066 Hi Mike, On 24/09/2013 18:09, Mike Treseler wrote: > On Tuesday, September 24, 2013 12:32:07 AM UTC-7, alb wrote: >> >> there are a couple of things that do not make me feel happy even if sim >> is ok: >> 1. the amount of logic inferred is exceeding my predictions (this is >> just an FSM with some registers and a couple of counters and it takes >> 12% of a 250k gates FPGA!). > > Have a look on the rtl viewer. Some variable array is too large or some > block ram does not fit the device. > > If you don't have a viewer, start out with the free quartus tools. as Andy said, the synthesizer did not quite realized there was an FSM. The fact that the next state was taken from a register confused it (I wonder why, since a state is just a register...). > >> 2. in the lab it does not work. > > Start with with just the reset procedure > check the reset pulse and all static outputs. reset procedure and static output look ok. The whole code simulated ok. > Add a clock and counter and check that. etc. I agree, I need to verify at each step what the rtl viewer shows, in order to be confident about what I'm doing. > >> Concerning 1. I'll need to investigate the RTL and see if there's >> something wrong going on (the Synplify Pro RTL viewer should be >> sufficient to do so). > > I never go near the bench until the RTL view is as expected. Pressures from above unfortunately... but I should admit that I looked at the RTL only *after* finding the HW did not work. > >> About 2., this is an FSM to read out a 1-wire bus in an infinite loop >> and I believe that at power up the 'Reset' on the 1-wire is sent too >> early (the line is still not stable at 'H') and the presence pulse is >> not sampled properly, causing the FSM to loop indefinitely in a state >> waiting for the presence bit to show up. I think this can be easily >> fixed waiting for the line to be stable first. > > I would read a burst at at time and check sims that the bus port has Z,1,0 > at the right times. I have a 1-wire slave in the TB and sims ok, all sequences are in the correct place as expected. What is not taken into account is the powerup time which might be different in sim and HW. From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.137.67 with SMTP id v3mr15907784qat.0.1380119190398; Wed, 25 Sep 2013 07:26:30 -0700 (PDT) X-Received: by 10.182.181.42 with SMTP id dt10mr309435obc.16.1380119190360; Wed, 25 Sep 2013 07:26:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!d5no1802138qap.0!news-out.google.com!9ni213qaf.0!nntp.google.com!d5no1802137qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2013 07:26:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> Subject: Re: combinational loops From: Andy Injection-Date: Wed, 25 Sep 2013 14:26:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7067 Al, I checked your update_ports procedure. In a clocked process, you cannot hav= e a combinatorial in-to-out path. I'm surprised it is not flagged as a warn= ging from the synthesis tool. I really don't know what circuitry you might = get from using input ports in the update_ports procedure, but it is possibl= e that, on a clock-cycle basis, the circuitry might still match simulation. All outputs driven by update_ports must be functions only of process variab= les or constants/generics, NOT input ports or signals. The references to va= riables in update_ports are to the registered values thereof (remember, upd= ate_ports also runs on the falling edge of the clock), and any logic (decis= ion making, expression, etc.) in the procedure is combinatorial after the r= egisters.=20 Just like in a combinatorial process, you also have to make sure that any p= orts that may be assigned in update_ports are always assigned, or else a la= tch will be inferred to remember the last value assigned to the port.=20 If update_ports were called inside the clocked if-then-else, the cycle-base= d timing of the outputs would be identical, but the input variables would b= e combinatorial, along with any logic in the procedure, and the ports would= be registered. In this case, you would also need to reset the output port = registers. The synchronous process template with three procedures (init_regs, update_r= egs, update_ports) works well within limits, but those limits must be obser= ved, and are not always well understood. I never really bought into the ide= a that anything was improved by using procedures here; I tend to see the th= ree regions of the clocked process as having those three distinct functions= anyway, procedure or not. Reuse of a procedure multiple times would be a g= ood reason, if not for the synthesis bug I mentioned. Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 17:25:23 +0200 Lines: 84 Message-ID: References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 97u2Nb9Lf/SkvWv6yM1BOghTUGiLYb8AJ/cAHFRTFjCnochW2I Cancel-Lock: sha1:yrxtzFnzev+5rnnXGd+eNbfoOgs= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7068 Hi Andy, On 25/09/2013 16:26, Andy wrote: [] > I checked your update_ports procedure. In a clocked process, you > cannot have a combinatorial in-to-out path. I'm surprised it is not > flagged as a warnging from the synthesis tool. I really don't know > what circuitry you might get from using input ports in the > update_ports procedure, but it is possible that, on a clock-cycle > basis, the circuitry might still match simulation. you are definitely right, that went completely unnoticed. Funny enough the rtl looks a multiplexer, as wanted. > All outputs driven by update_ports must be functions only of process > variables or constants/generics, NOT input ports or signals. The > references to variables in update_ports are to the registered values > thereof (remember, update_ports also runs on the falling edge of the > clock), and any logic (decision making, expression, etc.) in the > procedure is combinatorial after the registers. Since the logic is combinatorial for update_ports, shouldn't I bump in a simulation mismatch between pre and post synth. because of the sensitivity list for the combinational process? As far as I know synthesis tools tend to ignore sensitivity lists, resulting in a different behavior for the combinational logic... > Just like in a combinatorial process, you also have to make sure that > any ports that may be assigned in update_ports are always assigned, > or else a latch will be inferred to remember the last value assigned > to the port. I could potentially use a registered port with the following template instead: procedure template_a_rst is begin -- Has proven equivalent to v_rst for synthesis. if RST = '1' then init_regs; update_ports; elsif rising_edge(CLK) then update_regs; update_ports; end if; end procedure template_a_rst; and I just happen to notice a comment referring to the equivalence with the template I previously posted. > If update_ports were called inside the clocked if-then-else, the > cycle-based timing of the outputs would be identical, but the input > variables would be combinatorial, along with any logic in the > procedure, and the ports would be registered. In this case, you would > also need to reset the output port registers. See above. > > The synchronous process template with three procedures (init_regs, > update_regs, update_ports) works well within limits, but those limits > must be observed, and are not always well understood. I never really > bought into the idea that anything was improved by using procedures > here; I tend to see the three regions of the clocked process as > having those three distinct functions anyway, procedure or not. Reuse > of a procedure multiple times would be a good reason, if not for the > synthesis bug I mentioned. I agree on the limits and it is true that when sailing in unknown waters it is certainly not clear what will happen and instead of debugging code we might end up tricking the tools. The main issue I have with this approach is that variables are 'locally global', in the sense that they are local to the process, but global to every procedure in the code, potentially losing the encapsulation benefit provided by subprograms in the first place. I'd like to verify if there's a better way to isolate code which operates on globally defined data structures. The main merit I see in this approach is to clearly separate the three functions you referred to. I also find that readability is increased with this approach, even though I should really separate the reused states in separate fsm. From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.125.72 with SMTP id x8mr639592qar.5.1380140662655; Wed, 25 Sep 2013 13:24:22 -0700 (PDT) X-Received: by 10.182.66.130 with SMTP id f2mr101875obt.29.1380140662605; Wed, 25 Sep 2013 13:24:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!d5no1926910qap.0!news-out.google.com!9ni217qaf.0!nntp.google.com!d5no1926908qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Sep 2013 13:24:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <958c42f8-6623-4599-8d08-8ff8b9f3e1da@googlegroups.com> Subject: Re: combinational loops From: Mike Treseler Injection-Date: Wed, 25 Sep 2013 20:24:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7069 On Wednesday, September 25, 2013 8:25:23 AM UTC-7, alb wrote: > Hi Andy, > On 25/09/2013 16:26, Andy wrote: > > I checked your update_ports procedure. In a clocked process, you > >cannot have a combinatorial in-to-out path. Thanks Andy, Hi Alb, In the update_ports block I use only, my_port <= my_variable_v Keep other expressions in the update_regs block or in a function declared in architecture scope. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 25 Sep 2013 17:46:57 -0400 Organization: A noiseless patient Spider Lines: 84 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 25 Sep 2013 21:47:06 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="7047"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+21NJ3fdatcmu3U89S3kp+" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:WGuSj9Bm2Mq7dtcyUBNY77/RDNY= Xref: news.eternal-september.org comp.lang.vhdl:7070 On 9/25/2013 7:05 AM, alb wrote: > Hi Rick, > > On 25/09/2013 06:52, rickman wrote: > [] >>>> Where are your parameter lists for the procedures such as update_ports? >>> >>> No parameter lists. All variables have global scope in the process. >>> >>> This is indeed something I do not completely like about this approach >>> since I haven't found a way to 'protect' the access to variables and you >>> may end up with variable assignments all scattered, killing the benefit >>> of subprogram partitioning. >> >> Ok, at this point I am showing my ignorance of using procedures in VHDL. >> I never realized that scope would work this way. In fact, this sounds >> very unlike VHDL. I'm still a bit confused about a couple of things. > > There's only one process in the entire entity. Variables have local > scope in the process, but since there's nothing except one process they > can be considered 'global' in the entity. Moreover every procedure > defined within the process has access to all local variables as well. > >> The procedures init_regs and update_ports may be in a clocked process, >> but they are *not* in the clocked region of the clocked process and so >> can generate combinatorial logic. > > the init_regs procedure is called in the reset branch of the clocked > process, therefore will run to 'reset' all initial states of any locally > defined variable. > > In update_ports all appropriate variables are 'wired' to ports (no > signals). Meaning that every time the process is triggered they will be > assigned to a port. Since update_ports is only called when the process > is triggered I'm not sure if you can have an output port which is mapped > to a pure combinatorial logic of a set of inputs. > >> Again, I have not looked at the code >> in detail as that would require me to copy to a text file and open it in >> a decent editor rather than this limited newsreader. Are you sure there >> are no issues in one of those two procedures? > > Yeah I apologize for the code format, I try to keep everything under 80 > characters for this very purpose but I'm not always so strict :-/ > > I'm trying to remove most of the stuff and synthesize piece by piece. > Honestly I do not see how the init_regs and update_ports procedures can > be broken. I don't really see anything either. Looking at the RTL diagram may show you something useful. I often look at the schematics produced by synthesis when I am concerned about the hardware used. I don't recall needing to look at schematics to find bugs. It may help though if your circuit is small enough. >> As to the scope issue, I don't think you *have* to use the global scope. >> You can pass parameters into the procedures if you choose to. It seems >> to me that using procedures provides limited advantages over non-modular >> code by not using parameters. > > AFAIK vhdl passes arguments by value, making a local copy of the > parameter which has local scope to the subprogram, in this case I do not > know how I can have my 'state' variable retaining the value through > clock cycles. I'm not sure what that means. Procedures have inputs and outputs. Pass the inputs in and the outputs out. Where's the problem? To be honest, I have looked at using procedures before and didn't find any utility to taking a section of code delimited by the control structure of the registered process and partitioning it into procedures as blocks. If the procedures and/or functions are describing some logical entity, then it makes sense to me. But partitions for the sake of partitions don't help a lot when you don't have an easy way to test them as functional units. BTW, why are you using variables rather than signals? Variables are certainly useful at times. But I get the impression you are using them solely because that is what are used when writing software. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Thu, 26 Sep 2013 16:49:31 +0200 Lines: 80 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ktB/GfIShBc9gnEuWSL4xw91wAGHjv5HOa9eLDWYtzTqGfTBOz Cancel-Lock: sha1:98QqRfLzW/eNOd8rDmhQ2yP2SVw= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7071 Hi Rick, On 25/09/2013 23:46, rickman wrote: [] >> I'm trying to remove most of the stuff and synthesize piece by piece. >> Honestly I do not see how the init_regs and update_ports procedures can >> be broken. > > I don't really see anything either. Looking at the RTL diagram may show > you something useful. I often look at the schematics produced by > synthesis when I am concerned about the hardware used. I don't recall > needing to look at schematics to find bugs. It may help though if your > circuit is small enough. as Andy said, the update_ports was broken. That was a misuse of the template, forgetting about the whole idea about the single process. That said, it seemed the synthesis tool ignored the sensitivity list and did not infer any latch, on the contrary it instantiated a multiplexer just as I intended. By I agree with Andy and Mike that this is not the proper way to do it. [] >> AFAIK vhdl passes arguments by value, making a local copy of the >> parameter which has local scope to the subprogram, in this case I do not >> know how I can have my 'state' variable retaining the value through >> clock cycles. > > I'm not sure what that means. Procedures have inputs and outputs. Pass > the inputs in and the outputs out. Where's the problem? Indeed I can use 'inout' parameter for variables which need to retain the value (they will be locally modified and globally propagated), while I can use 'in' parameter for variables that the procedure need to be sensitive on. Using the same name for the global variable and the formal parameter might be a trick to 'protect' the global variable from being inadvertently overwritten by a procedure which is supposed to have read only access (with 'in' mode). > To be honest, I have looked at using procedures before and didn't find > any utility to taking a section of code delimited by the control > structure of the registered process and partitioning it into procedures > as blocks. If the procedures and/or functions are describing some > logical entity, then it makes sense to me. But partitions for the sake > of partitions don't help a lot when you don't have an easy way to test > them as functional units. I see two main advantages in using subprograms: 1. reuse 2. readability There's another subtle advantage in the template I posted, the three functional steps grouped in init_regs, updated_regs, update_ports make clear what often is not so evident in logic designs. I do not want to say that you cannot make readable code with several processes and signals to make them communicate, but I too often have seen single flops processes here and there with few attention to the overall function. I personally like this approach, regardless the problems that I'm currently facing (most probably related to my inexperience with the template itself). The template does not prevent to have a separate part of the entity where input-output combinational logic is inserted. > > BTW, why are you using variables rather than signals? Variables are > certainly useful at times. But I get the impression you are using them > solely because that is what are used when writing software. I used to use only signals because I did not quite understand the rules for variables. This is currently changing. While I consider abstraction a great benefit (just consider how easy is to describe a counter just saying 'cnt = cnt + 1', instead of describing connections between flops), the advantage of using variables is not only related to simulation performances (memory footprint for a signal is bigger), but also because it follows IMO more naturally the way of sequential reasoning. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Thu, 26 Sep 2013 13:56:15 -0400 Organization: A noiseless patient Spider Lines: 115 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 Sep 2013 17:56:20 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="8937"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18rHuf93kAN5qusVir+Sks9" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:T9Pw9fzGXtLSiT7nV4TEJq39yfo= Xref: news.eternal-september.org comp.lang.vhdl:7072 On 9/26/2013 10:49 AM, alb wrote: > Hi Rick, > > On 25/09/2013 23:46, rickman wrote: >> >> I don't really see anything either. Looking at the RTL diagram may show >> you something useful. I often look at the schematics produced by >> synthesis when I am concerned about the hardware used. I don't recall >> needing to look at schematics to find bugs. It may help though if your >> circuit is small enough. > > That said, it seemed the synthesis tool ignored the sensitivity list and > did not infer any latch, on the contrary it instantiated a multiplexer > just as I intended. By I agree with Andy and Mike that this is not the > proper way to do it. Synthesis tools *often* ignore sensitivity lists. >>> AFAIK vhdl passes arguments by value, making a local copy of the >>> parameter which has local scope to the subprogram, in this case I do not >>> know how I can have my 'state' variable retaining the value through >>> clock cycles. >> >> I'm not sure what that means. Procedures have inputs and outputs. Pass >> the inputs in and the outputs out. Where's the problem? > > Indeed I can use 'inout' parameter for variables which need to retain > the value (they will be locally modified and globally propagated), while > I can use 'in' parameter for variables that the procedure need to be > sensitive on. Sounds like a plan. > Using the same name for the global variable and the formal parameter > might be a trick to 'protect' the global variable from being > inadvertently overwritten by a procedure which is supposed to have read > only access (with 'in' mode). ??? If a procedure has an input with the same name as a global, it won't be able to access the global. But then as I said, I'm not fluent with procedures. I don't use globals for a variety of reasons including reuse and readability. >> To be honest, I have looked at using procedures before and didn't find >> any utility to taking a section of code delimited by the control >> structure of the registered process and partitioning it into procedures >> as blocks. If the procedures and/or functions are describing some >> logical entity, then it makes sense to me. But partitions for the sake >> of partitions don't help a lot when you don't have an easy way to test >> them as functional units. > > I see two main advantages in using subprograms: > > 1. reuse > 2. readability Yeah... maybe you can explain those. I think the procedure based approach is *less* readable, but that is subjective so I doubt we will agree. But as to reuse??? How is taking the code in a clocked process and breaking it into sections with wrappers around them make the code easier to reuse? Reuse comes from planning a design for reuse and making modules which are reusable. "Modules" does not have to be procedures. I typically use entities. > There's another subtle advantage in the template I posted, the three > functional steps grouped in init_regs, updated_regs, update_ports make > clear what often is not so evident in logic designs. Again, subjective. I have no trouble reading a standard clocked process without breaking it into sections. Heck, update_ports isn't even needed if you aren't using variables. > I do not want to say that you cannot make readable code with several > processes and signals to make them communicate, but I too often have > seen single flops processes here and there with few attention to the > overall function. Yes, but this is a separate issue. Any method can be abused. > I personally like this approach, regardless the problems that I'm > currently facing (most probably related to my inexperience with the > template itself). The template does not prevent to have a separate part > of the entity where input-output combinational logic is inserted. What is your background? Have you always been a hardware designer? >> BTW, why are you using variables rather than signals? Variables are >> certainly useful at times. But I get the impression you are using them >> solely because that is what are used when writing software. > > I used to use only signals because I did not quite understand the rules > for variables. This is currently changing. While I consider abstraction > a great benefit (just consider how easy is to describe a counter just > saying 'cnt = cnt + 1', instead of describing connections between > flops), the advantage of using variables is not only related to > simulation performances (memory footprint for a signal is bigger), but > also because it follows IMO more naturally the way of sequential reasoning. I don't follow. I can use an integer, a signed or an unsigned type and use the exact same code with a signal. The only difference is I don't have to assign my result to a signal to use it outside the process because it is already a signal. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.51.68 with SMTP id c4mr5071721qag.7.1380219033912; Thu, 26 Sep 2013 11:10:33 -0700 (PDT) X-Received: by 10.49.104.83 with SMTP id gc19mr146028qeb.12.1380219033875; Thu, 26 Sep 2013 11:10:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z5no3421qad.0!news-out.google.com!9ni350qaf.0!nntp.google.com!ek7no3189qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Sep 2013 11:10:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Thu, 26 Sep 2013 18:10:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7073 Al, The update_ports procedure (or the region of the clocked process in which i= t runs) is not its own process. Any code there runs anytime the process is = triggered (changes in reset or clk, including both edges of each). There is= no separate sensitivity list. Since update_ports should only be reading variables that are only updated w= hen init_regs or update_regs run, the output value of the ports never actua= lly changes on the falling edge, but they are reassigned (there is a transa= ction but no event). If you looked at a driven port's 'transaction attribut= e, that falling edge transaction would be apparent. And since there is no r= e-execution of the process to generate new output values, those output valu= es change in the same simulation delta cycle as any signal updated on the r= ising of the clock (e.g. a register).=20 I'm not sure what kind of circuitry your modified template (I assume you me= ant "process" template_a_rst instead of "procedure" template_a_rst?). Try i= t and see. But beware unlike the standard template which is compliant with = 1076.6-2004, the VHDL RTL Synthesis Standard, this behavior does not appear= to be supported. You could create an init_ports procedure that assigned co= nstant values to the ports during reset, and that should create registered = ports. Maybe synthesis could propagate the constants assigned to the regist= ers on to the outputs. VHDL inherited its lack of static local variables from Ada. They only appea= r to be static in a process because the process only executes once, while s= uspending and awakening many times.=20 Passing lots of variables into and out of a function or procedure can be ma= de much simpler by using a record.=20 If synthesis supported protected types and their method calls, they would a= llow complete encapsulation like entities, but with procedural instead of s= ignal interfaces. Something to think about... Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.5.5 with SMTP id 5mr5151464qat.4.1380220482113; Thu, 26 Sep 2013 11:34:42 -0700 (PDT) X-Received: by 10.49.116.116 with SMTP id jv20mr140132qeb.35.1380220482083; Thu, 26 Sep 2013 11:34:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z5no5700qad.0!news-out.google.com!9ni346qaf.0!nntp.google.com!z5no5699qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Sep 2013 11:34:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Thu, 26 Sep 2013 18:34:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7074 On Wednesday, September 25, 2013 4:46:57 PM UTC-5, rickman wrote: > On 9/25/2013 7:05 AM, alb wrote:=20 >> AFAIK vhdl passes arguments by value, making a local copy of the=20 >> parameter which has local scope to the subprogram, in this case I do not= =20 >> know how I can have my 'state' variable retaining the value through=20 >> clock cycles.=20 >I'm not sure what that means. Procedures have inputs and outputs. Pass the= inputs in and the outputs out. Where's the problem?=20 Inout ports can be used for this, but then the procedure does not remember = the last state, the process does. For in ports to procedures that do not span time, It is best to use a const= ant port kind, instead of variable or signal kind. A constant port can be a= ssociated with a signal, a variable, or an expression of either or both. Bu= t a variable port can only be associated with a variable, and a signal port= can only be associated with a signal. Inout and Out ports must be either signal or variable, and cannot be associ= ated with the other. Also, VHDL cannot recognize the signature difference between two procedures= whose only difference is variable vs signal port declarations. So writing = two different, otherwise identical procedures for a variable port and a sig= nal port is useless: the compiler cannot choose between them. Pass by value vs reference is kinda moot except for inout (you cannot write= an input anyway), and the standard mentions somewhere that it is an error = to depend on the simulator implementation one way or the other. Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.97.1 with SMTP id j1mr5722467qan.6.1380228272306; Thu, 26 Sep 2013 13:44:32 -0700 (PDT) X-Received: by 10.182.28.100 with SMTP id a4mr87297obh.28.1380228272270; Thu, 26 Sep 2013 13:44:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ek7no18544qab.0!news-out.google.com!9ni346qaf.0!nntp.google.com!z5no20142qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Sep 2013 13:44:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Thu, 26 Sep 2013 20:44:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7075 On Thursday, September 26, 2013 12:56:15 PM UTC-5, rickman wrote: > On 9/26/2013 10:49 AM, alb wrote:=20 >> On 25/09/2013 23:46, rickman wrote:=20 >> BTW, why are you using variables rather than signals? Variables are=20 >> certainly useful at times. But I get the impression you are using them= =20 >> solely because that is what are used when writing software.=20 > I used to use only signals because I did not quite understand the rules= =20 > for variables. This is currently changing. While I consider abstraction= =20 > a great benefit (just consider how easy is to describe a counter just=20 > saying 'cnt =3D cnt + 1', instead of describing connections between=20 > flops), the advantage of using variables is not only related to=20 > simulation performances (memory footprint for a signal is bigger), but=20 > also because it follows IMO more naturally the way of sequential > reasoning.=20 >> I don't follow. I can use an integer, a signed or an unsigned type and >> use the exact same code with a signal. The only difference is I don't=20 >> have to assign my result to a signal to use it outside the process=20 >> because it is already a signal. -- Rick I prefer variables to signals for several reasons: 1) Variables are declared locally in the process or subprogram (encapsulati= on). You can surround a process with a block statement in which you can dec= lare signals that are used only by that process, but it takes more code. 2) Use of variables can infer combinatorial or registered logic in a clocke= d process. 3) Variables allow you to create combinatorial or registered outputs from t= he same clocked process. 4) The update semantics of variable assignments are more intuitive from a S= W/code point of view. Signals assignments in a process are only pseudo-sequ= ential; in some aspects, order of execution matters, in others it does not.= Variables are purely sequential.=20 5) Not only is the variable's memory footprint less than a signal's, the ov= erhead of the separate update at suspension consumes less compute time. Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 27 Sep 2013 09:48:07 +0200 Lines: 65 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 6gy4GiA9ZVifA4ZOy6HNvA8pXrYnizTbD3zF/+Pe+wf7DcQ3Dx Cancel-Lock: sha1:0CzBHryfpjubSgQkwdg/f2IKie4= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7076 Hi Andy, On 24/09/2013 19:21, Andy wrote: [] > After reviewing your FSM though, I think you might do better with > separate, smaller state machine(s) for the reusable states, and > implement a hierarchical state machine. There is no point in > combining all the reusable and unique states into the same FSM. I came up with this new attempt to implement hierarchical FSMs: procedure update_regs is begin -- purpose: call the procedures above in the desired order writ_read (state_v, mstate_v, nstate_v); -- low level write/read pres_puls (state_v, mstate_v, nstate_v); -- presence pulse auto_read (state_v, mstate_v, nstate_v); -- top level fsm end procedure update_regs; the three FSMs run in 'parallel' and they pass each other the three main state variables. state_v, mstate_v and nstate_v [1] are globally accessible but the key point is in the formal parameter definitions of the three procedures: procedure writ_read ( state_v : inout state_t; mstate_v : in mstate_t; nstate_v : in nstate_t) is -- ... procedure pres_puls ( state_v : in state_t; mstate_v : inout mstate_t; nstate_v : in nstate_t) is -- ... procedure auto_read ( state_v : in state_t; mstate_v : in mstate_t; nstate_v : inout nstate_t) is -- ... While all states are available to all FSMs only one of them is changeable buy each of them. Moreover, calling the parameters with the same name as the global variables prevents accidental write access to global variables from inside the procedure, providing some degree of 'protection'. > Does Synplify actually recognize your FSM as an FSM (what does it > look like in the RTL viewer or FSM explorer)? Sometimes if you assign > the next state from the contents of a register other than the current > state, Synplify will not treat it as a state machine, which then > excludes optimizations normally performed on FSMs. With the current implementation Synplify Pro recognizes all the FSM and operates accordingly, resulting in an RTL which makes much more sense. That said, my stupid logic seems not working for other reasons that I now start to believe reside in my simulation setup not being 100% representative of the HW setup (ouch!). [1] I should really ask myself why I've chosen these set of names for the state variables... the fact they are not equal length is a worrying sign of my 'post 25 y.o. decline' From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Updating implicit signal Date: Fri, 27 Sep 2013 15:32:31 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <5231783B.2080107@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Sep 2013 12:32:31 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="12061"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18sVcQt1IkjaF7Z4DKoaYdxxRpz0k81HL0=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: Cancel-Lock: sha1:m7Vg0ZgA+DCOks7+ClsROIFixLI= Xref: news.eternal-september.org comp.lang.vhdl:7077 On 16.09.2013 22:15, Andy wrote: > "You can lead a horse to water, but you cannot make it drink." That is right. If you do not want to say what you mean, I cannot force you. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 27 Sep 2013 21:18:17 +0200 Lines: 72 Message-ID: References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net pQetIO48dCMkS4VDCx2yzAu73ZxKUUF4OjwhVyWzSGJuG2PNz0 Cancel-Lock: sha1:6NPRdfH1rcP8Kl9vegsAsZsBgyw= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7078 Hi Andy, On 26/09/2013 20:10, Andy wrote: > The update_ports procedure (or the region of the clocked process in > which it runs) is not its own process. Any code there runs anytime > the process is triggered (changes in reset or clk, including both > edges of each). There is no separate sensitivity list. this is clear and that is the main reason why update_ports cannot instantiate purely combinatorial combination of inputs to produce outputs. That said, aren't synthesis tool ignoring - for some strange reason - the sensitivity list? > Since update_ports should only be reading variables that are only > updated when init_regs or update_regs run, the output value of the > ports never actually changes on the falling edge, but they are > reassigned (there is a transaction but no event). If you looked at a > driven port's 'transaction attribute, that falling edge transaction > would be apparent. And since there is no re-execution of the process > to generate new output values, those output values change in the same > simulation delta cycle as any signal updated on the rising of the > clock (e.g. a register). Now I see why the template_rst and template_v_rst are functionally equivalent in Mike's example: http://hdfs.googlecode.com/svn/trunk/hdfs/lib/uart/uart.vhd > I'm not sure what kind of circuitry your modified template (I assume > you meant "process" template_a_rst instead of "procedure" > template_a_rst?). You are right, I should have said 'process' and should have modified the procedure to be a process instead, but I've been lazy and I copied it from the example above. > Try it and see. But beware unlike the standard > template which is compliant with 1076.6-2004, the VHDL RTL Synthesis > Standard, this behavior does not appear to be supported. You could > create an init_ports procedure that assigned constant values to the > ports during reset, and that should create registered ports. Maybe > synthesis could propagate the constants assigned to the registers on > to the outputs. Probably is not worth the effort and certainly if I start to depend on tools' implementation than I'm on my own. > > VHDL inherited its lack of static local variables from Ada. They only > appear to be static in a process because the process only executes > once, while suspending and awakening many times. as I showed in this post , you may come to some higher level of encapsulation, allowing a procedure to modify only a specific global variable, while still providing reading access to the others. > > Passing lots of variables into and out of a function or procedure can > be made much simpler by using a record. but the record type does not allow different modes for its elements, therefore limiting the aim of passing through formal parameters. > If synthesis supported protected types and their method calls, they > would allow complete encapsulation like entities, but with procedural > instead of signal interfaces. Something to think about... Learning to use protected types is the next point on my to-do list ;-) From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 01 Oct 2013 19:09:12 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <570d32b1-0688-4aff-a32e-2b5833fad390@googlegroups.com> <6e1e0120-287b-4918-8f03-eee9b71bb461@googlegroups.com> <79b6ecaf-6b24-4455-a619-fa077f6b1b8a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 1 Oct 2013 23:09:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="27737"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/I4rEGh4HbNjZ9xi6EWDtR" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:RvRdXly9ci/14yoR53hRzE/PEj0= Xref: news.eternal-september.org comp.lang.vhdl:7079 On 9/27/2013 3:18 PM, alb wrote: > Hi Andy, > > On 26/09/2013 20:10, Andy wrote: >> The update_ports procedure (or the region of the clocked process in >> which it runs) is not its own process. Any code there runs anytime >> the process is triggered (changes in reset or clk, including both >> edges of each). There is no separate sensitivity list. > > this is clear and that is the main reason why update_ports cannot > instantiate purely combinatorial combination of inputs to produce outputs. > > That said, aren't synthesis tool ignoring - for some strange reason - > the sensitivity list? I'm not sure I follow. What is being ignored about the sensitivity list? But I will say I have read about many times when there are errors in the sensitivity list and the simulation fails because of it, but the synthesis works just the same. But I expect this is very different from what you are talking about. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Tue, 01 Oct 2013 20:35:55 -0400 Organization: A noiseless patient Spider Lines: 101 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 2 Oct 2013 00:36:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="18671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Uo21ZpFHuxVuo0lwhbds+" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:IYTdeWSWWStHCbMkprWnBYj/mwc= Xref: news.eternal-september.org comp.lang.vhdl:7080 On 9/27/2013 3:48 AM, alb wrote: > Hi Andy, > > On 24/09/2013 19:21, Andy wrote: > [] >> After reviewing your FSM though, I think you might do better with >> separate, smaller state machine(s) for the reusable states, and >> implement a hierarchical state machine. There is no point in >> combining all the reusable and unique states into the same FSM. > > I came up with this new attempt to implement hierarchical FSMs: > > > procedure update_regs is > begin -- purpose: call the procedures above in the desired order > writ_read (state_v, mstate_v, nstate_v); -- low level write/read > pres_puls (state_v, mstate_v, nstate_v); -- presence pulse > auto_read (state_v, mstate_v, nstate_v); -- top level fsm > end procedure update_regs; > > > the three FSMs run in 'parallel' and they pass each other the three main > state variables. state_v, mstate_v and nstate_v [1] are globally > accessible but the key point is in the formal parameter definitions of > the three procedures: > > > procedure writ_read ( > state_v : inout state_t; > mstate_v : in mstate_t; > nstate_v : in nstate_t) is > -- ... > procedure pres_puls ( > state_v : in state_t; > mstate_v : inout mstate_t; > nstate_v : in nstate_t) is > -- ... > procedure auto_read ( > state_v : in state_t; > mstate_v : in mstate_t; > nstate_v : inout nstate_t) is > -- ... > > > While all states are available to all FSMs only one of them is > changeable buy each of them. Moreover, calling the parameters with the > same name as the global variables prevents accidental write access to > global variables from inside the procedure, providing some degree of > 'protection'. Maybe you are accustomed to this style, but I would find it rather complex and difficult to code for. Even though these variables will result in registers when used in a clocked process, as variables their values are updated immediately rather than waiting for a delta step like signals do. So the first procedure will run and update its state variable. Then the second procedure will run having to be aware that the first state variable has *already changed*... ect for the third state variable. I'm not sure what FSM would have three independent state variables like this. I am assuming the other variables would have to do with outputs or something else, dunno. I just know I would never use a style like this for FSM work. Typically any FSM has two signals or variables, present_state and next_state with obvious uses. Next_state is a function of present_state and inputs. Present_state is updated from next_state on the clock edge. So present_state is the registered value and next_state is in essence the value of the input to the state register. In most hardware implementations any other FSM will depend on the registered version of the other FSM state variables. Likewise the output of a FSM will typically only depend on the registered value. But when using a strict Mealy machine it can be useful to access the input to the state register. >> Does Synplify actually recognize your FSM as an FSM (what does it >> look like in the RTL viewer or FSM explorer)? Sometimes if you assign >> the next state from the contents of a register other than the current >> state, Synplify will not treat it as a state machine, which then >> excludes optimizations normally performed on FSMs. > > With the current implementation Synplify Pro recognizes all the FSM and > operates accordingly, resulting in an RTL which makes much more sense. > > That said, my stupid logic seems not working for other reasons that I > now start to believe reside in my simulation setup not being 100% > representative of the HW setup (ouch!). > > [1] I should really ask myself why I've chosen these set of names for > the state variables... the fact they are not equal length is a worrying > sign of my 'post 25 y.o. decline' Hmmm... I've not suffered a post 25 decline. I only sharpened through my 30s and 40s, but I am seeing a post 50 decline. I slow down and think more about what I do. lol -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 02 Oct 2013 02:30:57 -0400 Organization: A noiseless patient Spider Lines: 89 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 2 Oct 2013 06:31:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="13771"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+J6+3nay8Y9UIOu/z6Rozb" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:v7Q2JQYKCiJOSVZ+QGaYndp3dxk= Xref: news.eternal-september.org comp.lang.vhdl:7081 On 9/26/2013 4:44 PM, Andy wrote: > On Thursday, September 26, 2013 12:56:15 PM UTC-5, rickman wrote: >> On 9/26/2013 10:49 AM, alb wrote: >>> On 25/09/2013 23:46, rickman wrote: >>> BTW, why are you using variables rather than signals? Variables are >>> certainly useful at times. But I get the impression you are using them >>> solely because that is what are used when writing software. > >> I used to use only signals because I did not quite understand the rules >> for variables. This is currently changing. While I consider abstraction >> a great benefit (just consider how easy is to describe a counter just >> saying 'cnt = cnt + 1', instead of describing connections between >> flops), the advantage of using variables is not only related to >> simulation performances (memory footprint for a signal is bigger), but >> also because it follows IMO more naturally the way of sequential >> reasoning. > >>> I don't follow. I can use an integer, a signed or an unsigned type and >>> use the exact same code with a signal. The only difference is I don't >>> have to assign my result to a signal to use it outside the process >>> because it is already a signal. -- Rick > > I prefer variables to signals for several reasons: Certainly to each his own and I don't want to downplay your opinion, but let me rebut if I can. > 1) Variables are declared locally in the process or subprogram (encapsulation). You can surround a process with a block statement in which you can declare signals that are used only by that process, but it takes more code. The local/global thing is not so important in HDL the way most people use it. Very few designers put their entire design in one process with a large number of procedures. Rather the modularize by using multiple processes to describe the hardware they are designing a section at a time. When using signals they can only be driven validly by one process, so you get warnings, no, actually errors, when a signal is driven by multiple processes. The other way the global/local thing is not an issue is because most designers don't even use a single entity. Each entity has its own set of signals making them all local. > 2) Use of variables can infer combinatorial or registered logic in a clocked process. If that is useful to you good. I have never wanted to add combinatorial logic to a clock process, I keep the combinatorial logic separate because it is... well, separate. This is really an issue of what you are comfortable with. I don't care for what are fairly subtle usages to create such logic in a clocked process. It will confuse many designers and is subject to error. > 3) Variables allow you to create combinatorial or registered outputs from the same clocked process. Isn't this the same as 2? No, wait, you can't output variables, so you have to use signals to output anything from a clocked process, no? > 4) The update semantics of variable assignments are more intuitive from a SW/code point of view. Signals assignments in a process are only pseudo-sequential; in some aspects, order of execution matters, in others it does not. Variables are purely sequential. Intuitive is a nice word for "it matches my bias". If your background is sequential code like C, then yes, you will likely feel more comfortable with variables. I learned such languages, but when I learned HDL I was taught to describe the hardware (after all, were were hardware designers learning to use an HDL in place of schematics) and processes and signals are natural tools for that. > 5) Not only is the variable's memory footprint less than a signal's, the overhead of the separate update at suspension consumes less compute time. Here you are talking about simulation. I have never had an issue with running time in a simulation that didn't involve the amount of data being recorded rather than the simulation itself. But then I don't design huge FPGAs, I tend to do small designs, about the same complexity as you might find on a small MCU. I have a different approach to HDL use. My background is likely very different from yours. Also, my approach is widely used by the industry and so it well debugged in terms of the tools supporting it. I seem to have good productivity and my designs are solid (as long as I don't make newbie mistakes like I did recently where I forgot the synchronizing FF on an input). So different horses for different courses. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 02 Oct 2013 02:33:09 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 2 Oct 2013 06:34:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="13771"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+DZ1FurU4NWTyhccZ7dXQ5" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:eckU7lSfHT23+Ft32NRcBOA0qCU= Xref: news.eternal-september.org comp.lang.vhdl:7082 On 9/26/2013 2:34 PM, Andy wrote: > On Wednesday, September 25, 2013 4:46:57 PM UTC-5, rickman wrote: >> On 9/25/2013 7:05 AM, alb wrote: >>> AFAIK vhdl passes arguments by value, making a local copy of the >>> parameter which has local scope to the subprogram, in this case I do not >>> know how I can have my 'state' variable retaining the value through >>> clock cycles. > >> I'm not sure what that means. Procedures have inputs and outputs. Pass the inputs in and the outputs out. Where's the problem? > > Inout ports can be used for this, but then the procedure does not remember the last state, the process does. > > For in ports to procedures that do not span time, It is best to use a constant port kind, instead of variable or signal kind. A constant port can be associated with a signal, a variable, or an expression of either or both. But a variable port can only be associated with a variable, and a signal port can only be associated with a signal. > > Inout and Out ports must be either signal or variable, and cannot be associated with the other. > > Also, VHDL cannot recognize the signature difference between two procedures whose only difference is variable vs signal port declarations. So writing two different, otherwise identical procedures for a variable port and a signal port is useless: the compiler cannot choose between them. > > Pass by value vs reference is kinda moot except for inout (you cannot write an input anyway), and the standard mentions somewhere that it is an error to depend on the simulator implementation one way or the other. I still don't see the problem with using the parameter lists with procedures. Maybe you need to spell it out more clearly for me? -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 02 Oct 2013 11:47:21 +0200 Lines: 107 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net XbBdW6R2wEdlhxkTG2rC8ASbET1wQD0Hs2LUTJjpAtaMDmjXe1 Cancel-Lock: sha1:yjWLpowoP+AAYg7KEyuhWXQcuJM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7083 Hi Rick, On 02/10/2013 02:35, rickman wrote: [] >> I came up with this new attempt to implement hierarchical FSMs: >> >> >> procedure update_regs is >> begin -- purpose: call the procedures above in the desired order >> writ_read (state_v, mstate_v, nstate_v); -- low level write/read >> pres_puls (state_v, mstate_v, nstate_v); -- presence pulse >> auto_read (state_v, mstate_v, nstate_v); -- top level fsm >> end procedure update_regs; >> >> >> the three FSMs run in 'parallel' and they pass each other the three main >> state variables. state_v, mstate_v and nstate_v [1] are globally >> accessible but the key point is in the formal parameter definitions of >> the three procedures: >> >> >> procedure writ_read ( >> state_v : inout state_t; >> mstate_v : in mstate_t; >> nstate_v : in nstate_t) is >> -- ... >> procedure pres_puls ( >> state_v : in state_t; >> mstate_v : inout mstate_t; >> nstate_v : in nstate_t) is >> -- ... >> procedure auto_read ( >> state_v : in state_t; >> mstate_v : in mstate_t; >> nstate_v : inout nstate_t) is >> -- ... >> >> >> While all states are available to all FSMs only one of them is >> changeable buy each of them. Moreover, calling the parameters with the >> same name as the global variables prevents accidental write access to >> global variables from inside the procedure, providing some degree of >> 'protection'. > > Maybe you are accustomed to this style, but I would find it rather > complex and difficult to code for. Even though these variables will > result in registers when used in a clocked process, as variables their > values are updated immediately rather than waiting for a delta step like > signals do. So the first procedure will run and update its state > variable. Then the second procedure will run having to be aware that > the first state variable has *already changed*... ect for the third > state variable. I do not see what's wrong with the second procedure needing to be aware of the changed variable. When the second procedure runs all previous variables have been updated accordingly and depending on their values the procedure runs accordingly. To infer a register simply use the variable before it is assigned. > > I'm not sure what FSM would have three independent state variables like > this. I am assuming the other variables would have to do with outputs > or something else, dunno. I just know I would never use a style like > this for FSM work. this is what the RTL view is showing and what the FSM explorer has found. > > Typically any FSM has two signals or variables, present_state and > next_state with obvious uses. Next_state is a function of present_state > and inputs. Present_state is updated from next_state on the clock edge. > So present_state is the registered value and next_state is in essence > the value of the input to the state register. exactly the same here. In each individual FSM the inout mode in the parameter list is for the state parameter that the FSM will run with. Like in one process FSM, you do not need to formally separate the 'present state' and the 'next state'. > > In most hardware implementations any other FSM will depend on the > registered version of the other FSM state variables. Likewise the > output of a FSM will typically only depend on the registered value. But > when using a strict Mealy machine it can be useful to access the input > to the state register. I've thrown Mealy and Moore definitions away long ago. I think about the function, not a particular implementation. I prefer to have registered outputs and in my case those outputs are described directly in the appropriate states of the FSM, whether this is Mealy or Moore I could care less with all due respect. [] >> [1] I should really ask myself why I've chosen these set of names for >> the state variables... the fact they are not equal length is a worrying >> sign of my 'post 25 y.o. decline' > > Hmmm... I've not suffered a post 25 decline. I only sharpened through > my 30s and 40s, but I am seeing a post 50 decline. I slow down and > think more about what I do. lol At 25 y.o. I spent 3 months on the red roads of the Australian inland, a year later only 21 days in Chile and two years later only 15 days in New Zealand. Nowadays I can have a sore back after a night in a tent... why should I expect my brain to have followed a different course? ;-) From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.58.94.103 with SMTP id db7mr282847veb.40.1380726279377; Wed, 02 Oct 2013 08:04:39 -0700 (PDT) X-Received: by 10.49.116.116 with SMTP id jv20mr39490qeb.35.1380726279331; Wed, 02 Oct 2013 08:04:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!a6no972926qak.0!news-out.google.com!9ni3043qaf.0!nntp.google.com!q9no1264566qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Oct 2013 08:04:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Wed, 02 Oct 2013 15:04:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 142 Xref: news.eternal-september.org comp.lang.vhdl:7084 On Wednesday, October 2, 2013 1:30:57 AM UTC-5, rickman wrote: > The local/global thing is not so important in HDL the way most > people use it. Very few designers put their entire design in > one process with a large number of procedures. Rather the > modularize by using multiple processes to describe the hardware > they are designing a section at a time. When using signals they > can only be driven validly by one process, so you get warnings, > no, actually errors, when a signal is driven by multiple > processes. Encapsulation is often less about which code can modify/drive a variable/si= gnal than it is about which code can read it, depend on it, and quit workin= g if it is modified. For example, say I have a couple of processes in an architecture. One uses = a counter to step through some data, and it is not important which order it= is processed, so the author decides to use an up-counter.=20 Another process that can see that counter, uses that same counter's value t= o control something else within it, but it depends on the implementation de= cision in the first process to use an up-counter. What happens if the first process is modified to optimize the counter by co= nverting it to a down-counter? If the counter had been a local variable, th= en there would be nothing outside that process that could be directly depen= dent upon its behavior, and changing the direction of the counter would hav= e no impacts elsewhere. But if it is a signal, then the entire architecture= has to be understood to make sure that any changes to the counter's behavi= or do not have an unforeseen impact. Sometimes shared counters are a good thing; great, make them signals so tha= t it is known that it is intended to be shared. Otherwise, keep it local so= that it cannot be shared. Better yet, if the counter is shared among only = two of the processes, put those two processes in a block, and declare the c= ounter signal locally within the block. This protects the counter from depe= ndencies in the other processes in the architecture. Al's solution of passing state variables around between different processes= is another example. Generally, state variables are pure implementation, an= d should not be shared. A better solution might be to define the interfaces= between the procedures as explicit control (start) and status (finished) p= arameters, so that one procedure can be modified to change the way its FSM = works, while maintaining the interface signals' functionality, and the othe= r procedures would not be impacted. > > The other way the global/local thing is not an issue is because > most designers don't even use a single entity. Each entity has > its own set of signals making them all local. If designers are using a single process per entity, then yes, there is no p= ractical difference in scope between a signal and a variable. Most designer= s use multiple processes per entity, so there is a difference for most desi= gners. > I have never wanted to add combinatorial logic to a clock process, > I keep the combinatorial logic separate because it is... well, > separate. This is really an issue of what you are comfortable with. > I don't care for what are fairly subtle usages to create such logic > in a clocked process. It will confuse many designers and is subject > to error.=20 This is a matter of how most designers are taught HDL: by examples of what = kind of code structure creates what kind of circuit, and then just write co= ncurrent islands of code that generates those circuits, and wire them up (i= n code). Sure, it is important to know what kind of circuit will be created from a c= ertain piece of code. But the problem is, the synthesis tool is analyzing t= he behavior of the code, not the structure, and inferring the circuit from = that behavior. The problem is that designers are taught that "code that loo= ks like this" creates a register, and "code that looks like that" creates a= combinatorial circuit.=20 Designers should be taught that "code that BEHAVES like this" creates a reg= ister, etc. It is amazing to me how many different approaches to avoiding l= atches in RTL are based on a fundamental misunderstanding of the behavior t= hat infers a latch (which is very similar to the behavior that creates a re= gister). Design productivity can only progress so far by continuing to focus on desc= ribing the circuitry (gates and registers). To improve design productivity,= we have to start designing more at the behavioral level (functions, throug= hput and latency). Why do you think high level synthesis tools (that can sy= nthesize untimed models in C, etc.) are becoming so popular? I don't think = it is the language as much as it is the concept of describing behavior sepa= rate from throughput and latency (those are provided to the HLS tool separa= tely), and getting working hardware out the other end. > Isn't this the same as 2? No, wait, you can't output variables, so you ha= ve to use signals to output anything from a clocked process, no?=20 Of course, any output from a process must be a signal. But for that signal = to be a combinatorial function of registered values in the same process, th= e registers must be inferred from variables. If you use a signal for the re= gister in the process, you have to use a separate process for the combinato= rial function. > Intuitive is a nice word for "it matches my bias". If your background > is sequential code like C, then yes, you will likely feel more > comfortable with variables. I learned such languages, but when I > learned HDL I was taught to describe the hardware (after all, were > were hardware designers learning to use an HDL in place of schematics) > and processes and signals are natural tools for that.=20 Perhaps so, but my background is hardware design (analog and digital circui= t cards and later, FPGAs), not SW. My first few XC3090 FPGA designs were by= schematic entry. I did not immediately embrace HDL design (I actually lobb= ied managment against it), but once I tried it, I was hooked. My first VHDL= training was for simulation, not synthesis, so maybe that too has influenc= ed the way I use VHDL even for synthesis. Over the decades I have seen firs= t hand the value of designing the desired behavior of a circuit, rather tha= n describing the circuit itself. There are times where performance or synch= ronization still require focus on the circuit. But even for those, I tend t= o tweak the behavior I am describing to get the circuit I need (using RTL &= Technology viewers in the synthesis tool), rather than brute-force the cir= cuit description.=20 > I have never had an issue with running time in a simulation that didn't > involve the amount of data being recorded rather than the simulation > itself. But then I don't design huge FPGAs, I tend to do small designs, > about the same complexity as you might find on a small MCU. I have a > different approach to HDL use. My background is likely very different > from yours. Also, my approach is widely used by the industry and so it > well debugged in terms of the tools supporting it. I seem to have good > productivity and my designs are solid (as long as I don't make newbie > mistakes like I did recently where I forgot the synchronizing FF on an > input).=20 Among causes for slow simulations, using signals where variables would work= is pretty low on the list of big hitters. But using lots of combinatorial = processes is a much bigger hitter (gate level models are the extreme exampl= e of this). Some simulators can merge execution of processes that share the= same sensitivity list, saving the overhead of separately starting and stop= ping the individual processes. Combinatorial processes rarely share the sam= e sensitivities, so they are rarely combined, and the performance shows it. > So different horses for different courses.=20 Of course! Andy From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.5.5 with SMTP id 5mr9531812qat.4.1380766873009; Wed, 02 Oct 2013 19:21:13 -0700 (PDT) X-Received: by 10.49.53.70 with SMTP id z6mr210qeo.29.1380766872949; Wed, 02 Oct 2013 19:21:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no1442578qak.0!news-out.google.com!9ni4233qaf.0!nntp.google.com!a6no1442569qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Oct 2013 19:21:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> Subject: Re: combinational loops From: KJ Injection-Date: Thu, 03 Oct 2013 02:21:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7085 On Wednesday, October 2, 2013 11:04:39 AM UTC-4, Andy wrote: > Another process that can see that counter, uses that same counter's value= to control > something else within it, but it depends on the implementation decision i= n the first > process to use an up-counter. >=20 > What happens if the first process is modified to optimize the counter by = converting it=20 > to a down-counter? If the counter had been a local variable, then there w= ould be nothing > outside that process that could be directly dependent upon its behavior, = and changing > the direction of the counter would have no impacts elsewhere. But if it i= s a signal, > then the entire architecture has to be understood to make sure that any c= hanges to > the counter's behavior do not have an unforeseen impact. This is a weak argument. If a signal that is a counter can be 'seen' and u= sed for some other than the original intended purpose, then so can a variab= le...you simply put the 'other' code inside that same process and watch thi= ngs not work in the same way as when the counter is a signal. Pretending y= ou have some sort of firewall here doesn't make it one. If something no longer works because a behavior was changed it will show up= in the testbench. Even if you don't do that then you should be able to ca= tch it when you do a simple text search to see where else the signal or var= iable that you're modifying gets used elsewhere in the design. Making a be= haviour change without doing this simple text search to see what else can b= e affected is a design process that should be modified. One clear advantage of signals over variables is simply that signals can be= added to a wave window for debug after the fact, variables cannot. When a= n assertion is triggered or some other anomoly is noticed, the fact that yo= u can drag the signal over to the wave window and see the entire history an= d not have to restart the simulation can be a big time saving advantage. I= f your sims are short then restarting the sim is not an issue...but then if= the sim is short there is likely little wall clock time advantage to use v= ariables either. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Wed, 02 Oct 2013 23:24:46 -0400 Organization: A noiseless patient Spider Lines: 136 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Oct 2013 03:26:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="2444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18t89KCplj8hdNOdsRMv1Uk" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:kBa4qCN0esHYD2kkhmzNgslerxQ= Xref: news.eternal-september.org comp.lang.vhdl:7086 On 10/2/2013 5:47 AM, alb wrote: > Hi Rick, > > On 02/10/2013 02:35, rickman wrote: > [] >>> I came up with this new attempt to implement hierarchical FSMs: >>> >>> >>> procedure update_regs is >>> begin -- purpose: call the procedures above in the desired order >>> writ_read (state_v, mstate_v, nstate_v); -- low level write/read >>> pres_puls (state_v, mstate_v, nstate_v); -- presence pulse >>> auto_read (state_v, mstate_v, nstate_v); -- top level fsm >>> end procedure update_regs; >>> >>> >>> the three FSMs run in 'parallel' and they pass each other the three main >>> state variables. state_v, mstate_v and nstate_v [1] are globally >>> accessible but the key point is in the formal parameter definitions of >>> the three procedures: >>> >>> >>> procedure writ_read ( >>> state_v : inout state_t; >>> mstate_v : in mstate_t; >>> nstate_v : in nstate_t) is >>> -- ... >>> procedure pres_puls ( >>> state_v : in state_t; >>> mstate_v : inout mstate_t; >>> nstate_v : in nstate_t) is >>> -- ... >>> procedure auto_read ( >>> state_v : in state_t; >>> mstate_v : in mstate_t; >>> nstate_v : inout nstate_t) is >>> -- ... >>> >>> >>> While all states are available to all FSMs only one of them is >>> changeable buy each of them. Moreover, calling the parameters with the >>> same name as the global variables prevents accidental write access to >>> global variables from inside the procedure, providing some degree of >>> 'protection'. >> >> Maybe you are accustomed to this style, but I would find it rather >> complex and difficult to code for. Even though these variables will >> result in registers when used in a clocked process, as variables their >> values are updated immediately rather than waiting for a delta step like >> signals do. So the first procedure will run and update its state >> variable. Then the second procedure will run having to be aware that >> the first state variable has *already changed*... ect for the third >> state variable. > > I do not see what's wrong with the second procedure needing to be aware > of the changed variable. When the second procedure runs all previous > variables have been updated accordingly and depending on their values > the procedure runs accordingly. That *is* the problem. The second procedure sees the next state rather than the current state. > To infer a register simply use the variable before it is assigned. I thought they were all registers? If not, they aren't state variables. >> I'm not sure what FSM would have three independent state variables like >> this. I am assuming the other variables would have to do with outputs >> or something else, dunno. I just know I would never use a style like >> this for FSM work. > > this is what the RTL view is showing and what the FSM explorer has found. > >> >> Typically any FSM has two signals or variables, present_state and >> next_state with obvious uses. Next_state is a function of present_state >> and inputs. Present_state is updated from next_state on the clock edge. >> So present_state is the registered value and next_state is in essence >> the value of the input to the state register. > > exactly the same here. In each individual FSM the inout mode in the > parameter list is for the state parameter that the FSM will run with. > Like in one process FSM, you do not need to formally separate the > 'present state' and the 'next state'. And therein lies the problem. When using a single variable like this, if some state variable have been updated but not others, the FSM gets very complex. The isolated procedures for updating each state variable in your FSM have to be aware of one another and the order in which they are invoked. This greatly complicates the code and understanding of it. I would find that to be impossibly difficult to use. I don't consider this to be useful decomposition. >> In most hardware implementations any other FSM will depend on the >> registered version of the other FSM state variables. Likewise the >> output of a FSM will typically only depend on the registered value. But >> when using a strict Mealy machine it can be useful to access the input >> to the state register. > > I've thrown Mealy and Moore definitions away long ago. I think about the > function, not a particular implementation. > I prefer to have registered outputs and in my case those outputs are > described directly in the appropriate states of the FSM, whether this is > Mealy or Moore I could care less with all due respect. Yes, Mealy and Moore are not often used in a strict sense, but the point is access to the *next* value of the state rather than the current value. This lets you get registered outputs out on *this* clock edge rather than having them wait a clock cycle. >>> [1] I should really ask myself why I've chosen these set of names for >>> the state variables... the fact they are not equal length is a worrying >>> sign of my 'post 25 y.o. decline' >> >> Hmmm... I've not suffered a post 25 decline. I only sharpened through >> my 30s and 40s, but I am seeing a post 50 decline. I slow down and >> think more about what I do. lol > > At 25 y.o. I spent 3 months on the red roads of the Australian inland, a > year later only 21 days in Chile and two years later only 15 days in New > Zealand. Nowadays I can have a sore back after a night in a tent... why > should I expect my brain to have followed a different course? ;-) I give up..? Trick question? The brain develops as does the body. I can't do the things I could do at 25, but other things I do much better. I'm not willing to stop learning, but I have goals and my learning fits those goals. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Thu, 03 Oct 2013 00:20:26 -0400 Organization: A noiseless patient Spider Lines: 134 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Oct 2013 04:21:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="15033"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+BL5RfXZlJyO4rKCFEOL84" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:+DzXuMcRN+w6txBNKRgrYdWphkg= Xref: news.eternal-september.org comp.lang.vhdl:7087 On 10/2/2013 11:04 AM, Andy wrote: > On Wednesday, October 2, 2013 1:30:57 AM UTC-5, rickman wrote: >> The local/global thing is not so important in HDL the way most >> people use it. Very few designers put their entire design in >> one process with a large number of procedures. Rather the >> modularize by using multiple processes to describe the hardware >> they are designing a section at a time. When using signals they >> can only be driven validly by one process, so you get warnings, >> no, actually errors, when a signal is driven by multiple >> processes. > > Encapsulation is often less about which code can modify/drive a variable/signal than it is about which code can read it, depend on it, and quit working if it is modified. > > For example, say I have a couple of processes in an architecture. One uses a counter to step through some data, and it is not important which order it is processed, so the author decides to use an up-counter. > > Another process that can see that counter, uses that same counter's value to control something else within it, but it depends on the implementation decision in the first process to use an up-counter. > > What happens if the first process is modified to optimize the counter by converting it to a down-counter? If the counter had been a local variable, then there would be nothing outside that process that could be directly dependent upon its behavior, and changing the direction of the counter would have no impacts elsewhere. But if it is a signal, then the entire architecture has to be understood to make sure that any changes to the counter's behavior do not have an unforeseen impact. That makes no sense to me. Whether the counter implementation affects other logic depends on whether the other logic uses the value of the counter. Why wouldn't you know this if a signal is used? > Sometimes shared counters are a good thing; great, make them signals so that it is known that it is intended to be shared. Otherwise, keep it local so that it cannot be shared. Better yet, if the counter is shared among only two of the processes, put those two processes in a block, and declare the counter signal locally within the block. This protects the counter from dependencies in the other processes in the architecture. Sometimes??? A counter is part of a design, created by a designer. If the counter is intended to be shared it is shared, otherwise it is not. You are talking about a totally different situation than the OP is talking about using procedures. > Al's solution of passing state variables around between different processes is another example. Generally, state variables are pure implementation, and should not be shared. A better solution might be to define the interfaces between the procedures as explicit control (start) and status (finished) parameters, so that one procedure can be modified to change the way its FSM works, while maintaining the interface signals' functionality, and the other procedures would not be impacted. I don't follow exactly. My problem with alb's implementation is that the order of the procedure calls affects the values read by each procedure, all within *one process*. That has got to be clumsy if not impossible to make work. Or maybe I read his example wrong. If they are separate processes then they communicate by signals, no? >> The other way the global/local thing is not an issue is because >> most designers don't even use a single entity. Each entity has >> its own set of signals making them all local. > > If designers are using a single process per entity, then yes, there is no practical difference in scope between a signal and a variable. Most designers use multiple processes per entity, so there is a difference for most designers. Yeah, but I don't buy into the idea that using signals creates problems from lack of isolation. Modularization allows isolation. I use entities, you want to use processes, I don't see much difference. I put different state machines into different processes for clarity, I think you (or alb) are putting different state machines into different procedures in the same process. But I can't see how this woudl work the way he shows it with one variable for each state variable. With no isolation between the present state and next state I can't see how to code separate procedures. >> I have never wanted to add combinatorial logic to a clock process, >> I keep the combinatorial logic separate because it is... well, >> separate. This is really an issue of what you are comfortable with. >> I don't care for what are fairly subtle usages to create such logic >> in a clocked process. It will confuse many designers and is subject >> to error. > > This is a matter of how most designers are taught HDL: by examples of what kind of code structure creates what kind of circuit, and then just write concurrent islands of code that generates those circuits, and wire them up (in code). > > Sure, it is important to know what kind of circuit will be created from a certain piece of code. But the problem is, the synthesis tool is analyzing the behavior of the code, not the structure, and inferring the circuit from that behavior. The problem is that designers are taught that "code that looks like this" creates a register, and "code that looks like that" creates a combinatorial circuit. > > Designers should be taught that "code that BEHAVES like this" creates a register, etc. It is amazing to me how many different approaches to avoiding latches in RTL are based on a fundamental misunderstanding of the behavior that infers a latch (which is very similar to the behavior that creates a register). > > Design productivity can only progress so far by continuing to focus on describing the circuitry (gates and registers). To improve design productivity, we have to start designing more at the behavioral level (functions, throughput and latency). Why do you think high level synthesis tools (that can synthesize untimed models in C, etc.) are becoming so popular? I don't think it is the language as much as it is the concept of describing behavior separate from throughput and latency (those are provided to the HLS tool separately), and getting working hardware out the other end. I don't agree really. RTL doesn't describe literal registers and gates. It describes behavior at the level of registers. If you need that level of control, which many do just so they can understand what is being produced, then there is nothing wrong with RTL. Abstractions create obfuscation with the hardware produced. I often have trouble predicting and controlling the size and efficiency of a design. What you are a describing would likely make that much worse. >> Isn't this the same as 2? No, wait, you can't output variables, so you have to use signals to output anything from a clocked process, no? > > Of course, any output from a process must be a signal. But for that signal to be a combinatorial function of registered values in the same process, the registers must be inferred from variables. If you use a signal for the register in the process, you have to use a separate process for the combinatorial function. I don't have a problem with that although I would like to learn the technique better, I might end up liking it. I have seen it, but never used it. I'm usually too busy designing the circuit in my head to worry about the coding really. I just don't see problems with the coding. I'd like to be better at test benches though. There I sometimes code purely behaviorally. But only when timing is not such an issue. >> Intuitive is a nice word for "it matches my bias". If your background >> is sequential code like C, then yes, you will likely feel more >> comfortable with variables. I learned such languages, but when I >> learned HDL I was taught to describe the hardware (after all, were >> were hardware designers learning to use an HDL in place of schematics) >> and processes and signals are natural tools for that. > > Perhaps so, but my background is hardware design (analog and digital circuit cards and later, FPGAs), not SW. My first few XC3090 FPGA designs were by schematic entry. I did not immediately embrace HDL design (I actually lobbied managment against it), but once I tried it, I was hooked. My first VHDL training was for simulation, not synthesis, so maybe that too has influenced the way I use VHDL even for synthesis. Over the decades I have seen first hand the value of designing the desired behavior of a circuit, rather than describing the circuit itself. There are times where performance or synchronization still require focus on the circuit. But even for those, I tend to tweak the behavior I am describing to get the circuit I need (using RTL& Technology viewers in the synthesis tool), rather than brute-force the circuit description. There is also the issue that I don't use FPGAs and HDL every day, or any other tool for that matter. I move around enough that I want to learn a way to use a tool and then tend to stick with it so I don't have to keep relearning. The tools change enough as it is. >> I have never had an issue with running time in a simulation that didn't >> involve the amount of data being recorded rather than the simulation >> itself. But then I don't design huge FPGAs, I tend to do small designs, >> about the same complexity as you might find on a small MCU. I have a >> different approach to HDL use. My background is likely very different >> from yours. Also, my approach is widely used by the industry and so it >> well debugged in terms of the tools supporting it. I seem to have good >> productivity and my designs are solid (as long as I don't make newbie >> mistakes like I did recently where I forgot the synchronizing FF on an >> input). > > Among causes for slow simulations, using signals where variables would work is pretty low on the list of big hitters. But using lots of combinatorial processes is a much bigger hitter (gate level models are the extreme example of this). Some simulators can merge execution of processes that share the same sensitivity list, saving the overhead of separately starting and stopping the individual processes. Combinatorial processes rarely share the same sensitivities, so they are rarely combined, and the performance shows it. > >> So different horses for different courses. > > Of course! > > Andy Well, like I said, next design I do I will try the combinatorial output from a clocked process to see how I like it. Not sure when that will be. -- Rick From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.236.6.134 with SMTP id 6mr6547343yhn.7.1380791843598; Thu, 03 Oct 2013 02:17:23 -0700 (PDT) X-Received: by 10.50.110.6 with SMTP id hw6mr63461igb.13.1380791843561; Thu, 03 Oct 2013 02:17:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!q9no2850434qas.0!news-out.google.com!9ni4992qaf.0!nntp.google.com!q9no2850432qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Oct 2013 02:17:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.138.126.148; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 137.138.126.148 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> Subject: fifo reading From: revkarol Injection-Date: Thu, 03 Oct 2013 09:17:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7088 Hi, I'm trying to solve this issue with reading a fifo. I've an FSM which decides whether to read the next item in the fifo. Let's make the assumption that the fifo is never empty. I want to decide what to do with each element based on its contents. For now let's assume the elements are just 1 bit long. I have two input fifos (A and B ) and two output ports (X and Y). Here's the proposed functionality: If the element is '0', put it in X, if it's '1', put it in Y. With this logic, if both elements are the same I can only read one of them but if they're different I can read both. I can explain the problem with just one fifo. Let's say the A fifo is like this (and we read off the end): A : 0 1 1 0 Here's the problem: t | A | action ========================= 0 | 0 | set X <= A, set A_read 1 | 0 | X gets value of A, A_read goes high, unset A_read 2 | 1 | set Y <= A, A_read goes low, set A_read 3 | 1 | Y gets value of A, A_read goes high, unset A_read At t=1 A_read is still low and the fifo doesn't move along. Only at t=2 does is it high. So I'm reading at half the speed I want to. This smells like a classic problem, but I'm a bit of a noob. Any help would be appreciated. Regards, Karol. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Thu, 03 Oct 2013 17:17:46 +0200 Lines: 106 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qdhjJyVe9eweft1hI6GrVgxXzvccs846jZmCCxUdqgzffVFrsr Cancel-Lock: sha1:h+lvBQ6IGBFJ5J2S/540kw5HplY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7089 Hi Rick, On 03/10/2013 05:24, rickman wrote: [] >> I do not see what's wrong with the second procedure needing to be aware >> of the changed variable. When the second procedure runs all previous >> variables have been updated accordingly and depending on their values >> the procedure runs accordingly. > > That *is* the problem. The second procedure sees the next state rather > than the current state. That's the reason why the order of procedures matter. I let the higher FSM (the one that supposedly 'controls' everything) be the last to start and then respectively the second in rank and so on... >> To infer a register simply use the variable before it is assigned. > > I thought they were all registers? If not, they aren't state variables. They *are* registered. What I meant is that if you write this: a := a + 1; then 'a' is used before it is assigned, leading to a register. This is what happens in my fsm procedure, whether the procedure has a single case-switch which rolls over the state value, using it before assigning it. [] >> exactly the same here. In each individual FSM the inout mode in the >> parameter list is for the state parameter that the FSM will run with. >> Like in one process FSM, you do not need to formally separate the >> 'present state' and the 'next state'. > > And therein lies the problem. When using a single variable like this, > if some state variable have been updated but not others, the FSM gets > very complex. I don't get this. My state variable at each state depends on several conditions, some of them been states of another FSM (like you would have with a counter), where is the problem? > The isolated procedures for updating each state variable > in your FSM have to be aware of one another and the order in which they > are invoked. This greatly complicates the code and understanding of it. > I would find that to be impossibly difficult to use. I don't consider > this to be useful decomposition. See the following snippet of code: ------------------------------------------------------------------------------- procedure writ_read ( state_v : inout state_t; mstate_v : in mstate_t; nstate_v : in nstate_t) is begin case state_v is when IDLE => if mstate_v = START_READ or nstate_v = START_READ then state_v := READ_BGN; elsif mstate_v = START_WRITE or nstate_v = START_WRITE then state_v := WRITE_BGN; end if; when READ_BGN => state_v := READ_END; -- this is one clock cycle nRD_v := not nRD_v; when READ_END => state_v := IDLE; nRD_v := not nRD_v; DATA_v := DATA; when WRITE_BGN => state_v := WRITE_END; -- this is one clock cycle nWR_v := not nWR_v; when WRITE_END => state_v := DONE; nWR_v := not nWR_v; when DONE => state_v := IDLE; DATA_v := (others => 'Z'); -- release the bus when others => null; end case; end procedure writ_read; the 'awareness' you refer to is in the IDLE state case, where the 'if' branch reacts on the others' state variables... Being the author of this code I certainly cannot see the 'complication' that lies behind it, but please advise on how to write it *more* clear than this [1]. [] >> I've thrown Mealy and Moore definitions away long ago. I think about the >> function, not a particular implementation. >> I prefer to have registered outputs and in my case those outputs are >> described directly in the appropriate states of the FSM, whether this is >> Mealy or Moore I could care less with all due respect. > > Yes, Mealy and Moore are not often used in a strict sense, but the point > is access to the *next* value of the state rather than the current > value. This lets you get registered outputs out on *this* clock edge > rather than having them wait a clock cycle. 'this' or 'that' clock cycle does not really matter to me, latency apart I get the same throughput. From newsfish@newsfish Tue Dec 29 16:43:11 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: fifo reading Date: Thu, 03 Oct 2013 13:44:20 -0400 Organization: Alacron, Inc. Lines: 52 Message-ID: References: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Oct 2013 17:44:40 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="5570"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/fitOTVbkTu848yGOrdNhLM3qWEWkRmFk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> Cancel-Lock: sha1://FGfVAEGhvX06RBWNt/rZfZvdo= Xref: news.eternal-september.org comp.lang.vhdl:7090 revkarol wrote: > Hi, > > I'm trying to solve this issue with reading a fifo. > > I've an FSM which decides whether to read the next item in the fifo. Let's make the assumption that the fifo is never empty. > > I want to decide what to do with each element based on its contents. For now let's assume the elements are just 1 bit long. I have two input fifos (A and B ) and two output ports (X and Y). > > > Here's the proposed functionality: > If the element is '0', put it in X, if it's '1', put it in Y. With this logic, if both elements are the same I can only read one of them but if they're different I can read both. > > I can explain the problem with just one fifo. > Let's say the A fifo is like this (and we read off the end): > > A : 0 1 1 0 > > > Here's the problem: > > t | A | action > ========================= > 0 | 0 | set X <= A, set A_read > 1 | 0 | X gets value of A, A_read goes high, unset A_read > 2 | 1 | set Y <= A, A_read goes low, set A_read > 3 | 1 | Y gets value of A, A_read goes high, unset A_read > > At t=1 A_read is still low and the fifo doesn't move along. Only at t=2 does is it high. So I'm reading at half the speed I want to. > > This smells like a classic problem, but I'm a bit of a noob. > > Any help would be appreciated. > > Regards, > Karol. Normally I would sort the data into two separate streams at the input, and then write the appropriate FIFO. If you have data from two sources, either of which can go to either output on a word by word basis, then it may make sense to have a first set of FIFO's (one per source) that takes each data word with its destination tag and then a second set of FIFO's (one per destination) that feed the outputs. At the interface between the upstream (source) and downstream (destination) FIFO's you read and sort as quickly as possible, preferably running this intermediate data path at a higher clock rate to allow for cases where data comes in "clumps" for the same destination. The downstream FIFO's should be longer than the expected clumps to prevent starving the other destination. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:11 2015 X-Received: by 10.224.2.68 with SMTP id 4mr16171528qai.1.1380822639047; Thu, 03 Oct 2013 10:50:39 -0700 (PDT) X-Received: by 10.49.116.116 with SMTP id jv20mr72658qeb.35.1380822639006; Thu, 03 Oct 2013 10:50:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no3065606qak.0!news-out.google.com!9ni4233qaf.0!nntp.google.com!a6no3065598qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Oct 2013 10:50:38 -0700 (PDT) In-Reply-To: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Thu, 03 Oct 2013 17:50:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7091 On Wednesday, October 2, 2013 9:21:12 PM UTC-5, KJ wrote: > This is a weak argument. If a signal that is a counter can be 'seen' > and used for some other than the original intended purpose, then so > can a variable...you simply put the 'other' code inside that same > process and watch things not work in the same way as when the counter > is a signal. Pretending you have some sort of firewall here doesn't > make it one.=20 If you really believed this, why bother with more than one entity/architect= ure containing a single process in the entire design? That way you can easi= ly find all your signals and see how they are used, all in one file! Assuming that not all of the code is in one process per architecture, but t= hat the processes are limited in size and in purpose, then understanding wh= ere and how a variable is used is much simpler than for a signal under the = same circumstances. If someone later wants to use a variable for some other purpose, then they = have to add code to its process. This is much more likely to be noticed, an= d if not appropriate, flagged in review (speaking of design process issues.= ..) There is no firewall to prevent people from doing stupind things, only from= doing them in ways that are difficult to catch in review. You do raise a good point about capturing waveforms of variables. It sounds= like a tool issue to be solved. In the meantime, I might suggest local sig= nals declared in a block statement surrounding each process. There have also been suggestions in the past to amend the standard to allow= signals to be declared locally in a process (and therefore not visible out= side the process). That way, if you want the suspended update semantics, yo= u can have them without having to give up on encapsulation (or jump through= more hoops to keep it). Good code design standards (one of which is encapsulation) are intended to = avoid many problems before compilation, rather than waiting for a testbench= to be written to expose them in simulation, or even worse, system integrat= ion.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Thu, 03 Oct 2013 22:52:03 +0200 Lines: 16 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 42D7jVeYagpR9pQJ907b0A3L2RL3W9RVirxnN3VLxRnDFdGbL9 Cancel-Lock: sha1:B7+uXol1kPkdT062FgVjA4465i0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7092 I forgot to add a note to my previous post. On 03/10/2013 17:17, alb wrote: > the 'awareness' you refer to is in the IDLE state case, where the 'if' > branch reacts on the others' state variables... Being the author of this > code I certainly cannot see the 'complication' that lies behind it, but > please advise on how to write it *more* clear than this [1]. [1] I'm currently trying to work on a 'message passing' method which can provide a cleaner interface and increase the level of encapsulation, similar to what Andy referred to as 'explicit control (start) and status (finished) parameters'. I've followed a similar path in a C application for an embedded system and the pay off was huge. From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: fifo reading Date: Fri, 04 Oct 2013 00:25:40 +0200 Lines: 64 Message-ID: References: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net XbPt3tOBlBGb+NG3skB9twE6jPBK8r4Pt37r9DPS1O9odYVUzT Cancel-Lock: sha1:07FNdkw7IsntQLiSdVoV1pTs0l0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7093 Hi Karol, On 03/10/2013 11:17, revkarol wrote: [] > I've an FSM which decides whether to read the next item in the fifo. > Let's make the assumption that the fifo is never empty. IMO that's a very strong assumption which can prevent an easy modification of your further reasoning if it fails to be true. [] > Here's the proposed functionality: If the element is '0', put it in > X, if it's '1', put it in Y. Meaning you are willing to either lose half of the data or go at half of the speed according to data content. The first scenario does not violate your 'never empty' assumption, while it is not the case for the second one, unless your inputs are running at half the frequency your outputs can run at. > With this logic, if both elements are > the same I can only read one of them but if they're different I can > read both. I'm curious to know in your mind what will be the value of X when all data should go to Y. If you have all '1', X will be '0'? > I can explain the problem with just one fifo. Let's say the A fifo is > like this (and we read off the end): > A : 0 1 1 0 > Here's the problem: > > t | A | action > ========================= > 0 | 0 | set X <= A, set A_read > 1 | 0 | X gets value of A, A_read goes high, unset A_read > 2 | 1 | set Y <= A, A_read goes low, set A_read > 3 | 1 | Y gets value of A, A_read goes high, unset A_read > At t=1 A_read is still low and the fifo doesn't move along. Only at > t=2 does is it high. So I'm reading at half the speed I want to. If you spend one clock cycle to read the fifo and one clock cycle to evaluate whether your value should go in X or Y then yes, you are going half of the speed. You could instead read the fifo every cycle and combinatorially decide whether your output is of one kind or another: X <= A(p) and B(p); -- at least one '0' produces a '0' Y <= A(p) or B(p); -- at least one '1' produces a '1' Where p is the pointer to your data in the fifo. That is assuming that X (and respectively Y) will have a '1' when none of the bits is zero. You can add a registered output if you wish so. > This smells like a classic problem, but I'm a bit of a noob. HTH, Al From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.126.137 with SMTP id c9mr18953277qas.2.1380849016620; Thu, 03 Oct 2013 18:10:16 -0700 (PDT) X-Received: by 10.49.82.137 with SMTP id i9mr1503qey.16.1380849016564; Thu, 03 Oct 2013 18:10:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!q9no3741377qas.0!news-out.google.com!9ni7792qaf.0!nntp.google.com!q9no3741375qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Oct 2013 18:10:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: KJ Injection-Date: Fri, 04 Oct 2013 01:10:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7094 On Wednesday, October 2, 2013 9:21:12 PM UTC-5, KJ wrote:=20 > > This is a weak argument. If a signal that is a counter can be 'seen'=20 > > and used for some other than the original intended purpose, then so=20 > > can a variable...you simply put the 'other' code inside that same=20 > > process and watch things not work in the same way as when the counter= =20 > > is a signal. Pretending you have some sort of firewall here doesn't=20 > > make it one.=20 >=20 > If you really believed this, why bother with more than one entity/archite= cture containing > a single process in the entire design? That way you can easily find all y= our signals and=20 > see how they are used, all in one file!=20 >=20 You're missing your original point which I was responding to with this comm= ent. > Assuming that not all of the code is in one process per architecture, but= that the > processes are limited in size and in purpose, then understanding where an= d how a=20 > variable is used is much simpler than for a signal under the same circums= tances.=20 >=20 That's an assumption and, unless the code is very fresh in your mind a poor= one to make. Your original point was that making something a variable wou= ld somehow isolate an implementation change from rippling into some uninten= ded operation. But if you change the implementation of signal or variable = 'xyz', you need to search for every usage of 'xyz' in the entity (and beyon= d if 'xyz' is an entity output or affects an entity output) and insure you = won't break something. Thinking that just because 'xyz' is a variable will= in any limit the scope of that search is incorrect. You'll still have to = do a text search on 'xyz'. If you're not doing that, you're simply hoping = that the implementation change has no other unintended effects. > If someone later wants to use a variable for some other purpose, then the= y have to add > code to its process. This is much more likely to be noticed, and if not a= ppropriate, > flagged in review (speaking of design process issues...) >=20 I doubt it...but accept that you may have seen inappropriate usage of varia= bles being flagged in a review where similarly inappropriate usage of a sig= nal was not caught in a similar review. > There is no firewall to prevent people from doing stupind things, only fr= om doing=20 > them in ways that are difficult to catch in review.=20 >=20 Not sure what you think is a 'stupid' thing. You've already conceded that = there may be appropriate usages that violate your statement. Your suggestion was that it is somehow easier to search for 'xyz' in the pr= ocess rather than the architecture. My point is that you have to do the se= arch for 'xyz' and that you should use a tool. If the tool you're using is= simply your eyeball scan of the code (or the eyeballs of a review team) th= en you're right, but if you're using your eyeball (and the eyeball of other= s) to scan you're using the wrong tool. You should be using the search fun= ction of your text editor. When you use that tool you'll get to the "xyz n= ot found" with exactly the same effort regardless of whether 'xyz' is a sig= nal or variable and regardless of the size of the architecture being search= ed. > You do raise a good point about capturing waveforms of variables. It soun= ds like a tool > issue to be solved.=20 It is a gripe of mine too, but it doesn't seem to be a tool issue that will= go away soon. > In the meantime, I might suggest local signals declared in a block > statement surrounding each process.=20 >=20 Yep. > There have also been suggestions in the past to amend the standard to all= ow signals=20 > to be declared locally in a process (and therefore not visible outside th= e process). > That way, if you want the suspended update semantics, you can have them w= ithout having > to give up on encapsulation (or jump through more hoops to keep it).=20 >=20 And a good suggestion at that. > Good code design standards (one of which is encapsulation) are intended t= o avoid many > problems before compilation, rather than waiting for a testbench to be wr= itten to expose > them in simulation, or even worse, system integration.=20 I agree completely here, but this is off on another tangent. We simply see= m to disagree on whether the effort to check whether a change will have an = unintended effect is any different when using the most appropriate tool for= the job. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 04 Oct 2013 10:55:43 +0200 Lines: 48 Message-ID: References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Fg8Yp+4RrJGo8tNQJyrfngXR1/bGnOwS6CULr7Qbz6V3L3kiYo Cancel-Lock: sha1:P2yA8rVyWYSj1+eQlN1UWDdJLgM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7095 Hi Kevin, On 04/10/2013 03:10, KJ wrote: [] > Your original point was that making something a > variable would somehow isolate an implementation change from rippling > into some unintended operation. But if you change the implementation > of signal or variable 'xyz', you need to search for every usage of > 'xyz' in the entity (and beyond if 'xyz' is an entity output or > affects an entity output) and insure you won't break something. > Thinking that just because 'xyz' is a variable will in any limit the > scope of that search is incorrect. You'll still have to do a text > search on 'xyz'. If you're not doing that, you're simply hoping that > the implementation change has no other unintended effects. while if you have a signal 'xyz' and change its behavior you *must* verify the impact in the rest of the architecture and if needed, as you said, beyond the entity boundary, with a variable your search is limited to the process where it has been declared. Moreover, if your variable logic change does not affect the signals logic that are related to it within that process, you do not have to search beyond the process itself. Meaning you have kept the interface between processes the same, while changing the internal logic of the process, hence providing encapsulation. [] > Your suggestion was that it is somehow easier to search for 'xyz' in > the process rather than the architecture. My point is that you have > to do the search for 'xyz' and that you should use a tool. If the > tool you're using is simply your eyeball scan of the code (or the > eyeballs of a review team) then you're right, but if you're using > your eyeball (and the eyeball of others) to scan you're using the > wrong tool. You should be using the search function of your text > editor. When you use that tool you'll get to the "xyz not found" > with exactly the same effort regardless of whether 'xyz' is a signal > or variable and regardless of the size of the architecture being > searched. Having the variable local scope nobody prevents me calling all variables with the same name; I may have tens of variables all named 'cnt' but having a completely different logic for each individual process they belong too. Your tool now is in your way instead. When interfaces between processes (signals) have been defined you only need to make sure the change to the logic does not affect the interface and I'm not sure there's a tool out there (other than a simulator) to help you out. From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 04 Oct 2013 09:19:02 -0400 Organization: A noiseless patient Spider Lines: 148 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 4 Oct 2013 13:19:04 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="18520"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+em2ygHis7ywi9ic4ytFE/" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:J+IQcxBVEyH/Pyki3tXaUlCYi8w= Xref: news.eternal-september.org comp.lang.vhdl:7096 On 10/3/2013 11:17 AM, alb wrote: > Hi Rick, > > On 03/10/2013 05:24, rickman wrote: > [] >>> I do not see what's wrong with the second procedure needing to be aware >>> of the changed variable. When the second procedure runs all previous >>> variables have been updated accordingly and depending on their values >>> the procedure runs accordingly. >> >> That *is* the problem. The second procedure sees the next state rather >> than the current state. > > That's the reason why the order of procedures matter. I let the higher > FSM (the one that supposedly 'controls' everything) be the last to start > and then respectively the second in rank and so on... This is the awkward part. The way you have it written, procedures get the "next" state of variables that have been updated already and the "current" state of variables still to be updated! The current and next states of a registered variable correspond to the outputs and inputs of the register respectively. When using signals, the order of sequential statements is not important, but for variables it *is*. By partitioning the variable assignments this way you make it difficult for the designer to keep track of whether variables are in the current state or next state mode. Normally the various FSMs of a design all work on the same clock edge so the code needs to reflect that. If a signal is used it is not actually updated until after a delta cycle and so all procedures have the same input values regardless of the order called. >>> exactly the same here. In each individual FSM the inout mode in the >>> parameter list is for the state parameter that the FSM will run with. >>> Like in one process FSM, you do not need to formally separate the >>> 'present state' and the 'next state'. >> >> And therein lies the problem. When using a single variable like this, >> if some state variable have been updated but not others, the FSM gets >> very complex. > > I don't get this. My state variable at each state depends on several > conditions, some of them been states of another FSM (like you would have > with a counter), where is the problem? The problem is that in hardware each register has inputs and outputs. When you use a variable before it is assigned you are using the output of the register, when you use the variable after it has been assigned you are using the output of the logic and the input to the register. Try drawing some logic blocks (no need to actually define the gates) that implement your design. I bet either a) the resulting logic is not what you are picturing in your mind or b) the resulting logic is just not correct. >> The isolated procedures for updating each state variable >> in your FSM have to be aware of one another and the order in which they >> are invoked. This greatly complicates the code and understanding of it. >> I would find that to be impossibly difficult to use. I don't consider >> this to be useful decomposition. > > See the following snippet of code: > > > ------------------------------------------------------------------------------- > procedure writ_read ( > state_v : inout state_t; > mstate_v : in mstate_t; > nstate_v : in nstate_t) is > begin > case state_v is > when IDLE => > if mstate_v = START_READ or nstate_v = START_READ then > state_v := READ_BGN; > elsif mstate_v = START_WRITE or nstate_v = START_WRITE then > state_v := WRITE_BGN; > end if; > when READ_BGN => > state_v := READ_END; -- this is one clock cycle > nRD_v := not nRD_v; > when READ_END => > state_v := IDLE; > nRD_v := not nRD_v; > DATA_v := DATA; > when WRITE_BGN => > state_v := WRITE_END; -- this is one clock cycle > nWR_v := not nWR_v; > when WRITE_END => > state_v := DONE; > nWR_v := not nWR_v; > when DONE => > state_v := IDLE; > DATA_v := (others => 'Z'); -- release the bus > when others => null; > end case; > end procedure writ_read; > > > the 'awareness' you refer to is in the IDLE state case, where the 'if' > branch reacts on the others' state variables... Being the author of this > code I certainly cannot see the 'complication' that lies behind it, but > please advise on how to write it *more* clear than this [1]. Has mstate_v or nstate_v been updated in their procedures yet? You have to know this in order to know what value they will have. This is exactly the type of problems that happen when designers forget they are describing hardware rather than writing software. >>> I've thrown Mealy and Moore definitions away long ago. I think about the >>> function, not a particular implementation. >>> I prefer to have registered outputs and in my case those outputs are >>> described directly in the appropriate states of the FSM, whether this is >>> Mealy or Moore I could care less with all due respect. >> >> Yes, Mealy and Moore are not often used in a strict sense, but the point >> is access to the *next* value of the state rather than the current >> value. This lets you get registered outputs out on *this* clock edge >> rather than having them wait a clock cycle. > > 'this' or 'that' clock cycle does not really matter to me, latency apart > I get the same throughput. Ok, so now I understand. You don't *care* about what hardware is produced. Your design may be implemented very inefficiently, but it doesn't matter. I'm not sure if you care about latency or not. In most of my designs latency *is* an issue so I use HDL to describe the hardware rather than writing software and letting the chips fall where they may. (pun intended) Clock cycles count very much in my designs as well. Do you care about the clock speed? By using the next state value of a variable the logic created will most likely be slower than using the current state value since it is daisy chained. If you have three FSMs as in your earlier example machine C will be a function of all the inputs to FSM B as which is a function of all the inputs to FSM A and very likely result in cascaded or duplicated logic running three times slower than a design all based on the current state of a variable or signal. -- Rick From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 04 Oct 2013 09:25:25 -0400 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 4 Oct 2013 13:25:29 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="20659"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xBpLpMZSY5lYTM65uDbnJ" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:FzD3Vt+Us5jX+8D5yOQy+PJow2E= Xref: news.eternal-september.org comp.lang.vhdl:7097 On 10/3/2013 1:50 PM, Andy wrote: > > You do raise a good point about capturing waveforms of variables. It sounds like a tool issue to be solved. In the meantime, I might suggest local signals declared in a block statement surrounding each process. Variables are handled differently in simulation because they *are* different. A signal is never updated until the end of a delta cycle. Variables can be updated at any time. How do you plot a variable having three values in the same delta cycle? The ability to show signals after a simulation has started is only available if the flag to save *all* simulation data is set. This takes up a lot of disk space and makes the simulation run more slowly. No free lunches... To do this for variables would require saving a lot of additional information. -- Rick From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Fri, 04 Oct 2013 17:13:40 +0200 Lines: 204 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net V/t7vEAxYL0gOJBPYaXWFAeZ+OU2o8Tld99WQ3FFSlt6uoeseI Cancel-Lock: sha1:A1ZZ2ua8J88UNidzKNZMXDnU8IY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7098 Hi Rick, On 04/10/2013 15:19, rickman wrote: [] >>> That *is* the problem. The second procedure sees the next state rather >>> than the current state. >> >> That's the reason why the order of procedures matter. I let the higher >> FSM (the one that supposedly 'controls' everything) be the last to start >> and then respectively the second in rank and so on... > [] > When using signals, the order of sequential statements is not important, > but for variables it *is*. By partitioning the variable assignments > this way you make it difficult for the designer to keep track of whether > variables are in the current state or next state mode. Read from top to bottom, this may help. The synthesis tool seem to get it pretty straight forward. > Normally the various FSMs of a design all work on the same clock edge so > the code needs to reflect that. If a signal is used it is not actually > updated until after a delta cycle and so all procedures have the same > input values regardless of the order called. if your state depends on a value why do you bother so much if this value happens in a specific clock cycle? On top of this, I'm not thinking in terms of clock cycles, my FSM remains in a state until the other one has completed whatever it needs to complete. Timing has completely disappeared in my logic, what matters is only the functionality. [] >> I don't get this. My state variable at each state depends on several >> conditions, some of them been states of another FSM (like you would have >> with a counter), where is the problem? [] > When you use a variable before it is assigned you are using the output > of the register, when you use the variable after it has been assigned > you are using the output of the logic and the input to the register. a variable can infer both a register and a wire as I already posted: process (clk) variable something : std_logic; if rising_edge(clk) then if reset = '1' then something := '0'; else output_b <= something or input c; -- using the previous clock's value of 'something' infers a register something := input_a and input_b; -- comb. logic for a new value output_a <= something or input_c; -- which is used immediately, not registered here end if; end if; end process; while a signal in a clocked process can only generate registers. That's a flexibility I like to profit from. > Try drawing some logic blocks (no need to actually define the gates) > that implement your design. I bet either a) the resulting logic is not > what you are picturing in your mind or b) the resulting logic is just > not correct. They are three FSM with two counters and few registers, whether this is correct or not I'm not sure, that is why I simulate it. Being correct or wrong has nothing to do with the style used. >>> The isolated procedures for updating each state variable >>> in your FSM have to be aware of one another and the order in which they >>> are invoked. This greatly complicates the code and understanding of it. >>> I would find that to be impossibly difficult to use. I don't consider >>> this to be useful decomposition. >> >> See the following snippet of code: >> >> >> ------------------------------------------------------------------------------- >> >> procedure writ_read ( >> state_v : inout state_t; >> mstate_v : in mstate_t; >> nstate_v : in nstate_t) is >> begin >> case state_v is >> when IDLE => >> if mstate_v = START_READ or nstate_v = START_READ then >> state_v := READ_BGN; >> elsif mstate_v = START_WRITE or nstate_v = START_WRITE then >> state_v := WRITE_BGN; >> end if; >> when READ_BGN => >> state_v := READ_END; -- this is one clock cycle >> nRD_v := not nRD_v; >> when READ_END => >> state_v := IDLE; >> nRD_v := not nRD_v; >> DATA_v := DATA; >> when WRITE_BGN => >> state_v := WRITE_END; -- this is one clock cycle >> nWR_v := not nWR_v; >> when WRITE_END => >> state_v := DONE; >> nWR_v := not nWR_v; >> when DONE => >> state_v := IDLE; >> DATA_v := (others => 'Z'); -- release the bus >> when others => null; >> end case; >> end procedure writ_read; >> >> [] > Has mstate_v or nstate_v been updated in their procedures yet? You have > to know this in order to know what value they will have. Why should I care? When the clock will tick the state_v register will either move on or stay where it is according to the values of mstate_v or nstate_v for *that* clock cycle. I'm not thinking on *when* the state changes, I actually do not want to rely on timing since I may need to add a pipeline stage to get an operation done, while still keep the functionality in place. > > This is exactly the type of problems that happen when designers forget > they are describing hardware rather than writing software. You are certainly entitled to draw any conclusion and I do not intend to change your opinion, I can only say that I see the flops and gates as you claim you're capable to do with your style. [] >>> Yes, Mealy and Moore are not often used in a strict sense, but the point >>> is access to the *next* value of the state rather than the current >>> value. This lets you get registered outputs out on *this* clock edge >>> rather than having them wait a clock cycle. >> >> 'this' or 'that' clock cycle does not really matter to me, latency apart >> I get the same throughput. > > Ok, so now I understand. You don't *care* about what hardware is > produced. This is what you say, not me. > Your design may be implemented very inefficiently, but it > doesn't matter. In my case, area is not an issue and timing...well I can argue that if I half the clock rate I still get what I need (I'm only too late in the project phase to debate about the system clock rate!). Having said that, my code needs to be ported and extended on different FPGAs and my pure goal is readability. Writing the building blocks (procedures) to allow a more complex functionality to be added later is more important than your acclaimed inefficiency. > I'm not sure if you care about latency or not. why are you not sure? What is your point in doubting on this? > In most > of my designs latency *is* an issue so I use HDL to describe the > hardware rather than writing software and letting the chips fall where > they may. (pun intended) When latency *is* a problem than you're overall speed starts to suffer since you cannot pipeline your design. > Clock cycles count very much in my designs as well. While counting how many clock cycles there are between two operations make sense (latency), I do not see what sense makes doing the operation at the 4302423th clock cycle vs 4302424th, but again it all depends on the specs. > Do you care about the clock speed? By using the next state value of a > variable the logic created will most likely be slower than using the > current state value since it is daisy chained. Why you keep saying I'm using the 'next state'? A synchronous flop sensitive to a clock edge can *only* be sensitive to values from the past. If you manage to get it to be sensitive to values from the future I'll be interested to see it. It's a one process only, every register only reacts on a clock edge, the value of a state depends only on the value of a combination of registers which have been updated in the previous clock, certainly not in the next clock cycle. > If you have three FSMs > as in your earlier example machine C will be a function of all the > inputs to FSM B as which is a function of all the inputs to FSM A and > very likely result in cascaded or duplicated logic running three times > slower than a design all based on the current state of a variable or > signal. You are entitled to /believe/ that, I normally verify what I say with a test and if it proves me wrong or right than there's nothing else I need to believe. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.97.1 with SMTP id j1mr22749298qan.6.1380903869087; Fri, 04 Oct 2013 09:24:29 -0700 (PDT) X-Received: by 10.49.119.196 with SMTP id kw4mr41018qeb.23.1380903869039; Fri, 04 Oct 2013 09:24:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no3980254qak.0!news-out.google.com!9ni10580qaf.0!nntp.google.com!q9no4293540qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Oct 2013 09:24:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99915b5d-f384-4c86-a2cf-83a0ec628486@googlegroups.com> Subject: Re: combinational loops From: KJ Injection-Date: Fri, 04 Oct 2013 16:24:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7099 On Friday, October 4, 2013 4:55:43 AM UTC-4, alb wrote: On 04/10/2013 03:10, KJ wrote:=20 > > Your original point was that making something a=20 > > variable would somehow isolate an implementation change from rippling= =20 > > into some unintended operation. But if you change the implementation= =20 > > of signal or variable 'xyz', you need to search for every usage of=20 > > 'xyz' in the entity (and beyond if 'xyz' is an entity output or=20 > > affects an entity output) and insure you won't break something.=20 > > Thinking that just because 'xyz' is a variable will in any limit the=20 > > scope of that search is incorrect. You'll still have to do a text=20 > > search on 'xyz'. If you're not doing that, you're simply hoping that= =20 > > the implementation change has no other unintended effects.=20 >=20 >=20 > while if you have a signal 'xyz' and change its behavior you *must*=20 > verify the impact in the rest of the architecture and if needed, as you= =20 > said, beyond the entity boundary, with a variable your search is limited= =20 > to the process where it has been declared.=20 >=20 Your search does not end at the end of a process (or entity) just because y= ou use a variable. Consider the following simple statement added within a = process where 'xyz' is the variable: some_sig <=3D xyz; By your reasoning, you would not need to verify the impact of 'some_sig' si= nce 'xyz' is a local variable and cannot escape. That reasoning is incorre= ct. My only point is that the use of a *variable* does not aid you in any = way when it comes to making a change to the implementation of that variable= (i.e. changing the logic that generates the variable). I'm not debating w= hether using the variable localizes the use or whether or not using variabl= es is 'good' or not. > Moreover, if your variable logic change does not affect the signals=20 > logic that are related to it within that process, you do not have to=20 > search beyond the process itself. Meaning you have kept the interface=20 > between processes the same, while changing the internal logic of the=20 > process, hence providing encapsulation.=20 >=20 Encapulation is not the point. This sub-thread was about how supposedly us= ing a variable rather than a signal somehow provides additional protection = from some unintended functional changes when the design is modified in the = future. Already mentioned was that locally scoped signals within a block s= tatement would be equivalent in scope with a variable, but the locally scop= ed signal could still escape the block statement in exactly the same manner= as shown for a variable. Therefore, the search for dependencies would con= tinue outside the local scope whether that scope was a process or a block. =20 >=20 > Having the variable local scope nobody prevents me calling all variables= =20 > with the same name; I may have tens of variables all named 'cnt' but=20 > having a completely different logic for each individual process they=20 > belong too. Your tool now is in your way instead.=20 >=20 Might I suggest that if you have lots of variables all named the same, that= you are likely leaving a messy design trail for somebody to have to deciph= er down the road. You can also reuse a particular variable and give it com= pletely different functional definitions within a process due to the sequen= tial nature of a process...but that doesn't mean you should do things that = way. > When interfaces between processes (signals) have been defined you only=20 > need to make sure the change to the logic does not affect the interface= =20 > and I'm not sure there's a tool out there (other than a simulator) to=20 > help you out.=20 >=20 The text editor is one effective tool but yes it fails if everything is nam= ed the same and you depend on scope alone to sort it out. The dataflow win= dow in a simulator will give you precisely what you need. It will show you= all dependencies no matter they are in the entire simulation model (i.e. n= ot limited in scope by process or entity). It works with signals...not var= iables. Score another for signal and a whiff for variables. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.52.30.112 with SMTP id r16mr2071377vdh.0.1380909764697; Fri, 04 Oct 2013 11:02:44 -0700 (PDT) X-Received: by 10.50.6.98 with SMTP id z2mr412288igz.0.1380909764619; Fri, 04 Oct 2013 11:02:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!q9no4363312qas.0!news-out.google.com!9ni10580qaf.0!nntp.google.com!q9no4363284qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Oct 2013 11:02:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Fri, 04 Oct 2013 18:02:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7100 On Friday, October 4, 2013 8:19:02 AM UTC-5, rickman wrote: > When using signals, the order of sequential statements is not > important, but for variables it *is*. The order of read (access) relative to write (update) is not important, but the order of writes relative to other writes is! Consider sequential signal assignment statements in a process: count <= 0; if a then count <= count + 1; end if; if b then count <= count; -- ;^) end if; This is why I consider sequential signal assignments pseudo-sequential. Some aspects are sequential, others are not. Variable assignments are purely sequential. Andy From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Sun, 06 Oct 2013 09:55:07 -0400 Organization: A noiseless patient Spider Lines: 236 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 6 Oct 2013 13:55:22 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="2f1d56cc32a64948e21bd8c19c258ccf"; logging-data="23892"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+1Xaaikd6tytQYLcwDtMFV" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:Q1Ccm8K8Mycxc2sLJ397yHPTc80= Xref: news.eternal-september.org comp.lang.vhdl:7101 On 10/4/2013 11:13 AM, alb wrote: > Hi Rick, > > On 04/10/2013 15:19, rickman wrote: > [] >>>> That *is* the problem. The second procedure sees the next state rather >>>> than the current state. >>> >>> That's the reason why the order of procedures matter. I let the higher >>> FSM (the one that supposedly 'controls' everything) be the last to start >>> and then respectively the second in rank and so on... >> > [] >> When using signals, the order of sequential statements is not important, >> but for variables it *is*. By partitioning the variable assignments >> this way you make it difficult for the designer to keep track of whether >> variables are in the current state or next state mode. > > Read from top to bottom, this may help. The synthesis tool seem to get > it pretty straight forward. > >> Normally the various FSMs of a design all work on the same clock edge so >> the code needs to reflect that. If a signal is used it is not actually >> updated until after a delta cycle and so all procedures have the same >> input values regardless of the order called. > > if your state depends on a value why do you bother so much if this value > happens in a specific clock cycle? On top of this, I'm not thinking in > terms of clock cycles, my FSM remains in a state until the other one has > completed whatever it needs to complete. Timing has completely > disappeared in my logic, what matters is only the functionality. I *design* hardware. If I don't care when or how something happens I can use graphical tools and just skip HDL altogether... which I don't do because I find it much easier to just "do it". Why have multiple methodologies for designing FSMs when one method works, is simple to design and simple to read? >>> I don't get this. My state variable at each state depends on several >>> conditions, some of them been states of another FSM (like you would have >>> with a counter), where is the problem? > > [] >> When you use a variable before it is assigned you are using the output >> of the register, when you use the variable after it has been assigned >> you are using the output of the logic and the input to the register. > > a variable can infer both a register and a wire as I already posted: > > process (clk) > variable something : std_logic; > if rising_edge(clk) then > if reset = '1' then > something := '0'; > else > output_b<= something or input c; -- using the previous clock's > value of 'something' infers a register > something := input_a and input_b; -- comb. logic for a new value > output_a<= something or input_c; -- which is used immediately, > not registered here > end if; > end if; > end process; > > > while a signal in a clocked process can only generate registers. That's > a flexibility I like to profit from. You aren't addressing my point. You either don't know what hardware is being generated from your code or you don't care. You have indicated you don't try to control the hardware generated, so I guess that is what's going on, you don't care. I do care. I *always* want to know what hardware is generated and have control. >> Try drawing some logic blocks (no need to actually define the gates) >> that implement your design. I bet either a) the resulting logic is not >> what you are picturing in your mind or b) the resulting logic is just >> not correct. > > They are three FSM with two counters and few registers, whether this is > correct or not I'm not sure, that is why I simulate it. Being correct or > wrong has nothing to do with the style used. No but the efficiency will vary and is *very much* a function of style. > [] >> Has mstate_v or nstate_v been updated in their procedures yet? You have >> to know this in order to know what value they will have. > > Why should I care? When the clock will tick the state_v register will > either move on or stay where it is according to the values of mstate_v > or nstate_v for *that* clock cycle. I'm not thinking on *when* the state > changes, I actually do not want to rely on timing since I may need to > add a pipeline stage to get an operation done, while still keep the > functionality in place. You should care because depending on whether the variables have been updated will determine what FSM you are *actually* designing. Designing hardware without understanding what hardware is generated is a *bad* idea. >> This is exactly the type of problems that happen when designers forget >> they are describing hardware rather than writing software. > > You are certainly entitled to draw any conclusion and I do not intend to > change your opinion, I can only say that I see the flops and gates as > you claim you're capable to do with your style. But you have said you don't care how the FSMs depend on one another. If you don't care, how can you know? Much of your code will produce combinatorial logic without registers in the path. It is entirely possible with your style, if you *don't care* about the hardware, to produce a purely combinatorial path from input to output also depending on decodes of the states without realizing it. That circuit will be subject to glitching which may or may *not* show up in simulation. No, you won't change my point of view because I have looked at yours and found it wanting, no, I have found it ignoring the facts of hardware design. >>>> Yes, Mealy and Moore are not often used in a strict sense, but the point >>>> is access to the *next* value of the state rather than the current >>>> value. This lets you get registered outputs out on *this* clock edge >>>> rather than having them wait a clock cycle. >>> >>> 'this' or 'that' clock cycle does not really matter to me, latency apart >>> I get the same throughput. >> >> Ok, so now I understand. You don't *care* about what hardware is >> produced. > > This is what you say, not me. To quote you from above in the very post I am replying to... "> Why should I care?" >> Your design may be implemented very inefficiently, but it >> doesn't matter. > > In my case, area is not an issue and timing...well I can argue that if I > half the clock rate I still get what I need (I'm only too late in the > project phase to debate about the system clock rate!). > > Having said that, my code needs to be ported and extended on different > FPGAs and my pure goal is readability. Writing the building blocks > (procedures) to allow a more complex functionality to be added later is > more important than your acclaimed inefficiency. Yes, you talk about readability but you have not shown anything "unreadable" about using signals or *not* glomming all the design into one process. >> I'm not sure if you care about latency or not. > > why are you not sure? What is your point in doubting on this? > >> In most >> of my designs latency *is* an issue so I use HDL to describe the >> hardware rather than writing software and letting the chips fall where >> they may. (pun intended) > > When latency *is* a problem than you're overall speed starts to suffer > since you cannot pipeline your design. Yes, what is your point? You have said you don't try to control the hardware with your coding style, so you don't have control over any of this. >> Clock cycles count very much in my designs as well. > > While counting how many clock cycles there are between two operations > make sense (latency), I do not see what sense makes doing the operation > at the 4302423th clock cycle vs 4302424th, but again it all depends on > the specs. > >> Do you care about the clock speed? By using the next state value of a >> variable the logic created will most likely be slower than using the >> current state value since it is daisy chained. > > Why you keep saying I'm using the 'next state'? A synchronous flop > sensitive to a clock edge can *only* be sensitive to values from the > past. If you manage to get it to be sensitive to values from the future > I'll be interested to see it. Much of the logic generated by your design will depend on the "next state" logic of any variable that has been updated before the one being assigned. If you don't understand that you don't understand variable. > It's a one process only, every register only reacts on a clock edge, the > value of a state depends only on the value of a combination of registers > which have been updated in the previous clock, certainly not in the next > clock cycle. But as you have observed, variables in a process can generate combinatorial logic and that is what an updated variable has done. >> If you have three FSMs >> as in your earlier example machine C will be a function of all the >> inputs to FSM B as which is a function of all the inputs to FSM A and >> very likely result in cascaded or duplicated logic running three times >> slower than a design all based on the current state of a variable or >> signal. > > You are entitled to /believe/ that, I normally verify what I say with a > test and if it proves me wrong or right than there's nothing else I need > to believe. Ok, so take a look at your synthesis result. One of two things will result from the code you have described. If A is updated before B and B depends on A, then either B will depend on the inputs to the A register or B will duplicate all the logic that was generated for the A register. You have the code, you have the tool, let us know how it works out. I don't wish to continue to discuss this further. I believe I have completed all the explanations of my points. But I would be interested in seeing the results of your synthesis. -- Rick From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.93.19 with SMTP id t19mr43694220qam.3.1381088945806; Sun, 06 Oct 2013 12:49:05 -0700 (PDT) X-Received: by 10.50.73.39 with SMTP id i7mr645629igv.1.1381088945768; Sun, 06 Oct 2013 12:49:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no1515595qav.0!news-out.google.com!9ni17590qaf.0!nntp.google.com!i2no1515586qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Oct 2013 12:49:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.65.154.7; posting-account=AMxjgQoAAAD5ejzRqRaTARoQix_rFYKU NNTP-Posting-Host: 70.65.154.7 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60894b51-1a92-4f43-967d-623313ced6f5@googlegroups.com> Subject: How to design 4 bit 4:1 multiplexer From: Faisal Kabir Injection-Date: Sun, 06 Oct 2013 19:49:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7102 Hello below is code for 1 bit 4:1 multiplexer. Can anybody tell me how to design 4 bit from 1 bit. Thanks // 4-to-1 multiplexer. Port list is taken exactly from // the I/O diagram. module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); // Port declarations from the I/O diagram output out; input i0, i1, i2, i3; input s1, s0; // Internal wire declarations wire s1n, s0n; wire y0, y1, y2, y3; // Gate instantiations // Create s1n and s0n signals. not (s1n, s1); not (s0n, s0); // 3-input and gates instantiated and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); // 4-input or gate instantiated or (out, y0, y1, y2, y3); endmodule // Define the stimulus module (no ports) module stimulus; // Declare variables to be connected // to inputs reg IN0, IN1, IN2, IN3; reg S1, S0; // Declare output wire wire OUTPUT; // Instantiate the multiplexer mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0); // Stimulate the inputs initial begin // set input lines IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0; #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3); // choose IN0 S1 = 0; S0 = 0; #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); // choose IN1 S1 = 0; S0 = 1; #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); // choose IN2 S1 = 1; S0 = 0; #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); // choose IN3 S1 = 1; S0 = 1; #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT); end endmodule From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.58.34.169 with SMTP id a9mr3507918vej.21.1381159960938; Mon, 07 Oct 2013 08:32:40 -0700 (PDT) X-Received: by 10.49.48.38 with SMTP id i6mr1284109qen.4.1381159960918; Mon, 07 Oct 2013 08:32:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no6263575qak.0!news-out.google.com!9ni20631qaf.0!nntp.google.com!i2no2174962qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 08:32:40 -0700 (PDT) In-Reply-To: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=137.138.126.148; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 137.138.126.148 References: <8b510fbe-b8d8-4be4-963f-52b380787cdb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: fifo reading From: revkarol Injection-Date: Mon, 07 Oct 2013 15:32:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7103 Hi Gabor, Al, Thanks for the quick responses. Certainly food for thought. Al: I know the fifo will be empty sometimes. I just thought it would be easier for explanation to make the assumption that it's not. In the long run I think congestion will be my main issue, rather than what to do when idle. Gabor: I think you're right that I need a faster write on the output. So probably a dual-clock fifo is the solution. Karol. On Thursday, 3 October 2013 11:17:23 UTC+2, revkarol wrote: > Hi, > > > > I'm trying to solve this issue with reading a fifo. > > > > I've an FSM which decides whether to read the next item in the fifo. Let's make the assumption that the fifo is never empty. > > > > I want to decide what to do with each element based on its contents. For now let's assume the elements are just 1 bit long. I have two input fifos (A and B ) and two output ports (X and Y). > > > > > > Here's the proposed functionality: > > If the element is '0', put it in X, if it's '1', put it in Y. With this logic, if both elements are the same I can only read one of them but if they're different I can read both. > > > > I can explain the problem with just one fifo. > > Let's say the A fifo is like this (and we read off the end): > > > > A : 0 1 1 0 > > > > > > Here's the problem: > > > > t | A | action > > ========================= > > 0 | 0 | set X <= A, set A_read > > 1 | 0 | X gets value of A, A_read goes high, unset A_read > > 2 | 1 | set Y <= A, A_read goes low, set A_read > > 3 | 1 | Y gets value of A, A_read goes high, unset A_read > > > > At t=1 A_read is still low and the fifo doesn't move along. Only at t=2 does is it high. So I'm reading at half the speed I want to. > > > > This smells like a classic problem, but I'm a bit of a noob. > > > > Any help would be appreciated. > > > > Regards, > > Karol. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.93.19 with SMTP id t19mr52615266qam.3.1381172732894; Mon, 07 Oct 2013 12:05:32 -0700 (PDT) X-Received: by 10.49.64.72 with SMTP id m8mr94480qes.20.1381172732868; Mon, 07 Oct 2013 12:05:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2335184qav.0!news-out.google.com!9ni17512qaf.0!nntp.google.com!a6no6422231qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 12:05:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.153.152.144; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 188.153.152.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Mon, 07 Oct 2013 19:05:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7104 Hi to all! I did this filter: 128 order, with 8 bit input and 16 bit coefficients (2 complement). But i don't understand because the multiplication doesn't work. My VHDL is very simple and behavioral: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_signed.ALL; use IEEE.STD_LOGIC_arith.ALL; entity fir128 is port( input: in std_logic_vector(7 downto 0); clk : in std_logic; output: out std_logic_vector(200 downto 0) ); end fir128; architecture Behavioral of fir128 is type mult_type is array (128 downto 0) of std_logic_vector(23 downto 0); signal sig_coeff : mult_type; type add_type is array (128 downto 0) of std_logic_vector(200 downto 0); signal sig_add : add_type; type memory is array (128 downto 0) of std_logic_vector(15 downto 0); signal coeff : memory :=( "0000000000000111", "0000000000000101", "0000000000000001", "1111111111111100", "1111111111111001", "1111111111111000", "1111111111111100", "0000000000000010", "0000000000001001", "0000000000001100", "0000000000001001", "0000000000000001", "1111111111110110", "1111111111101111", "1111111111101111", "1111111111111001", "0000000000001000", "0000000000010111", "0000000000011011", "0000000000010010", "1111111111111110", "1111111111100110", "1111111111011000", "1111111111011101", "1111111111110110", "0000000000011000", "0000000000110100", "0000000000111001", "0000000000100000", "1111111111110010", "1111111111000100", "1111111110101110", "1111111111000001", "1111111111110111", "0000000000111011", "0000000001101010", "0000000001101000", "0000000000101111", "1111111111010101", "1111111110000011", "1111111101100111", "1111111110010111", "0000000000000110", "0000000010000011", "0000000011001110", "0000000010111000", "0000000000111101", "1111111110001101", "1111111011111101", "1111111011011100", "1111111101010010", "0000000000111011", "0000000100110100", "0000000110111011", "0000000101101111", "0000000001000111", "1111111010100101", "1111110101000110", "1111110011111101", "1111111001011100", "0000000101110100", "0000010110110011", "0000101000001101", "0000110101001110", "0000111010000010", "0000110101001110", "0000101000001101", "0000010110110011", "0000000101110100", "1111111001011100", "1111110011111101", "1111110101000110", "1111111010100101", "0000000001000111", "0000000101101111", "0000000110111011", "0000000100110100", "0000000000111011", "1111111101010010", "1111111011011100", "1111111011111101", "1111111110001101", "0000000000111101", "0000000010111000", "0000000011001110", "0000000010000011", "0000000000000110", "1111111110010111", "1111111101100111", "1111111110000011", "1111111111010101", "0000000000101111", "0000000001101000", "0000000001101010", "0000000000111011", "1111111111110111", "1111111111000001", "1111111110101110", "1111111111000100", "1111111111110010", "0000000000100000", "0000000000111001", "0000000000110100", "0000000000011000", "1111111111110110", "1111111111011101", "1111111111011000", "1111111111100110", "1111111111111110", "0000000000010010", "0000000000011011", "0000000000010111", "0000000000001000", "1111111111111001", "1111111111101111", "1111111111101111", "1111111111110110", "0000000000000001", "0000000000001001", "0000000000001100", "0000000000001001", "0000000000000010", "1111111111111100", "1111111111111000", "1111111111111001", "1111111111111100", "0000000000000001", "0000000000000101", "0000000000000111"); signal zero : std_logic_vector(200 downto 0):=(others=>'0'); begin process(clk) begin if clk'event and clk='1' then sig_add(128)<= zero + sig_coeff(128); for i in 128 downto 0 loop sig_coeff(i)<= input*coeff(i); if i = 0 then sig_add(0) <= sig_add(1)+sig_coeff(0); else sig_add(i-1)<=sig_add(i)+sig_coeff(i-1); end if; end loop; end if; end process; output<=sig_add(0); end Behavioral; From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.144.41 with SMTP id sj9mr7096252pab.23.1381174799704; Mon, 07 Oct 2013 12:39:59 -0700 (PDT) X-Received: by 10.50.127.229 with SMTP id nj5mr817383igb.2.1381174799643; Mon, 07 Oct 2013 12:39:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!z6no45750613pbz.1!news-out.google.com!rn2ni113391pbc.1!nntp.google.com!y3no67942903pbx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 12:39:59 -0700 (PDT) In-Reply-To: <99915b5d-f384-4c86-a2cf-83a0ec628486@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> <99915b5d-f384-4c86-a2cf-83a0ec628486@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: combinational loops From: Andy Injection-Date: Mon, 07 Oct 2013 19:39:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7105 On Friday, October 4, 2013 11:24:28 AM UTC-5, KJ wrote: > Your search does not end at the end of a process (or entity) just because > you use a variable. Consider the following simple statement added within a > process where 'xyz' is the variable: > some_sig <= xyz; > By your reasoning, you would not need to verify the impact of 'some_sig' > since 'xyz' is a local variable and cannot escape. That reasoning is > incorrect. By gosh, you're right, KJ! Whoah! This is an even bigger problem than we thought: local signals in an architecture suffer the same exact fate when assigned to a port (gasp)! Thanks to your enlightenment, we should use only one huge entity/architecture and skip all this useless hierarchical encapsulation window-dressing, to nip this problem in the bud! Seriously, exporting a variable by assignment to a signal is just another of the variable's "uses" that must be considered when modifying the variable. Andy From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.68.218.163 with SMTP id ph3mr5407154pbc.5.1381175016643; Mon, 07 Oct 2013 12:43:36 -0700 (PDT) X-Received: by 10.49.48.38 with SMTP id i6mr1353157qen.4.1381175016220; Mon, 07 Oct 2013 12:43:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no45757654pbz.1!news-out.google.com!z6ni82374pbu.0!nntp.google.com!z6no45757648pbz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 12:43:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.153.152.144; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 188.153.152.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Mon, 07 Oct 2013 19:43:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7106 Il giorno luned=EC 7 ottobre 2013 21:05:32 UTC+2, Ste_ee ha scritto: > Hi to all! I did this filter: 128 order, with 8 bit input and 16 bit coef= ficients (2 complement). >=20 > But i don't understand because the multiplication doesn't work. My VHDL i= s very simple and behavioral: >=20 >=20 >=20 > library IEEE; >=20 > use IEEE.STD_LOGIC_1164.ALL; >=20 > use IEEE.STD_LOGIC_signed.ALL; >=20 > use IEEE.STD_LOGIC_arith.ALL; >=20 >=20 >=20 > entity fir128 is >=20 > port( >=20 > input: in std_logic_vector(7 downto 0); >=20 > clk : in std_logic; >=20 > output: out std_logic_vector(200 downto 0) >=20 > ); >=20 > end fir128; >=20 >=20 >=20 > architecture Behavioral of fir128 is >=20 >=20 >=20 > type mult_type is array (128 downto 0) of std_logic_vector(23 downto 0); >=20 > signal sig_coeff : mult_type; >=20 >=20 >=20 > type add_type is array (128 downto 0) of std_logic_vector(200 downto 0); >=20 > signal sig_add : add_type; >=20 >=20 >=20 > type memory is array (128 downto 0) of std_logic_vector(15 downto 0); =09 >=20 > signal coeff : memory :=3D(=20 >=20 > "0000000000000111", >=20 > "0000000000000101", >=20 > "0000000000000001", >=20 > "1111111111111100", >=20 > "1111111111111001", >=20 > "1111111111111000", >=20 > "1111111111111100", >=20 > "0000000000000010", >=20 > "0000000000001001", >=20 > "0000000000001100", >=20 > "0000000000001001", >=20 > "0000000000000001", >=20 > "1111111111110110", >=20 > "1111111111101111", >=20 > "1111111111101111", >=20 > "1111111111111001", >=20 > "0000000000001000", >=20 > "0000000000010111", >=20 > "0000000000011011", >=20 > "0000000000010010", >=20 > "1111111111111110", >=20 > "1111111111100110", >=20 > "1111111111011000", >=20 > "1111111111011101", >=20 > "1111111111110110", >=20 > "0000000000011000", >=20 > "0000000000110100", >=20 > "0000000000111001", >=20 > "0000000000100000", >=20 > "1111111111110010", >=20 > "1111111111000100", >=20 > "1111111110101110", >=20 > "1111111111000001", >=20 > "1111111111110111", >=20 > "0000000000111011", >=20 > "0000000001101010", >=20 > "0000000001101000", >=20 > "0000000000101111", >=20 > "1111111111010101", >=20 > "1111111110000011", >=20 > "1111111101100111", >=20 > "1111111110010111", >=20 > "0000000000000110", >=20 > "0000000010000011", >=20 > "0000000011001110", >=20 > "0000000010111000", >=20 > "0000000000111101", >=20 > "1111111110001101", >=20 > "1111111011111101", >=20 > "1111111011011100", >=20 > "1111111101010010", >=20 > "0000000000111011", >=20 > "0000000100110100", >=20 > "0000000110111011", >=20 > "0000000101101111", >=20 > "0000000001000111", >=20 > "1111111010100101", >=20 > "1111110101000110", >=20 > "1111110011111101", >=20 > "1111111001011100", >=20 > "0000000101110100", >=20 > "0000010110110011", >=20 > "0000101000001101", >=20 > "0000110101001110", >=20 > "0000111010000010", >=20 > "0000110101001110", >=20 > "0000101000001101", >=20 > "0000010110110011", >=20 > "0000000101110100", >=20 > "1111111001011100", >=20 > "1111110011111101", >=20 > "1111110101000110", >=20 > "1111111010100101", >=20 > "0000000001000111", >=20 > "0000000101101111", >=20 > "0000000110111011", >=20 > "0000000100110100", >=20 > "0000000000111011", >=20 > "1111111101010010", >=20 > "1111111011011100", >=20 > "1111111011111101", >=20 > "1111111110001101", >=20 > "0000000000111101", >=20 > "0000000010111000", >=20 > "0000000011001110", >=20 > "0000000010000011", >=20 > "0000000000000110", >=20 > "1111111110010111", >=20 > "1111111101100111", >=20 > "1111111110000011", >=20 > "1111111111010101", >=20 > "0000000000101111", >=20 > "0000000001101000", >=20 > "0000000001101010", >=20 > "0000000000111011", >=20 > "1111111111110111", >=20 > "1111111111000001", >=20 > "1111111110101110", >=20 > "1111111111000100", >=20 > "1111111111110010", >=20 > "0000000000100000", >=20 > "0000000000111001", >=20 > "0000000000110100", >=20 > "0000000000011000", >=20 > "1111111111110110", >=20 > "1111111111011101", >=20 > "1111111111011000", >=20 > "1111111111100110", >=20 > "1111111111111110", >=20 > "0000000000010010", >=20 > "0000000000011011", >=20 > "0000000000010111", >=20 > "0000000000001000", >=20 > "1111111111111001", >=20 > "1111111111101111", >=20 > "1111111111101111", >=20 > "1111111111110110", >=20 > "0000000000000001", >=20 > "0000000000001001", >=20 > "0000000000001100", >=20 > "0000000000001001", >=20 > "0000000000000010", >=20 > "1111111111111100", >=20 > "1111111111111000", >=20 > "1111111111111001", >=20 > "1111111111111100", >=20 > "0000000000000001", >=20 > "0000000000000101", >=20 > "0000000000000111"); >=20 >=20 >=20 >=20 >=20 > signal zero : std_logic_vector(200 downto 0):=3D(others=3D>'0'); >=20 > =09 >=20 > begin >=20 > process(clk) >=20 > begin >=20 >=20 >=20 > if clk'event and clk=3D'1' then >=20 > sig_add(128)<=3D zero + sig_coeff(128); >=20 >=20 >=20 > for i in 128 downto 0 loop >=20 >=20 >=20 > sig_coeff(i)<=3D input*coeff(i); >=20 >=20 >=20 > if i =3D 0 then >=20 > sig_add(0) <=3D sig_add(1)+sig_coeff(0); >=20 > else >=20 > sig_add(i-1)<=3Dsig_add(i)+sig_coeff(i-1); >=20 > end if; >=20 > =09 >=20 > end loop; >=20 > end if; >=20 > end process; >=20 >=20 >=20 > output<=3Dsig_add(0); >=20 > =09 >=20 > end Behavioral; I changed with this, but output is ever X. for i in 128 downto 0 loop sig_coeff(i)<=3D input*coeff(i); if i =3D 128 then sig_add(128)<=3D zero + sig_coeff(128); else sig_add(i)<=3Dsig_add(i+1)+sig_coeff(i); end if; From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.102.100 with SMTP id fn4mr680794pab.47.1381175747903; Mon, 07 Oct 2013 12:55:47 -0700 (PDT) X-Received: by 10.49.133.225 with SMTP id pf1mr1313744qeb.6.1381175747842; Mon, 07 Oct 2013 12:55:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y3no67971874pbx.0!news-out.google.com!rn2ni113391pbc.1!nntp.google.com!y3no67971867pbx.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 12:55:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.153.152.144; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 188.153.152.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Mon, 07 Oct 2013 19:55:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7107 Il giorno luned=EC 7 ottobre 2013 21:05:32 UTC+2, Ste_ee ha scritto: > Hi to all! I did this filter: 128 order, with 8 bit input and 16 bit coef= ficients (2 complement). >=20 > But i don't understand because the multiplication doesn't work. My VHDL i= s very simple and behavioral: >=20 >=20 >=20 > library IEEE; >=20 > use IEEE.STD_LOGIC_1164.ALL; >=20 > use IEEE.STD_LOGIC_signed.ALL; >=20 > use IEEE.STD_LOGIC_arith.ALL; >=20 >=20 >=20 > entity fir128 is >=20 > port( >=20 > input: in std_logic_vector(7 downto 0); >=20 > clk : in std_logic; >=20 > output: out std_logic_vector(200 downto 0) >=20 > ); >=20 > end fir128; >=20 >=20 >=20 > architecture Behavioral of fir128 is >=20 >=20 >=20 > type mult_type is array (128 downto 0) of std_logic_vector(23 downto 0); >=20 > signal sig_coeff : mult_type; >=20 >=20 >=20 > type add_type is array (128 downto 0) of std_logic_vector(200 downto 0); >=20 > signal sig_add : add_type; >=20 >=20 >=20 > type memory is array (128 downto 0) of std_logic_vector(15 downto 0); =09 >=20 > signal coeff : memory :=3D(=20 >=20 > "0000000000000111", >=20 > "0000000000000101", >=20 > "0000000000000001", >=20 > "1111111111111100", >=20 > "1111111111111001", >=20 > "1111111111111000", >=20 > "1111111111111100", >=20 > "0000000000000010", >=20 > "0000000000001001", >=20 > "0000000000001100", >=20 > "0000000000001001", >=20 > "0000000000000001", >=20 > "1111111111110110", >=20 > "1111111111101111", >=20 > "1111111111101111", >=20 > "1111111111111001", >=20 > "0000000000001000", >=20 > "0000000000010111", >=20 > "0000000000011011", >=20 > "0000000000010010", >=20 > "1111111111111110", >=20 > "1111111111100110", >=20 > "1111111111011000", >=20 > "1111111111011101", >=20 > "1111111111110110", >=20 > "0000000000011000", >=20 > "0000000000110100", >=20 > "0000000000111001", >=20 > "0000000000100000", >=20 > "1111111111110010", >=20 > "1111111111000100", >=20 > "1111111110101110", >=20 > "1111111111000001", >=20 > "1111111111110111", >=20 > "0000000000111011", >=20 > "0000000001101010", >=20 > "0000000001101000", >=20 > "0000000000101111", >=20 > "1111111111010101", >=20 > "1111111110000011", >=20 > "1111111101100111", >=20 > "1111111110010111", >=20 > "0000000000000110", >=20 > "0000000010000011", >=20 > "0000000011001110", >=20 > "0000000010111000", >=20 > "0000000000111101", >=20 > "1111111110001101", >=20 > "1111111011111101", >=20 > "1111111011011100", >=20 > "1111111101010010", >=20 > "0000000000111011", >=20 > "0000000100110100", >=20 > "0000000110111011", >=20 > "0000000101101111", >=20 > "0000000001000111", >=20 > "1111111010100101", >=20 > "1111110101000110", >=20 > "1111110011111101", >=20 > "1111111001011100", >=20 > "0000000101110100", >=20 > "0000010110110011", >=20 > "0000101000001101", >=20 > "0000110101001110", >=20 > "0000111010000010", >=20 > "0000110101001110", >=20 > "0000101000001101", >=20 > "0000010110110011", >=20 > "0000000101110100", >=20 > "1111111001011100", >=20 > "1111110011111101", >=20 > "1111110101000110", >=20 > "1111111010100101", >=20 > "0000000001000111", >=20 > "0000000101101111", >=20 > "0000000110111011", >=20 > "0000000100110100", >=20 > "0000000000111011", >=20 > "1111111101010010", >=20 > "1111111011011100", >=20 > "1111111011111101", >=20 > "1111111110001101", >=20 > "0000000000111101", >=20 > "0000000010111000", >=20 > "0000000011001110", >=20 > "0000000010000011", >=20 > "0000000000000110", >=20 > "1111111110010111", >=20 > "1111111101100111", >=20 > "1111111110000011", >=20 > "1111111111010101", >=20 > "0000000000101111", >=20 > "0000000001101000", >=20 > "0000000001101010", >=20 > "0000000000111011", >=20 > "1111111111110111", >=20 > "1111111111000001", >=20 > "1111111110101110", >=20 > "1111111111000100", >=20 > "1111111111110010", >=20 > "0000000000100000", >=20 > "0000000000111001", >=20 > "0000000000110100", >=20 > "0000000000011000", >=20 > "1111111111110110", >=20 > "1111111111011101", >=20 > "1111111111011000", >=20 > "1111111111100110", >=20 > "1111111111111110", >=20 > "0000000000010010", >=20 > "0000000000011011", >=20 > "0000000000010111", >=20 > "0000000000001000", >=20 > "1111111111111001", >=20 > "1111111111101111", >=20 > "1111111111101111", >=20 > "1111111111110110", >=20 > "0000000000000001", >=20 > "0000000000001001", >=20 > "0000000000001100", >=20 > "0000000000001001", >=20 > "0000000000000010", >=20 > "1111111111111100", >=20 > "1111111111111000", >=20 > "1111111111111001", >=20 > "1111111111111100", >=20 > "0000000000000001", >=20 > "0000000000000101", >=20 > "0000000000000111"); >=20 >=20 >=20 >=20 >=20 > signal zero : std_logic_vector(200 downto 0):=3D(others=3D>'0'); >=20 > =09 >=20 > begin >=20 > process(clk) >=20 > begin >=20 >=20 >=20 > if clk'event and clk=3D'1' then >=20 > sig_add(128)<=3D zero + sig_coeff(128); >=20 >=20 >=20 > for i in 128 downto 0 loop >=20 >=20 >=20 > sig_coeff(i)<=3D input*coeff(i); >=20 >=20 >=20 > if i =3D 0 then >=20 > sig_add(0) <=3D sig_add(1)+sig_coeff(0); >=20 > else >=20 > sig_add(i-1)<=3Dsig_add(i)+sig_coeff(i-1); >=20 > end if; >=20 > =09 >=20 > end loop; >=20 > end if; >=20 > end process; >=20 >=20 >=20 > output<=3Dsig_add(0); >=20 > =09 >=20 > end Behavioral; The input is "impulse": stim_proc: process begin =09 input<=3D(others=3D>'0'); wait for 10 ns; input<=3D"00000001"; wait for 10 ns; input<=3D(others=3D>'0'); wait; end process; From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.162.134 with SMTP id ya6mr98703pab.7.1381194497589; Mon, 07 Oct 2013 18:08:17 -0700 (PDT) X-Received: by 10.50.111.200 with SMTP id ik8mr870567igb.7.1381194497141; Mon, 07 Oct 2013 18:08:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!z6no46256176pbz.1!news-out.google.com!z6ni82918pbu.0!nntp.google.com!i2no2372431qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 18:08:16 -0700 (PDT) In-Reply-To: <60894b51-1a92-4f43-967d-623313ced6f5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: <60894b51-1a92-4f43-967d-623313ced6f5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b774db3-b490-474c-9381-9060e1f9cd71@googlegroups.com> Subject: Re: How to design 4 bit 4:1 multiplexer From: Jim Lewis Injection-Date: Tue, 08 Oct 2013 01:08:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7108 Simple, use type std_logic_vector on your ports rather than std_logic. :). Try comp.lang.verilog for an answer in Verilog. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.168.198 with SMTP id zy6mr6766pab.46.1381198961283; Mon, 07 Oct 2013 19:22:41 -0700 (PDT) X-Received: by 10.182.246.133 with SMTP id xw5mr59obc.14.1381198960716; Mon, 07 Oct 2013 19:22:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!y3no68529088pbx.0!news-out.google.com!z6ni82918pbu.0!nntp.google.com!i2no2390554qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Oct 2013 19:22:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <26f48274-b635-4745-852f-f0c249189614@googlegroups.com> <99915b5d-f384-4c86-a2cf-83a0ec628486@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <44c1b3b4-060b-4744-9532-3ce9d90cc310@googlegroups.com> Subject: Re: combinational loops From: KJ Injection-Date: Tue, 08 Oct 2013 02:22:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7109 On Friday, October 4, 2013 11:24:28 AM UTC-5, KJ wrote: > > Your search does not end at the end of a process (or entity) just because > > you use a variable. Consider the following simple statement added within a > > process where 'xyz' is the variable: > > some_sig <= xyz; > > By your reasoning, you would not need to verify the impact of 'some_sig' > > since 'xyz' is a local variable and cannot escape. That reasoning is > > incorrect. > > > By gosh, you're right, KJ! > > Whoah! This is an even bigger problem than we thought: local signals in an architecture suffer the same exact fate when assigned to a port (gasp)! > Glad I could help clear this up for you Andy. > Thanks to your enlightenment, we should use only one huge entity/architecture and skip all this useless hierarchical encapsulation window-dressing, to nip this problem in the bud! > Note that you are on the only one in this thread that has suggested "huge entity/architecture" or "skip all this useless hierarchical encapsulation" so on this point you're nipping your own bud. > > Seriously, exporting a variable by assignment to a signal is just another of the variable's "uses" that must be considered when modifying the variable. > Thanks for the update Captain Obvious. Report back soon, love to hear from you. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.125.72 with SMTP id x8mr5761128qar.5.1381244670622; Tue, 08 Oct 2013 08:04:30 -0700 (PDT) X-Received: by 10.49.94.41 with SMTP id cz9mr24938qeb.26.1381244670603; Tue, 08 Oct 2013 08:04:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2538802qav.0!news-out.google.com!9ni21583qaf.0!nntp.google.com!a6no6619258qak.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Oct 2013 08:04:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: 1999outback@gmail.com Injection-Date: Tue, 08 Oct 2013 15:04:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7110 Some comments: 1. Replace IEEE.STD_LOGIC_signed.ALL and IEEE.STD_LOGIC_arith.ALL (generall= y considered evil) with ieee.numeric_std.all, and used the signed type inst= ead of std_logic_vector. See www.gstitt.ece.ufl.edu/vhdl/refs/vhdl_math_tri= cks_mapld_2003.pdf for more info. 2. sig_add(128)<=3D zero + sig_coeff(128) doesn't add any value. 3. 201 significant bits for intermediate values and the result (from an 8-b= it input and 16-bit coefficients) are way overkill. 4. It looks like you're trying to do this in one clock cycle, but signals d= on't get updated until the process suspends, so in this case it will take 1= 29 clock cycles to get the wrong answer. 5. There is no input delay chain - there should be a shift register or othe= r memory that stores inputs, then multiply input(0..128) * coeff(0..128). 6. If this is not a homework assignment, have you considered using a FIR co= re? From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.126.137 with SMTP id c9mr6564516qas.2.1381246992614; Tue, 08 Oct 2013 08:43:12 -0700 (PDT) X-Received: by 10.182.243.131 with SMTP id wy3mr2591obc.17.1381246992477; Tue, 08 Oct 2013 08:43:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2544442qav.0!news-out.google.com!9ni21544qaf.0!nntp.google.com!i2no2544432qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Oct 2013 08:43:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: 1999outback@gmail.com Injection-Date: Tue, 08 Oct 2013 15:43:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7111 On Tuesday, October 8, 2013 11:04:30 AM UTC-4, 1999o...@gmail.com wrote: > Some comments: >=20 >=20 >=20 > 1. Replace IEEE.STD_LOGIC_signed.ALL and IEEE.STD_LOGIC_arith.ALL (genera= lly considered evil) with ieee.numeric_std.all, and used the signed type in= stead of std_logic_vector. See www.gstitt.ece.ufl.edu/vhdl/refs/vhdl_math_t= ricks_mapld_2003.pdf for more info. >=20 >=20 >=20 > 2. sig_add(128)<=3D zero + sig_coeff(128) doesn't add any value. >=20 >=20 >=20 > 3. 201 significant bits for intermediate values and the result (from an 8= -bit input and 16-bit coefficients) are way overkill. >=20 >=20 >=20 > 4. It looks like you're trying to do this in one clock cycle, but signals= don't get updated until the process suspends, so in this case it will take= 129 clock cycles to get the wrong answer. >=20 >=20 >=20 > 5. There is no input delay chain - there should be a shift register or ot= her memory that stores inputs, then multiply input(0..128) * coeff(0..128). >=20 >=20 >=20 > 6. If this is not a homework assignment, have you considered using a FIR = core? Sorry - I didn't read the subject and see that it's a transposed form filte= r. In #5 the delay chain is not at the input, but at the multiplication res= ults. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.182.153.35 with SMTP id vd3mr465173obb.37.1381253725286; Tue, 08 Oct 2013 10:35:25 -0700 (PDT) X-Received: by 10.50.44.67 with SMTP id c3mr124686igm.13.1381253724996; Tue, 08 Oct 2013 10:35:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.88.MISMATCH!i2no2559921qav.0!news-out.google.com!9ni21585qaf.0!nntp.google.com!i2no2559916qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Oct 2013 10:35:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=93.144.143.7; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 93.144.143.7 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Tue, 08 Oct 2013 17:35:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7112 Il giorno marted=EC 8 ottobre 2013 17:43:12 UTC+2, 1999o...@gmail.com ha sc= ritto: > On Tuesday, October 8, 2013 11:04:30 AM UTC-4, 1999o...@gmail.com wrote: >=20 > > Some comments: >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 1. Replace IEEE.STD_LOGIC_signed.ALL and IEEE.STD_LOGIC_arith.ALL (gene= rally considered evil) with ieee.numeric_std.all, and used the signed type = instead of std_logic_vector. See www.gstitt.ece.ufl.edu/vhdl/refs/vhdl_math= _tricks_mapld_2003.pdf for more info. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 2. sig_add(128)<=3D zero + sig_coeff(128) doesn't add any value. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 3. 201 significant bits for intermediate values and the result (from an= 8-bit input and 16-bit coefficients) are way overkill. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 4. It looks like you're trying to do this in one clock cycle, but signa= ls don't get updated until the process suspends, so in this case it will ta= ke 129 clock cycles to get the wrong answer. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 5. There is no input delay chain - there should be a shift register or = other memory that stores inputs, then multiply input(0..128) * coeff(0..128= ). >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > 6. If this is not a homework assignment, have you considered using a FI= R core? >=20 >=20 >=20 > Sorry - I didn't read the subject and see that it's a transposed form fil= ter. In #5 the delay chain is not at the input, but at the multiplication r= esults. Thank you for answer! True, the signals get update out of process. The filter is for exam of laboratory and FIR Core would be too easy, and i = don't learn :). Unfortunately there isn't an exam about signal processing, then i don't und= erstand how will the better size of adders. At the output of filter there i= s generally a DAC, but it hasn't 30, 40 bit in input.Then i have to truncat= e the data?=20 But i believe there is already 1 FF after the multiplication.=20 For first thing i will try to insert the delay chain on input and i will le= t you know!! From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.111.201 with SMTP id t9mr12297556qap.8.1381310554317; Wed, 09 Oct 2013 02:22:34 -0700 (PDT) X-Received: by 10.50.8.42 with SMTP id o10mr53977iga.3.1381310554287; Wed, 09 Oct 2013 02:22:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no6785470qak.0!news-out.google.com!9ni22252qaf.0!nntp.google.com!i2no2711490qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2013 02:22:33 -0700 (PDT) In-Reply-To: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=160.80.235.244; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 160.80.235.244 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Wed, 09 Oct 2013 09:22:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7113 Il giorno marted=EC 8 ottobre 2013 19:35:24 UTC+2, Ste_ee ha scritto: > Il giorno marted=EC 8 ottobre 2013 17:43:12 UTC+2, 1999o...@gmail.com ha = scritto: >=20 > > On Tuesday, October 8, 2013 11:04:30 AM UTC-4, 1999o...@gmail.com wrote= : >=20 > >=20 >=20 > > > Some comments: >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 1. Replace IEEE.STD_LOGIC_signed.ALL and IEEE.STD_LOGIC_arith.ALL (ge= nerally considered evil) with ieee.numeric_std.all, and used the signed typ= e instead of std_logic_vector. See www.gstitt.ece.ufl.edu/vhdl/refs/vhdl_ma= th_tricks_mapld_2003.pdf for more info. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 2. sig_add(128)<=3D zero + sig_coeff(128) doesn't add any value. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 3. 201 significant bits for intermediate values and the result (from = an 8-bit input and 16-bit coefficients) are way overkill. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 4. It looks like you're trying to do this in one clock cycle, but sig= nals don't get updated until the process suspends, so in this case it will = take 129 clock cycles to get the wrong answer. >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 5. There is no input delay chain - there should be a shift register o= r other memory that stores inputs, then multiply input(0..128) * coeff(0..1= 28). >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > >=20 >=20 > >=20 >=20 > > > 6. If this is not a homework assignment, have you considered using a = FIR core? >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Sorry - I didn't read the subject and see that it's a transposed form f= ilter. In #5 the delay chain is not at the input, but at the multiplication= results. >=20 >=20 >=20 > Thank you for answer! >=20 > True, the signals get update out of process. >=20 > The filter is for exam of laboratory and FIR Core would be too easy, and = i don't learn :). >=20 > Unfortunately there isn't an exam about signal processing, then i don't u= nderstand how will the better size of adders. At the output of filter there= is generally a DAC, but it hasn't 30, 40 bit in input.Then i have to trunc= ate the data?=20 >=20 > But i believe there is already 1 FF after the multiplication.=20 >=20 > For first thing i will try to insert the delay chain on input and i will = let you know!! I tried to implement delay chain after multiplication, but i see always the= first 3 coefficients and then 0. The adders don't work..i don't know.. i t= ried the delay chain on input too, but nothing.Look this: process(clk) begin if clk'event and clk=3D'1' then for i in 127 downto 0 loop sig_coeff(i)<=3D input*coeff(i); =09 delaymult1(i)<=3Dsig_coeff(i); delaymult2(i)<=3Ddelaymult1(i); =09 if i =3D 127 then sig_add(i)<=3D "000000000"& delaymult2(i); else sig_add(i)<=3Dsig_add(i+1)+delaymult2(i); =09 end if; end loop; end if; end process; output<=3Dadd(0); From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.51.68 with SMTP id c4mr13247423qag.7.1381320366572; Wed, 09 Oct 2013 05:06:06 -0700 (PDT) X-Received: by 10.49.104.83 with SMTP id gc19mr6828qeb.12.1381320366557; Wed, 09 Oct 2013 05:06:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a6no6858246qak.0!news-out.google.com!9ni22252qaf.0!nntp.google.com!i2no2785107qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2013 05:06:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8afa9314-bcb7-4984-8be8-9d0e81f9cd2f@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: 1999outback@gmail.com Injection-Date: Wed, 09 Oct 2013 12:06:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7114 You may have been closer in your 2nd post, but it looks like you have too m= any delay elements, not too few! In the addition, you want to add the immed= iate result of the multiplication with the delayed result of the neighborin= g multiplication, however since both operands are flip-flip outputs it does= n't look like you're doing that. Either directly use the multiplication res= ult (instead of storing it in a signal), or use a variable for the multipli= cation result, which will not create a register if it's assigned before it'= s used (google or look in your textbook for variables vs. signals). For the bit widths, it sounds like you haven't learned that yet, but I'm no= t sure how much help I can be since I've always had the luxury of using FPG= A cores or DSP software libraries. However, some things to look at or try: 1. Notice what happens when you multiply 2's complement integer numbers (tr= y it with all combinations of positive/negative maximum values): you get 2 = sign bits, feel free to throw one away, or use a fixed point library (googl= e "vhdl fixed point"). 2. Put you coefficient into a spreadsheet and multiply each positive coeffi= cient by the maximum positive input and each negative coefficient by the ma= ximum negative input, then sum the results, that will give you the worst-ca= se (though unlikely) # of bits required. Usually coefficients are scaled su= ch that the worst-case result is the sum of the number of input + coefficie= nt bits, or in your case 24. Try it first though, as I could be completely = wrong. For your DAC output, yes, truncate the data using the most significa= nt relevant bits. Other notes: if you reset the registers you can start seeing valid data (th= e impulse response which will be the coefficients) immediately, as opposed = to 128 clock cycles of invalid data. Are you running the simulation long en= ough? From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.224.51.68 with SMTP id c4mr13258674qag.7.1381320492866; Wed, 09 Oct 2013 05:08:12 -0700 (PDT) X-Received: by 10.49.116.145 with SMTP id jw17mr1157qeb.25.1381320492853; Wed, 09 Oct 2013 05:08:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2786052qav.0!news-out.google.com!9ni22252qaf.0!nntp.google.com!i2no2786050qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2013 05:08:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: 1999outback@gmail.com Injection-Date: Wed, 09 Oct 2013 12:08:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7115 You may have been closer in your 2nd post, but it looks like you have too m= any delay elements, not too few! In the addition, you want to add the immed= iate result of the multiplication with the delayed result of the neighborin= g multiplication, however since both operands are flip-flip outputs it does= n't look like you're doing that. Either directly use the multiplication res= ult (instead of storing it in a signal), or use a variable for the multipli= cation result, which will not create a register if it's assigned before it'= s used (google or look in your textbook for variables vs. signals). For the bit widths, it sounds like you haven't learned that yet, but I'm no= t sure how much help I can be since I've always had the luxury of using FPG= A cores or DSP software libraries. However, some things to look at or try: 1. Notice what happens when you multiply 2's complement integer numbers (tr= y it with all combinations of positive/negative maximum values): you get 2 = sign bits, feel free to throw one away, or use a fixed point library (googl= e "vhdl fixed point"). 2. Put your coefficients into a spreadsheet and multiply each positive coef= ficient by the maximum positive input and each negative coefficient by the = maximum negative input, then sum the results, that will give you the worst-= case (though unlikely) # of bits required. Usually coefficients are scaled = such that the worst-case result is the sum of the number of input + coeffic= ient bits, or in your case 24. Try it first though, as I could be completel= y wrong. For your DAC output, yes, truncate the data using the most signifi= cant relevant bits. Other notes: if you reset the registers you can start seeing valid data (th= e impulse response which will be the coefficients) immediately, as opposed = to 128 clock cycles of invalid data. Are you running the simulation long en= ough? From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.221.137 with SMTP id qe9mr2800769pac.4.1381345032203; Wed, 09 Oct 2013 11:57:12 -0700 (PDT) X-Received: by 10.50.85.50 with SMTP id e18mr29259igz.9.1381345032105; Wed, 09 Oct 2013 11:57:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no49558958pbz.1!news-out.google.com!9ni23764qaf.0!nntp.google.com!i2no3105134qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Oct 2013 11:57:11 -0700 (PDT) In-Reply-To: <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=93.144.165.231; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 93.144.165.231 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d0e105c-521a-4259-830e-8207926a291b@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Wed, 09 Oct 2013 18:57:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7116 Il giorno mercoled=EC 9 ottobre 2013 14:08:12 UTC+2, 1999o...@gmail.com ha = scritto: > You may have been closer in your 2nd post, but it looks like you have too= many delay elements, not too few! In the addition, you want to add the imm= ediate result of the multiplication with the delayed result of the neighbor= ing multiplication, however since both operands are flip-flip outputs it do= esn't look like you're doing that. Either directly use the multiplication r= esult (instead of storing it in a signal), or use a variable for the multip= lication result, which will not create a register if it's assigned before i= t's used (google or look in your textbook for variables vs. signals). >=20 >=20 >=20 > For the bit widths, it sounds like you haven't learned that yet, but I'm = not sure how much help I can be since I've always had the luxury of using F= PGA cores or DSP software libraries. However, some things to look at or try= : >=20 > 1. Notice what happens when you multiply 2's complement integer numbers (= try it with all combinations of positive/negative maximum values): you get = 2 sign bits, feel free to throw one away, or use a fixed point library (goo= gle "vhdl fixed point"). >=20 > 2. Put your coefficients into a spreadsheet and multiply each positive co= efficient by the maximum positive input and each negative coefficient by th= e maximum negative input, then sum the results, that will give you the wors= t-case (though unlikely) # of bits required. Usually coefficients are scale= d such that the worst-case result is the sum of the number of input + coeff= icient bits, or in your case 24. Try it first though, as I could be complet= ely wrong. For your DAC output, yes, truncate the data using the most signi= ficant relevant bits. >=20 >=20 >=20 > Other notes: if you reset the registers you can start seeing valid data (= the impulse response which will be the coefficients) immediately, as oppose= d to 128 clock cycles of invalid data. Are you running the simulation long = enough? The numbers of bits of coefficients were been calculated in function of the= ir maximum value, plus sign. But now i don't know more thing to do, i tried= all delay and without delay, on input too, but on testbench i always have= =20 XXXXXXX1=B0coeff-2=B0coeff-3=B0coeff000000000000000 and never all coefficie= nts. I tried to reset registers but i always have the same result. I did underst= and that the output of multiplier must to be synchronous with output of the= adder, but i don't know thing to change more. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.52.64.177 with SMTP id p17mr3571524vds.3.1381411149533; Thu, 10 Oct 2013 06:19:09 -0700 (PDT) X-Received: by 10.49.48.197 with SMTP id o5mr2474qen.31.1381411149508; Thu, 10 Oct 2013 06:19:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no4326513qav.0!news-out.google.com!9ni24092qaf.0!nntp.google.com!i2no4326506qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Oct 2013 06:19:09 -0700 (PDT) In-Reply-To: <0d0e105c-521a-4259-830e-8207926a291b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=159.245.32.2; posting-account=nKnZHQoAAADJGS6e5rJbPJ0f_hTrkTZH NNTP-Posting-Host: 159.245.32.2 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> <0d0e105c-521a-4259-830e-8207926a291b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35521ee8-f0db-46de-87e9-e7e31cb61e1d@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: 1999outback@gmail.com Injection-Date: Thu, 10 Oct 2013 13:19:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7117 The multiplier outputs shouldn't be registered - only the adder outputs sho= uld be registered (assuming the input is properly synchronized). Note that = every signal assignment in a clocked process will create a register. If you= look at a previous post (below), you're creating registers for sig_coeff()= , delaymult1(), delaymult2() and sig_add(). However you only want to create= registers for sig_add() and use immediate values for everything else. > sig_coeff(i)<=3D input*coeff(i); > =20 > delaymult1(i)<=3Dsig_coeff(i); > delaymult2(i)<=3Ddelaymult1(i); > =20 > if i =3D 127 then > sig_add(i)<=3D "000000000"& delaymult2(i); > else > sig_add(i)<=3Dsig_add(i+1)+delaymult2(i); Is your testbench set up properly, e.g. same clock rate, etc.? I usually us= e something like this: =20 input <=3D (others =3D> '0'); wait until rising_edge(clk); input <=3D "00000001"; wait until rising_edge(clk); input <=3D (others =3D> '0'); And if I'm trying to wait for multiple clock periods, let's say 10: wait for CLOCK_PERIOD * 10; When looking at the simulation results, don't just look at the final output= , also look at any intermediate result(s) you can find. From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.42.93.207 with SMTP id y15mr10110330icm.20.1381571289678; Sat, 12 Oct 2013 02:48:09 -0700 (PDT) X-Received: by 10.50.25.40 with SMTP id z8mr205098igf.15.1381571289494; Sat, 12 Oct 2013 02:48:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no8092859qav.0!news-out.google.com!9ni29475qaf.0!nntp.google.com!i2no8092850qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Oct 2013 02:48:08 -0700 (PDT) In-Reply-To: <35521ee8-f0db-46de-87e9-e7e31cb61e1d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.153.154.25; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 188.153.154.25 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> <0d0e105c-521a-4259-830e-8207926a291b@googlegroups.com> <35521ee8-f0db-46de-87e9-e7e31cb61e1d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15127181-fb83-4133-b749-c450bf00936c@googlegroups.com> Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Sat, 12 Oct 2013 09:48:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7118 Il giorno gioved=EC 10 ottobre 2013 15:19:09 UTC+2, 1999o...@gmail.com ha s= critto: > The multiplier outputs shouldn't be registered - only the adder outputs s= hould be registered (assuming the input is properly synchronized). Note tha= t every signal assignment in a clocked process will create a register. If y= ou look at a previous post (below), you're creating registers for sig_coeff= (), delaymult1(), delaymult2() and sig_add(). However you only want to crea= te registers for sig_add() and use immediate values for everything else. >=20 >=20 >=20 > > sig_coeff(i)<=3D input*coeff(i); >=20 > > =20 >=20 > > delaymult1(i)<=3Dsig_coeff(i); >=20 > > delaymult2(i)<=3Ddelaymult1(i); >=20 > > =20 >=20 > > if i =3D 127 then >=20 > > sig_add(i)<=3D "000000000"& delaymult2(i); >=20 > > else >=20 > > sig_add(i)<=3Dsig_add(i+1)+delaymult2(i); >=20 >=20 >=20 > Is your testbench set up properly, e.g. same clock rate, etc.? I usually = use something like this: >=20 > =20 >=20 > input <=3D (others =3D> '0'); >=20 > wait until rising_edge(clk); >=20 > input <=3D "00000001"; >=20 > wait until rising_edge(clk); >=20 > input <=3D (others =3D> '0'); >=20 >=20 >=20 > And if I'm trying to wait for multiple clock periods, let's say 10: >=20 >=20 >=20 > wait for CLOCK_PERIOD * 10; >=20 >=20 >=20 > When looking at the simulation results, don't just look at the final outp= ut, also look at any intermediate result(s) you can find. At the end i solved with structural description!!! :) From newsfish@newsfish Tue Dec 29 16:43:12 2015 X-Received: by 10.66.160.36 with SMTP id xh4mr9203079pab.11.1381571489145; Sat, 12 Oct 2013 02:51:29 -0700 (PDT) X-Received: by 10.50.66.161 with SMTP id g1mr205859igt.5.1381571489070; Sat, 12 Oct 2013 02:51:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no51636569pbz.1!news-out.google.com!9ni29475qaf.0!nntp.google.com!i2no8096818qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Oct 2013 02:51:28 -0700 (PDT) In-Reply-To: <35521ee8-f0db-46de-87e9-e7e31cb61e1d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.153.154.25; posting-account=l7FE3goAAAAloQp40Fsg20Gc2UWfXOeH NNTP-Posting-Host: 188.153.154.25 References: <8bb8a3c3-814e-46f9-ba5c-9e5a6672f8d7@googlegroups.com> <963d783b-6d3c-4c21-adc3-ba8f0024a6b0@googlegroups.com> <0d0e105c-521a-4259-830e-8207926a291b@googlegroups.com> <35521ee8-f0db-46de-87e9-e7e31cb61e1d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FIR Filter Transposed Form VHDL From: Ste_ee Injection-Date: Sat, 12 Oct 2013 09:51:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7119 Il giorno gioved=EC 10 ottobre 2013 15:19:09 UTC+2, 1999o...@gmail.com ha s= critto: > The multiplier outputs shouldn't be registered - only the adder outputs s= hould be registered (assuming the input is properly synchronized). Note tha= t every signal assignment in a clocked process will create a register. If y= ou look at a previous post (below), you're creating registers for sig_coeff= (), delaymult1(), delaymult2() and sig_add(). However you only want to crea= te registers for sig_add() and use immediate values for everything else. >=20 >=20 >=20 > > sig_coeff(i)<=3D input*coeff(i); >=20 > > =20 >=20 > > delaymult1(i)<=3Dsig_coeff(i); >=20 > > delaymult2(i)<=3Ddelaymult1(i); >=20 > > =20 >=20 > > if i =3D 127 then >=20 > > sig_add(i)<=3D "000000000"& delaymult2(i); >=20 > > else >=20 > > sig_add(i)<=3Dsig_add(i+1)+delaymult2(i); >=20 >=20 >=20 > Is your testbench set up properly, e.g. same clock rate, etc.? I usually = use something like this: >=20 > =20 >=20 > input <=3D (others =3D> '0'); >=20 > wait until rising_edge(clk); >=20 > input <=3D "00000001"; >=20 > wait until rising_edge(clk); >=20 > input <=3D (others =3D> '0'); >=20 >=20 >=20 > And if I'm trying to wait for multiple clock periods, let's say 10: >=20 >=20 >=20 > wait for CLOCK_PERIOD * 10; >=20 >=20 >=20 > When looking at the simulation results, don't just look at the final outp= ut, also look at any intermediate result(s) you can find. A the end i solved with structural description!! Thank you very much, reall= y From newsfish@newsfish Tue Dec 29 16:43:12 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: timing verification Date: Mon, 14 Oct 2013 22:54:43 +0200 Lines: 27 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net MtrH/Wtn0XmlYvQlFHv26gz7BMpVIC1bsQu9mmwJm5jfks/+6A Cancel-Lock: sha1:iKIy28VqQkPO6rKjbpVUFHuy2SA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7120 Hi everyone, I'm at the point where I might need to verify timing relationships between two or more signals/variables in my code. I've read PSL assertions can serve the need, but what if I need this task to be done by yesterday and I do not know PSL at all? Any suggestion on investing some of my time in learning PSL? Since my signals/variables are nowhere near the top entity port definition, how can I verify the timing through a testbench? I may understand how to verify external interfaces, but I guess is going to be hard to do that on internal objects. As of today I'm listing the signals on a piece of paper, writing down timing relationships and then checking them off with a waveform viewer...extremely painful and inefficient! Any pointer is appreciated. Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer03.iad.highwinds-media.com!news.iad.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx22.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131015-0, 15/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 42 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1381823133 86.29.12.221 (Tue, 15 Oct 2013 07:45:33 UTC) NNTP-Posting-Date: Tue, 15 Oct 2013 07:45:33 UTC Organization: virginmedia.com Date: Tue, 15 Oct 2013 08:45:30 +0100 X-Received-Body-CRC: 633125116 X-Received-Bytes: 2543 Xref: news.eternal-september.org comp.lang.vhdl:7121 On 14/10/2013 21:54, alb wrote: > Hi everyone, > > I'm at the point where I might need to verify timing relationships > between two or more signals/variables in my code. > > I've read PSL assertions can serve the need, but what if I need this > task to be done by yesterday and I do not know PSL at all? Any > suggestion on investing some of my time in learning PSL? > > Since my signals/variables are nowhere near the top entity port > definition, how can I verify the timing through a testbench? I may > understand how to verify external interfaces, but I guess is going to be > hard to do that on internal objects. > > As of today I'm listing the signals on a piece of paper, writing down > timing relationships and then checking them off with a waveform > viewer...extremely painful and inefficient! > > Any pointer is appreciated. > > Al > Hi Al, PSL is a great language to have in your EDA toolset but as you don't have time to learn it I would suggest you check out OVL which are monitor/checkers written in VHDL/Verilog. OVL is supplied with most (all?) simulators and some can even be synthesised. If you have access to Modelsim then try the OVL assertion manager which allows you to configure them using a GUI. As a final suggestion, once you have some more time I would suggest you do get onto a PSL/SVA course as it opens up the wonderful world of Functional and Formal Verification. Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Tue, 15 Oct 2013 20:41:15 +0200 Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Dq7NsdZiI5VvgJ/6ymHq2AZleHzl0fNMSH7EJV67hpgrkyU7es Cancel-Lock: sha1:BO6UMsijZM9MSsS4aAncma22nr4= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7122 Hi Hans, On 15/10/2013 09:45, HT-Lab wrote: [] >> I'm at the point where I might need to verify timing relationships >> between two or more signals/variables in my code. [] > PSL is a great language to have in your EDA toolset but as you don't > have time to learn it I would suggest you check out OVL which are > monitor/checkers written in VHDL/Verilog. OVL is supplied with most > (all?) simulators and some can even be synthesised. If you have access > to Modelsim then try the OVL assertion manager which allows you to > configure them using a GUI. Uhm, it looks to me ModelSim SE (the one I have) does not support PSL, but isn't PSL formally part of VHDL-2008? I've read here (http://osvvm.org/forums/topic/psl-or-sva) about even further possible integration of PSL into VHDL. Thanks for the OVL hint! I'll start to play with it and see where it leads to. > As a final suggestion, once you have some more time I would suggest you > do get onto a PSL/SVA course as it opens up the wonderful world of > Functional and Formal Verification. I do functional verification through TLM in VHDL and I'm about to dig in the usage of OSVVM for constrained coverage. Unfortunately this approach does not give me the level of observability I needed, especially on internal bus protocols, that's why I wanted to explore other means. From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Tue, 15 Oct 2013 18:42:47 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 15 Oct 2013 22:43:16 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="1365"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Y5oxbjdecUW7MHcVCG7j+" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:IGLLxc+3v1xQwpCS8q3021i1PCc= Xref: news.eternal-september.org comp.lang.vhdl:7123 On 10/15/2013 2:41 PM, alb wrote: > Hi Hans, > > On 15/10/2013 09:45, HT-Lab wrote: > [] >>> I'm at the point where I might need to verify timing relationships >>> between two or more signals/variables in my code. > [] >> PSL is a great language to have in your EDA toolset but as you don't >> have time to learn it I would suggest you check out OVL which are >> monitor/checkers written in VHDL/Verilog. OVL is supplied with most >> (all?) simulators and some can even be synthesised. If you have access >> to Modelsim then try the OVL assertion manager which allows you to >> configure them using a GUI. > > Uhm, it looks to me ModelSim SE (the one I have) does not support PSL, > but isn't PSL formally part of VHDL-2008? I've read here > (http://osvvm.org/forums/topic/psl-or-sva) about even further possible > integration of PSL into VHDL. > > Thanks for the OVL hint! I'll start to play with it and see where it > leads to. > >> As a final suggestion, once you have some more time I would suggest you >> do get onto a PSL/SVA course as it opens up the wonderful world of >> Functional and Formal Verification. > > I do functional verification through TLM in VHDL and I'm about to dig in > the usage of OSVVM for constrained coverage. Unfortunately this approach > does not give me the level of observability I needed, especially on > internal bus protocols, that's why I wanted to explore other means. Sounds like I am a bit behind in this. I have always verified timing by setting timing constrains for the P&R tool which verifies the design meets the timing constraints. Is there some other aspect of timing that constraints don't work for? PSL, OVL, SVA, OSVVM, TLM...??? I need to check this out I expect. For timing at higher levels, like "does this happen three clock cycles after that happens", I have always just verified that by inspection or functional simulation. Are these tools ways of adding formal verification of this sort of timing? -- Rick From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer03.iad.highwinds-media.com!news.iad.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx32.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131015-1, 15/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 63 Message-ID: <%xr7u.16752$RX.8286@fx32.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1381909755 86.29.12.221 (Wed, 16 Oct 2013 07:49:15 UTC) NNTP-Posting-Date: Wed, 16 Oct 2013 07:49:15 UTC Organization: virginmedia.com Date: Wed, 16 Oct 2013 08:49:12 +0100 X-Received-Body-CRC: 1078823801 X-Received-Bytes: 3565 Xref: news.eternal-september.org comp.lang.vhdl:7124 Hi Alb, On 15/10/2013 19:41, alb wrote: > Hi Hans, > > On 15/10/2013 09:45, HT-Lab wrote: > [] >>> I'm at the point where I might need to verify timing relationships >>> between two or more signals/variables in my code. > [] >> PSL is a great language to have in your EDA toolset but as you don't >> have time to learn it I would suggest you check out OVL which are >> monitor/checkers written in VHDL/Verilog. OVL is supplied with most >> (all?) simulators and some can even be synthesised. If you have access >> to Modelsim then try the OVL assertion manager which allows you to >> configure them using a GUI. > > Uhm, it looks to me ModelSim SE (the one I have) does not support PSL, Modelsim SE is an obsolete product (for many years), speaks to Mentor to see if you can exchange it for a (hopefully free) Questa Core license (which does support PSL/SVA). > but isn't PSL formally part of VHDL-2008? I've read here It is but that doesn't mean you get it for free ;-), it is the same with SystemVerilog, the language is split into 2 parts and you only get access to the Verification part if you pay a lot of money. > (http://osvvm.org/forums/topic/psl-or-sva) about even further possible > integration of PSL into VHDL. Interesting read, one point I would make is that you can steer your testbench from PSL. Apart from using Tcl you can use PSL endpoints which are supported by Modelsim and I assume other simulators. > > Thanks for the OVL hint! I'll start to play with it and see where it > leads to. > >> As a final suggestion, once you have some more time I would suggest you >> do get onto a PSL/SVA course as it opens up the wonderful world of >> Functional and Formal Verification. > > I do functional verification through TLM in VHDL and I'm about to dig in Not sure I understand as TLM is nothing but an abstraction layer, it doesn't allow you to verify functionality in your design unless you write your own checkers. > the usage of OSVVM for constrained coverage. Unfortunately this approach The OS-VVM is a great framework, unfortunately most engineers (managers?) still think they have to move to SystemVerilog to add a re-usable CR verification framework to their environment. Regards, Hans. > does not give me the level of observability I needed, especially on > internal bus protocols, that's why I wanted to explore other means. > From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer01.iad.highwinds-media.com!news.iad.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx13.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131015-1, 15/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 43 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1381912364 86.29.12.221 (Wed, 16 Oct 2013 08:32:44 UTC) NNTP-Posting-Date: Wed, 16 Oct 2013 08:32:44 UTC Organization: virginmedia.com Date: Wed, 16 Oct 2013 09:32:41 +0100 X-Received-Body-CRC: 1493675055 X-Received-Bytes: 3064 Xref: news.eternal-september.org comp.lang.vhdl:7125 Hi Rickman, On 15/10/2013 23:42, rickman wrote: .. >> >> I do functional verification through TLM in VHDL and I'm about to dig in >> the usage of OSVVM for constrained coverage. Unfortunately this approach >> does not give me the level of observability I needed, especially on >> internal bus protocols, that's why I wanted to explore other means. > > Sounds like I am a bit behind in this. I have always verified timing by > setting timing constrains for the P&R tool which verifies the design > meets the timing constraints. Is there some other aspect of timing that > constraints don't work for? You use assertions to make sure that your timing constraints itself are correct. For example, there are occasions where it is not easy to determine if you always have a multi-cycle path (e.g. a designs with multiple clock domains). In this case an assertion can help (or prove exhaustively if you use a formal tool). For false path an assertion even becomes a must have as checking them manually (i.e. looking at a gate level schematic!) is an error prone and a very time consuming activity. > > PSL, OVL, SVA, OSVVM, TLM...??? I need to check this out I expect. > > For timing at higher levels, like "does this happen three clock cycles > after that happens", I have always just verified that by inspection or > functional simulation. Are these tools ways of adding formal > verification of this sort of timing? You can quite easily add an embedded assertion (supplied with the design itself) that always checks that A happens 3 clock cycles after B. The problem with Verilog/VHDL is that they are very verbose and hence more susceptible to bugs, languages like PSL/SVA are designed for this task and hence are very concise, easy to use for sequences and un-ambiguous. You can write a page of VHDL/Verilog or 1 line of PSL/SVA. Regards, Hans. > From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Wed, 16 Oct 2013 13:23:46 +0200 Lines: 82 Message-ID: References: <%xr7u.16752$RX.8286@fx32.am4> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net MI+x5dZ9gJoRzL7GonmQoAYjRp343I4NWHMZz3rP0O96hF+rr2 Cancel-Lock: sha1:LTd8NvJwI8BBMQlZVbRJ/XG9IeI= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <%xr7u.16752$RX.8286@fx32.am4> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7126 Hi Hans, On 16/10/2013 09:49, HT-Lab wrote: [] >> Uhm, it looks to me ModelSim SE (the one I have) does not support PSL, > > Modelsim SE is an obsolete product (for many years), speaks to Mentor to > see if you can exchange it for a (hopefully free) Questa Core license > (which does support PSL/SVA). > The Actel design flow uses ModelSim SE and the whole team (ok, three people!) uses it. I'm not sure it would be an easy switch. >> but isn't PSL formally part of VHDL-2008? I've read here > > It is but that doesn't mean you get it for free ;-), it is the same with > SystemVerilog, the language is split into 2 parts and you only get > access to the Verification part if you pay a lot of money. Crap! Ok, I guess I'm going to live with this fact unless I want to build up a revolution, which does not quite fit my current schedule ;-) > >> (http://osvvm.org/forums/topic/psl-or-sva) about even further possible >> integration of PSL into VHDL. > > Interesting read, one point I would make is that you can steer your > testbench from PSL. Apart from using Tcl you can use PSL endpoints which > are supported by Modelsim and I assume other simulators. Ok, I just had a look at 'endpoints' in PSL, but how do you pass that information to your running vhdl testbench??? >> >> Thanks for the OVL hint! I'll start to play with it and see where it >> leads to. >> >>> As a final suggestion, once you have some more time I would suggest you >>> do get onto a PSL/SVA course as it opens up the wonderful world of >>> Functional and Formal Verification. >> >> I do functional verification through TLM in VHDL and I'm about to dig in > > Not sure I understand as TLM is nothing but an abstraction layer, it > doesn't allow you to verify functionality in your design unless you > write your own checkers. through the bus functional model I get access to all interfaces of my top level entity and verify all specs on those interfaces. The problem comes when I add IPs to my logic and I need to verify the internal interface to that IP is according to the IP specs. That's why I wanted to be able to verify timing of internal interfaces. True, I may still get a failure in the IP interfaces which is observable on my external interfaces, but then it would be hard to know what is not working. In principle I could perform unit testing, but this requires a lot of overhead and very few of the verification code would be reusable. My approach was inspired by this paper: http://www.synthworks.com/papers/VHDL_Subblock_Verification_DesignCon_2003_P.pdf Even though I did not go through the hassle of instantiating (or configuring) incremental pieces of the DUT because of other reasons (starting from a very bad structural choice in the DUT components). > >> the usage of OSVVM for constrained coverage. Unfortunately this approach > > The OS-VVM is a great framework, unfortunately most engineers > (managers?) still think they have to move to SystemVerilog to add a > re-usable CR verification framework to their environment. I'm about to start a hot discussion about the use of OSVVM vs. SystemVerilog for verification in my working environment, I guess SV has the lead in system verification just because OSVVM was not there at the beginning. The main problem I see is the overall support of SV vs OSVVM, in terms of verification IPs and packages, know-how. From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Wed, 16 Oct 2013 13:45:34 +0200 Lines: 50 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ABoTlaETIahZRDe8heCCjgwXyDBviXmwld/FLBI8GhTeIMIPXO Cancel-Lock: sha1:qvuKmlTsyHlpkV3JE/JGa7Tadq8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7127 Hi Rick, On 16/10/2013 00:42, rickman wrote: [] >> I do functional verification through TLM in VHDL and I'm about to dig in >> the usage of OSVVM for constrained coverage. Unfortunately this approach >> does not give me the level of observability I needed, especially on >> internal bus protocols, that's why I wanted to explore other means. > > Sounds like I am a bit behind in this. I have always verified timing by > setting timing constrains for the P&R tool which verifies the design > meets the timing constraints. Is there some other aspect of timing that > constraints don't work for? > > PSL, OVL, SVA, OSVVM, TLM...??? I need to check this out I expect. > > For timing at higher levels, like "does this happen three clock cycles > after that happens", I have always just verified that by inspection or > functional simulation. Are these tools ways of adding formal > verification of this sort of timing? > Let me add just two additional comments to what Hans has already said. IMO the first problem comes with 'state observability', that is you have been able to stimulate a logic path (code coverage) *and* you are able to observe the effect. In my case I have to deal with a very simple processor data bus with address and data, WR and RD and few other control signals. The result of the transaction on the bus will be some data ending up in my output register. Externally I have access only to the output register, therefore I can only see whether the data I expect will be there or not, and if not I have to look at the waveforms and/or the code. Moreover if I do changes that affect the interface I would need to perform this analysis again. With the tools discussed here you can add observability to your design without the need to add extra logic or bring a lot of test points out. So your simulation can even check that those changes have not affected the bus access requirements. Secondly there's another, and maybe more important, aspect: constrained random stimuli. Direct testing might not be sufficient for full functional coverage (or at least might be a very lengthy process), therefore you may need to add constrained random stimuli to reach coverage goals. At this point it is very unpractical to 'inspect' the waveforms and guarantee that for each transaction the requirements are met. HTH, Al From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.42.112.138 with SMTP id y10mr894042icp.28.1381931555972; Wed, 16 Oct 2013 06:52:35 -0700 (PDT) X-Received: by 10.50.111.200 with SMTP id ik8mr608020igb.7.1381931555741; Wed, 16 Oct 2013 06:52:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no15644893qav.0!news-out.google.com!9ni46435qaf.0!nntp.google.com!o2no8097120qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Oct 2013 06:52:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: timing verification From: Andy Injection-Date: Wed, 16 Oct 2013 13:52:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7128 Al, Excellent point about state observability on internal interfaces. I have used "wrappers" around internal components/entities that include VHD= L assertions (or could use OVL, PSA, etc.) to verify certain aspects of the= interface.=20 I am planning on adding OSVVM coverage model(s) to the wrapper so that I ca= n capture/monitor how well the interface is exercised from the system level= interfaces. Wrappers could even be nested. You can also "modify" the interface via the wrapper for easier system verif= ication. For example, your entity may have a data output with a correspondi= ng valid output that signifies when the data output is valid and safe to us= e. The wrapper can drive 'X's on the data port when the valid port is not a= sserted, ensuring that the consumer does not use the data except when it is= valid.=20 I have seen so many cases where the data consumer violated the protocol, bu= t still worked only because the data producer kept the data valid for longe= r than indicated. One small change to the producer (maybe an optimization),= and suddenly the consumer will quit working, even thought the producer is = still following the protocol. My wrappers take the form of an an additional architecture for the same ent= ity it wraps (the wrapper re-instantiates the component/entity within itsel= f). These can be inserted either using configurations (if you use component= s), or by making sure that your simulation compile scripts compile the wrap= per architecture AFTER the RTL architecture, if you use entity instantiatio= ns. In the latter case, the system RTL should not specify an architecture f= or those entities, but the wrapper's instantiation of the entity (itself) s= hould specify the RTL architecture. That way, if no wrapper architecture is= compiled (or is compiled after the RTL architecture), no wrapper is used (= as might be the case for other test cases or for synthesis.) I keep the wrapper architectures in separate files in the testbench source = folder(s).=20 Andy From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer02.iad.highwinds-media.com!feed-me.highwinds-media.com!peer02.fr7!news.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: <%xr7u.16752$RX.8286@fx32.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131016-0, 16/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 69 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1381934485 86.29.12.221 (Wed, 16 Oct 2013 14:41:25 UTC) NNTP-Posting-Date: Wed, 16 Oct 2013 14:41:25 UTC Organization: virginmedia.com Date: Wed, 16 Oct 2013 15:41:22 +0100 X-Received-Body-CRC: 2357401986 X-Received-Bytes: 3448 Xref: news.eternal-september.org comp.lang.vhdl:7129 Hi Alb, On 16/10/2013 12:23, alb wrote: > Hi Hans, > > On 16/10/2013 09:49, HT-Lab wrote: > [] >>> Uhm, it looks to me ModelSim SE (the one I have) does not support PSL, >> >> Modelsim SE is an obsolete product (for many years), speaks to Mentor to >> see if you can exchange it for a (hopefully free) Questa Core license >> (which does support PSL/SVA). >> > > The Actel design flow uses ModelSim SE and the whole team (ok, three > people!) uses it. I'm not sure it would be an easy switch. It is the same product with some extra features and a different name ;-) .. >> >> Interesting read, one point I would make is that you can steer your >> testbench from PSL. Apart from using Tcl you can use PSL endpoints which >> are supported by Modelsim and I assume other simulators. > > Ok, I just had a look at 'endpoints' in PSL, but how do you pass that > information to your running vhdl testbench??? Very simple, as soon as you define an endpoint you get an extra boolean signal (endp below) in your design. Example: architecture rtl of test_tb is -- psl default clock is rising_edge(clk); -- psl sequence seq is {a;b}; -- psl endpoint endp is {seq}; begin process begin if endp=TRUE then -- change testbench behaviour end if; end process; end architecture rtl; As soon as "a" is asserted followed by "b" in the next clock cycle the endpoint endp becomes true. You can treat endp like any other signal, drag in the waveform window etc. .. >> The OS-VVM is a great framework, unfortunately most engineers >> (managers?) still think they have to move to SystemVerilog to add a >> re-usable CR verification framework to their environment. > > I'm about to start a hot discussion about the use of OSVVM vs. > SystemVerilog for verification in my working environment, I guess SV has > the lead in system verification just because OSVVM was not there at the > beginning. The main problem I see is the overall support of SV vs OSVVM, > in terms of verification IPs and packages, know-how. Yes, you are right, if you planning to use third party verification IP then VMM/OVM/UVM (i.e. all SystemVerilog) is the only way forward. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.66.162.134 with SMTP id ya6mr1575666pab.7.1381943746030; Wed, 16 Oct 2013 10:15:46 -0700 (PDT) X-Received: by 10.50.20.38 with SMTP id k6mr99323ige.17.1381943745839; Wed, 16 Oct 2013 10:15:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!z6no53881424pbz.1!news-out.google.com!9ni45434qaf.0!nntp.google.com!i2no15949478qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Oct 2013 10:15:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.237.174.107; posting-account=ladvKwoAAADxX4hmN8dzRJYXVGKui6dv NNTP-Posting-Host: 197.237.174.107 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Partnership Request From: Dan Wawa Injection-Date: Wed, 16 Oct 2013 17:15:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7130 Hi, I have designed a microprocessor that works as a USB device that I call= DorQ. Its function is to speed up the processing speed of any computer tha= t it is connected to by a factor of several thousands of times. I call it t= he concept of Parallel Bus Processing. My design is still in VHDL source co= de and I need a partner to help fabricate/manufacture and market this new k= ind of USB device. I repeat, this is a completely new USB device that will = work with any PC in the world. Would you be interested in partnering with m= e in this venture? Please contact me with your yes or no response or any id= eas about companies that may accept designs from partners as part of their = product lines. You can also contact me at loumbut5@hotmail.com From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Thu, 17 Oct 2013 11:27:42 +0200 Lines: 75 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net cs/yV3dwlylZr35JzZ8k5wzKShfKQuGJoQpJrAv3yaCnnIyy05 Cancel-Lock: sha1:jldPmkDVu9clEuWA8ZjPpxmBI6Q= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7131 Hi Andy, On 16/10/2013 15:52, Andy wrote: > I have used "wrappers" around internal components/entities that > include VHDL assertions (or could use OVL, PSA, etc.) to verify > certain aspects of the interface. > > I am planning on adding OSVVM coverage model(s) to the wrapper so > that I can capture/monitor how well the interface is exercised from > the system level interfaces. Wrappers could even be nested. > > You can also "modify" the interface via the wrapper for easier system > verification. For example, your entity may have a data output with a > corresponding valid output that signifies when the data output is > valid and safe to use. The wrapper can drive 'X's on the data port > when the valid port is not asserted, ensuring that the consumer does > not use the data except when it is valid. So that's the place you can actually perform protocol checks! But then how do you collect or steer the testbench based on these checks? Other than 'severity' levels to either break or continue the simulation, there's a way to access this information from the TB? AKAIK you cannot access through hierarchies of entities unless your wrapper has out ports which provide a connection to the upper levels. This would mean that the top entity wrapper would be populated with a bunch of ports related to internal interfaces' wrappers... Am I missing something? But I guess I got your point, since is for verification purposes only you can have multiple drivers and enforce the requirement, forcing the consumer to break 'early' in the verification process. > > I have seen so many cases where the data consumer violated the > protocol, but still worked only because the data producer kept the > data valid for longer than indicated. One small change to the > producer (maybe an optimization), and suddenly the consumer will quit > working, even thought the producer is still following the protocol. Let alone when the producer is out of specs (say a too early integration) and you need to tight those requirements to make it working. While the producer gets fixed according to new requirements you may still proceed with the verification process of the consumer. > > My wrappers take the form of an an additional architecture for the > same entity it wraps (the wrapper re-instantiates the > component/entity within itself). These can be inserted either using > configurations (if you use components), or by making sure that your > simulation compile scripts compile the wrapper architecture AFTER the > RTL architecture, if you use entity instantiations. I use vmk to generate Makefiles for compilation. It resolves the dependencies automatically analyzing the code structure and since the wrapper 'depends' on the rtl architecture the condition is met. I should say that I'd like to start using configurations more regularly, but never had a deep motivation for it yet. > In the latter > case, the system RTL should not specify an architecture for those > entities, but the wrapper's instantiation of the entity (itself) > should specify the RTL architecture. That way, if no wrapper > architecture is compiled (or is compiled after the RTL architecture), > no wrapper is used (as might be the case for other test cases or for > synthesis.) > > I keep the wrapper architectures in separate files in the testbench > source folder(s). The only limitation I see is that you can only use this approach during pre-synth simulation. For post-synth simulation I get a flat netlist where wrappers are not existing anymore. Do you need to change/adapt your testbenches to accommodate this? Am I missing something else? From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Thu, 17 Oct 2013 16:30:51 +0200 Lines: 37 Message-ID: References: <%xr7u.16752$RX.8286@fx32.am4> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net CnD5lj8TUSYD9HlmDF5k4wFXwHl5CE9HFRT209U/FMzdUaKNwr Cancel-Lock: sha1:O9/8LdZE3D7RvGbmxiN4oQJt2b8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7132 Hi Hans, On 16/10/2013 16:41, HT-Lab wrote: [] >> Ok, I just had a look at 'endpoints' in PSL, but how do you pass that >> information to your running vhdl testbench??? > > Very simple, as soon as you define an endpoint you get an extra boolean > signal (endp below) in your design. Example: > > architecture rtl of test_tb is > > -- psl default clock is rising_edge(clk); > -- psl sequence seq is {a;b}; > -- psl endpoint endp is {seq}; > > begin > process > begin > if endp=TRUE then > -- change testbench behaviour > end if; > end process; > end architecture rtl; Ok, does it mean that 'a' and 'b' assertions are visible at the top level even if they are defined in the inner interfaces and/or elements of your logic? > As soon as "a" is asserted followed by "b" in the next clock cycle the > endpoint endp becomes true. You can treat endp like any other signal, > drag in the waveform window etc. Uhm I might then have misunderstood what Jim Lewis referred to in the link I provided earlier in this thread. As I understand it, there's no way currently to access information gathered by PSL (I presume unless it's on the same hierarchical level), is this correct? From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.158.4 with SMTP id wq4mr3481339obb.18.1382031902129; Thu, 17 Oct 2013 10:45:02 -0700 (PDT) X-Received: by 10.50.138.197 with SMTP id qs5mr252949igb.7.1382031902055; Thu, 17 Oct 2013 10:45:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no17717599qav.0!news-out.google.com!9ni50474qaf.0!nntp.google.com!i2no17717584qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Oct 2013 10:45:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d59dd53-0972-4224-829d-9059753570bb@googlegroups.com> Subject: Re: timing verification From: Andy Injection-Date: Thu, 17 Oct 2013 17:45:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7133 Al, For interaction with the rest of the testbench from within the wrapper, you= have a few different options that don't require adding signals to the DUT = hierarchy and port maps. You can use global signals or shared variables (including method calls on t= hose shared variables) declared in a simulation package. These are often go= od for maintaining a global pass/fail status and/or error count. In VHDL-2008, you can also hierarchically access signals without going thro= ugh formal ports to get them. I have also simply used assert/report statements to put messages in the sim= ulation log that can be post-processed. I have steadily moved away from using configurations. The cost of maintaini= ng them and the component declarations they rely upon is too high. The wrap= per architectures are one way I have avoided using configurations. From the= wrapper, you can also modify or set the RTL architecture's generics to alt= er behavior for some tests. The wrapper architecture can also access 'insta= nce_name or 'path_name attributes to find out "where it is" and alter its b= ehavior based on its location. So there isn't much left for which you reall= y need configurations. I don't use vmkr, so I don't know how it might work with wrapper architectu= res. I used to use make to reduce compile time for incremental changes, but= that does not seem to be as big an issue as it used to be. There is someth= ing to be said for a script that compiles the simulation (or the DUT) from = scratch, the same way every time, regardless of what has or has not changed= . Wrapper architectures are not compatible with gate level simulations (at le= ast not wrappers for entities within the DUT). =20 After synthesis optimizations, retiming, etc. specific internal interface f= eatures may not even exist at the gate level. However, a wrapper can instantiate the gate level model in place of the RTL= . Wrappers can also create or instantiate a different model of an RTL entity = for improving the simulation performance, or providing internal stimulus, e= tc. Andy From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!weretis.net!feeder1.news.weretis.net!feeder4.news.weretis.net!rt.uk.eu.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: Partnership Request Date: Thu, 17 Oct 2013 10:53:49 -0700 Organization: Aioe.org NNTP Server Lines: 12 Message-ID: <5260242D.8050602@yahoo.com> References: NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7134 > Hi, I have designed a microprocessor that works as a USB device that I call DorQ. (etc) That's quite a claim: "speed up the processing speed of any computer"! All that just by connecting your USB device? I'm not aware of any existing USB technology that could possibly make the host PC run three orders of magnitude faster. Can you give us a hint about how it works? JJS From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Partnership Request Date: Thu, 17 Oct 2013 16:36:20 -0400 Organization: Alacron, Inc. Lines: 20 Message-ID: References: <5260242D.8050602@yahoo.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 17 Oct 2013 20:38:07 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="23308"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18PFG0EkxGiZ/PzahrRDpgVSy5iwQ4WKys=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <5260242D.8050602@yahoo.com> Cancel-Lock: sha1:BvM1g7HLwFWYidN1vDmGen6OCEM= Xref: news.eternal-september.org comp.lang.vhdl:7135 John Speth wrote: >> Hi, I have designed a microprocessor that works as a USB device that I >> call DorQ. (etc) > > That's quite a claim: "speed up the processing speed of any computer"! > All that just by connecting your USB device? I'm not aware of any > existing USB technology that could possibly make the host PC run three > orders of magnitude faster. > > Can you give us a hint about how it works? > > JJS > > Probably works best with the USB 4.0 port on Intel's latest "Brooklyn Bridge" chip set ;) -- Gabor From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Fri, 18 Oct 2013 17:01:50 +0200 Lines: 94 Message-ID: References: <3d59dd53-0972-4224-829d-9059753570bb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ibI7/bE6rC0ItkYvFGD9XQRH/MDNhfx9Pkp+mS8E8iBRo413p4 Cancel-Lock: sha1:CujR5tmLBTWGielGXuTbrUY/omE= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: <3d59dd53-0972-4224-829d-9059753570bb@googlegroups.com> X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7136 Hi Andy, On 17/10/2013 19:45, Andy wrote: > Al, > > For interaction with the rest of the testbench from within the > wrapper, you have a few different options that don't require adding > signals to the DUT hierarchy and port maps. > > You can use global signals or shared variables (including method > calls on those shared variables) declared in a simulation package. > These are often good for maintaining a global pass/fail status and/or > error count. My experience with global signals is quite bad in general and even when writing software, every time I had to deal with large amount of global variables I ended up regretting that choice... I'm not familiar with protected types, but I guess that at least they provide some sort of encapsulation with their methods and their private data structures. In this case the wrappers might update coverage (write access to data structures) while the TB can steer its course accordingly (read access to data structures). Keeping data structures separate for each interface (or wrapper) might facilitate the effort. > > In VHDL-2008, you can also hierarchically access signals without > going through formal ports to get them. Ok, this is something I did not know, I should keep reading about the main differences between 2008 and previous versions of the standard. > I have also simply used assert/report statements to put messages in > the simulation log that can be post-processed. Yep, that's something that already gives you more observability. > I don't use vmkr, so I don't know how it might work with wrapper > architectures. FYI I'm using vmk, not vmkr. I tried to use the latter but I did have problems in compiling it. > I used to use make to reduce compile time for > incremental changes, but that does not seem to be as big an issue as > it used to be. I agree, but I'm kind of used to incremental compilation and do not see any pitfall in it, but it is possible that my understanding of the process is somewhat limited. > There is something to be said for a script that > compiles the simulation (or the DUT) from scratch, the same way every > time, regardless of what has or has not changed.. The compilation order has to be taken care of anyhow and this is something that so far tools have asked the users to do (AFAIK). If I have to insert a new entity in my code I simply run vmk first: > vmk -o Makefile *.vhd and then 'make'. The dependencies are automatically found and I do not need to know where to put my new file in the list of files to be compiled. Moreover, if I need to add a component that has several other components in its hierarchy the hassle grows if everything should be handled manually, but not if there's a tool handy. What is the benefit of running the simulation from scratch the same way every time? > Wrapper architectures are not compatible with gate level simulations > (at least not wrappers for entities within the DUT). > > After synthesis optimizations, retiming, etc. specific internal > interface features may not even exist at the gate level. > > However, a wrapper can instantiate the gate level model in place of > the RTL.. Uhm, that's interesting indeed. Meaning that for integration purposes of several IPs you may still use wrappers and benefit from their advantages. The simulation would still be a functional one, but some of the elements might be gate level models. You could in principle have behavioral models (even not synthesizable), just to proceed with the functional verification and get the simulation framework in place before the rtl model is ready. Using rtl libraries instead of behavioral would be sufficient to switch. > Wrappers can also create or instantiate a different model of an RTL > entity for improving the simulation performance, or providing > internal stimulus, etc. I guess at this point I have no more excuses for not using wrappers! ;-) From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx25.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: <%xr7u.16752$RX.8286@fx32.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131018-0, 18/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 57 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1382114872 86.29.12.221 (Fri, 18 Oct 2013 16:47:52 UTC) NNTP-Posting-Date: Fri, 18 Oct 2013 16:47:52 UTC Organization: virginmedia.com Date: Fri, 18 Oct 2013 17:47:49 +0100 X-Received-Body-CRC: 2903069619 X-Received-Bytes: 3066 Xref: news.eternal-september.org comp.lang.vhdl:7137 Hi Alb, On 17/10/2013 15:30, alb wrote: > Hi Hans, > > On 16/10/2013 16:41, HT-Lab wrote: > [] >>> Ok, I just had a look at 'endpoints' in PSL, but how do you pass that >>> information to your running vhdl testbench??? >> >> Very simple, as soon as you define an endpoint you get an extra boolean >> signal (endp below) in your design. Example: >> >> architecture rtl of test_tb is >> >> -- psl default clock is rising_edge(clk); >> -- psl sequence seq is {a;b}; >> -- psl endpoint endp is {seq}; >> >> begin >> process >> begin >> if endp=TRUE then >> -- change testbench behaviour >> end if; >> end process; >> end architecture rtl; > > Ok, does it mean that 'a' and 'b' assertions are visible at the top > level even if they are defined in the inner interfaces and/or elements > of your logic? Sorry I should have mentioned the above was just a bit of pseudo code, a and b are std_logic signals. Also (before anybody corrects me ;-) the curly braces on {seq} are redundant as seq is already defined as a sequence. > >> As soon as "a" is asserted followed by "b" in the next clock cycle the >> endpoint endp becomes true. You can treat endp like any other signal, >> drag in the waveform window etc. > > Uhm I might then have misunderstood what Jim Lewis referred to in the > link I provided earlier in this thread. As I understand it, there's no > way currently to access information gathered by PSL (I presume unless > it's on the same hierarchical level), is this correct? You are correct that endpoints are only valid at the current level, however, as it is a signal you should be able to reference it at a different level using VHDL2008 hierarchical references or vendors own solution like Signalspy in Modelsim. Regards, Hans. www.ht-lab.com > From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.109.200 with SMTP id hu8mr1620470obb.20.1382119391870; Fri, 18 Oct 2013 11:03:11 -0700 (PDT) X-Received: by 10.182.75.232 with SMTP id f8mr41111obw.0.1382119391823; Fri, 18 Oct 2013 11:03:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!o2no11900209qas.0!news-out.google.com!9ni50460qaf.0!nntp.google.com!o2no11900202qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Oct 2013 11:03:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <3d59dd53-0972-4224-829d-9059753570bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3781157e-e280-4f35-bf51-2c3f4d53905a@googlegroups.com> Subject: Re: timing verification From: Andy Injection-Date: Fri, 18 Oct 2013 18:03:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1824 Xref: news.eternal-september.org comp.lang.vhdl:7138 Al, For simulation or synthesis, you want to ensure your tool is running from only your files (from the repository), not from some version already sitting in a library inside the tool somewhere. Especially for synthesis, I have seen compilation order (or skipping re-compilation of previously compiled unchanged files) affect optimizations. Now I always synthesize from scratch ("Run->Resynthesize All" or "project -run synthesis -clean") Andy From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.236.147.18 with SMTP id s18mr4525521yhj.28.1382124545135; Fri, 18 Oct 2013 12:29:05 -0700 (PDT) X-Received: by 10.182.28.129 with SMTP id b1mr24827obh.37.1382124545063; Fri, 18 Oct 2013 12:29:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.88.MISMATCH!i2no19576941qav.0!news-out.google.com!9ni50460qaf.0!nntp.google.com!o2no12026988qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Oct 2013 12:29:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.74.55.62; posting-account=YHBUCgoAAADFrSXs8bOecBdEesd417Xp NNTP-Posting-Host: 24.74.55.62 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <725542b2-5144-4b9d-a081-c4ecc14b9c38@googlegroups.com> Subject: VHDL sharing components? From: Matt Johnson Injection-Date: Fri, 18 Oct 2013 19:29:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7139 I'm not sure if this is possible, as I haven't been able to think of a way = to do it with my limited knowledge of VHDL. I'm making a 4-stage processor (fetch, decode, execute, writeback) in VHDL = for a class project. Each of the different stages are supposed to be differ= ent VHDL files. I've put my registers as a component in the execute stage. In my writeback = stage, I'm supposed to modify register values with the output of my ALU whi= ch is in the execute stage. If my registers are a component of the execute = stage, is it possible to share that component with the writeback stage to e= dit the values? I'm not sure how to approach this... From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL sharing components? Date: Fri, 18 Oct 2013 16:04:10 -0400 Organization: Alacron, Inc. Lines: 30 Message-ID: References: <725542b2-5144-4b9d-a081-c4ecc14b9c38@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Oct 2013 20:04:14 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="29369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/f2D7i2eLcU6+V25aToW0t/y9z4UcnePc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <725542b2-5144-4b9d-a081-c4ecc14b9c38@googlegroups.com> Cancel-Lock: sha1:kNuaH8QhbJfbYApwxjepRrzcy2E= Xref: news.eternal-september.org comp.lang.vhdl:7140 Matt Johnson wrote: > I'm not sure if this is possible, as I haven't been able to think of a way to do it with my limited knowledge of VHDL. > > I'm making a 4-stage processor (fetch, decode, execute, writeback) in VHDL for a class project. Each of the different stages are supposed to be different VHDL files. > > I've put my registers as a component in the execute stage. In my writeback stage, I'm supposed to modify register values with the output of my ALU which is in the execute stage. If my registers are a component of the execute stage, is it possible to share that component with the writeback stage to edit the values? I'm not sure how to approach this... You don't really want to "share a component." What you want is to provide a port for writing the register file. That is you need to look at your registers like a RAM that has address, data write enable pins. If the registers physically exist in one module, then you need to make these signals ports so they can be accessed by another module. The registers themselves, and the process to write and read them are all in one module. It really helps to start by drawing a simplified block diagram of your system and figure out what signals you need to pass between the various modules. Then define what the requirements are for the signals, for example how the "RAM" gets written - when does the write data need to be valid with respect to the write enable, clock, etc. It's much harder to start writing VHDL right away and trying to work from a bottom-up approach. Many seasoned veterans of logic design may prefer to work that way, but it's only possible because they start with a good idea of the system and its interconnect requirements. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.230.168 with SMTP id sz8mr4172784obc.9.1382248181559; Sat, 19 Oct 2013 22:49:41 -0700 (PDT) X-Received: by 10.50.79.228 with SMTP id m4mr113888igx.9.1382248181325; Sat, 19 Oct 2013 22:49:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no22694003qav.0!news-out.google.com!9ni58915qaf.0!nntp.google.com!i2no22693994qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Oct 2013 22:49:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: timing verification From: Mike Treseler Injection-Date: Sun, 20 Oct 2013 05:49:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7141 On Monday, October 14, 2013 1:54:43 PM UTC-7, alb wrote: > I'm at the point where I might need to verify timing relationships > between two or more signals/variables in my code. > > I've read PSL assertions can serve the need, but what if I need this > task to be done by yesterday and I do not know PSL at all? Any > suggestion on investing some of my time in learning PSL? Timing relationships are best covered by static timing analysis. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Mon, 21 Oct 2013 16:57:21 +0200 Lines: 16 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net W5++qmDASSCnHLi+bczxQgjiyDP26ZXvrykFDkSRFeXv3tUvM8 Cancel-Lock: sha1:hHsC+ZQIdsHepmDxQICPEQfqanQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 In-Reply-To: X-Enigmail-Version: 1.6a1pre Xref: news.eternal-september.org comp.lang.vhdl:7142 Hi Mike, On 20/10/2013 07:49, Mike Treseler wrote: >> I'm at the point where I might need to verify timing relationships >> between two or more signals/variables in my code. [] > Timing relationships are best covered by static timing analysis. How would you use static timing analysis to verify that a read operation has happened 'n clocks' after a write operation? Or that a sequence of events has happened? I've always used static timing analysis to verify that propagation delays were smaller than my clock rate (corrected for setup/hold time), but nothing more than that. From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.142.67 with SMTP id ru3mr1008373obb.17.1382547621614; Wed, 23 Oct 2013 10:00:21 -0700 (PDT) X-Received: by 10.49.2.33 with SMTP id 1mr52221qer.38.1382547621348; Wed, 23 Oct 2013 10:00:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no29624738qav.0!news-out.google.com!rn2ni119355pbc.1!nntp.google.com!i2no29624731qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Oct 2013 10:00:21 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.226.175.89; posting-account=4d_lDQoAAADxxhVFIaC-WFcpEaHpQ4mH NNTP-Posting-Host: 81.226.175.89 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76f170d9-b810-4f9c-bf04-09d155f73594@googlegroups.com> Subject: Lattice EFB I2C core works in simulation, but not on hardware From: littlegamer Injection-Date: Wed, 23 Oct 2013 17:00:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7143 Hello, Perhaps someone with Lattice experience can answer this for me. I am buildi= ng a design on a MachXO2 using the EFB for I2C slave communication. I built= my own state machine for writing and reading to the wishbone bus. In simul= ation, it works perfectly. I can read and write to the I2C lines, see what = the wishbone bus is doing, data is processed correctly. In simulation. When= I synthesize the design and feed it to an actual MachXO2, it doesn't work = at all. The I2C core is alive, it responds to addresses by sending ACKs, al= so when writing data, but when trying to read the exact same address, it fe= eds me rubbish (like 0x0B or 0x0F), repeatedly writing will cause the devic= e to crash by pulling the SDA or SCL lines hard low.=20 I'm using the internal oscillator at 8MHz portmapped to the Wishbone bus. I= 've changed the statemachine to do the same thing specified in the referenc= e designs (as in, discarding the read buffer twice, disabling and re-enabli= ng the interrupt source for TRRDY, waiting for BUSY low etc). Apart from th= e extra wishbone transactions, simulation results and hardware results rema= in the same. I have no clue where to look for. Can anyone give me pointers? Regards, littlegamer From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Lattice EFB I2C core works in simulation, but not on hardware Date: Fri, 25 Oct 2013 10:18:16 +0200 Lines: 35 Message-ID: References: <76f170d9-b810-4f9c-bf04-09d155f73594@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net rL11AXlpvbpKN80FlI7ycg6Mi7P7cqcOGDs91kWDa9/9IKQ6+W Cancel-Lock: sha1:FbNVDPJ+Y2Q8KTjKRUBHBQeJ7jg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 In-Reply-To: <76f170d9-b810-4f9c-bf04-09d155f73594@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7144 Hi littlegamer, On 23/10/2013 19:00, littlegamer wrote: [] > Perhaps someone with Lattice experience can answer this for me. I am > building a design on a MachXO2 using the EFB for I2C slave > communication. I built my own state machine for writing and reading > to the wishbone bus. In simulation, it works perfectly. I can read > and write to the I2C lines, see what the wishbone bus is doing, data > is processed correctly. In simulation. When I synthesize the design > and feed it to an actual MachXO2, it doesn't work at all. have you run a post-synth simulation? Have you performed static timing analysis? If not I strongly invite you to do so before going on the bench. > The I2C > core is alive, it responds to addresses by sending ACKs, also when > writing data, but when trying to read the exact same address, it > feeds me rubbish (like 0x0B or 0x0F), repeatedly writing will cause > the device to crash by pulling the SDA or SCL lines hard low. Be aware that often simulation vs. reality mismatches are due to 'incomplete simulation environment'. Check that all the input to your logic is properly modeled in your simulation, including timing and most of all power-up/rst sequence. HTH, Al p.s.: How do you define a 'device crash'? I've seen a car crash yesterday and I bet that I do not have to explain you what a car crash is. My suggestion: try to describe your problem according to your observations, not to your - understandable - frustration for having a not working hardware. From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.61.77 with SMTP id n13mr2158141obr.34.1382730802490; Fri, 25 Oct 2013 12:53:22 -0700 (PDT) X-Received: by 10.49.40.168 with SMTP id y8mr1966qek.42.1382730802187; Fri, 25 Oct 2013 12:53:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!i2no34187987qav.0!news-out.google.com!z6ni91518pbu.0!nntp.google.com!i2no34187958qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Oct 2013 12:53:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.66.32.10; posting-account=G2Q-IAoAAADNUg_BhH_fy0sl63kpLuGU NNTP-Posting-Host: 194.66.32.10 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492) From: saeed omer Injection-Date: Fri, 25 Oct 2013 19:53:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:7145 hello my friends, I want to help me to write VHDL code for (SN7492) thanks saeed From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.66.121.194 with SMTP id lm2mr8708658pab.20.1382968128267; Mon, 28 Oct 2013 06:48:48 -0700 (PDT) X-Received: by 10.49.71.230 with SMTP id y6mr42249qeu.17.1382968127986; Mon, 28 Oct 2013 06:48:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!y3no82852256pbx.0!news-out.google.com!rn2ni128679pbc.1!nntp.google.com!i2no5906974qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Oct 2013 06:48:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.66.32.10; posting-account=G2Q-IAoAAADNUg_BhH_fy0sl63kpLuGU NNTP-Posting-Host: 194.66.32.10 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <236b317c-74df-4ab2-9aef-afa0b819af50@googlegroups.com> Subject: Re: DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492) From: saeed omer Injection-Date: Mon, 28 Oct 2013 13:48:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7146 hello my friends who do someone want to help me to write VHDL code for (SN7492)? my email: eng14551@gmail.com thanks saeed From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492) Date: Mon, 28 Oct 2013 09:52:00 -0400 Organization: Alacron, Inc. Lines: 20 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Oct 2013 13:52:51 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="21722"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PNSHq/NXqGaNiU0LRwJ5hstxsfvGK+l4=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:wHxPPLHyp7aTEtN7PGkPsjf0gRE= Xref: news.eternal-september.org comp.lang.vhdl:7147 saeed omer wrote: > hello my friends, > > I want to help me to write VHDL code for (SN7492) > > thanks > saeed > This data sheet: http://www.ti.com/lit/ds/symlink/sn74ls92.pdf should help you model this part with VHDL. On the other hand, nobody in their right mind would design a counter like this nowadays. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:13 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: DIVIDE-BY-TWELVE DECODE COUNTERS( SN7492) Date: Mon, 28 Oct 2013 09:10:06 -0700 Organization: Highland Technology, Inc. Lines: 21 Message-ID: <20131028091006.17d8b443@rg.highlandtechnology.com> References: <236b317c-74df-4ab2-9aef-afa0b819af50@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="5438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+hAx9BQ9E4V896HBrhEfbH" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:yl3Simm/BflDY29Qj6tOhcSe7c0= Xref: news.eternal-september.org comp.lang.vhdl:7148 On Mon, 28 Oct 2013 06:48:47 -0700 (PDT) saeed omer wrote: > hello my friends > > > who do someone want to help me to write VHDL code for (SN7492)? > my email: > eng14551@gmail.com > > thanks > saeed > I don't know any FPGA consultants who'll take less than $90/hr, nor who'll take under a 10 hour job. So I'm assuming this problem is worth $900 to have solved for you? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.182.204.33 with SMTP id kv1mr7542206obc.26.1382989013075; Mon, 28 Oct 2013 12:36:53 -0700 (PDT) X-Received: by 10.50.171.169 with SMTP id av9mr225409igc.11.1382989012206; Mon, 28 Oct 2013 12:36:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no6783329qav.0!news-out.google.com!rn2ni128679pbc.1!nntp.google.com!i2no6783270qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Oct 2013 12:36:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d5a69f1-4923-44f8-94b8-31535078cee7@googlegroups.com> Subject: Re: timing verification From: Mike Treseler Injection-Date: Mon, 28 Oct 2013 19:36:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7149 On Monday, October 21, 2013 7:57:21 AM UTC-7, alb wrote: > How would you use static timing analysis to verify that a read operation > has happened 'n clocks' after a write operation? Or that a sequence of > events has happened? Static timing covers setup and hold timing relationships for all registers in the programmable device and external registers driving or reading the programmable device ports. 'n clocks' type verifications for a synchronous design that meets Fmax static timing, can be covered by a synchronous testbench that meets the setup and hold pin requirements of the programmable device design. > I've always used static timing analysis to verify that propagation > delays were smaller than my clock rate (corrected for setup/hold time), > but nothing more than that. Yes, device Fmax is the basic constraint and the easiest to use, but IO constraints are most critical for the testbench and on the real bench. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:13 2015 X-Received: by 10.58.128.33 with SMTP id nl1mr10135295veb.28.1382990796125; Mon, 28 Oct 2013 13:06:36 -0700 (PDT) X-Received: by 10.50.61.162 with SMTP id q2mr229117igr.10.1382990795829; Mon, 28 Oct 2013 13:06:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.88.MISMATCH!i2no6901202qav.0!news-out.google.com!rn2ni128679pbc.1!nntp.google.com!i2no6901145qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Oct 2013 13:06:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5287ccd8-0806-4bc0-b247-d070675a8cc8@googlegroups.com> Subject: Re: combinational loops From: Mike Treseler Injection-Date: Mon, 28 Oct 2013 20:06:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7150 On Friday, September 27, 2013 12:48:07 AM UTC-7, alb wrote: > > After reviewing your FSM though, I think you might do better with > > separate, smaller state machine(s) for the reusable states, and > > implement a hierarchical state machine. There is no point in > > combining all the reusable and unique states into the same FSM. I prefer to concatenate blocks of state machine update code for multiple machines with one state variable per block. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Mon, 28 Oct 2013 21:25:30 +0100 Lines: 35 Message-ID: References: <3d5a69f1-4923-44f8-94b8-31535078cee7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net auQ+DPCAcBMNQ2A8rmMxSAdvbM8EFy1H0h+U1o1JzpfT5444b+ Cancel-Lock: sha1:SSPPLUuXuT/56U1fzuSVhEzyzko= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 In-Reply-To: <3d5a69f1-4923-44f8-94b8-31535078cee7@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7151 Hi Mike, On 28/10/2013 20:36, Mike Treseler wrote: [] >> How would you use static timing analysis to verify that a read >> operation has happened 'n clocks' after a write operation? Or that >> a sequence of events has happened? > > Static timing covers setup and hold timing relationships for all > registers in the programmable device and external registers driving > or reading the programmable device ports. > > 'n clocks' type verifications for a synchronous design that meets > Fmax static timing, can be covered by a synchronous testbench that > meets the setup and hold pin requirements of the programmable device > design. This is what I typically do myself as well, but that wouldn't be possible if instead of 'pin requirements' we were talking about 'interface requirements' of an internal interface of your design. I guess the suggestions of using assertions through 'wrappers' may solve the issue. >> I've always used static timing analysis to verify that propagation >> delays were smaller than my clock rate (corrected for setup/hold >> time), but nothing more than that. > > Yes, device Fmax is the basic constraint and the easiest to use, but > IO constraints are most critical for the testbench and on the real > bench. I deal often with asynchronous interfaces therefore I typically synchronize them before use and do not constraint them at all. Actually is there any good guide on how to constraint I/O?. From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: combinational loops Date: Mon, 28 Oct 2013 21:39:33 +0100 Lines: 25 Message-ID: References: <289b4b10-8b7f-4424-8bf6-32ddf3cc4748@googlegroups.com> <5a148b06-4241-444b-849c-75adf26294a2@googlegroups.com> <5287ccd8-0806-4bc0-b247-d070675a8cc8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net LQNtrKObpeUaIk1ERnOxvQwH+UY4MzrooZIjnMkRgbmSbGeaMs Cancel-Lock: sha1:TUzQI4uxviHY/JOXiQ7xZHKFHYE= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 In-Reply-To: <5287ccd8-0806-4bc0-b247-d070675a8cc8@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7152 Hi Mike, On 28/10/2013 21:06, Mike Treseler wrote: >>> After reviewing your FSM though, I think you might do better >>> with separate, smaller state machine(s) for the reusable states, >>> and implement a hierarchical state machine. There is no point in >>> combining all the reusable and unique states into the same FSM. > > I prefer to concatenate blocks of state machine update code for > multiple machines with one state variable per block. how do you prevent state machines not to 'step on each other toes'? I had three state machines with three state variables, but living in one procedure only I found myself 'tempted' at changing a state variable from within another state machine logic. Being very skeptical about my rigorousness, I waved this problem separating the fsms in three different procedures with state variables passed through parameters called in the same way as the global variables [1] but with different type (in or inout) for each fsm. The level of separation I achieve is good enough, with a minimal overhead. [1] the variables are locally scoped to the process but, being the process the only statement in the architecture, they act as if they were 'global' in the architecture scope. From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: timing verification Date: Mon, 28 Oct 2013 19:16:38 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Oct 2013 23:17:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="11963"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2Cv25MVJ+pVqRGaHwx93i" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:uFZ5+2p2GcAIelnfXYTMbr+h8jc= Xref: news.eternal-september.org comp.lang.vhdl:7153 On 10/16/2013 4:32 AM, HT-Lab wrote: > Hi Rickman, > > On 15/10/2013 23:42, rickman wrote: > ... >>> >>> I do functional verification through TLM in VHDL and I'm about to dig in >>> the usage of OSVVM for constrained coverage. Unfortunately this approach >>> does not give me the level of observability I needed, especially on >>> internal bus protocols, that's why I wanted to explore other means. >> >> Sounds like I am a bit behind in this. I have always verified timing by >> setting timing constrains for the P&R tool which verifies the design >> meets the timing constraints. Is there some other aspect of timing that >> constraints don't work for? > > You use assertions to make sure that your timing constraints itself are > correct. For example, there are occasions where it is not easy to > determine if you always have a multi-cycle path (e.g. a designs with > multiple clock domains). In this case an assertion can help (or prove > exhaustively if you use a formal tool). For false path an assertion even > becomes a must have as checking them manually (i.e. looking at a gate > level schematic!) is an error prone and a very time consuming activity. Can you explain? I'm not following how an assertion will help. >> PSL, OVL, SVA, OSVVM, TLM...??? I need to check this out I expect. >> >> For timing at higher levels, like "does this happen three clock cycles >> after that happens", I have always just verified that by inspection or >> functional simulation. Are these tools ways of adding formal >> verification of this sort of timing? > > You can quite easily add an embedded assertion (supplied with the design > itself) that always checks that A happens 3 clock cycles after B. The > problem with Verilog/VHDL is that they are very verbose and hence more > susceptible to bugs, languages like PSL/SVA are designed for this task > and hence are very concise, easy to use for sequences and un-ambiguous. > You can write a page of VHDL/Verilog or 1 line of PSL/SVA. Counting clock cycles is not the same as timing analysis. That would be design verification. I can't think of an example of needing to verify something like this. I guess my designs aren't so complex... or maybe not so simple? -- Rick From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!nx01.iad01.newshosting.com!newshosting.com!69.16.185.113.MISMATCH!peer03.iad.highwinds-media.com!feed-me.highwinds-media.com!peer03.fr7!news.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx17.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: timing verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131028-1, 28/10/2013), Outbound message X-Antivirus-Status: Clean Lines: 44 Message-ID: <9YKbu.50013$5L5.38998@fx17.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1383037829 86.29.12.221 (Tue, 29 Oct 2013 09:10:29 UTC) NNTP-Posting-Date: Tue, 29 Oct 2013 09:10:29 UTC Organization: virginmedia.com Date: Tue, 29 Oct 2013 09:10:25 +0000 X-Received-Body-CRC: 569027823 X-Received-Bytes: 3100 Xref: news.eternal-september.org comp.lang.vhdl:7154 Hi Rickman, On 28/10/2013 23:16, rickman wrote: > On 10/16/2013 4:32 AM, HT-Lab wrote: .. >> >> You use assertions to make sure that your timing constraints itself are >> correct. For example, there are occasions where it is not easy to >> determine if you always have a multi-cycle path (e.g. a designs with >> multiple clock domains). In this case an assertion can help (or prove >> exhaustively if you use a formal tool). For false path an assertion even >> becomes a must have as checking them manually (i.e. looking at a gate >> level schematic!) is an error prone and a very time consuming activity. > > Can you explain? I'm not following how an assertion will help. You put an assertion on the control signals of the path so that the assertion will fire/fail when the false path is selected (i.e. data flows through the path). Tools like Fishtail generates the false path assertions automatically for you. .. >> >> You can quite easily add an embedded assertion (supplied with the design >> itself) that always checks that A happens 3 clock cycles after B. The >> problem with Verilog/VHDL is that they are very verbose and hence more >> susceptible to bugs, languages like PSL/SVA are designed for this task >> and hence are very concise, easy to use for sequences and un-ambiguous. >> You can write a page of VHDL/Verilog or 1 line of PSL/SVA. > > Counting clock cycles is not the same as timing analysis. That would be > design verification. I can't think of an example of needing to verify > something like this. I guess my designs aren't so complex... or maybe > not so simple? true, using assertions for false and multi-cycle path is merging functional and timing verification. However, your static timing tool is not going to tell you if you path is false or not, it just give you the propagation delay. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.182.116.200 with SMTP id jy8mr470851obb.22.1383072689612; Tue, 29 Oct 2013 11:51:29 -0700 (PDT) X-Received: by 10.50.40.4 with SMTP id t4mr366680igk.15.1383072689398; Tue, 29 Oct 2013 11:51:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!o2no8890384qas.0!news-out.google.com!9ni57qaf.0!nntp.google.com!i2no8890280qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Oct 2013 11:51:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.131.240; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.131.240 References: <3d5a69f1-4923-44f8-94b8-31535078cee7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <712bb7c0-664d-4b17-a2a7-f2d71c9e6fbf@googlegroups.com> Subject: Re: timing verification From: Mike Treseler Injection-Date: Tue, 29 Oct 2013 18:51:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7155 > > 'n clocks' type verifications for a synchronous design that meets > > Fmax static timing, can be covered by a synchronous testbench that > > meets the setup and hold pin requirements of the programmable device > > design. > On Monday, October 28, 2013 1:25:30 PM UTC-7, alb wrote: > > This is what I typically do myself as well, but that wouldn't be > possible if instead of 'pin requirements' we were talking about > 'interface requirements' of an internal interface of your design. I just use a fast enough clock so that these are all synchronous and covered by the testbench. > I deal often with asynchronous interfaces therefore I typically > synchronize them before use and do not constraint them at all. Even in this case, the clock constraint must match the hardware. Duty cycle etc. > Actually > is there any good guide on how to constraint I/O?. No. It's a mess. Trial and error. Synopsis/Quartus sdc works the best. https://www.google.com/search?q=sdc+file+example Good luck -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.58.39.202 with SMTP id r10mr2161328vek.12.1383144562616; Wed, 30 Oct 2013 07:49:22 -0700 (PDT) X-Received: by 10.49.94.116 with SMTP id db20mr67188qeb.19.1383144562596; Wed, 30 Oct 2013 07:49:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i2no1208887qav.0!news-out.google.com!9ni1qaf.0!nntp.google.com!i2no1208885qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Oct 2013 07:49:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.73.206.123; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 85.73.206.123 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1183fee2-de1e-4aba-8854-232a256298e3@googlegroups.com> Subject: FREE download of HercuLeS high-level synthesis! From: Nikolaos Kavvadias Injection-Date: Wed, 30 Oct 2013 14:49:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1920 Xref: news.eternal-september.org comp.lang.vhdl:7156 Dear all, HercuLeS by Ajax Compilers, Inc. (http://www.ajaxcompilers.com) is an easy to use high-level synthesis (HLS) environment for the automatic translation of algorithms to hardware. HercuLeS is suitable for both hardware-oriented and software-minded engineers. You can download the FREE version of HercuLeS for Windows 7 (64-bit) and Linux (32-bit and 64-bit) from here: http://www.nkavvadias.com/temp/index.php No registrations, no emails, no additional downloads, no fuss! Just get the file, read the instructions from this page, and you are set! Compared to the BASIC and FULL versions, there are some features intentionally missing from the FREE version; please consult the HercuLeS feature matrix for full details: http://www.nkavvadias.com/hercules/hercules-feature-matrix.html Best regards, Nikolaos Kavvadias CEO Ajax Compilers Kornarou 12 Rd, Nea Ampliani, 35100 Lamia Greece From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.58.112.195 with SMTP id is3mr5736419veb.29.1383576439848; Mon, 04 Nov 2013 06:47:19 -0800 (PST) X-Received: by 10.182.135.227 with SMTP id pv3mr18788obb.26.1383576439772; Mon, 04 Nov 2013 06:47:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!i2no9197538qav.0!news-out.google.com!9ni10200qaf.0!nntp.google.com!o2no18179983qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Nov 2013 06:47:19 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.85.219.144; posting-account=Ug9nxwoAAACFxlURdRqcYVJyEM9H4mAs NNTP-Posting-Host: 141.85.219.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3f6f18f5-c83b-46ed-89b8-f483fc092b4c@googlegroups.com> Subject: Verilog Binary Divider From: Kristo Godari Injection-Date: Mon, 04 Nov 2013 14:47:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: news.eternal-september.org comp.lang.vhdl:7157 I need a Verilog behavioral model (verilog behavioral code) for: - unsigned 8-bit division The module I have to use is this one: module divider( output reg[7:0] q, output reg[7:0] r, input [7:0] a,b); endmodule where a=b*q+r Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms to solve it. Can someone help me? From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Verilog Binary Divider Date: Mon, 04 Nov 2013 16:24:58 +0100 Lines: 43 Message-ID: References: <3f6f18f5-c83b-46ed-89b8-f483fc092b4c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net udviL7s5/V8FZavaR1yIgQQ0oLbb1xwQP0iToPiA0mg/JJE953 Cancel-Lock: sha1:qszbr1/nGTqxDyLH351E01IJGP8= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <3f6f18f5-c83b-46ed-89b8-f483fc092b4c@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7158 Hi Kristo, On 04/11/2013 15:47, Kristo Godari wrote: > I need a Verilog behavioral model (verilog behavioral code) for: > - unsigned 8-bit division > > The module I have to use is this one: > > module divider( > output reg[7:0] q, > output reg[7:0] r, > input [7:0] a,b); > endmodule > > where a=b*q+r > > Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms > to solve it. > > Can someone help me? why not posting on comp.lang.verilog? this is a vhdl newsgroup. About cross-posting I also have some comments: try to avoid it if at all possible and if necessary try to mention that you crossposted the message on another group so that people might be able to track and post accordingly. On the particular subject (even if does not make a difference if it is verilog or vhdl), I would try to understand what is the peculiarity of each algorithm and which of these benefits and costs is more suited to your application. Google is your friend here, a first search brings up a lot of stuff on power awareness, speed, and also some models (opencores). Another possibility is to implement them all and then pick up the one that performs better in your particular application. I usually tend to use comparison when it comes to performances optimization, but only if the gain is worth the pain! HTH, Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.182.246.39 with SMTP id xt7mr4573340obc.40.1383688019511; Tue, 05 Nov 2013 13:46:59 -0800 (PST) X-Received: by 10.182.45.170 with SMTP id o10mr1581obm.41.1383688019282; Tue, 05 Nov 2013 13:46:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!o2no21053600qas.0!news-out.google.com!9ni12508qaf.0!nntp.google.com!i2no12076016qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Nov 2013 13:46:59 -0800 (PST) In-Reply-To: <3f6f18f5-c83b-46ed-89b8-f483fc092b4c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.73.206.123; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 85.73.206.123 References: <3f6f18f5-c83b-46ed-89b8-f483fc092b4c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Verilog Binary Divider From: Nikolaos Kavvadias Injection-Date: Tue, 05 Nov 2013 21:46:59 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7159 Hi Kristo Why not assess the offers you have in freelancer? Some offers may guarantee= quality work with good quality/$ balance for you. Best regards Nikolaos Kavvadias =CE=B7 =CE=94=CE=B5=CF=85=CF=84=CE=AD=CF=81=CE=B1, 4 =CE=9D=CE=BF=CE=B5=CE= =BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2013 4:47:19 =CE=BC.=CE=BC. UTC+2, =CE=BF= =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Kristo Godari =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > I need a Verilog behavioral model (verilog behavioral code) for: >=20 > - unsigned 8-bit division=20 >=20 >=20 >=20 > The module I have to use is this one: >=20 >=20 >=20 > module divider( >=20 > output reg[7:0] q, >=20 > output reg[7:0] r, >=20 > input [7:0] a,b); >=20 > endmodule >=20 >=20 >=20 > where a=3Db*q+r >=20 >=20 >=20 > Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms=20 >=20 > to solve it. >=20 >=20 >=20 > Can someone help me? From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: I need an or_reduce for an array of std_logic_vectors Date: Wed, 6 Nov 2013 09:34:25 -0600 Organization: A noiseless patient Spider Lines: 24 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="6135"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183REOg6YQH+Ny/gKLQMqUp38q0V+WSpOc=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:YbYOkSvVmfvCPPbzl9NmyfUM/wg= Xref: news.eternal-september.org comp.lang.vhdl:7160 Hi, If I have a std_logic_vector: signal vec : std_logic_vector(0 to N); I can easily get the OR of all the bits with or_reduce(vec). What what if I have an array of std_logic_vectors: type arr_type is array (0 to X) of std_logic_vector(0 to N) signal my_arr : arr_type; I want a function that ORs all fo the vectors in the array to produce one result std_logic_vector(0 to N) where each bit of the result is the OR of all the bits at that location. I.e. bit 0 of the result is the OR of all the bit 0s of each entry in my_arr? Does something like this already exist or if not, hopefully someone can sketch out a function that would be able to do this for variable X and N? I've made some attempts with for/generate and for/loop but I didn't hit on anything that would compile. Thanks in advance. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Wed, 6 Nov 2013 09:48:28 -0600 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="15703"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zwdaSlMRy6BCMRc9hNW5i9iAiAMhHp1M=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:8URk3RZMeY3LoWdVioBeLgody1E= Xref: news.eternal-september.org comp.lang.vhdl:7161 In article , richardn@nospam.com says... > > Hi, > > If I have a std_logic_vector: > > signal vec : std_logic_vector(0 to N); > > I can easily get the OR of all the bits with or_reduce(vec). > > What what if I have an array of std_logic_vectors: > > type arr_type is array (0 to X) of std_logic_vector(0 to N) > signal my_arr : arr_type; > > I want a function that ORs all fo the vectors in the array to produce one result > std_logic_vector(0 to N) where each bit of the result is the OR of all the bits at that > location. I.e. bit 0 of the result is the OR of all the bit 0s of each entry in my_arr? > > Does something like this already exist or if not, hopefully someone can sketch out a function > that would be able to do this for variable X and N? I've made some attempts with > for/generate and for/loop but I didn't hit on anything that would compile. Thanks in > advance. > > Richard Nicholas One thing I forgot to mention: this does not need to be synthesizable. Its for behavioral code. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Wed, 06 Nov 2013 16:55:00 +0100 Lines: 39 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 6OKZLpxRbFaO3O34UjH2Hgw7XPv45KLbqhxhvubmTcjIW5pP4Z Cancel-Lock: sha1:XxoioMs1SJq+3bNHcPKGjU2i9+Y= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7162 Hi Richard, On 06/11/2013 16:34, Richard Nicholas wrote: [] > type arr_type is array (0 to X) of std_logic_vector(0 to N) > signal my_arr : arr_type; > > I want a function that ORs all fo the vectors in the array to produce one result > std_logic_vector(0 to N) where each bit of the result is the OR of all the bits at that > location. I.e. bit 0 of the result is the OR of all the bit 0s of each entry in my_arr? If I understood correctly your question I guess that something along these lines should work. -- not compiled nor tried... just a hint! function you_name_it(arg : my_arr) return std_logic is variable temp : std_logic_vector (arg'length - 1 downto 0); begin -- WARNING: no sanity check on vector dimension! for i in 0 to temp'length - 1 loop temp(i) := or_reduce(arg(i)(arg(i)'range)); end loop; return or_reduce(temp); end; > > Does something like this already exist or if not, hopefully someone can sketch out a function > that would be able to do this for variable X and N? I've made some attempts with > for/generate and for/loop but I didn't hit on anything that would compile. Thanks in > advance. Maybe it would be more useful for you to post your attempts and try to understand why you did not manage. Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.236.147.18 with SMTP id s18mr2683907yhj.28.1383791286069; Wed, 06 Nov 2013 18:28:06 -0800 (PST) X-Received: by 10.49.15.198 with SMTP id z6mr169413qec.5.1383791286036; Wed, 06 Nov 2013 18:28:06 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i2no14398490qav.0!news-out.google.com!9ni14580qaf.0!nntp.google.com!i2no14398480qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 6 Nov 2013 18:28:05 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Subject: Re: I need an or_reduce for an array of std_logic_vectors From: KJ Injection-Date: Thu, 07 Nov 2013 02:28:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2112 Xref: news.eternal-september.org comp.lang.vhdl:7163 > On Wednesday, November 6, 2013 10:34:25 AM UTC-5, Richard Nicholas wrote: > What what if I have an array of std_logic_vectors: > > type arr_type is array (0 to X) of std_logic_vector(0 to N) > signal my_arr : arr_type; > > I want a function that ORs all fo the vectors in the array to produce one result > std_logic_vector(0 to N) where each bit of the result is the OR of all the bits > at that location. I.e. bit 0 of the result is the OR of all the bit 0s of each > entry in my_arr? > > Does something like this already exist or if not, hopefully someone can sketch > out a function that would be able to do this for variable X and N? -- Not tested, but pretty close...definitely more than just a sketch function or_reduce(L: arr_type) return std_logic is variable RetVal: std_logic_vector(L'range); begin for i in L'range loop RetVa(i) := or_reduce(L(i)); end loop; return(RetVal); end function or_reduce; Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Thu, 07 Nov 2013 10:00:24 +0100 Lines: 21 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net i2sFL13WcmjduNlhR+sVeAuYWb8ZN4GdL2sr8YHEoNAneMlV4n Cancel-Lock: sha1:kPLxJufn5WsgwHrYOqlmVeb/iq0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7164 Hi KJ, On 07/11/2013 03:28, KJ wrote: [] > -- Not tested, but pretty close...definitely more than just a sketch > function or_reduce(L: arr_type) return std_logic is > variable RetVal: std_logic_vector(L'range); > begin > for i in L'range loop > RetVa(i) := or_reduce(L(i)); > end loop; > return(RetVal); I guess it should read: return(or_reduce(RetVal)); > end function or_reduce; I always envy your capability to write such neat functions! Mine was close, but certainly some steps behind :-) From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.42.60.130 with SMTP id q2mr2419953ich.21.1383830212210; Thu, 07 Nov 2013 05:16:52 -0800 (PST) X-Received: by 10.182.115.134 with SMTP id jo6mr120078obb.6.1383830212039; Thu, 07 Nov 2013 05:16:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!i2no15062260qav.0!news-out.google.com!9ni15040qaf.0!nntp.google.com!i2no15062250qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 Nov 2013 05:16:51 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: I need an or_reduce for an array of std_logic_vectors From: KJ Injection-Date: Thu, 07 Nov 2013 13:16:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:7165 On Thursday, November 7, 2013 4:00:24 AM UTC-5, alb wrote: > I guess it should read: > return(or_reduce(RetVal)); That might be want the OP really wants, but what he stated was "where each bit of the result is the OR of all the bits at that location." which means he wants a vector of 'or_reduce' results, not an 'or_reduce' of the 'or_reduce' results. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Thu, 07 Nov 2013 14:42:55 +0100 Lines: 19 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net h3wKZK+JgaFYUHJ1rhDEKgW2kFnA5linMhZUDUSC8gIxQu6KBh Cancel-Lock: sha1:PXrhPGa+stJpgL2Mn0GXW2bkVbQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7166 Hi KJ, On 07/11/2013 14:16, KJ wrote: > On Thursday, November 7, 2013 4:00:24 AM UTC-5, alb wrote: >> I guess it should read: return(or_reduce(RetVal)); > > That might be want the OP really wants, but what he stated was "where > each bit of the result is the OR of all the bits at that location." > which means he wants a vector of 'or_reduce' results, not an > 'or_reduce' of the 'or_reduce' results. You are right, I 'extrapolated' a little bit too much :-). But then the return value of your function should be a std_logic_vector the size of which is unknown until instantiation. Can an unconstrained array be the result of a function? I believe I had troubles with this in the past. Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Thu, 7 Nov 2013 10:46:01 -0600 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="17285"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18/xLSPORJ2wi7bI6JAPBZUAuNxvKbji3Q=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:ixJlv3k0hVrdYlBax+eQm/5r2Pg= Xref: news.eternal-september.org comp.lang.vhdl:7167 In article <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com>, kkjennings@sbcglobal.net says... > > > On Wednesday, November 6, 2013 10:34:25 AM UTC-5, Richard Nicholas wrote: > > What what if I have an array of std_logic_vectors: > > > > type arr_type is array (0 to X) of std_logic_vector(0 to N) > > signal my_arr : arr_type; > > > > I want a function that ORs all fo the vectors in the array to produce one result > > std_logic_vector(0 to N) where each bit of the result is the OR of all the bits > > at that location. I.e. bit 0 of the result is the OR of all the bit 0s of each > > entry in my_arr? > > > > Does something like this already exist or if not, hopefully someone can sketch > > out a function that would be able to do this for variable X and N? > > -- Not tested, but pretty close...definitely more than just a sketch > function or_reduce(L: arr_type) return std_logic is > variable RetVal: std_logic_vector(L'range); > begin > for i in L'range loop > RetVa(i) := or_reduce(L(i)); > end loop; > return(RetVal); > end function or_reduce; Thank you both for your help. I probably did not explain what I was looking for clearly. I wanted a function that would just OR all the vectors in the array, not or_reduce each vector, creating a new vector of those results. With the help of a colleague, I think we have a solution that does what I need: function array_or( vectors : req_arr) return std_ulogic_vector is variable result : std_ulogic_vector (vectors(0)'range); begin result := vectors(0); for i in 1 to req_arr'length-1 loop result := result or vectors(i); end loop; return result; end array_or; It could be made slightly more general by not taking advantage of the fact that all the vectors are of the form (0 to N). Thanks again. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.58.201.36 with SMTP id jx4mr2552619vec.35.1383843442824; Thu, 07 Nov 2013 08:57:22 -0800 (PST) X-Received: by 10.182.246.72 with SMTP id xu8mr113147obc.15.1383843442628; Thu, 07 Nov 2013 08:57:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i2no15339835qav.0!news-out.google.com!9ni15680qaf.0!nntp.google.com!o2no24316757qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 Nov 2013 08:57:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2131c181-b558-4de3-ad0a-06ac97e7ea44@googlegroups.com> Subject: Re: I need an or_reduce for an array of std_logic_vectors From: KJ Injection-Date: Thu, 07 Nov 2013 16:57:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2022 Xref: news.eternal-september.org comp.lang.vhdl:7168 On Thursday, November 7, 2013 8:42:55 AM UTC-5, alb wrote: > But then the return value of your function should be a std_logic_vector the > size of which is unknown until instantiation. Can an unconstrained array be > the result of a function? I believe I had troubles with this in the past. You're correct, the result of my function should have been a vector. To answer your question, you don't define the range of an output vector doing so would be an error. I intended to have: function or_reduce(L: arr_type) return std_logic_vector If you define the range of the output vector like this... function or_reduce(L: arr_type) return std_logic_vector(0 to 2) That would produce a compile error. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.182.158.4 with SMTP id wq4mr6178098obb.18.1383988670330; Sat, 09 Nov 2013 01:17:50 -0800 (PST) X-Received: by 10.49.3.105 with SMTP id b9mr325160qeb.6.1383988670299; Sat, 09 Nov 2013 01:17:50 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.87.MISMATCH!o2no26530618qas.0!news-out.google.com!9ni18611qaf.0!nntp.google.com!o2no26530607qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Nov 2013 01:17:50 -0800 (PST) In-Reply-To: <1183fee2-de1e-4aba-8854-232a256298e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.130.27.45; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 79.130.27.45 References: <1183fee2-de1e-4aba-8854-232a256298e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <346d3843-fd40-42a5-b23e-a5fe90903b40@googlegroups.com> Subject: Re: FREE download of HercuLeS high-level synthesis! From: Nikolaos Kavvadias Injection-Date: Sat, 09 Nov 2013 09:17:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7169 Dear all, just to keep you updated with the latest on HercuLeS high-level synthesis: http://www.nkavvadias.com/temp/index.php http://www.ajaxcompilers.com New versions for Windows 7 (64-bit) and Linux (64-bit) have recently been uploaded. Here is the update summary: 2013-11-06: HercuLeS GUI integration simplifications (Windows 7 only). 2013-10-30: Linux 64-bit version added! (experimental) 2013-10-29: Windows and Linux 32-bit version fix: Garbage collection library was missing. 2013-10-25: Linux 32-bit version added! Best regards Nikolaos Kavvadias CEO Ajax Compilers Kornarou 12 Rd, Nea Ampliani, 35100 Lamia Greece From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.66.220.163 with SMTP id px3mr7001460pac.38.1384216159123; Mon, 11 Nov 2013 16:29:19 -0800 (PST) X-Received: by 10.50.83.6 with SMTP id m6mr286512igy.1.1384216158935; Mon, 11 Nov 2013 16:29:18 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeds.phibee-telecom.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!z6no6839270pbz.1!news-out.google.com!9ni23588qaf.0!nntp.google.com!o2no30392679qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Nov 2013 16:29:18 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.183.6.42; posting-account=V3TcBQoAAACn8N3Z_oiElhEBvt0GHKK0 NNTP-Posting-Host: 64.183.6.42 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL signal and variable assignment From: ramy Injection-Date: Tue, 12 Nov 2013 00:29:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7170 Hi, What is the difference between the two assignments? signal s1 : std_logic_vector(3 downto 0); signal s2 : std_logic_vector(3 downto 0); begin main : process (clock, reset_n) variable v1 : std_logic_vector(3 downto 0) := (others => '0'); variable v2 : std_logic_vector(3 downto 0) := (others => '0'); begin if (reset_n = '0') then s1 <= (others => '0'); s2 <= (others => '0'); elsif (clock'event and clock = '1' ) then -- ASSIGNMENT 1 v1 := '1' + s1; s1 <= v1; -- ASSIGNMENT 2 s2 <= v2; v2 := '1' + s2; end if; end process main; From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal and variable assignment Date: Mon, 11 Nov 2013 16:37:19 -0800 Organization: Highland Technology, Inc. Lines: 39 Message-ID: <20131111163719.002d2212@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="1433"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19V6/ZooHpLG+Uq1KIyr4o3" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:hJzRkLQjCrQ4xWu1dSiPjotJbgg= Xref: news.eternal-september.org comp.lang.vhdl:7171 On Mon, 11 Nov 2013 16:29:18 -0800 (PST) ramy wrote: > Hi, What is the difference between the two assignments? > > signal s1 : std_logic_vector(3 downto 0); > signal s2 : std_logic_vector(3 downto 0); > begin > main : process (clock, reset_n) > variable v1 : std_logic_vector(3 downto 0) := (others => '0'); > variable v2 : std_logic_vector(3 downto 0) := (others => '0'); > begin > if (reset_n = '0') then > s1 <= (others => '0'); > s2 <= (others => '0'); > elsif (clock'event and clock = '1' ) then > > -- ASSIGNMENT 1 > v1 := '1' + s1; > s1 <= v1; > > -- ASSIGNMENT 2 > s2 <= v2; > v2 := '1' + s2; > > end if; > end process main; In VHDL, variable assignments (:=) take effect immediately, the way they would in a software language like C, such that subsequent lines see the changed value. Signal assignments (<=) take effect only at the end of the delta cycle, which for synthesizable code is the same as saying at the end of that run through the process. Subsequent statements in the same process continue to see the old value; only on the next invocation of the process will the new value be visible. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.68.234.165 with SMTP id uf5mr10796589pbc.0.1384223574693; Mon, 11 Nov 2013 18:32:54 -0800 (PST) X-Received: by 10.50.82.33 with SMTP id f1mr338022igy.0.1384223574616; Mon, 11 Nov 2013 18:32:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no6886820pbz.1!news-out.google.com!9ni23588qaf.0!nntp.google.com!o2no30502639qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 11 Nov 2013 18:32:54 -0800 (PST) In-Reply-To: <20131111163719.002d2212@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.183.6.42; posting-account=V3TcBQoAAACn8N3Z_oiElhEBvt0GHKK0 NNTP-Posting-Host: 64.183.6.42 References: <20131111163719.002d2212@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL signal and variable assignment From: ramya.murali.d@gmail.com Injection-Date: Tue, 12 Nov 2013 02:32:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7172 ""In VHDL, variable assignments (:=) take effect immediately, the way they would in a software language like C, such that subsequent lines see the changed value. "" What if the subsequent line is a signal assignment like in Assignment 1? Also, in Assignment 1, is s1 a register? If yes, is setup time applicable to v1? On Monday, November 11, 2013 4:37:19 PM UTC-8, Rob Gaddi wrote: > On Mon, 11 Nov 2013 16:29:18 -0800 (PST) > > ramy wrote: > > > > > Hi, What is the difference between the two assignments? > > > > > > signal s1 : std_logic_vector(3 downto 0); > > > signal s2 : std_logic_vector(3 downto 0); > > > begin > > > main : process (clock, reset_n) > > > variable v1 : std_logic_vector(3 downto 0) := (others => '0'); > > > variable v2 : std_logic_vector(3 downto 0) := (others => '0'); > > > begin > > > if (reset_n = '0') then > > > s1 <= (others => '0'); > > > s2 <= (others => '0'); > > > elsif (clock'event and clock = '1' ) then > > > > > > -- ASSIGNMENT 1 > > > v1 := '1' + s1; > > > s1 <= v1; > > > > > > -- ASSIGNMENT 2 > > > s2 <= v2; > > > v2 := '1' + s2; > > > > > > end if; > > > end process main; > > > > In VHDL, variable assignments (:=) take effect immediately, the way they > > would in a software language like C, such that subsequent lines see the > > changed value. Signal assignments (<=) take effect only at the end of > > the delta cycle, which for synthesizable code is the same as saying at > > the end of that run through the process. Subsequent statements in the > > same process continue to see the old value; only on the next invocation > > of the process will the new value be visible. > > > > -- > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal and variable assignment Date: Tue, 12 Nov 2013 01:26:36 -0500 Organization: A noiseless patient Spider Lines: 115 Message-ID: References: <20131111163719.002d2212@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Nov 2013 06:26:48 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="21154"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19SEEKv5G8xYGN40GdKSiOb" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:S2cLlZe8BdeHjO/JRVsCaKcHn70= Xref: news.eternal-september.org comp.lang.vhdl:7173 On 11/11/2013 9:32 PM, ramya.murali.d@gmail.com wrote: > ""In VHDL, variable assignments (:=) take effect immediately, the way they > would in a software language like C, such that subsequent lines see the > changed value. "" > What if the subsequent line is a signal assignment like in Assignment 1? What line follows does not matter. A variable is updated immediately, period, end of sentence. In example 1 v1 is updated by the assignment before the next line is executed. So v1 takes the value '1' + S1 although I'm not sure what that means. S1 is an SLV and I don't know of a library that defines the '+' operator for a character and an SLV. But then I get rusty in VHDL between projects and I may just be forgetting this one. When the next line is executed s1 will be given the value of v1 so that after the process exits s1 will be updated to the value that was in v1. In example 2 the signal assignment is first so although s2 is assigned the value of v2, it is not actually updated until the process exits, long after v2 is updated by the subsequent statement. The assignment of v2 happens immediately, but since s2 has not been updated v2 gets the old value of s2. > Also, in Assignment 1, is s1 a register? If yes, is setup time applicable to v1? In example 1 s1 is indeed the output of a register. v1 is not the output of a register, rather it is the output of the logic feeding register s1, or you can think of it as the input to the register s1. In the second example v2 is the output of a register because it is used *before* it is assigned. That implies it must remember its value from the last iteration of the code i.e. a register. So both s2 and v2 are the outputs of registers. Rick > On Monday, November 11, 2013 4:37:19 PM UTC-8, Rob Gaddi wrote: >> On Mon, 11 Nov 2013 16:29:18 -0800 (PST) >> >> ramy wrote: >> >> >> >>> Hi, What is the difference between the two assignments? >> >>> >> >>> signal s1 : std_logic_vector(3 downto 0); >> >>> signal s2 : std_logic_vector(3 downto 0); >> >>> begin >> >>> main : process (clock, reset_n) >> >>> variable v1 : std_logic_vector(3 downto 0) := (others => '0'); >> >>> variable v2 : std_logic_vector(3 downto 0) := (others => '0'); >> >>> begin >> >>> if (reset_n = '0') then >> >>> s1<= (others => '0'); >> >>> s2<= (others => '0'); >> >>> elsif (clock'event and clock = '1' ) then >> >>> >> >>> -- ASSIGNMENT 1 >> >>> v1 := '1' + s1; >> >>> s1<= v1; >> >>> >> >>> -- ASSIGNMENT 2 >> >>> s2<= v2; >> >>> v2 := '1' + s2; >> >>> >> >>> end if; >> >>> end process main; >> >> >> >> In VHDL, variable assignments (:=) take effect immediately, the way they >> >> would in a software language like C, such that subsequent lines see the >> >> changed value. Signal assignments (<=) take effect only at the end of >> >> the delta cycle, which for synthesizable code is the same as saying at >> >> the end of that run through the process. Subsequent statements in the >> >> same process continue to see the old value; only on the next invocation >> >> of the process will the new value be visible. >> >> >> >> -- >> >> Rob Gaddi, Highland Technology -- www.highlandtechnology.com >> >> Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Tue, 12 Nov 2013 12:11:48 +0100 Lines: 51 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net aS0v0flYjhwGm8d8zE1KtwYMc9HMeyRck3wzuONt0rg5y7lpq4 Cancel-Lock: sha1:WgoTe1J88UC7oA/VrcjILuB1b24= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7174 Hi Richard, On 07/11/2013 17:46, Richard Nicholas wrote: > Thank you both for your help. I probably did not explain what I was looking for clearly. I > wanted a function that would just OR all the vectors in the array, not or_reduce each vector, > creating a new vector of those results. Reading somehow the OP it should have been indeed clear, I think the preamble with the or_reduce example biased our mindset (or at least mine!). > With the help of a colleague, I think we have a solution that does what I need: > > function array_or( vectors : req_arr) return std_ulogic_vector is > > variable result : std_ulogic_vector (vectors(0)'range); > > begin > result := vectors(0); > for i in 1 to req_arr'length-1 loop > result := result or vectors(i); > end loop; > > return result; > end array_or; Actually you get the same result simply using KJ's function preceded by a 'transpose' function on the array (matrix): my_array_t <= transpose (my_array); my_vector <= or_reduce (my_array_t); This separation will help you reuse your code, since now your functions are not bound to your specific operation. > It could be made slightly more general by not taking advantage of the > fact that all the vectors are of the form (0 to N). Thanks again. IMO that generalization has to go in the data structure, not in the functions which operate on them. If you have an 'array' of 'something', each element has to be the same 'something', but if you have a register instead, you can collect vectors of different sizes. Be aware though that depending on the operation you are doing the value that you pick for elements that need to be padded may affect your result. Padding with zero does not affect an or_reduce, but it does affect an and_reduce! Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal and variable assignment Date: Tue, 12 Nov 2013 13:38:07 +0100 Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net xJopC1IPv6hOjwalXK4LmwO7+bhQUTtbA/+HHjTBOQ7jyfLZE6 Cancel-Lock: sha1:pwxpQeSKZrAVj1b4qnE6gFLBO64= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7175 Hi Ramya, On 12/11/2013 01:29, ramy wrote: > Hi, What is the difference between the two assignments? > signal s1 : std_logic_vector(3 downto 0); > signal s2 : std_logic_vector(3 downto 0); > begin > main : process (clock, reset_n) > variable v1 : std_logic_vector(3 downto 0) := (others => '0'); > variable v2 : std_logic_vector(3 downto 0) := (others => '0'); > begin > if (reset_n = '0') then > s1 <= (others => '0'); > s2 <= (others => '0'); > elsif (clock'event and clock = '1' ) then > > -- ASSIGNMENT 1 > v1 := '1' + s1; > s1 <= v1; > > -- ASSIGNMENT 2 > s2 <= v2; > v2 := '1' + s2; > > end if; > end process main; first of all please avoid using SLV if you need to add something to it. Use an integer or (un)signed instead since '+' functions are standardized in the 'numeric_std' package. Secondly why don't you just simulate it? I actually did it and found what I expected. Thirdly and maybe more to the point, remember that since variables take a value immediately, order of assignment matters. In the first case v1 is simply a combinatorial logic with a summing function which feeds the register s1, in the second case v2 is a register which is fed by a summing function and that is registered again with s2. This means that in the first case you have some comb. logic and a register, in the second case you'll have some comb. logic and two registers, having the operation done in twice the time. HTH, Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal and variable assignment Date: Tue, 12 Nov 2013 13:44:49 +0100 Lines: 13 Message-ID: References: <20131111163719.002d2212@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ObgYnNmZEDSAJpPsLlvUNgUWJCoFV1+NMHXayl4IwSs6aNbEn1 Cancel-Lock: sha1:yjy98qbhqWagO9HqNLgPNk2qD1Y= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7176 Hi Rick, On 12/11/2013 07:26, rickman wrote: [] S1 is an SLV and I don't know of > a library that defines the '+' operator for a character and an SLV. there's no 'character' involved, the operator the OP intended to use is overloaded in std_logic_unsigned which is deprecated but unfortunately made it through several text books (as well as std_logic_arith and std_logic_signed). Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Tue, 12 Nov 2013 11:02:50 -0600 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="27619"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+cDoipgDNr5okr0Pl7L/PPUce6OryyJQQ=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:c2A9yCdisQGKqV5c3AgG/8sj/BY= Xref: news.eternal-september.org comp.lang.vhdl:7177 In article , alessandro.basili@cern.ch says... > > It could be made slightly more general by not taking advantage of the > > fact that all the vectors are of the form (0 to N). Thanks again. > > IMO that generalization has to go in the data structure, not in the > functions which operate on them. If you have an 'array' of 'something', > each element has to be the same 'something', but if you have a register > instead, you can collect vectors of different sizes. Yes, this function will only operate on arrays that start at 0. Each location of the array has a std_ulogic_vector -- all are the same size. I realized later that the code I posted does not depend on those std_ulogic_vectors having the form (0 to N) because I used 'range to define the size of those vectors. So as long as the array indexes always start with 0, I think this function should handle any sizes of vectors. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal and variable assignment Date: Tue, 12 Nov 2013 21:17:48 -0500 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <20131111163719.002d2212@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 13 Nov 2013 02:18:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="1875"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Ir2Y68TbGKXVl4x8DhTZE" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:w+r06xCp4SSwMqNRM0coOZeV6mA= Xref: news.eternal-september.org comp.lang.vhdl:7178 On 11/12/2013 7:44 AM, alb wrote: > Hi Rick, > > On 12/11/2013 07:26, rickman wrote: > [] > S1 is an SLV and I don't know of >> a library that defines the '+' operator for a character and an SLV. > > there's no 'character' involved, the operator the OP intended to use is > overloaded in std_logic_unsigned which is deprecated but unfortunately > made it through several text books (as well as std_logic_arith and > std_logic_signed). I'm not going to argue with you about this, but the OP's code which you trimmed was adding a character to the SLV. The character may be interpreted as a single bit of data, but calling it a character is not invalid. The point is that this statement without a greater context is not valid VHDL. v1 := '1' + s1; -- Rick From newsfish@newsfish Tue Dec 29 16:43:14 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: I need an or_reduce for an array of std_logic_vectors Date: Wed, 13 Nov 2013 15:33:21 +0100 Lines: 53 Message-ID: References: <448f2df9-d209-432e-bfdb-71fcf5180276@googlegroups.com> <2131c181-b558-4de3-ad0a-06ac97e7ea44@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /oK+MR8thN09+95Ikvj97w5k9PEMhMInEAxBYn0EC2KbU3OYiw Cancel-Lock: sha1:3ZOgJT48bcMZ0Cur8X3WfNCY0yA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <2131c181-b558-4de3-ad0a-06ac97e7ea44@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7179 Hi KJ, On 07/11/2013 17:57, KJ wrote: [] > If you define the range of the output vector like this... > function or_reduce(L: arr_type) return std_logic_vector(0 to 2) > That would produce a compile error. Ok, I verified what happened in my case. I have two functions to convert between integers and slv: ------------------------------------------------------------------------------- function htoi (L : std_ulogic_vector) return integer is variable val : integer; begin val := to_integer(unsigned(L)); return val; end function; ------------------------------------------------------------------------------- function itoh (L : integer) return std_ulogic_vector is variable val : std_ulogic_vector(31 downto 0); begin val := std_logic_vector(to_unsigned(L, val'length)); return val; end function; In the 'itoh' function I considered that integers are 32 bits max and I constrained val accordingly. When I call the function I'm not sure if I need to constrain the dimensions of the returned value: signal my_slv0: std_logic_vector(7 downto 0); signal my_slv1: std_logic_vector(7 downto 0); my_slv0 <= itoh(123); my_slv1 <= itoh(123)(my_slv1'range); vcom compiles ok for both cases, while synplify_pro flags an error saying "Width mismatch, location has width 8, value 32" for my_slv0. What is the correct assignment? Thanks in advance, Al From newsfish@newsfish Tue Dec 29 16:43:14 2015 X-Received: by 10.66.144.41 with SMTP id sj9mr1838263pab.23.1384473327634; Thu, 14 Nov 2013 15:55:27 -0800 (PST) X-Received: by 10.49.75.168 with SMTP id d8mr148559qew.3.1384473327577; Thu, 14 Nov 2013 15:55:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no8688900pbz.1!news-out.google.com!9ni28650qaf.0!nntp.google.com!i2no1470708qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 14 Nov 2013 15:55:27 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <20131111163719.002d2212@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <691675c0-f533-47b4-a269-51a850266254@googlegroups.com> Subject: Re: VHDL signal and variable assignment From: Andy Injection-Date: Thu, 14 Nov 2013 23:55:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7180 On Monday, November 11, 2013 8:32:54 PM UTC-6, ramya.m...@gmail.com wrote: > Also, in Assignment 1, is s1 a register?=20 In synthesizable VHDL, any reference to a signal assigned in a clocked proc= ess is usually* a reference to the output of a register. This is commonly s= implified to "the signal is a register", which is usually accurate, but not= always*. However, with a variable in a clocked process, different references to (rea= ds of) the same variable in the same clock cycle could return different val= ues, depending on what/when it was most recently written. Therefore, the va= riable itself is neither register nor combinatorial, but each reference to = it would be either (the output of a) registered or combinatorial.=20 If the variable was (or could have been) written in the same clock cycle, b= ut prior to the reference, then the reference is combinatorial.=20 If the variable was not (and could not have been) written in the same clock= cycle prior to the reference, then the reference is registered.=20 In the case when a variable may or may not have been written in the same cl= ock cycle prior to the reference, the same condition that determines whethe= r the prior write ocurred also controls an implied multiplexer which select= s either the combinatorial value feeding the register, or the register outp= ut. Thus the output is combinatorial (the output of the multiplexer). *The above is for assignments and references to variables and signals insid= e the clocked if/elsif-statement. A reference to a variable AFTER the end o= f the clocked if/elsif-statement is always registered. More importantly, si= gnals assigned from an expression of variables after the end of the clocked= if/elsif statement are the combinatorial result of the expressed logic aft= er the variables' registers. This is the only way to generate a combinatori= al output signal directly from a clocked process. If this seems confusing, just remember that the synthesis tool will create = a circuit that mimics the clock-cycle behavior of the executed code. If it = takes an extra clock cycle for a value to propagate through the process, th= en the synthesis tool will use a register to create that extra clock cycle = delay.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: compact bus description Date: Fri, 15 Nov 2013 16:57:14 +0100 Lines: 30 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net H/34FWClfh7m711dUiXvQQhIxNyytZFa5Z7yvXciTx8AyCZaES Cancel-Lock: sha1:9Ykzq36hLk98gMYRw0aXDCLq3jk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7181 Hi everyone, I was wondering if there's any way to describe a bus 'type' and declare it to be a port, where the bus has signals going in and out of an entity. I certainly know that registers can group elements together but then when declared as ports they can be of in/out/inout mode only [1]. On a practical side, assuming I want to have a wishbone bus, can I group all the signals in a sort of "macro port" which can be mapped more easily? I certainly realize that an 'in' port on one side should be an 'out' one on another side. In my testbenches I usually 'abstract' the physical interface with some sort of type definition which then is mapped into the physical port through a set of functions but would that be advisable for synthesis? Any hint/suggestion/comment is appreciated, Al [1] I intentionally omitted 'buffer' and 'linkage', the first being essentially the same as 'out' in vhdl-2008 and the second being something I've never understood the reason for :-/ -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.58.23.166 with SMTP id n6mr3759168vef.13.1384550793833; Fri, 15 Nov 2013 13:26:33 -0800 (PST) X-Received: by 10.182.118.170 with SMTP id kn10mr104921obb.20.1384550793755; Fri, 15 Nov 2013 13:26:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!o2no2527552qas.0!news-out.google.com!9ni30638qaf.0!nntp.google.com!o2no2527542qas.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 15 Nov 2013 13:26:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> Subject: Re: compact bus description From: KJ Injection-Date: Fri, 15 Nov 2013 21:26:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7182 On Friday, November 15, 2013 10:57:14 AM UTC-5, alb wrote: > I was wondering if there's any way to describe a bus 'type' and declare > it to be a port, where the bus has signals going in and out of an entity. > Other than to declare all signals as 'inout', there is no way to group signals together and have individual elements have different modes. If you do declare everything as 'inout', then you need to add statements in the architecture to tri-state all of the signals that you would like to be 'in'. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.182.109.164 with SMTP id ht4mr5690262obb.16.1384636546803; Sat, 16 Nov 2013 13:15:46 -0800 (PST) X-Received: by 10.50.8.42 with SMTP id o10mr243625iga.3.1384636546755; Sat, 16 Nov 2013 13:15:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!n1no765207qai.0!news-out.google.com!9ni32491qaf.0!nntp.google.com!i2no3378376qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 16 Nov 2013 13:15:46 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.141.131; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.141.131 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> Subject: Re: compact bus description From: Mike Treseler Injection-Date: Sat, 16 Nov 2013 21:15:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7183 On Friday, November 15, 2013 7:57:14 AM UTC-8, alb wrote: > I was wondering if there's any way to describe a bus 'type' and declare > it to be a port, where the bus has signals going in and out of an entity. I agree with KJ, but I don't understand your requirement. > On a practical side, assuming I want to have a wishbone bus, can I group > all the signals in a sort of "macro port" which can be mapped more > easily? I certainly realize that an 'in' port on one side should be an > 'out' one on another side. Since the wishbone bus is wired through the fpga fabric, there can't be a a= n internal node, other than a pin driver, that requires bidirectional opera= tion. =20 > In my testbenches I usually 'abstract' the physical interface with some > sort of type definition which then is mapped into the physical port > through a set of functions but would that be advisable for synthesis? It's not required for synthesis. Only in the case of simulating multiple de= vices, could such an abstraction be useful. I always start with a fpga pin = level testbench. Anything complicated in the fabric can be covered with fun= ctions and assertions. Finding or making a "good enough" model for external= device can sometimes be a problem, but at the pin level I also have the op= tion of putting a scope on it. > Any hint/suggestion/comment is appreciated, OK.=20 1. Use complex functions and types as needed for synthesis because they are= easy to test statically even if they are unlikely to be reused. 2. Sim whatever you can at the fpga device entity pin level first. -- Mike Treseler =20 From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: compact bus description Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 17 Nov 2013 02:42:35 GMT Lines: 42 Message-ID: <52882d1a$0$2753$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4b38af14.news.astraweb.com X-Trace: DXC=LYH8gSmR^Fn:PIc[8_6SKeL?0kYOcDh@jZD3?OaX:Skm\>T:^Al174h Hi everyone, > > I was wondering if there's any way to describe a bus 'type' and declare > it to be a port, where the bus has signals going in and out of an > entity. > > I certainly know that registers can group elements together but then > when declared as ports they can be of in/out/inout mode only [1]. > > On a practical side, assuming I want to have a wishbone bus, can I group > all the signals in a sort of "macro port" which can be mapped more > easily? I certainly realize that an 'in' port on one side should be an > 'out' one on another side. Yes and no. You can't group all the signals together, as the port mode must be IN or OUT (or INOUT, but that's really not what you want). System Verilog got this right (allowing input and output in the one interface), but this is VHDL so the best you can do is have one record for the inputs and another for the outputs. That means your bus port mappings come down to: port map ( big_bus_in => whatever, big_bus_out => whatever ) You mentioned Wishbone. It's easy to make "from_syscon", "from_master" and "to_master" records, but be aware that in VHDL if you are using the same record definitions throughout a design (which is the only sensible way to do it, no?) you can't paramaterise the field widths on each use of the Wishone via generics. You can paramaterise them via constants in a package, however, but that applies across the whole design. BTW, I've been defining buses in VHDL this way since the turn of the century. Tool support is good as long as the records are only used for internal signals. Top level ports (e.g. those on pins of your chip) really should be restricted to std_(u)logic or std_(u)logic_vector. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Mon, 18 Nov 2013 09:51:30 +0100 Lines: 71 Message-ID: References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net a2NstALmnRMTZXkNn+yGjQ6Gtj+HyVgQa4tvGD4TUWvL3SgQww Cancel-Lock: sha1:WsdyJQVroG2y/kYRs8ucJMXJVyk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7185 Hi KJ, On 15/11/2013 22:26, KJ wrote: > On Friday, November 15, 2013 10:57:14 AM UTC-5, alb wrote: >> I was wondering if there's any way to describe a bus 'type' and >> declare it to be a port, where the bus has signals going in and out >> of an entity. >> > Other than to declare all signals as 'inout', there is no way to > group signals together and have individual elements have different > modes. has this feature ever been considered for an upgrade in the language? With the growing need to have an on-chip bus or network, wouldn't an easier way to 'connect' components help? I actually see current component mapping a bit cumbersome; you need to have ports and signals to wire them together. If those ports which belong to the same interface can be 'combined' to some extent the interconnect task could potentially be easier. Moreover what is the benefit of having a signal for the port map? Unless the signal is used in the architecture where components are wired together (which I tend to avoid), it seems that signal declaration is highly redundant: -- ... signal a; signal b; begin component_0: foo port map ( a => a, b => b, ); component_1: foo port map ( a => b, b => a, ); -- ... The need to pass through a signal also forces the port map to be present for both components, while in general if a port of component_a is assigned to a port of component_b, the opposite is implicitly valid. What if the following code was valid: component_0: foo port map ( a => component_1.b, b => component_1.a, ); Since there's never a free lunch, what is the downside of having such a feature? I certainly did not go through the full definition of what can be a 'combined' port and there are certainly pitfalls and technical obstacles which might prevent this. Believe me I do not want to start a flame, I might be a little provocative but my intent is to see whether the language can evolve further. Al From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer01.am1!peering.am1!npeersf03.am4!fx29.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: compact bus description References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131116-1, 16/11/2013), Outbound message X-Antivirus-Status: Clean Lines: 87 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1384768055 86.29.12.221 (Mon, 18 Nov 2013 09:47:35 UTC) NNTP-Posting-Date: Mon, 18 Nov 2013 09:47:35 UTC Organization: virginmedia.com Date: Mon, 18 Nov 2013 09:47:35 +0000 X-Received-Body-CRC: 1922390120 X-Received-Bytes: 3603 Xref: news.eternal-september.org comp.lang.vhdl:7186 On 18/11/2013 08:51, alb wrote: > Hi KJ, > > On 15/11/2013 22:26, KJ wrote: >> On Friday, November 15, 2013 10:57:14 AM UTC-5, alb wrote: >>> I was wondering if there's any way to describe a bus 'type' and >>> declare it to be a port, where the bus has signals going in and out >>> of an entity. >>> >> Other than to declare all signals as 'inout', there is no way to >> group signals together and have individual elements have different >> modes. > > has this feature ever been considered for an upgrade in the language? Yes, both mixed in/out ports in records and SV Interfaces are being considered for the next language revision, see: http://www.eda.org/twiki/bin/view.cgi/P1076/CollectedRequirements Anybody can join the group, Regards, Hans www.ht-lab.com > With the growing need to have an on-chip bus or network, wouldn't an > easier way to 'connect' components help? > > I actually see current component mapping a bit cumbersome; you need to > have ports and signals to wire them together. If those ports which > belong to the same interface can be 'combined' to some extent the > interconnect task could potentially be easier. > > Moreover what is the benefit of having a signal for the port map? Unless > the signal is used in the architecture where components are wired > together (which I tend to avoid), it seems that signal declaration is > highly redundant: > > > -- ... > signal a; > signal b; > > begin > > component_0: foo > port map ( > a => a, > b => b, > ); > > component_1: foo > port map ( > a => b, > b => a, > ); > -- ... > > > The need to pass through a signal also forces the port map to be present > for both components, while in general if a port of component_a is > assigned to a port of component_b, the opposite is implicitly valid. > > What if the following code was valid: > > > component_0: foo > port map ( > a => component_1.b, > b => component_1.a, > ); > > > Since there's never a free lunch, what is the downside of having such a > feature? I certainly did not go through the full definition of what can > be a 'combined' port and there are certainly pitfalls and technical > obstacles which might prevent this. > > Believe me I do not want to start a flame, I might be a little > provocative but my intent is to see whether the language can evolve further. > > Al > From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Mon, 18 Nov 2013 14:24:33 +0100 Lines: 72 Message-ID: References: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net RCk6z7OyPwaKkOGhE91uswZIGf4kJ6xJaoaMNL5DX8zPqNkmS8 Cancel-Lock: sha1:DCoiEAjIAdtrltTK//C3FfTptmg= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7187 Hi Mike, On 16/11/2013 22:15, Mike Treseler wrote: > On Friday, November 15, 2013 7:57:14 AM UTC-8, alb wrote: >> I was wondering if there's any way to describe a bus 'type' and >> declare it to be a port, where the bus has signals going in and out >> of an entity. > > I agree with KJ, but I don't understand your requirement. It is possible that I do not clearly know what I want and that I might have wrongly stated what I want, therefore I certainly understand your possible lack of understanding :-). I would like to declare 'something' that defines my connection (being it wishbone, or whatever else) with a single name identifier so that when I connect it to other components I do not need to care about port assignment the way I do now. > >> On a practical side, assuming I want to have a wishbone bus, can I >> group all the signals in a sort of "macro port" which can be mapped >> more easily? I certainly realize that an 'in' port on one side >> should be an 'out' one on another side. > > Since the wishbone bus is wired through the fpga fabric, there can't > be a an internal node, other than a pin driver, that requires > bidirectional operation. while I agree with you that internal nodes do not have bidirectional operations, the tristate logic model might facilitate the functional description (leaving the tool instantiate all the necessary muxes). It is not seldom that I define an internal data bus as tristated while several sources may want to drive it. >> In my testbenches I usually 'abstract' the physical interface with >> some sort of type definition which then is mapped into the physical >> port through a set of functions but would that be advisable for >> synthesis? > > It's not required for synthesis. Only in the case of simulating > multiple devices, could such an abstraction be useful. I always start > with a fpga pin level testbench. Anything complicated in the fabric > can be covered with functions and assertions. Finding or making a > "good enough" model for external device can sometimes be a problem, > but at the pin level I also have the option of putting a scope on > it. Assuming the logic 'contains' multiple 'devices' of the same type which need to be connected together, the possibility to alleviate the wiring effort might be useful. [] > 1. Use complex functions and types as needed for synthesis because > they are easy to test statically even if they are unlikely to be > reused. what do you mean by 'test statically'? > > 2. Sim whatever you can at the fpga device entity pin level first. This is my main mantra! I first concentrate on the pin level because I know that in the field, that's nearly the only thing I can access. This adds an extra effort (and logic) in order to make each state observable. Too often though I jumped in projects where these aspects weren't really put in at the design stage and when it comes to verification it becomes a mess. That is why I recently started to look into assertions to investigate the possibility to increase observability without changing the hardware. From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Mon, 18 Nov 2013 09:56:56 -0800 Organization: Highland Technology, Inc. Lines: 32 Message-ID: <20131118095656.14f52f91@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="19062"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182feoHxqvXwkFQ0O7GQoXU" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:HkWclkBkxolBKa+U/tXWcBnalOg= Xref: news.eternal-september.org comp.lang.vhdl:7188 On Fri, 15 Nov 2013 16:57:14 +0100 alb wrote: > Hi everyone, > > I was wondering if there's any way to describe a bus 'type' and declare > it to be a port, where the bus has signals going in and out of an entity. > > I certainly know that registers can group elements together but then > when declared as ports they can be of in/out/inout mode only [1]. > > On a practical side, assuming I want to have a wishbone bus, can I group > all the signals in a sort of "macro port" which can be mapped more > easily? I certainly realize that an 'in' port on one side should be an > 'out' one on another side. > > In my testbenches I usually 'abstract' the physical interface with some > sort of type definition which then is mapped into the physical port > through a set of functions but would that be advisable for synthesis? > > Any hint/suggestion/comment is appreciated, > I've done several projects using an internal WISHBONE bus. In each and every one of them, my code is peppered with t_wb_mosi and t_wb_miso, which mean whatever they happen to mean for that particular project. It's unfortunate and obnoxious, but not the end of the world. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Tue, 19 Nov 2013 10:43:53 +0200 Lines: 22 Message-ID: References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1384850633 16506 2001:708:310:3430:213:21ff:fe1b:b396 (19 Nov 2013 08:43:53 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Tue, 19 Nov 2013 08:43:53 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:hCtacmt0UhBvdjhELzRSROXkYeI= Xref: news.eternal-september.org comp.lang.vhdl:7189 KJ writes: > On Friday, November 15, 2013 10:57:14 AM UTC-5, alb wrote: >> I was wondering if there's any way to describe a bus 'type' and declare >> it to be a port, where the bus has signals going in and out of an entity. >> > Other than to declare all signals as 'inout', there is no way to group signals together and have individual elements have different modes. > > If you do declare everything as 'inout', then you need to add statements in the architecture to tri-state all of the signals that you would like to be 'in'. So basically the way to do this sort of thing is still having separate records for inputs and outputs. I googled and you wrote about this in 2006, saying that tools are usually smart enough to figure out which signals are actually inouts... So are you sure the tri-stating is actually needed? BTW, does anyone know what happened to the proposals for SystemVerilog like interfaces in VHDL? For example, here is one proposing direction for signals in records: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/proposals/ft17_composite_interface_mode.txt Was this just rejected? From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!eweka.nl!lightspeed.eweka.nl!69.16.177.246.MISMATCH!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx29.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: compact bus description References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131118-1, 18/11/2013), Outbound message X-Antivirus-Status: Clean Lines: 21 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1384851065 86.29.12.221 (Tue, 19 Nov 2013 08:51:05 UTC) NNTP-Posting-Date: Tue, 19 Nov 2013 08:51:05 UTC Organization: virginmedia.com Date: Tue, 19 Nov 2013 08:51:04 +0000 X-Received-Body-CRC: 3910947748 X-Received-Bytes: 1595 Xref: news.eternal-september.org comp.lang.vhdl:7190 On 19/11/2013 08:43, Anssi Saari wrote: .. > > BTW, does anyone know what happened to the proposals for SystemVerilog > like interfaces in VHDL? For example, here is one proposing direction > for signals in records: > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/proposals/ft17_composite_interface_mode.txt > > Was this just rejected? > Don't think so: http://www.eda.org/twiki/bin/view.cgi/P1076/BlockInterfaces It is a popular enhancement, Regards, Hans www,ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Tue, 19 Nov 2013 12:45:26 -0500 Organization: A noiseless patient Spider Lines: 96 Message-ID: References: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 19 Nov 2013 17:45:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="5404132b0bc0af353c3ab42cd24ec3d3"; logging-data="32485"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hN38vMW2sXRtlmd3RDtAE" User-Agent: Mozilla/5.0 (Windows NT 6.0; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 In-Reply-To: Cancel-Lock: sha1:GtTg9mqpVUwMO1r+eAvp4OHgSDs= Xref: news.eternal-september.org comp.lang.vhdl:7191 On 11/18/2013 8:24 AM, alb wrote: > Hi Mike, > > On 16/11/2013 22:15, Mike Treseler wrote: >> On Friday, November 15, 2013 7:57:14 AM UTC-8, alb wrote: >>> I was wondering if there's any way to describe a bus 'type' and >>> declare it to be a port, where the bus has signals going in and out >>> of an entity. >> >> I agree with KJ, but I don't understand your requirement. > > It is possible that I do not clearly know what I want and that I might > have wrongly stated what I want, therefore I certainly understand your > possible lack of understanding :-). > > I would like to declare 'something' that defines my connection (being it > wishbone, or whatever else) with a single name identifier so that when I > connect it to other components I do not need to care about port > assignment the way I do now. I understand what you are looking for. You wish to wrap up all the details of a bus interface in a port into one structure, one name. But as far as I know, there is no way to do this in VHDL. We have records for combining data declarations of different types. But we have nothing that can function more widely in a port map for combining IO types. >>> On a practical side, assuming I want to have a wishbone bus, can I >>> group all the signals in a sort of "macro port" which can be mapped >>> more easily? I certainly realize that an 'in' port on one side >>> should be an 'out' one on another side. >> >> Since the wishbone bus is wired through the fpga fabric, there can't >> be a an internal node, other than a pin driver, that requires >> bidirectional operation. > > while I agree with you that internal nodes do not have bidirectional > operations, the tristate logic model might facilitate the functional > description (leaving the tool instantiate all the necessary muxes). > > It is not seldom that I define an internal data bus as tristated while > several sources may want to drive it. Yes, the hands off approach to hardware design, almost like designing software. >>> In my testbenches I usually 'abstract' the physical interface with >>> some sort of type definition which then is mapped into the physical >>> port through a set of functions but would that be advisable for >>> synthesis? >> >> It's not required for synthesis. Only in the case of simulating >> multiple devices, could such an abstraction be useful. I always start >> with a fpga pin level testbench. Anything complicated in the fabric >> can be covered with functions and assertions. Finding or making a >> "good enough" model for external device can sometimes be a problem, >> but at the pin level I also have the option of putting a scope on >> it. > > Assuming the logic 'contains' multiple 'devices' of the same type which > need to be connected together, the possibility to alleviate the wiring > effort might be useful. > > [] >> 1. Use complex functions and types as needed for synthesis because >> they are easy to test statically even if they are unlikely to be >> reused. > > what do you mean by 'test statically'? > >> >> 2. Sim whatever you can at the fpga device entity pin level first. > > This is my main mantra! I first concentrate on the pin level because I > know that in the field, that's nearly the only thing I can access. This > adds an extra effort (and logic) in order to make each state observable. > > Too often though I jumped in projects where these aspects weren't really > put in at the design stage and when it comes to verification it becomes > a mess. That is why I recently started to look into assertions to > investigate the possibility to increase observability without changing > the hardware. Ignoring the power of a simulation only because you can't duplicate it in the field is a bit like... well, I can't even come up with an analogy. That makes no sense to me. I test at all levels as I design hardware. Then I test the total entity in ways that can be duplicated in the field, but more importantly come from the spec. All you can do is to test each requirement of your design. If you can't test that from the outside of the design looking in, does it matter as a requirement? That applies to both the simulation and the physical object. -- Rick From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.236.53.70 with SMTP id f46mr14198257yhc.17.1384889289604; Tue, 19 Nov 2013 11:28:09 -0800 (PST) X-Received: by 10.50.171.169 with SMTP id av9mr513130igc.11.1384889289479; Tue, 19 Nov 2013 11:28:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dz2no1490556qab.0!news-out.google.com!9ni36578qaf.0!nntp.google.com!dz2no1490542qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 Nov 2013 11:28:09 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.46.141.131; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u NNTP-Posting-Host: 50.46.141.131 References: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cdb6c42-4de0-4933-8208-8b584e3d1070@googlegroups.com> Subject: Re: compact bus description From: Mike Treseler Injection-Date: Tue, 19 Nov 2013 19:28:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7192 On Monday, November 18, 2013 5:24:33 AM UTC-8, alb wrote: > while I agree with you that internal nodes do not have bidirectional > operations, the tristate logic model might facilitate the functional > description (leaving the tool instantiate all the necessary muxes). True, but the necessary muxes and control logic could also be inferred dire= ctly in a single process entity. Value flow is my preferred abstraction. Sy= nthesis can sort out the muxes. > It is not seldom that I define an internal data bus as tristated while > several sources may want to drive it. That's another way to do it. Not quite as close to the metal though. > > 1. Use complex functions and types as needed for synthesis because > > they are easy to test statically even if they are unlikely to be > > reused. > what do you mean by 'test statically'? Hide assertion declarations (synthesis translate_off) after the process tem= plate to test the synthesis functions. That way I can get terminal output t= hat tests the actual synthesis functions and other declarations every time = vsim elaborates the synthesis code with debug_c true.=20 > > 2. Sim whatever you can at the fpga device entity pin level first. > This is my main mantra! I first concentrate on the pin level because I > know that in the field, that's nearly the only thing I can access. This > adds an extra effort (and logic) in order to make each state observable. > Too often though I jumped in projects where these aspects weren't really > put in at the design stage and when it comes to verification it becomes > a mess. That is why I recently started to look into assertions to > investigate the possibility to increase observability without changing > the hardware. I agree that synthesis code assertions of some sort are needed to debug com= plex control functions. Sometimes rewriting old code and rolling your own f= unctions is faster. Sometimes work is just hard. -- Mike Treseler From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.52.108.166 with SMTP id hl6mr240624vdb.0.1384956347955; Wed, 20 Nov 2013 06:05:47 -0800 (PST) X-Received: by 10.182.78.103 with SMTP id a7mr9937obx.4.1384956347918; Wed, 20 Nov 2013 06:05:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dz2no2208309qab.0!news-out.google.com!9ni38227qaf.0!nntp.google.com!dz2no2208306qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Nov 2013 06:05:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e7fe18a-f1ab-4efe-80de-84c5b5c6c01d@googlegroups.com> Subject: Re: compact bus description From: KJ Injection-Date: Wed, 20 Nov 2013 14:05:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7193 On Monday, November 18, 2013 3:51:30 AM UTC-5, alb wrote: > has this feature ever been considered for an upgrade in the language? > > With the growing need to have an on-chip bus or network, wouldn't an > > easier way to 'connect' components help? > Yes it has, see this link http://www.eda.org/twiki/bin/view.cgi/P1076/BlockInterfaces VHDL language standards are currently being proposed, here is the home page for that group. http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome > > > What if the following code was valid: > > > > > > component_0: foo > > port map ( > > a => component_1.b, > > b => component_1.a, > > ); > > > > > > Since there's never a free lunch, what is the downside of having such a > > feature? I certainly did not go through the full definition of what can > > be a 'combined' port and there are certainly pitfalls and technical > > obstacles which might prevent this. > > > > Believe me I do not want to start a flame, I might be a little > > provocative but my intent is to see whether the language can evolve further. > If you want to change the language, then you need to take your suggestion to the proper forum which is at the links I posted earlier. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.66.220.163 with SMTP id px3mr304260pac.38.1384956722450; Wed, 20 Nov 2013 06:12:02 -0800 (PST) X-Received: by 10.182.118.138 with SMTP id km10mr9062obb.27.1384956722383; Wed, 20 Nov 2013 06:12:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z6no10585623pbz.1!news-out.google.com!9ni37803qaf.0!nntp.google.com!i2no6857190qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Nov 2013 06:12:02 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <24af7c8f-e5e4-4593-8ff9-d396c4bb8b45@googlegroups.com> Subject: Re: compact bus description From: KJ Injection-Date: Wed, 20 Nov 2013 14:12:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7194 On Tuesday, November 19, 2013 3:43:53 AM UTC-5, Anssi Saari wrote: >=20 > > If you do declare everything as 'inout', then you need to add statement= s in the architecture to tri-state all of the signals that you would like t= o be 'in'. >=20 >=20 >=20 > So basically the way to do this sort of thing is still having separate >=20 > records for inputs and outputs. I googled and you wrote about this in >=20 > 2006, saying that tools are usually smart enough to figure out which >=20 > signals are actually inouts... So are you sure the tri-stating is >=20 > actually needed? >=20 >=20 I don't recall ever writing that 'tools are usually smart enough to figure = out which signals are actually inouts' even if it was seven years ago. You have to tri-state the 'inputs' since they are declared as 'inout' which= means that they drive the signal. If you have no driver specified because= you are using it as an input, the implicit driver is 'U'. No other signal= that is supposed to be able to drive that signal will be able to override = the 'U'. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Wed, 20 Nov 2013 15:54:36 +0100 Lines: 39 Message-ID: References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> <4e7fe18a-f1ab-4efe-80de-84c5b5c6c01d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net BR8d3/6j46Ywiba5XdET+AnqjvtRdT8vgJ/EBRnjl0KCDj3FQ2 Cancel-Lock: sha1:htxArLl1tLGS7tHbJdqEt14dWp0= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <4e7fe18a-f1ab-4efe-80de-84c5b5c6c01d@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7195 Hi KJ, On 20/11/2013 15:05, KJ wrote: > On Monday, November 18, 2013 3:51:30 AM UTC-5, alb wrote: >> has this feature ever been considered for an upgrade in the >> language? [] > Yes it has, see this link > http://www.eda.org/twiki/bin/view.cgi/P1076/BlockInterfaces > > VHDL language standards are currently being proposed, here is the > home page for that group. > http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome thanks again for the pointers. I'm actually trying to go through the page in order to understand what was the evolution. My experience in language definition is scant at best, but I guess that I'll definitely learn something from this process. [] >> Believe me I do not want to start a flame, I might be a little >> >> provocative but my intent is to see whether the language can evolve >> further. >> > > If you want to change the language, then you need to take your > suggestion to the proper forum which is at the links I posted > earlier. I believe that my experience and knowledge is still too shallow to be of any use at that level, but I'll certainly stick around and through some thoughts if found appropriate. The fact that a feature like this has been taken into consideration already alleviates part of my discomfort that led me to post here in the first place. Al From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.182.118.194 with SMTP id ko2mr725515obb.32.1384974224524; Wed, 20 Nov 2013 11:03:44 -0800 (PST) X-Received: by 10.182.199.39 with SMTP id jh7mr37035obc.25.1384974224361; Wed, 20 Nov 2013 11:03:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dz2no2442843qab.0!news-out.google.com!9ni37803qaf.0!nntp.google.com!i2no7088897qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Nov 2013 11:03:44 -0800 (PST) In-Reply-To: <24af7c8f-e5e4-4593-8ff9-d396c4bb8b45@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> <24af7c8f-e5e4-4593-8ff9-d396c4bb8b45@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c4760d3-892b-445e-9de2-8bc0afcd8321@googlegroups.com> Subject: Re: compact bus description From: Andy Injection-Date: Wed, 20 Nov 2013 19:03:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2682 X-Received-Body-CRC: 2716772417 Xref: news.eternal-september.org comp.lang.vhdl:7196 On Wednesday, November 20, 2013 8:12:02 AM UTC-6, KJ wrote: > You have to tri-state the 'inputs' since they are declared as 'inout' whi= ch > means that they drive the signal. If you have no driver specified because > you are using it as an input, the implicit driver is 'U'. No other signal > that is supposed to be able to drive that signal will be able to override > the 'U'. If I'm not mistaken, if you explicitly define an initial value of 'Z' for e= ach element of a signal at the signal's declaration, then all drivers assoc= iated with that signal take the same initial value as their default value (= instead of the implicit 'U' for a signal with no explicit initialization in= the declaration).=20 For an element of an inout port associated with such an initialized signal,= which is really treated as an input-only element (and therefore never assi= gned), the element driver will retain the default value (e.g. 'Z') indefini= tely. Meanwhile, other drivers (e.g. in other components) can explicitly ov= erride the 'Z' value, allowing them to treat the element as an "output", pa= ssing such values to the associated "inputs". Jim Lewis' (of Synthworks) Advanced Testbench course demonstrates this tech= nique, but I have not tried it in synthesis yet. Andy From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.43.74.133 with SMTP id yw5mr776014icb.15.1384983233421; Wed, 20 Nov 2013 13:33:53 -0800 (PST) X-Received: by 10.49.99.37 with SMTP id en5mr110605qeb.8.1384983233385; Wed, 20 Nov 2013 13:33:53 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i2no8719qav.0!news-out.google.com!9ni0qaf.0!nntp.google.com!i2no8715qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Nov 2013 13:33:53 -0800 (PST) In-Reply-To: <7c4760d3-892b-445e-9de2-8bc0afcd8321@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> <24af7c8f-e5e4-4593-8ff9-d396c4bb8b45@googlegroups.com> <7c4760d3-892b-445e-9de2-8bc0afcd8321@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: compact bus description From: KJ Injection-Date: Wed, 20 Nov 2013 21:33:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2796 X-Received-Body-CRC: 4055231089 Xref: news.eternal-september.org comp.lang.vhdl:7197 On Wednesday, November 20, 2013 2:03:44 PM UTC-5, Andy wrote: > On Wednesday, November 20, 2013 8:12:02 AM UTC-6, KJ wrote: > > You have to tri-state the 'inputs' since they are declared as 'inout' which > > means that they drive the signal. If you have no driver specified because > > you are using it as an input, the implicit driver is 'U'. No other signal > > that is supposed to be able to drive that signal will be able to override > > the 'U'. > If I'm not mistaken, if you explicitly define an initial value of 'Z' for > each element of a signal at the signal's declaration, then all drivers associated > with that signal take the same initial value as their default value (instead of > the implicit 'U' for a signal with no explicit initialization in the declaration). I think you're mistaken (but admit I haven't tried). When you have an entity with an out or inout port, there will be an implicit driver created for the output of that entity with a value of 'U' for std_(u)logic type. Tying a signal that has an initial value of 'Z' will do nothing, the 'U' will still be there and win out. However, if the entity has a default of 'Z' applied in the port definition it will work. Adding an explicit assignment statement within the architecture or a default value on the entity will accomplish the goal of overriding the 'U'. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.68.177.226 with SMTP id ct2mr1207136pbc.2.1384994564929; Wed, 20 Nov 2013 16:42:44 -0800 (PST) X-Received: by 10.49.74.199 with SMTP id w7mr136261qev.3.1384994564875; Wed, 20 Nov 2013 16:42:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!z6no10739091pbz.1!news-out.google.com!9ni144qaf.0!nntp.google.com!i2no138353qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Nov 2013 16:42:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <43618582-59ff-4e30-a5e4-c21fe3a1fa9d@googlegroups.com> <24af7c8f-e5e4-4593-8ff9-d396c4bb8b45@googlegroups.com> <7c4760d3-892b-445e-9de2-8bc0afcd8321@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: compact bus description From: Andy Injection-Date: Thu, 21 Nov 2013 00:42:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7198 On Wednesday, November 20, 2013 3:33:53 PM UTC-6, KJ wrote: > Tying a signal that has an initial value of 'Z' will do nothing, the 'U' will still be there and win out. That's what I thought too, until I took Jim's Advanced TB class... I HIGHLY recommend it! All drivers associated (e.g. during elaboration) with the signal will get the same initialization/default as the signal. I was quite surprised myself. That part of the class focused on transactions modeled as resolved records passed between procedures (inout ports on each) rather than entities, but entities and procedures should behave the same WRT this aspect. I repeat, I have not tried this in synthesis. Andy From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: compact bus description Date: Fri, 22 Nov 2013 10:42:31 +0100 Lines: 58 Message-ID: References: <614b6695-32bf-4eac-8d68-d584dd771a74@googlegroups.com> <0cdb6c42-4de0-4933-8208-8b584e3d1070@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net NTlwuHlZ5wUkvvrUHgIbygNqXq52XNagdIhfjHyuGkQwNGfU0w Cancel-Lock: sha1:fRL5Y5yYLItk0JWfVQY1EJC4LNM= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 In-Reply-To: <0cdb6c42-4de0-4933-8208-8b584e3d1070@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7199 Hi Mike, On 19/11/2013 20:28, Mike Treseler wrote: > On Monday, November 18, 2013 5:24:33 AM UTC-8, alb wrote: > >> while I agree with you that internal nodes do not have >> bidirectional operations, the tristate logic model might facilitate >> the functional description (leaving the tool instantiate all the >> necessary muxes). > > True, but the necessary muxes and control logic could also be > inferred directly in a single process entity. Value flow is my > preferred abstraction. Synthesis can sort out the muxes. I am also a big fan of 'single process entity' but I still connect several entities through an on-system-bus which often is described with tristate logic. In this way my system can scale up (and down) much more easily, or at least I think it does. >> It is not seldom that I define an internal data bus as tristated >> while several sources may want to drive it. > > That's another way to do it. Not quite as close to the metal though. Correct, I find that being close to the metal is something that I can live without if I gain in maintainability and readability of the code. This, of course, may not always apply. >>> 1. Use complex functions and types as needed for synthesis >>> because they are easy to test statically even if they are >>> unlikely to be reused. > >> what do you mean by 'test statically'? > > Hide assertion declarations (synthesis translate_off) after the > process template to test the synthesis functions. That way I can get > terminal output that tests the actual synthesis functions and other > declarations every time vsim elaborates the synthesis code with > debug_c true. Uhm, since I'm pretty fresh new to assertion as of today, would it be possible for you to post a small example? [] > I agree that synthesis code assertions of some sort are needed to > debug complex control functions. Sometimes rewriting old code and > rolling your own functions is faster. Sometimes work is just hard. What is difficult to estimate is the short and long term benefits of debugging vs. rewriting. I often leave this decision to my inner senses to decide and when their voices say 'enough is enough' I scrap everything away and start from ground zero! I certainly believe there's a more 'formal' way for this decision problem :-) Al From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.182.236.74 with SMTP id us10mr7511020obc.36.1385291234519; Sun, 24 Nov 2013 03:07:14 -0800 (PST) X-Received: by 10.50.83.6 with SMTP id m6mr337756igy.1.1385291234325; Sun, 24 Nov 2013 03:07:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!transit4.readnews.com!209.85.216.88.MISMATCH!i2no4048778qav.0!news-out.google.com!p7ni12qat.0!nntp.google.com!i2no4048773qav.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 Nov 2013 03:07:13 -0800 (PST) In-Reply-To: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=202.164.55.103; posting-account=MqDrMgoAAAAF6JCqgzcsSILmO6ikUxYn NNTP-Posting-Host: 202.164.55.103 References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33a8f535-a1a0-42ad-b41f-a0a3687d3ce6@googlegroups.com> Subject: Re: Carry Save Adder (CSA) Verilog code From: joshimohit83@gmail.com Injection-Date: Sun, 24 Nov 2013 11:07:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7200 On Monday, November 13, 2006 5:30:53 PM UTC+5:30, humble...@hotmail.com wrote: > Hi, > > I need the Verilog code for a carry save adder (CSA). Can some one > please supply this. It takes three inputs and produces 2 outputs - the > sum and the carry. > > Thaks Much. Verilog code for Carry Save Adder: module carrysave(p0,p1,p2,p3,p4,p5,s,c,a,b); output [5:0]p0,p1,p2,p3,p4,p5; output [10:0]s; output [7:0]c; input [5:0]a,b; wire d,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,e1,e2,e3,e4,e5,e6,e7,e8,e9,e10,e11,e13,e14,e15,e16,e17; assign p0=b[0]?a:0; assign p1=b[1]?a:0; assign p2=b[2]?a:0; assign p3=b[3]?a:0; assign p4=b[4]?a:0; assign p5=b[5]?a:0; assign s[0]=p0[0]; HA h1(s[1],d,p0[1],p1[0]); HA h2(e5,d5,p1[5],p2[4]); FA m1(e1,d1,p0[2],p1[1],p2[0]); FA m2(e2,d2,p0[3],p1[2],p2[1]); FA m3(e3,d3,p0[4],p1[3],p2[2]); FA m4(e4,d4,p0[5],p1[4],p2[3]); HA h3(e6,d6,p3[1],p4[0]); HA h4(e11,d11,p4[5],p5[4]); FA m5(e7,d7,p3[2],p4[1],p5[0]); FA m6(e8,d8,p3[3],p4[2],p5[1]); FA m7(e9,d9,p3[4],p4[3],p5[2]); FA m8(e10,d10,p3[5],p4[4],p5[3]); HA h5(s[2],d12,d,e1); FA m9(e13,d13,d1,e2,p3[0]); FA m10(e14,d14,d2,e3,e6); FA m11(e15,d15,d3,e4,e7); FA m12(e16,d16,d4,e5,e8); FA m13(e17,d17,d5,e6,p2[5]); HA h6(s[3],c[0],d12,e13); HA h7(s[4],c[1],d13,e14); HA h8(s[9],c[6],d10,e11); HA h9(s[10],c[7],d11,p5[5]); FA m14(s[5],c[2],d6,d14,e15); FA m15(s[6],c[3],d7,d15,e16); FA m16(s[7],c[4],d8,d16,e17); FA m17(s[8],c[5],d9,d17,e10); endmodule From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Re: Carry Save Adder (CSA) Verilog code Date: Mon, 25 Nov 2013 09:09:04 +0100 Lines: 31 Message-ID: References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> <33a8f535-a1a0-42ad-b41f-a0a3687d3ce6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net HyuiCGTeA78J2e0LTxHLPg9jCZgRdeIGp25sUvAIIRLoCj2QOQ Cancel-Lock: sha1:l8/ALai8HEEGkI8Jq+nSI20oE6M= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.1 In-Reply-To: <33a8f535-a1a0-42ad-b41f-a0a3687d3ce6@googlegroups.com> X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7201 Hi joshimohit83, On 11/24/2013 12:07 PM, joshimohit83@gmail.com wrote: > On Monday, November 13, 2006 5:30:53 PM UTC+5:30, humble...@hotmail.com wrote: >> Hi, >> >> I need the Verilog code for a carry save adder (CSA). Can some one >> please supply this. It takes three inputs and produces 2 outputs - the >> sum and the carry. >> >> Thaks Much. > > > Verilog code for Carry Save Adder: [] I have few comments on your post: 1. what makes you think a reply to a message wrote 7 years ago might be helpful? I really hope the OP figured out to implement a CSA to get his homework done by now. 2. why posting a verilog code on a vhdl group? Even though people here are certainly proficient in both languages I would rather post messages like this on c.l.verilog. 3. let me add that a code like this, no matter which language you use, is highly unreadable and with a high potential to have multiple nasty bugs (how easy is to mistype a variable with another?). Al From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.182.247.71 with SMTP id yc7mr17278898obc.7.1385756420439; Fri, 29 Nov 2013 12:20:20 -0800 (PST) X-Received: by 10.49.104.69 with SMTP id gc5mr1509qeb.23.1385756420373; Fri, 29 Nov 2013 12:20:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!bm17no1499833qab.0!news-out.google.com!p7ni3494qat.0!nntp.google.com!bm17no1499822qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 29 Nov 2013 12:20:20 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.12.76.185; posting-account=GYIsLgoAAAA5P3M4LMWWP6Bhe2stK2eE NNTP-Posting-Host: 94.12.76.185 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: inequality with std_logic_vector in what package is defined From: thierrybingo@googlemail.com Injection-Date: Fri, 29 Nov 2013 20:20:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7202 Hi, I wonder in what packages the inequality like <, <=3D involving std_logic_= vector operators are defined. I wrote the code below, compiled it with mode= lsim and it worked fine. However std_logic_1164 package does not have the d= efintion of < with std_logic_vector..so how the result is computed? Cheers library ieee; use ieee.std_logic_1164.all; entity comp is port (a,b: in std_logic_vector(3 downto 0);=20 ctr:out std_logic); end entity; =20 architecture behaviour of comp is begin ctr<=3D'1' when (a Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: inequality with std_logic_vector in what package is defined References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wmrxrAhjuUPzQDboTjexVxbAx+LItTF5zmayfQDbOfuHaw7QWFDnT2BpE5oks2Pyc9CFw1SB3/Ppxm2!uMrE9IR5NpPfdDNJDUAotFFX1A4T/nVG/FzAdnBF8nB/z7NzZoRSGhnmhstaVJVVDExHgV0x6af/!XHdW//dxno0G0cyq08QJHGkhiA== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2461 Xref: news.eternal-september.org comp.lang.vhdl:7203 On 29/11/13 20:20, thierrybingo@googlemail.com wrote: > Hi, > I wonder in what packages the inequality like <, <= involving std_logic_vector operators are defined. I wrote the code below, compiled it with modelsim and it worked fine. However std_logic_1164 package does not have the defintion of < with std_logic_vector..so how the result is computed? > Cheers > > > > library ieee; > use ieee.std_logic_1164.all; > > entity comp is > port (a,b: in std_logic_vector(3 downto 0); > ctr:out std_logic); > end entity; > > architecture behaviour of comp is > begin > ctr<='1' when (a '0'; > end; > It's part of the language - any enumerated type has implicit operators (<, > etc) based on the position of the literals in the type. In std_logic, '1' is to the left of '0', so '1' is considered greater than '0'. So if a) the vectors are the same length and b) you are thinking of them as "unsigned" c) you don't try and compare e.g. 'H' and '0' it works. However if you are thinking of your vectors as representing signed numbers, or they are of different lengths, or they contain values that are not '0' or '1', strange (but well-defined) things will happen, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.52.252.106 with SMTP id zr10mr879871vdc.8.1385834179086; Sat, 30 Nov 2013 09:56:19 -0800 (PST) X-Received: by 10.50.111.200 with SMTP id ik8mr191674igb.7.1385834179043; Sat, 30 Nov 2013 09:56:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bm17no2803949qab.0!news-out.google.com!9ni8114qaf.0!nntp.google.com!p15no4336596qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 30 Nov 2013 09:56:18 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62a92b9b-7b59-4555-9c4f-2b396c42de96@googlegroups.com> Subject: Re: inequality with std_logic_vector in what package is defined From: Jim Lewis Injection-Date: Sat, 30 Nov 2013 17:56:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2405 X-Received-Body-CRC: 1031110096 Xref: news.eternal-september.org comp.lang.vhdl:7204 Anytime you are doing math on vectors, you should use a math type (such as = unsigned, signed, ufixed, sfixed, float, integer). For unsigned and signed= I recommend using the IEEE standard package "ieee.numeric_std.all" (rather= than the shareware package "ieee.std_logic_arith.all"). =20 If this is the only math usage of a and b, you can do: ctr<=3D'1' when (unsigned(a) < unsigned(b)) else '0';=20 If you tool supports VHDL-2008, you can get an unsigned interpretation of s= td_logic_vector by using "ieee.numeric_std_unsigned.all". However, over th= e life of a project, using a math type is a better from a documentation sta= nd point. =20 If your synthesis tool does not support VHDL-2008, you can use the sharewar= e package, "ieee.std_logic_unsigned.all" to accomplish the same thing. =20 If you use a relational and the vectors are not the same length or they con= tain an H or L, then the results will not match the desired numeric results= . IE: "100" > "01001" will return true. So I recommend using package "nu= meric_std_unsigned" to protect against this. =20 Jim From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: constrained random verification of a fifo - with OSVVM Date: Fri, 06 Dec 2013 10:43:08 +0100 Lines: 66 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net lF5dAcqr4BIu5nrk/Vrf6gg9bxfxWKAHlL3IGoAfzkcgwh1iQp Cancel-Lock: sha1:AWL02Yk6cjvi9K701CaRXcmWZR4= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.1.1 X-Enigmail-Version: 1.6 Xref: news.eternal-september.org comp.lang.vhdl:7205 Hi everyone, I have an 'event fifo' which is a fifo storing packages of data upon a 'trigger' condition on one side, while a serial interface is pulling events out on the other. Through the serial interface I may not only pull out events but also monitor a status register with some status bits of the fifo itself (full, empty, almost-full, almost-empty). My goal is to verify that the fifo runs correctly in all conditions and the appropriate level of handshake in the system is capable to handle a fifo-full condition. My 'simulation framework' has an harness and several testcases (for different purposes), together with other entities that appropriately stimulate each interface to the logic. One such an entity is the 'trigger', which initiate the various 'trigger conditions' upon a transaction from my testcase: while number_of_loops > 0 loop -- use number_of_loops as a seed for random trigger pattern generate_trigger_pattern(number_of_loops); -- initiate transaction to set the trigger pattern set_trigger_pattern(data, to_srv, fr_srv); -- verify data packet polling through serial port -- ... number_of_loops := number_of_loops - 1; end loop; Now as you can see above (hopefully my snapshot is not too cryptic), I have a very 'sequential' approach, where each trigger condition is followed by a poll of an event, so I can never run with more than one event in my fifo. My plan therefore is to change the transaction for the trigger module in a way that it will start initiating trigger conditions by itself concurrently and at a randomly distributed pace. But now it comes the problem of 'coverage'. How may I define my bins and my coverage model? I believe that my randomization variables should somehow affect the speed at which the trigger module generates trigger patterns on one side, and the speed of polling events on the other, so some sort of cross-coverage I guess? In the subject I specified OSVVM because that is what I'd like to use in the first place. I'm not willing at this time to dig into SV UVM since I have not enough time to learn another language and also because I strongly support the rise of OSVVM ;-). Any suggestion/remark/pointer would be greatly appreciated and yes I wish one day I can take the testbench course from SynthWorks but my current schedule is still very packed. Hopefully one day... Thank you all, Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.236.123.136 with SMTP id v8mr682366yhh.56.1386340343167; Fri, 06 Dec 2013 06:32:23 -0800 (PST) X-Received: by 10.50.20.7 with SMTP id j7mr49695ige.8.1386340342983; Fri, 06 Dec 2013 06:32:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.88.MISMATCH!p15no7933950qaj.0!news-out.google.com!p7ni11074qat.0!nntp.google.com!p15no7933942qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Dec 2013 06:32:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.77.115; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.77.115 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: constrained random verification of a fifo - with OSVVM From: Jim Lewis Injection-Date: Fri, 06 Dec 2013 14:32:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7206 Hi Al, In this case, ad-hoc functional coverage will work well. What you want to = detect is a write attempt while the FIFO is full and a read attempt while t= he FIFO is empty. You can capture each of these at the active edge of cloc= k with a single assignment. Next you need to count each of the attempts. = I count each of these as they rise (again with a single conditional assignm= ent). =20 That should take care of your coverage modeling. As for the random traffic= , I do random bursts with random idle times separating them on both the TX = and RX side. Make sure that the testbench TX and RX can run independently = from each other - ie: are in separate processes. Jim From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.66.17.234 with SMTP id r10mr1918678pad.40.1387142216524; Sun, 15 Dec 2013 13:16:56 -0800 (PST) X-Received: by 10.49.88.5 with SMTP id bc5mr327864qeb.4.1387142216425; Sun, 15 Dec 2013 13:16:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!i10no7939735pba.1!news-out.google.com!p7ni18966qat.0!nntp.google.com!p15no28274431qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Dec 2013 13:16:56 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.234.34.15; posting-account=0KhDFAoAAAA5moxsxQcEMGJ2ZrpBSwVJ NNTP-Posting-Host: 5.234.34.15 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples From: hsoleimani88@gmail.com Injection-Date: Sun, 15 Dec 2013 21:16:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7207 I am also looking for this code, please help me :((((( Many thanks, Hamid. hsoleimani88@gmail.com From newsfish@newsfish Tue Dec 29 16:43:15 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 16 Dec 2013 03:44:22 -0600 Date: Mon, 16 Dec 2013 09:44:22 +0000 From: MK User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-12kIct4yyl1eN7l38t+aNWNKS149US5UY78OG2+s0AuOEeJlB7SFkaVdyLFSuI9OBNp1hlbphnd135M!aEoOxNMxytFvRL/Z8yqLzeZwK/hXmZPAVsShi0AXISRKup8pPQf58cuVeOz0/MxsKAdbcV+0XxM= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1825 Xref: news.eternal-september.org comp.lang.vhdl:7208 On 15/12/2013 21:16, hsoleimani88@gmail.com wrote: > I am also looking for this code, please help me :((((( > > Many thanks, > Hamid. > > hsoleimani88@gmail.com > Last time I did this sort of stuff (about 20 years ago) we used HCMOS logic and some of the very early Xilinx 64 and 100 logic cell FPGAs. It wasn't that hard. What's your actual problem here ? If you are looking for plug in IP I think you will need to pay for it - if you are stuck with something then you need to explain what you are trying to do. Michael Kellett From newsfish@newsfish Tue Dec 29 16:43:15 2015 X-Received: by 10.43.128.197 with SMTP id hf5mr279469icc.2.1387447598831; Thu, 19 Dec 2013 02:06:38 -0800 (PST) X-Received: by 10.50.79.133 with SMTP id j5mr46479igx.2.1387447598548; Thu, 19 Dec 2013 02:06:38 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!p15no33977648qaj.0!news-out.google.com!p7ni21133qat.0!nntp.google.com!ie8no23367513qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Dec 2013 02:06:38 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=106.216.33.66; posting-account=uPGfxAoAAADuJ_fvwEdaKKiwWzFdylQI NNTP-Posting-Host: 106.216.33.66 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0302d394-cf17-46da-b474-71bfb2ca3cbc@googlegroups.com> Subject: New Cloud Based VHDL Simulator-Tarang From: neer4j.iit.delhi@gmail.com Injection-Date: Thu, 19 Dec 2013 10:06:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7209 Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not possible in Desktop/Offline Tools. No Bulky Installations Fastest Simulation Work as Teams Work from anywhere Platform Independent You can try it on http://www.tarangeda.com From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.111.MISMATCH!peer01.iad.highwinds-media.com!feed-me.highwinds-media.com!peer02.fr7!news.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx06.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: New Cloud Based VHDL Simulator-Tarang References: <0302d394-cf17-46da-b474-71bfb2ca3cbc@googlegroups.com> In-Reply-To: <0302d394-cf17-46da-b474-71bfb2ca3cbc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131218-2, 18/12/2013), Outbound message X-Antivirus-Status: Clean Lines: 25 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1387448568 86.29.12.221 (Thu, 19 Dec 2013 10:22:48 UTC) NNTP-Posting-Date: Thu, 19 Dec 2013 10:22:48 UTC Organization: virginmedia.com Date: Thu, 19 Dec 2013 10:22:45 +0000 X-Received-Body-CRC: 13892662 X-Received-Bytes: 1866 Xref: news.eternal-september.org comp.lang.vhdl:7210 On 19/12/2013 10:06, neer4j.iit.delhi@gmail.com wrote: > Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not possible in Desktop/Offline Tools. Which features are not possible with a desktop simulator? > > No Bulky Installations > Fastest Simulation > Work as Teams > Work from anywhere > Platform Independent > > You can try it on http://www.tarangeda.com > Given that you use GHDL as your backend simulator there is a long way for you to go to reach the stage of say a free Modelsim OEM version. Still I applaud your effort and hope you will succeed. I also hope you will pass on some of your development work back to the GHDL project. Good luck, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx19.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: New Cloud Based VHDL Simulator-Tarang References: <0302d394-cf17-46da-b474-71bfb2ca3cbc@googlegroups.com> In-Reply-To: <0302d394-cf17-46da-b474-71bfb2ca3cbc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 131218-2, 18/12/2013), Outbound message X-Antivirus-Status: Clean Lines: 25 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1387448432 86.29.12.221 (Thu, 19 Dec 2013 10:20:32 UTC) NNTP-Posting-Date: Thu, 19 Dec 2013 10:20:32 UTC Organization: virginmedia.com Date: Thu, 19 Dec 2013 10:20:29 +0000 X-Received-Body-CRC: 13892662 X-Received-Bytes: 1827 Xref: news.eternal-september.org comp.lang.vhdl:7211 On 19/12/2013 10:06, neer4j.iit.delhi@gmail.com wrote: > Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not possible in Desktop/Offline Tools. Which features are not possible with a desktop simulator? > > No Bulky Installations > Fastest Simulation > Work as Teams > Work from anywhere > Platform Independent > > You can try it on http://www.tarangeda.com > Given that you use GHDL as your backend simulator there is a long way for you to go to reach the stage of say a free Modelsim OEM version. Still I applaud your effort and hope you will succeed. I also hope you will pass on some of your development work back to the GHDL project. Good luck, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.42.131.129 with SMTP id z1mr1339434ics.25.1387479179453; Thu, 19 Dec 2013 10:52:59 -0800 (PST) X-Received: by 10.50.87.71 with SMTP id v7mr106125igz.11.1387479179400; Thu, 19 Dec 2013 10:52:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.swapon.de!newsfeed.fsmpi.rwth-aachen.de!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!209.85.216.87.MISMATCH!ie8no24034674qab.0!news-out.google.com!l9ni3433qay.0!nntp.google.com!ie8no24034673qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Dec 2013 10:52:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.52.96.19; posting-account=uU9hKAoAAAA-mPs62dknNaEy_zQSxSuv NNTP-Posting-Host: 72.52.96.19 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How to load multiple test vector files, where the filename come from generic parameters? From: py Injection-Date: Thu, 19 Dec 2013 18:52:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7212 Hi, For my test bench design, I coded an input procedure that loops continuously. In each iteration, it opens a vector file and load the content as test stimulus. What I'm trying to do is pipe in the filenames as generic parameters. At the moment, I can only do something ugly like this: for ii in 0 to G_NUM_TEST_CYCLE-1 loop if ii=0 then readline_nospace(f_data_ref, rline); elsif ii = 1 then readline_nospace(f_data_ref_1, rline); elsif ii = 2 then readline_nospace(f_data_ref_2, rline); ... Is there a way to create an array string (if so what's the syntax? I am using vhdl2008) to specify a set of index-able filenames? Thanks From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp6-1.free.fr!not-for-mail Date: Thu, 19 Dec 2013 22:53:48 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: How to load multiple test vector files, where the filename come from generic parameters? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 26 Message-ID: <52b36ae8$0$2266$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 19 Dec 2013 22:53:44 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1387490024 news-3.free.fr 2266 88.185.146.198:1354 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7213 Le 19/12/2013 19:52, py a écrit : > Hi, > > For my test bench design, I coded an input procedure that loops continuously. In each iteration, it opens a vector file and load the content as test stimulus. > What I'm trying to do is pipe in the filenames as generic parameters. [...] > Is there a way to create an array string (if so what's the syntax? I am using vhdl2008) to specify a set of index-able filenames? Hello You can define an array of strings but they will have to have the same length (all elements of an array mut be of the exact same type) A more flexible way would be to read the file names from a single file: variable filename : line; file filenames_file, tb_file : text; while not endfile(filenames_file) loop readline(filenames_file, filename); -- Read the file name file_open(tb_file, filename.all, read_mode); -- Open the file while not endfile(tb_file) loop end loop; file_close(tb_file); end loop; Nicolas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.149.67 with SMTP id ty3mr1962813pab.27.1387497581287; Thu, 19 Dec 2013 15:59:41 -0800 (PST) X-Received: by 10.50.8.42 with SMTP id o10mr136182iga.3.1387497581034; Thu, 19 Dec 2013 15:59:41 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!y3no10354322pbx.0!news-out.google.com!l9ni3433qay.0!nntp.google.com!ie8no24426757qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Dec 2013 15:59:40 -0800 (PST) In-Reply-To: <52b36ae8$0$2266$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.52.96.19; posting-account=uU9hKAoAAAA-mPs62dknNaEy_zQSxSuv NNTP-Posting-Host: 72.52.96.19 References: <52b36ae8$0$2266$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8343f16d-5366-4cda-a608-bea77978ef68@googlegroups.com> Subject: Re: How to load multiple test vector files, where the filename come from generic parameters? From: py Injection-Date: Thu, 19 Dec 2013 23:59:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7214 Thanks! I was stump earlier due to uneven filename length. This file of files approach sounds good. From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.58.169.81 with SMTP id ac17mr3905290vec.15.1387554959765; Fri, 20 Dec 2013 07:55:59 -0800 (PST) X-Received: by 10.50.239.132 with SMTP id vs4mr202310igc.4.1387554959580; Fri, 20 Dec 2013 07:55:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!ie8no25375100qab.0!news-out.google.com!l9ni254qay.0!nntp.google.com!ie8no25375090qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Dec 2013 07:55:59 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.213.16.101; posting-account=555uVAoAAADXkAwfYiuwybzzScWcHGjk NNTP-Posting-Host: 49.213.16.101 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4b655414-755c-46ec-9e78-9d688d95b477@googlegroups.com> Subject: barcode scanner program display with android.. From: Saifullah Hasshim Injection-Date: Fri, 20 Dec 2013 15:55:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7215 Hello..i have project that need to display item price to smarphone.. does anyone know how to display output at smartphone?? From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.tele2net.at!news.panservice.it!feed.xsnews.nl!border02.ams.xsnews.nl!feeder01.ams.xsnews.nl!abuse.newsxs.nl!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: barcode scanner program display with android.. References: <4b655414-755c-46ec-9e78-9d688d95b477@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: <7b3c$52b47a0f$5f6173bc$30260@abuse.newsxs.nl> X-Complaints-To: abuse@newsxs.nl Organization: Newsxs Date: Fri, 20 Dec 2013 18:10:39 +0100 Lines: 14 X-Upload: Secured through NewsXS SSL NNTP-Posting-Date: Fri, 20 Dec 2013 18:10:39 +0100 Xref: news.eternal-september.org comp.lang.vhdl:7216 In comp.lang.vhdl, Saifullah Hasshim wrote: > Hello..i have project that need to display item price to smarphone.. does anyone know how to display output at smartphone?? Ask in an appropriate group? You may find that the actual price is not included in the barcode, so be prepared to talk to the store's database as well. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Humans are communications junkies. We just can't get enough. -- Alan Kay From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: barcode scanner program display with android.. Date: Fri, 20 Dec 2013 10:03:34 -0800 Organization: Aioe.org NNTP Server Lines: 8 Message-ID: References: <4b655414-755c-46ec-9e78-9d688d95b477@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7217 On 12/20/2013 7:55 AM, Saifullah Hasshim wrote: > Hello..i have project that need to display item price to smarphone.. does anyone know how to display output at smartphone?? yes. JJS From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!ecngs!feeder2.ecngs.de!proxad.net!feeder1-1.proxad.net!cleanfeed1-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Fri, 20 Dec 2013 19:10:03 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: How to load multiple test vector files, where the filename come from generic parameters? References: <52b36ae8$0$2266$426a74cc@news.free.fr> <8343f16d-5366-4cda-a608-bea77978ef68@googlegroups.com> In-Reply-To: <8343f16d-5366-4cda-a608-bea77978ef68@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 7 Message-ID: <52b487f8$0$2036$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 20 Dec 2013 19:10:00 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1387563000 news-2.free.fr 2036 88.185.146.198:1065 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7218 Le 20/12/2013 00:59, py a écrit : > Thanks! I was stump earlier due to uneven filename length. This file of files approach sounds good. > It's ben a while since I've used this, my code may need some rework but the basic ideas is there. Nicolas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.52.72.37 with SMTP id a5mr13907154vdv.0.1388186529309; Fri, 27 Dec 2013 15:22:09 -0800 (PST) X-Received: by 10.49.88.5 with SMTP id bc5mr623354qeb.4.1388186529253; Fri, 27 Dec 2013 15:22:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no45912951qaj.0!news-out.google.com!p7ni6760qat.0!nntp.google.com!p15no45912942qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Dec 2013 15:22:09 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.120.62; posting-account=bnMNTQoAAABvQaaF2yBrhyaw89hiI2tr NNTP-Posting-Host: 46.11.120.62 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: structural VHDL From: gg Injection-Date: Fri, 27 Dec 2013 23:22:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2270 X-Received-Body-CRC: 1073285512 Xref: news.eternal-september.org comp.lang.vhdl:7219 hi all, I need to design a structural model of function unit (of a datapath) consisting of ALU and SHIFTER. http://s9.postimg.org/tw3hivo7j/datapath_fn.png As far as I know, a structural model is a code representing a block diagram of the system .. am I right? Now... with a very basic knowledge I obtained, I started by looking at the operations of both blocks in the function unit: ALU - ADD, ADDC, SUB, SUBC, AND, OR, XOR, NOT Shifter - ROR, ROL, RORC, ROLC Now, to start with, I tackled the ALU alone by defining each component. Example shown for addition and or operation. ___ entity ALU is port(A, B, c_in: in std_logic_vector(3 downto 0) ; sum, c_out: out std_logic_vector(3 downto 0)); end entity ALU; architecture structural of ALU is component Adder is port (x,y: in std_logic_vector(3 downto 0); sum, carry: out std_logic); end component Adder; ..... component or_1 is port (x,y: in std_logic_vector(3 downto 0); z : out std_logic); end component or_1; ___ and finally component instantiation statements: ___ begin Add_b: Adder port map(x=>A, y=>B, sum=>sum, carry=>c_out); .... Or_b: or_1 port map(x=>A, y=>B, z=>sum); end architecture structural; ___ 1. Am I on the right track? 2. Now I need to code the shifter as well .. How should I go with it? From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.189.228 with SMTP id gl4mr14035978pac.26.1388596709634; Wed, 01 Jan 2014 09:18:29 -0800 (PST) X-Received: by 10.49.1.104 with SMTP id 8mr185qel.22.1388596709541; Wed, 01 Jan 2014 09:18:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!kk17no1624395pbb.0!news-out.google.com!p7ni1129qat.0!nntp.google.com!p15no54281099qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jan 2014 09:18:29 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.4.47; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp NNTP-Posting-Host: 72.64.4.47 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Active-HDL: all writes to STDOUT are prefixed with "KERNEL:" From: Brian Davis Injection-Date: Wed, 01 Jan 2014 17:18:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7220 Does anyone know how to turn off the "KERNEL:" prefixing that occurs in Active-HDL ( using 9.2 Lattice Edition ) when one writes to STDOUT ? The closest thing I've found in the documentation is 'printdisplaytasksource', which just makes the prefixed message even more verbose. I have an existing testbench which writes log messages to STDOUT for later parsing; having this extra "KERNEL:" string prefixed to every write breaks the parser. i.e., the following VHDL: write (l, String'("Hello world!")); writeline (output, l); Produces: KERNEL: Hello world! Instead of the expected: Hello world! -Brian From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx21.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Active-HDL: all writes to STDOUT are prefixed with "KERNEL:" References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140102-0, 02/01/2014), Outbound message X-Antivirus-Status: Clean Lines: 34 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1388679348 86.29.12.221 (Thu, 02 Jan 2014 16:15:48 UTC) NNTP-Posting-Date: Thu, 02 Jan 2014 16:15:48 UTC Organization: virginmedia.com Date: Thu, 02 Jan 2014 16:15:46 +0000 X-Received-Body-CRC: 1517878295 X-Received-Bytes: 2195 Xref: news.eternal-september.org comp.lang.vhdl:7221 On 01/01/2014 17:18, Brian Davis wrote: > Does anyone know how to turn off the "KERNEL:" prefixing that occurs in Active-HDL ( using 9.2 Lattice Edition ) when one writes to STDOUT ? > > The closest thing I've found in the documentation is 'printdisplaytasksource', which just makes the prefixed message even more verbose. > > I have an existing testbench which writes log messages to STDOUT for later parsing; having this extra "KERNEL:" string prefixed to every write breaks the parser. > > i.e., the following VHDL: > > write (l, String'("Hello world!")); > writeline (output, l); > > Produces: > KERNEL: Hello world! > > Instead of the expected: > Hello world! > > -Brian > I suspect there must be something as it is quite a basic requirement (lots of testbenches write log files which are filtered/analysed later on). On Modelsim you can find the option on the main transcript menu (or use set PrefMain(LinePrefix) {# } in your script) which shows you how popular it is. If there is no option in Aldec then I guess you have to resort to a bit of good old text filtering. Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: or_reduce for array of std_ulogic_vectors REVISITED Date: Wed, 8 Jan 2014 16:27:13 -0600 Organization: A noiseless patient Spider Lines: 44 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="b965729184c29a924b6ec91cc606ed36"; logging-data="1163"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zqUgNRq0n8XmuxzH3FlCJC1QvZk14RJc=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:F/H8oqZVzHU90CcuFPymKLW1X0E= Xref: news.eternal-september.org comp.lang.vhdl:7222 Hi all, I posted back in November that I needed a funtion that would take as input an array of std_ulogic_vectors and return a std_ulogic_vector which is the OR of all of the vectors in the array. What we came up with is: function array_or( vectors : arr) return std_ulogic_vector is variable result : std_ulogic_vector (vectors(0)'range); begin result := vectors(0); for i in 1 to arr'length-1 loop result := result or vectors(i); end loop; return result; end array_or; where arr is defined like: type arr is array (0 to 99) of std_ulogic_vector(0 to 15); So array_or works for all arrays defined as type arr but not, for example, arrays of these types: type arr1 is array (0 to 99) of std_ulogic_vector(0 to 3); type arr2 is array (0 to 99) of std_ulogic_vector(0 to 63); type arr3 is array (0 to 99) of std_ulogic_vector(0 to 31); type arr4 is array (0 to 99) of std_ulogic_vector(0 to 87); I'm having trouble making the function general though because I will have numerous array types that I want to use with this one function. In my case all the arrays will all have the same number of array elements but the std_ulogic_vectors contained in the arrays have different lengths like the examples above. I want to be able to run array_or on diferent array types without having a function (even overloaded) for all the different sizes of std_ulogic_vector. Can this be done? The funtion above is already figuring out the range of the vector but I can't figure out how to pass some kind of generic sized array to the function. Any help would be appreciated. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.162.101 with SMTP id xz5mr101600pab.5.1389229340611; Wed, 08 Jan 2014 17:02:20 -0800 (PST) X-Received: by 10.182.118.138 with SMTP id km10mr1009obb.27.1389229340245; Wed, 08 Jan 2014 17:02:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!a5no6714231pbg.1!news-out.google.com!l9ni8458qay.0!nntp.google.com!p15no3636332qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 8 Jan 2014 17:02:20 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED From: KJ Injection-Date: Thu, 09 Jan 2014 01:02:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7223 On Wednesday, January 8, 2014 5:27:13 PM UTC-5, Richard Nicholas wrote: >=20 > Can this be done? The funtion above is already figuring out the range of= the vector but I=20 >=20 > can't figure out how to pass some kind of generic sized array to the func= tion. Any help=20 >=20 Arrays of arrays that are not constrained can be problematic at times. Wit= h VHDL-2008 you can at least define unconstrained arrays of arrays however = you can't always use them the way you'd like to (like what you're trying to= do). I don't think there is a way to do what you want with your function = and make it generic due to this limitation. A different approach is to make a two dimensional array: type sulv2d is array(natural range<>, natural range<>) of std_ulogic; Now you can write your function to work with any 2D array to implement your= function. The complication comes if you need to work with the std_ulogic_= vectors such as my_arr(3) which is no longer a std_ulogic_vector(0 to 3). = You can work around that difficulty by creating to/from conversion function= s that take as input the 2D array and the index of the row/column that you = want to extract or assign. The to_std_ulogic_vector function would return = a real std_ulogic_vector; the from_std_ulogic_vector would assign into the = 2D array the elements from the input std_ulogic_vector. Those to/from func= tions can be generic. The other way would be to rewrite your code to work = with the 2D array rather than a array of 1D vectors. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.236.86.77 with SMTP id v53mr1124729yhe.41.1389278421156; Thu, 09 Jan 2014 06:40:21 -0800 (PST) X-Received: by 10.182.111.170 with SMTP id ij10mr16738obb.18.1389278420828; Thu, 09 Jan 2014 06:40:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no4685689qaj.0!news-out.google.com!l9ni11962qay.0!nntp.google.com!p15no4685680qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jan 2014 06:40:20 -0800 (PST) In-Reply-To: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED From: Andy Injection-Date: Thu, 09 Jan 2014 14:40:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2793 X-Received-Body-CRC: 3970660527 Xref: news.eternal-september.org comp.lang.vhdl:7224 On Wednesday, January 8, 2014 7:02:20 PM UTC-6, KJ wrote: > With VHDL-2008 you can at least define unconstrained arrays of arrays how= ever > you can't always use them the way you'd like to (like what you're trying = to > do). I don't think there is a way to do what you want with your function = and > make it generic due to this limitation.=20 Just to be clear, 2008 std lets you define arrays (constrained or not) of u= nconstrained arrays. Prior versions of the standard required all elements o= f any array to be either scalar, constrained array or record types. I was not aware of 2008 restrictions on arrays of unconstrained arrays that= would prohibit their use as the OP desires. Restrictions that would prohib= it what the OP wants would drasticly limit the applications of such arrays.= Can you elaborate? Another approach/work-around that the OP might want to try is to add a leng= th argument to the function that explicitly defines the length of the resul= t vector and correspondingly, the length of each of the elements of the vec= tors argument. Perhaps this would work around the limitations you mentioned= ?=20 This solution would still requre a type for vectors that is an array (const= raine or not) of unconstrained arrays, and therefore 2008 compatibility wit= h all tools involved. Note that very few (if any) tools support ALL 2008 en= hancements, so each tool must be specifically checked (and tested) to confi= rm the desired feature is supported before the feature is adopted in a desi= gn. Andy From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED Date: Thu, 9 Jan 2014 10:44:52 -0600 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="4765"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Jwgcy9H3+vbRSvey1BgLaD2jWyu2qErA=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:sllK+zEfjb/f5Cy2YFQRCEIvJUE= Xref: news.eternal-september.org comp.lang.vhdl:7225 In article , jonesandy@comcast.net says... > > On Wednesday, January 8, 2014 7:02:20 PM UTC-6, KJ wrote: > > With VHDL-2008 you can at least define unconstrained arrays of arrays however > > you can't always use them the way you'd like to (like what you're trying to > > do). I don't think there is a way to do what you want with your function and > > make it generic due to this limitation. > > Just to be clear, 2008 std lets you define arrays (constrained or not) of unconstrained arrays. > Prior versions of the standard required all elements of any array to be either scalar, > constrained array or record types. > I was not aware of 2008 restrictions on arrays of unconstrained arrays that would prohibit > their use as the OP desires. Restrictions that would prohibit what the OP wants would > drasticly limit the applications of such arrays. Can you elaborate? I would really be sad if VHDL does not allow you to write a function that can OR together an array of std_logic_vectors without having to fix the size of the std_logic_vectors. > Another approach/work-around that the OP might want to try is to add a length argument > to the function that explicitly defines the length of the result vector and > correspondingly, the length of each of the elements of the vectors argument. Perhaps this > would work around the limitations you mentioned? I am interested in this idea. I would be happy to pass the length into the function. Do you know what syntax to make that work? Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED Date: Thu, 9 Jan 2014 10:49:53 -0600 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="4765"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX187bBn2mWPB5J2ozQKJvKv3ru+dI6CSWWg=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:GwTpEjDHT2vCI/NiAOT+pdiy2Xo= Xref: news.eternal-september.org comp.lang.vhdl:7226 In article <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com>, kkjennings@sbcglobal.net says... > The complication comes if you need to work with the std_ulogic_vectors such as my_arr(3) > which is no longer a std_ulogic_vector(0 to 3). Right. I do need to use to my_arr(3) as a std_ulogic_vector. >You can work around that difficulty by creating to/from conversion functions... Ug. Thanks for the suggestions. I'll continue to search for a cleaner solution before doing this. Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.182.112.231 with SMTP id it7mr2712396obb.22.1389324976324; Thu, 09 Jan 2014 19:36:16 -0800 (PST) X-Received: by 10.182.138.66 with SMTP id qo2mr72963obb.8.1389324976118; Thu, 09 Jan 2014 19:36:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!6no1517289qao.1!news-out.google.com!l9ni12267qay.0!nntp.google.com!p15no5892843qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jan 2014 19:36:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED From: KJ Injection-Date: Fri, 10 Jan 2014 03:36:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2620 X-Received-Body-CRC: 2073615496 Xref: news.eternal-september.org comp.lang.vhdl:7227 On Thursday, January 9, 2014 9:40:20 AM UTC-5, Andy wrote: > On Wednesday, January 8, 2014 7:02:20 PM UTC-6, KJ wrote: > I was not aware of 2008 restrictions on arrays of unconstrained arrays that > would prohibit their use as the OP desires. Restrictions that would prohibit > what the OP wants would drasticly limit the applications of such arrays. Can > you elaborate? Actually, it might work after all. I had an error in my rewrite of the function 'array_or' that made that led me to believe the function wasn't handling the unconstrained array of an unconstrained array. Upon reviewing, that problem has been cleaned up. The posted code below compiles and might actually perform the intended function. If not, it should provide a decent starting point. Kevin Jennings library ieee; use ieee.std_logic_1164.all; entity foo is end foo; architecture rtl of foo is subtype sulv_arr is std_ulogic_vector; type arr is array (natural range <>) of std_ulogic_vector; function array_or( vectors : arr) return std_ulogic_vector is variable result : std_ulogic_vector (vectors(vectors'left)'range); begin result := vectors(vectors'left); for i in vectors'range loop result := result or vectors(i); end loop; return result; end array_or; begin end rtl; From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.43.4.4 with SMTP id oa4mr2331320icb.2.1389325185153; Thu, 09 Jan 2014 19:39:45 -0800 (PST) X-Received: by 10.182.138.66 with SMTP id qo2mr73060obb.8.1389325185065; Thu, 09 Jan 2014 19:39:45 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no5896693qaj.0!news-out.google.com!l9ni12322qay.0!nntp.google.com!6no1521142qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jan 2014 19:39:44 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED From: KJ Injection-Date: Fri, 10 Jan 2014 03:39:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1610 X-Received-Body-CRC: 2393567092 Xref: news.eternal-september.org comp.lang.vhdl:7228 On Thursday, January 9, 2014 11:49:53 AM UTC-5, Richard Nicholas wrote: > Ug. Thanks for the suggestions. I'll continue to search for a cleaner > solution before doing > My later post is the cleaner solution you're looking for...whether it actually works the way you intend or not is for you to discover but at least it compiles (with VHDL 2008). Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED Date: Fri, 10 Jan 2014 10:27:36 -0600 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="30961"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xnZuAlQvkm+pLz4qKfRHQfH8JFWSxpzA=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:Wc1hlINsuzF1dCU0QvQ2bwEFEns= Xref: news.eternal-september.org comp.lang.vhdl:7229 In article , kkjennings@sbcglobal.net says... > > On Thursday, January 9, 2014 11:49:53 AM UTC-5, Richard Nicholas wrote: > > Ug. Thanks for the suggestions. I'll continue to search for a cleaner > > solution before doing > > > My later post is the cleaner solution you're looking for...whether it actually works the way you intend or not is for you to discover but at least it compiles (with VHDL 2008). > > Kevin Jennings Thank you so much. I'm looking forward to checking it out! Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.182.251.230 with SMTP id zn6mr4935112obc.14.1389412830023; Fri, 10 Jan 2014 20:00:30 -0800 (PST) X-Received: by 10.49.94.144 with SMTP id dc16mr110370qeb.21.1389412829956; Fri, 10 Jan 2014 20:00:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!6no3309755qao.1!news-out.google.com!l9ni13399qay.0!nntp.google.com!p15no7680252qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jan 2014 20:00:29 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.37.178.92; posting-account=GaKVeQoAAACeQC6QgJ6CcBIs1Fw4Qt1M NNTP-Posting-Host: 197.37.178.92 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <119f983a-142e-48e0-b73d-7e29d9786235@googlegroups.com> Subject: SOLUTIONS MANUAL: An Introduction To Management Science Quantitative Approaches To Decision Making 12th Ed by Anderson, Sweeney From: macmorino5@gmail.com Injection-Date: Sat, 11 Jan 2014 04:00:29 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7230 I have the instructor's solution manual for these textbooks .. They are all= in PDF format .. If you are interested in any one, please send an email to= macmorino(at)gmail(dot)com .. Please I CHARGE for sending the PDF files. Here are the solution manual to some titles.. =09 SOLUTIONS MANUAL: A First Course in the Finite Element Method, 4th Edition = logan SOLUTIONS MANUAL: A Course in Modern Mathematical Physics by Peter Szekeres SOLUTIONS MANUAL: A Course in Ordinary Differential Equations by Swift, Wir= kus SOLUTIONS MANUAL: A First Course in Abstract Algebra (7th Ed., John B. Fral= eigh) =20 SOLUTIONS MANUAL: A First Course in Differential Equations - The Classic F= ifth Edition By Zill, Dennis G SOLUTIONS MANUAL: A First Course in Differential Equations, 9th Ed by Denni= s G. Zill SOLUTIONS MANUAL: A First Course In Probability 7th Edition by Sheldon M. R= oss SOLUTIONS MANUAL: A First Course in Probability Theory, 6th edition, by S. = Ross. SOLUTIONS MANUAL: A First Course in String Theory, 2004, Barton Zwiebach SOLUTIONS MANUAL: A Practical Introduction to Data Structures and Algorithm= Analysis 2Ed by Shaffer SOLUTIONS MANUAL: A Quantum Approach to Condensed Matter Physics (Philip L.= Taylor & Olle Heinonen) SOLUTIONS MANUAL: A Short Course in General Relativity 2e by J. Foster and = J. D. Nightingale SOLUTIONS MANUAL: A Short Introduction to Quantum Information and Quantum C= omputation by Michel Le Bellac SOLUTIONS MANUAL: A Transition to Advanced Mathematics 5th E by Smith, Egge= n, Andre=20 SOLUTIONS MANUAL: Accounting Principles 8e by Kieso, Kimmel SOLUTIONS MANUAL: Accounting principles 8th Ed by Weygandt SOLUTIONS MANUAL: Accounting, 23 Ed by Carl S. Warren, James M. Reeve, Jona= than Duchac SOLUTIONS MANUAL: Accounting,8th Ed by Horngren,Harrison, Oliver SOLUTIONS MANUAL: Adaptive Control, 2nd. Ed., by Astrom, Wittenmark SOLUTIONS MANUAL: Adaptive Filter Theory (4th Ed., Simon Haykin) SOLUTIONS MANUAL: Advanced Accounting 10E international ED by Beams , Cleme= nt, Anthony, Lowensohn SOLUTIONS MANUAL: Advanced accounting 9th Ed by Hoyle, Schaefer SOLUTIONS MANUAL: Advanced Calculus Gerald B. Folland SOLUTIONS MANUAL: Advanced Digital Design with the Verilog HDL by Michael D= . Ciletti SOLUTIONS MANUAL: Advanced Dynamics (Greenwood) SOLUTIONS MANUAL: Advanced Engineering Electromagnetics by Constantine A. B= alanis SOLUTIONS MANUAL: Advanced Engineering Mathematics 3rd ed zill SOLUTIONS MANUAL: Advanced Engineering Mathematics 8Ed Erwin Kreyszig SOLUTIONS MANUAL: Advanced Engineering Mathematics by Erwin Kreyszig, 9th e= d SOLUTIONS MANUAL: Advanced Engineering Mathematics, 6th Edition by Peter V.= O'Neil SOLUTIONS MANUAL: Advanced Engineering Mathematics, 7th Ed by Peter V. O'Ne= il SOLUTIONS MANUAL: Advanced Engineering Mathematics,2E, by Zill, Cullen SOLUTIONS MANUAL: Advanced Engineering Thermodynamics, 3rd Edition by Adria= n Bejan SOLUTIONS MANUAL: Advanced Financial Accounting by Baker SOLUTIONS MANUAL: Advanced Financial Accounting 5 Ed by Baker=20 SOLUTIONS MANUAL: Advanced Financial Accounting 8 Ed by Baker=20 SOLUTIONS MANUAL: Advanced Functions & Introductory Calculus by Kirkpatrick= , McLeish, Montesanto SOLUTIONS MANUAL: Advanced Industrial Economics by Martin SOLUTIONS MANUAL: Advanced Industrial Economics, 2nd ED Stephen Martin SOLUTIONS MANUAL: Advanced Macroeconomics 2nd edition by David Romer SOLUTIONS MANUAL: Advanced Macroeconomics, by David Romer SOLUTIONS MANUAL: Advanced Mathematical Concepts Precalculus with Applicati= ons ( Glencoe ) SOLUTIONS MANUAL: Advanced Mechanics of Materials 6th ed by Boresi, Schmidt SOLUTIONS MANUAL: Advanced Modern Engineering Mathematics 3rd Ed Glyn James SOLUTIONS MANUAL: Advanced Modern Engineering Mathematics 4th Ed Glyn James SOLUTIONS MANUAL: Advanced Modern Engineering Mathematics, 3rd Ed., by G. J= ames SOLUTIONS MANUAL: Advanced Organic Chemistry Part A- Structure and Mechanis= ms 5th E by Carey, Sundberg SOLUTIONS MANUAL: Aircraft Structures for Engineering Students (4th Ed., T.= H.G. Megson) SOLUTIONS MANUAL: Algebra & Trigonometry and Precalculus, 3rd Ed By Beecher= , Penna, Bittinger SOLUTIONS MANUAL: Algebra Baldor SOLUTIONS MANUAL: Algebra-By Thomas W. Hungerford SOLUTIONS MANUAL: Algorithm Design (Jon Kleinberg & =C3=83=E2=80=B0va Tardo= s)=20 SOLUTIONS MANUAL: An Interactive Introduction to Mathematical Analysis 2nd = E (Jonathan Lewin) SOLUTIONS MANUAL: An Introduction To Analysis (3rdEd) -by William Wade SOLUTIONS MANUAL: An Introduction To Analysis 4th Ed by William Wade SOLUTIONS MANUAL: An Introduction to Database Systems (8th Ed., C.J. Date) SOLUTIONS MANUAL: An Introduction to Derivatives and Risk Management by cha= nce, brooks SOLUTIONS MANUAL: An Introduction to Economic Dynamics by Ronald Shone SOLUTIONS MANUAL: An Introduction To Management Science Quantitative Approa= ches To Decision Making 12th Ed by Anderson, Sweeney SOLUTIONS MANUAL: An Introduction to Modern Astrophysics (2nd Ed., Bradley = W. Carroll & Dale A. Ostlie) SOLUTIONS MANUAL: An Introduction to Numerical Analysis By Endre S=C3=BCli,= David F. Mayers SOLUTIONS MANUAL: An Introduction to Ordinary Differential Equations (James= C. Robinson) SOLUTIONS MANUAL: An Introduction to Signals and Systems by John Stuller SOLUTIONS MANUAL: An Introduction to Stochastic Modeling 3rd Ed by Taylor, = Karlin SOLUTIONS MANUAL: An Introduction to the Finite Element Method (3rd Ed., J.= N. Reddy) SOLUTIONS MANUAL: An Introduction to Thermal Physics by Schroeder, Daniel V SOLUTIONS MANUAL: An Introduction to Thermodynamics and Statistical Mechani= cs (2nd Ed, Keith Stowe) SOLUTIONS MANUAL: An Introduction to Wavelets through Linear Algebra by Fra= zier SOLUTIONS MANUAL: Analog Integrated Circuit Design, by Johns, Martin SOLUTIONS MANUAL: Analysis and Design of Analog Integrated Circuits (4th Ed= ition) by Gray , Lewis , Meyer SOLUTIONS MANUAL: Analysis and Design of Analog Integrated Circuits 5th Ed = ( vol.1 ) ch1-4 by Gray, Meyer SOLUTIONS MANUAL: Analysis With an Introduction to Proof 4th Ed By Steven R= . Lay SOLUTIONS MANUAL: Analysis, Synthesis,and Design of Chemical Processes 3rd = ED by Turton, Shaeiwitz SOLUTIONS MANUAL: Analytical Chemistry, Higson SOLUTIONS MANUAL: Analytical Mechanics 7E by Grant R. Fowles, George L. Cas= siday SOLUTIONS MANUAL: Antenna Theory 2nd edition by Balanis SOLUTIONS MANUAL: Antenna Theory and Design, 2nd Ed Vol.1 by Stutzman, Thie= le SOLUTIONS MANUAL: Antennas for All Applications (3rd Ed., John Kraus & Rona= ld Marhefka) SOLUTIONS MANUAL: Applied Calculus by Hallett,Gleason, Lock, Flath SOLUTIONS MANUAL: Applied Calculus for the Managerial, Life, and Social Sci= ences, 7 E, by Soo T. Tan SOLUTIONS MANUAL: Applied Calculus for the Managerial, Life, and Social Sci= ences, 8 E, by Soo T. Tan SOLUTIONS MANUAL: Applied Econometric Time Series, 2nd Edition by Enders SOLUTIONS MANUAL: Applied Electromagnetism 2nd Ed by Shen, Huang SOLUTIONS MANUAL: Applied Finite Element Analysis 2ed, by LJ SEGERLIND SOLUTIONS MANUAL: Applied Fluid Mechanics (6th Ed., Mott) SOLUTIONS MANUAL: Applied Linear Regression 3rd Ed by Sanford Weisberg SOLUTIONS MANUAL: Applied Linear Statistical Models 5th Ed by Kutner, Nacht= sheim SOLUTIONS MANUAL: Applied Mathematics, 3rd Ed by J. David Logan SOLUTIONS MANUAL: Applied Numerical Analysis, 7th Edition, by Gerald, Wheat= ley SOLUTIONS MANUAL: Applied Numerical Methods with MATLAB for Engineers and S= cientists 2nd E by Chapra SOLUTIONS MANUAL: Applied Numerical Methods with MATLAB for Engineers and S= cientists( Steven C. Chapra) SOLUTIONS MANUAL: Applied Partial Differential Equations (4th Ed., Haberman= ) SOLUTIONS MANUAL: Applied Partial Differential Equations by J. David Logan SOLUTIONS MANUAL: Applied Quantum Mechanics ( A. F. J. Levi ) SOLUTIONS MANUAL: Applied Statistics and Probability for Engineers ( 2nd Ed= ., Douglas Montgomery & George Runger ) SOLUTIONS MANUAL: Applied Statistics and Probability for Engineers (3rd Ed.= , Douglas Montgomery & George Runger) SOLUTIONS MANUAL: Applied Strength of Materials (4th Ed., Mott) SOLUTIONS MANUAL: Applied Strength of Materials (5th Ed., Mott) SOLUTIONS MANUAL: Applying Maths in the Chemical and Biomolecular Sciences,= Beddard SOLUTIONS MANUAL: Artificial Intelligence A Modern Approach 2e by Russell, = Norvig SOLUTIONS MANUAL: Artificial Neural Networks by B. Yegnanarayana and S. Ram= esh SOLUTIONS MANUAL: Assembly Language for Intel-Based Computers ( 3rd Edition= ) by Kip R. Irvine SOLUTIONS MANUAL: Auditing and Assurance Services- An Integrated Approach 1= 2E by Arens SOLUTIONS MANUAL: Auditing and Assurance Services, 12th edition, Alvin A Ar= ens, Randal J Elder, Mark Beasley SOLUTIONS MANUAL: Auditing and Assurance Services, 13 ed by Arens, Elder, B= easley SOLUTIONS MANUAL: Auditing and Assurance Services, 2nd Ed by Louwers SOLUTIONS MANUAL: Automatic Control Systems 9 Ed by Kuo, Golnaraghi SOLUTIONS MANUAL: Automatic Control Systems, 8E, by Kuo, Golnaraghi SOLUTIONS MANUAL: Basic Econometrics 4 ed by Damodar N. Gujarati SOLUTIONS MANUAL: Basic Electrical Engineering By Nagrath, D P Kothari SOLUTIONS MANUAL: Basic Electromagnetics with Applications by Nannapaneni N= arayana Rao SOLUTIONS MANUAL: Basic Engineering Circuit Analysis, 7th Ed by David Irwin SOLUTIONS MANUAL: Basic Engineering Circuit Analysis, 8th Edition by J. Dav= id Irwin, R. Mark Nelms SOLUTIONS MANUAL: Basic Engineering Circuit Analysis, 9th Ed by Irwin, Nelm= s SOLUTIONS MANUAL: Basic Engineering Mathematics by Chan, Hung SOLUTIONS MANUAL: Basic Heat and Mass Transfer by A. F. Mills SOLUTIONS MANUAL: Basic Principles and Calculations in Chemical Engineering= 7th E by Himmelblau, Riggs SOLUTIONS MANUAL: Basic Probability Theory by Robert B. Ash SOLUTIONS MANUAL: Bayesian Core by Christian P. Robert and Jean-Michel Mari= n SOLUTIONS MANUAL: Bioprocess Engineering Principles (Pauline M. Doran) SOLUTIONS MANUAL: Business Statistics - Decision Making 7th E by David F. G= roebner SOLUTIONS MANUAL: C++ for Computer Science and Engineering by Vic Broquard SOLUTIONS MANUAL: C++ How to Program 3rd edition - Deitel SOLUTIONS MANUAL: C++ How to Program 7th Ed by Deitel SOLUTIONS MANUAL: CALCULO VECTORIAL 7th Ed. by Louis Leithold SOLUTIONS MANUAL: Calculus 8th Edition by Varberg, Purcell, Rigdon SOLUTIONS MANUAL: Calculus - Early Transcendental Functions 3rd ED by Larso= n, Ron SOLUTIONS MANUAL: Calculus - Early Transcendentals, 6th E, by Anton, Bivens= , Davis SOLUTIONS MANUAL: Calculus - Early Transcendentals, 7E, by Anton, Bivens, D= avis SOLUTIONS MANUAL: Calculus - Late Transcendentals Single Variable, 8th Ed b= y Anton, Bivens, Davis SOLUTIONS MANUAL: Calculus (9th Ed., Dale Varberg, Edwin Purcell & Steve Ri= gdon) SOLUTIONS MANUAL: Calculus 2nd edition-M. Spivak SOLUTIONS MANUAL: Calculus 3rd Ed by Michael Spivak SOLUTIONS MANUAL: Calculus 6th ed by James Stewart SOLUTIONS MANUAL: Calculus 8th Ed by Ron Larson, Robert P. Hostetler, Bruce= H. Edwards SOLUTIONS MANUAL: Calculus A Complete Course 6th Edition by by R.A. Adams SOLUTIONS MANUAL: CALCULUS An Intuitive and Physical Approach 2nd ed by Mor= ris Kline SOLUTIONS MANUAL: Calculus and its Applications (11th Ed., Larry J Goldstei= n, Schneider, Lay & Asmar) SOLUTIONS MANUAL: Calculus by Gilbert Strang SOLUTIONS MANUAL: Calculus early transcendentals 8th Ed, by Anton Bivens D= avis SOLUTIONS MANUAL: Calculus Early Transcendentals, 5th Edition, JAMES STEWAR= T SOLUTIONS MANUAL: Calculus George Thomas 10th ed Vol 1 SOLUTIONS MANUAL: Calculus of Variations MA 4311 LECTURE NOTES ( Russak ) SOLUTIONS MANUAL: Calculus On Manifolds by Spivak SOLUTIONS MANUAL: Calculus One & Several Variables 8e by S Salas SOLUTIONS MANUAL: Calculus One And Several Variables 10th Edition by S Sala= s SOLUTIONS MANUAL: Calculus Vol 2 by Apostol SOLUTIONS MANUAL: Calculus Volume 1 by J. Marsden, A. Weinstein SOLUTIONS MANUAL: Calculus With Analytic Geometry 4th ( Henry Edwards & Dav= id E. Penney) SOLUTIONS MANUAL: Calculus with Applications 8 Edition by Lial, Greenwell, = Ritchey SOLUTIONS MANUAL: Calculus, 4th edition stewart SOLUTIONS MANUAL: Calculus, Early Transcendentals 7 Ed by Edwards & Penny SOLUTIONS MANUAL: Calculus, Single and Multivariable, 4E.,Vol 1& Vol 2 by H= ughes-Hallett,McCallum SOLUTIONS MANUAL: Calculus, Single Variable, 3E by Hughes-Hallett,McCallum SOLUTIONS MANUAL: Chemical and Engineering Thermodynamics 3Ed by Stanley I.= Sandler SOLUTIONS MANUAL: Chemical Engineering Design (Coulson & Richardson's Chemi= cal Engineering - Volume 6) - (4th Ed., Sinnott) SOLUTIONS MANUAL: Chemical Engineering Volume 1, 6th Edition, by Richardson= , Coulson,Backhurst, Harker SOLUTIONS MANUAL: Chemical Reaction Engineering 3rd ED by Octave Levenspiel SOLUTIONS MANUAL: Chemical, Biochemical, and Engineering Thermodynamics, 4t= h Ed by Sandler SOLUTIONS MANUAL: Chemistry 2nd Edition Vol.1 by Julia Burdge SOLUTIONS MANUAL: Chemistry, 10th Ed by Chang SOLUTIONS MANUAL: Chemistry, 7th Edition by Susan A. Zumdahl SOLUTIONS MANUAL: Chip Design for Submicron VLSI CMOS Layout and Simulation= , John P. Uyemura SOLUTIONS MANUAL: Cisco Technical Solution Series IP Telephony Solution Gui= de Version 2.0 SOLUTIONS MANUAL: Classical Dynamics of Particles and Systems, 5th Ed, by M= arion, Thornton SOLUTIONS MANUAL: Classical Dynamics, A Contemporary Approach (Jorge V. Jos= e) SOLUTIONS MANUAL: Classical Electrodynamics 2nd ED by John David Jackson SOLUTIONS MANUAL: Classical Electrodynamics by John David Jackson SOLUTIONS MANUAL: Classical Mechanics (Douglas Gregory) SOLUTIONS MANUAL: Classical Mechanics 2nd Ed by Goldstein SOLUTIONS MANUAL: CMOS Analog Circuit Design, 2ed by Phillip E. Allen, Doug= las R. Holberg SOLUTIONS MANUAL: CMOS- Circuit Design, Layout, and Simulation, Revised 2nd= Ed by R. Jacob Baker SOLUTIONS MANUAL: Cmos Digital Integrated Circuits , Sung-Mo Kang,Yusuf Leb= lebici SOLUTIONS MANUAL: CMOS Mixed-Signal Circuit Design, 2nd Ed by R. Jacob Bak= er SOLUTIONS MANUAL: CMOS VLSI Design Circuit & Design Perspective 3rd Ed by H= aris & West SOLUTIONS MANUAL: College Algebra 8th Ed by Michael Sullivan SOLUTIONS MANUAL: COLLEGE ALGEBRA AND TRIGONOMETRY 6th E by Aufmann, Barke= r, Verity SOLUTIONS MANUAL: College Geometry A Discovery Approach 2nd E by David Kay SOLUTIONS MANUAL: College Physics 8 ED by Serway, Faughn, Vuille SOLUTIONS MANUAL: College Physics 9th ED by Serway,Vuille (Teague) SOLUTIONS MANUAL: Communication Networks, 2e, Alberto Leon-Garcia, Indra Wi= djaja SOLUTIONS MANUAL: Communication Systems (4th Ed., Simon Haykin) SOLUTIONS MANUAL: Communication Systems An Introduction to Signals and Nois= e in Electrical Communication, 4E, A. Bruce Carlson SOLUTIONS MANUAL: Communication Systems Engineering (2nd Ed., John G. Proak= is & Masoud Salehi) SOLUTIONS MANUAL: Complex Variables and Applications 7 ed by JW Brown RV Ch= urchill SOLUTIONS MANUAL: Complex Variables with Applications, 3rd ED by David A. W= unsch SOLUTIONS MANUAL: COMPUTATIONAL FINANCE A SCIENTIFIC PERSPECTIVE MILEN KASS= ABOV,CORNELIS A. LOS SOLUTIONS MANUAL: Computational Techniques for Fluid Dynamics Srinivas, K.,= Fletcher, C.A.J. SOLUTIONS MANUAL: Computer Architecture - A Quantitative Approach, 4th Ed b= y Hennessy, Patterson SOLUTIONS MANUAL: Computer Architecture Pipelined & Parallel Processor Desi= gn by Michael J Flynn SOLUTIONS MANUAL: Computer Graphics Using OpenGL 3rd E by Francis S Hill, J= r. & Stephen M Kelley SOLUTIONS MANUAL: Computer Networking A Top-Down Approach Featuring the Int= ernet, 3E Kurose,Ross SOLUTIONS MANUAL: Computer Networking: A Top-Down Approach (4th Ed., James = F. Kurose & Keith W. Ross) SOLUTIONS MANUAL: Computer Networks - A Systems Approach 3 ed by Peterson D= avie=20 SOLUTIONS MANUAL: Computer Networks - A Systems Approach 4 ed by Peterson D= avie SOLUTIONS MANUAL: Computer Networks A Systems Approach, 2nd Edition, Larry = Peterson, Bruce Davie SOLUTIONS MANUAL: Computer Networks, 4th Ed., by Andrew S. Tanenbaum SOLUTIONS MANUAL: Computer Organization 3rd Edition by Carl Hamacher , Zvon= oko Vranesic ,Safwat Zaky SOLUTIONS MANUAL: Computer Organization and Architecture: Designing for Per= formance (7th Ed., William Stallings) SOLUTIONS MANUAL: Computer Organization and Design The Hardware Software In= terface 4 ed by David A Patterson SOLUTIONS MANUAL: Computer Organization and Design The Hardware Software In= terface, 3rd edition by David A Patterson and John L Hennessy SOLUTIONS MANUAL: Computer Science Illuminated 4th ed by Nell Dale, John Le= wis SOLUTIONS MANUAL: Computer system architecture 3rd Ed Morris Mano SOLUTIONS MANUAL: Computer Systems- A Programmer=E2=80=99s Perspective by B= ryant, O=E2=80=99Hallaron SOLUTIONS MANUAL: Computer Systems Organization and Architecture by John D.= Carpinelli SOLUTIONS MANUAL: Computer Vision A Modern Approach by Forsyth, Ponce SOLUTIONS MANUAL: Computer-Controlled Systems 3rd ED by Astrom, Wittenmark SOLUTIONS MANUAL: Concepts and Applications of Finite Element Analysis (4th= Ed., Cook, Malkus, Plesha & Witt) SOLUTIONS MANUAL: Concepts in Thermal Physics 2nd Ed by Blundell SOLUTIONS MANUAL: Concepts of Modern Physics 6th ED by Arthur Beiser SOLUTIONS MANUAL: Concepts of Physics (Volume 1 & 2) by H.C. Verma SOLUTIONS MANUAL: Concepts of Programming Languages 7th ED by Sebesta SOLUTIONS MANUAL: Construction Surveying and Layout 2ed by Crawford SOLUTIONS MANUAL: Contemporary Engineering Economics (4th Ed., Chan Park) SOLUTIONS MANUAL: Contemporary Engineering Economics 5th Ed by Chan S. Park SOLUTIONS MANUAL: Continuum Electromechanics by James R. Melcher SOLUTIONS MANUAL: Control Systems Engineering, 4E, by Norman Nise SOLUTIONS MANUAL: Control Systems Engineering, 6th ED by Norman Nise SOLUTIONS MANUAL: Control Systems Principles and Design 2e by M. Gopal SOLUTIONS MANUAL: Convex Analysis and Optimization Dimitri P. Bertsekas SOLUTIONS MANUAL: Corporate Finance & MyFinanceLab Student Access Code Card= , Global 2 Ed by Berk, DeMarzo SOLUTIONS MANUAL: Corporate Finance 8th edition by Ross SOLUTIONS MANUAL: Corporate Finance 9th edition by Ross SOLUTIONS MANUAL: Corporate Finance The Core plus MyFinanceLab Student Acce= ss Kit (Jonathan Berk & Peter DeMarzo) SOLUTIONS MANUAL: Corporate Finance, 7E, by Ross SOLUTIONS MANUAL: Corporations, Partnerships, Estates and Trusts ( 2011 ) b= y Hoffman, Maloney SOLUTIONS MANUAL: COST ACCOUNTING - Creating Value for Management 5th E by = MICHAEL MAHER SOLUTIONS MANUAL: Cost Accounting-A Managerial Emphasis 13th Ed by Charles = Horngren SOLUTIONS MANUAL: Coulson & Richardson=E2=80=99s Chemical Engineering (Vol = 2 - 5th Ed) & (Vol 3 - 3rd Ed) by BACKHURST, HARKER SOLUTIONS MANUAL: Cryptography and Network Security (4th Ed., William Stall= ings) SOLUTIONS MANUAL: Data & Computer Communication, 7th Ed, by William Stallin= gs SOLUTIONS MANUAL: Data Communications Networking 4th Ed by Behrouz Forouzan SOLUTIONS MANUAL: Data Structures and Algorithm Analysis in C 2nd ED by Wei= ss SOLUTIONS MANUAL: Data Structures with Java by John R. Hubbard, Anita Huray SOLUTIONS MANUAL: Database Management Systems, 3rd Ed., by Ramakrishnan, Ge= hrke SOLUTIONS MANUAL: Database System Concepts 4th ED by Silberschatz , Korth ,= Sudarshan SOLUTIONS MANUAL: Database System Concepts 5th ED by Silberschatz, Korth, S= udarshan SOLUTIONS MANUAL: Derivatives - Principles & Practice by Sundaram , Das SOLUTIONS MANUAL: Design Analysis in Rock Mechanics by William G. Pariseau SOLUTIONS MANUAL: Design and Analysis of Experiments, 6E, by Montgomery SOLUTIONS MANUAL: Design of Analog CMOS Integrated Circuits by Razavi SOLUTIONS MANUAL: Design of Analog CMOS Integrated Circuits, 2 Edition, by = Razavi Douglas C. Montgomery SOLUTIONS MANUAL: Design of Fluid Thermal Systems, 2nd Edition janna SOLUTIONS MANUAL: Design of Machinery (3rd Ed., Norton) SOLUTIONS MANUAL: Design of machinery 4th ed by Norton SOLUTIONS MANUAL: Design of Reinforced Concrete, 8th Ed by McCormac, Brown SOLUTIONS MANUAL: Design with Constructal Theory by Adrian Bejan, Lorente SOLUTIONS MANUAL: Design with Operational Amplifiers and Analog Integrated = Circuits (3rd Ed., Sergio Franco) SOLUTIONS MANUAL: Device Electronics for Integrated Circuits 3rd Edition by= muller kamins SOLUTIONS MANUAL: Differential Equations & Linear Algebra 3rd ed by C. Henr= y Edwards & David E. Penney SOLUTIONS MANUAL: Differential Equations and Boundary Value Problems - Comp= uting and Modeling 4th Ed by Edwards, Penney SOLUTIONS MANUAL: Differential Equations and Linear Algebra ( 2nd Ed., Jerr= y Farlow, Hall, McDill & West) SOLUTIONS MANUAL: Differential Equations and Linear Algebra ( C. Henry Edwa= rds & David E. Penney) SOLUTIONS MANUAL: Differential Equations and Linear Algebra 3e by Stephen W= Goode SOLUTIONS MANUAL: Differential Equations with Boundary Value Problems (2e, = John Polking, Al Boggess & Arnold) SOLUTIONS MANUAL: Digital & Analog Communication Systems (7th Ed., Leon W. = Couch) SOLUTIONS MANUAL: Digital Communication 3rd ED by Barry, Lee, Messerschmitt SOLUTIONS MANUAL: Digital Communications Fundamentals and Applications 2e B= ernard Sklar SOLUTIONS MANUAL: Digital Communications, 4E, by Proakis SOLUTIONS MANUAL: Digital Control & State Variable Methods 2nd Ed by Madan = Gopal SOLUTIONS MANUAL: Digital Design (4th Ed., M. Morris Mano & Michael D. Cile= tti) SOLUTIONS MANUAL: Digital Design: Principles and Practices Package (4th Ed.= , John F. Wakerly) SOLUTIONS MANUAL: Digital Fundamentals ( 9th Ed., Thomas L. Floyd) SOLUTIONS MANUAL: Digital Image Processing, 2e, by Gonzalez, Woods SOLUTIONS MANUAL: Digital Integrated Circuits, 2nd Ed., by Rabaey SOLUTIONS MANUAL: Digital Logic Design by Mano SOLUTIONS MANUAL: Digital Signal Processing - A Modern Introduction, by Ash= ok Ambardar SOLUTIONS MANUAL: Digital Signal Processing Principles, Algorithms and App= lications, 3rd Edition by John G. Proakis SOLUTIONS MANUAL: Digital Signal Processing 4th Ed by Proakis, Manolakis SOLUTIONS MANUAL: Digital Signal Processing a computer based approach (2nd = Ed.) (Mitra) SOLUTIONS MANUAL: Digital Signal Processing a computer based approach (Mitr= a) SOLUTIONS MANUAL: Digital Signal Processing by Proakis & Manolakis SOLUTIONS MANUAL: Digital Signal Processing by Thomas J. Cavicchi SOLUTIONS MANUAL: Digital Systems - Principles and Applications (10th Ed., = Ronald Tocci, Neal Widmer, Greg Moss) SOLUTIONS MANUAL: Discovering Advanced Algebra - An Investigative Approach SOLUTIONS MANUAL: Discrete and Combinatorial Mathematics 5e by Ralph P. Gri= maldi SOLUTIONS MANUAL: Discrete Mathematics ( 6th Ed., Richard Johnsonbaugh ) SOLUTIONS MANUAL: Discrete Mathematics ( 6th Edition) by Richard Johnsonbau= gh SOLUTIONS MANUAL: Discrete Mathematics 3rd ED by Goodaire, Parmenter SOLUTIONS MANUAL: Discrete Mathematics with Applications 3rd ED by Susanna = S. Epp SOLUTIONS MANUAL: Discrete Random Signals and Statistical Signal Processing= Charles W. Therrien SOLUTIONS MANUAL: Discrete Time Signal Processing, 2nd Edition, Oppenheim SOLUTIONS MANUAL: Discrete-Event System Simulation 3rd Ed by banks SOLUTIONS MANUAL: Discrete-Time Signal Processing 3rd ed by Oppenheim, Scha= fer SOLUTIONS MANUAL: DSP First A Multimedia Approach-Mclellan, Schafer & Yoder SOLUTIONS MANUAL: Dynamic Modeling and Control of Engineering Systems 2 E T= . Kulakowski , F. Gardner, Shearer SOLUTIONS MANUAL: Dynamics of Flight- Stability and Control, 3rd Ed by Etki= n, Reid SOLUTIONS MANUAL: Dynamics of Mechanical Systems by C. T. F. Ross SOLUTIONS MANUAL: Dynamics of Structures 2nd ED by Clough, Penzien SOLUTIONS MANUAL: Dynamics of structures 3rd E by Anil K. Chopra SOLUTIONS MANUAL: Econometric Analysis of Cross Section and Panel Data (200= 3 ) by Jeffrey M Wooldridge SOLUTIONS MANUAL: Econometric Analysis, 5E, by Greene SOLUTIONS MANUAL: Econometric Analysis, 6E, by Greene SOLUTIONS MANUAL: Econometrics of Financial Markets, by Adamek, Cambell, Lo= , MacKinlay, Viceira SOLUTIONS MANUAL: Econometrics, 2nd edition by Badi H. Baltagi SOLUTIONS MANUAL: Econometrics: A Modern Introduction (Michael P. Murray) SOLUTIONS MANUAL: Elasticity - Theory, Applications and Numerics 2nd ED by = Martin H. Sadd SOLUTIONS MANUAL: Electric Circuits (7th Ed., James W Nilsson & Susan Riede= l) SOLUTIONS MANUAL: Electric Circuits (8th Ed., James W Nilsson & Susan Riede= l) SOLUTIONS MANUAL: Electric Circuits 9th Ed by Nilsson, Riedel SOLUTIONS MANUAL: Electric Machinery 6th ed. A.E. Fitzgerald,Kingsley,Umans SOLUTIONS MANUAL: Electric Machinery and Power System Fundamentals (Chapman= ) SOLUTIONS MANUAL: Electric Machinery Fundamentals (4th Ed., Chapman) SOLUTIONS MANUAL: Electric Machines Analysis and Design Applying MATLAB,Jim= Cathey SOLUTIONS MANUAL: Electric Machines By D. P. Kothari, I. J. Nagrath SOLUTIONS MANUAL: Electrical Engineering - Principles and Applications 5E H= ambley SOLUTIONS MANUAL: Electrical Engineering Principles and Applications (3rd E= d., Allan R. Hambley) SOLUTIONS MANUAL: Electrical Engineering Principles and Applications (4th E= d., Allan R. Hambley) SOLUTIONS MANUAL: Electrical Machines, Drives and Power Systems (6th Ed., T= heodore Wildi) SOLUTIONS MANUAL: Electromagnetic Fields and Energy by Haus, Melcher SOLUTIONS MANUAL: Electromagnetics Problem Solver (Problem Solvers) By The = Staff of REA SOLUTIONS MANUAL: Electromagnetism. Principles and Applications by LORRAIN,= PAUL ; CORSON, DAVID SOLUTIONS MANUAL: Electromechanical Dynamics Part 1, 2, 3 by Herbert H. Woo= dson, James R. Melcher SOLUTIONS MANUAL: Electronic Circuit Analysis, 2nd Ed., by Donald Neamen SOLUTIONS MANUAL: Electronic Devices 6th ed and electronic devices Electro= n Flow Version 4th ed, Floyd SOLUTIONS MANUAL: Electronic Devices and Circuit Theory 10th Ed by Boylesta= d, Nashelsky SOLUTIONS MANUAL: Electronic Devices and Circuit Theory 8th Ed by Robert Bo= ylestad SOLUTIONS MANUAL: Electronic Physics Strabman SOLUTIONS MANUAL: Electronics & Communication Engineering 5th ED by Kanodi= a=20 SOLUTIONS MANUAL: Electronics, 2nd Ed., by Allan R. Hambley SOLUTIONS MANUAL: Elementary Differential Equations ( Werner E. Kohler, Joh= nson) SOLUTIONS MANUAL: Elementary Differential Equations and Boundary Value Prob= lems (8th Ed., Boyce & Diprima) SOLUTIONS MANUAL: Elementary Linear Algebra 5th edition by Stanley I. Gross= man SOLUTIONS MANUAL: Elementary Linear Algebra by Matthews SOLUTIONS MANUAL: Elementary Linear Algebra with Applications (9th Ed., How= ard Anton & Chris Rorres) SOLUTIONS MANUAL: Elementary Linear Algebra with Applications 9E by Kolman,= Hill SOLUTIONS MANUAL: Elementary mechanics & thermodynamics jhon w.Nobury SOLUTIONS MANUAL: ELEMENTARY NUMBER THEORY AND ITS APPLICATIONS, (5TH EDITI= ON, Bart Goddard, Kenneth H. Rosen) SOLUTIONS MANUAL: Elementary Number Theory and Its Applications, 6th Ed by = Kenneth H. Rosen SOLUTIONS MANUAL: Elementary Principles of Chemical Processes (3rd Ed., Fel= der & Rousseau) SOLUTIONS MANUAL: Elementary Statistics Using The Graphing Calculator 9 Ed = by MILTON LOYER SOLUTIONS MANUAL: Elementary Statistics Using the Graphing Calculator For t= he TI-83-84 Plus (Mario F. Triola) SOLUTIONS MANUAL: ELEMENTARY SURVEYING 13th ED by Ghilani,Wolf SOLUTIONS MANUAL: Elements of Information Theory - M. Cover, Joy A. Thomas SOLUTIONS MANUAL: Elements of Chemical Reaction Engineering 4th Edition by = Fogler=20 SOLUTIONS MANUAL: Elements of Chemical Reaction Engineering by Fogler hubba= rd, hamman , johnson , 3rd edition SOLUTIONS MANUAL: Elements of Deductive Inference by Bessie, Glennan SOLUTIONS MANUAL: Elements of Electromagnetics , 2 ed by Matthew N. O. Sadi= ku SOLUTIONS MANUAL: Elements of Electromagnetics , 3ed by Matthew N. O. Sadik= u SOLUTIONS MANUAL: Elements of Forecasting in Business, Finance, Economics a= nd Government by Diebold SOLUTIONS MANUAL: Embedded Microcomputer Systems Real Time Interfacing, 2nd= Edition , Jonathan W. Valvano SOLUTIONS MANUAL: Embedded System Design by Vahid, Givargis SOLUTIONS MANUAL: Engineering and Chemical Thermodynamics (Koretsky) SOLUTIONS MANUAL: ENGINEERING BIOMECHANICS (STATICS) by Angela Matos, Eladi= o Pereira, Juan Uribe and Elisandra Valentin SOLUTIONS MANUAL: Engineering Circuit Analysis 6Ed, Luay Shaban SOLUTIONS MANUAL: Engineering Circuit Analysis 6th ed by Hayt SOLUTIONS MANUAL: Engineering Circuit Analysis 7th Ed. by William H. Hayt J= r SOLUTIONS MANUAL: Engineering Economic Analysis 9th ED by Newnan SOLUTIONS MANUAL: Engineering Economy and the Decision-Making Process (Jose= ph C. Hartman) SOLUTIONS MANUAL: Engineering Economy, 14 Ed by Sullivan SOLUTIONS MANUAL: Engineering Electromagnetics 6E by William H. Hayt Jr. an= d John A. Buck SOLUTIONS MANUAL: Engineering Electromagnetics 7E by William H. Hayt Jr. an= d John A. Buck SOLUTIONS MANUAL: Engineering Fluid Mechanics - 8th Ed by Crowe, Elger & Ro= berson SOLUTIONS MANUAL: Engineering Fluid Mechanics 7th Ed by Crowe and Donald SOLUTIONS MANUAL: Engineering Materials Science, by Milton Ohring SOLUTIONS MANUAL: Engineering Mathematics (4th Ed., John Bird) SOLUTIONS MANUAL: Engineering Mechanics - Dynamics by Boresi, Schmidt SOLUTIONS MANUAL: Engineering Mechanics - Dynamics, 5th Ed (J. L. Meriam, L= . G. Kraige) SOLUTIONS MANUAL: Engineering Mechanics - Dynamics, 6th Ed (J. L. Meriam, L= . G. Kraige) SOLUTIONS MANUAL: Engineering Mechanics - Statics (10th Edition) by Russell= C. Hibbeler SOLUTIONS MANUAL: Engineering Mechanics - Statics (11th Edition) by Russell= C. Hibbeler SOLUTIONS MANUAL: Engineering Mechanics - Statics by Boresi, Schmidt SOLUTIONS MANUAL: Engineering Mechanics - Statics, 4th Ed (J. L. Meriam, L.= G. Kraige) SOLUTIONS MANUAL: Engineering Mechanics - Statics, 6th Ed (J. L. Meriam, L.= G. Kraige) SOLUTIONS MANUAL: Engineering Mechanics : Dynamics (11th Ed., Hibbeler) SOLUTIONS MANUAL: Engineering Mechanics by Manoj Kumar Harbola SOLUTIONS MANUAL: Engineering Mechanics Dynamic (10th Edition) hibbeler SOLUTIONS MANUAL: Engineering Mechanics Dynamics (12th Ed., Hibbeler) SOLUTIONS MANUAL: Engineering Mechanics Dynamics, Bedford & Fowler, 5th Edi= tion SOLUTIONS MANUAL: Engineering Mechanics Dynamics, by R. C. Hibbeler, 3rd SOLUTIONS MANUAL: Engineering Mechanics Statics (12th Ed., Hibbeler) SOLUTIONS MANUAL: Engineering Mechanics Statics, Bedford & Fowler, 5th Edit= ion SOLUTIONS MANUAL: Engineering Mechanics, Dynamics 2nd E by Riley, Sturges SOLUTIONS MANUAL: Engineering Mechanics, Statics 2nd E by Riley, Sturges SOLUTIONS MANUAL: Engineering Statistics (4th Ed., Douglas Montgomery, Geor= ge Runger & Norma Faris Hubele) SOLUTIONS MANUAL: Engineering Vibration 3rd Ed by Inman SOLUTIONS MANUAL: Equilibrium Statistical Physics, 2nd E by Plischke, Ber= gersen SOLUTIONS MANUAL: Erosion and sedimentation by Pierre Y. Julien SOLUTIONS MANUAL: Essentials of Corporate Finance 6th Ed by Ross,Westerfiel= d,Jordan SOLUTIONS MANUAL: Essentials of Corporate Finance 7th Ed by Ross,Westerfiel= d,Jordan SOLUTIONS MANUAL: Essentials of Soil Mechanics and Foundations: Basic Geote= chnics (7th Ed., David F. McCarthy) SOLUTIONS MANUAL: Experimental Methods for Engineers 8th ED by Holman SOLUTIONS MANUAL: Feedback Control of Dynamic Systems (4th Ed., Franklin, P= owell & Emami-Naeini) SOLUTIONS MANUAL: Feedback Control of Dynamic Systems (5th Ed., Franklin, P= owell & Emami-Naeini) SOLUTIONS MANUAL: Feedback Control of Dynamic Systems 6th E by Franklin, P= owell, Naeini SOLUTIONS MANUAL: Field and Wave Electromagnetics 2nd Ed by David K. Cheng SOLUTIONS MANUAL: Financial Accounting 6th E with Annual Report by Libby, S= hort SOLUTIONS MANUAL: Financial Accounting 6th Ed by Harrison SOLUTIONS MANUAL: Financial Accounting An Integrated Approach, 6th Ed by Gi= bbins SOLUTIONS MANUAL: Financial Management- Principles and Applications, 10th E= d by Keown, Scott SOLUTIONS MANUAL: Financial Management- Theory and Practice 12 th ED by Bri= gham, Ehrhardt SOLUTIONS MANUAL: Financial Reporting and Analysis Using Financial Accounti= ng Information 10th Ed by Gibson SOLUTIONS MANUAL: Financial Reporting and Analysis, 3E by Revsine, Collins,= Johnson SOLUTIONS MANUAL: Finite Element Techniques in Structural Mechanics Ross SOLUTIONS MANUAL: First Course in Abstract Algebra, 3rd Ed by Joseph J. Rot= man SOLUTIONS MANUAL: First Course in Probability (7th Ed., Sheldon Ross) SOLUTIONS MANUAL: Fluid Mechanics (5th Ed., White) SOLUTIONS MANUAL: Fluid Mechanics 4th Ed by Cohen, Kundu SOLUTIONS MANUAL: Fluid Mechanics 4th Edition by Frank M. White SOLUTIONS MANUAL: Fluid Mechanics and Thermodynamics of Turbomachinery (5th= Ed., S.L. Dixon) SOLUTIONS MANUAL: Fluid Mechanics by CENGEL SOLUTIONS MANUAL: Fluid Mechanics Egon Krause SOLUTIONS MANUAL: Fluid Mechanics for Chemical Engineers, 3rd Ed by Noel de= Nevers SOLUTIONS MANUAL: Fluid Mechanics Fundamentals and Applications by =C3=87en= gel & Cimbala SOLUTIONS MANUAL: Fluid Mechanics with Engineering Applications, 10th Editi= on, by Finnemore SOLUTIONS MANUAL: Foundations of Analog and Digital Electronic Circuits by = Agarwal, Lang SOLUTIONS MANUAL: Foundations of Applied Combinatorics by Bender, Williamso= n SOLUTIONS MANUAL: Foundations of Colloid Science 2e , Hunter SOLUTIONS MANUAL: Foundations of Electromagnetic Theory by John R. Reitz, F= rederick J. Milford SOLUTIONS MANUAL: Foundations of Mathematical Economics by Michael Carter SOLUTIONS MANUAL: Foundations of Modern Macroeconomics 2nd Ed by Heijdra, = Reijnders, Romp SOLUTIONS MANUAL: Fourier and Laplace Transform - Antwoorden SOLUTIONS MANUAL: Fractal Geometry Mathematical Foundations and Application= s, 2nd Ed Kenneth Falcone SOLUTIONS MANUAL: fracture mechanics ; fundamentals and applications, 2E, b= y T.L. Anderson SOLUTIONS MANUAL: From Polymers to Plastics By A.K. van der Vegt SOLUTIONS MANUAL: Fundamental Methods of Mathematical Economics 4th E by Ch= iang,Wainwright SOLUTIONS MANUAL: Fundamental Quantum Mechanics for Engineers by Leon van D= ommelen SOLUTIONS MANUAL: Fundamentals of Advanced Accounting By Fischer, Taylor SOLUTIONS MANUAL: Fundamentals of Aerodynamics ( 3 Ed., Anderson) SOLUTIONS MANUAL: Fundamentals of Aerodynamics (2 Ed., Anderson) SOLUTIONS MANUAL: Fundamentals of Aircraft Structural Analysis by Howard D.= Curtis SOLUTIONS MANUAL: Fundamentals of Applied Electromagnetics (5th Ed., Fawwaz= T. Ulaby) SOLUTIONS MANUAL: Fundamentals of Chemical Reaction Engineering by Davis SOLUTIONS MANUAL: Fundamentals of Complex Analysis ( 3rd Ed., E. Saff & Art= hur Snider ) SOLUTIONS MANUAL: Fundamentals of Computer Organization and Architecture by= Abd-El-Barr, El-Rewini=20 SOLUTIONS MANUAL: Fundamentals of Corporate Finance 8th edition by Ross SOLUTIONS MANUAL: Fundamentals of Corporate Finance 9th edition by Ross SOLUTIONS MANUAL: Fundamentals of Corporate Finance, 4th Edition (Brealey, = Myers, Marcus) SOLUTIONS MANUAL: Fundamentals of Differential Equations 7E Kent Nagle, B. = Saff, Snider SOLUTIONS MANUAL: Fundamentals of Differential Equations and Boundary Value= Problems, 6th Ed by Nagle ,Saff, Snider SOLUTIONS MANUAL: Fundamentals of Digital Logic with VHDL Design (1st Ed., = Stephen Brown Vranesic) SOLUTIONS MANUAL: Fundamentals of Electric Circuits (2nd.ed.) by C.K.Alexan= der M.N.O.Sadiku SOLUTIONS MANUAL: Fundamentals of Electric Circuits (4E., Charles Alexander= & Matthew Sadiku) SOLUTIONS MANUAL: Fundamentals of Electromagnetics with Engineering Applica= tions (Stuart Wentworth) SOLUTIONS MANUAL: Fundamentals of Electronic Circuit Design , Comer SOLUTIONS MANUAL: Fundamentals of Engineering Economics 2nd E by Chan S. Pa= rk SOLUTIONS MANUAL: FUNDAMENTALS OF ENGINEERING ELECTROMAGNETICS, by DAVID CH= ENG SOLUTIONS MANUAL: Fundamentals of Engineering Thermodynamics, 6th Ed (Micha= el J. Moran, Howard N. Shapiro) SOLUTIONS MANUAL: Fundamentals of Engineering Thermodynamics, 7th Ed (Micha= el J. Moran, Howard N. Shapiro) SOLUTIONS MANUAL: Fundamentals of Financial Management 12th edition James C= . Van Horne, Wachowicz SOLUTIONS MANUAL: Fundamentals of Fluid Mechanics 5th Ed Munson Young Okiis= hi SOLUTIONS MANUAL: Fundamentals of Fluid Mechanics 6th Ed by Munson SOLUTIONS MANUAL: Fundamentals of Fluid Mechanics, 4E (Bruce R. Munson, Don= ald F. Young, Theodore H.) SOLUTIONS MANUAL: Fundamentals of Heat and Mass Transfer - 5th Edition F.P.= Incropera D.P. DeWitt SOLUTIONS MANUAL: Fundamentals of Heat and Mass Transfer (4th Ed., Incroper= a, DeWitt) SOLUTIONS MANUAL: Fundamentals of Heat and Mass Transfer (6th Ed., Incroper= a, DeWitt) SOLUTIONS MANUAL: Fundamentals of Hydraulic Engineering Systems 4th E by Ho= ughtalen,Akan,Hwang SOLUTIONS MANUAL: Fundamentals of Investments, 4 th ed by Jordan and Miller SOLUTIONS MANUAL: Fundamentals of Investments, 5th E by Jordan, Miller SOLUTIONS MANUAL: Fundamentals of Investments, 6th E by Jordan, Miller,Dolv= in SOLUTIONS MANUAL: Fundamentals of Logic Design, 5th Ed., by Charles Roth SOLUTIONS MANUAL: Fundamentals of Machine Component Design (3rd Ed., Juvina= ll) SOLUTIONS MANUAL: Fundamentals of Machine Component Design 4th Ed by Juvina= ll SOLUTIONS MANUAL: Fundamentals of Machine Elements 2nd E by Bernard Hamrock SOLUTIONS MANUAL: Fundamentals of Machine Elements by Bernard Hamrock SOLUTIONS MANUAL: Fundamentals of Manufacturing 2nd Edition by Philip D. Ru= fe SOLUTIONS MANUAL: Fundamentals of Materials Science and Engineering- An Int= egrated Approach, 3rd Ed by Callister SOLUTIONS MANUAL: Fundamentals of Microelectronics by Behzad Razavi SOLUTIONS MANUAL: Fundamentals of Modern Manufacturing 3rd Ed by Mikell P. = Groover SOLUTIONS MANUAL: Fundamentals of Modern Manufacturing: Materials, Processe= s, and Systems (2nd Ed., Mikell P. Groover) SOLUTIONS MANUAL: Fundamentals of Modern Manufacturing: Materials, Processe= s, and Systems 4th Ed.by Groover SOLUTIONS MANUAL: Fundamentals of Momentum, Heat and Mass Transfer, 4th Ed = by Welty,Wilson SOLUTIONS MANUAL: Fundamentals of Momentum, Heat and Mass Transfer, 5th Ed = by Welty,Wilson SOLUTIONS MANUAL: Fundamentals of Organic Chemistry, 5E, by T. W. Graham So= lomons SOLUTIONS MANUAL: Fundamentals of Physics (7th Ed., David Halliday, Robert = Resnick & Jearl Walker) SOLUTIONS MANUAL: Fundamentals of Physics 9th Ed by Resnick, Walker, Hallid= ay SOLUTIONS MANUAL: Fundamentals of Physics, 8th Edition Halliday, Resnick, W= alker SOLUTIONS MANUAL: Fundamentals of Power Semiconductor Devices By Jayant Bal= iga SOLUTIONS MANUAL: Fundamentals of Probability, with Stochastic Processes (3= rd Ed., Saeed Ghahramani) SOLUTIONS MANUAL: Fundamentals of Quantum Mechanics (C.L. Tang) SOLUTIONS MANUAL: Fundamentals of Semiconductor Devices, 1st Edition by And= erson SOLUTIONS MANUAL: Fundamentals of Signals and Systems Using the Web and Mat= lab (3rd Ed., Kamen & Bonnie S Heck) SOLUTIONS MANUAL: Fundamentals of Solid-State Electronics by Chih-Tang Sah SOLUTIONS MANUAL: Fundamentals of Structural Analysis 3rd Ed by Leet SOLUTIONS MANUAL: Fundamentals of Thermal-Fluid Sciences, 2nd Ed. by Cengel SOLUTIONS MANUAL: Fundamentals of Thermodynamics 5th Ed by Sonntag, Borgnak= ke and Van Wylen SOLUTIONS MANUAL: Fundamentals of Thermodynamics 6th Ed by Sonntag, Borgnak= ke & Van Wylen SOLUTIONS MANUAL: Fundamentals of Thermodynamics 7th Ed by Borgnakke, Sonnt= ag SOLUTIONS MANUAL: Fundamentals of Wireless Communication by Tse and Viswana= th SOLUTIONS MANUAL: Fundamentals of Wireless Communication by Tse, Viswanath SOLUTIONS MANUAL: Fundamentals of Digital Signal Processing using MATLAB, 2= nd Ed by Schilling, Harris SOLUTIONS MANUAL: Gas Dynamics (3rd Ed., John & Keith) SOLUTIONS MANUAL: General Chemistry 9 Edition by Ebbings, Gammon SOLUTIONS MANUAL: General Chemistry, 8th Edition by Ralph H. Petrucci; Will= iam S. Harwood; Geoffrey Herring SOLUTIONS MANUAL: Geometry - A High School Course by S. Lang and G. Murrow SOLUTIONS MANUAL: Geometry ( Glencoe ) SOLUTIONS MANUAL: Geometry and Discrete Mathematics Addison Wesley SOLUTIONS MANUAL: Green Engineering - Environmentally Conscious Design of C= hemical Processes by Shonnard, Allen SOLUTIONS MANUAL: Guide to Energy Management, 6th Edition by Klaus Dieter E= . Pawlik SOLUTIONS MANUAL: Guide to Energy Management, Fifth Edition, Klaus-Dieter E= . Pawlik SOLUTIONS MANUAL: HARCOURT MATHEMATICS 12 Advanced Functions and Introducto= ry Calculus SOLUTIONS MANUAL: Harcourt Mathematics 12 Geometry and Discrete Mathematics SOLUTIONS MANUAL: Heat and Mass Transfer: A Practical Approach (3rd. Ed., C= engel)=20 SOLUTIONS MANUAL: Heat Transfer A Practical Approach ,Yunus A. Cengel 2d ed SOLUTIONS MANUAL: Heating, Ventilating and Air Conditioning Analysis and De= sign, 6th Edition McQuiston, Parker, Spitler SOLUTIONS MANUAL: Higher Algebra 3rd edition by Hall and Knight SOLUTIONS MANUAL: HIGH-SPEED NETWORKS AND INTERNETS 2 ED STALLINGS SOLUTIONS MANUAL: History of Mathematics: Brief Version (Victor J. Katz) SOLUTIONS MANUAL: Hydraulics in Civil and Environmental Engineering 4 E by = Chadwick , Morfett SOLUTIONS MANUAL: Hydraulics in Civil and Environmental Engineering 4th Ed = by Chadwick , Borthwick SOLUTIONS MANUAL: Industrial Organization Theory & Applications by Shy SOLUTIONS MANUAL: Intermediate Accounting - IFRS Edition Vol.1 by Kieso, We= ygandt, Warfield SOLUTIONS MANUAL: Intermediate Accounting 12th ed by Kieso SOLUTIONS MANUAL: Intermediate Accounting 13 ed by Kieso SOLUTIONS MANUAL: Intermediate Accounting 14 ed by Kieso SOLUTIONS MANUAL: INTERMEDIATE ACCOUNTING, 6th Edition, by Spiceland, Sepe SOLUTIONS MANUAL: Intermediate Algebra - Concepts & Applications 8th Ed by = Bittinger, Ellenbogen SOLUTIONS MANUAL: Introduction to Algorithms, 2nd Ed by Cormen, Leiserson= =20 SOLUTIONS MANUAL: Introduction to Applied Modern Physics by Henok Abebe SOLUTIONS MANUAL: Introduction to Chemical Engineering Thermodynamics (7th = Ed., Smith & Van Ness) SOLUTIONS MANUAL: Introduction to Commutative Algebra by M. F. Atiyah SOLUTIONS MANUAL: Introduction to Digital Signal Processing (in Serbian) by= Lj. Milic and Z. Dobrosavljevic SOLUTIONS MANUAL: Introduction to Econometrics (2nd ed., James H. Stock & M= ark W. Watson) SOLUTIONS MANUAL: Introduction to Electric Circuits 7th Edition by Dorf, Sv= aboda SOLUTIONS MANUAL: Introduction to Electric Circuits, 6E, Dorf SOLUTIONS MANUAL: Introduction to Electrodynamics (3rd Ed., David J. Griffi= ths) SOLUTIONS MANUAL: Introduction to Elementary Particles 2nd Ed by David Grif= fiths SOLUTIONS MANUAL: Introduction to Environmental Engineering and Science (3r= d Ed., Gilbert M. Masters & Wendell P. Ela) SOLUTIONS MANUAL: Introduction to Environmental Engineering and Science, Ed= ition 2, Masters SOLUTIONS MANUAL: Introduction to Ergonomics 2E by Robert Bridger SOLUTIONS MANUAL: Introduction to Flight 7th ED by John D. Anderson SOLUTIONS MANUAL: Introduction to Fluid Mechanics ( 7 E., Robert Fox, Alan = McDonald & Philip ) SOLUTIONS MANUAL: Introduction to Fluid Mechanics (6E., Robert Fox, Alan Mc= Donald & Philip) SOLUTIONS MANUAL: Introduction to fluid mechanics 5th edition by Alan T. Mc= Donald, Robert W Fox SOLUTIONS MANUAL: Introduction to Fourier Optics 3rd Ed by Joseph W. Goodma= n SOLUTIONS MANUAL: Introduction to Graph Theory 2E - West SOLUTIONS MANUAL: Introduction to Heat Transfer by Vedat S. Arpaci, Ahmet S= elamet, Shu-Hsin Kao SOLUTIONS MANUAL: Introduction to Hydrology 5th Edition by Warren Viessman= Jr., Gary L. Lewis SOLUTIONS MANUAL: Introduction to Java Programming, Comprehensive Version 7= th Ed by Liang SOLUTIONS MANUAL: Introduction to Linear Algebra, 3rd Ed., by Gilbert Stran= g SOLUTIONS MANUAL: Introduction to Linear Algebra, 4th Ed by Gilbert Strang SOLUTIONS MANUAL: Introduction to Management Accounting, 14 ED by Horngren,= Schatzberg SOLUTIONS MANUAL: Introduction to Materials Science for Engineers (6th Ed.,= Shackelford) SOLUTIONS MANUAL: Introduction to Materials Science for Engineers 7th E by = Shackelford SOLUTIONS MANUAL: Introduction to Mathematical Statistics (6th Ed., Hogg, C= raig & McKean) SOLUTIONS MANUAL: Introduction to Mechatronics and Measurements Systems 2nd= Ed by Alciatore, Histand SOLUTIONS MANUAL: Introduction to Mechatronics and Measurements Systems 3rd= Ed by Alciatore, Histand SOLUTIONS MANUAL: Introduction to Nuclear And Particle Physics 2nd E by Bro= mberg, Das, Ferbel SOLUTIONS MANUAL: Introduction to Operations Research - 7th ed by Frederick= Hillier, Gerald Lieberman SOLUTIONS MANUAL: Introduction to Probability 2nd Ed by Bertsekas and Tsits= iklis SOLUTIONS MANUAL: Introduction to Probability by Dimitri P. Bertsekas and J= ohn N. Tsitsiklis SOLUTIONS MANUAL: Introduction to Probability by Grinstead, Snell SOLUTIONS MANUAL: Introduction to Probability Models 10th Ed by M. Ross SOLUTIONS MANUAL: Introduction to Probability Models 9th Ed by M. Ross SOLUTIONS MANUAL: Introduction to Quantum Mechanics (2nd Ed., David J. Grif= fiths) SOLUTIONS MANUAL: Introduction to Quantum Mechanics 1st edition (1995) by D= avid J. Griffiths SOLUTIONS MANUAL: Introduction to Queueing Theory 2nd Edition by R.B. Coope= r SOLUTIONS MANUAL: Introduction to Scientific Computation and Programming, 1= st Edition by Daniel Kaplan SOLUTIONS MANUAL: Introduction to Signal Processing by S. J. Orfanidis SOLUTIONS MANUAL: Introduction to Signal Processing by Sophocles J. Orfanid= is SOLUTIONS MANUAL: Introduction to Solid State Physics 8th Ed by Kittel & Ch= arles SOLUTIONS MANUAL: Introduction to Statistical Physics by Kerson Huang SOLUTIONS MANUAL: Introduction to Statistical Physics by Silvio Salinas SOLUTIONS MANUAL: Introduction to Statistical Quality Control (4th Ed., Dou= glas C. Montgomery) SOLUTIONS MANUAL: Introduction to Statistical Quality Control (5th Ed., Dou= glas C. Montgomery) SOLUTIONS MANUAL: Introduction to the Theory of Computation by Ching Law SOLUTIONS MANUAL: Introduction to the Thermodynamics of Materials 3 E by Ga= skell SOLUTIONS MANUAL: Introduction to Thermal and Fluids Engineering by Kaminsk= i, Jensen SOLUTIONS MANUAL: Introduction to Thermal Systems Engineering Moran Shapiro= Munson SOLUTIONS MANUAL: Introduction to VLSI Circuits and Systems, by John P. Uye= mura SOLUTIONS MANUAL: Introduction to Wireless Systems by P.M Shankar SOLUTIONS MANUAL: Introductory Circuit Analysis 11 E by Boylestad SOLUTIONS MANUAL: Introductory Econometrics A Modern Approach, 3Ed by Jeff= rey Wooldridge SOLUTIONS MANUAL: Introductory Mathematical Analysis for Business, Economic= s and the Life and Social Sciences, 12th E By Haeussler,Paul,Wood SOLUTIONS MANUAL: Introductory Mathematical Analysis for Business, Economic= s, and the Life and Social Sciences, 13 E by Haeussler,Paul,Wood SOLUTIONS MANUAL: Introductory Quantum Optics (Christopher Gerry & Peter Kn= ight) SOLUTIONS MANUAL: Introdution to Accounting 3rd Ed by Marriott, Mellett SOLUTIONS MANUAL: Introdution to Solid State Physics, 8th Edition by Kittel= =20 SOLUTIONS MANUAL: Investment Analysis & Portfolio Management, 7e by Reilly,= Brown SOLUTIONS MANUAL: Investment Analysis and Portfolio Management 7th Edition = by Frank K. et al. Reilly SOLUTIONS MANUAL: Investments by Charles P. Jones SOLUTIONS MANUAL: IT Networking Labs by Cavaiani SOLUTIONS MANUAL: IT Networking Labs by Tom Cavaiani SOLUTIONS MANUAL: Java How to program 7th Ed by Deitel=20 SOLUTIONS MANUAL: Journey into Mathematics An Introduction to Proofs ,Jose= ph Rotman SOLUTIONS MANUAL: Kinematics, Dynamics, and Design of Machinery, 2nd Ed., W= aldron & Kinzel SOLUTIONS MANUAL: Kinetics of Catalytic Reactions by M. Albert Vannice SOLUTIONS MANUAL: LabVIEW for Engineers by Larsen SOLUTIONS MANUAL: Laser Fundamentals (2nd Ed., William T. Silfvast) SOLUTIONS MANUAL: Learning SAS in the Computer Lab 3rd ED by Elliott, Morre= ll SOLUTIONS MANUAL: Lectures on Corporate Finance 2006, 2 Ed by Bossaerts, Oe= degaard SOLUTIONS MANUAL: Linear Algebra - 2 Ed - Poole SOLUTIONS MANUAL: Linear Algebra and Its Applications 3rd ed by David C. La= y SOLUTIONS MANUAL: Linear Algebra Done Right, 2nd Ed by Sheldon Axler SOLUTIONS MANUAL: Linear Algebra with Applications (6th Ed., S. Leon) SOLUTIONS MANUAL: Linear Algebra with Applications 3rd Ed by Otto Bretscher SOLUTIONS MANUAL: Linear Algebra With Applications, 2nd Edition by W. Keith= Nicholson SOLUTIONS MANUAL: Linear Algebra, 4th Ed, by Stephen H. Friedberg , Arnold = J. Insel , Lawrence E. Spence =20 SOLUTIONS MANUAL: Linear Algebra, by J. Hefferon SOLUTIONS MANUAL: Linear Circuit Analysis Time Domain, Phasor and Laplace..= , 2nd Ed, Lin SOLUTIONS MANUAL: Linear Circuit Analysis, 2nd Ed by DeCarlo , Pen-Min Lin SOLUTIONS MANUAL: Linear dynamic systems and signals by Zoran Gajic SOLUTIONS MANUAL: Linear Systems And Signals, 1stE, B P Lathi SOLUTIONS MANUAL: Logic and Computer Design Fundamentals, 2E, by Morris Man= o and Charles Kime SOLUTIONS MANUAL: Logic and Computer Design Fundamentals, 3d edition by Mor= ris Mano and Charles Kime SOLUTIONS MANUAL: Logic and Computer Design Fundamentals, 4/E, by Morris Ma= no and Charles Kime=20 SOLUTIONS MANUAL: Machine Design : An Integrated Approach (3rd Ed., Norton) SOLUTIONS MANUAL: Machines and Mechanisms - Applied Kinematic Analysis, 3E = by David H. Myszka SOLUTIONS MANUAL: Macroeconomics A European Text 2nd Ed by Mertens, Weder SOLUTIONS MANUAL: Managerial Accounting 11th Ed by Garrison & Noreen SOLUTIONS MANUAL: Managerial Accounting 13th E by Garrison, Noreen, Brewer SOLUTIONS MANUAL: Managing Business and Professional Communication 2nd ed C= arley H. Dodd SOLUTIONS MANUAL: Managing Business Process Flows: Principles of Operations= Management(2nd Ed., Anupind, Chopra, Deshmukh, et al) SOLUTIONS MANUAL: Managing Engineering and Technology (4th, Morse & Babcock= ) SOLUTIONS MANUAL: Manufacturing Processes for Engineering Materials (5th Ed= . Kalpakjian & Smith) SOLUTIONS MANUAL: Materials - engineering, science, properties, and design SOLUTIONS MANUAL: Materials and Processes in Manufacturing (9th Ed., E. Pau= l DeGarmo, J. T. Black,Kohser) SOLUTIONS MANUAL: Materials- Engineering, Science, Processing and Design 2n= d ED by Ashby SOLUTIONS MANUAL: Materials for Civil and Construction Engineers 3rd ED by = Mamlouk, Zaniewski=20 SOLUTIONS MANUAL: Materials Science and Engineering- An Introduction ( 7th = Ed., William D. Callister, Jr.) SOLUTIONS MANUAL: Materials Science and Engineering- An Introduction (6th E= d., William D. Callister, Jr.) SOLUTIONS MANUAL: MATH 1010 - Applied Finite Mathematics - 2009 by D.W. Tri= m SOLUTIONS MANUAL: MATH 1010 - Applied Finite Mathematics by D.W. Trim SOLUTIONS MANUAL: Mathematical Analysis, Second Edition by Tom M. Apostol SOLUTIONS MANUAL: Mathematical Methods for Physicists 5 Ed, Arfken SOLUTIONS MANUAL: Mathematical Methods for Physics and Engineering, (3rd Ed= ., Riley,Hobson) SOLUTIONS MANUAL: Mathematical Methods in the Physical Sciences; 3 edition = by Mary L. Boas SOLUTIONS MANUAL: Mathematical Models in Biology An Introduction (Elizabeth= S. Allman & John A. Rhodes) SOLUTIONS MANUAL: Mathematical Proofs - A Transition to Advanced Mathematic= s 2nd Ed by Chartrand, Polimeni, Zhang SOLUTIONS MANUAL: Mathematical Techniques 4th ED by D W Jordan & P Smith SOLUTIONS MANUAL: Mathematics for Economists, by Carl P. Simon , Lawrence E= . Blume SOLUTIONS MANUAL: Mathematics for Management Science - A Bridging Course by= Tulett SOLUTIONS MANUAL: Mathematics for Physicists by Susan Lea SOLUTIONS MANUAL: Matrix Analysis and Applied Linear Algebra by Meyer SOLUTIONS MANUAL: Matter and Interactions, 3rd Ed VOL 1 by Chabay, Sherwood SOLUTIONS MANUAL: Matter and Interactions, 3rd Ed VOL 2 by Chabay, Sherwood SOLUTIONS MANUAL: McGraw-Hill Ryerson Calculus & Advanced Function by Dearl= ing, Erdman, et all SOLUTIONS MANUAL: Mechanical Behavior of Materials 3rd Ed by Norman E. Dowl= ing SOLUTIONS MANUAL: Mechanical Engineering Design 8th Ed by Shigley & Budynas SOLUTIONS MANUAL: Mechanical Engineering Design 9th Ed by Shigley & Budynas SOLUTIONS MANUAL: Mechanical Engineering Design, 7th Ed. by Mischke, Shigle= y SOLUTIONS MANUAL: Mechanical Measurements (6th Ed., Beckwith, Marangoni & L= ienhard) SOLUTIONS MANUAL: Mechanical Vibrations (3rd Ed., Rao) SOLUTIONS MANUAL: Mechanical Vibrations 4th Ed SI Units by Rao SOLUTIONS MANUAL: Mechanics of Aircraft Structures, 2nd Ed by Sun SOLUTIONS MANUAL: Mechanics of Fluids (8th Ed., Massey)=20 SOLUTIONS MANUAL: Mechanics of Fluids 3rd ED Vol 1 by Merle C. Potter SOLUTIONS MANUAL: Mechanics of Fluids 4th ED by I.H. Shames SOLUTIONS MANUAL: Mechanics of Materials 5 edition by James M. Gere SOLUTIONS MANUAL: Mechanics of Materials (6th Ed., Riley, Sturges & Morris) SOLUTIONS MANUAL: Mechanics of Materials 4 E by Russell C. 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Varian SOLUTIONS MANUAL: Microeconomic Theory Basic Principles and Extensions 9E (= South-Western ) by Walter Nicholson SOLUTIONS MANUAL: Microeconomic Theory by Segal Tadelis Hara Chiaka Hara St= eve Tadelis SOLUTIONS MANUAL: Microeconomic Theory, by Mas-Colell, Whinston, Green SOLUTIONS MANUAL: Microeconomics, 6th Ed by Pyndick, Rubinfeld SOLUTIONS MANUAL: Microelectronic Circuit Analysis and Design, 3rd Edition,= by D. Neamen SOLUTIONS MANUAL: Microelectronic Circuit Design (3rd Ed., Richard Jaeger &= Travis Blalock) SOLUTIONS MANUAL: Microelectronic Circuit Design 4th ED by Jaeger, Blalock SOLUTIONS MANUAL: Microelectronic Circuits By Adel Sedra 5th Edition=20 SOLUTIONS MANUAL: Microelectronic Circuits, 4th Ed. by Sedra and Smith SOLUTIONS MANUAL: Microelectronic Circuits, 5th Ed. by Sedra and Smith SOLUTIONS MANUAL: Microelectronics Digital and Analog Circuits and Systems = by Millman SOLUTIONS MANUAL: Microelectronics I & II by Dr.Chang SOLUTIONS MANUAL: Microelectronics,Solution MANUAL,5thEd,MAZ SOLUTIONS MANUAL: Microprocessors and Interfacing, Revised 2nd Edition by D= ouglas V Hall SOLUTIONS MANUAL: Microwave and Rf Design of Wireless Systems, 1st Edition,= by Pozar SOLUTIONS MANUAL: Microwave Engineering, 2nd Ed., by David M. Pozar SOLUTIONS MANUAL: Microwave Engineering, 3rd Ed., by David M. Pozar SOLUTIONS MANUAL: Microwave Transistor Amplifiers Analysis and Design, 2nd = Ed., by Guillermo Gonzalez SOLUTIONS MANUAL: Mobile Communications 2nd ed by Jochen Schiller SOLUTIONS MANUAL: Modern Control Engineering 3rd Ed. - K. OGATA SOLUTIONS MANUAL: Modern Control Engineering 4th Ed. - K. OGATA SOLUTIONS MANUAL: Modern Control Engineering 5 Ed. - K. OGATA SOLUTIONS MANUAL: Modern Control Systems 11E by Richard C Dorf and Robert H= . Bishop SOLUTIONS MANUAL: Modern Control Systems 9 E by Richard C Dorf and Robert H= . Bishop SOLUTIONS MANUAL: Modern Control Systems, 12th Ed by Dorf, Bishop SOLUTIONS MANUAL: Modern Digital and Analog Communication Systems, 3rd Ed.,= by Lathi SOLUTIONS MANUAL: Modern Digital Electronics 3 Ed by R P Jain SOLUTIONS MANUAL: Modern Digital Electronics,3E by R P JAIN SOLUTIONS MANUAL: Modern Digital Signal Processing-Roberto Cristi SOLUTIONS MANUAL: MODERN OPERATING SYSTEMS 2nd ed A.S.TANENBAUM SOLUTIONS MANUAL: Modern Organic Synthesis An Introduction by George Zweife= l, Michael Nantz SOLUTIONS MANUAL: Modern Physics 2nd E by Randy Harris SOLUTIONS MANUAL: Modern Physics 4th ed by Mark Llewellyn SOLUTIONS MANUAL: Modern Physics 4th ed by Tipler, Llewellyn SOLUTIONS MANUAL: Modern Physics for Scientists and Engineers 3rd E by Thor= nton and Rex SOLUTIONS MANUAL: Modern Portfolio Theory and Investment Analysis, 7th Ed b= y Gruber,Goetzmann SOLUTIONS MANUAL: MODERN POWER SYSTEM ANALYSIS 3rd E by Kothari,Nagrath SOLUTIONS MANUAL: Modern Quantum Mechanics (Revised Edition) by J. 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Beer) SOLUTIONS MANUAL: Vector Mechanics for Engineers Dynamics (7th Ed., Ferdina= nd P. Beer) SOLUTIONS MANUAL: Vector Mechanics for Engineers Dynamics (8th Ed., Ferdina= nd P. Beer) SOLUTIONS MANUAL: Vector Mechanics for Engineers Statics (7th Ed., Ferdina= nd P. Beer) SOLUTIONS MANUAL: Vector Mechanics for Engineers Statics (8th Ed., Ferdina= nd P. Beer) SOLUTIONS MANUAL: Vector Mechanics for Engineers Statics & Dynamics (6th Ed= ., Ferdinand P. Beer) SOLUTIONS MANUAL: VHDL for Engineers - International Edition by Kenneth L.= Short SOLUTIONS MANUAL: Water and Wastewater Technology 7th E by Hammer SOLUTIONS MANUAL: WIRELESS COMMUNICATIONS AND NETWORKS 2nd E by Stallings From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Resolution func in the initialization Date: Mon, 13 Jan 2014 21:41:29 +0200 Organization: A noiseless patient Spider Lines: 49 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 13 Jan 2014 19:41:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13275"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18mUrXTH+d4657cgXuSbri1T40ywdfEk/8=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 Cancel-Lock: sha1:WNmxjt6/oVT+QzGjGlvaCFYGVEQ= Xref: news.eternal-september.org comp.lang.vhdl:7231 --- begin code --- architecture ARCH of TOP is type int_vector is array (integer range<>) of integer; function driver_counter( values : int_vector ) return integer is variable result : integer := 0; variable l: line; begin for index in values'range loop if values(index) /= 0 then result := result + 1; write (l, integer'image(values(index)) & ","); end if; end loop; report l.all & " count resolved => " & integer'image(result); return result; end function; signal S1: driver_counter integer := 6; begin -- s1 <= 1; end architecture; -- end code --- In Modelsim, the driver_counter does not print any reports, which means that resolution is not executed on S1, despite it is resolved and Ashenden says --- begin quote --- The resolution function for a resolved signal is also invoked to initialize the signal. At the start of a simulation, the drivers for the signal are initialized to the expression included in the signal declaration, or to the default initial value for the signal type if no initialization expression is given. The resolution function is then invoked using these driver values to determine the initial value for the signal. In this way, the signal always has a properly resolved value, right from the start of the simulation. --- end quote --- If, however, I uncomment the last line, assignment s1 <= 1, the driver_counter is executed twice, reporting that there is only one driver. Is everything ok? Why the resolution is not invoked when drivers are disconnected? From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.144.41 with SMTP id sj9mr11725946pab.23.1389666524456; Mon, 13 Jan 2014 18:28:44 -0800 (PST) X-Received: by 10.50.152.41 with SMTP id uv9mr10810igb.13.1389666524356; Mon, 13 Jan 2014 18:28:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!a5no9868600pbg.1!news-out.google.com!gg4ni1657qab.0!nntp.google.com!6no9090765qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 Jan 2014 18:28:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.217; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.217 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> Subject: Re: Resolution func in the initialization From: Dio Gratia Injection-Date: Tue, 14 Jan 2014 02:28:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7232 The resolution function calls are caused by transactions on drivers. No drivers, no transactions. I added std.textio in a use clause, an entity declaration for top with no p= orts. The only way I know of to get two resolution function calls would be to hav= e S1 be evaluated in an expression after it's active (and the default value= causes a transaction, followed by the 0 time concurrent signal assignment)= : signal S1: driver_counter integer :=3D 6; signal S2: driver_counter integer :=3D 0; begin -- s1 <=3D 1 ; =20 CONC_SIGNAL_ASSIGN_EQUIV: process=20 begin s1 <=3D 1; wait; -- only a static expression on the right hand side, execut= es once. end process; =20 s2 <=3D s1; ghdl -r top top.vhdl:19:17:@0ms:(report note): 6, count resolved =3D> 1 top.vhdl:19:17:@0ms:(report note): 1, count resolved =3D> 1 top.vhdl:19:17:@0ms:(report note): 1, count resolved =3D> 1 The first one is for S2 following the default value assignment to S1, the = second one is S1 assigned 1, the third one is for S2 being assigned S1 aft= er an S1 transaction. Otherwise there should be only one transaction during a simulation cycle, a= nd without S1 appearing on the right hand side of an assignment (or in a se= nsitivity list) there would be only one time 0 delta cycle (and one transac= tion on S1, to 1). It sounds like Modelsim is doing something you've managed to catch them out= at that wouldn't otherwise matter (an extra delta cycle just for default v= alues), or what you've presented as the behavior isn't complete. With your = architecture unmodified ghdl only reports one invocation of the resolution = function. (One transaction for one simulation cycle at time 0, the resolve= d driver value of 1): =20 ghdl -r top top.vhdl:19:17:@0ms:(report note): 1, count resolved =3D> 1 See IEEE Std 1076-1993, 12.4.4 (Elaboration) Other concurrent statements, 12.6.1 Drivers (Execution of a model) Drivers, and 12.6.2 (Execution of a = model) Propagation of signal values. (Or equivalent sections in -2008, -20= 02 should match -1993). This was done with ghdl-0.31 date stamped 20140108, gcc version. From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Richard Nicholas Newsgroups: comp.lang.vhdl Subject: Re: or_reduce for array of std_ulogic_vectors REVISITED Date: Mon, 13 Jan 2014 21:45:17 -0600 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <8fb24f43-4c46-48a4-bec5-b0bcc3411ef2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="4ab8a032b4437ca4bf56b1f2fcdd427c"; logging-data="10013"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PNZ/5LycBdX5+gR38R2BtXq6OpKIwJMA=" User-Agent: MicroPlanet-Gravity/3.0.4 Cancel-Lock: sha1:YGecqe1RrS62/G/0tOwZYEvbL8U= Xref: news.eternal-september.org comp.lang.vhdl:7233 In article , kkjennings@sbcglobal.net says... > The posted code below compiles and might actually perform the intended function. > If not, it should provide a decent starting point. Kevin, just wanted to let you know I have tried your version of the function and its working great! Thanks so much! Richard Nicholas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.221.137 with SMTP id qe9mr194511pac.4.1389691033042; Tue, 14 Jan 2014 01:17:13 -0800 (PST) X-Received: by 10.49.82.45 with SMTP id f13mr8908qey.20.1389691032989; Tue, 14 Jan 2014 01:17:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!a5no9992789pbg.1!news-out.google.com!gg4ni2493qab.0!nntp.google.com!p15no13840222qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 01:17:12 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.235.91.29; posting-account=pErCnAkAAAAJKh2FbBHXtHBH6otZFfEB NNTP-Posting-Host: 212.235.91.29 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL design flatten compilation From: ronhk25 Injection-Date: Tue, 14 Jan 2014 09:17:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7234 Hi all, I have a hierarchical vhdl design, i would like to remove all the hierarchi= es during the design compilation ("flatten compilation"). My purpose is to import this flattened compiled design into a multiple FPGA= s simulation environment in order to prevent duplicate name conflicts durin= g the environment compilation and elaboration. I'm not sure that "flatten compilation" is the accurate terminology but a g= ood example might be an importing of a third party IP core from FPGA vendor= , when i import a FIFO (for example) from Altera of Xilinx all i need is a = VHD wrapper file that points to only one vendor compiled library which is m= apped to my project (no need to import the whole hierarchical design). I would like to import my compiled design into my simulation environment in= the same way, does someone know how to do that? p.s. I tried to import the design as a gate level technology dependent flat= file (VHO file) but the result was a very slow simulation so i would be ha= ppy to learn about a better solution... Thanks, Ron From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.50.154.73 with SMTP id vm9mr883973igb.2.1389692719867; Tue, 14 Jan 2014 01:45:19 -0800 (PST) X-Received: by 10.49.16.168 with SMTP id h8mr11852qed.2.1389692719837; Tue, 14 Jan 2014 01:45:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no13874427qaj.0!news-out.google.com!gg4ni1657qab.0!nntp.google.com!6no9531963qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 01:45:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a7b96c0-7fd0-4951-9ea2-0e008ec81fa2@googlegroups.com> Subject: Re: VHDL design flatten compilation From: Thomas Stanka Injection-Date: Tue, 14 Jan 2014 09:45:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2499 X-Received-Body-CRC: 2137980038 Xref: news.eternal-september.org comp.lang.vhdl:7235 Am Dienstag, 14. Januar 2014 10:17:12 UTC+1 schrieb ronhk25: > My purpose is to import this flattened compiled design into a multiple FP= GAs simulation environment in order to prevent duplicate name conflicts dur= ing the environment compilation and elaboration. I understand you assume, that you avoid name conflicts between several desi= gns when importing each design as "flat netlist" instead of hierarchical de= sign. A flat netlist really requires to synthesis flat and simulate netlists, whi= ch is a pain, when doing a simulation containing several complex designs.= =20 The solution to this problem is to use dedicated libraries instead of compi= ling all into library work. Configurations allow you to be specific about w= hat architecture should be used in which location. Eg. you have design1 and design2 with both using an entity "rxif", you can = configure design1 to use design1_lib.rxif and design2 to use design2_lib.rx= if. This mechanism allows you to haven even several different entities of same = name in design, if you use eg. uart_lib and pci_lib for different ipcores f= or uart and pci. You have an initial overhead when configuring all vhdl cod= e, but in the end it solves a lot of naming problems and is the only possib= ilty in complex code reuse.=20 regards Thomas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.52.119.212 with SMTP id kw20mr2495696vdb.8.1389698759267; Tue, 14 Jan 2014 03:25:59 -0800 (PST) X-Received: by 10.49.50.3 with SMTP id y3mr19556qen.0.1389698759242; Tue, 14 Jan 2014 03:25:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!p15no14007748qaj.0!news-out.google.com!gg4ni1657qab.0!nntp.google.com!6no9654450qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 03:25:59 -0800 (PST) In-Reply-To: <6a7b96c0-7fd0-4951-9ea2-0e008ec81fa2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.235.91.29; posting-account=pErCnAkAAAAJKh2FbBHXtHBH6otZFfEB NNTP-Posting-Host: 212.235.91.29 References: <6a7b96c0-7fd0-4951-9ea2-0e008ec81fa2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04f74906-94f3-489e-90a4-cc092fbb4dc7@googlegroups.com> Subject: Re: VHDL design flatten compilation From: ronhk25 Injection-Date: Tue, 14 Jan 2014 11:25:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7236 Thomas,=20 I understand that this solution will solve conflicts during the compilation= but won't it be problematic during the elaboration? Does the simulator "kn= ows" to search for the compiled entity in the correct library and bind it c= orrectly? Are you sure that it won't just bind the first compiled entity wi= th the searched name? Regarding the flat netlist, do you mean that there is no way to create a te= chnology independent flat netlist/compiled file? Thank you for your help! Ron From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.66.158.6 with SMTP id wq6mr368599pab.39.1389700457155; Tue, 14 Jan 2014 03:54:17 -0800 (PST) X-Received: by 10.182.118.170 with SMTP id kn10mr5768obb.20.1389700456943; Tue, 14 Jan 2014 03:54:16 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!usenet-its.stanford.edu!usenet.stanford.edu!kk17no9189552pbb.0!news-out.google.com!gg4ni2493qab.0!nntp.google.com!p15no14043737qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 03:54:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a22a1c5-de02-47a5-8d0b-9bfbc5265915@googlegroups.com> Subject: Re: VHDL design flatten compilation From: KJ Injection-Date: Tue, 14 Jan 2014 11:54:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7237 On Tuesday, January 14, 2014 4:17:12 AM UTC-5, ronhk25 wrote: >=20 > I have a hierarchical vhdl design, i would like to remove all the hierarc= hies during the design compilation ("flatten compilation"). >=20 > My purpose is to import this flattened compiled design into a multiple FP= GAs simulation environment in order to prevent duplicate name conflicts dur= ing the environment compilation and elaboration. >=20 What sort of 'duplicate name conflicts' are you talking about? Elaborate a= bit on what you are actually trying to do and what problem you are actuall= y having. > I'm not sure that "flatten compilation" is the accurate terminology but a= =20 > good example might be an importing of a third party IP core from FPGA ven= dor,=20 > when i import a FIFO (for example) from Altera of Xilinx all i need is a = VHD=20 > wrapper file that points to only one vendor compiled library which is map= ped=20 > to my project (no need to import the whole hierarchical design). In what way is what you are trying to do then any different than this examp= le with the FIFO? There is nothing inherently special about a third party = IP core, when you instantiate multiples of your own hand written entity it = works the exact same way. >=20 > I would like to import my compiled design into my simulation environment = in=20 > the same way, does someone know how to do that? >=20 You don't "import" designs into VHDL. Within an architecture, you instanti= ate entities. All of those entities and the architectures for those entiti= es must exist in the library (typically 'work') or you won't sim. There is= nothing special that is being done for third party IP that you think you a= re "importing". Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.58.190.68 with SMTP id go4mr11853889vec.7.1389705448750; Tue, 14 Jan 2014 05:17:28 -0800 (PST) X-Received: by 10.49.48.105 with SMTP id k9mr25795qen.1.1389705448732; Tue, 14 Jan 2014 05:17:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!6no9799792qao.1!news-out.google.com!gg4ni2493qab.0!nntp.google.com!p15no14145867qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 05:17:28 -0800 (PST) In-Reply-To: <0a22a1c5-de02-47a5-8d0b-9bfbc5265915@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.235.91.29; posting-account=pErCnAkAAAAJKh2FbBHXtHBH6otZFfEB NNTP-Posting-Host: 212.235.91.29 References: <0a22a1c5-de02-47a5-8d0b-9bfbc5265915@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ab00c70-dfd5-417f-ac4d-11bde24a7afc@googlegroups.com> Subject: Re: VHDL design flatten compilation From: ronhk25 Injection-Date: Tue, 14 Jan 2014 13:17:28 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7238 =D7=91=D7=AA=D7=90=D7=A8=D7=99=D7=9A =D7=99=D7=95=D7=9D =D7=A9=D7=9C=D7=99= =D7=A9=D7=99, 14 =D7=91=D7=99=D7=A0=D7=95=D7=90=D7=A8 2014 13:54:16 UTC+2, = =D7=9E=D7=90=D7=AA KJ: Kevin, > What sort of 'duplicate name conflicts' are you talking about? Elaborate= a bit on what you are actually trying to do and what problem you are actua= lly having.>=20 I will try to clarify this- Lets assume that i have a hierarchical design, = in one of the hierarchies I have an entity which is called "Counter". Now i= would like to simulate my design and i want to buy from you a simulation m= odel of some component, your simulation model is also hierarchical and cont= ains entity which is also called "Counter". Now I have in my simulation env= ironment two different entities with the same name- "Counter", that's what = I call a "duplicate name conflicts". > In what way is what you are trying to do then any different than this exa= mple with the FIFO? There is nothing inherently special about a third part= y IP core, when you instantiate multiples of your own hand written entity i= t works the exact same way. >=20 In the example with the FIFO i have to add into my design a wrapper vhd fil= e which points to a vendor library (e.g. altera_mf if the FIFO was generate= d in Quatus MegaWizard) which is mapped to my project. In altera_mf there i= s a folder with the compiled files of that component (e.g. dcfifo). Now, i = don't know if the designer of this dcfifo component designed it as a flat o= r hierarchical design and if he instantiated an entity called "counter". Th= e nice thing is that i also don't have to worry about it because all i need= is the wrapper file and the dcfifo folder with the compiled files. Now back to my first example, if you would like to send me a vhdl simulatio= n model of a component (a fifo for examole :)), that you designed by instan= tiating 50 different entities into one top file. Would you send me all the = 50 folders (each one of them contains compiled files of one entity) that yo= u have in your "work" directory? in this way if you have an entity called "= counter" you will send me a folder called "counter" and then we go back to = the duplicate name conflict... it seems to be more reasonable that you will= have the ability to remove all the hierarchies by flatten compilation into= one and only one folder, exactly like the FIFO example. The thing is that = i don't know how to do that and if its possible. =20 From newsfish@newsfish Tue Dec 29 16:43:16 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Tue, 14 Jan 2014 17:01:08 +0200 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jan 2014 15:01:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="14745"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18WAND609Oop1YNanNkkvo4RvfVb+O5bKA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> Cancel-Lock: sha1:KlmAiW6zIk9qmekcFywzJmPvGPc= Xref: news.eternal-september.org comp.lang.vhdl:7239 Wait, I do not understand. Is Modelsim wrong generating a transaction with single assignment S1 <= 1 but no S2 <= 1? I expected to catch the modelsim on the resolution invocation even without a transaction. I do not understand why do you refer me to the IEEE sections. Do you mean that Ashenden is wrong or not absolutely certain in the cited quote? On 14.01.2014 4:28, Dio Gratia wrote: > The resolution function calls are caused by transactions on drivers. > > No drivers, no transactions. > > I added std.textio in a use clause, an entity declaration for top with no ports. > > The only way I know of to get two resolution function calls would be to have S1 be evaluated in an expression after it's active (and the default value causes a transaction, followed by the 0 time concurrent signal assignment): > > signal S1: driver_counter integer := 6; > signal S2: driver_counter integer := 0; > > begin > -- s1 <= 1 ; > > CONC_SIGNAL_ASSIGN_EQUIV: > process > begin > s1 <= 1; > wait; -- only a static expression on the right hand side, executes once. > end process; > s2 <= s1; > > ghdl -r top > top.vhdl:19:17:@0ms:(report note): 6, count resolved => 1 > top.vhdl:19:17:@0ms:(report note): 1, count resolved => 1 > top.vhdl:19:17:@0ms:(report note): 1, count resolved => 1 > > The first one is for S2 following the default value assignment to S1, the second one is S1 assigned 1, the third one is for S2 being assigned S1 after an S1 transaction. > > Otherwise there should be only one transaction during a simulation cycle, and without S1 appearing on the right hand side of an assignment (or in a sensitivity list) there would be only one time 0 delta cycle (and one transaction on S1, to 1). > > It sounds like Modelsim is doing something you've managed to catch them out at that wouldn't otherwise matter (an extra delta cycle just for default values), or what you've presented as the behavior isn't complete. With your architecture unmodified ghdl only reports one invocation of the resolution function. (One transaction for one simulation cycle at time 0, the resolved driver value of 1): > > ghdl -r top > top.vhdl:19:17:@0ms:(report note): 1, count resolved => 1 > > See IEEE Std 1076-1993, 12.4.4 (Elaboration) Other concurrent statements, > 12.6.1 Drivers (Execution of a model) Drivers, and 12.6.2 (Execution of a model) Propagation of signal values. (Or equivalent sections in -2008, -2002 should match -1993). > > This was done with ghdl-0.31 date stamped 20140108, gcc version. > From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.50.18.4 with SMTP id s4mr1435261igd.5.1389713640733; Tue, 14 Jan 2014 07:34:00 -0800 (PST) X-Received: by 10.49.13.225 with SMTP id k1mr39757qec.16.1389713640700; Tue, 14 Jan 2014 07:34:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no14329969qaj.0!news-out.google.com!gg4ni2493qab.0!nntp.google.com!p15no14329966qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 07:34:00 -0800 (PST) In-Reply-To: <04f74906-94f3-489e-90a4-cc092fbb4dc7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <6a7b96c0-7fd0-4951-9ea2-0e008ec81fa2@googlegroups.com> <04f74906-94f3-489e-90a4-cc092fbb4dc7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60b8ed7f-7bf2-498a-a00c-3637f945e65d@googlegroups.com> Subject: Re: VHDL design flatten compilation From: Thomas Stanka Injection-Date: Tue, 14 Jan 2014 15:34:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2203 X-Received-Body-CRC: 4243170436 Xref: news.eternal-september.org comp.lang.vhdl:7240 Am Dienstag, 14. Januar 2014 12:25:59 UTC+1 schrieb ronhk25: > I understand that this solution will solve conflicts during the compilati= on but won't it be problematic during the elaboration? Does the simulator "= knows" to search for the compiled entity in the correct library and bind it= correctly? Are you sure that it won't just bind the first compiled entity = with the searched name? If you have a configured design, there exist no problems in any stage. The = simulator uses exact the entity-architecture(-configuration) you tell him t= o use in configuration. That is one of the real strong points in VHDL.=20 =20 > Regarding the flat netlist, do you mean that there is no way to create a = technology independent flat netlist/compiled file? There is no real benefit in simulation time between netlist that is vendor = dependent and netlist that is vendor independant. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:16 2015 X-Received: by 10.52.159.99 with SMTP id xb3mr419744vdb.4.1389741791848; Tue, 14 Jan 2014 15:23:11 -0800 (PST) X-Received: by 10.182.130.169 with SMTP id of9mr37514obb.26.1389741791775; Tue, 14 Jan 2014 15:23:11 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!6no10701702qao.1!news-out.google.com!gg4ni2779qab.0!nntp.google.com!6no10701697qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 15:23:11 -0800 (PST) In-Reply-To: <8ab00c70-dfd5-417f-ac4d-11bde24a7afc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <0a22a1c5-de02-47a5-8d0b-9bfbc5265915@googlegroups.com> <8ab00c70-dfd5-417f-ac4d-11bde24a7afc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <335f972a-128b-4a7d-8ae9-d56ad378e903@googlegroups.com> Subject: Re: VHDL design flatten compilation From: Andy Injection-Date: Tue, 14 Jan 2014 23:23:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3368 X-Received-Body-CRC: 4078840655 Xref: news.eternal-september.org comp.lang.vhdl:7241 The entity name-space (actually the signature name-space) in VHDL is the li= brary. If you have multiple counter entities with the same signature (inclu= ding number and types of ports/generics, and names of them if named associa= tion is used in the instantiation), then they must be compiled into (and in= stantiated from) separate libraries. You specify the library by prefixing t= he entity name with the library name. The same holds for packages. "Work" is a predifined alias for the library into which the unit is being, = or was, compiled. So if, in one entity/architecture, I instantiate "entity = work.mycomp", then mycomp is expected to be compiled into the same library = as the instantiating entity/architecture.=20 Using "work" library prefix helps keep library naming independent of physic= al libraries until they are actually compiled into the library. Always use = "work.whatever" when instantiating an entity (or using a package) from the = same library. Use "lib_name.whatever" when instantiating an entity (or usin= g a package) from a different library. This allows you to choose the actual= name of the library only when you actually compile things into it. And som= eone else that needs to use the same body of code can compile it into a dif= ferenly named library in their environment, in case they already had a libr= ary named the same. Just to be clear, simulators don't compile HDL into netlists, synthesis too= ls do that. The synthesis tool may also create an HDL model of the synthesi= zed netlist. Place and route tools may also create an HDL model of the post= -place & route netlist, back annotated with actual routing-induced timing d= elays. Simulators compile HDL into an executable. There is a huge performan= ce difference (wall-clock time) between a simulation of an RTL model and a = netlist model (an hdl model that only instantiates primitives, as generated= from the synthesis or P&R tool). The RTL model will generally be MUCH fast= er to simulate (in wall-clock time, not the clock speed of the simulated ci= rcuit). Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.66.136.166 with SMTP id qb6mr1555147pab.44.1389742081309; Tue, 14 Jan 2014 15:28:01 -0800 (PST) X-Received: by 10.50.239.132 with SMTP id vs4mr112161igc.4.1389742081062; Tue, 14 Jan 2014 15:28:01 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!kk17no9502974pbb.0!news-out.google.com!fv6ni3230qab.1!nntp.google.com!p15no15055198qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 15:28:00 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.217; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.217 References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Resolution func in the initialization From: Dio Gratia Injection-Date: Tue, 14 Jan 2014 23:28:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7242 On Wednesday, January 15, 2014 4:01:08 AM UTC+13, valtih1978 wrote: > Wait, I do not understand. > > I can short circuit all this by stating my understanding was flawed (the standard is a bit big to hold entirely in your head). I did an email exchange with Tristan Gingold the author of ghdl overnight and he demonstrated fairly conclusively ghdl should have reported two resolution function calls: > Looks like this following patch fixes the issue: > > --- a/translate/grt/grt-signals.adb Tue Jan 14 04:28:23 2014 +0100 > +++ b/translate/grt/grt-signals.adb Tue Jan 14 16:50:52 2014 +0100 > @@ -3257,7 +3257,7 @@ > > when Net_One_Resolved => > Sig.Has_Active := True; > - if Sig.Nbr_Ports > 0 then > + if Sig.S.Nbr_Drivers + Sig.Nbr_Ports > 0 then > Compute_Resolved_Signal (Sig.S.Resolv); > Sig.Value := Sig.Driving_Value; > end if; > > > I now get: > > $ ghdl_mcode -c driver1.vhdl -r top > driver1.vhdl:18:5:@0ms:(report note): 6, count resolved => 1 > driver1.vhdl:18:5:@0ms:(report note): 1, count resolved => 1 He found there was a missing resolution function call during the initial transaction in procedure Init_Signals (in grt-signals.adb) ignoring drivers for a resolved signal unless they were ports. It would appear Modelsim is indeed correct reporting two resolution function call occurrences. (The fix will show up in in ghdl-0.32, and it would appear it takes multiple drivers or a resolution function that reports like driver_counter in top.vhdl to show the problem. You've contributed indirectly to making ghdl a better VHDL tool.) From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.66.246.194 with SMTP id xy2mr1613338pac.36.1389742343742; Tue, 14 Jan 2014 15:32:23 -0800 (PST) X-Received: by 10.182.44.198 with SMTP id g6mr377obm.35.1389742343400; Tue, 14 Jan 2014 15:32:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!a5no10359554pbg.1!news-out.google.com!gg4ni2779qab.0!nntp.google.com!6no10713843qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 14 Jan 2014 15:32:23 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> Subject: Re: Resolution func in the initialization From: Andy Injection-Date: Tue, 14 Jan 2014 23:32:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7243 Many simulators will not call the resolution function if there is only one driver for a signal in the model. There are probably simulator settings to disable that optimization. Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.42.22.206 with SMTP id p14mr427332icb.18.1389779096921; Wed, 15 Jan 2014 01:44:56 -0800 (PST) X-Received: by 10.49.71.76 with SMTP id s12mr9604qeu.30.1389779096811; Wed, 15 Jan 2014 01:44:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no11308271qao.1!news-out.google.com!gg4ni4085qab.0!nntp.google.com!6no11308255qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 01:44:56 -0800 (PST) In-Reply-To: <335f972a-128b-4a7d-8ae9-d56ad378e903@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.235.91.29; posting-account=pErCnAkAAAAJKh2FbBHXtHBH6otZFfEB NNTP-Posting-Host: 212.235.91.29 References: <0a22a1c5-de02-47a5-8d0b-9bfbc5265915@googlegroups.com> <8ab00c70-dfd5-417f-ac4d-11bde24a7afc@googlegroups.com> <335f972a-128b-4a7d-8ae9-d56ad378e903@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9703ec37-6564-41eb-b07e-c37a82d20419@googlegroups.com> Subject: Re: VHDL design flatten compilation From: ronhk25 Injection-Date: Wed, 15 Jan 2014 09:44:56 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Xref: news.eternal-september.org comp.lang.vhdl:7244 15HXqteQ16jXmdeaINeZ15XXnSDXqNeR15nXoteZLCAxNSDXkdeZ16DXldeQ16ggMjAxNCANCg0K VGhhbmsgeW91IEFuZHksIHRoaXMgZXhwbGFuYXRpb24gd2FzIHZlcnkgaGVscGZ1bCENCg0KUm9u From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 13:08:54 +0200 Organization: A noiseless patient Spider Lines: 2 Message-ID: <52D66C46.10501@not.email.me> References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="9790"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18uedyWi7gOAx1n5cLcJk5odlnwWM3bFIk=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> Cancel-Lock: sha1:VU9+kQneMsqxwpnDVHwbz2wzlQY= Xref: news.eternal-september.org comp.lang.vhdl:7245 My question was about "specified behaviour in case of no drivers". Can I remind you about that? From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 13:09:15 +0200 Organization: A noiseless patient Spider Lines: 2 Message-ID: References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jan 2014 11:09:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="9882"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1896vJmnoFFYhFHzP52tA0Q3xPvS0ad+xM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> Cancel-Lock: sha1:5Tdlqta19zbIiCQOEjZ1R6NeIFg= Xref: news.eternal-september.org comp.lang.vhdl:7246 My question was about "specified behaviour in case of no drivers". Can I remind you about that? From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.125.79 with SMTP id y55mr947281yhh.53.1389805674098; Wed, 15 Jan 2014 09:07:54 -0800 (PST) X-Received: by 10.182.47.161 with SMTP id e1mr29737obn.24.1389805674040; Wed, 15 Jan 2014 09:07:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!6no11845833qao.1!news-out.google.com!fv6ni3477qab.1!nntp.google.com!p15no16198344qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 09:07:53 -0800 (PST) In-Reply-To: <52D66C46.10501@not.email.me> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> <52D66C46.10501@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Resolution func in the initialization From: Andy Injection-Date: Wed, 15 Jan 2014 17:07:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3411 X-Received-Body-CRC: 2215210252 Xref: news.eternal-september.org comp.lang.vhdl:7247 On Wednesday, January 15, 2014 5:08:54 AM UTC-6, valtih1978 wrote: > My question was about "specified behaviour in case of no drivers". Can I > remind you about that? Have you contacted Modelsim about this? If so, what did they say? While Ashenden is a recognized expert in VHDL, and IINM actually wrote part= of the LRM, the LRM is the authoratative definition of the language, not A= shenden. Modelsim should follow the LRM, not Ashenden, if the two conflict.= Therefore, we generally refer to the LRM when trying to figure out how a V= HDL simulator should behave. My speculation (since I am only a user of Modelsim, that's all it is, specu= lation) is that with no drivers, there is no reason to call a resolution fu= nction. With what argument would it be called, a null vector? Given that your resolution function changes the value even if only one driv= er is used, does the signal actually get initialized to 6, or to 1 (with th= e concurrent assignment statement uncommented)? If the resolution function were called with no drivers, the resolved value = would be 0, not 6. Would we expect the initial value of the signal to then = be 0, or 6? LRM 6.4.2.3 indicates that the value provided by the initializa= tion expression is the initial value of the signal, but later in the same s= ection: "The default value associated with a scalar signal defines the value compon= ent of a transaction that is the initial contents of each driver (if any) o= f that signal. The time component of the transaction is not defined, but th= e transaction is understood to have already occurred by the start of simula= tion." For most cases (wierd resolution functions excluded), there is no differenc= e. >From the LRM descriptions, I might expect that with no drivers, the signal = is initialized to 6. With one driver, the signal would have an initial valu= e of 1 (regardless of the value assigned by the concurrent assignment, it i= s the resolved value of all drivers, which are initialized to 6). Interesting test case... Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 19:44:59 +0200 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> <52D66C46.10501@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jan 2014 17:45:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13992"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+JVwb8nn90U9pDvz6lRdltRcrcGRKHj1s=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: Cancel-Lock: sha1:BX+R597+T5nu+2+pSnBAusLs2J0= Xref: news.eternal-september.org comp.lang.vhdl:7248 > Have you contacted Modelsim about this? If so, what did they say? Here is a special group to ask details about VHDL. Why should we do it in private conversation with Modelsim? We may contract Modelsim only after we establish that their simulator is bad. > My speculation (since I am only a user of Modelsim, that's all it is, speculation) is that with no drivers, there is no reason to call a resolution function. With what argument would it be called, a null vector? Yes, the fact that VHDL specification mandates the default value, mentioned by Ashenden, means that there is no value for the function to operate on. > From the LRM descriptions, I might expect that with no drivers, the signal is initialized to 6. Why not null? > With one driver, the signal would have an initial value of 1 That is clear. But why is the second call of the resolution function? > For most cases (wierd resolution functions excluded), there is no difference. I suspect that Ashenden precisely stipulates the wired cases that you exclude. If there is no differece, there is no need to make the stipulation made by Ashenden. From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 19:53:32 +0200 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jan 2014 17:53:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="18226"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19N4rBnelbmpRFvF6gKdSD+smSbBuNUYBw=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: Cancel-Lock: sha1:D6PNTkIWKu3hIvjaZCql1GoG9Os= Xref: news.eternal-september.org comp.lang.vhdl:7249 In the case of signal UResOfRes: (or_bits) bit_vector(1 to 4) := "0111"; begin UResOfRes <= "1111"; -- UResOfRes <= "0011"; resolutions are not invoked even with single vector. I must to enable the second driver in order to for the resolutions to start invoking. I always call vsim with -nvopt. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.191.136 with SMTP id g8mr1139736yhn.48.1389811387133; Wed, 15 Jan 2014 10:43:07 -0800 (PST) X-Received: by 10.49.85.2 with SMTP id d2mr75003qez.9.1389811387080; Wed, 15 Jan 2014 10:43:07 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no16328171qaj.0!news-out.google.com!fv6ni3477qab.1!nntp.google.com!p15no16328158qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 10:43:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.8.144.152; posting-account=yBXqWgoAAAA4OYeyb4GZH3REJz4A4dc5 NNTP-Posting-Host: 67.8.144.152 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: simulation help From: jeffreywhite2011@my.fit.edu Injection-Date: Wed, 15 Jan 2014 18:43:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4702 X-Received-Body-CRC: 582496631 Xref: news.eternal-september.org comp.lang.vhdl:7250 Hi all, I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-po= int fft followed by an 128 point fft. I'm using counters to simulate the ff= ts. I've tried a state-machine implementation, but when I run the sim, the = input to the state machine goes to an 'X' instead of a '1' when the counter= in the 32-point fft process hits it's final value of ten. Also, the state = never goes from state0 to state 1. the way I thought it would work is: 1. the system starts in state0 and the input to the state machine is 0. 2. the 32-point process counts to 10 and then sets the input to '1'. 3. the state changes to state1. 4. the 128 point process counts to 30 and then sets the input to '0'. My code can be seen below. thank you for your help. Jeff White ---------------------------------------------------------------------------= ------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity stateMachineWfft_32pt is end stateMachineWfft_32pt; architecture Behavioral of stateMachineWfft_32pt is constant CLOCK_PERIOD : time :=3D 100 ns; signal aclk : std_logic :=3D '0'; -- the master clock signal input : std_logic :=3D '0'; -- the thing that makes the state machi= ne do stuff type state_type is (state0, state1); signal current_state : state_type; signal next_state : state_type; begin ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <=3D '0'; wait for CLOCK_PERIOD; loop aclk <=3D '0'; wait for CLOCK_PERIOD/2; aclk <=3D '1'; wait for CLOCK_PERIOD/2; end loop; end process clock_gen; =20 fft_128pt : process(aclk, input) variable count1 : integer :=3D 0; begin if(current_state =3D state1 and aclk'event and aclk =3D '1' ) then count1 :=3D count1 + 1; =09 if(count1 =3D 30) then input <=3D'0'; end if; end if; end process fft_128pt; ------------------------------------------------------------------------ -- implement a fft_32pt to 10 and then return a value signifying completio= n ------------------------------------------------------------------------ =20 fft_32pt : process(aclk, input) =20 variable count : integer :=3D 0; begin if(current_state =3D state0 and aclk'event and aclk =3D '1') then count :=3D count + 1; if(count =3D 10) then input <=3D '1'; =09 end if; end if; end process fft_32pt; =20 =20 state_machine : process( current_state, input ) begin -- case current_state is when state0 =3D> if(input =3D '0') then next_state <=3D state0; elsif (input =3D '1') then next_state <=3D state1; end if; when state1 =3D> if(input =3D '1') then next_state <=3D state1; elsif (input =3D'0') then next_state <=3D state0; end if; end case; -- =20 end process state_machine; ---------------------------------------------------------------------------= ------- -- implement the transfer of next state to current state ---------------------------------------------------------------------------= ------- state_update : process (aclk) begin if( rising_edge(aclk)) then current_state <=3D next_state; end if; end process state_update; end Behavioral; From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.182.95.68 with SMTP id di4mr1477139obb.4.1389811702393; Wed, 15 Jan 2014 10:48:22 -0800 (PST) X-Received: by 10.49.35.45 with SMTP id e13mr76565qej.7.1389811702342; Wed, 15 Jan 2014 10:48:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no16335854qaj.0!news-out.google.com!fv6ni3477qab.1!nntp.google.com!p15no16335847qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 10:48:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.8.144.152; posting-account=yBXqWgoAAAA4OYeyb4GZH3REJz4A4dc5 NNTP-Posting-Host: 67.8.144.152 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26409f09-d8ac-4158-bfe2-2bead9d7e3f7@googlegroups.com> Subject: Re: simulation help From: jeffreywhite2011@my.fit.edu Injection-Date: Wed, 15 Jan 2014 18:48:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 6175 X-Received-Body-CRC: 748389169 Xref: news.eternal-september.org comp.lang.vhdl:7251 On Wednesday, January 15, 2014 1:43:06 PM UTC-5, jeffreyw...@my.fit.edu wro= te: > Hi all, >=20 >=20 >=20 > I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-= point fft followed by an 128 point fft. I'm using counters to simulate the = ffts. I've tried a state-machine implementation, but when I run the sim, th= e input to the state machine goes to an 'X' instead of a '1' when the count= er in the 32-point fft process hits it's final value of ten. Also, the stat= e never goes from state0 to state 1. >=20 >=20 >=20 > the way I thought it would work is: >=20 >=20 >=20 > 1. the system starts in state0 and the input to the state machine is 0. >=20 > 2. the 32-point process counts to 10 and then sets the input to '1'. >=20 > 3. the state changes to state1. >=20 > 4. the 128 point process counts to 30 and then sets the input to '0'. >=20 >=20 >=20 > My code can be seen below. >=20 >=20 >=20 > thank you for your help. >=20 >=20 >=20 > Jeff White >=20 >=20 >=20 > -------------------------------------------------------------------------= --------- >=20 > library IEEE; >=20 > use IEEE.STD_LOGIC_1164.ALL; >=20 >=20 >=20 > -- Uncomment the following library declaration if using >=20 > -- arithmetic functions with Signed or Unsigned values >=20 > --use IEEE.NUMERIC_STD.ALL; >=20 >=20 >=20 > -- Uncomment the following library declaration if instantiating >=20 > -- any Xilinx primitives in this code. >=20 > --library UNISIM; >=20 > --use UNISIM.VComponents.all; >=20 >=20 >=20 > entity stateMachineWfft_32pt is >=20 > end stateMachineWfft_32pt; >=20 >=20 >=20 >=20 >=20 > architecture Behavioral of stateMachineWfft_32pt is >=20 >=20 >=20 > constant CLOCK_PERIOD : time :=3D 100 ns; >=20 >=20 >=20 > signal aclk : std_logic :=3D '0'; -- the master clock >=20 > signal input : std_logic :=3D '0'; -- the thing that makes the state mac= hine do stuff >=20 >=20 >=20 > type state_type is (state0, state1); >=20 > signal current_state : state_type; >=20 > signal next_state : state_type; >=20 >=20 >=20 >=20 >=20 > begin >=20 >=20 >=20 > ----------------------------------------------------------------------- >=20 > -- Generate clock >=20 > ----------------------------------------------------------------------- >=20 >=20 >=20 > clock_gen : process >=20 > begin >=20 > aclk <=3D '0'; >=20 > wait for CLOCK_PERIOD; >=20 > loop >=20 > aclk <=3D '0'; >=20 > wait for CLOCK_PERIOD/2; >=20 > aclk <=3D '1'; >=20 > wait for CLOCK_PERIOD/2; >=20 > end loop; >=20 > end process clock_gen; >=20 > =20 >=20 > fft_128pt : process(aclk, input) >=20 > variable count1 : integer :=3D 0; >=20 > begin >=20 > if(current_state =3D state1 and aclk'event and aclk =3D '1' ) then >=20 > count1 :=3D count1 + 1; =09 >=20 > if(count1 =3D 30) then >=20 > input <=3D'0'; >=20 > end if; >=20 > end if; >=20 > end process fft_128pt; >=20 >=20 >=20 > ------------------------------------------------------------------------ >=20 > -- implement a fft_32pt to 10 and then return a value signifying complet= ion >=20 > ------------------------------------------------------------------------ >=20 > =20 >=20 > fft_32pt : process(aclk, input) >=20 > =20 >=20 > variable count : integer :=3D 0; >=20 >=20 >=20 > begin >=20 > if(current_state =3D state0 and aclk'event and aclk =3D '1') then >=20 > count :=3D count + 1; >=20 > if(count =3D 10) then >=20 > input <=3D '1'; =09 >=20 > end if; >=20 > end if; >=20 > end process fft_32pt; >=20 > =20 >=20 > =20 >=20 > state_machine : process( current_state, input ) >=20 > begin >=20 > -- >=20 > case current_state is >=20 > when state0 =3D> >=20 > if(input =3D '0') then >=20 > next_state <=3D state0; >=20 > elsif (input =3D '1') then >=20 > next_state <=3D state1; >=20 > end if; >=20 > when state1 =3D> >=20 > if(input =3D '1') then >=20 > next_state <=3D state1; >=20 > elsif (input =3D'0') then >=20 > next_state <=3D state0; >=20 > end if; >=20 > end case; >=20 > -- =20 >=20 > end process state_machine; >=20 >=20 >=20 >=20 >=20 > -------------------------------------------------------------------------= --------- >=20 > -- implement the transfer of next state to current state >=20 > -------------------------------------------------------------------------= --------- >=20 >=20 >=20 > state_update : process (aclk) >=20 > begin >=20 >=20 >=20 > if( rising_edge(aclk)) then >=20 > current_state <=3D next_state; >=20 > end if; >=20 > end process state_update; >=20 >=20 >=20 > end Behavioral; I changed the process signatures to=20 fft_128pt : process(aclk, current_state) and=20 fft_32pt : process(aclk, currentat_state) with no change in the behavior of the simulation. From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 20:55:45 +0200 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jan 2014 18:55:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="8616"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+IbQL6+2RAgcbSxThrSRmlmekVx3kN0h4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: Cancel-Lock: sha1:B5cR1N7xG+hQqbiv4979I/AKBug= Xref: news.eternal-september.org comp.lang.vhdl:7252 Curiously, signal UResOfRes: (or_bits) bit_vector(1 to 1) := "0"; begin UResOfRes <= "1"; UResOfRes <= "0" after 2 ns; Calls the resolution twice, with (0,0) and (0,1) at time 0 ns whereas the same with init value := "0" in place of "1", calls the resolution with (1,1) at time 0 and (0,1) at time 2 ns. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.180.2 with SMTP id i2mr1299359yhm.4.1389816117114; Wed, 15 Jan 2014 12:01:57 -0800 (PST) X-Received: by 10.140.47.170 with SMTP id m39mr24924qga.19.1389816116686; Wed, 15 Jan 2014 12:01:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no16438275qaj.0!news-out.google.com!fv6ni3477qab.1!nntp.google.com!p15no16438273qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 12:01:56 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.8.144.152; posting-account=yBXqWgoAAAA4OYeyb4GZH3REJz4A4dc5 NNTP-Posting-Host: 67.8.144.152 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80280375-c3ab-4151-b7ef-eeeaeb611c37@googlegroups.com> Subject: Re: simulation help From: jeffreywhite2011@my.fit.edu Injection-Date: Wed, 15 Jan 2014 20:01:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 6037 X-Received-Body-CRC: 3805792754 Xref: news.eternal-september.org comp.lang.vhdl:7253 On Wednesday, January 15, 2014 1:43:06 PM UTC-5, jeffreyw...@my.fit.edu wro= te: > Hi all, >=20 >=20 >=20 > I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-= point fft followed by an 128 point fft. I'm using counters to simulate the = ffts. I've tried a state-machine implementation, but when I run the sim, th= e input to the state machine goes to an 'X' instead of a '1' when the count= er in the 32-point fft process hits it's final value of ten. Also, the stat= e never goes from state0 to state 1. >=20 >=20 >=20 > the way I thought it would work is: >=20 >=20 >=20 > 1. the system starts in state0 and the input to the state machine is 0. >=20 > 2. the 32-point process counts to 10 and then sets the input to '1'. >=20 > 3. the state changes to state1. >=20 > 4. the 128 point process counts to 30 and then sets the input to '0'. >=20 >=20 >=20 > My code can be seen below. >=20 >=20 >=20 > thank you for your help. >=20 >=20 >=20 > Jeff White >=20 >=20 >=20 > -------------------------------------------------------------------------= --------- >=20 > library IEEE; >=20 > use IEEE.STD_LOGIC_1164.ALL; >=20 >=20 >=20 > -- Uncomment the following library declaration if using >=20 > -- arithmetic functions with Signed or Unsigned values >=20 > --use IEEE.NUMERIC_STD.ALL; >=20 >=20 >=20 > -- Uncomment the following library declaration if instantiating >=20 > -- any Xilinx primitives in this code. >=20 > --library UNISIM; >=20 > --use UNISIM.VComponents.all; >=20 >=20 >=20 > entity stateMachineWfft_32pt is >=20 > end stateMachineWfft_32pt; >=20 >=20 >=20 >=20 >=20 > architecture Behavioral of stateMachineWfft_32pt is >=20 >=20 >=20 > constant CLOCK_PERIOD : time :=3D 100 ns; >=20 >=20 >=20 > signal aclk : std_logic :=3D '0'; -- the master clock >=20 > signal input : std_logic :=3D '0'; -- the thing that makes the state mac= hine do stuff >=20 >=20 >=20 > type state_type is (state0, state1); >=20 > signal current_state : state_type; >=20 > signal next_state : state_type; >=20 >=20 >=20 >=20 >=20 > begin >=20 >=20 >=20 > ----------------------------------------------------------------------- >=20 > -- Generate clock >=20 > ----------------------------------------------------------------------- >=20 >=20 >=20 > clock_gen : process >=20 > begin >=20 > aclk <=3D '0'; >=20 > wait for CLOCK_PERIOD; >=20 > loop >=20 > aclk <=3D '0'; >=20 > wait for CLOCK_PERIOD/2; >=20 > aclk <=3D '1'; >=20 > wait for CLOCK_PERIOD/2; >=20 > end loop; >=20 > end process clock_gen; >=20 > =20 >=20 > fft_128pt : process(aclk, input) >=20 > variable count1 : integer :=3D 0; >=20 > begin >=20 > if(current_state =3D state1 and aclk'event and aclk =3D '1' ) then >=20 > count1 :=3D count1 + 1; =09 >=20 > if(count1 =3D 30) then >=20 > input <=3D'0'; >=20 > end if; >=20 > end if; >=20 > end process fft_128pt; >=20 >=20 >=20 > ------------------------------------------------------------------------ >=20 > -- implement a fft_32pt to 10 and then return a value signifying complet= ion >=20 > ------------------------------------------------------------------------ >=20 > =20 >=20 > fft_32pt : process(aclk, input) >=20 > =20 >=20 > variable count : integer :=3D 0; >=20 >=20 >=20 > begin >=20 > if(current_state =3D state0 and aclk'event and aclk =3D '1') then >=20 > count :=3D count + 1; >=20 > if(count =3D 10) then >=20 > input <=3D '1'; =09 >=20 > end if; >=20 > end if; >=20 > end process fft_32pt; >=20 > =20 >=20 > =20 >=20 > state_machine : process( current_state, input ) >=20 > begin >=20 > -- >=20 > case current_state is >=20 > when state0 =3D> >=20 > if(input =3D '0') then >=20 > next_state <=3D state0; >=20 > elsif (input =3D '1') then >=20 > next_state <=3D state1; >=20 > end if; >=20 > when state1 =3D> >=20 > if(input =3D '1') then >=20 > next_state <=3D state1; >=20 > elsif (input =3D'0') then >=20 > next_state <=3D state0; >=20 > end if; >=20 > end case; >=20 > -- =20 >=20 > end process state_machine; >=20 >=20 >=20 >=20 >=20 > -------------------------------------------------------------------------= --------- >=20 > -- implement the transfer of next state to current state >=20 > -------------------------------------------------------------------------= --------- >=20 >=20 >=20 > state_update : process (aclk) >=20 > begin >=20 >=20 >=20 > if( rising_edge(aclk)) then >=20 > current_state <=3D next_state; >=20 > end if; >=20 > end process state_update; >=20 >=20 >=20 > end Behavioral; I figured it out. Thanks for reading. jw From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Wed, 15 Jan 2014 22:38:28 +0200 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 15 Jan 2014 20:38:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="14040"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Ypkxlo7V1xxGlfy4Edgl6pVIXEc/5Uns=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: Cancel-Lock: sha1:nYNf4IghYQLbehdh4yivL15fzng= Xref: news.eternal-september.org comp.lang.vhdl:7254 Ok, this helped me to figure out the logic. No resolution function is called on the signal if there are no drivers. Otherwise, the resolution function is called to initialize the signal where the signal initial value is used as the initial driver value. This particularly means that resolution function function sum(integers: integer_array) return integer result := 0 foreach I in integers, result += I for the signal s3 : sum integer := 3 will initialize the signal to 6 instead of 3 if there are two drivers because we have two drivers and each contributes 3, and to 3 if there is one driver or no drivers. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.228.228 with SMTP id f94mr1803560yhq.43.1389831078051; Wed, 15 Jan 2014 16:11:18 -0800 (PST) X-Received: by 10.182.114.135 with SMTP id jg7mr202obb.34.1389831077917; Wed, 15 Jan 2014 16:11:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!p15no16734931qaj.0!news-out.google.com!gg4ni4818qab.0!nntp.google.com!p15no16734927qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 16:11:17 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <38ebdb51-6dc7-455d-8975-f99ae4d5b49b@googlegroups.com> <4e145db9-48e7-40fe-8961-435cd4d1c956@googlegroups.com> <52D66C46.10501@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40cf5fb6-4b6f-4234-908c-d53df792aba1@googlegroups.com> Subject: Re: Resolution func in the initialization From: Andy Injection-Date: Thu, 16 Jan 2014 00:11:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2439 X-Received-Body-CRC: 1976674210 Xref: news.eternal-september.org comp.lang.vhdl:7255 There is a difference between a null vector and "no value". No value would = be an error since it violates the type check on the input parameter. Callin= g your driver_counter() function with a null vector is completely legal (bu= t I doubt it happens as a resolution function). The function would return a= value of 0, because the result variable is initialized to 0, and never alt= ered if the input argument is a null vector. > Why not null?=20 Because null is not a legal integer value. > But why the second call of the resolution function?=20 Because the transaction from the concurrent assignment statement happens at= time 0 plus 1 delta, whereas the initialization call happens at 0+0. > I suspect that Ashenden precisely stipulates the wired cases that you=20 exclude. Semantics: "stipulate" =3D "explicitly state". Ashenden did not explicitly = state the wierd cases. Perhaps he had them in mind, since they are one of t= he few ways his case could be demonstrated.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.42.110.198 with SMTP id r6mr1825530icp.33.1389831383478; Wed, 15 Jan 2014 16:16:23 -0800 (PST) X-Received: by 10.182.118.138 with SMTP id km10mr43626obb.27.1389831383289; Wed, 15 Jan 2014 16:16:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!6no12385246qao.1!news-out.google.com!gg4ni4818qab.0!nntp.google.com!p15no16740109qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 15 Jan 2014 16:16:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81accfd0-0b9d-408e-96e7-bb7068ff73fa@googlegroups.com> Subject: Re: Resolution func in the initialization From: Andy Injection-Date: Thu, 16 Jan 2014 00:16:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1540 X-Received-Body-CRC: 434729702 Xref: news.eternal-september.org comp.lang.vhdl:7256 On Wednesday, January 15, 2014 2:38:28 PM UTC-6, valtih1978 wrote: > ...will initialize the signal to 6 instead of 3 if there are two drivers because we have two drivers and each contributes 3, and to 3 if there is one driver or no drivers. Did you test this, or is this what you expect will happen? I believe you are correct, but I have not tried it. Thanks for the info. Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Resolution func in the initialization Date: Thu, 16 Jan 2014 15:48:08 +0200 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: <81accfd0-0b9d-408e-96e7-bb7068ff73fa@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 16 Jan 2014 13:48:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="21726"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vUymgynC7Z9BNMKeG1UOiirkB+L4nybA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: <81accfd0-0b9d-408e-96e7-bb7068ff73fa@googlegroups.com> X-Antivirus-Status: Clean X-Antivirus: avast! (VPS 140109-2, 09.01.2014), Outbound message Cancel-Lock: sha1:ocg+vSC/ywLw+24t+J8ENX8Rz5U= Xref: news.eternal-september.org comp.lang.vhdl:7257 This is how Modelsim behaves and it seems reasonable to me. --- This email is free from viruses and malware because avast! Antivirus protection is active. http://www.avast.com From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.59.12.105 with SMTP id ep9mr2122885ved.9.1390011356615; Fri, 17 Jan 2014 18:15:56 -0800 (PST) X-Received: by 10.140.28.34 with SMTP id 31mr3570qgy.9.1390011356560; Fri, 17 Jan 2014 18:15:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no15880001qao.1!news-out.google.com!fv6ni4421qab.1!nntp.google.com!6no15879998qao.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 Jan 2014 18:15:56 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.203; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp NNTP-Posting-Host: 72.64.6.203 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Active-HDL: all writes to STDOUT are prefixed with "KERNEL:" From: Brian Davis Injection-Date: Sat, 18 Jan 2014 02:15:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7258 Hans wrote: > > On Modelsim you can find the option on the main > transcript menu (or use set PrefMain(LinePrefix) {# } > There is a similar control in Active-HDL, $messageprefix (default = #) But that controls an additional prefix that shows up only in the GUI console transcript window: # KERNEL: Hello world! > > If there is no option in Aldec then I guess you have > to resort to a bit of good old text filtering. > Yes, I've been using an s/^KERNEL:// preprocessing filter as a workaround. But it seems rather silly to need this... > > I suspect there must be something as it is quite a basic > requirement (lots of testbenches write log files which > are filtered/analysed later on). > I have not been able to find a vsim command line option to disable this. However, I did finally find a way to turn it off from the GUI: Turning off Active-HDL message prefix (affects both GUI and command line): - fire up the Active-HDL GUI - Tools=>Preferences=>Environment=>Console=>uncheck "Show Message Prefix" Turning off additional GUI message prefix: $set messageprefix "" ---------------------- Other notes: I'm trying to implement a simulator-agnostic testsuite which parses the output logs from a bunch of simulator runs. Ideally, I would like to turn off this prefix from the command line script that runs the testsuite, without needing user intervention in the GUI. So far Aldec is the only simulator I've found that corrupts writes to STDOUT. Also of note, Aldec writes both simulator and program messages both to STDOUT. Other simulators I've checked write their various messages to STDERR, while the VHDL write_line()s go to STDOUT; this lets you redirect the two independently. Writes to a file are un-corrupted, but I would need to some add file plumbing to my testbench & design. Somewhat amusingly, opening a (Windows) file named CON: allows writes to STDOUT without the prefix: file_open(log_file,"CON:",WRITE_MODE); write (l, String'("Hello world!")); writeline (log_file, l); Produces: Hello world! -Brian From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.58.95.1 with SMTP id dg1mr5641799veb.29.1390175733108; Sun, 19 Jan 2014 15:55:33 -0800 (PST) X-Received: by 10.140.36.37 with SMTP id o34mr14673qgo.10.1390175733082; Sun, 19 Jan 2014 15:55:33 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!6no19059008qao.1!news-out.google.com!gg4ni8086qab.0!nntp.google.com!p15no23393489qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 Jan 2014 15:55:32 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.203; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp NNTP-Posting-Host: 72.64.6.203 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3b9155e7-e0b1-453e-8c68-427f40f0e438@googlegroups.com> Subject: Re: Active-HDL: all writes to STDOUT are prefixed with "KERNEL:" From: Brian Davis Injection-Date: Sun, 19 Jan 2014 23:55:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7259 A correction to my earlier post: > >However, I did finally find a way to turn it off from the GUI: > >Turning off Active-HDL message prefix (affects both GUI and command line): > - fire up the Active-HDL GUI > - Tools=>Preferences=>Environment=>Console=>uncheck "Show Message Prefix" > It turns out that "Show Message Prefix" option works only in the GUI, and does not affect the command line vsim simulator. (When I tested earlier, I must have mistakenly run the test code that was patched for file IO to STDOUT) I'll stick with the filter workaround for now, and see whether I can open an Aldec support account (when using a free Lattice license) to ask Aldec about this. -Brian From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <52dd5f70$0$9227$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Resolution func in the initialization Newsgroups: comp.lang.vhdl Date: Mon, 20 Jan 2014 18:40:00 +0100 References: Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 40 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1390239600 dreader35.news.xs4all.nl 9227 puiterl/195.242.97.150:44662 Xref: news.eternal-september.org comp.lang.vhdl:7260 valtih1978 wrote: > --- begin code --- > > architecture ARCH of TOP is > > type int_vector is array (integer range<>) of integer; > function driver_counter( values : int_vector ) return integer is > variable result : integer := 0; > variable l: line; > begin > for index in values'range loop > if values(index) /= 0 then > result := result + 1; > write (l, integer'image(values(index)) & ","); > end if; > end loop; > report l.all & " count resolved => " & integer'image(result); > return result; > end function; When using access types (which "line" is), one always must be careful not to create a memory leak. The above code contains a memory leak. A string is allocated by calling "write". The return from the function where the allocation took place results in loss of the "pointer" (l) to the string. The memory used by the sting is not freed, there is no automatic garbage collection in VHDL. The solution is to place a deallocate statement between the report and return statement: deallocate(l); Even if the procedure writeline was used (instead of report), deallocate would be necessary. The writeline procedure leaves l pointing to an empty string. Even an empty string uses a non-zero amount of memory. -- Paul Uiterlinden AimValley B.V. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.50.154.73 with SMTP id vm9mr1627406igb.2.1390409530813; Wed, 22 Jan 2014 08:52:10 -0800 (PST) X-Received: by 10.182.117.138 with SMTP id ke10mr1066obb.42.1390409530376; Wed, 22 Jan 2014 08:52:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c10no753543igq.0!news-out.google.com!vg8ni2igb.0!nntp.google.com!uq10no1516437igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jan 2014 08:52:10 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18932660-2001-4976-bdd0-193c44ae3949@googlegroups.com> Subject: Calculating Percentages in VHDL? From: Cory Shol Injection-Date: Wed, 22 Jan 2014 16:52:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7261 Hello all, I am working on a project that needs to complete safety crosschecks on a regular basis. If a User sets up the equipment at a specific setting the FPGA logic will calculate a Reference Voltage (lets say a 16 bit number ). The user will also set a percentage from 10-35% (Overvoltage Threshold). Once the user says he wants the system to allow 15% of overvoltage. I want to calculate in the logic the 16 bit referance voltage * .15 . How does one go about calculating percentages? I am using a Xilinx Spartan 3a 700a. A link to an tutorial or algorithm would be great. Thanks From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Calculating Percentages in VHDL? Date: Wed, 22 Jan 2014 09:45:33 -0800 Organization: Highland Technology, Inc. Lines: 24 Message-ID: <20140122094533.7eca9bc9@rg.highlandtechnology.com> References: <18932660-2001-4976-bdd0-193c44ae3949@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="22efc02dfed284f1cd28230f6e0993c5"; logging-data="18560"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/IuBgpPft5ObMiuF6/LK/w" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Bo9hNeRFCyQjPaPIzi/avxEO6fQ= Xref: news.eternal-september.org comp.lang.vhdl:7262 On Wed, 22 Jan 2014 08:52:10 -0800 (PST) Cory Shol wrote: > Hello all, > > I am working on a project that needs to complete safety crosschecks on a regular basis. > > If a User sets up the equipment at a specific setting the FPGA logic will calculate a Reference Voltage (lets say a 16 bit number ). The user will also set a percentage from 10-35% (Overvoltage Threshold). > > Once the user says he wants the system to allow 15% of overvoltage. > > I want to calculate in the logic the 16 bit referance voltage * .15 . > > > How does one go about calculating percentages? I am using a Xilinx Spartan 3a 700a. A link to an tutorial or algorithm would be great. > > Thanks > R * 0.15 = R * (0.15 * 2^17) / 2^17 -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.66.102.8 with SMTP id fk8mr1097357pab.24.1390413955289; Wed, 22 Jan 2014 10:05:55 -0800 (PST) X-Received: by 10.182.47.161 with SMTP id e1mr26074obn.24.1390413954760; Wed, 22 Jan 2014 10:05:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!ma3no1015944pbc.0!news-out.google.com!vg8ni2igb.0!nntp.google.com!uq10no1630071igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jan 2014 10:05:54 -0800 (PST) In-Reply-To: <20140122094533.7eca9bc9@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.215.48.194; posting-account=YtzxkQoAAADNZeUWb6WHy9-ntlODoWtJ NNTP-Posting-Host: 67.215.48.194 References: <18932660-2001-4976-bdd0-193c44ae3949@googlegroups.com> <20140122094533.7eca9bc9@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Calculating Percentages in VHDL? From: Cory Shol Injection-Date: Wed, 22 Jan 2014 18:05:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7263 On Wednesday, January 22, 2014 11:45:33 AM UTC-6, Rob Gaddi wrote: > On Wed, 22 Jan 2014 08:52:10 -0800 (PST) > > Cory Shol wrote: > > > > > Hello all, > > > > > > I am working on a project that needs to complete safety crosschecks on a regular basis. > > > > > > If a User sets up the equipment at a specific setting the FPGA logic will calculate a Reference Voltage (lets say a 16 bit number ). The user will also set a percentage from 10-35% (Overvoltage Threshold). > > > > > > Once the user says he wants the system to allow 15% of overvoltage. > > > > > > I want to calculate in the logic the 16 bit referance voltage * .15 . > > > > > > > > > How does one go about calculating percentages? I am using a Xilinx Spartan 3a 700a. A link to an tutorial or algorithm would be great. > > > > > > Thanks > > > > > > > R * 0.15 = R * (0.15 * 2^17) / 2^17 > > > > -- > > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > > Email address domain is currently out of order. See above to fix. Ahh yes , I actually just thought about something similar to that just before I read the reply. Sometimes your brain doesn't work as fast as you want it to. From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.66.172.38 with SMTP id az6mr1162883pac.7.1390417032930; Wed, 22 Jan 2014 10:57:12 -0800 (PST) X-Received: by 10.140.95.144 with SMTP id i16mr69548qge.1.1390417032837; Wed, 22 Jan 2014 10:57:12 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!goblin3!goblin2!goblin.stu.neva.ru!novso.com!news.he.net!news.snarked.org!newsfeed.news.ucla.edu!usenet.stanford.edu!rq2no1057684pbb.1!news-out.google.com!gg4ni967qab.0!nntp.google.com!k15no1684611qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jan 2014 10:57:12 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <18932660-2001-4976-bdd0-193c44ae3949@googlegroups.com> <20140122094533.7eca9bc9@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b3c1765-bbfa-4dce-9eb6-89730441c2b1@googlegroups.com> Subject: Re: Calculating Percentages in VHDL? From: Andy Injection-Date: Wed, 22 Jan 2014 18:57:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: news.eternal-september.org comp.lang.vhdl:7264 Try the fixed point library in VHDL. It is included in the 2008 standard, and a quick google search will get you the vhdl fixed point user guide that shows you how to use it. Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.68.201.7 with SMTP id jw7mr4871544pbc.8.1391065738018; Wed, 29 Jan 2014 23:08:58 -0800 (PST) X-Received: by 10.182.115.134 with SMTP id jo6mr90762obb.6.1391065737660; Wed, 29 Jan 2014 23:08:57 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!uq10no5503451igb.0!news-out.google.com!vg8ni1igb.0!nntp.google.com!c10no5401470igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Jan 2014 23:08:57 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:bded:92e0:a0ef:9d40:c484:42b9; posting-account=k5nptwkAAADqCCFX9WAZnt6feBAS-RPC NNTP-Posting-Host: 2602:306:bded:92e0:a0ef:9d40:c484:42b9 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: aditya.verma210@gmail.com Injection-Date: Thu, 30 Jan 2014 07:08:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7265 can i get solutions manual to Wireless Communications (Andrea Goldsmith) From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.108.228 with SMTP id q64mr5002868yhg.36.1391092002996; Thu, 30 Jan 2014 06:26:42 -0800 (PST) X-Received: by 10.50.50.8 with SMTP id y8mr262091ign.13.1391092002889; Thu, 30 Jan 2014 06:26:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no10531628qaq.0!news-out.google.com!vg8ni1igb.0!nntp.google.com!c10no6939678igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 30 Jan 2014 06:26:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=180.215.102.60; posting-account=9FRWwgoAAABy3EBKLnV8yQnOgWncjbR- NNTP-Posting-Host: 180.215.102.60 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <422872ca-91ff-47c4-87ca-0b1ff0f6c5a9@googlegroups.com> Subject: Re: Multi Valued logic simulation using VHDL? From: Lokesh Kanna Injection-Date: Thu, 30 Jan 2014 14:26:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1791 X-Received-Body-CRC: 1197750122 Xref: news.eternal-september.org comp.lang.vhdl:7266 On Saturday, February 21, 2004 12:13:12 AM UTC+5:30, Guru Prasad wrote: > Hi! > > I have taken on a project of benchmarking the relative performance of > a binary ALU Vs a ternary ALU. I was wondering if I could use VHDL to > program a simple ALU that does multiplication, addition and division > for multi-valued logic and if so, could someone point me to recources > where I can find more information about the same? > > thanks. hai guru, I hv planned to do the same project that u did...Though u hv done years back,help me by sending some links where we can find the sample codes for ternary MVL operation. lokesh00xx@gmail.com . thanks in advance...:) From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 09 Feb 2014 01:56:58 -0600 From: recow182 Subject: RE: fpga IOB Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 4a86863c-e362-4a24-b7a2-cece23ea8f05 References: <5b6bb57f-3cd8-4131-9d5e-e5e05747eb27@m16g2000yqc.googlegroups.com> Message-ID: Date: Sun, 09 Feb 2014 01:56:58 -0600 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-qaFANOKMUqPpjXRrJ/RmU67hK8h9gqRyqvn8DQECT1f0Nab/Is4yrWTxz1Zzb7/trnKjgr5fxgGAXhZ!S1jtBDPKyn++1hC9Et09nVd1reXpb2QNb5fYaUwU4dsv6bFqhf61LCUyQEkobOjdDLGYKKe7vfFn!qg== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1020 Xref: news.eternal-september.org comp.lang.vhdl:7267 How can I disable this feature? From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 09 Feb 2014 01:57:50 -0600 From: sathiyamoorthy Subject: image erosion and dilation code Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: f82f5b02-c011-4f50-9a58-84dd462ea779 Message-ID: Date: Sun, 09 Feb 2014 01:57:50 -0600 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-lJ5r49bIdnnE0UK+oWl4ciwID7bqZp9NDosQJAP9FIrwp3RMp5K0dPh/crI0wGKvhDue7Al1hs/kz/A!eTPiy0Df001WU3GVp6ajE8TYj0m/yGGMWezqkjmSfaZ8T0exuLk/hy9kQu0V1Yh9KlI6jwcC2KBR!Pg== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1101 Xref: news.eternal-september.org comp.lang.vhdl:7268 i write many code for image erosion & dilation code bt its not working if u hav plz send me sir it will help me for the project to my mail sathiyamoorthyece@gmail.com From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.145.34 with SMTP id o22mr11277159yhj.22.1392044001051; Mon, 10 Feb 2014 06:53:21 -0800 (PST) X-Received: by 10.50.9.37 with SMTP id w5mr53667iga.7.1392044000906; Mon, 10 Feb 2014 06:53:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!k15no15898797qaq.0!news-out.google.com!vg8ni23igb.0!nntp.google.com!c10no15495057igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 10 Feb 2014 06:53:20 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <5b6bb57f-3cd8-4131-9d5e-e5e05747eb27@m16g2000yqc.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <84dbb777-e6ae-4600-a601-96a4c6d2e345@googlegroups.com> Subject: Re: fpga IOB From: Andy Injection-Date: Mon, 10 Feb 2014 14:53:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7269 On Sunday, February 9, 2014 1:56:58 AM UTC-6, recow182 wrote: > How can I disable this feature? It depends on your synthesis tool... Look for a synthesis option called disable_io_insertion or similar (at least with Synplify). Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.236.209.134 with SMTP id s6mr11451796yho.40.1392120714504; Tue, 11 Feb 2014 04:11:54 -0800 (PST) X-Received: by 10.140.50.34 with SMTP id r31mr158423qga.15.1392120714476; Tue, 11 Feb 2014 04:11:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border5.a.newsrouter.astraweb.com!border2.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!f11no17171130qae.1!news-out.google.com!y18ni7903qap.1!nntp.google.com!f11no17171124qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Feb 2014 04:11:54 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d1344e6-4693-46b9-bcbb-c82cc00e3415@googlegroups.com> Subject: These no else statements generate latches? From: fl Injection-Date: Tue, 11 Feb 2014 12:11:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 23 Xref: news.eternal-september.org comp.lang.vhdl:7270 Hi, I have read that it should have complete IF THEN ELSE to avoid latches generated for FPGA application. But I find the following process which was generated from an automatic VHDL generating software. Does this example have the danger to generate latch or not? Of course, I can implement it (it seems there is no latch yet). I would like to have a clear canalization to know the full story about it. Thanks, ........... temp_process12_Delay_stepcnt : PROCESS (clk, reset) BEGIN IF reset = '1' THEN int_delay_pipe_1(0 TO 2) <= (OTHERS => (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF enb_1_1_1 = '1' THEN int_delay_pipe_1(0) <= dcnt; int_delay_pipe_1(1 TO 2) <= int_delay_pipe_1(0 TO 1); END IF; END IF; END PROCESS temp_process12_Delay_stepcnt; From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx09.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: These no else statements generate latches? Newsgroups: comp.lang.vhdl References: <9d1344e6-4693-46b9-bcbb-c82cc00e3415@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 29 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1392122006 62.49.20.82 (Tue, 11 Feb 2014 12:33:26 UTC) NNTP-Posting-Date: Tue, 11 Feb 2014 12:33:26 UTC Date: Tue, 11 Feb 2014 12:33:26 GMT X-Received-Body-CRC: 2253976760 X-Received-Bytes: 1837 Xref: news.eternal-september.org comp.lang.vhdl:7271 On Tue, 11 Feb 2014 04:11:54 -0800, fl wrote: > Hi, > > I have read that it should have complete IF THEN ELSE to avoid latches > generated for FPGA application. But I find the following process which > was generated from an automatic VHDL generating software. > > Does this example have the danger to generate latch or not? Of course, I > can implement it (it seems there is no latch yet). I would like to have > a clear canalization to know the full story about it. > ELSIF clk'event AND clk = '1' THEN > IF enb_1_1_1 = '1' THEN int_delay_pipe_1(0) <= dcnt; > int_delay_pipe_1(1 TO 2) <= int_delay_pipe_1(0 TO 1); > END IF; > END IF; No it won't implement latches, because the incomplete IF statement is in a clocked process. So it will implement registers instead : if the condition is false, the register will retain its current value. I recommend simplifying to "if rising_edge(clk) then ..." but that is less important. In a different process without a proper clock expression, yes you could get latches. - Brian From newsfish@newsfish Tue Dec 29 16:43:17 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: These no else statements generate latches? Date: Tue, 11 Feb 2014 09:10:05 -0500 Organization: Alacron, Inc. Lines: 44 Message-ID: References: <9d1344e6-4693-46b9-bcbb-c82cc00e3415@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 11 Feb 2014 14:08:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="6815"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18WoZMkNIKaJhi97dykbjGEkUgjC5ybdbk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:M3QXWZWAxCKdLX7FJhiMV3zwK0Q= Xref: news.eternal-september.org comp.lang.vhdl:7272 Brian Drummond wrote: > On Tue, 11 Feb 2014 04:11:54 -0800, fl wrote: > >> Hi, >> >> I have read that it should have complete IF THEN ELSE to avoid latches >> generated for FPGA application. But I find the following process which >> was generated from an automatic VHDL generating software. >> >> Does this example have the danger to generate latch or not? Of course, I >> can implement it (it seems there is no latch yet). I would like to have >> a clear canalization to know the full story about it. > >> ELSIF clk'event AND clk = '1' THEN >> IF enb_1_1_1 = '1' THEN int_delay_pipe_1(0) <= dcnt; >> int_delay_pipe_1(1 TO 2) <= int_delay_pipe_1(0 TO 1); >> END IF; >> END IF; > > No it won't implement latches, because the incomplete IF statement is in > a clocked process. So it will implement registers instead : if the > condition is false, the register will retain its current value. > > I recommend simplifying to "if rising_edge(clk) then ..." but that is > less important. > > In a different process without a proper clock expression, yes you could > get latches. > > - Brian Just a clarification. The edge-triggered (clocked) process will create registers whether or not there is an incomplete IF statement. However the incomplete IF will cause the Q output of those registers to feed back to the D inputs, or alternately use a clock enable to hold the register's current state depending on the architecture you target. For most FPGA's internal (fabric) flops this would not be an issue. There are some cases like IOB flops where feedback or clock enables might prevent the tools from placing the register in the IOB, or force the tools to replicate the register to allow a copy without self-feedback to be placed in the IOB. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.66.218.70 with SMTP id pe6mr70928pac.33.1392136649205; Tue, 11 Feb 2014 08:37:29 -0800 (PST) X-Received: by 10.182.117.138 with SMTP id ke10mr332obb.42.1392136648905; Tue, 11 Feb 2014 08:37:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no17681214igq.0!news-out.google.com!vg8ni31igb.0!nntp.google.com!uq10no16150136igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Feb 2014 08:37:28 -0800 (PST) In-Reply-To: <9d1344e6-4693-46b9-bcbb-c82cc00e3415@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <9d1344e6-4693-46b9-bcbb-c82cc00e3415@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a9f207f-7f9c-4160-8131-41167d5030ca@googlegroups.com> Subject: Re: These no else statements generate latches? From: Andy Injection-Date: Tue, 11 Feb 2014 16:37:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7273 On Tuesday, February 11, 2014 6:11:54 AM UTC-6, fl wrote: > I would like to have a clear canalization to know the full story about it= . Perhaps you meant "canonization"? This is perhaps the most mis-understood and ill-instructed concept of logic= synthesis: the synthesis of storage, and more practically, how to avoid sy= nthesizing a latch, which is a type of storage element. Generally speaking, anytime a signal or variable is required to retain its = value from a previous execution of the process that assigns it, a storage e= lement is synthesized to remember that value. Whether the storage is synthesized as a register or a latch is based on the= conditions under which the previous value was stored. It if was stored onl= y upon the edge of another signal, then a register is synthesized to hold t= he value. If not, then a latch is synthesized to hold the value. How can one avoid unintentionally synthesizing a latch? Avoid having to rem= ember a previous value that was not stored on a clock edge. Within most clo= cked processes*, it is impossible to synthesize a latch, because storage wi= thin them always occurs on a clock edge. That leaves combinatorial processes. If you can avoid combinatorial process= es, then your chances of synthezising latches reduce to zero*. If you need or desire to use combinatorial processes, the oft-stated advice= is to "add an else for every if". The problem is, this is neither necessar= y nor sufficient to avoid latches.=20 To avoid a latch in a combinatorial process, ensure that every execution pa= th through the combinatorial process assigns a value to every signal or var= iable ever assigned by the process.=20 You could do that within else statements for every if statement, but that i= nspection for completeness during review is extremely difficult, because yo= u still have to confirm that every signal/variable gets assigned at least s= omewhere for every possible path through the conditional statements.=20 A better approach for combinatorial processes is to provide default assignm= ent statements for every signal and variable assigned by the process (note = these assignments cannot simply assign a signal with its current value, or = you defeat the whole purpose of avoiding latches.) Execute these default as= signments right up front in the process, before any conditional statements = could interfere with their execution. When using variables exclusively for combinatorial logic within a clocked p= rocess, the same approach works to avoid inadvertently synthesizing a regis= ter from a variable (if that is forbidden in your organization or project).= Just make sure every variable has a default assignemnt statement immediate= ly folowing the "if rising_edge(clk) then" statement, but prior to any furt= her conditional statements, and none of your variables will synthesize to a= register either.=20 Notice a pattern here? It doesn't matter what kind of storage element you a= re trying to avoid, the rules are the same. *There's always a catch... Within clocked processes, it is possible to defi= ne combinatorial outputs that are functions of registers represented by loc= al variables. These combinatorial output signal assignments are placed with= in the process, but after the "end if" for the clock edge detection (just b= efore the "end process" statement.) In this region, if a signal is only som= etimes assigned, a latch can also be synthesized. If you have conditional s= tatements in this region, then also include default assignments at the begi= nning of this region. If you don't use these types of outputs, then you don= 't have to worry about it. Andy From newsfish@newsfish Tue Dec 29 16:43:17 2015 X-Received: by 10.42.119.209 with SMTP id c17mr839356icr.17.1392177952854; Tue, 11 Feb 2014 20:05:52 -0800 (PST) X-Received: by 10.50.79.130 with SMTP id j2mr38482igx.2.1392177952734; Tue, 11 Feb 2014 20:05:52 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no18497909igq.0!news-out.google.com!ul13ni15igb.0!nntp.google.com!uq10no16967637igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Feb 2014 20:05:52 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=Ntc6-QoAAABoqk1I3ZuNAujnuWZTh0VD NNTP-Posting-Host: 115.187.63.199 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> Subject: Help using generate statement From: "koyel.aphy@gmail.com" Injection-Date: Wed, 12 Feb 2014 04:05:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7274 Hi, Can someone please tell me that if I declare a signal inside generate state= ment then whether that signal gets replicated a number of times that is dic= tated by the generate statement? Please take a look at the following exampl= e which is a portion of a code available online rounds: for i in 0 to 2 ** DEPTH - 1 generate signal round_k : std_logic_vector(31 downto 0); signal round_w : std_logic_vector(511 downto 0); signal round_s : std_logic_vector(255 downto 0); begin round_k <=3D K(i * 2 ** (6 - DEPTH) + conv_integer(step)); round_w <=3D w(i) when step =3D "000000" else w(i + 1); round_s <=3D s(i) when step =3D "000000" else s(i + 1); transform: sha256_transform port map ( clk =3D> clk, w_in =3D> round_w, w_out =3D> w(i + 1), s_in =3D> round_s, s_out =3D> s(i + 1), k =3D> round_k ); end generate; So do the signals round_k, round_w and round_s get replicated 2 ** DEPTH - = 1 times? Also does the component sha56_transform get replicated 2 ** DEPTH = - 1 times? Thank you, Best Regards From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.66.65.202 with SMTP id z10mr1633319pas.45.1392206911291; Wed, 12 Feb 2014 04:08:31 -0800 (PST) X-Received: by 10.182.213.41 with SMTP id np9mr319258obc.3.1392206910920; Wed, 12 Feb 2014 04:08:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no17425612igb.0!news-out.google.com!ul13ni14igb.0!nntp.google.com!c10no18955383igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Feb 2014 04:08:30 -0800 (PST) In-Reply-To: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29c50823-7e0f-45dd-b80b-b26f92b379c4@googlegroups.com> Subject: Re: Help using generate statement From: KJ Injection-Date: Wed, 12 Feb 2014 12:08:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7275 On Tuesday, February 11, 2014 11:05:52 PM UTC-5, koyel...@gmail.com wrote: > > So do the signals round_k, round_w and round_s get replicated 2 ** DEPTH - 1 > times? Also does the component sha56_transform get replicated 2 ** DEPTH - 1 > times? > Yes to both questions Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed4.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <52fb6fa6$0$24931$e4fe514c@dreader36.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Help using generate statement Newsgroups: comp.lang.vhdl Date: Wed, 12 Feb 2014 13:57:10 +0100 References: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 50 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1392209830 dreader36.news.xs4all.nl 24931 puiterl/195.242.97.150:36878 Xref: news.eternal-september.org comp.lang.vhdl:7276 koyel.aphy@gmail.com wrote: > Hi, > > Can someone please tell me that if I declare a signal inside generate > statement then whether that signal gets replicated a number of times that > is dictated by the generate statement? Yes, they are. > Please take a look at the following > example which is a portion of a code available online > > rounds: for i in 0 to 2 ** DEPTH - 1 generate > signal round_k : std_logic_vector(31 downto 0); > signal round_w : std_logic_vector(511 downto 0); > signal round_s : std_logic_vector(255 downto 0); > begin > round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step)); > round_w <= w(i) when step = "000000" else w(i + 1); > round_s <= s(i) when step = "000000" else s(i + 1); > > transform: sha256_transform > port map ( > clk => clk, > w_in => round_w, > w_out => w(i + 1), > s_in => round_s, > s_out => s(i + 1), > k => round_k > ); > end generate; > > So do the signals round_k, round_w and round_s get replicated 2 ** DEPTH - > 1 times? Yes, they are. > Also does the component sha56_transform get replicated 2 ** DEPTH > - 1 times? Yes, that's what the generate statement is all about. And to be precise: the component gets instantiated 2 ** DEPTH times (so without "- 1"). -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.236.145.34 with SMTP id o22mr2879117yhj.22.1392265422215; Wed, 12 Feb 2014 20:23:42 -0800 (PST) X-Received: by 10.50.43.161 with SMTP id x1mr43094igl.13.1392265422011; Wed, 12 Feb 2014 20:23:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!f11no19031339qae.1!news-out.google.com!s3ni16789qas.0!nntp.google.com!uq10no18350121igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Feb 2014 20:23:41 -0800 (PST) In-Reply-To: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=InKtjwoAAADGcfo0qx53UFf1Ya_UtGvZ NNTP-Posting-Host: 115.187.63.199 References: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <78978192-184f-4385-b8a6-25e3e5ed072c@googlegroups.com> Subject: Re: Help using generate statement From: koyel.aphy@gmail.com Injection-Date: Thu, 13 Feb 2014 04:23:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 10 Xref: news.eternal-september.org comp.lang.vhdl:7277 Thank you very much for your replies. Actually round_w, round_k and round_s= do not have indices as round_w(i), round_k(i) and round_s(i) as usually th= e signals that are replicated under generate statements have but I think as= you said the signals will be replicated as they are declared under generat= e statement, they will be interpreted as round_w(i), round_k(i) and round_s= (i) while implementing. Correct if I am wromg. Thanks again, Best Regards From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.224.47.129 with SMTP id n1mr201625qaf.4.1392285406698; Thu, 13 Feb 2014 01:56:46 -0800 (PST) X-Received: by 10.50.164.163 with SMTP id yr3mr38313igb.3.1392285406567; Thu, 13 Feb 2014 01:56:46 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f11no19219135qae.1!news-out.google.com!s3ni16790qas.0!nntp.google.com!c10no20159662igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 01:56:46 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.82.6; posting-account=vk2qlAoAAAD2nuTPtHmjhfYNJFzetXoe NNTP-Posting-Host: 14.139.82.6 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <02b5b279-1bda-4b96-9f6a-b33e4f0c6a25@googlegroups.com> Subject: Kode-da-Circiut Online VHDL Competition From: Ajit Mathew Injection-Date: Thu, 13 Feb 2014 09:56:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1790 X-Received-Body-CRC: 3230592599 Xref: news.eternal-september.org comp.lang.vhdl:7278 Felicity '14, brings brings to you one of it's kind, Online VHDL Coding, Kode Da Circuit. In this contest, participants have to come up with hardware solution for given problems which will be simulated using VHDL. This is a 24 hour event. The online judge will be using GHDL(http://ghdl.free.fr/) to simulate the VHDL codes. Problems will vary from designing simple circuits to complex hardware used for acceleration. We are currently running a familiarization phase (at http://felicity.iiit.ac.in/threads/kodedacircuit/) so that participants can be comfortable with the judge and the scoring system of the contest. The main event will be held on 15th of February at 2:30pm UTC. Cash prizes woth Rs 10,000 are up for grab. If you have any question reply to this thread. Ajit Mathew Organiser From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed4.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <52fc9f9b$0$25295$e4fe514c@dreader34.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Help using generate statement Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 11:34:03 +0100 References: <1d0d5b44-486a-4395-a4f8-5b67134fee79@googlegroups.com> <78978192-184f-4385-b8a6-25e3e5ed072c@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 66 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1392287643 dreader34.news.xs4all.nl 25295 puiterl/195.242.97.150:47693 Xref: news.eternal-september.org comp.lang.vhdl:7279 koyel.aphy@gmail.com wrote: > Thank you very much for your replies. Actually round_w, round_k and > round_s do not have indices as round_w(i), round_k(i) and round_s(i) as > usually the signals that are replicated under generate statements have but > I think as you said the signals will be replicated as they are declared > under generate statement, they will be interpreted as round_w(i), > round_k(i) and round_s(i) while implementing. Correct if I am wromg. The signals are local for each generate iteration. Just as variables are local to processes or subprograms, or signals declared in block statements. They can be declared multiple times with the same name, because they live in different scopes and don't see each other. The same goes for signals declared in a generate loop. How it is implemented, in don't know or care. As long as it follows the rules of the Language Reference Manual. Speaking of which, the LRM (2002 in this case) reads: "Elaboration of a generate statement consists of the replacement of the generate statement with zero or more copies of a block statement whose declarative part consists of the declarative items contained within the generate statement and whose statement part consists of the concurrent statements contained within the generate statement. These block statements are said to be represented by the generate statement. Each block statement is then elaborated." Example, also from the LRM: -- The following generate statement: LABL : for I in 1 to 2 generate signal s1 : INTEGER; begin s1 <= p1; Inst1 : and_gate port map (s1, p2(I), p3); end generate LABL; -- is equivalent to the following two block statements: LABL : block constant I : INTEGER := 1; signal s1 : INTEGER; begin s1 <= p1; Inst1 : and_gate port map (s1, p2(I), p3); end block LABL; LABL : block constant I : INTEGER := 2; signal s1 : INTEGER; begin s1 <= p1; Inst1 : and_gate port map (s1, p2(I), p3); end block LABL; I hope this answers your questions. Now that I look at the above example, I would not expect it to be allowed to use the same label for the two block statements... -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx26.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: Kode-da-Circiut Online VHDL Competition Newsgroups: comp.lang.vhdl References: <02b5b279-1bda-4b96-9f6a-b33e4f0c6a25@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 19 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1392290338 62.49.20.82 (Thu, 13 Feb 2014 11:18:58 UTC) NNTP-Posting-Date: Thu, 13 Feb 2014 11:18:58 UTC Date: Thu, 13 Feb 2014 11:18:58 GMT X-Received-Body-CRC: 3187321743 X-Received-Bytes: 1548 Xref: news.eternal-september.org comp.lang.vhdl:7280 On Thu, 13 Feb 2014 01:56:46 -0800, Ajit Mathew wrote: > Felicity '14, brings brings to you one of it's kind, Online VHDL Coding, > Kode Da Circuit. In this contest, participants have to come up with > hardware solution for given problems which will be simulated using VHDL. > > This is a 24 hour event. The online judge will be using > GHDL(http://ghdl.free.fr/) to simulate the VHDL codes. Problems will > vary from designing simple circuits to complex hardware used for > acceleration. Interesting competition! Please state which version of ghdl the judge is using. Many reported issues with ghdl-0.29 have been resolved in ghdl-0.31. https://sourceforge.net/projects/ghdl-updates/ - Brian From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.58.136.100 with SMTP id pz4mr352994veb.26.1392292190068; Thu, 13 Feb 2014 03:49:50 -0800 (PST) X-Received: by 10.50.22.243 with SMTP id h19mr50570igf.5.1392292189746; Thu, 13 Feb 2014 03:49:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.111.MISMATCH!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no19264050qaq.0!news-out.google.com!h8ni0igy.0!nntp.google.com!c10no20271571igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 03:49:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.82.6; posting-account=vk2qlAoAAAD2nuTPtHmjhfYNJFzetXoe NNTP-Posting-Host: 14.139.82.6 References: <02b5b279-1bda-4b96-9f6a-b33e4f0c6a25@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1aaf241d-16c6-4ee2-b365-ebed498a0f04@googlegroups.com> Subject: Re: Kode-da-Circiut Online VHDL Competition From: Ajit Mathew Injection-Date: Thu, 13 Feb 2014 11:49:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1504 X-Received-Body-CRC: 243203135 Xref: news.eternal-september.org comp.lang.vhdl:7281 > Interesting competition! > > > > Please state which version of ghdl the judge is using. > > Many reported issues with ghdl-0.29 have been resolved in ghdl-0.31. > > > > https://sourceforge.net/projects/ghdl-updates/ > > > > - Brian Hi Brian, We are using GHDL 0.29 version. We will try to update it to 0.31 for the main event on 15th. Thanks. Ajit From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.195.75 with SMTP id ic11mr2079683obc.31.1392350443402; Thu, 13 Feb 2014 20:00:43 -0800 (PST) X-Received: by 10.182.3.12 with SMTP id 12mr3975oby.36.1392350443152; Thu, 13 Feb 2014 20:00:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no21298309igq.0!news-out.google.com!h8ni8igy.0!nntp.google.com!c10no21298298igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 20:00:42 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=69.114.113.165; posting-account=MjRvlAoAAAAtZVSkPwQVdYstOujWTQNb NNTP-Posting-Host: 69.114.113.165 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> Subject: 2bit- comparator -- VDHL Error in ModelSim about this Script. From: quaere1verum@gmail.com Injection-Date: Fri, 14 Feb 2014 04:00:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7282 The error info is not descriptive. Anyone catches it? Library ieee; Use ieee.std_logic_1164.all; -- I am trying to simulate the logic below -- aeqb = (a1'.b1').(a0'.b0') + (a1'.b1').(a0.b0) + (a1.b1).(a0'b0') + (a1.b1).(a0.b0) Entity two_bit_equal is Port ( a, b: in std_logic_vector(1 downto 0); aeqb : out std_logic); End two_bit_equal; Architecture arch of two_bit_equal is Signal p0, p1,p2,p3 : std_logic; begin aeqb <= (p0 or p1) or (p2 or p3); P0 <= (a(1) and b(1)) or (a(0)and b(0)); P1<= (a(1)and b(1)) and ( (not a(0)) and (not b(0))); P2<= ( (not a(1)) and (not b(1))) and (a(0) and b(0)); P3 <= ( (not a(1)) and (not b(1)) ) and ( (not a(0)) and (not b(0)) ); End arch; From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.42.250.196 with SMTP id mp4mr1801237icb.29.1392351143075; Thu, 13 Feb 2014 20:12:23 -0800 (PST) X-Received: by 10.182.33.4 with SMTP id n4mr45339obi.9.1392351142839; Thu, 13 Feb 2014 20:12:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no21306743igq.0!news-out.google.com!h8ni8igy.0!nntp.google.com!c10no21306737igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 20:12:22 -0800 (PST) In-Reply-To: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=69.114.113.165; posting-account=MjRvlAoAAAAtZVSkPwQVdYstOujWTQNb NNTP-Posting-Host: 69.114.113.165 References: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2efa1b55-be3c-47d0-a67c-fb440099a044@googlegroups.com> Subject: Re: 2bit- comparator -- VDHL Error in ModelSim about this Script. From: quaere1verum@gmail.com Injection-Date: Fri, 14 Feb 2014 04:12:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7283 The test file I am using is this: -- =================================== Library ieee; Use ieee.std_logic_1164.all; Entity Test_two_bit_equal is End Test_two_bit_equal; Architecture arch_test of test_two_bit_equal is component two_bit_equal Port ( a, b: in std_logic_vector(1 downto 0); aeqb : out std_logic); End component; Signal p1, p0 : std_logic_vector(1 downto 0); Signal pout : std_logic; Signal error : std_logic := '0'; begin uut: two_bit_equal port map(a => p0, b => p1, aeqb => pout); process begin p0 <= "00"; p1 <= "00"; wait for 1 ns; if (pout = '0') then error <= '1'; end if; wait for 200 ns; p0 <= "01"; p1 <= "00"; wait for 1 ns; if (pout = '1') then error <= '1'; end if; wait for 200 ns; p0 <= "01"; p1 <= "11"; wait for 1 ns; if (pout = '1') then error <= '1'; end if; wait for 200 ns; p0 <= "11"; p1 <= "00"; wait for 1 ns; if (pout = '1') then error <= '1'; end if; wait for 200 ns; p0 <= "11"; p1 <= "11"; wait for 1 ns; if (pout = '0') then error <= '1'; end if; wait for 200 ns; p0 <= "10"; p1 <= "11"; wait for 1 ns; if (pout = '1') then error <= '1'; end if; wait for 200 ns; p0 <= "10"; p1 <= "10"; wait for 1 ns; if (pout = '0') then error <= '1'; end if; wait for 200 ns; p0 <= "11"; p1 <= "01"; wait for 1 ns; if (pout = '1') then error <= '1'; end if; wait for 200 ns; if (error = '0') then report "No errors detected. Simulation successful" severity failure; else report "Error detected" severity failure; end if; end process; End arch_test; From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.186.105 with SMTP id fj9mr2202563obc.5.1392354327609; Thu, 13 Feb 2014 21:05:27 -0800 (PST) X-Received: by 10.50.22.243 with SMTP id h19mr17122igf.5.1392354327426; Thu, 13 Feb 2014 21:05:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no19817288igb.0!news-out.google.com!rw17ni2igc.0!nntp.google.com!uq10no19817279igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 21:05:26 -0800 (PST) In-Reply-To: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.133.180; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.133.180 References: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03f12d91-1fb2-4ea2-a9b1-95272442d300@googlegroups.com> Subject: Re: 2bit- comparator -- VDHL Error in ModelSim about this Script. From: Dio Gratia Injection-Date: Fri, 14 Feb 2014 05:05:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7284 On Friday, February 14, 2014 5:00:42 PM UTC+13, quaere...@gmail.com wrote: > The error info is not descriptive. Anyone catches it? Yes. > > -- I am trying to simulate the logic below P0 P1 P2 > -- aeqb = (a1'.b1').(a0'.b0') + (a1'.b1').(a0.b0) + (a1.b1).(a0'b0') + _ P3 > (a1.b1).(a0.b0) > > P0 <= (a(1) and b(1)) or (a(0)and b(0)); Should be: P0 <= (a(1) and b(1)) and (a(0)and b(0)); (And ya, I simulated it with your test bench.) % ghdl -a two_bit_equal.vhdl % ghdl -e Test_two_bit_equal david_koontz@Macbook: ghdl -r Test_two_bit_equal --wave=twobit.ghw two_bit_equal.vhdl:203:12:@1608ns:(report failure): No errors detected. Simulation successful ./test_two_bit_equal:error: report failed ./test_two_bit_equal:error: simulation failed ghdl: compilation error (And you could have ended simulation with a wait; statement). From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.24.5 with SMTP id q5mr2163759obf.23.1392354793562; Thu, 13 Feb 2014 21:13:13 -0800 (PST) X-Received: by 10.182.17.67 with SMTP id m3mr6155obd.23.1392354793357; Thu, 13 Feb 2014 21:13:13 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no19823344igb.0!news-out.google.com!h8ni8igy.0!nntp.google.com!c10no21352796igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 13 Feb 2014 21:13:13 -0800 (PST) In-Reply-To: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=69.114.113.165; posting-account=MjRvlAoAAAAtZVSkPwQVdYstOujWTQNb NNTP-Posting-Host: 69.114.113.165 References: <6a5a103f-f6b9-4b03-b61f-f9ffe9fd9389@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: 2bit- comparator -- VDHL Error in ModelSim about this Script. From: quaere1verum@gmail.com Injection-Date: Fri, 14 Feb 2014 05:13:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7285 Thank you all, the error was trivial. Notice P0 leftmost statement. The error is that it should be AND and not OR Correct == (a1.b1).(a0.b0) P0 <= (a(1) and b(1)) and (a(0)and b(0)); From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.129.129 with SMTP id nw1mr3214822obb.34.1392392415795; Fri, 14 Feb 2014 07:40:15 -0800 (PST) X-Received: by 10.182.204.42 with SMTP id kv10mr11239obc.33.1392392415622; Fri, 14 Feb 2014 07:40:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no22033847igq.0!news-out.google.com!h8ni8igy.0!nntp.google.com!c10no22033835igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Feb 2014 07:40:15 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7299eb6b-420b-4d60-9754-eefbc70cab0a@googlegroups.com> Subject: How to implement an irragular table? From: fl Injection-Date: Fri, 14 Feb 2014 15:40:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7286 Hi, I want to implement a table, which has nonlinear input. For example, its input has 7 segmentations: Segmentation........... Mapping ratio 1-511.................. 1 : 1 512-1023............... 1 : 2 1024-2047.............. 1 : 4 2048-4095.............. 1 : 8 4096-8191.............. 1 : 16 8192-16383............. 1 : 32 16384-32767............ 1 : 64 Thus, the first row has 511 entries while all others have 256 entries. There are values (26 bits in wordlength) corresponding to these entries. I am new to VHDL. It looks like a lookup table, but the nonlinear entries make me feel difficult. Could you help me on this problem? Thanks, From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!border2.nntp.ams2.giganews.com!backlog4.nntp.ams3.giganews.com!backlog4.nntp.ams.giganews.com!border2.nntp.ams.giganews.com!nntp.giganews.com!news.astraweb.com!border5.a.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to implement an irragular table? Newsgroups: comp.lang.vhdl References: <7299eb6b-420b-4d60-9754-eefbc70cab0a@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 15 Feb 2014 23:24:02 GMT Lines: 61 Message-ID: <52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 4c0f0a4e.news.astraweb.com X-Trace: DXC=X0P_=;L0k:UaaSDeVe\e2]L?0kYOcDh@Z7^o:UA4R?cUel::[kgGj3R]G;2>V^?kWS2Of6BS7?ncZNL\jPCROYGQMPI=dacFNnT X-Original-Bytes: 3463 Xref: news.eternal-september.org comp.lang.vhdl:7287 On Fri, 14 Feb 2014 07:40:15 -0800, fl wrote: > Hi, > > I want to implement a table, which has nonlinear input. For example, its > input has 7 segmentations: > > Segmentation........... Mapping ratio 1-511.................. 1 : 1 > 512-1023............... 1 : 2 1024-2047.............. 1 : 4 > 2048-4095.............. 1 : 8 4096-8191.............. 1 : 16 > 8192-16383............. 1 : 32 16384-32767............ 1 : 64 > > Thus, the first row has 511 entries while all others have 256 entries. > There are values (26 bits in wordlength) corresponding to these entries. > > I am new to VHDL. It looks like a lookup table, but the nonlinear > entries make me feel difficult. Could you help me on this problem? > > > Thanks, This reminds of the time I implemented a very fast integer log2 function that could return one (pipelined) result every clock. I have no idea whether this is relevant to your problem though, but you might get something out of the following description. The first thing I did was to check for a value of zero at the input. Zero was a special case (as log(0) isn't a regular number) and won't be considered further here. Next I counted the number of leading zeros in the input word, using some simple logic expressed in a few lines of VHDL. This number corresponded to the "segment" in your post. I will call this number the "exponent". Next I used a barrel shifter (a few lines of VHDL) to shift the input word to the left by the number of leading zeros calculated in the previous stage. At the output of the shifter (which I will call the "mantissa"), the leftmost bit will be '1', of course (as we shifted by the number of leading zeros and we are ignoring the special case of all zeros input). Next I took several of the most significant bits of the mantissa (but not the most significant bit which is always 1 and carries no information) and used them as an input to a lookup table implemented in a single FPGA block ram. The contents of the lookup table were precalculated (in a spreadsheet) to be log2 over a range of [1, 2), giving results over [0, 1). Log2 is fairly smooth in this range (it's close to a straight line), so I didn't need to use a particularly wide or deep table to get my desired accuracy. For more accuracy I could have coded this table as the deviation from a straight line then added the input to the output, but I did not need to do that. The final result was the exponent concatenated with the output of the lookup table. I hope that helps, or at least does not confuse. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.68.231.233 with SMTP id tj9mr7187985pbc.2.1392517712491; Sat, 15 Feb 2014 18:28:32 -0800 (PST) X-Received: by 10.140.105.181 with SMTP id c50mr1910qgf.12.1392517712439; Sat, 15 Feb 2014 18:28:32 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!c10no24343407igq.0!news-out.google.com!s3ni20101qas.0!nntp.google.com!f11no21313069qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Feb 2014 18:28:32 -0800 (PST) In-Reply-To: <52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <7299eb6b-420b-4d60-9754-eefbc70cab0a@googlegroups.com> <52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <657d4302-6acb-44ad-9dba-20963a1d615c@googlegroups.com> Subject: Re: How to implement an irragular table? From: fl Injection-Date: Sun, 16 Feb 2014 02:28:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1804 X-Received-Body-CRC: 2723417758 Xref: news.eternal-september.org comp.lang.vhdl:7288 Thanks Allan. Your post really gives me some fresh view on my question. I m= ay start in your idea later. After I sort through my question, I think that I care about resource cost f= or a Xilinx Spartan 6 now. The input has 15 bits for 0...32767 while there = are total 2048 distinct value corresponding to these entries. A straight fo= rward look up table works, which looks like a 15-bit input, 26-bit output t= able.=20 My question now is whether there is a structure less than the above design,= because there are only 2048 (11-bit, not 15-bit) output distinct values. Thanks, From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.236.134.174 with SMTP id s34mr6937906yhi.32.1392553107553; Sun, 16 Feb 2014 04:18:27 -0800 (PST) X-Received: by 10.140.85.179 with SMTP id n48mr52091qgd.6.1392553107536; Sun, 16 Feb 2014 04:18:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no21482077qaq.0!news-out.google.com!dr7ni182qab.1!nntp.google.com!f11no21511059qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Feb 2014 04:18:27 -0800 (PST) In-Reply-To: <52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <7299eb6b-420b-4d60-9754-eefbc70cab0a@googlegroups.com> <52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31466768-7d79-49c8-836e-e2f86df50585@googlegroups.com> Subject: Re: How to implement an irragular table? From: fl Injection-Date: Sun, 16 Feb 2014 12:18:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4641 X-Received-Body-CRC: 1515619714 Xref: news.eternal-september.org comp.lang.vhdl:7289 On Saturday, February 15, 2014 6:24:02 PM UTC-5, Allan Herriman wrote: > On Fri, 14 Feb 2014 07:40:15 -0800, fl wrote: > > > > > Hi, > > > > > > I want to implement a table, which has nonlinear input. For example, its > > > input has 7 segmentations: > > > > > > Segmentation........... Mapping ratio 1-511.................. 1 : 1 > > > 512-1023............... 1 : 2 1024-2047.............. 1 : 4 > > > 2048-4095.............. 1 : 8 4096-8191.............. 1 : 16 > > > 8192-16383............. 1 : 32 16384-32767............ 1 : 64 > > > > > > Thus, the first row has 511 entries while all others have 256 entries. > > > There are values (26 bits in wordlength) corresponding to these entries. > > > > > > I am new to VHDL. It looks like a lookup table, but the nonlinear > > > entries make me feel difficult. Could you help me on this problem? > > > > > > > > > Thanks, > > > > This reminds of the time I implemented a very fast integer log2 function > > that could return one (pipelined) result every clock. > > I have no idea whether this is relevant to your problem though, but you > > might get something out of the following description. > > > > The first thing I did was to check for a value of zero at the input. > > Zero was a special case (as log(0) isn't a regular number) and won't be > > considered further here. > > > > Next I counted the number of leading zeros in the input word, using some > > simple logic expressed in a few lines of VHDL. This number corresponded > > to the "segment" in your post. I will call this number the "exponent". > > > > Next I used a barrel shifter (a few lines of VHDL) to shift the input > > word to the left by the number of leading zeros calculated in the > > previous stage. At the output of the shifter (which I will call the > > "mantissa"), the leftmost bit will be '1', of course (as we shifted by > > the number of leading zeros and we are ignoring the special case of all > > zeros input). > > > > Next I took several of the most significant bits of the mantissa (but not > > the most significant bit which is always 1 and carries no information) > > and used them as an input to a lookup table implemented in a single FPGA > > block ram. > > > > The contents of the lookup table were precalculated (in a spreadsheet) to > > be log2 over a range of [1, 2), giving results over [0, 1). Log2 is > > fairly smooth in this range (it's close to a straight line), so I didn't > > need to use a particularly wide or deep table to get my desired accuracy. > > For more accuracy I could have coded this table as the deviation from a > > straight line then added the input to the output, but I did not need to > > do that. > > > > The final result was the exponent concatenated with the output of the > > lookup table. > > > > I hope that helps, or at least does not confuse. > > > > Regards, > > Allan I have found a solution for my problem. It is about using stages to get the value out. Your method is really stimulating to me. Just one thing I need you more information. "For more accuracy I could have coded this table as the deviation from a straight line then added the input to the output, but I did not need to do that." Could you give me a little more detail on above? Thanks again. From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to implement an irragular table? Newsgroups: comp.lang.vhdl References: <7299eb6b-420b-4d60-9754-eefbc70cab0a@googlegroups.com> < 52fff712$0$29885$c3e8da3$5496439d@news.astraweb.com> < 31466768-7d79-49c8-836e-e2f86df50585@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 16 Feb 2014 13:58:21 GMT Lines: 168 Message-ID: <5300c3fd$0$29870$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 3cec81fd.news.astraweb.com X-Trace: DXC=52Yh[`CekkO0UO2<>T]L;AL?0kYOcDh@J7^o:UA4R?cEFRPSXaZN\EB]G;2>V^?kWC2Of6BS7?ncJNL\jPCROYGA]H40H3`e]QF Xref: news.eternal-september.org comp.lang.vhdl:7290 On Sun, 16 Feb 2014 04:18:27 -0800, fl wrote: > On Saturday, February 15, 2014 6:24:02 PM UTC-5, Allan Herriman wrote: >> On Fri, 14 Feb 2014 07:40:15 -0800, fl wrote: >> >> >> >> > Hi, >> >> >> > >> > I want to implement a table, which has nonlinear input. For example, >> > its >> >> > input has 7 segmentations: >> >> >> > >> > Segmentation........... Mapping ratio 1-511.................. 1 : 1 >> >> > 512-1023............... 1 : 2 1024-2047.............. 1 : 4 >> >> > 2048-4095.............. 1 : 8 4096-8191.............. 1 : 16 >> >> > 8192-16383............. 1 : 32 16384-32767............ 1 : 64 >> >> >> > >> > Thus, the first row has 511 entries while all others have 256 >> > entries. >> >> > There are values (26 bits in wordlength) corresponding to these >> > entries. >> >> >> > >> > I am new to VHDL. It looks like a lookup table, but the nonlinear >> >> > entries make me feel difficult. Could you help me on this problem? >> >> >> > >> >> > >> > Thanks, >> >> >> >> This reminds of the time I implemented a very fast integer log2 >> function >> >> that could return one (pipelined) result every clock. >> >> I have no idea whether this is relevant to your problem though, but you >> >> might get something out of the following description. >> >> >> >> The first thing I did was to check for a value of zero at the input. >> >> Zero was a special case (as log(0) isn't a regular number) and won't be >> >> considered further here. >> >> >> >> Next I counted the number of leading zeros in the input word, using >> some >> >> simple logic expressed in a few lines of VHDL. This number >> corresponded >> >> to the "segment" in your post. I will call this number the "exponent". >> >> >> >> Next I used a barrel shifter (a few lines of VHDL) to shift the input >> >> word to the left by the number of leading zeros calculated in the >> >> previous stage. At the output of the shifter (which I will call the >> >> "mantissa"), the leftmost bit will be '1', of course (as we shifted by >> >> the number of leading zeros and we are ignoring the special case of all >> >> zeros input). >> >> >> >> Next I took several of the most significant bits of the mantissa (but >> not >> >> the most significant bit which is always 1 and carries no information) >> >> and used them as an input to a lookup table implemented in a single >> FPGA >> >> block ram. >> >> >> >> The contents of the lookup table were precalculated (in a spreadsheet) >> to >> >> be log2 over a range of [1, 2), giving results over [0, 1). Log2 is >> >> fairly smooth in this range (it's close to a straight line), so I >> didn't >> >> need to use a particularly wide or deep table to get my desired >> accuracy. >> >> For more accuracy I could have coded this table as the deviation from a >> >> straight line then added the input to the output, but I did not need to >> >> do that. >> >> >> >> The final result was the exponent concatenated with the output of the >> >> lookup table. >> >> >> >> I hope that helps, or at least does not confuse. >> >> >> >> Regards, >> >> Allan > > I have found a solution for my problem. It is about using stages to get > the value out. > Your method is really stimulating to me. Just one thing I need you more > information. > > "For more accuracy I could have coded this table as the deviation from a > straight line then added the input to the output, but I did not need to > do that." > > Could you give me a little more detail on above? Thanks again. I meant that instead of using a table to hold the value of log2(x+1) function over the range [0,1), you could instead use the function log2(x +1)-(x+1), then add the input (x+1) after the table lookup using a regular adder. BTW, the '1' comes from the most significant bit of the mantissa that is always 1 (that we discarded). In floating point parlance it is called a "hidden bit" or "implicit bit". Compare the functions log2(x) with log2(x)-x with x in the range [1,2) and you will see that log2(x) has outputs in the range of [0,1) whereas log2(x)-x has outputs in the range [0, 0.087]. This means you need three bits less table width for a given accuracy, or (more likely) 3 bits more accuracy for a given width of lookup table, for the cost of one adder. If your table already takes only 1 block ram and meets your accuracy goal, this isn't an improvement. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.19.164 with SMTP id g4mr9895047obe.21.1392627807824; Mon, 17 Feb 2014 01:03:27 -0800 (PST) X-Received: by 10.140.34.147 with SMTP id l19mr11447qgl.30.1392627807749; Mon, 17 Feb 2014 01:03:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!c10no26185716igq.0!news-out.google.com!dr7ni182qab.1!nntp.google.com!f11no22026587qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Feb 2014 01:03:27 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.156.133.130; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx NNTP-Posting-Host: 217.156.133.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: How to instantiate a verilog block inside a VHDL entity? From: thunder Injection-Date: Mon, 17 Feb 2014 09:03:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7291 Hello My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block. QS: Is it possible to instantiate a verilog block inside a VHDL block? QS: If the answer to the above question is yes, how to achieve this? Thanks in advance JO From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!news.tele.dk!news.tele.dk!small.news.tele.dk!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-ID: <5301e130$0$25270$e4fe514c@dreader34.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: How to instantiate a verilog block inside a VHDL entity? Newsgroups: comp.lang.vhdl Date: Mon, 17 Feb 2014 11:15:12 +0100 References: Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 22 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1392632112 dreader34.news.xs4all.nl 25270 puiterl/195.242.97.150:42030 Xref: news.eternal-september.org comp.lang.vhdl:7292 thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog > block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? Yes. > QS: If the answer to the above question is yes, how to achieve this? Declare a component for the Verilog module and instantiate it just like any other VHDL component. Check your simulator user's manual for details. -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to instantiate a verilog block inside a VHDL entity? Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 17 Feb 2014 12:46:24 GMT Lines: 84 Message-ID: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: e767c192.news.astraweb.com X-Trace: DXC=Z1^F3Se[UW?YCNS1UYSjA1L?0kYOcDh@:7^o:UA4R?c5\g^KX1`]9C=]G;2>V^?kW32Of6BS7?nc:NL\jPCROYG1mO`cXa>28Z4 Xref: news.eternal-september.org comp.lang.vhdl:7293 On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog > block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > QS: If the answer to the above question is yes, how to achieve this? > > Thanks in advance My experience is that it is possible to instantiate a verilog module inside a VHDL architecture, both using component instantiation and entity instantiation, in most tools, for both synthesis and simulation. Significantly, Altera Quartus does not allow entity instantiation, which means if you want Altera compatibility you will need to write a component declaration for each Verilog module. Things that don't work the way you'd want: - heirarchical references typically can't go across a VHDL/Verilog boundary. Things to avoid for portability: - (for ports) types other than std_logic, std_logic_vector - (for generics/parameters) types other than integer and string - in some tools (e.g. older Modelsim), port mappings can only be to signals. It is not possible to map a port to a constant, for example. Example: module foo #( parameter bar = 1 ) ( input wire bletch, output reg baz = 1'b0 ); You could instantiate this as an entity, provided that it has already been compiled into the work library: some_label : entity work.foo generic map ( bar => 2 ) port map ( bletch => signal1, baz => signal2 ); Or if you really like typing you could instantiate module foo as a component: component foo is generic ( bar : integer := 1 ); port ( bletch : in std_logic; baz : out std_logic ); end component foo; ... some_label : component foo generic map ( bar => 2 ) port map ( bletch => signal1, baz => signal2 ); Note that the keyword "component" is optional in a component instantiation. Most people leave it out. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to instantiate a verilog block inside a VHDL entity? Date: Mon, 17 Feb 2014 16:26:35 -0500 Organization: Alacron, Inc. Lines: 109 Message-ID: References: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 17 Feb 2014 21:27:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="2416"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19sz0S+xSpZjxl/RIMKiJBIT06bf8B8fMI=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:Rtpg6etr6pqEFnMq7Lw6owZygRE= Xref: news.eternal-september.org comp.lang.vhdl:7294 Allan Herriman wrote: > On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote: > >> Hello >> >> >> My design consists of VHDL blocks. Now i need to instantiate a verilog >> block inside my VHDL block. >> >> QS: Is it possible to instantiate a verilog block inside a VHDL block? >> QS: If the answer to the above question is yes, how to achieve this? >> >> Thanks in advance > > My experience is that it is possible to instantiate a verilog module > inside a VHDL architecture, both using component instantiation and entity > instantiation, in most tools, for both synthesis and simulation. > > Significantly, Altera Quartus does not allow entity instantiation, which > means if you want Altera compatibility you will need to write a component > declaration for each Verilog module. > > Things that don't work the way you'd want: > - heirarchical references typically can't go across a VHDL/Verilog > boundary. > > Things to avoid for portability: > - (for ports) types other than std_logic, std_logic_vector > - (for generics/parameters) types other than integer and string > - in some tools (e.g. older Modelsim), port mappings can only be to > signals. It is not possible to map a port to a constant, for example. > > > Example: > > module foo > #( > parameter bar = 1 > ) > ( > input wire bletch, > output reg baz = 1'b0 > ); > > You could instantiate this as an entity, provided that it has already > been compiled into the work library: > > some_label : entity work.foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Or if you really like typing you could instantiate module foo as a > component: > > component foo is > generic ( > bar : integer := 1 > ); > port ( > bletch : in std_logic; > baz : out std_logic > ); > end component foo; > > ... > > some_label : component foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Note that the keyword "component" is optional in a component > instantiation. Most people leave it out. > > Regards, > Allan The last time I did this with Xilinx tools (ISE) I found I needed to use a component instantiation. However I didn't need to do much typing because once you add the verilog module to the project you can "View instantiation template" which generates the required component declaration as well as the instantiation template to paste into your VHDL code. Some other things to avoid are Verilog port names with upper and lower case, especially not having ports that differ *only* in the case of the name like: module foobar ( input wire FOO, input wire Foo, output reg foo ); which is legal Verilog, but can wreak havoc when you try to instantiate it from VHDL. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.224.55.129 with SMTP id u1mr11750897qag.6.1392695514535; Mon, 17 Feb 2014 19:51:54 -0800 (PST) X-Received: by 10.50.50.39 with SMTP id z7mr344094ign.0.1392695514201; Mon, 17 Feb 2014 19:51:54 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no22505354qaq.0!news-out.google.com!h8ni12igy.0!nntp.google.com!uq10no25967908igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Feb 2014 19:51:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=InKtjwoAAADGcfo0qx53UFf1Ya_UtGvZ NNTP-Posting-Host: 115.187.63.199 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <343518c6-387c-422b-a99d-f2209443c637@googlegroups.com> Subject: help regarding an open source From: koyel.aphy@gmail.com Injection-Date: Tue, 18 Feb 2014 03:51:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1638 X-Received-Body-CRC: 3467844332 Xref: news.eternal-september.org comp.lang.vhdl:7295 Hi, Can someone tell what top.vhd is doing, which can be found in the list of v= hdl codes in the following link https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/pr= ojects/VHDL_Xilinx_Port It appears to me that load always contain some undefined bits as it is unde= fined initially and rxdata fills only 8 bits (0 to 7) of load and further t= hese 8 bits are transferred to the bits from 8 to 15 so ultimately only 0 t= o 15 will contain 1s or 0s and the rest will be undefined. If this happens = state and data will contain undefined values and then how the code will wor= k? Thanks, Regards From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <5303307b$0$9231$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: help regarding an open source Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2014 11:05:47 +0100 References: <343518c6-387c-422b-a99d-f2209443c637@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 39 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1392717947 dreader35.news.xs4all.nl 9231 puiterl/195.242.97.150:52464 Xref: news.eternal-september.org comp.lang.vhdl:7296 koyel.aphy@gmail.com wrote: > Hi, > > Can someone tell what top.vhd is doing, which can be found in the list of > vhdl codes in the following link > > https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_Xilinx_Port > > It appears to me that load always contain some undefined bits as it is > undefined initially and rxdata fills only 8 bits (0 to 7) of load and > further these 8 bits are transferred to the bits from 8 to 15 so > ultimately only 0 to 15 will contain 1s or 0s and the rest will be > undefined. If this happens state and data will contain undefined values > and then how the code will work? I do not know where you get the idea from that only 8 bits are transferred to bits 8 to 15. Lines 180 and 181 form a 344 bit shift register, where one byte of data is shifted in at a time: 180: load(343 downto 8) <= load(335 downto 0); 181: load(7 downto 0) <= rxdata; The upper eight bits are shifted out, to lower eight bits receive the data. The two lines just as well could have been written as one line: load <= load(335 downto 0) & rxdata; For the rest of the functionality of top.vhd: no idea, if have not looked into it any further. -- Paul Uiterlinden AimValley From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.111.227 with SMTP id il3mr12857897obb.41.1392721307995; Tue, 18 Feb 2014 03:01:47 -0800 (PST) X-Received: by 10.50.115.71 with SMTP id jm7mr417854igb.14.1392721307800; Tue, 18 Feb 2014 03:01:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no27380524igb.0!news-out.google.com!h8ni16igy.0!nntp.google.com!c10no28901697igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2014 03:01:47 -0800 (PST) In-Reply-To: <5303307b$0$9231$e4fe514c@dreader35.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=InKtjwoAAADGcfo0qx53UFf1Ya_UtGvZ NNTP-Posting-Host: 115.187.63.199 References: <343518c6-387c-422b-a99d-f2209443c637@googlegroups.com> <5303307b$0$9231$e4fe514c@dreader35.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52bc24a0-2815-426b-9d5b-347c44eaa863@googlegroups.com> Subject: Re: help regarding an open source From: koyel.aphy@gmail.com Injection-Date: Tue, 18 Feb 2014 11:01:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7297 got it. Thank you very much! Further information on top.vhd is welcome. Best Regards, From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to instantiate a verilog block inside a VHDL entity? Newsgroups: comp.lang.vhdl References: < 530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 18 Feb 2014 13:05:39 GMT Lines: 115 Message-ID: <53035aa3$0$2888$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: f7e951a9.news.astraweb.com X-Trace: DXC=PJPZ<6EG5VlMm1IZKF?@MbL?0kYOcDh@j@lQVJW>eJke2243=N_ Allan Herriman wrote: >> On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote: >> >>> Hello >>> >>> >>> My design consists of VHDL blocks. Now i need to instantiate a verilog >>> block inside my VHDL block. >>> >>> QS: Is it possible to instantiate a verilog block inside a VHDL block? >>> QS: If the answer to the above question is yes, how to achieve this? >>> >>> Thanks in advance >> >> My experience is that it is possible to instantiate a verilog module >> inside a VHDL architecture, both using component instantiation and >> entity instantiation, in most tools, for both synthesis and simulation. >> >> Significantly, Altera Quartus does not allow entity instantiation, >> which means if you want Altera compatibility you will need to write a >> component declaration for each Verilog module. >> >> Things that don't work the way you'd want: >> - heirarchical references typically can't go across a VHDL/Verilog >> boundary. >> >> Things to avoid for portability: >> - (for ports) types other than std_logic, std_logic_vector - (for >> generics/parameters) types other than integer and string - in some >> tools (e.g. older Modelsim), port mappings can only be to signals. It >> is not possible to map a port to a constant, for example. >> >> >> Example: >> >> module foo #( >> parameter bar = 1 >> ) >> ( >> input wire bletch, output reg baz = 1'b0 >> ); >> >> You could instantiate this as an entity, provided that it has already >> been compiled into the work library: >> >> some_label : entity work.foo generic map ( >> bar => 2 >> ) >> port map ( >> bletch => signal1, baz => signal2 >> ); >> >> Or if you really like typing you could instantiate module foo as a >> component: >> >> component foo is generic ( >> bar : integer := 1 >> ); >> port ( >> bletch : in std_logic; >> baz : out std_logic >> ); >> end component foo; >> >> ... >> >> some_label : component foo generic map ( >> bar => 2 >> ) >> port map ( >> bletch => signal1, baz => signal2 >> ); >> >> Note that the keyword "component" is optional in a component >> instantiation. Most people leave it out. >> >> Regards, >> Allan > > The last time I did this with Xilinx tools (ISE) I found I needed to use > a component instantiation. Entity instantiation of Verilog in VHDL works as far back as ISE 6.3 (possibly earlier, but that is the oldest version I can test right now). A co-worker advised that it's broken again in ISE 14.7 for Virtex 4 but not Virtex 6 or 7 targets - something to do with the "old" parser and "new" parser switch. I haven't tried it in Vivado yet. > Some other things to avoid are Verilog port names with upper and lower > case, especially not having ports that differ *only* in the case of the > name like: > > module foobar ( > input wire FOO, > input wire Foo, > output reg foo > ); > > which is legal Verilog, but can wreak havoc when you try to instantiate > it from VHDL. Another thing that has bitten me in the past was port names that are VHDL keywords. "In" and "out" seem popular port names in Verilog, and don't work so well in VHDL. I also recall that an old Xilinx Unisim model (CLBRAM, I think) had a port called "do" (data output) which causes probnlems for the same reason. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:18 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to instantiate a verilog block inside a VHDL entity? Date: Tue, 18 Feb 2014 10:04:04 -0500 Organization: Alacron, Inc. Lines: 29 Message-ID: References: < 530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> <53035aa3$0$2888$c3e8da3$76491128@news.astraweb.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Feb 2014 15:05:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="27034"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ui8rUT/i0Ih0HQKlrK4FrEGcOfIWKw0Q=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <53035aa3$0$2888$c3e8da3$76491128@news.astraweb.com> Cancel-Lock: sha1:sqgcJsd77hiEQasNdXkPuxZfUl4= Xref: news.eternal-september.org comp.lang.vhdl:7299 Allan Herriman wrote: > On Mon, 17 Feb 2014 16:26:35 -0500, GaborSzakacs wrote: > >> Allan Herriman wrote: [snip] > > > Another thing that has bitten me in the past was port names that are VHDL > keywords. "In" and "out" seem popular port names in Verilog, and don't > work so well in VHDL. > > I also recall that an old Xilinx Unisim model (CLBRAM, I think) had a > port called "do" (data output) which causes probnlems for the same reason. > > Regards, > Allan I've seen other weird problems in XST with mixed language projects. For example I found that if I had code in Verilog and VHDL that each used the same library primitive (e.g. RAMB16_S9_S9) XST would rename one of them with a suffix (e.g. RAMB16_S9_S9_1) and then barf because it couldn't find the renamed unit in any library. In general I've found mixed language projects to be a headache. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.66.145.105 with SMTP id st9mr6991907pab.23.1392753399730; Tue, 18 Feb 2014 11:56:39 -0800 (PST) X-Received: by 10.140.102.139 with SMTP id w11mr34142qge.37.1392753399655; Tue, 18 Feb 2014 11:56:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!uq10no28345015igb.0!news-out.google.com!dr7ni182qab.1!nntp.google.com!f11no23630767qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2014 11:56:39 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <84de1543-d2c2-4899-8b9d-4ab63e17750d@googlegroups.com> Subject: pipeline and low power relationship From: fl Injection-Date: Tue, 18 Feb 2014 19:56:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7300 Hi, Excuse me I post this question here because I think it is related to VHDL d= esign than other algorithm groups. Pipeline is heavily used in VHDL design.= I read the book "VLSI digital signal processing systems" by K. K. Parhi. I= t says that pipeline and parallel design can lower power consumption. More = specifically, pipeline can "increase the sample clock or to reduce the powe= r consumption at same speed." (Parhi)=20 I personally have a guess about the above statement. Is it implicitly assum= ing that power consumption increases very fast with sample clock? Anyway, I= still cannot imagine "to reduce the power consumption at same speed." I do not find relevant example on that book or on-line. Could you explain i= t to me? Thanks, From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.67.14.70 with SMTP id fe6mr194526pad.15.1392795748056; Tue, 18 Feb 2014 23:42:28 -0800 (PST) X-Received: by 10.140.94.173 with SMTP id g42mr3238qge.34.1392795747997; Tue, 18 Feb 2014 23:42:27 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no29308691igb.0!news-out.google.com!dr7ni182qab.1!nntp.google.com!f11no24024764qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Feb 2014 23:42:27 -0800 (PST) In-Reply-To: <84de1543-d2c2-4899-8b9d-4ab63e17750d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: <84de1543-d2c2-4899-8b9d-4ab63e17750d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: pipeline and low power relationship From: goouse99@gmail.com Injection-Date: Wed, 19 Feb 2014 07:42:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7301 Am Dienstag, 18. Februar 2014 20:56:39 UTC+1 schrieb fl: > Hi, >=20 >=20 >=20 > Excuse me I post this question here because I think it is related to VHDL= design than other algorithm groups. Pipeline is heavily used in VHDL desig= n. I read the book "VLSI digital signal processing systems" by K. K. Parhi.= It says that pipeline and parallel design can lower power consumption. Mor= e specifically, pipeline can "increase the sample clock or to reduce the po= wer consumption at same speed." (Parhi)=20 >=20 >=20 >=20 > I personally have a guess about the above statement. Is it implicitly ass= uming that power consumption increases very fast with sample clock? Anyway,= I still cannot imagine "to reduce the power consumption at same speed." >=20 >=20 >=20 > I do not find relevant example on that book or on-line. Could you explain= it to me? >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 > Thanks, Hi, higher clock rates cause higher power consumption in a CMOS device. That's a trivial fact. If it increases "very fast" depends on your interpretation of that phrase. Pipelined designs can be used in two ways. 1) To increase the sampling or data rate.=20 Here you spend additional hardware for each computational step, where each = step uses one clock cycle.=20 Therefore the data rate is equal to the clock rate, which can become very h= igh. High data rate plus increased design size cause high power consumption. 2) However, if you decide to keep the data rate constant (low) the power lo= sses due to CMOS transistor switching will stay low too. (Still there's som= e loss du to the higher number of registers.) The other option would be to save design space for the cost of a higher sys= tem clock rate depending on the number of required computational steps. sys_clk =3D datarate*N_steps Wether the second option works for you in order to save power depends on th= e technology you are using. You have some function of power/f per switching element.=20 Now it depends on that function and your design wether spending additional = HW at low frequencies saves energy compared to a small design running at a = higher frequency. There might be some trade-off point for each technology and application, th= at needs to be calculated to make a reasonable decision. Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.66.182.137 with SMTP id ee9mr14632448pac.0.1392800988324; Wed, 19 Feb 2014 01:09:48 -0800 (PST) X-Received: by 10.50.122.10 with SMTP id lo10mr9007igb.11.1392800988021; Wed, 19 Feb 2014 01:09:48 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c10no30915583igq.0!news-out.google.com!rw17ni6igc.0!nntp.google.com!c10no30915573igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Feb 2014 01:09:47 -0800 (PST) In-Reply-To: <52bc24a0-2815-426b-9d5b-347c44eaa863@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=InKtjwoAAADGcfo0qx53UFf1Ya_UtGvZ NNTP-Posting-Host: 115.187.63.199 References: <343518c6-387c-422b-a99d-f2209443c637@googlegroups.com> <5303307b$0$9231$e4fe514c@dreader35.news.xs4all.nl> <52bc24a0-2815-426b-9d5b-347c44eaa863@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: help regarding an open source From: koyel.aphy@gmail.com Injection-Date: Wed, 19 Feb 2014 09:09:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7302 Hi, I am unable to understand in top.vhd why the condition rxstrobe =3D1 is kep= t while using the condition hit =3D1 as it may happen that rxstrobe =3D0 an= d hit =3D1 and then the statements under hit =3D1 will not be executed. It = is needed to detect hits and if a hit occurs (hit =3D 1) and rxstrobe is 0 = then the hit will not be detected but it needs to be in bitcoins. Please he= lp if possible. Regards From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.182.22.133 with SMTP id d5mr15220589obf.27.1392808499359; Wed, 19 Feb 2014 03:14:59 -0800 (PST) X-Received: by 10.50.46.37 with SMTP id s5mr17437igm.0.1392808499186; Wed, 19 Feb 2014 03:14:59 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no29522872igb.0!news-out.google.com!rw17ni6igc.0!nntp.google.com!c10no31050824igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Feb 2014 03:14:58 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=115.187.63.199; posting-account=InKtjwoAAADGcfo0qx53UFf1Ya_UtGvZ NNTP-Posting-Host: 115.187.63.199 References: <343518c6-387c-422b-a99d-f2209443c637@googlegroups.com> <5303307b$0$9231$e4fe514c@dreader35.news.xs4all.nl> <52bc24a0-2815-426b-9d5b-347c44eaa863@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0fee221c-0e19-419b-b6c0-cb370a2cd4a3@googlegroups.com> Subject: Re: help regarding an open source From: koyel.aphy@gmail.com Injection-Date: Wed, 19 Feb 2014 11:14:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7303 one further question is: 'nonce' is being fed to the input in miner.vhd and= 'hit' is an output, which is obtained as hit <=3D '1' when outerhash(255 downto 224) =3D x"00000000" and step =3D "0= 00000" else '0';(taken from miner.vhd) 'outerhash' depends on the value of 'nonce' somehow but the 'nonce' for whi= ch I get the hit (hit means 'hit'=3D1) is not the one that appears (in 'non= ce' signal) when 'hit' hits (gets the value of 1) as 'nonce' keep on increm= enting every clock pulse and by the time a 'nonce' gives rise to a hit, the= value of 'nonce' has incremented and changed to some other value. So in to= p.vhd under the if condition (if hit =3D'1') txdata gets the value of that = nonce that appears when 'hit' hits but not of that nonce that causes the hi= t. But in bitcoin mining as far as I understood we need to find the nonce t= hat causes the hit ('hit' gets a value of 1). I am unable to find out where= I am wrong. Please point that out and clarify. Many thanks, regards From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.224.66.196 with SMTP id o4mr13752170qai.2.1392829288521; Wed, 19 Feb 2014 09:01:28 -0800 (PST) X-Received: by 10.50.111.11 with SMTP id ie11mr60025igb.2.1392829288224; Wed, 19 Feb 2014 09:01:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!f11no24265821qae.1!news-out.google.com!rw17ni8igc.0!nntp.google.com!c10no31454854igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Feb 2014 09:01:27 -0800 (PST) In-Reply-To: <3291EB8F.7143@bytecraft.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=75.196.131.14; posting-account=4hnSbgoAAADrgu_bMthWurKYRwoPaM82 NNTP-Posting-Host: 75.196.131.14 References: <328B8304.41C67EA6@prairiecomm.com> <56nvth$ekk@sjx-ixn7.ix.netcom.com> <3291EB8F.7143@bytecraft.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2f3fa230-07b3-476f-b458-bc50060452bd@googlegroups.com> Subject: Re: VHDL to C From: fatinellicastrati@gmail.com Injection-Date: Wed, 19 Feb 2014 17:01:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 27 Xref: news.eternal-september.org comp.lang.vhdl:7304 On Tuesday, November 19, 1996 1:00:00 AM UTC-7, Walter Banks wrote: > Does anyone know (have) a VHDL to C converter or compiler. > > Walter Banks > http://www.bytecraft.com VHDL TO C ? if VHDL is synthesis type .You could do VHDL to Verilog first and the look for a Verilog to C converter From newsfish@newsfish Tue Dec 29 16:43:18 2015 X-Received: by 10.66.102.8 with SMTP id fk8mr2217228pab.24.1392861902855; Wed, 19 Feb 2014 18:05:02 -0800 (PST) X-Received: by 10.140.24.149 with SMTP id 21mr624qgr.32.1392861902793; Wed, 19 Feb 2014 18:05:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!uq10no30535015igb.0!news-out.google.com!s3ni26781qas.0!nntp.google.com!k15no24477491qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Feb 2014 18:05:02 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <390d452a-68de-4c71-926c-5cbe380e0cf5@googlegroups.com> Subject: Questions about negate a negative number From: fl Injection-Date: Thu, 20 Feb 2014 02:05:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7305 Hi, I am new to VHDL. My project is about designing a division lookup table for= signed number entries. In order to use less resources, I want to implement= the table only for positive entries. "The sign of the division result can = be evaluated by an XOR gate." If the result sign is negative, it may need t= o negate a division operand. For example, if the signed number is 16-bit, I= can negate -32700 by bit-wise not the bits and add 1. Is this method right= ? Or do you have a better and simple method? Second, how to deal with -32768, because the maximum positive number is 327= 67. I have read VHDL data type conversion of signed and unsigned. I do not find= they are useful in my problem yet. signed, unsigned are only a number inte= rpretation? Thanks,=20 From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Questions about negate a negative number Date: Thu, 20 Feb 2014 09:50:12 -0500 Organization: Alacron, Inc. Lines: 33 Message-ID: References: <390d452a-68de-4c71-926c-5cbe380e0cf5@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Feb 2014 14:52:10 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="11839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18B26h0fixD9HeSro7P8r7N3f7P6pQ3d9E=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <390d452a-68de-4c71-926c-5cbe380e0cf5@googlegroups.com> Cancel-Lock: sha1:gYtDGVMc1drRqsKWNjz1p5aFu0w= Xref: news.eternal-september.org comp.lang.vhdl:7306 fl wrote: > Hi, > > I am new to VHDL. My project is about designing a division lookup table for signed number entries. In order to use less resources, I want to implement the table only for positive entries. "The sign of the division result can be evaluated by an XOR gate." If the result sign is negative, it may need to negate a division operand. For example, if the signed number is 16-bit, I can negate -32700 by bit-wise not the bits and add 1. Is this method right? Or do you have a better and simple method? > > Second, how to deal with -32768, because the maximum positive number is 32767. > > I have read VHDL data type conversion of signed and unsigned. I do not find they are useful in my problem yet. signed, unsigned are only a number interpretation? > > > Thanks, > > Dealing with cases like -32768 is usually a large portion of the design process. You need to decide how you want to handle it. For example, you could say it represents an "overflow error" and cause an exception in the process. You could also say 32767 is close enough to 32768 for your purposes and then you just need to "saturate" to the maximum number that can be expressed in the given number of bits. One way to deal with situations like this is to use an intermediate format that can hold any possible answer, and then check the result to see if it will fit in the output size. In the case of negating a 16-bit number, you could use 17 bits when doing the negation, and then clip to 32767 if the result is greater than 32767. On the other hand, when doing a table you might just decide not to have table entries that could cause an overflow, for example using -32767 in the table value instead of -32768. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.68.130.166 with SMTP id of6mr1557465pbb.1.1392924511558; Thu, 20 Feb 2014 11:28:31 -0800 (PST) X-Received: by 10.140.84.233 with SMTP id l96mr69578qgd.14.1392924511107; Thu, 20 Feb 2014 11:28:31 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!ecngs!feeder2.ecngs.de!212.27.60.7.MISMATCH!feeder1-1.proxad.net!proxad.net!feeder1-2.proxad.net!209.85.213.216.MISMATCH!uy17no825533igb.0!news-out.google.com!rw17ni17igc.0!nntp.google.com!uy17no825480igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 11:28:31 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Subject: Can wild letters be used in case statements? From: fl Injection-Date: Thu, 20 Feb 2014 19:28:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7307 Hi, I am implementing 7 lookup tables, which compose a large table. In this way, the resource used only depends on the table values. I only list one lut component: lut6 to save space below. You can see that s_addr6(5:0) is ignored. This is a 64 to 1 saving for the table (These 64 addresses have one same lut output). I use Modelsim 6.5 SE. The problem is that it seems that the case always select "when others " line. Even though tmp value is "000011100000001" (15 bits), it does not use o_tmp_2 output. This case statement originates from "The designer's guide to VHDL" book. In the example snippet on the book, it uses "case?". But Xilinx ISE does not understand "case?". Could you help me on this problem? Thanks, signal tmp : unsigned(14 DOWNTO 0); signal o_tmp0 : std_logic_vector(25 DOWNTO 0); signal o_tmp1 : std_logic_vector(25 DOWNTO 0); signal o_tmp2 : std_logic_vector(25 DOWNTO 0); signal o_tmp3 : std_logic_vector(25 DOWNTO 0); signal o_tmp4 : std_logic_vector(25 DOWNTO 0); signal o_tmp5 : std_logic_vector(25 DOWNTO 0); signal o_tmp6 : std_logic_vector(25 DOWNTO 0); signal o_tmp_0 : unsigned(25 DOWNTO 0); signal o_tmp_1 : unsigned(25 DOWNTO 0); signal o_tmp_2 : unsigned(25 DOWNTO 0); signal o_tmp_3 : unsigned(25 DOWNTO 0); signal o_tmp_4 : unsigned(25 DOWNTO 0); signal o_tmp_5 : unsigned(25 DOWNTO 0); signal o_tmp_6 : unsigned(25 DOWNTO 0); signal s_addr0 : unsigned(8 DOWNTO 0); signal s_addr1 : unsigned(7 DOWNTO 0); signal s_addr2 : unsigned(7 DOWNTO 0); signal s_addr3 : unsigned(7 DOWNTO 0); signal s_addr4 : unsigned(7 DOWNTO 0); signal s_addr5 : unsigned(7 DOWNTO 0); signal s_addr6 : unsigned(7 DOWNTO 0); signal lut_reciprocal_internal : unsigned(25 DOWNTO 0); lut6 : kalman_fadd_lut6 port map ( clk => clk, reset => reset, enb_1_1_1 => '1', divider_u => std_logic_vector(s_addr6), lut_reciprocal => o_tmp6); tmp <= unsigned(divider_in(14 downto 0)); o_tmp_0 <= unsigned(o_tmp0); o_tmp_1 <= unsigned(o_tmp1); o_tmp_2 <= unsigned(o_tmp2); o_tmp_3 <= unsigned(o_tmp3); o_tmp_4 <= unsigned(o_tmp4); o_tmp_5 <= unsigned(o_tmp5); o_tmp_6 <= unsigned(o_tmp6); s_addr0 <= tmp( 8 downto 0); s_addr1 <= tmp( 8 downto 1); s_addr2 <= tmp( 9 downto 2); s_addr3 <= tmp(10 downto 3); s_addr4 <= tmp(11 downto 4); s_addr5 <= tmp(12 downto 5); s_addr6 <= tmp(13 downto 6); PROCESS(tmp) BEGIN CASE tmp IS -- lut: 15 address bus when "1--------------" => lut_reciprocal_internal <= o_tmp_6; when "01-------------" => lut_reciprocal_internal <= o_tmp_5; when "001------------" => lut_reciprocal_internal <= o_tmp_4; when "0001-----------" => lut_reciprocal_internal <= o_tmp_3; when "00001----------" => lut_reciprocal_internal <= o_tmp_2; when "000001---------" => lut_reciprocal_internal <= o_tmp_1; WHEN OTHERS => lut_reciprocal_internal <= o_tmp_0; END CASE; END PROCESS; From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.112.171.5 with SMTP id aq5mr2045541lbc.21.1392929716728; Thu, 20 Feb 2014 12:55:16 -0800 (PST) X-Received: by 10.140.20.167 with SMTP id 36mr69785qgj.13.1392929715864; Thu, 20 Feb 2014 12:55:15 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!nntp.giganews.com!news.osn.de!diablo2.news.osn.de!195.208.113.67.MISMATCH!goblin1!goblin.stu.neva.ru!w7no8705724lbi.1!news-out.google.com!le8ni18022lbc.0!nntp.google.com!s7no8609701lbd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 12:55:15 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> Subject: Why does this if process wrong? From: fl Injection-Date: Thu, 20 Feb 2014 20:55:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 36 Xref: news.eternal-september.org comp.lang.vhdl:7308 Hi, I write the following conditional decoder, but the synthesis gives error: Line 240. parse error, unexpected EQ from the first elsif line and thereafter elsif lines. What is wrong? Thanks, signal tmp : unsigned(14 DOWNTO 0); PROCESS(tmp) BEGIN if tmp(14) then lut_reciprocal_internal <= o_tmp_6; elsif (tmp(14 downto 13)=="01") then lut_reciprocal_internal <= o_tmp_5; elsif (tmp(14 downto 12)=="001") then lut_reciprocal_internal <= o_tmp_4; elsif (tmp(14 downto 11)=="0001") then lut_reciprocal_internal <= o_tmp_3; elsif (tmp(14 downto 10)=="00001") then lut_reciprocal_internal <= o_tmp_2; elsif (tmp(14 downto 9)=="000001") then lut_reciprocal_internal <= o_tmp_1; elsif (tmp(14 downto 9)=="000000") then lut_reciprocal_internal <= o_tmp_0; end if; END PROCESS; From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does this if process wrong? Date: Thu, 20 Feb 2014 16:25:54 -0500 Organization: Alacron, Inc. Lines: 51 Message-ID: References: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Feb 2014 21:27:55 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32504"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+9M/8PGnBO5Tr92GvvJ4Iijxm3ZXp9WNc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> Cancel-Lock: sha1:qawf0bCbkf9JZCcUSc0TFgH5v7w= Xref: news.eternal-september.org comp.lang.vhdl:7309 fl wrote: > Hi, > > I write the following conditional decoder, but the synthesis gives error: > > Line 240. parse error, unexpected EQ > > from the first elsif line and thereafter elsif lines. > > What is wrong? > > > Thanks, > > > > > > signal tmp : unsigned(14 DOWNTO 0); > > PROCESS(tmp) > BEGIN > if tmp(14) then > lut_reciprocal_internal <= o_tmp_6; > elsif (tmp(14 downto 13)=="01") then > lut_reciprocal_internal <= o_tmp_5; > elsif (tmp(14 downto 12)=="001") then > lut_reciprocal_internal <= o_tmp_4; > elsif (tmp(14 downto 11)=="0001") then > lut_reciprocal_internal <= o_tmp_3; > elsif (tmp(14 downto 10)=="00001") then > lut_reciprocal_internal <= o_tmp_2; > elsif (tmp(14 downto 9)=="000001") then > lut_reciprocal_internal <= o_tmp_1; > elsif (tmp(14 downto 9)=="000000") then > lut_reciprocal_internal <= o_tmp_0; > end if; > END PROCESS; if tmp(14) then This sort of condition only works on booleans. Bit selects from an unsigned wouldn't work unless you wrote something like: if tmp(14) = '1' then By the way, when you paste a snip of code it would be nice to indicate where line 240 is. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.112.123.225 with SMTP id md1mr68053lbb.13.1392932563964; Thu, 20 Feb 2014 13:42:43 -0800 (PST) X-Received: by 10.140.47.170 with SMTP id m39mr77806qga.19.1392932563598; Thu, 20 Feb 2014 13:42:43 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!goblin3!goblin1!goblin.stu.neva.ru!w7no8929686lbi.1!news-out.google.com!le8ni18022lbc.0!nntp.google.com!s7no8834505lbd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 13:42:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e67030f-792c-4eb2-ab37-57338a361706@googlegroups.com> Subject: Re: Why does this if process wrong? From: fl Injection-Date: Thu, 20 Feb 2014 21:42:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7310 Thanks. The more difficult problem for me is the rest, such as: elsif (tmp(14 downto 13)=="01") then It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result. I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again. if tmp(14 downto 13) == 01 then c_tmp_5 <= '1'; else c_tmp_5 <= '0'; end if; From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.152.201.198 with SMTP id kc6mr2242062lac.2.1392934269018; Thu, 20 Feb 2014 14:11:09 -0800 (PST) X-Received: by 10.140.91.72 with SMTP id y66mr74793qgd.23.1392934268605; Thu, 20 Feb 2014 14:11:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!goblin3!goblin1!goblin.stu.neva.ru!w7no9063722lbi.1!news-out.google.com!ow6ni19456lbb.1!nntp.google.com!w7no9063697lbi.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 14:11:08 -0800 (PST) In-Reply-To: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.39.15.136; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 217.39.15.136 References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7378ec61-8c64-48aa-9121-2fd1cffc2b51@googlegroups.com> Subject: Re: Can wild letters be used in case statements? From: Jim Lewis Injection-Date: Thu, 20 Feb 2014 22:11:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7311 Unfortunately Xilinx has been focusing on Vivado. =20 VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it = as a bug to Xilinx. Also be sure to refer to the Mentor study which shows = that 70% of FPGA RTL designers use VHDL, so how come they are lagging so fa= r behind in implementing the VHDL-2008 standard. From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.112.171.5 with SMTP id aq5mr2231108lbc.21.1392934424559; Thu, 20 Feb 2014 14:13:44 -0800 (PST) X-Received: by 10.140.95.144 with SMTP id i16mr78218qge.1.1392934424177; Thu, 20 Feb 2014 14:13:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!goblin3!goblin1!goblin.stu.neva.ru!w7no9075205lbi.1!news-out.google.com!ow6ni19456lbb.1!nntp.google.com!w7no9075192lbi.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 14:13:43 -0800 (PST) In-Reply-To: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.39.15.136; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 217.39.15.136 References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can wild letters be used in case statements? From: Jim Lewis Injection-Date: Thu, 20 Feb 2014 22:13:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7312 Unfortunately Xilinx has been focusing on Vivado. =20 VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it = as a bug to Xilinx. Also be sure to refer to the Mentor study which shows = that 70% of FPGA RTL designers use VHDL, so how come they are lagging so fa= r behind in implementing the VHDL-2008 standard.=20 Altera documentation indicates that they do support the matching case state= ment (Case?). From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.112.247.68 with SMTP id yc4mr2661603lbc.16.1392947142904; Thu, 20 Feb 2014 17:45:42 -0800 (PST) X-Received: by 10.140.107.138 with SMTP id h10mr95113qgf.2.1392947142493; Thu, 20 Feb 2014 17:45:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!s7no9889929lbd.0!news-out.google.com!le8ni18022lbc.0!nntp.google.com!s7no9889887lbd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Feb 2014 17:45:42 -0800 (PST) In-Reply-To: <5e67030f-792c-4eb2-ab37-57338a361706@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> <5e67030f-792c-4eb2-ab37-57338a361706@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3c7924c9-2530-408b-912a-3f85a10376c6@googlegroups.com> Subject: Re: Why does this if process wrong? From: fl Injection-Date: Fri, 21 Feb 2014 01:45:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7313 On Thursday, February 20, 2014 4:42:43 PM UTC-5, fl wrote: > Thanks. The more difficult problem for me is the rest, such as: > > > > > > elsif (tmp(14 downto 13)=="01") then > > > > > > It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result. > > > > I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again. > > > > > > if tmp(14 downto 13) == 01 then > > c_tmp_5 <= '1'; > > else > > c_tmp_5 <= '0'; > > end if; Thanks. I realize that VHDL needs one '=' sign for equal. From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.112.170.5 with SMTP id ai5mr945705lbc.1.1392983907003; Fri, 21 Feb 2014 03:58:27 -0800 (PST) X-Received: by 10.140.37.18 with SMTP id q18mr2927qgq.20.1392983906685; Fri, 21 Feb 2014 03:58:26 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!goblin1!goblin.stu.neva.ru!s7no12192948lbd.0!news-out.google.com!le8ni18022lbc.0!nntp.google.com!s7no12192908lbd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Feb 2014 03:58:26 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can wild letters be used in case statements? From: fl Injection-Date: Fri, 21 Feb 2014 11:58:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7314 On Thursday, February 20, 2014 5:13:43 PM UTC-5, Jim Lewis wrote: > Unfortunately Xilinx has been focusing on Vivado. =20 >=20 >=20 >=20 > VHDL-2008 is the only easy avenue to your circuit. Make sure to submit i= t as a bug to Xilinx. Also be sure to refer to the Mentor study which show= s that 70% of FPGA RTL designers use VHDL, so how come they are lagging so = far behind in implementing the VHDL-2008 standard.=20 >=20 >=20 >=20 > Altera documentation indicates that they do support the matching case sta= tement (Case?). Thanks. The if then can get the function but with a large cascaded delay. A= s Xilinx does not support it, can I construct such functionality by myself? I have no idea on how to do that now. Please shed some light on it if you k= now. From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does this if process wrong? Date: Fri, 21 Feb 2014 08:45:16 -0500 Organization: Alacron, Inc. Lines: 40 Message-ID: References: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> <5e67030f-792c-4eb2-ab37-57338a361706@googlegroups.com> <3c7924c9-2530-408b-912a-3f85a10376c6@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 21 Feb 2014 13:45:27 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="24898"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JqJ27PjHQ++2lot2re6o3W1XZZYVN/tw=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3c7924c9-2530-408b-912a-3f85a10376c6@googlegroups.com> Cancel-Lock: sha1:KuXPnxDmjqyT8IGGRafupKzMnPY= Xref: news.eternal-september.org comp.lang.vhdl:7315 fl wrote: > On Thursday, February 20, 2014 4:42:43 PM UTC-5, fl wrote: >> Thanks. The more difficult problem for me is the rest, such as: >> >> >> >> >> >> elsif (tmp(14 downto 13)=="01") then >> >> >> >> >> >> It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result. >> >> >> >> I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again. >> >> >> >> >> >> if tmp(14 downto 13) == 01 then >> >> c_tmp_5 <= '1'; >> >> else >> >> c_tmp_5 <= '0'; >> >> end if; > > Thanks. I realize that VHDL needs one '=' sign for equal. I originally missed that, too. I do most of my coding in Verilog. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Sat, 22 Feb 2014 14:13:44 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Can wild letters be used in case statements? References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> In-Reply-To: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 25 Message-ID: <5308a288$0$2137$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 22 Feb 2014 14:13:44 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1393074824 news-3.free.fr 2137 88.185.146.198:1133 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7316 Le 20/02/2014 20:28, fl a écrit : > Hi, > > I am implementing 7 lookup tables, which compose a large table. In this way, the resource used only depends on the table values. I only list one lut component: lut6 to save space below. > PROCESS(tmp) > BEGIN > CASE tmp IS > -- lut: 15 address bus > when "1--------------" => lut_reciprocal_internal <= o_tmp_6; > when "01-------------" => lut_reciprocal_internal <= o_tmp_5; > when "001------------" => lut_reciprocal_internal <= o_tmp_4; > when "0001-----------" => lut_reciprocal_internal <= o_tmp_3; > when "00001----------" => lut_reciprocal_internal <= o_tmp_2; > when "000001---------" => lut_reciprocal_internal <= o_tmp_1; > WHEN OTHERS => lut_reciprocal_internal <= o_tmp_0; > END CASE; > END PROCESS; > Hi Seems to me you'd be better off with cascaded if...then...elsif... statements in this particular case. Nicolas From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Sat, 22 Feb 2014 14:18:14 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why does this if process wrong? References: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> In-Reply-To: <8b1a55f2-d265-4910-bab9-13afb819501b@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 37 Message-ID: <5308a396$0$2188$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 22 Feb 2014 14:18:14 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1393075094 news-3.free.fr 2188 88.185.146.198:1189 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7317 Le 20/02/2014 21:55, fl a écrit : > > signal tmp : unsigned(14 DOWNTO 0); > > PROCESS(tmp) > BEGIN > if tmp(14) then > lut_reciprocal_internal <= o_tmp_6; > elsif (tmp(14 downto 13)=="01") then > lut_reciprocal_internal <= o_tmp_5; > elsif (tmp(14 downto 12)=="001") then > lut_reciprocal_internal <= o_tmp_4; > elsif (tmp(14 downto 11)=="0001") then > lut_reciprocal_internal <= o_tmp_3; > elsif (tmp(14 downto 10)=="00001") then > lut_reciprocal_internal <= o_tmp_2; > elsif (tmp(14 downto 9)=="000001") then > lut_reciprocal_internal <= o_tmp_1; > elsif (tmp(14 downto 9)=="000000") then > lut_reciprocal_internal <= o_tmp_0; > end if; > END PROCESS; > Apart from the double = that you've already spotted, I think you don't need to test all the upper 0s. Assuming this is for synthesis, the only values you'll get are 0s and 1s so you can test only one bit at a time : if tmp(14) = '1' then elsif tmp(13) = '1' then -- because tmp(14) is 0 if you reach this case. elsif tmp(12) = '1' then ... else ... end if; Nicolas From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Can wild letters be used in case statements? Date: Sat, 22 Feb 2014 20:07:56 -0500 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 23 Feb 2014 01:08:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7ab9644a7797d322f9e8bdefd4bbdffe"; logging-data="16249"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18WEvHg6far6KEeJw+JsAOe" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 In-Reply-To: Cancel-Lock: sha1:I8IOHGizuur4c3cGS49CHYNuv9A= Xref: news.eternal-september.org comp.lang.vhdl:7318 On 2/21/2014 6:58 AM, fl wrote: > On Thursday, February 20, 2014 5:13:43 PM UTC-5, Jim Lewis wrote: >> Unfortunately Xilinx has been focusing on Vivado. >> >> >> >> VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it as a bug to Xilinx. Also be sure to refer to the Mentor study which shows that 70% of FPGA RTL designers use VHDL, so how come they are lagging so far behind in implementing the VHDL-2008 standard. >> >> >> >> Altera documentation indicates that they do support the matching case statement (Case?). > > Thanks. The if then can get the function but with a large cascaded delay. As Xilinx does not support it, can I construct such functionality by myself? > I have no idea on how to do that now. Please shed some light on it if you know. > Not clear what you mean by a "large cascaded delay." Any reasonable synthesis engine will create the same logic whether you use a case statement or the equivalent if ... elsif ... else statements. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.182.158.4 with SMTP id wq4mr9874824obb.18.1393254162936; Mon, 24 Feb 2014 07:02:42 -0800 (PST) X-Received: by 10.50.70.3 with SMTP id i3mr154615igu.3.1393254162736; Mon, 24 Feb 2014 07:02:42 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uy17no8530328igb.0!news-out.google.com!o4ni0igd.0!nntp.google.com!uy17no8530315igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Feb 2014 07:02:42 -0800 (PST) In-Reply-To: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.137.96.24; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.137.96.24 References: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: Daniel Kho Injection-Date: Mon, 24 Feb 2014 15:02:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7319 > > Significantly, Altera Quartus does not allow entity instantiation, which > > means if you want Altera compatibility you will need to write a component > > declaration for each Verilog module. > I suggest for those who like to see this feature supported by Quartus, file a mySupport case with Altera (if you have enough privileges), or submit a post in Altera Forums. Based on my experience with Altera, they have the habit of prioritising work based on number of requests filed on a particular topic. If there are many requests regarding a single issue, that issue will receive more attention. -daniel From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.182.158.4 with SMTP id wq4mr11202883obb.18.1393288329525; Mon, 24 Feb 2014 16:32:09 -0800 (PST) X-Received: by 10.140.20.167 with SMTP id 36mr76715qgj.13.1393288329497; Mon, 24 Feb 2014 16:32:09 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1284278igb.0!news-out.google.com!s3ni31889qas.0!nntp.google.com!k15no31144100qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Feb 2014 16:32:09 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.141.14; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.141.14 References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can wild letters be used in case statements? From: fl Injection-Date: Tue, 25 Feb 2014 00:32:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7320 On Saturday, February 22, 2014 8:07:56 PM UTC-5, Gabor Sz wrote: > On 2/21/2014 6:58 AM, fl wrote: >=20 > > On Thursday, February 20, 2014 5:13:43 PM UTC-5, Jim Lewis wrote: >=20 > >> Unfortunately Xilinx has been focusing on Vivado. >=20 > >> >=20 > >> >=20 > >> >=20 > >> VHDL-2008 is the only easy avenue to your circuit. Make sure to submi= t it as a bug to Xilinx. Also be sure to refer to the Mentor study which s= hows that 70% of FPGA RTL designers use VHDL, so how come they are lagging = so far behind in implementing the VHDL-2008 standard. >=20 > >> >=20 > >> >=20 > >> >=20 > >> Altera documentation indicates that they do support the matching case = statement (Case?). >=20 > > >=20 > > Thanks. The if then can get the function but with a large cascaded dela= y. As Xilinx does not support it, can I construct such functionality by mys= elf? >=20 > > I have no idea on how to do that now. Please shed some light on it if y= ou know. >=20 > > >=20 >=20 >=20 > Not clear what you mean by a "large cascaded delay." Any reasonable >=20 > synthesis engine will create the same logic whether you use a case >=20 > statement or the equivalent if ... elsif ... else statements. >=20 >=20 >=20 > --=20 >=20 > Gabor Excuse me, I am new to VHDL yet. On some VHDL books, it shows me that "if t= hen else" structure will generate cascaded muxes (i.e. there is priorities = in "if...then...else" structures. Because of the cascaded muxes, the delay = will be larger), while "when... case..." generates no priority structures (= All cases are exclusive with each other and combined to the whole set. This= structure uses more resources but less delay). I will check the book and c= heck the implementation results later. Thanks for your comments. From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: Can wild letters be used in case statements? Date: Tue, 25 Feb 2014 11:39:50 +0100 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 25 Feb 2014 10:39:49 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="6375311d8a19312d2554532d912d2594"; logging-data="23311"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hqaDwkj8j83d4CP1cVQuH" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 In-Reply-To: Cancel-Lock: sha1:tzo9yOLFSlsdBHs8jYaSWsOm1pw= Xref: news.eternal-september.org comp.lang.vhdl:7321 Am 25.02.2014 01:32, schrieb fl: > > Excuse me, I am new to VHDL yet. On some VHDL books, it shows me that "if then else" structure will generate cascaded muxes (i.e. there is priorities in "if...then...else" structures. Because of the cascaded muxes, the delay will be larger), while "when... case..." generates no priority structures (All cases are exclusive with each other and combined to the whole set. This structure uses more resources but less delay). I will check the book and check the implementation results later. Thanks for your comments. > Generally that's right. But if you use in every if statement the same signal/variable, then the if ... elsif ... else is equivalent to a case structure. For example: if (tmp = "0001") then ... elsif (tmp = "0010") then ... else ... end if; should produce the same synthesis output then case tmp is when "0001" => ... when "0010" => ... when others => ... end case; You can produce a small example project and implement both structures. My synthesis tool (Xilinx XST Version 14.x) works like expected. I use this approach really often to avoid "locally static" warnings in case statements. Tobias From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.236.90.200 with SMTP id e48mr507615yhf.28.1393352063839; Tue, 25 Feb 2014 10:14:23 -0800 (PST) X-Received: by 10.50.50.242 with SMTP id f18mr87301igo.17.1393352063556; Tue, 25 Feb 2014 10:14:23 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no1106248qaj.1!news-out.google.com!o4ni1igd.0!nntp.google.com!uq10no2977787igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Feb 2014 10:14:23 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.167.190.71; posting-account=Q5DnYQoAAAAPkh04McnDfQaG9Mgj2u1Q NNTP-Posting-Host: 70.167.190.71 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Subject: problem with unsigned vs std_logic_vector From: jlodman@gmail.com Injection-Date: Tue, 25 Feb 2014 18:14:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7322 I'm having a problem with a VHDL signal I hadn't expected. Simulator is Modelsim. When I declare a signal signal A : unsigned(31 downto 0); or signal A : std_logic_vector(31 downto 0); I get unexpected results from the unsigned case specifically when I try to set the 31st bit. I don't expect there would be a difference but I could be wrong. I am using numeric_std Thanks for any insight. From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.42.230.79 with SMTP id jl15mr452998icb.7.1393407820698; Wed, 26 Feb 2014 01:43:40 -0800 (PST) X-Received: by 10.140.47.43 with SMTP id l40mr34848qga.11.1393407820666; Wed, 26 Feb 2014 01:43:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no4044170igb.0!news-out.google.com!s3ni36464qas.0!nntp.google.com!k15no32773096qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Feb 2014 01:43:40 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL verification using Python via VHPI From: Chris Higgs Injection-Date: Wed, 26 Feb 2014 09:43:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7323 Greetings! I thought you might be interested to know that Cocotb now includes native s= upport for VHDL simulation using VHPI to interact with the simulator. For those not familiar with Cocotb, it's an open-source project that uses P= ython to provide a powerful framework for functional verification of RTL de= signs. The RTL to be tested hangs in free space in the simulator and all st= imulus and checking is performed from within Python. For more information have a look at the documentation[1] or examples on EDA= Playground[2]. For anybody in the UK, I'll be presenting at the NMI FPGA Verification even= t tomorrow[3] to share my experience of using Cocotb on commercial projects= . Thanks, Chris [1] https://cocotb.readthedocs.org [2] http://www.edaplayground.com/s/example/106 [3] http://www.nmi.org.uk/events/event-details//FPGA1Q14 From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: problem with unsigned vs std_logic_vector Date: Wed, 26 Feb 2014 12:29:36 +0100 Lines: 22 Message-ID: References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net hYbCTQZGP14GD/6lpJ28MwKz6Sy0PoaGV/qzE1FrigAJqf4z0Z Cancel-Lock: sha1:wl7j5OOdBMogr8rfCXmZeft1Fgo= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:7324 Am 25.02.2014 19:14, schrieb jlodman@gmail.com: > I'm having a problem with a VHDL signal I hadn't expected. Simulator > is Modelsim. > > When I declare a signal > > signal A : unsigned(31 downto 0); > > or > > signal A : std_logic_vector(31 downto 0); > > I get unexpected results from the unsigned case specifically when I > try to set the 31st bit. I don't expect there would be a difference > but I could be wrong. You need to be more specific. What "unexpected results"? What exactly are you trying to do, what are you expecting to happen, and what does actually happen? Greetings, Sean From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.43.103.136 with SMTP id di8mr1367483icc.14.1393475422321; Wed, 26 Feb 2014 20:30:22 -0800 (PST) X-Received: by 10.50.23.107 with SMTP id l11mr646016igf.17.1393475422181; Wed, 26 Feb 2014 20:30:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.Update.UU.SE!news.Update.UU.SE!news.stack.nl!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no694520igb.0!news-out.google.com!h8ni3igy.0!nntp.google.com!uq10no694512igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Feb 2014 20:30:21 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.137.96.24; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 175.137.96.24 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c717ef0-804f-4338-84d8-091c4711db46@googlegroups.com> Subject: Re: problem with unsigned vs std_logic_vector From: Daniel Kho Injection-Date: Thu, 27 Feb 2014 04:30:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7325 > You need to be more specific. What "unexpected results"? What exactly > > are you trying to do, what are you expecting to happen, and what does > > actually happen? > > > > Greetings, > > Sean Yes, also how did you assign your signal A? Did you try forcing A(31) to some hard-coded value and see what happens? regards, daniel From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx14.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: problem with unsigned vs std_logic_vector Newsgroups: comp.lang.vhdl References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> <7c717ef0-804f-4338-84d8-091c4711db46@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 25 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1393500117 62.49.20.82 (Thu, 27 Feb 2014 11:21:57 UTC) NNTP-Posting-Date: Thu, 27 Feb 2014 11:21:57 UTC Date: Thu, 27 Feb 2014 11:21:57 GMT X-Received-Body-CRC: 3154269422 X-Received-Bytes: 1483 Xref: news.eternal-september.org comp.lang.vhdl:7326 On Wed, 26 Feb 2014 20:30:21 -0800, Daniel Kho wrote: >> You need to be more specific. What "unexpected results"? What exactly >> >> are you trying to do, what are you expecting to happen, and what does >> >> actually happen? >> >> >> >> Greetings, >> >> Sean > > > Yes, also how did you assign your signal A? Did you try forcing A(31) to > some hard-coded value and see what happens? Actually, the 31st bit would be either A(30) or A(1) depending on how the OP counted; as a little-endian guy I would consider A(31) to be the 32nd bit... I agree the question as posted is hopelessly unclear. - Brian From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx35.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with unsigned vs std_logic_vector References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> In-Reply-To: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140227-0, 27/02/2014), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1393501586 86.29.12.221 (Thu, 27 Feb 2014 11:46:26 UTC) NNTP-Posting-Date: Thu, 27 Feb 2014 11:46:26 UTC Organization: virginmedia.com Date: Thu, 27 Feb 2014 11:46:24 +0000 X-Received-Body-CRC: 2839710796 X-Received-Bytes: 1643 Xref: news.eternal-september.org comp.lang.vhdl:7327 On 25/02/2014 18:14, jlodman@gmail.com wrote: > I'm having a problem with a VHDL signal I hadn't expected. Simulator is Modelsim. > > When I declare a signal > > signal A : unsigned(31 downto 0); > > or > > signal A : std_logic_vector(31 downto 0); > > I get unexpected results from the unsigned case specifically when I try to set the 31st bit. I don't expect there would be a difference but I could be wrong. > > I am using numeric_std > > Thanks for any insight. > I suspect the longest static prefix manage to trip another user ;-) Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx07.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Can wild letters be used in case statements? References: <8bdd8f1c-d311-4ad1-9142-44f1145185b9@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140227-0, 27/02/2014), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1393502219 86.29.12.221 (Thu, 27 Feb 2014 11:56:59 UTC) NNTP-Posting-Date: Thu, 27 Feb 2014 11:56:59 UTC Organization: virginmedia.com Date: Thu, 27 Feb 2014 11:56:58 +0000 X-Received-Body-CRC: 1184314994 X-Received-Bytes: 2280 Xref: news.eternal-september.org comp.lang.vhdl:7328 On 21/02/2014 11:58, fl wrote: > On Thursday, February 20, 2014 5:13:43 PM UTC-5, Jim Lewis wrote: >> Unfortunately Xilinx has been focusing on Vivado. >> >> >> >> VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it as a bug to Xilinx. Also be sure to refer to the Mentor study which shows that 70% of FPGA RTL designers use VHDL, so how come they are lagging so far behind in implementing the VHDL-2008 standard. >> >> >> >> Altera documentation indicates that they do support the matching case statement (Case?). > > Thanks. The if then can get the function but with a large cascaded delay. As Xilinx does not support it, can I construct such functionality by myself? > I have no idea on how to do that now. Please shed some light on it if you know. > If I understand this Xilinx answer record correctly, VHDL2008 synthesis will not be supported until 2014.3 which probably means end of this year. http://www.xilinx.com/support/answers/51502.html If you have some budget I would suggest you have a word with Mentor/Synplify to get hold of a proper synthesis tool. Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.50.225.6 with SMTP id rg6mr335329igc.6.1393542064718; Thu, 27 Feb 2014 15:01:04 -0800 (PST) X-Received: by 10.50.122.10 with SMTP id lo10mr10702igb.11.1393542064571; Thu, 27 Feb 2014 15:01:04 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no2178755igb.0!news-out.google.com!h8ni4igy.0!nntp.google.com!uq10no2189987igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Feb 2014 15:01:03 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=67.164.210.201; posting-account=oyPdVAoAAACIiryKC7Thi33-gGPrNMQv NNTP-Posting-Host: 67.164.210.201 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <22905eed-b074-47d9-a6cc-bc8dacdd14a9@googlegroups.com> Subject: Fizzim - the free finite state machine design tool adds VHDL ! From: zimmerdesignservices@gmail.com Injection-Date: Thu, 27 Feb 2014 23:01:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7329 fizzim (www.fizzim.pl) is a free, open source fsm design tool. The gui runs in java and the backend code generator is in perl. It was originally written to output verilog, then systemverilog was added, and now vhdl. The vhdl version is in beta test. You can download it from www.fizzim.com. Feedback is appreciated. Paul Zimmer Zimmer Design Services From newsfish@newsfish Tue Dec 29 16:43:19 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.tele.dk!news.tele.dk!small.news.tele.dk!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!newsfeed.arcor.de!newsspool2.arcor-online.net!news.arcor.de.POSTED!not-for-mail Date: Fri, 28 Feb 2014 10:43:33 +0100 From: Gerhard Hoffmann Reply-To: ghf@hoffmann-hochfrequenz.de User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with unsigned vs std_logic_vector References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> In-Reply-To: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 39 Message-ID: <53105a49$0$9525$9b4e6d93@newsspool1.arcor-online.net> Organization: Arcor NNTP-Posting-Date: 28 Feb 2014 10:43:37 CET NNTP-Posting-Host: 78cb4c08.newsspool1.arcor-online.net X-Trace: DXC=FDIS:Lo`VHKI7\_^6>c20Jic==]BZ:afN4Fo<]lROoRAnkgeX?EC@@@3fo:?cn\?KA3>5MOK` I'm having a problem with a VHDL signal I hadn't expected. Simulator is Modelsim. > > When I declare a signal > > signal A : unsigned(31 downto 0); > > or > > signal A : std_logic_vector(31 downto 0); > > I get unexpected results from the unsigned case specifically when I try to set the 31st bit. I don't expect there would be a difference but I could be wrong. > > I am using numeric_std > > Thanks for any insight. > Probably your code breaks when you try to convert to integer. Integers are only + / - 2 Giga and you would also need sth. between +2Giga and slightly less than +4Giga for full 32 bit unsigneds. 0x8000 0000 is also forbidden. That's not your fault, that's brain damage built into the language. It's fun testing a 64 bit design if you cannot formulate the numbers for your test cases in a readable way. I was thinking about a BCD arithmetic package that provides at least the equivalent of 256 bits. 4 bits stored per char. Should give fast conversion to/from int/string/signed/unsigned/fixed etc. and implementation could be an easy table-driven version of paper & pencil. Google summer of code? Still could not be used for long loops & synthesis. I really want int64 and int128. regards, Gerhard From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.182.112.231 with SMTP id it7mr7320147obb.22.1393612925447; Fri, 28 Feb 2014 10:42:05 -0800 (PST) X-Received: by 10.50.50.139 with SMTP id c11mr89043igo.14.1393612925268; Fri, 28 Feb 2014 10:42:05 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news.glorb.com!uq10no3522653igb.0!news-out.google.com!gi6ni3igc.0!nntp.google.com!uq10no3522640igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 10:42:04 -0800 (PST) In-Reply-To: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.167.190.71; posting-account=Q5DnYQoAAAAPkh04McnDfQaG9Mgj2u1Q NNTP-Posting-Host: 70.167.190.71 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with unsigned vs std_logic_vector From: jlodman@gmail.com Injection-Date: Fri, 28 Feb 2014 18:42:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7331 On Tuesday, February 25, 2014 10:14:23 AM UTC-8, jlo...@gmail.com wrote: > I'm having a problem with a VHDL signal I hadn't expected. Simulator is M= odelsim. >=20 >=20 >=20 > When I declare a signal >=20 >=20 >=20 > signal A : unsigned(31 downto 0); >=20 >=20 >=20 > or >=20 >=20 >=20 > signal A : std_logic_vector(31 downto 0); >=20 >=20 >=20 > I get unexpected results from the unsigned case specifically when I try t= o set the 31st bit. I don't expect there would be a difference but I could = be wrong. >=20 >=20 >=20 > I am using numeric_std >=20 >=20 >=20 > Thanks for any insight. I did try and force it to a hardcoded value of '1' by "or" with x"8000_0000= ". It ended up as x"0000_0003" It's become clear that unsigned really can't handle a value large than 2^31= -1, even when declaring a large range (I tried it). With everything else id= entical, when I changed the unsigned(31 downto 0) to std_logic_vector(31 do= wnto 0) everything worked perfectly. I simply wasn't expecting this. Readin= g on-line it seems that even though the simulator/compiler accepts it, an u= nsigned bigger than an integer don't work right even when not using it to w= ork with integers.=20 As Gerhard indicates, this restriction on integers is becoming a Not Fun if= not a serious problem in the language that should have been fixed in the l= ast standard. Unsigned and signed should work regardless of the range speci= fied, even if they would kick out now when trying to convert to a 32 bit in= teger. Since I have 36 bit addresses, I now have to do more work to get them out. From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.182.180.81 with SMTP id dm17mr7566206obc.37.1393613620595; Fri, 28 Feb 2014 10:53:40 -0800 (PST) X-Received: by 10.50.50.242 with SMTP id f18mr90259igo.17.1393613620439; Fri, 28 Feb 2014 10:53:40 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no3554712igb.0!news-out.google.com!h8ni4igy.0!nntp.google.com!uq10no3554701igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 10:53:39 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.167.190.71; posting-account=Q5DnYQoAAAAPkh04McnDfQaG9Mgj2u1Q NNTP-Posting-Host: 70.167.190.71 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> Subject: getting the range from a member of a record. From: jlodman@gmail.com Injection-Date: Fri, 28 Feb 2014 18:53:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7332 Why doesn't the following code compile? type header_t is record A : std_logic_vector(31 downto 0); B : std_logic_vector(39 downto 0); C : std_logic_vector(8 downto 0); D : std_logic_vector(7 downto 0); E : std_logic_vector(9 downto 0); end record; type compare_t is record A1 : std_logic_vector(header_t.A'LEFT downto header_t.A'RIGHT)); -- (152) B1 : std_logic_vector(header_t.D'LEFT downto header_t.D'RIGHT)); C1 : std_logic_vector(header_t.E'LEFT downto header_t.E'RIGHT); end record; Modelsim gives the error for all three compare_t entries: # ** Warning: sorter_pkg.vhd(152): (vcom-1260) Type mark (header_t) cannot be prefix of selected name. The website http://www.csee.umbc.edu/portal/help/VHDL/attribute.html indicates that the 'LEFT and 'RIGHT can be used for any type. Is there another way to code this? From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.58.23.170 with SMTP id n10mr2569551vef.25.1393631609496; Fri, 28 Feb 2014 15:53:29 -0800 (PST) X-Received: by 10.50.59.179 with SMTP id a19mr110361igr.10.1393631609270; Fri, 28 Feb 2014 15:53:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w5no3212004qac.0!news-out.google.com!h8ni6igy.0!nntp.google.com!y6no292747igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 15:53:28 -0800 (PST) In-Reply-To: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.230; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.230 References: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39f11380-54bf-44e0-a51b-3023d76596e1@googlegroups.com> Subject: Re: getting the range from a member of a record. From: Dio Gratia Injection-Date: Fri, 28 Feb 2014 23:53:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2500 X-Received-Body-CRC: 2829559154 Xref: news.eternal-september.org comp.lang.vhdl:7333 On Saturday, March 1, 2014 7:53:39 AM UTC+13, jlo...@gmail.com wrote: > Why doesn't the following code compile? > > The following is a re-write using a package containing a shared variable to illustrate (generating a small analyzable example): library ieee; use ieee.std_logic_1164.all; package fum is type header_t is record A : std_logic_vector(31 downto 0); B : std_logic_vector(39 downto 0); C : std_logic_vector(8 downto 0); D : std_logic_vector(7 downto 0); E : std_logic_vector(9 downto 0); end record; signal foo: header_t; type compare_t is record A1 : std_logic_vector(foo.A'LEFT downto foo.A'RIGHT); -- (152) B1 : std_logic_vector(foo.D'LEFT downto foo.D'RIGHT); C1 : std_logic_vector(foo.E'LEFT downto foo.E'RIGHT); end record; end package; This analyzes successfully. The record type mark is not allowed as a suffix in a selected name. There is no record header_t, it's a type declaration for a record not an actual record. See the LRM section on selected names. "A selected name may be used to denote an element of a record, an object designated by an access value, or a named entity whose declaration is contained within another named entity, particularly within a library or a package." From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.58.210.3 with SMTP id mq3mr2717370vec.28.1393632659021; Fri, 28 Feb 2014 16:10:59 -0800 (PST) X-Received: by 10.50.30.66 with SMTP id q2mr110957igh.1.1393632658743; Fri, 28 Feb 2014 16:10:58 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no1801819qab.1!news-out.google.com!h8ni5igy.0!nntp.google.com!y6no309461igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 16:10:58 -0800 (PST) In-Reply-To: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.230; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.230 References: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f0364ca-e90c-48a2-a293-df829fa66b79@googlegroups.com> Subject: Re: getting the range from a member of a record. From: Dio Gratia Injection-Date: Sat, 01 Mar 2014 00:10:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7334 And I intended to write prefix, not suffix. From newsfish@newsfish Tue Dec 29 16:43:19 2015 X-Received: by 10.236.65.136 with SMTP id f8mr2320220yhd.11.1393633470358; Fri, 28 Feb 2014 16:24:30 -0800 (PST) X-Received: by 10.50.2.100 with SMTP id 4mr112061igt.8.1393633470136; Fri, 28 Feb 2014 16:24:30 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!xmission!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w5no3235266qac.0!news-out.google.com!h8ni5igy.0!nntp.google.com!y6no325415igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 16:24:29 -0800 (PST) In-Reply-To: <39f11380-54bf-44e0-a51b-3023d76596e1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.167.190.71; posting-account=Q5DnYQoAAAAPkh04McnDfQaG9Mgj2u1Q NNTP-Posting-Host: 70.167.190.71 References: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> <39f11380-54bf-44e0-a51b-3023d76596e1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7347c185-8070-489e-8d65-1009f1e0f2bf@googlegroups.com> Subject: Re: getting the range from a member of a record. From: jlodman@gmail.com Injection-Date: Sat, 01 Mar 2014 00:24:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2970 X-Received-Body-CRC: 1074068387 Xref: news.eternal-september.org comp.lang.vhdl:7335 On Friday, February 28, 2014 3:53:28 PM UTC-8, Dio Gratia wrote: > On Saturday, March 1, 2014 7:53:39 AM UTC+13, jlo...@gmail.com wrote: > > > Why doesn't the following code compile? > > > > > > > > > > The following is a re-write using a package containing a shared variable to illustrate (generating a small analyzable example): > > > > library ieee; > > use ieee.std_logic_1164.all; > > > > package fum is > > type header_t is > > record > > A : std_logic_vector(31 downto 0); > > B : std_logic_vector(39 downto 0); > > C : std_logic_vector(8 downto 0); > > D : std_logic_vector(7 downto 0); > > E : std_logic_vector(9 downto 0); > > end record; > > > > signal foo: header_t; > > > > type compare_t is > > record > > A1 : std_logic_vector(foo.A'LEFT downto foo.A'RIGHT); -- (152) > > B1 : std_logic_vector(foo.D'LEFT downto foo.D'RIGHT); > > C1 : std_logic_vector(foo.E'LEFT downto foo.E'RIGHT); > > end record; > > > > end package; > > > > This analyzes successfully. > > > > The record type mark is not allowed as a suffix in a selected name. There is no record header_t, it's a type declaration for a record not an actual record. > > > > See the LRM section on selected names. > > > > "A selected name may be used to denote an element of a record, an object designated by an access value, or a named entity whose declaration is contained within another named entity, particularly within a library or a package." So I need to create a shared variable in the package just to get at what I should be able to get at anyway? Thanks for the help! From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.94.48 with SMTP id m36mr2619046yhf.47.1393645630526; Fri, 28 Feb 2014 19:47:10 -0800 (PST) X-Received: by 10.50.66.196 with SMTP id h4mr118488igt.16.1393645630279; Fri, 28 Feb 2014 19:47:10 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no1933591qab.1!news-out.google.com!h8ni6igy.0!nntp.google.com!y6no510758igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Feb 2014 19:47:09 -0800 (PST) In-Reply-To: <7347c185-8070-489e-8d65-1009f1e0f2bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.230; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.230 References: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> <39f11380-54bf-44e0-a51b-3023d76596e1@googlegroups.com> <7347c185-8070-489e-8d65-1009f1e0f2bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <398ff2f4-bf64-48f2-8647-238aca42c42c@googlegroups.com> Subject: Re: getting the range from a member of a record. From: Dio Gratia Injection-Date: Sat, 01 Mar 2014 03:47:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7336 > > So I need to create a shared variable in the package just to get at what I should be able to get at anyway? > > > > Thanks for the help! Not at all. And I didn't say you had to declare a shared variable. It was a demonstration of using a selected name. library ieee; use ieee.std_logic_1164.all; -- See IEEE Std 1076-1993 for example, 3.2.1 Array types package foo is subtype A_index_range is natural range 31 downto 0; subtype B_index_range is natural range 39 downto 0; subtype C_index_range is natural range 8 downto 0; subtype D_index_range is natural range 7 downto 0; subtype E_index_range is natural range 9 downto 0; type header_t is record A : std_logic_vector(A_index_range); B : std_logic_vector(B_index_range); C : std_logic_vector(C_index_range); D : std_logic_vector(D_index_range); E : std_logic_vector(E_index_range); end record; type compare_t is record A1 : std_logic_vector(A_index_range); -- (152) B1 : std_logic_vector(B_index_range); C1 : std_logic_vector(C_index_range); end record; end package; library ieee; use ieee.std_logic_1164.all; use work.foo.all; entity fum is end entity; architecture fie of fum is signal fee: header_t; signal fo: compare_t; signal a: std_logic_vector (A_index_range) := X"feedface" ; signal a1: std_logic_vector (A_index_range) := X"deadbeef" ; begin fee.A <= a; fo.A1 <= a1; end architecture; Which, analyzes, elaborates and runs demonstrating a lack of constraint errors for the default values for signals a and a1. (Consider you may have just been 'holding it wrong'). From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx27.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: problem with unsigned vs std_logic_vector Newsgroups: comp.lang.vhdl References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 19 Message-ID: <01lQu.33802$WJ7.11920@fx27.fr7> NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1393679548 62.49.20.82 (Sat, 01 Mar 2014 13:12:28 UTC) NNTP-Posting-Date: Sat, 01 Mar 2014 13:12:28 UTC Date: Sat, 01 Mar 2014 13:12:28 GMT X-Received-Body-CRC: 1102598779 X-Received-Bytes: 1545 Xref: news.eternal-september.org comp.lang.vhdl:7337 On Fri, 28 Feb 2014 10:42:04 -0800, jlodman wrote: > On Tuesday, February 25, 2014 10:14:23 AM UTC-8, jlo...@gmail.com wrote: >> I'm having a problem with a VHDL signal I hadn't expected. Simulator is >> Modelsim. >> signal A : unsigned(31 downto 0); > I did try and force it to a hardcoded value of '1' by "or" with > x"8000_0000". It ended up as x"0000_0003" > It's become clear that unsigned really can't handle a value large than > 2^31-1, even when declaring a large range (I tried it). Unsigned can handle any required range. Integer (and Natural) can't. Yes this does cause difficulty in current implementations of VHDL. Fortunately you can create Unsigned literal values without using Integer. - Brian From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!feed-me.highwinds-media.com!peer04.fr7!news.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx27.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: problem with unsigned vs std_logic_vector Newsgroups: comp.lang.vhdl References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 19 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1393679578 62.49.20.82 (Sat, 01 Mar 2014 13:12:58 UTC) NNTP-Posting-Date: Sat, 01 Mar 2014 13:12:58 UTC Date: Sat, 01 Mar 2014 13:12:58 GMT X-Received-Body-CRC: 1102598779 X-Received-Bytes: 1631 Xref: news.eternal-september.org comp.lang.vhdl:7338 On Fri, 28 Feb 2014 10:42:04 -0800, jlodman wrote: > On Tuesday, February 25, 2014 10:14:23 AM UTC-8, jlo...@gmail.com wrote: >> I'm having a problem with a VHDL signal I hadn't expected. Simulator is >> Modelsim. >> signal A : unsigned(31 downto 0); > I did try and force it to a hardcoded value of '1' by "or" with > x"8000_0000". It ended up as x"0000_0003" > It's become clear that unsigned really can't handle a value large than > 2^31-1, even when declaring a large range (I tried it). Unsigned can handle any required range. Integer (and Natural) can't. Yes this does cause difficulty in current implementations of VHDL. Fortunately you can create Unsigned literal values without using Integer. - Brian From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.154.5 with SMTP id vk5mr5426363veb.32.1393738639768; Sat, 01 Mar 2014 21:37:19 -0800 (PST) X-Received: by 10.50.122.10 with SMTP id lo10mr178454igb.11.1393738639488; Sat, 01 Mar 2014 21:37:19 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no2992548qab.1!news-out.google.com!gi6ni6igc.0!nntp.google.com!h3no147566igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Mar 2014 21:37:18 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.150.196; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.150.196 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2eff0d84-9724-4dae-b434-920c695190a7@googlegroups.com> Subject: Re: problem with unsigned vs std_logic_vector From: Daniel Kho Injection-Date: Sun, 02 Mar 2014 05:37:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2180 X-Received-Body-CRC: 3452663955 Xref: news.eternal-september.org comp.lang.vhdl:7339 > > Unsigned can handle any required range. Integer (and Natural) can't. Yes, (un)signed and any array types such as std_(u)logic_vector can handle any required range. Scalar types such as integer can't as mentioned by Brian. You should try with a simple testcase: architecture test of design is signal A : unsigned(31 downto 0); begin A<=x"8000_0000"; end architecture test; Try changing the value from x"8000_0000" to x"0", resimulate, and notice if there are any changes in the simulated waveform. Also, you could try with just driving a single bit to different values and resimulate to notice the difference: A(31)<='1'; A(31)<='0'; > > Actually, the 31st bit would be either A(30) or A(1) depending on how the > OP counted; as a little-endian guy I would consider A(31) to be the 32nd > bit... Yes, I'm a little-endian guy myself, though I have the (bad) habit of referring A(0) as the zeroth bit instead of the first bit. Sorry about that. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.66.149.67 with SMTP id ty3mr5101394pab.27.1393739136499; Sat, 01 Mar 2014 21:45:36 -0800 (PST) X-Received: by 10.50.43.131 with SMTP id w3mr178840igl.9.1393739136235; Sat, 01 Mar 2014 21:45:36 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h3no153476igd.0!news-out.google.com!gi6ni6igc.0!nntp.google.com!h3no153473igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Mar 2014 21:45:35 -0800 (PST) In-Reply-To: <7sjvua$4a7$2@news.vsnl.net.in> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=113.178.55.3; posting-account=cZboUgoAAACQBId033xJXMiLKhSJGaMw NNTP-Posting-Host: 113.178.55.3 References: <7sjvua$4a7$2@news.vsnl.net.in> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <53b4f58f-dcea-4e5b-a959-6c8174b9285f@googlegroups.com> Subject: Re: Reed Solomon codec using VHDL From: annguyen10111305@gmail.com Injection-Date: Sun, 02 Mar 2014 05:45:36 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7340 On Saturday, September 25, 1999 2:00:00 PM UTC+7, Pradeep Rao wrote: > As part of my final year project, I'm working on designing a Reed-Solomon > codec using VHDL. We also intend to transport this design to a FPGA. I wo= uld > like to know about the resources required to acheive the above. > I would also be grateful if someone could give me tips and mention common > pitfalls to avoid, since I'm working in a limited timeframe. > Thank you. > pradeep b=E1=BA=A1n c=C3=B3 c=C3=B2n t=E1=BA=A5t c=E1=BA=A3 t=C3=A0i li=E1=BB=87u l= i=C3=AAn quan v=E1=BB=81 reed solomon ko .g=E1=BB=ADi qua mail m=C3=ACnh = =C4=91=C6=B0=E1=BB=A3c ko.mail: annguyen10111305@gmail.com From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.40.97 with SMTP id w1mr6231638vek.13.1393770956697; Sun, 02 Mar 2014 06:35:56 -0800 (PST) X-Received: by 10.50.93.37 with SMTP id cr5mr201259igb.8.1393770956340; Sun, 02 Mar 2014 06:35:56 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no3668733qab.1!news-out.google.com!gi6ni0igc.0!nntp.google.com!ur14no804299igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Mar 2014 06:35:55 -0800 (PST) In-Reply-To: <2eff0d84-9724-4dae-b434-920c695190a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.151.106; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.151.106 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> <2eff0d84-9724-4dae-b434-920c695190a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43b2751a-bd7d-4364-8e95-c10488bda958@googlegroups.com> Subject: Re: problem with unsigned vs std_logic_vector From: Daniel Kho Injection-Date: Sun, 02 Mar 2014 14:35:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7341 > > Try changing the value from x"8000_0000" to x"0", resimulate, and notice if there are any changes in the simulated waveform. I meant to say change x"8000_0000" to x"0000_0000" or 32x"0". -daniel From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.228.228 with SMTP id f94mr6197182yhq.43.1393797945064; Sun, 02 Mar 2014 14:05:45 -0800 (PST) X-Received: by 10.50.41.100 with SMTP id e4mr218688igl.0.1393797944958; Sun, 02 Mar 2014 14:05:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!matrix.darkstorm.co.uk!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no4144509qab.1!news-out.google.com!gi6ni0igc.0!nntp.google.com!ur14no1529168igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Mar 2014 14:05:44 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.230; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.230 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with unsigned vs std_logic_vector From: Dio Gratia Injection-Date: Sun, 02 Mar 2014 22:05:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5281 X-Received-Body-CRC: 3897936311 Xref: news.eternal-september.org comp.lang.vhdl:7342 On Saturday, March 1, 2014 7:42:04 AM UTC+13, jlo...@gmail.com wrote: >=20 > Since I have 36 bit addresses, I now have to do more work to get them out= . You're statement that an unsigned can deal with greater than 31 bits is unf= ounded for VHDL in general. There's also not an arithmetic operator define= d for std_logic_vector by default in VHDL unless you're also using synopsys= 's package std_logic_unsigned. You should consider it anathema to mix nume= ric_std (which provides unsigned) with synopsys's packages. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is end entity; architecture foo of test is function unsigned_to_string (inp: unsigned) return string is variable tmp: string (1 to inp'LENGTH) :=3D ""; variable eval: character; variable index: positive; begin for i in inp'RANGE loop if inp(i) =3D 'U' then eval :=3D 'U'; elsif inp(i) =3D 'X' then eval :=3D 'X'; elsif inp(i) =3D '0' then eval :=3D '0'; elsif inp(i) =3D '1' then eval :=3D '1'; elsif inp(i) =3D 'Z' then eval :=3D 'Z'; elsif inp(i) =3D 'W' then eval :=3D 'W'; elsif inp(i) =3D 'L' then eval :=3D 'L'; elsif inp(i) =3D 'H' then eval :=3D 'H'; else eval :=3D '-'; end if ; tmp(index) :=3D eval; index :=3D index + 1; end loop; return tmp; end function; =20 signal A: unsigned (31 downto 0); signal B: unsigned (35 downto 0); signal C: unsigned (35 downto 0); begin A <=3D x"80000000" after 1 ns; B <=3D x"800000000" after 1 ns; C <=3D A + B; MONITOR: assert C =3D x"FFFFFFFFF" report LF & "A =3D " & unsigned_to_string(A) & LF &=20 "B =3D " & unsigned_to_string(B) & LF & "C =3D " & unsigned_to_string(C) severity NOTE; end architecture; %% ghdl -a unsigned.vhdl %% ghdl -e test %% ghdl -r test ../../../src/ieee/numeric_std-body.v93:1613:7:@0ms:(assertion warning): NUM= ERIC_STD."=3D": metavalue detected, returning FALSE unsigned.vhdl:40:1:@0ms:(assertion note): A =3D UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU B =3D UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU C =3D UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ../../../src/ieee/numeric_std-body.v93:1613:7:@0ms:(assertion warning): NUM= ERIC_STD."=3D": metavalue detected, returning FALSE unsigned.vhdl:40:1:@0ms:(assertion note): A =3D UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU B =3D UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU C =3D XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX unsigned.vhdl:40:1:@1ns:(assertion note): A =3D 10000000000000000000000000000000 B =3D 100000000000000000000000000000000000 C =3D 100010000000000000000000000000000000 %% All the 'U's are expected from the default assignment to the left most valu= e of std_ulogic for each element of the unsigned arrays. The second report= is due to no delay in the assignment of C. You get all 'X's adding two ar= rays of 'U's. The third report shows the results of C <=3D A + B; unsigned is an array of std_logic which uses a nine value representation to= describe bit values ('U','X','0','1','Z','W','L','H','-'). The function "= +" (an adding operator) is defined in package numeric_std. =20 You could note I was too lazy to convert unsigned to string representations= in base 16, they are shown by std_logic element (i.e. bit by bit). There's also useful information derived from familiarity with the packages,= for example the array length of the result for the function "+" (an operat= or) is derived from the MAX of the length of it's two arguments. C is a an= array of the std_ulogic nine level (MVL9 originally from Synopsys) represe= ntation of an array of bits that has a range of 35 downto 0 (36 bits). Perhaps you could show us an example VHDL description that exhibits your pr= oblem? From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.182.19.231 with SMTP id i7mr13757097obe.25.1393847672110; Mon, 03 Mar 2014 03:54:32 -0800 (PST) X-Received: by 10.50.115.71 with SMTP id jm7mr260399igb.14.1393847671912; Mon, 03 Mar 2014 03:54:31 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no2516428igb.0!news-out.google.com!gi6ni4igc.0!nntp.google.com!r2no1679161igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 03:54:31 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=59.97.10.124; posting-account=_wB-cAoAAAD5BXfA_MyiShyJ9oSzzhj1 NNTP-Posting-Host: 59.97.10.124 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> Subject: Execution of a process without an event occurring in its sensitivity list From: Raja Harsha Injection-Date: Mon, 03 Mar 2014 11:54:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7343 Hi, Is it possible that a process gets executed even when there is no change in the inputs given in the sensitivity list? For example, Process (x,y,z) begin if a='1' then c<=d+f; p=r-q; end if; end process; In the above program, if i change a or d or any other input except x or y or z, does the process get executed? I have read in some literature that a process gets executed only once by default and then only when there is a change in signals mentioned in the sensitivity list. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.136.35 with SMTP id px3mr8486213veb.31.1393852359313; Mon, 03 Mar 2014 05:12:39 -0800 (PST) X-Received: by 10.140.105.54 with SMTP id b51mr26737qgf.29.1393852359246; Mon, 03 Mar 2014 05:12:39 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no4871525qab.1!news-out.google.com!bw18ni88qab.1!nntp.google.com!hw13no4871521qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 05:12:39 -0800 (PST) In-Reply-To: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2a2c293b-607d-455d-8bb2-5a03750a3ea3@googlegroups.com> Subject: Re: Execution of a process without an event occurring in its sensitivity list From: KJ Injection-Date: Mon, 03 Mar 2014 13:12:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1431 X-Received-Body-CRC: 2531596902 Xref: news.eternal-september.org comp.lang.vhdl:7344 On Monday, March 3, 2014 6:54:31 AM UTC-5, Raja Harsha wrote: > I have read in some literature that a process gets executed only once by > default and then only when there is a change in signals mentioned in the > sensitivity list. That is correct. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Execution of a process without an event occurring in its sensitivity list Date: Mon, 03 Mar 2014 09:55:07 -0500 Organization: Alacron, Inc. Lines: 21 Message-ID: References: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> <2a2c293b-607d-455d-8bb2-5a03750a3ea3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 3 Mar 2014 14:56:13 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="15901"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QBIE8UaH8D6vVITwUNN9CPOd1Wuxxoqk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <2a2c293b-607d-455d-8bb2-5a03750a3ea3@googlegroups.com> Cancel-Lock: sha1:hz6INJCvXMRRASlKcTfioenFNqo= Xref: news.eternal-september.org comp.lang.vhdl:7345 KJ wrote: > On Monday, March 3, 2014 6:54:31 AM UTC-5, Raja Harsha wrote: >> I have read in some literature that a process gets executed only once by >> default and then only when there is a change in signals mentioned in the >> sensitivity list. > > That is correct. > > Kevin Jennings > You should qualify this by saying it's correct for simulation. For synthesis the tool will normally assume that there is complete coverage in the sensitivity list, and it will generate logic that depends on all inputs regardless of whether there is a change on x, y, z or not. On the other hand the way the question was worded, I assume means we're talking about simulation, because there's no concept of a process being executed in the synthesized hardware. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Execution of a process without an event occurring in its sensitivity list Date: Mon, 03 Mar 2014 10:03:58 -0500 Organization: Alacron, Inc. Lines: 27 Message-ID: References: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> <2a2c293b-607d-455d-8bb2-5a03750a3ea3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 3 Mar 2014 15:05:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="18695"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+OscDkeOfKdRZLYFWcgMX3KyT89Yz67c=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:C/jyQuksa2OQMaCvPTCD48RqwgU= Xref: news.eternal-september.org comp.lang.vhdl:7346 GaborSzakacs wrote: > KJ wrote: >> On Monday, March 3, 2014 6:54:31 AM UTC-5, Raja Harsha wrote: >>> I have read in some literature that a process gets executed only once >>> by default and then only when there is a change in signals mentioned >>> in the sensitivity list. >> >> That is correct. >> >> Kevin Jennings >> > > You should qualify this by saying it's correct for simulation. For > synthesis the tool will normally assume that there is complete > coverage in the sensitivity list, and it will generate logic that > depends on all inputs regardless of whether there is a change on > x, y, z or not. On the other hand the way the question was worded, > I assume means we're talking about simulation, because there's > no concept of a process being executed in the synthesized hardware. > I forgot to add that the synthesis tool will also generate a warning when it completes the sensitivity list for you, indicating that your hardware implementation may not match the behavioral simulation. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!news.tele.dk!news.tele.dk!small.news.tele.dk!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!feed.news.schlund.de!schlund.de!news.online.de!not-for-mail From: Michael Dreschmann Newsgroups: comp.lang.vhdl Subject: Comparison with ieee_proposed.fixed_pkg Date: Tue, 25 Feb 2014 03:55:21 +0100 Organization: 1&1 Internet AG Lines: 106 Message-ID: NNTP-Posting-Host: dslb-092-074-236-214.pools.arcor-ip.net Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: online.de 1393296922 6530 92.74.236.214 (25 Feb 2014 02:55:22 GMT) X-Complaints-To: abuse@einsundeins.com NNTP-Posting-Date: Tue, 25 Feb 2014 02:55:22 +0000 (UTC) User-Agent: ForteAgent/7.20.32.1218 trialware Xref: news.eternal-september.org comp.lang.vhdl:7347 Hi all, I'm using the ieee_proposed.fixed_pkg library for a new project. I use Modelsim for simulation and so far everything looked really nice until I tested some developed cores in actual FPGA hardware. I want to use the VHDL code posted below to multiply an angle (in_t) by a variable number (in_scale) and wrap the result over so that it stays within a range of -180 to +180 degrees. Everything works fine in simulation and also XST doesn't show any warnings or errors. However, when I test the module in a real FPGA it seems that all "if conditions" comparing sfixed values (if (tmp_cor >= to_sfixed(180.0, tmp_cor)) then) always return false. When I convert the sfixed signals to signed vectors before performing the comparison everything works as desired: (if (to_signed(tmp_cor, 9 + scale_width + t_precision) >= to_signed(to_sfixed(180.0, tmp_cor), 9 + scale_width + t_precision)) then). I tried ISE 13.3 and 14.4, each time with the fixed_pkg library provided with the ISE version. Does anyone has made similar observations and might even have a solution for this problem? Best regards and thanks in advance, Michael ----- library ieee; use ieee.std_logic_1164.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; entity tscale is generic ( scale_width: integer := 3; scale_precision: integer := 12; t_precision: integer := 12 ); port ( clk: in std_logic; in_strb: in std_logic; in_t: in sfixed(8 downto -t_precision); in_scale: in sfixed(scale_width - 1 downto -scale_precision); in_offset: in sfixed(8 downto -t_precision); -- applied to the scaled input out_strb: out std_logic; out_t: out sfixed(8 downto -t_precision) ); end tscale; architecture rtl of tscale is signal tmp_strb: std_logic; signal tmp_t: sfixed(8 + scale_width downto -t_precision); signal tmp_cor: sfixed(8 + scale_width downto -t_precision); signal cor_active: std_logic; begin process(clk) begin if rising_edge(clk) then tmp_strb <= in_strb; if (in_strb = '1') then tmp_t <= resize((in_t * in_scale) + in_offset, tmp_t); end if; end if; end process; process(clk) variable done: std_logic; variable strb_req: std_logic; begin if rising_edge(clk) then out_strb <= '0'; done := '0'; if (tmp_strb = '1') then tmp_cor <= tmp_t; cor_active <= '1'; end if; if (cor_active = '1') then if (tmp_cor >= to_sfixed(180.0, tmp_cor)) then -- correct angle overflow tmp_cor <= resize(tmp_cor - to_sfixed(360.0, tmp_cor), tmp_cor); elsif (tmp_cor < to_sfixed(-180.0, tmp_cor)) then tmp_cor <= resize(tmp_cor + to_sfixed(360.0, tmp_cor), tmp_cor); else cor_active <= '0'; done := '1'; end if; end if; if (done = '1') then out_strb <= cor_active; out_t <= resize(tmp_cor, 8, -t_precision); end if; end if; end process; end rtl; From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.182.252.235 with SMTP id zv11mr14367933obc.43.1393863723143; Mon, 03 Mar 2014 08:22:03 -0800 (PST) X-Received: by 10.182.28.129 with SMTP id b1mr11810obh.37.1393863722986; Mon, 03 Mar 2014 08:22:02 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!r2no2096337igi.0!news-out.google.com!h8ni8igy.0!nntp.google.com!r2no2096324igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 08:22:02 -0800 (PST) In-Reply-To: <7347c185-8070-489e-8d65-1009f1e0f2bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <390690de-20ec-46e0-a5e2-54630c22f837@googlegroups.com> <39f11380-54bf-44e0-a51b-3023d76596e1@googlegroups.com> <7347c185-8070-489e-8d65-1009f1e0f2bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8326dc2c-8e0a-41eb-a9a4-3d787ff55b33@googlegroups.com> Subject: Re: getting the range from a member of a record. From: Andy Injection-Date: Mon, 03 Mar 2014 16:22:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7348 On Friday, February 28, 2014 6:24:29 PM UTC-6, jlo...@gmail.com wrote: > So I need to create a shared variable in the package just to get at what I > should be able to get at anyway? You could instead declare a signal or a constant (either locally or in the type's package) and use it to access the record elements' attributes. Andy From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.66.158.6 with SMTP id wq6mr182757pab.39.1393864768975; Mon, 03 Mar 2014 08:39:28 -0800 (PST) X-Received: by 10.182.119.133 with SMTP id ku5mr209805obb.4.1393864768713; Mon, 03 Mar 2014 08:39:28 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no21562iga.0!news-out.google.com!h8ni9igy.0!nntp.google.com!l13no21551iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 08:39:28 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8aead76c-f5d6-4e1e-814d-cc902d39a49c@googlegroups.com> Subject: Re: problem with unsigned vs std_logic_vector From: Andy Injection-Date: Mon, 03 Mar 2014 16:39:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7349 On Sunday, March 2, 2014 4:05:44 PM UTC-6, Dio Gratia wrote: > ...There's also not an arithmetic operator defined for std_logic_vector by > default in VHDL unless you're also using synopsys's package > std_logic_unsigned. VHDL-2008 includes the package ieee.numeric_standard_unsigned, which defines arithmetic operators with std_logic_vector operands for unsigned arithmetic. > You should consider it anathema to mix numeric_std (which provides unsigned) > with synopsys's packages. Amen. If your synthesis/simulation vendor does not support VHDL-2008, tell them you need it, or switch tools. Even with the two ieee packages, I doubt there is an operator defined to add an SLV to an unsigned. Just don't go there... Andy From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.18.196 with SMTP id l44mr8025454yhl.52.1393865450004; Mon, 03 Mar 2014 08:50:50 -0800 (PST) X-Received: by 10.183.1.40 with SMTP id bd8mr211483obd.11.1393865449845; Mon, 03 Mar 2014 08:50:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no5122131qab.1!news-out.google.com!h8ni9igy.0!nntp.google.com!l13no40444iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 08:50:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Comparison with ieee_proposed.fixed_pkg From: Andy Injection-Date: Mon, 03 Mar 2014 16:50:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7350 Are you sure the generics are set the same in simulation as they are in synthesis? To protect yourself against that in your test, you might want to use to_signed(tmp_cor, tmp_cor'length). Andy From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.143.198 with SMTP id l46mr8623232yhj.56.1393871640890; Mon, 03 Mar 2014 10:34:00 -0800 (PST) X-Received: by 10.50.30.66 with SMTP id q2mr293140igh.1.1393871640686; Mon, 03 Mar 2014 10:34:00 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w5no6656925qac.0!news-out.google.com!h8ni3igy.0!nntp.google.com!ur14no3149632igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Mar 2014 10:34:00 -0800 (PST) In-Reply-To: <8aead76c-f5d6-4e1e-814d-cc902d39a49c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.154.132.230; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.154.132.230 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> <8aead76c-f5d6-4e1e-814d-cc902d39a49c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with unsigned vs std_logic_vector From: Dio Gratia Injection-Date: Mon, 03 Mar 2014 18:34:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2910 X-Received-Body-CRC: 4237640559 Xref: news.eternal-september.org comp.lang.vhdl:7351 On Tuesday, March 4, 2014 5:39:28 AM UTC+13, Andy wrote: > On Sunday, March 2, 2014 4:05:44 PM UTC-6, Dio Gratia wrote: > > > ...There's also not an arithmetic operator defined for std_logic_vector by > > > default in VHDL unless you're also using synopsys's package > > > std_logic_unsigned. > > > > VHDL-2008 includes the package ieee.numeric_standard_unsigned, which defines arithmetic operators with std_logic_vector operands for unsigned arithmetic. Technically it's by inheritance. numeric_std_unsigned defines arithemetic and other operators for std_ulogic_vector which the 2008 std_logic_1164 package defines standard_logic_vector as a resolved subtype of. > > > You should consider it anathema to mix numeric_std (which provides unsigned) > > > with synopsys's packages. > > > > Amen. If your synthesis/simulation vendor does not support VHDL-2008, tell them you need it, or switch tools. > > > > Even with the two ieee packages, I doubt there is an operator defined to add an SLV to an unsigned. Just don't go there... See the bit above about standard_logic_vector being a subtype of std_ulogic_vector. In 2008 unsigned is a resolved UN_RESOLVED_UNSIGNED which is an array type of STD_ULOGIC. They two array types (standard_logic_vector and UNSIGNED) aren't closely related. Their elements do have the same base type. > And imagine how few religious arguments over types we'd have today if unsigned had been an alias for std_logic_vector originally. They're all just bags of bits (arrays) and the hardware (the 'H' in VHDL) really doesn't care. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.23.170 with SMTP id n10mr202904vef.25.1393950560854; Tue, 04 Mar 2014 08:29:20 -0800 (PST) X-Received: by 10.50.47.48 with SMTP id a16mr391317ign.6.1393950560737; Tue, 04 Mar 2014 08:29:20 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no613424qab.1!news-out.google.com!h8ni11igy.0!nntp.google.com!ur14no994893igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 08:29:20 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.179; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.179 References: <17e8e334-3e25-4079-ae32-a9e2b33fd30a@googlegroups.com> <2a2c293b-607d-455d-8bb2-5a03750a3ea3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d1a439b-ad8a-468e-8e28-640afd24343c@googlegroups.com> Subject: Re: Execution of a process without an event occurring in its sensitivity list From: Daniel Kho Injection-Date: Tue, 04 Mar 2014 16:29:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7352 > > You should qualify this by saying it's correct for simulation. For >=20 > > synthesis the tool will normally assume that there is complete >=20 > > coverage in the sensitivity list, and it will generate logic that >=20 > > depends on all inputs regardless of whether there is a change on >=20 > > x, y, z or not. On the other hand the way the question was worded, >=20 > > I assume means we're talking about simulation, because there's >=20 > > no concept of a process being executed in the synthesized hardware. >=20 > >=20 >=20 >=20 >=20 > I forgot to add that the synthesis tool will also generate a warning >=20 > when it completes the sensitivity list for you, indicating that your >=20 > hardware implementation may not match the behavioral simulation. >=20 >=20 >=20 > --=20 >=20 > Gabor Yes, what Gabor said is correct. Synthesis tools usually trigger processes = by inferring all inputs instead of looking at the sensitivity list. This is= one of the few things that synthesis tools tend to behave differently from= simulation tools. I still prefer that synthesis tools infer no logic when = none of the signals in the sensitivity list changes. Simulation tools follo= w the standard more strictly than synthesis tools in this respect. From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Luis Cupido Newsgroups: comp.lang.vhdl Subject: loop 10000 iterations limit in quartusII. Date: Tue, 04 Mar 2014 16:47:38 +0000 Organization: Aioe.org NNTP Server Lines: 22 Message-ID: NNTP-Posting-Host: 9G/GNxqVFY7HdOa4Nmi99g.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7353 Hello, I have a perfect working VHDL code that fills in a RAM with sine sine and cosine tables. All works just fine. As soon as I wanted to generate 16K or 32K of tables, bang! compilation aborts and Quartus says it exists loops after 10000 iterations. The help at altera site says it is intentional to prevent (dumb) users from infinite loops Furthermor they say if one wants more than 10000 iteration go break the loop into more loops below 10000 iterations !!! How bizarre !!! couldn't it just issue a warning ?... (even DOS asked "are you sure" on del *.*... how funny it would be to see "you are deleting too much files, go delete one by one") Ahhgggg !!! Anyone one knows a way to bypass this ? I would hate to slice my beautiful loops. specially as the component has its size passed up on generics. Luis C. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.94.48 with SMTP id m36mr248003yhf.47.1393953589666; Tue, 04 Mar 2014 09:19:49 -0800 (PST) X-Received: by 10.182.251.194 with SMTP id zm2mr8623obc.12.1393953589468; Tue, 04 Mar 2014 09:19:49 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!w5no638672qac.0!news-out.google.com!h8ni11igy.0!nntp.google.com!ur14no1027717igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 09:19:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> Subject: Re: loop 10000 iterations limit in quartusII. From: Jim Lewis Injection-Date: Tue, 04 Mar 2014 17:19:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7354 Hi Luis, This is an indication of something iterating on delta cycles. I am assumin= g that you are treating the RAM as a ROM and pre-filling it some how. It i= s likely that the pre-fill operation has a "wait for 0 ns ;" in it. =20 The group can give you more insight if you are willing to post your code. In hardware, while delta cycles do not correspond directly to actual delays= in your circuit, after synthesis they will be roughly proportional to your= circuit delays. As a result, if you have 10,000 delta cycles in your actu= al hardware, you are generally out of luck in creating logic of any reasona= ble speed. Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!aioe.org!.POSTED!not-for-mail From: Luis Cupido Newsgroups: comp.lang.vhdl Subject: Re: loop 10000 iterations limit in quartusII. Date: Tue, 04 Mar 2014 20:28:33 +0000 Organization: Aioe.org NNTP Server Lines: 53 Message-ID: References: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> NNTP-Posting-Host: 9G/GNxqVFY7HdOa4Nmi99g.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7355 Tks. Jim. It is indeed a ROM using RAM blocks and the loop is the fill in of the ROM contents. None of those loops actually synthesize into hardware they just generate the memory initialization file, as expected. So quartus really interpreted my coding correctly. And all works beautifully if the loop size stays below 10000 iterations. Here is the altera info: "CAUSE: ... you specified a loop that does not terminate within 10,000 iterations. This message may occur because the loop's terminating condition depends on a signal or non-constant variable. You may also have forgotten to increment a variable in the loop's terminating condition. To avoid an infinite loop or memory exhaustion, Quartus II Integrated Synthesis prematurely terminated the synthesis of your design. ACTION: Check the loop for errors or non-constant terminating conditions. If you can guarantee that your loop will exit within 10,000 iterations, you can bypass this error by adding an explicit exit statement that terminates the loop after N < 10,000 iterations. If your loop should iterate more than 10,000 times, <<< you will need to factor the loop into multiple loops with 10,000 or fewer iterations each.>>>" Last sentence is killing me as it sounds too silly to be true !!! Here is my loop: impure function SinFillTab return rom_type is variable cpt: integer:=0; variable rom_tmp: rom_type; begin cpt := 0; while (cpt < QUART) loop rom_tmp(cpt) := to_signed(integer(real(AMP)*sin( real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16); cpt := cpt + 1; end loop; return(rom_tmp); end SinFillTab; -- Luis C. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.120.33 with SMTP id kz1mr869445veb.2.1393967009840; Tue, 04 Mar 2014 13:03:29 -0800 (PST) X-Received: by 10.50.13.1 with SMTP id d1mr42436igc.0.1393967009738; Tue, 04 Mar 2014 13:03:29 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w5no731833qac.0!news-out.google.com!h8ni13igy.0!nntp.google.com!l13no1667212iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 13:03:29 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: loop 10000 iterations limit in quartusII. From: Jim Lewis Injection-Date: Tue, 04 Mar 2014 21:03:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7356 Hi Luis, That indeed is a silly error. Surely an artifact of when ROMs were never that big - :). Did you try a nested pair of loops such as the following (minus any bugs I might have coded). It seems like a simple check that you might be able to work around to some degree. impure function SinFillTab return rom_type is variable cpt, IterationLimit : integer:=0; variable rom_tmp: rom_type; begin cpt := 0; OUTER : while (cpt < QUART) loop IterationLimit := 1; INNER : while (IterationLimit < 10,000 and cpt < QUART) loop rom_tmp(cpt) := to_signed(integer(real(AMP)*sin( real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16); cpt := cpt + 1; IterationLimit := IterationLimit + 1 ; end loop INNER ; end loop OUTER ; return(rom_tmp); end SinFillTab; Have you submitted a bug report to them? I would include your code so they know it is their silly issue and not yours. Jim From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.182.109.200 with SMTP id hu8mr954712obb.20.1393968368977; Tue, 04 Mar 2014 13:26:08 -0800 (PST) X-Received: by 10.140.25.79 with SMTP id 73mr3179qgs.42.1393968368947; Tue, 04 Mar 2014 13:26:08 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1680257iga.0!news-out.google.com!du2ni225qab.0!nntp.google.com!w5no739152qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 13:26:08 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: loop 10000 iterations limit in quartusII. From: KJ Injection-Date: Tue, 04 Mar 2014 21:26:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7357 On Tuesday, March 4, 2014 3:28:33 PM UTC-5, Luis Cupido wrote: >=20 > It is indeed a ROM using RAM blocks and the loop is the fill in of the=20 >=20 > ROM contents. >=20 - Have you tried a for loop rather than a while loop? Maybe the checking f= or 10,000 is only done on 'while' loops since 'while' depend on a loop cond= ition that the synthesizer needs to evaluate on each loop. A 'for' loop ca= n be statically analyzed to determine exactly how many loops would be neede= d so there should be no reason for it to limit you there. - As Jim mentioned, submit the case to Altera. Even if you're using the fr= ee tools and maybe not getting any actual support, it does at least send so= mething into them about problems with their tools that they might decide to= fix. - When you submit to Altera, might also ask if there is any way to modify t= hat 10,000 limit so that you can work around this limitation in their tool. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.66.144.170 with SMTP id sn10mr117638pab.43.1393976417626; Tue, 04 Mar 2014 15:40:17 -0800 (PST) X-Received: by 10.50.70.3 with SMTP id i3mr107941igu.3.1393976417518; Tue, 04 Mar 2014 15:40:17 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.etla.org!news.litech.org!news.glorb.com!l13no1730032iga.0!news-out.google.com!h8ni18igy.0!nntp.google.com!ur14no1230269igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 15:40:17 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <573a95bc-2196-45b6-b42a-44f9f169ecdc@googlegroups.com> <8aead76c-f5d6-4e1e-814d-cc902d39a49c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <44f15931-f362-44c9-9740-3123ce53403f@googlegroups.com> Subject: Re: problem with unsigned vs std_logic_vector From: Andy Injection-Date: Tue, 04 Mar 2014 23:40:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7358 On Monday, March 3, 2014 12:34:00 PM UTC-6, Dio Gratia wrote: > They two array types (standard_logic_vector and UNSIGNED) aren't closely > related. Their elements do have the same base type.=20 This is not true. The BASE TYPES of std_logic_vector and unsigned are both = arrays of std_ulogic. That makes them closely related. > And imagine how few religious arguments over types we'd have today if uns= igned > had been an alias for std_logic_vector originally. They're all just bags = of > bits (arrays) and the hardware (the 'H' in VHDL) really doesn't care. How do you specify that you want SLV to have an unsigned numeric representa= tion? VHDL lets you (or other users before you) write packages that do that= for you, or define the SLV representation as twos-complement, signed or un= signed fixed point, or floating point. When you want to mix them, VHDL want= s to know explicitly how you want them mixed, so it can accurately model th= e behavior you want. From an accurate model, accurate hardware can be synth= esized, rather than guessed at. If all you want to do is describe HW structure/implementation instead of be= havior, use edif. It doesn't care either. Andy From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Luis Cupido Newsgroups: comp.lang.vhdl Subject: Re: loop 10000 iterations limit in quartusII. Date: Wed, 05 Mar 2014 00:23:47 +0000 Organization: Aioe.org NNTP Server Lines: 33 Message-ID: References: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> NNTP-Posting-Host: 9G/GNxqVFY7HdOa4Nmi99g.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7359 On 3/4/2014 9:26 PM, KJ wrote: > - Have you tried a for loop rather than a while loop? Thanks for the hint. indeed It WORKS fine with a "for loop". Okay... I can understand their reasons... even so I would prefer to be the the one that make infinite loops occasionally rather then be restricted from writing code freely. IMHO this would be a very good case for a warning and not for a show stopper. if one suspected that the compiler is taking too long would see the warning and decide to abort or let it continue. >> this one goes to happily to any size<< impure function SinFillTab return rom_type is variable cpt: integer:=0; variable rom_tmp: rom_type; begin for cpt in 0 to QUART-1 loop rom_tmp(cpt) := to_signed(integer(real(AMP)*sin( real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16); end loop; return(rom_tmp); end SinFillTab; --- tks to all. Luis C. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.66.218.70 with SMTP id pe6mr1814008pac.33.1394002394958; Tue, 04 Mar 2014 22:53:14 -0800 (PST) X-Received: by 10.50.59.179 with SMTP id a19mr455556igr.10.1394002394811; Tue, 04 Mar 2014 22:53:14 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no1341889igb.0!news-out.google.com!h8ni18igy.0!nntp.google.com!ur14no1341886igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Mar 2014 22:53:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.179; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.179 References: <01256492-9ae4-49df-abe7-ba106735a06a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: loop 10000 iterations limit in quartusII. From: Daniel Kho Injection-Date: Wed, 05 Mar 2014 06:53:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7360 > - When you submit to Altera, might also ask if there is any way to modify= that 10,000 limit so that you can work around this limitation in their too= l.=20 This reminds me of a case I filed to Altera a long time ago. I remember Mod= elSim giving me an "iteration limit reached" error, but Quartus failed to g= ive me any error at the time. For your case, seems like Quartus did finally= give an error when the iteration limit is reached. The case I filed to Altera points to the fact that Quartus supports Verilog= iteration limits, but not for VHDL. It didn't seem to make any sense that = they could do for one language and ignore the other. Anyway, you got me che= cking back on this again. I saw that there is no option for us to change the iteration limit (though = the one for Verilog is still there): Assignments > Settings > Analysis & Synthesis Settings > More Settings > It= eration limit for (non-)constant Verilog loops Perhaps Altera is slowly supporting VHDL iteration limits, though the featu= re to change it away from 10,000 is not there yet. As with others, I suggest you file a case with Altera. -daniel From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.224.47.129 with SMTP id n1mr3205473qaf.4.1394044364849; Wed, 05 Mar 2014 10:32:44 -0800 (PST) X-Received: by 10.50.66.197 with SMTP id h5mr378979igt.16.1394044364660; Wed, 05 Mar 2014 10:32:44 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed0.kamp.net!newsfeed.kamp.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.87.MISMATCH!w5no1026777qac.0!news-out.google.com!h8ni13igy.0!nntp.google.com!l13no2033112iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Mar 2014 10:32:44 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.102.103.12; posting-account=bhVurwoAAADeuE5lbJ0GcSAQ38Dh-VeP NNTP-Posting-Host: 14.102.103.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c638276-fae9-42c0-9510-391ff4d749ed@googlegroups.com> Subject: code for Arbiter in verilog From: Anish Gupta Injection-Date: Wed, 05 Mar 2014 18:32:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7361 Did any one know the code for Arbiter in verilog just for 4 masters calling and storing data in Sram based on the priority. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.182.65.168 with SMTP id y8mr2055506obs.38.1394046227561; Wed, 05 Mar 2014 11:03:47 -0800 (PST) X-Received: by 10.140.27.43 with SMTP id 40mr40603qgw.27.1394046227532; Wed, 05 Mar 2014 11:03:47 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ur14no1662157igb.0!news-out.google.com!bw18ni1187qab.1!nntp.google.com!w5no1035422qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Mar 2014 11:03:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.84.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.84.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a330ac9-b0b9-48b1-95b0-ade87b8a0bd5@googlegroups.com> Subject: [ANN] Availability for remote task/assignment work From: Nikolaos Kavvadias Injection-Date: Wed, 05 Mar 2014 19:03:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2159 X-Received-Body-CRC: 3292572762 Xref: news.eternal-september.org comp.lang.vhdl:7362 Dear all, I hope you are doing well! I would like to let you know that I'm actively seeking for collaboration opportunities, such as permanent work, contract work or (remote or on-site) project/task assignments regarding: - custom EDA (Electronic Design Automation) tool development - VHDL and/or Verilog HDL IP development - compiler (frontend, analyses/optimizations, backend) development - FPGA-based system prototype development For indicative reasons, I disclose my rates as an independent collaborator: - Hourly rate (remotely): 29 EUR - Hourly rate (on-site): 49 EUR - Daily rate (remotely): 129 EUR - Daily rate (on-site; Greece): 199 EUR - Full day on-site consultancy fee (abroad; accomodation and travel expenses not included): 295 EUR Of course, flat fees per specific assignment basis are also possible and can be negotiated. In case you have anything in mind I would be interested to know. Best regards Nikolaos Kavvadias http://www.nkavvadias.com Independent Research Scientist / CEO Ajax Compilers Lamia, Greece PS: I apologize for the cross-posting; this newsgroup is highly relevant to my interests. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.236.69.35 with SMTP id m23mr6653781yhd.6.1394182342816; Fri, 07 Mar 2014 00:52:22 -0800 (PST) X-Received: by 10.140.101.171 with SMTP id u40mr280569qge.1.1394182342789; Fri, 07 Mar 2014 00:52:22 -0800 (PST) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no2038242qab.1!news-out.google.com!bw18ni3075qab.1!nntp.google.com!hw13no2038237qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 7 Mar 2014 00:52:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.84.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.84.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98197987-711a-4b17-b558-c935565c74e5@googlegroups.com> Subject: Multi-function, universal, CORDIC IP available from the OpenCores website From: Nikolaos Kavvadias Injection-Date: Fri, 07 Mar 2014 08:52:22 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3165 X-Received-Body-CRC: 2273358579 Xref: news.eternal-september.org comp.lang.vhdl:7363 Dear all, I hope you are doing well. Just wanted to let you know that I've uploaded one of my first "serious" de= signs passed through HercuLeS HLS: http://www.nkavvadias.com/hercules/ This was around 2010, and it was an HLS showcase for a partner/client in Eu= rope. I can finally distribute the test case freely so here you are: http://www.opencores.org/project,kvcordic Description:=20 The design is a universal CORDIC IP core supporting all directions (ROTATIO= N, VECTORING) and modes (CIRCULAR, LINEAR, HYPERBOLIC). The I/O interface is s= imilar to e.g. the CORDIC IP generated by Xilinx Core Generator). It provid= es three data inputs (xin,yin, zin) and three data outputs (xout,yout, zout= ) as well as the direction and mode control inputs. The testbench will test= the core for computing cos (xin), sin (yin), arctan(yin/xin), yin/xin, =E2= =88=9Aw, 1/=E2=88=9Aw, with xin =3D w + 1/4, yin =3D w =E2=88=92 1/4, but it can be used for anything c= omputable by CORDIC iterations. The computation of 1/=E2=88=9Aw is performe= d in two stages: a) y =3D 1/w, b) z =3D =E2=88=9Ay.=20 The design is a monolithic FSMD that does not include post-processing neede= d such as the scaling operation for the square root. The FSMD for the CORDI= C uses Q2.14 =EF=AC=81xed-point arithmetic. The core achieves 18 (CIRCULAR,= LINEAR) and 19 cycles (HYPERBOLIC) per sample or n + 4 and n + 5 cycles, r= espectively, where n is the fractional bitwidth. A single-cycle per iterati= on constraint imposes the use of distributed LUT RAM, otherwise 3 cycles are required per sample (dis= tinct load, compute, store cycles). SPECIAL THANKS: Go to MSc and PhD candidate Mrs. Vasiliki Giannakopoulou fo= r explaining to me how CORDIC works and for implementing a hand-coded optim= ized version to compare with! Her hand-written CORDIC is also blazing fast = for a portable non-Xilinx or non-Altera specific design. Best regards, Nikolaos Kavvadias Independent Research Scientist / Hardware engineer / EDA developer http://www.nkavvadias.com Lamia, Greece From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.187.6 with SMTP id fo6mr10211304vec.34.1394361558440; Sun, 09 Mar 2014 03:39:18 -0700 (PDT) X-Received: by 10.140.20.77 with SMTP id 71mr268qgi.17.1394361558366; Sun, 09 Mar 2014 03:39:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no2717323qab.1!news-out.google.com!bw18ni3075qab.1!nntp.google.com!hw13no2717322qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Mar 2014 03:39:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.85.0.97; posting-account=EasocgoAAAB-ekRV1jaJlH9Ox5t2qeg6 NNTP-Posting-Host: 141.85.0.97 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a010fe9-effa-4436-b1da-27f7861a73cd@googlegroups.com> Subject: Need help designing a circuit in Verilog From: eithriad@gmail.com Injection-Date: Sun, 09 Mar 2014 10:39:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7364 Define and design a circuit which receives a one-bit wave form and shows on its three one-bit outputs, by one clock cycle long positive impulses, the following events: -any positive transition of the input signal -any negative transition of the input signal -any transition of the input signal From newsfish@newsfish Tue Dec 29 16:43:20 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx32.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: Need help designing a circuit in Verilog Newsgroups: comp.lang.vhdl References: <6a010fe9-effa-4436-b1da-27f7861a73cd@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 13 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1394388589 62.49.20.82 (Sun, 09 Mar 2014 18:09:49 UTC) NNTP-Posting-Date: Sun, 09 Mar 2014 18:09:49 UTC Date: Sun, 09 Mar 2014 18:09:49 GMT X-Received-Body-CRC: 3191459261 X-Received-Bytes: 1250 Xref: news.eternal-september.org comp.lang.vhdl:7365 On Sun, 09 Mar 2014 03:39:18 -0700, eithriad wrote: > Define and design a circuit which receives a one-bit wave form and shows > on its three one-bit outputs, by one clock cycle long positive impulses, > the following events: > -any positive transition of the input signal -any negative transition of > the input signal -any transition of the input signal comp.lang.vhdl is probably not the best group for a Verilog question. - Brian From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.224.36.137 with SMTP id t9mr832420qad.4.1394388838133; Sun, 09 Mar 2014 11:13:58 -0700 (PDT) X-Received: by 10.140.105.54 with SMTP id b51mr3720qgf.29.1394388838118; Sun, 09 Mar 2014 11:13:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no2818974qab.1!news-out.google.com!du2ni1227qab.0!nntp.google.com!w5no2848284qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Mar 2014 11:13:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.84.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.84.194 References: <6a010fe9-effa-4436-b1da-27f7861a73cd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Need help designing a circuit in Verilog From: Nikolaos Kavvadias Injection-Date: Sun, 09 Mar 2014 18:13:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7366 =CE=A4=CE=B7 =CE=9A=CF=85=CF=81=CE=B9=CE=B1=CE=BA=CE=AE, 9 =CE=9C=CE=B1=CF= =81=CF=84=CE=AF=CE=BF=CF=85 2014 8:09:49 =CE=BC.=CE=BC. UTC+2, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Brian Drummond =CE=AD=CE=B3=CF=81= =CE=B1=CF=88=CE=B5: > On Sun, 09 Mar 2014 03:39:18 -0700, eithriad wrote: >=20 >=20 >=20 > > Define and design a circuit which receives a one-bit wave form and show= s >=20 > > on its three one-bit outputs, by one clock cycle long positive impulses= , >=20 > > the following events: >=20 > > -any positive transition of the input signal -any negative transition o= f >=20 > > the input signal -any transition of the input signal >=20 >=20 >=20 > comp.lang.vhdl is probably not the best group for a Verilog question. >=20 >=20 >=20 > - Brian Indeed, the OP should try comp.lang.vhdl, albeit this homework question loo= ks like a classic one. From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.58.231.201 with SMTP id ti9mr9378395vec.5.1394388863297; Sun, 09 Mar 2014 11:14:23 -0700 (PDT) X-Received: by 10.140.48.177 with SMTP id o46mr1978qga.35.1394388863236; Sun, 09 Mar 2014 11:14:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no2819174qab.1!news-out.google.com!bw18ni3075qab.1!nntp.google.com!hw13no2819173qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Mar 2014 11:14:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.84.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.84.194 References: <6a010fe9-effa-4436-b1da-27f7861a73cd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <101c2827-bbbe-4cf4-94c7-21d7394b258a@googlegroups.com> Subject: Re: Need help designing a circuit in Verilog From: Nikolaos Kavvadias Injection-Date: Sun, 09 Mar 2014 18:14:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1267 X-Received-Body-CRC: 3394072401 Xref: news.eternal-september.org comp.lang.vhdl:7367 geez I meant comp.lang.verilog, go figure From newsfish@newsfish Tue Dec 29 16:43:20 2015 X-Received: by 10.224.124.5 with SMTP id s5mr9080264qar.1.1395057156665; Mon, 17 Mar 2014 04:52:36 -0700 (PDT) X-Received: by 10.140.91.45 with SMTP id y42mr26013qgd.26.1395057156639; Mon, 17 Mar 2014 04:52:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w5no5385561qac.0!news-out.google.com!bw18ni15307qab.1!nntp.google.com!hw13no5357203qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Mar 2014 04:52:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.84.194; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.84.194 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <90e471a2-f411-4235-b36f-afbb756e8ea8@googlegroups.com> Subject: VHDL simulator supporting SCE-MI or vendor's DPI? From: Nikolaos Kavvadias Injection-Date: Mon, 17 Mar 2014 11:52:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1911 X-Received-Body-CRC: 4152731064 Xref: news.eternal-september.org comp.lang.vhdl:7368 Dear all, I would like to ask whether there exists any VHDL simulator (either FLOSS, = commercial freeware or commercial for licensing) that supports the SCE-MI (= Standard Co-emulation Modeling Interface) standard, whether 2.1 or 2.2. You= can read more about SCE-MI here: http://www.accellera.org/downloads/standards/sce-mi/SCE-MI_v22-140120-final= .pdf I can find mentions of SCE-MI on Mentor Graphics and Aldec blogs but I'm no= t sure if it is supported by the current state of the tools. My AE Modelsim= version (10.1d), for instance, supports the DPI (Direct Programming Interf= ace) but I'm not sure about SCE-MI. GHDL and Icarus probably don't support it or am I wrong? An alternative would be if any vendor that has their own implementation of = DPI for VHDL, maybe? Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: [cross-post]path verification Followup-To: comp.lang.vhdl Date: 17 Mar 2014 15:44:41 GMT Lines: 35 Message-ID: X-Trace: individual.net ufauPrv5f1xocus4eGcafg0XxsmH2XwtcmtjQdmDZ0sncGozKj X-Orig-Path: not-for-mail Cancel-Lock: sha1:cn8vu6yRL2q26+HrC3zsh4/+zaU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7369 comp.arch.fpga:20275 Dear all, I have a microcontroller with an FPU which is delivered as an IP (I mean the FPU). In order to run at a decent frequency, some of the operations are allowed to complete in within a certain amount of cycles, but the main problem is that we do not know how many. That said, if we run the synthesis tool without timing constraints on those paths, we have a design that is much slower than can be. Multicycle constraints are out of question because they are hard to verify and maintain, so we decided to set false paths and perform post-layout sims to extract those values to be used in the RTL in a second iteration. There are several reasons why I do not particularly like this approach: 1. it relies on post-layout sims which are resource consuming 2. if we change technology we will likely need to do the whole process again 3. we are obliged to perform incremental place&route since an optimized implementation (maybe done automatically) may have an impact on our delays. So far we have not come out with an alternative solution that is not going to imply redesign (like pipelining, c-slowing, retiming, ...). Any ideas/suggestions? Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.fsmpi.rwth-aachen.de!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx29.am4.POSTED!not-for-mail Message-ID: <532736EC.1000103@htminuslab.com> From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL simulator supporting SCE-MI or vendor's DPI? References: <90e471a2-f411-4235-b36f-afbb756e8ea8@googlegroups.com> In-Reply-To: <90e471a2-f411-4235-b36f-afbb756e8ea8@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140317-0, 17/03/2014), Outbound message X-Antivirus-Status: Clean Lines: 30 NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1395078892 86.29.12.221 (Mon, 17 Mar 2014 17:54:52 UTC) NNTP-Posting-Date: Mon, 17 Mar 2014 17:54:52 UTC Organization: virginmedia.com Date: Mon, 17 Mar 2014 17:54:52 +0000 X-Received-Body-CRC: 2005800092 X-Received-Bytes: 2393 Xref: news.eternal-september.org comp.lang.vhdl:7370 On 17/03/2014 11:52, Nikolaos Kavvadias wrote: > Dear all, > > I would like to ask whether there exists any VHDL simulator (either FLOSS, commercial freeware or commercial for licensing) that supports the SCE-MI (Standard Co-emulation Modeling Interface) standard, whether 2.1 or 2.2. You can read more about SCE-MI here: > > http://www.accellera.org/downloads/standards/sce-mi/SCE-MI_v22-140120-final.pdf > > I can find mentions of SCE-MI on Mentor Graphics and Aldec blogs but I'm not sure if it is supported by the current state of the tools. My AE Modelsim version (10.1d), for instance, supports the DPI (Direct Programming Interface) but I'm not sure about SCE-MI. > > GHDL and Icarus probably don't support it or am I wrong? > > An alternative would be if any vendor that has their own implementation of DPI for VHDL, maybe? > > Best regards > Nikolaos Kavvadias > http://www.nkavvadias.com > Hi Nikolaos, SCE-MI is nothing more than a protocol description (like TLM), you can implement it in any language you like. The only issue you have to resolve is the physical layer, that is how are you going to communicate with the hardware. Probably the easiest communication on Modelsim is using sockets (via Tcl/DPI/PLI/FLI) and then use another PC to bridge between the socket and your hardware. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: [cross-post]path verification Date: Mon, 17 Mar 2014 19:31:55 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 55 Message-ID: References: NNTP-Posting-Host: +XZUpqwGg6W4jfUjJWhQTA.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7371 comp.arch.fpga:20278 In comp.arch.fpga alb wrote: > I have a microcontroller with an FPU which is delivered as an IP (I mean > the FPU). In order to run at a decent frequency, some of the operations > are allowed to complete in within a certain amount of cycles, but the > main problem is that we do not know how many. So you paid someone for this? I am not sure what you mean by "a certain number of clock cycles" and "do not know how many". If it is all combinatorial, it will complete with some delay, not in some number of clock cycles. That is, the delay will not depend on any clock you supply. You then have to either be able to run the design through timing analysis and see how long that is, or the ones you bought it from should tell you. Though more usual, the logic should have a signal indicating when the result is valid. You could run the FPU in the timing tools with a variety (random) inputs and find out how long it takes. Then find the distribution of delays, and find a reasonable maximum. It might be data dependent and have a long tail. (A post-normalize shifter might depend on the number of digits being shifted, and the rare long shifts would have to be accounted for.) > That said, if we run the synthesis tool without timing constraints on > those paths, we have a design that is much slower than can be. > Multicycle constraints are out of question because they are hard to > verify and maintain, so we decided to set false paths and perform > post-layout sims to extract those values to be used in the RTL in a > second iteration. > There are several reasons why I do not particularly like this approach: > 1. it relies on post-layout sims which are resource consuming > 2. if we change technology we will likely need to do the whole process > again > 3. we are obliged to perform incremental place&route since an optimized > implementation (maybe done automatically) may have an impact on our > delays. > So far we have not come out with an alternative solution that is not > going to imply redesign (like pipelining, c-slowing, retiming, ...). The FPUs that I know of should be pipelined. (Is there a clock input?) You shouldn't have to do the pipelining, but you do need to know the number of clock cycles (and clock rate) for each operation. If the design is encrypted, such that you can't look at it, they need to give you enough information to be able to use it. -- glen From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 18 Mar 2014 07:47:59 GMT Lines: 105 Message-ID: References: X-Trace: individual.net 6Yyv/Q7j4r689mjyXpo8sgEwmGob1epV+ifC4dpqIOLTpf7HSi X-Orig-Path: not-for-mail Cancel-Lock: sha1:dX7gjOC56vfZlXnwuisE4aPJSlU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7372 Hi Glen, In comp.arch.fpga glen herrmannsfeldt wrote: [] >> I have a microcontroller with an FPU which is delivered as an IP (I mean >> the FPU). In order to run at a decent frequency, some of the operations >> are allowed to complete in within a certain amount of cycles, but the >> main problem is that we do not know how many. > > So you paid someone for this? that is correct. Well it was a development on a european project where several universities did something and then we tried to stich it together... The aim was to have a small footprint embedded microcontroller capable of floating-point calculations. > I am not sure what you mean by "a certain number of clock cycles" > and "do not know how many". I admit I was not too clear, let's try again. The IP is the FPU and it came fully verified but never validated on the hardware (i.e. no P&R, no STA, no backannotate sim). We built around it a microcontroller and now it is time to target the technology for the specific project. So at this stage we do not know, considering the target logic, what is the logic depth for each operation of the FPU and we do not know how many clock cycles we need to wait in order to get the value out at the given target frequency. > If it is all combinatorial, it will complete with some delay, not > in some number of clock cycles. That is, the delay will not depend > on any clock you supply. You then have to either be able to run > the design through timing analysis and see how long that is, or the > ones you bought it from should tell you. As you correctly pointed out the delay does not depend on the clock frequency, but it depends on the target technology and final routing. In order for the microcontroller to work correctly I need to 'wait' for each specific operation a certain amount of clock cycles in order to be able to sample correctly the result. I already know that, at the target frequency, it will take more than one cycle to complete most of the operations, therefore my timing analysis will fail miserably. Not only that, without releasing some timing constraints on some specific path, the synthesis tool will take the worst path and extract the max frequency from that [1]. Regarding the possibility to ask the developer(s), the team has fallen apart in the meanwhile and now we need to chase people around the globe to get some info (not easy). > Though more usual, the logic should have a signal indicating when > the result is valid. that is a valid point indeed, I implicitely assumed there's no such signal, but is equally possible that we haven't 'seen it'. In order to find something you should look for it... > > You could run the FPU in the timing tools with a variety (random) > inputs and find out how long it takes. Then find the distribution > of delays, and find a reasonable maximum. It might be data dependent > and have a long tail. (A post-normalize shifter might depend on the > number of digits being shifted, and the rare long shifts would have > to be accounted for.) I'm not sure I'm following. If for timing tools you mean STA than there's no such a thing like 'variety of inputs', the tool is static and is only calculating delays associated with paths in a graph. What you suggest seems more a post-layout simulation...did I get it wrong? Running the STA without constraining the synthesis tool might be suboptimal since the synthesis tool did not come out with an optimized implementation. >> That said, if we run the synthesis tool without timing constraints on >> those paths, we have a design that is much slower than can be. >> Multicycle constraints are out of question because they are hard to >> verify and maintain, so we decided to set false paths and perform >> post-layout sims to extract those values to be used in the RTL in a >> second iteration. [] > > The FPUs that I know of should be pipelined. (Is there a clock input?) > You shouldn't have to do the pipelining, but you do need to know the > number of clock cycles (and clock rate) for each operation. The FPU is not pipelined otherwise I would have known the amount of clock cycles simply with the depth of the pipe. Am I wrong? Why is not pipelined is a different topic. > If the design is encrypted, such that you can't look at it, they > need to give you enough information to be able to use it. The design is not encrypted but nobody really wanted to dig into those details so far. I agree with you that is probably worth spending some effort to understand how it works in the details and come out with a solution that is suited to fix the root of the problem rather than come up with ad-hoc solutions. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 18 Mar 2014 08:57:35 GMT Lines: 13 Message-ID: References: X-Trace: individual.net 2nZ7YofzrY63BgGbo3jwLAlEeG/qUxuw3F1djK+3ADLnkiOHbi X-Orig-Path: not-for-mail Cancel-Lock: sha1:Cjg0Eeml4zNpJC98yWnKhGuonTQ= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7373 forgot to add a note that I refer to in my previous article... alb wrote: [] > I already know that, at the target frequency, it will take more than one > cycle to complete most of the operations, therefore my timing analysis > will fail miserably. Not only that, without releasing some timing > constraints on some specific path, the synthesis tool will take the > worst path and extract the max frequency from that [1]. [] [1] I actually do not know the way the synthesis tool works, but it seems my simple model pretty much matches what is happening From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.66.102.8 with SMTP id fk8mr14564593pab.24.1395218948305; Wed, 19 Mar 2014 01:49:08 -0700 (PDT) X-Received: by 10.50.59.179 with SMTP id a19mr567179igr.10.1395218947969; Wed, 19 Mar 2014 01:49:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!l13no8211634iga.0!news-out.google.com!dd7ni76igb.0!nntp.google.com!l13no8211626iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Mar 2014 01:49:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.167.73.55; posting-account=hwy8AQoAAAAXhrq-2rjjmxyei7PRsYAW NNTP-Posting-Host: 122.167.73.55 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e8be343-3f93-4eb2-b932-0d6de636a187@googlegroups.com> Subject: Integers which are more than 32 bit From: bipper Injection-Date: Wed, 19 Mar 2014 08:49:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7374 Hello everyone.. I have a top module which has an output in std_logic_vector format of 81 bits. In the test bench code I want to write this output vector (of size 81 bits) into a text file in integer format. But due to the 32 bit size limit of integers its not working. Any round ways to achieve this? Thanks.. From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx33.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140319-1, 19/03/2014), Outbound message X-Antivirus-Status: Clean Lines: 45 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1395247532 86.29.12.221 (Wed, 19 Mar 2014 16:45:32 UTC) NNTP-Posting-Date: Wed, 19 Mar 2014 16:45:32 UTC Organization: virginmedia.com Date: Wed, 19 Mar 2014 16:45:31 +0000 X-Received-Body-CRC: 2265150092 X-Received-Bytes: 2685 Xref: news.eternal-september.org comp.lang.vhdl:7375 On 17/03/2014 15:44, alb wrote: > Dear all, > > I have a microcontroller with an FPU which is delivered as an IP (I mean > the FPU). In order to run at a decent frequency, some of the operations > are allowed to complete in within a certain amount of cycles, but the > main problem is that we do not know how many. > > That said, if we run the synthesis tool without timing constraints on > those paths, we have a design that is much slower than can be. > Multicycle constraints are out of question because they are hard to > verify and maintain, so we decided to set false paths and perform > post-layout sims to extract those values to be used in the RTL in a > second iteration. > > There are several reasons why I do not particularly like this approach: > > 1. it relies on post-layout sims which are resource consuming > 2. if we change technology we will likely need to do the whole process > again > 3. we are obliged to perform incremental place&route since an optimized > implementation (maybe done automatically) may have an impact on our > delays. > > So far we have not come out with an alternative solution that is not > going to imply redesign (like pipelining, c-slowing, retiming, ...). > > Any ideas/suggestions? I would suggest you speak to your boss to see if you can spend some money on getting a Fishtail Focus license. This tool will automatically extract multicyle and false path from your design. The output is a bunch of SDC constraints and assertions (PSL/SVA) for verifications. http://www.fishtail-da.com/ Regards, Hans. www.ht-lab.com > > Al > From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <532b12d8$0$24937$e4fe514c@dreader36.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Integers which are more than 32 bit Newsgroups: comp.lang.vhdl Date: Thu, 20 Mar 2014 17:10:00 +0100 References: <1e8be343-3f93-4eb2-b932-0d6de636a187@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 24 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1395331800 dreader36.news.xs4all.nl 24937 puiterl/195.242.97.150:41124 Xref: news.eternal-september.org comp.lang.vhdl:7376 bipper wrote: > Hello everyone.. > > I have a top module which has an output in std_logic_vector format of 81 > bits. In the test bench code I want to write this output vector (of size > 81 bits) into a text file in integer format. But due to the 32 bit size > limit of integers its not working. Any round ways to achieve this? If I where to write these vectors into a text file, being lazy, I would choose to write them hexadecimally. That is quite easy by looping over the vector in steps of four (after making the length dividable by four) and spewing out the nibbles. If you really want to write out in integer format, you could convert the binary string into BDC (binary coded decimal) and then print the nibbles, which are now the decimal digits. For the binary to BCD conversion, look at the double dabble algorithm: https://en.wikipedia.org/wiki/Double_dabble -- Paul Uiterlinden www.aimvalley.nl From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!news.osn.de!diablo2.news.osn.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 20 Mar 2014 16:25:07 -0500 Date: Thu, 20 Mar 2014 21:25:07 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Integers which are more than 32 bit References: <1e8be343-3f93-4eb2-b932-0d6de636a187@googlegroups.com> In-Reply-To: <1e8be343-3f93-4eb2-b932-0d6de636a187@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 22 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wMwgWdvmq7KEXksZrbGjEHxoyjurF6MaVLWB/lbofDVWG2xKuRokgUu+dKbiLL5ZaNsIFnVtGSmgoLu!k5f4frBe4BqUAehNU8wwldmgKH7kDXktf6AFCwdLSbJEyz5pIwalXm3IX/nC4oOd5W95BEW1wvKa!NUXvr/8dufClMr7CZ8sOTKeaWqg= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1776 Xref: news.eternal-september.org comp.lang.vhdl:7377 On 19/03/14 08:49, bipper wrote: > Hello everyone.. > > I have a top module which has an output in std_logic_vector format of 81 bits. In the test bench code I want to write this output vector > (of size 81 bits) into a text file in integer format. But due to the 32 bit size limit of integers its not working. Any round ways to achieve this? > > Thanks.. > You could write in hex using hwrite (from std_logic_textio). Then surround with the appropriate integer base specifier, e.g. write(L, string'("16#")); hwrite(s, L); write(L, string'("#")); writeline(F, L); regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.66.65.109 with SMTP id w13mr19472428pas.21.1395398389152; Fri, 21 Mar 2014 03:39:49 -0700 (PDT) X-Received: by 10.140.107.138 with SMTP id h10mr942026qgf.2.1395398389097; Fri, 21 Mar 2014 03:39:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no11160908igb.0!news-out.google.com!du2ni10175qab.0!nntp.google.com!hw13no6885092qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Mar 2014 03:39:48 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: precompilation 'Vhdl' syntax From: olivier90dir@gmail.com Injection-Date: Fri, 21 Mar 2014 10:39:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7378 Hi all, I vould like to find a good syntaxe for this action : PeekDat <= X"0000000" & "000" & Data.InitDone when PpAdd = X"05" else Timer when PpAdd = X"08" else MiscReg1 when PpAdd = X"26" else MiscReg2 when PpAdd = X"27" else CsteVersion when PpAdd = X"10" else for I in 1 to NB_MSGRX loop CntRxA.CntComOk(I) when PpAdd = (X"10" + I) else CntRxA.CntComKo(I) when PpAdd = (X"1A" + I) else CntRxB.CntComOk(I) when PpAdd = (X"4A" + I) else CntRxB.CntComKo(I) when PpAdd = (X"50" + I) else end loop; else X"00000000"; I don't know if it's possible to add for I .. generte inside this code. Maybye there are an others syntax Thank you for your help Olivier . From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx07.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: precompilation 'Vhdl' syntax Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 54 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1395408539 62.49.20.82 (Fri, 21 Mar 2014 13:28:59 UTC) NNTP-Posting-Date: Fri, 21 Mar 2014 13:28:59 UTC Date: Fri, 21 Mar 2014 13:28:59 GMT X-Received-Body-CRC: 1521264246 X-Received-Bytes: 2735 Xref: news.eternal-september.org comp.lang.vhdl:7379 On Fri, 21 Mar 2014 03:39:48 -0700, olivier90dir wrote: > Hi all, > > I vould like to find a good syntaxe for this action : > > PeekDat <= X"0000000" & "000" & Data.InitDone when PpAdd = X"05" else > Timer when PpAdd = X"08" else MiscReg1 when PpAdd = > X"26" else MiscReg2 when PpAdd = X"27" else CsteVersion when > PpAdd = X"10" else > for I in 1 to NB_MSGRX loop > CntRxA.CntComOk(I) when PpAdd = (X"10" + I) else > CntRxA.CntComKo(I) when PpAdd = (X"1A" + I) else > CntRxB.CntComOk(I) when PpAdd = (X"4A" + I) else > CntRxB.CntComKo(I) when PpAdd = (X"50" + I) else end loop; > else X"00000000"; > > I don't know if it's possible to add for I .. generte inside this code. > Maybye there are an others syntax No loop necessary. PeekDat <= X"0000000" & "000" & Data.InitDone when PpAdd = X"05" else Timer when PpAdd = X"08" else ... CntRxA.CntComOk(PpAdd - X"10") when PpAdd > X"10" and PpAdd <= X"10" + NB_MSGRX else CntRxA.CntComKo(PpAdd - X"1A") when PpAdd > X"1A" and PpAdd <= X"1A" + NB_MSGRX else CntRxB.CntComOk(PpAdd - X"4A") when PpAdd > X"4A" and PpAdd <= X"4A" + NB_MSGRX else CntRxB.CntComKo(PpAdd - X"50") when PpAdd > X"50" and PpAdd <= X"50" + NB_MSGRX else X"00000000"; Simplify using a function: function AddrMatch(Addr : whatever; Base : whatever) return boolean is begin return Addr > Base and Addr <= Base + NB_MSGRX; end AddrMatch; PeekDat <= ... CntRxA.CntComOk(PpAdd - X"10") when AddrMatch(PpAdd, X"10") else... And use named constants... constant RxABase : whatever := X"10"; PeekDat <= ... CntRxA.CntComOk(RxABase) when AddrMatch(RxABase) else... - Brian From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.236.144.102 with SMTP id m66mr18516789yhj.50.1395409694434; Fri, 21 Mar 2014 06:48:14 -0700 (PDT) X-Received: by 10.182.176.99 with SMTP id ch3mr3408obc.38.1395409694268; Fri, 21 Mar 2014 06:48:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w5no6966923qac.0!news-out.google.com!dd7ni123igb.0!nntp.google.com!ur14no11250346igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Mar 2014 06:48:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95f6ee09-2251-4d64-946b-54483a8d7b19@googlegroups.com> Subject: Re: precompilation 'Vhdl' syntax From: Olivier Dir Injection-Date: Fri, 21 Mar 2014 13:48:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3783 X-Received-Body-CRC: 2550540758 Xref: news.eternal-september.org comp.lang.vhdl:7380 Le vendredi 21 mars 2014 14:28:59 UTC+1, Brian Drummond a =E9crit=A0: > On Fri, 21 Mar 2014 03:39:48 -0700, olivier90dir wrote: >=20 >=20 >=20 > > Hi all, >=20 > >=20 >=20 > > I vould like to find a good syntaxe for this action : >=20 > >=20 >=20 > > PeekDat <=3D X"0000000" & "000" & Data.InitDone when PpAdd =3D X"05" = else >=20 > > Timer when PpAdd =3D X"08" else MiscReg1 when PpAdd =3D >=20 > > X"26" else MiscReg2 when PpAdd =3D X"27" else CsteVersion =20 >=20 > when >=20 > > PpAdd =3D X"10" else >=20 > > for I in 1 to NB_MSGRX loop >=20 > > CntRxA.CntComOk(I) when PpAdd =3D (X"10" + I) else >=20 > > CntRxA.CntComKo(I) when PpAdd =3D (X"1A" + I) else >=20 > > CntRxB.CntComOk(I) when PpAdd =3D (X"4A" + I) else >=20 > > CntRxB.CntComKo(I) when PpAdd =3D (X"50" + I) else end loop; >=20 > > else X"00000000"; >=20 > >=20 >=20 > > I don't know if it's possible to add for I .. generte inside this code. >=20 > > Maybye there are an others syntax >=20 >=20 >=20 > No loop necessary. >=20 >=20 >=20 > PeekDat <=3D X"0000000" & "000" & Data.InitDone when PpAdd =3D X"05" el= se >=20 > Timer when PpAdd =3D X"08" else >=20 > ... >=20 > CntRxA.CntComOk(PpAdd - X"10") when PpAdd > X"10"=20 >=20 > and PpAdd <=3D X"10" + NB_MSGRX else >=20 > CntRxA.CntComKo(PpAdd - X"1A") when PpAdd > X"1A"=20 >=20 > and PpAdd <=3D X"1A" + NB_MSGRX else >=20 > CntRxB.CntComOk(PpAdd - X"4A") when PpAdd > X"4A"=20 >=20 > and PpAdd <=3D X"4A" + NB_MSGRX else >=20 > CntRxB.CntComKo(PpAdd - X"50") when PpAdd > X"50"=20 >=20 > and PpAdd <=3D X"50" + NB_MSGRX else >=20 > X"00000000"; >=20 >=20 >=20 > Simplify using a function: >=20 >=20 >=20 > function AddrMatch(Addr : whatever; Base : whatever) return boolean i= s >=20 > begin >=20 > return Addr > Base and Addr <=3D Base + NB_MSGRX; >=20 > end AddrMatch; >=20 >=20 >=20 > PeekDat <=3D ... >=20 > CntRxA.CntComOk(PpAdd - X"10") when AddrMatch(PpAdd, X"10") else... >=20 >=20 >=20 > And use named constants... >=20 > =20 >=20 > constant RxABase : whatever :=3D X"10"; >=20 >=20 >=20 > PeekDat <=3D ... >=20 > CntRxA.CntComOk(RxABase) when AddrMatch(RxABase) else... >=20 >=20 >=20 > - Brian Thank you for your help !=20 Good solution !=20 I like your syntax. .=20 From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 24 Mar 2014 09:02:23 GMT Lines: 54 Message-ID: References: X-Trace: individual.net IRFUa4gXDWSOLizgARvUkQKLW2HU5qJ2LR01BQsmO56v5ne7Fw X-Orig-Path: not-for-mail Cancel-Lock: sha1:aFSAlgSbMz1Vi+IXyLjQ80/fWPE= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7381 Hi Glen, sorry for the delayed reply...been quite busy lately. In comp.lang.vhdl glen herrmannsfeldt wrote: [] >> I have a microcontroller with an FPU which is delivered as an IP (I mean >> the FPU). In order to run at a decent frequency, some of the operations >> are allowed to complete in within a certain amount of cycles, but the >> main problem is that we do not know how many. [] > Though more usual, the logic should have a signal indicating when > the result is valid. I have digged a little in the code and found a signal called /ready/ and thought I solved my issues, but then wait a minute, how can you implement a signal ready that takes into account a combinatorial path? And even if, I need to inform my synthesis tool about those paths being either multicycle paths or false paths, otherwise it'll try to make them fit in a single clock cycle. [] > The FPUs that I know of should be pipelined. (Is there a clock input?) > You shouldn't have to do the pipelining, but you do need to know the > number of clock cycles (and clock rate) for each operation. For a pipelined FPU the signal /ready/ makes much more sense (at least that's the only sense I see), but being not the case here I'll have to find a different way to verify the design. > If the design is encrypted, such that you can't look at it, they > need to give you enough information to be able to use it. I might have found a different approach. Being the FPU part of an embedded microprocessor, I may take the advantage of having the possibility to run a program on it and perform the verification with it. My testbench would not generate any particular signal, just the ones enough for the embedded processor to run, but the program loaded into it will perform the FPU operations and check they are indeed correct. If not I'll need to incrementally add a clock cycle delay before fetching the result into the output register. This approach might be very time consuming, but I see two main advantages: 1. it's totally agnostic w.r.t. the implementation. I do not need to know the details and I can run it for any technology, without the need to update my multicycle paths (I still need to keep the false path in place though). 2. it's the simulator that works, not me. Considering how much I'm paid per hour, I think it is much less expensive if a stupid machine does the job instead of me. I have not yet run a full-fledged program within modelsim, but I managed to run a simple 'hello world' program with no time. Al From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Date: 24 Mar 2014 12:55:12 GMT Lines: 35 Message-ID: X-Trace: individual.net byJyZ+4wVq39HmWDowSmuQqHlbql9NUzJsdPp2HrLL/dKh6mfv X-Orig-Path: not-for-mail Cancel-Lock: sha1:EuilM6b5UA5T9UmbyXoXdD8PLfI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7382 Hi everyone, it seems the above warning is filed when some of my signals/variables are not initialized and therefore some metavalue is either propagated or, as in this case, forced to some value. These warnings happens only at time 0 and do not bother me too much in general, but I hate discarding these long list of warnings everytime I run a sim. Any option to force vsim to *not* report warnings is not acceptable since I want to be able to see other potential problems. Any idea on how to get rid of those? AFAIK assigning default signal/variable values at declaration is not good habit since it may lead to a mismatch between pre-synth and post-synth behavior. BTW I also receive the same type of warning but filed from std_logic_arith: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es) the funny thing is that I'm not using std_logic_arith in my design (I do have std_logic_unsigned though[1])! Does this make any sense? Any comment is appreciated. Al [1] and yes, I know I shouldn't be using std_logic_unsigned since is not standard but the code is verified and I do not want to break something that has been delivered to us only because of the library. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.kamp.net!newsfeed.kamp.net!news.unit0.net!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx07.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140324-0, 24/03/2014), Outbound message X-Antivirus-Status: Clean Lines: 47 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1395670435 86.29.12.221 (Mon, 24 Mar 2014 14:13:55 UTC) NNTP-Posting-Date: Mon, 24 Mar 2014 14:13:55 UTC Organization: virginmedia.com Date: Mon, 24 Mar 2014 14:13:54 +0000 X-Received-Body-CRC: 730289572 X-Received-Bytes: 2544 Xref: news.eternal-september.org comp.lang.vhdl:7383 On 24/03/2014 12:55, alb wrote: > Hi everyone, > > it seems the above warning is filed when some of my signals/variables > are not initialized and therefore some metavalue is either propagated > or, as in this case, forced to some value. > > These warnings happens only at time 0 and do not bother me too much in > general, but I hate discarding these long list of warnings everytime I > run a sim. Any option to force vsim to *not* report warnings is not > acceptable since I want to be able to see other potential problems. > > Any idea on how to get rid of those? This is what I use in the beginning of my .do files, set StdArithNoWarnings 1 run 0 ns; set StdArithNoWarnings 0 Regards, Hans. www.ht-lab.com AFAIK assigning default > signal/variable values at declaration is not good habit since it may > lead to a mismatch between pre-synth and post-synth behavior. > > BTW I also receive the same type of warning but filed from > std_logic_arith: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an > arithmetic operand, the result will be 'X'(es) > > the funny thing is that I'm not using std_logic_arith in my design (I do > have std_logic_unsigned though[1])! Does this make any sense? > > Any comment is appreciated. > > Al > > [1] and yes, I know I shouldn't be using std_logic_unsigned since is not > standard but the code is verified and I do not want to break something > that has been delivered to us only because of the library. > From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Date: 24 Mar 2014 14:35:08 GMT Lines: 32 Message-ID: References: X-Trace: individual.net 9TbqxAMpmq1uXqVJxV5n8A+wqj0gNaYWaJd5oQBclNV6ql/QcX X-Orig-Path: not-for-mail Cancel-Lock: sha1:2Lk3Sja9F4Kg+QaMQToHInbDjyQ= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7384 Hi Hans, HT-Lab wrote: [] >> These warnings happens only at time 0 and do not bother me too much in >> general, but I hate discarding these long list of warnings everytime I >> run a sim. Any option to force vsim to *not* report warnings is not >> acceptable since I want to be able to see other potential problems. >> >> Any idea on how to get rid of those? > > This is what I use in the beginning of my .do files, > > set StdArithNoWarnings 1 > run 0 ns; > set StdArithNoWarnings 0 > Thanks a lot! This works indeed and I suppose I can do the very same trick for the numeric_std package (NumericStdNoWarnings 1/0). [] >> BTW I also receive the same type of warning but filed from >> std_logic_arith: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an >> arithmetic operand, the result will be 'X'(es) >> >> the funny thing is that I'm not using std_logic_arith in my design (I do >> have std_logic_unsigned though[1])! Does this make any sense? any idea instead about the above mentioned unexpected behavior? Al From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx34.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140324-0, 24/03/2014), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: <4tYXu.5$3b7.1@fx34.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1395676096 86.29.12.221 (Mon, 24 Mar 2014 15:48:16 UTC) NNTP-Posting-Date: Mon, 24 Mar 2014 15:48:16 UTC Organization: virginmedia.com Date: Mon, 24 Mar 2014 15:48:15 +0000 X-Received-Body-CRC: 3425653661 X-Received-Bytes: 1812 Xref: news.eternal-september.org comp.lang.vhdl:7385 On 24/03/2014 14:35, alb wrote: > Hi Hans, .. > > [] >>> BTW I also receive the same type of warning but filed from >>> std_logic_arith: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an >>> arithmetic operand, the result will be 'X'(es) >>> >>> the funny thing is that I'm not using std_logic_arith in my design (I do >>> have std_logic_unsigned though[1])! Does this make any sense? > > any idea instead about the above mentioned unexpected behavior? Hi Al, Looks like std_logic_arith is being references in package std_logic_unsigned, library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package STD_LOGIC_UNSIGNED is .... end STD_LOGIC_UNSIGNED; Regards, Hans www.ht-lab.com > > Al > From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 25 Mar 2014 11:21:10 GMT Lines: 88 Message-ID: <533166a5$0$11126$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 3640551a.news.astraweb.com X-Trace: DXC=@Ed^0= Hi everyone, > > it seems the above warning is filed when some of my signals/variables > are not initialized and therefore some metavalue is either propagated > or, as in this case, forced to some value. > > These warnings happens only at time 0 and do not bother me too much in > general, but I hate discarding these long list of warnings everytime I > run a sim. Any option to force vsim to *not* report warnings is not > acceptable since I want to be able to see other potential problems. > > Any idea on how to get rid of those? AFAIK assigning default > signal/variable values at declaration is not good habit since it may > lead to a mismatch between pre-synth and post-synth behavior. > > BTW I also receive the same type of warning but filed from > std_logic_arith: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an > arithmetic operand, the result will be 'X'(es) > > the funny thing is that I'm not using std_logic_arith in my design (I do > have std_logic_unsigned though[1])! Does this make any sense? > > Any comment is appreciated. > > Al > > [1] and yes, I know I shouldn't be using std_logic_unsigned since is not > standard but the code is verified and I do not want to break something > that has been delivered to us only because of the library. Consider the following: signal sig1 : std_logic := '1'; signal sig2 : std_logic; ... statement1 : sig2 <= sig1; Note that a signal declaration without an initialiser is equivalent to a declaration with an initialiser of the leftmost value of the type, in this case 'U'. At the start of simulation, sig1 has the value '1', and sig2 has the value 'U'. The implicit process associated with the assignment in statement1 then runs, and 1 delta cycle later, (the driver of) sig2 gets the value '1'. So, sig2 starts with the value 'U', then 1 delta later (but still at time 0 ns) it gets the value '1'. If you had a process which had sig2 in its sensitivity list, it would run once at the start of simultion, when sig2 was 'U', then once more when sig2 has the value '1'. My guess is that in your code you have something like this: signal u1 : unsigned(1 downto 0); -- no initialiser signal u2 : unsigned(1 downto 0) := (others => '0'); signal u3 : unsigned(1 downto 0); ... statement2 : u1 <= u2; statement3 : u3 <= u1 + 1; Initial: u1 is "UU', u2 is "00", u2 is "UU" Then the statement3 process runs, and the warning about metavalues is generated because u1 is "UU". U3 gets assigned the value "XX". The next delta u1 is "00". The statement3 process runs again. This time, no warning is generated and u3 gets assigned the value "01". Now consider what would happen if you'd given u1 an initialiser. You should be able to join the dots from there. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Date: 25 Mar 2014 15:46:41 GMT Lines: 76 Message-ID: References: <533166a5$0$11126$c3e8da3@news.astraweb.com> X-Trace: individual.net ieZtezr9Ew4yRfr0E/IsygpZ8C84fP3wr8wdaSLFbYO8gW4zWY X-Orig-Path: not-for-mail Cancel-Lock: sha1:7fs7s+Ao+idOfQk89B2QBQwvNiM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7387 Hi Allan, Allan Herriman wrote: >> it seems the above warning is filed when some of my signals/variables >> are not initialized and therefore some metavalue is either propagated >> or, as in this case, forced to some value. [...] > > Consider the following: > > signal sig1 : std_logic := '1'; > signal sig2 : std_logic; > > ... > > statement1 : sig2 <= sig1; > > > Note that a signal declaration without an initialiser is equivalent to a > declaration with an initialiser of the leftmost value of the type, in > this case 'U'. > > At the start of simulation, sig1 has the value '1', and sig2 has the > value 'U'. > The implicit process associated with the assignment in statement1 then > runs, and 1 delta cycle later, (the driver of) sig2 gets the value '1'. > > So, sig2 starts with the value 'U', then 1 delta later (but still at time > 0 ns) it gets the value '1'. > > If you had a process which had sig2 in its sensitivity list, it would run > once at the start of simultion, when sig2 was 'U', then once more when > sig2 has the value '1'. Thanks for the explanation, it helped clarifying some doubts I had on the beginning of the whole simulation process. IMHO though, initialization might be rather dangerous since you may rely on the initial values for proper operation. Eventually the hardware will have its own initial values (AFAIK synthesis does ignore initial values) and your logic go completely nuts because of wrong intial assumptions. I do prefer to verify that my 'U' are correctly assigned by some controlled flow before the signal is used. > My guess is that in your code you have something like this: > > signal u1 : unsigned(1 downto 0); -- no initialiser > > signal u2 : unsigned(1 downto 0) := (others => '0'); > > signal u3 : unsigned(1 downto 0); > > ... > > statement2 : u1 <= u2; > > statement3 : u3 <= u1 + 1; > > Initial: u1 is "UU', u2 is "00", u2 is "UU" I have indeed several initialized declarations as well as uninitialized ones, I did not bother to check the sequence of calling though. In the end the OP was about making the initial warnings 'silent' because they are /expected/. I should have added that my design does work as is and I'm not going to break it because of this reason ;-) [] > > Now consider what would happen if you'd given u1 an initialiser. > > You should be able to join the dots from there. Are you inferring that I should initialize every signal/variable during declaration? I guess I have missed your point. Al From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.182.251.230 with SMTP id zn6mr15424276obc.14.1395771806355; Tue, 25 Mar 2014 11:23:26 -0700 (PDT) X-Received: by 10.50.2.100 with SMTP id 4mr562101igt.8.1395771806224; Tue, 25 Mar 2014 11:23:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l13no11209294iga.0!news-out.google.com!gi6ni430igc.0!nntp.google.com!ur14no13808001igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Mar 2014 11:23:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.35 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41f942a6-89d8-410a-8966-359eccdd53be@googlegroups.com> Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 From: Andy Injection-Date: Tue, 25 Mar 2014 18:23:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1667 X-Received-Body-CRC: 3662388379 Xref: news.eternal-september.org comp.lang.vhdl:7388 The warning indicates that you are attempting to interpret the numerical representation of a variable/signal when such interpretation is not valid. I usually try to avoid the warning by managing when the function is called. I try to call it from a clocked process (after reset), perhaps when a flag or state machine indicates the data (e.g. from an external interface) should be valid. Calling the function in an concurrent assignment is just begging for the warning. This isn't always practical, but drastically reduces the number of occurrences. Andy From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Newsgroups: comp.lang.vhdl References: <533166a5$0$11126$c3e8da3@ news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 Mar 2014 13:31:26 GMT Lines: 88 Message-ID: <5332d6ad$0$6574$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: e344d562.news.astraweb.com X-Trace: DXC=]2DNa@H6WAPJRMXARX Hi Allan, > Allan Herriman wrote: >>> it seems the above warning is filed when some of my signals/variables >>> are not initialized and therefore some metavalue is either propagated >>> or, as in this case, forced to some value. > [...] >> >> Consider the following: >> >> signal sig1 : std_logic := '1'; >> signal sig2 : std_logic; >> >> ... >> >> statement1 : sig2 <= sig1; >> >> >> Note that a signal declaration without an initialiser is equivalent to >> a declaration with an initialiser of the leftmost value of the type, in >> this case 'U'. >> >> At the start of simulation, sig1 has the value '1', and sig2 has the >> value 'U'. >> The implicit process associated with the assignment in statement1 then >> runs, and 1 delta cycle later, (the driver of) sig2 gets the value '1'. >> >> So, sig2 starts with the value 'U', then 1 delta later (but still at >> time 0 ns) it gets the value '1'. >> >> If you had a process which had sig2 in its sensitivity list, it would >> run once at the start of simultion, when sig2 was 'U', then once more >> when sig2 has the value '1'. > > Thanks for the explanation, it helped clarifying some doubts I had on > the beginning of the whole simulation process. > > IMHO though, initialization might be rather dangerous since you may rely > on the initial values for proper operation. Eventually the hardware will > have its own initial values (AFAIK synthesis does ignore initial values) > and your logic go completely nuts because of wrong intial assumptions. > > I do prefer to verify that my 'U' are correctly assigned by some > controlled flow before the signal is used. > >> My guess is that in your code you have something like this: >> >> signal u1 : unsigned(1 downto 0); -- no initialiser >> >> signal u2 : unsigned(1 downto 0) := (others => '0'); >> >> signal u3 : unsigned(1 downto 0); >> >> ... >> >> statement2 : u1 <= u2; >> >> statement3 : u3 <= u1 + 1; >> >> Initial: u1 is "UU', u2 is "00", u2 is "UU" > > I have indeed several initialized declarations as well as uninitialized > ones, I did not bother to check the sequence of calling though. In the > end the OP was about making the initial warnings 'silent' because they > are /expected/. I should have added that my design does work as is and > I'm not going to break it because of this reason ;-) > > [] >> >> Now consider what would happen if you'd given u1 an initialiser. >> >> You should be able to join the dots from there. > > Are you inferring that I should initialize every signal/variable during > declaration? I guess I have missed your point. I wasn't inferring that you should do that, merely trying to point out one possible way you can deal with it. The metavalues may indicate something useful, and you would lose this by initialising everything. I usually use Andy's approach in actual code, BTW. Sometimes I will use initialisers to get rid of warnings in code that's already been verified. Han's approach is probably the best though, particularly if using scripts to run the simulation. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 Date: 26 Mar 2014 16:22:53 GMT Lines: 27 Message-ID: References: <41f942a6-89d8-410a-8966-359eccdd53be@googlegroups.com> X-Trace: individual.net tJT422DdACkLW8yDBjeXYA1CORZckUr5LQY+Pqdnf58IM7JzHt X-Orig-Path: not-for-mail Cancel-Lock: sha1:KhyZLHBjsnRWcKulBRU0xoOzis8= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7390 Hi Andy, Andy wrote: [] > I usually try to avoid the warning by managing when the function is > called. I try to call it from a clocked process (after reset), perhaps > when a flag or state machine indicates the data (e.g. from an external > interface) should be valid. There are still cases where is not really possible to avoid metavalues until the wires are driven (I can thing of a non pipelined ALU). In these cases the data path will propagate its metavalues as needed. If these wires are driven internally through registers they will have a metavalues at time 0 since their process will trigger first when the reset signal is still 'U', am I wrong? I should do a simple test to verify my statement... :-/ > Calling the function in an concurrent assignment is just begging for > the warning. As usually happens, you inherit this type of code at a stage where changing these aspects will simply be a too big effort to be worth it. Hans's solution for the time being provides a sufficiently good patch to this issue. Al From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: [cross-post][long] svn workflow for fpga development Date: 27 Mar 2014 13:44:34 GMT Lines: 63 Message-ID: X-Trace: individual.net l5qRZ/NJM4l1t0ytAEpBEgFL4mqfox49GDmWa43mG/VAVIoLjU X-Orig-Path: not-for-mail Cancel-Lock: sha1:ArKLknj0Y31WsyoDGN2N1aDPm7k= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7391 comp.arch.fpga:20311 Hi everyone, this is not really a question, but more some food for thoughts on how to optimize an fpga development flow leveraging the benefit of a vcs. I've been using svn since sometime now and I cannot imagine a world without a vcs under your belt when dealing with complex systems in a collaborative environment. In the past I've always followed two simple rules: 1. never break the trunk 2. commit often The reasons behind these two rules are quite simple and I stick to them because from them it derives a set of additional rules which allow you to respect the one above. The first rule is there because without it anyone new in the team cannot simply checkout a copy and rely on it. This implies that commits to the trunk are performed when a feature or a bugfix is completed and does not break compatibility with the rest of the system. Allowing a newcomer to easily get into the flow alleviates hours of training, but even experienced designers do need to rely on a stable version to perform their regression testing and/or add features to it. The second rule is needed because the very purpose of a vcs is to track changes as regularly as possible so that you (or somebody else) can roll back and forth and use what is most appropriate at any given time. Apparently the two rules are in contraddiction since the first advocates few commits (only the good ones) and the second lots of commits (even broken ones). To benefit from both of the two worlds 'branching' come to rescue. When branching the trunk we set up our working environment in a clean way and we can mess up with it as long as we want, until the feature/bugfix is complete. Only at that point we can merge it back into the trunk so that the trunk gets all the goodies we worked on. Working on a branch leaves (no pun intended) the trunk safe from exploration efforts and allows everyone to rely upon it. After all, an healthy trunk means an healthy tree. The pitfall here is that too often people branch and then never sync with the evolving trunk, so when it is time to merge it is a hell! Syncing regularly with the trunk allows to keep the branch on track without the risk to fight when it is time to close the branch and move on. I have deliberately left out of the flow the concept of tagging because that is not adding too much to this conversation and might be treated separately (maybe another thread ;-)). If you find this flow somehow lacking important features and/or missing completely essential points which are relevant to fpga development flow I'd appreciate if you could share your thoughts. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.66.150.106 with SMTP id uh10mr916454pab.13.1395934342538; Thu, 27 Mar 2014 08:32:22 -0700 (PDT) X-Received: by 10.140.96.229 with SMTP id k92mr59527qge.4.1395934342487; Thu, 27 Mar 2014 08:32:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no11816904iga.0!news-out.google.com!bw18ni25003qab.1!nntp.google.com!hw13no9193377qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Mar 2014 08:32:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <41f942a6-89d8-410a-8966-359eccdd53be@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <68f8f05f-1428-4ec6-9e22-742f8d6804dd@googlegroups.com> Subject: Re: Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 From: Andy Injection-Date: Thu, 27 Mar 2014 15:32:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7392 Unfortunately I know all too well of the problems associated with inherited= code. This is but the tip of the iceberg. When called from a clocked process, to_integer() will only execute when eit= her reset is active or a rising edge is detected on the clock. The former i= s unlikely since a reset assignment using a conversion of another (unknown = valued) signal is probably a design/code bug that would not synthesize anyw= ay. If your simulation starts the clock with the reset inactive or undefined, w= ell, you'll still get the warnings... I would script the simulation to disa= ble warnings until reset is first active. I usually initialize the reset si= gnal to active in the testbench, to make sure it is active before edges occ= ur on the clock. Andy From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: [cross-post][long] svn workflow for fpga development Date: Thu, 27 Mar 2014 18:07:42 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 39 Message-ID: References: Injection-Date: Thu, 27 Mar 2014 18:07:42 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="8696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18vjIPYXZhhWAWtCGulKPi6" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:baao3Gfh7hPZICBJrfcI0Oh0QQk= Xref: news.eternal-september.org comp.lang.vhdl:7393 comp.arch.fpga:20312 In article , alb wrote: > >this is not really a question, but more some food for thoughts on how to >optimize an fpga development flow leveraging the benefit of a vcs. > >I've been using svn since sometime now and I cannot imagine a world >without a vcs under your belt when dealing with complex systems in a >collaborative environment. > >In the past I've always followed two simple rules: > 1. never break the trunk > 2. commit often I'll add my 2 cents. Rule 1 is not as important in my experience. Having a regular regression (nightly, weekly, whatever), that runs on a clean checkout of the trunk is more important. Then you can easily identify what broke the trunk. The version control tools allow's everyone to continue working (by unmerging the offending commit). Rules 2 is spot on. Check in early, check in often. Working on branches is great, but as you indicated, merging sucks. The tools (SVN at least) allow easy branching, but are shitty when it comes to merges. If you've got a version control tool that allows for easy merging back to the trunk, then you've got the best of all. Atria (clearcase) really did this well, but was hell for admin, and performance sucked. I've no experience with the more modern distributed vcs (git, mercurial). Someone else hopefully will chime in here on how well they handle branches and merges... --Mark From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: [cross-post][long] svn workflow for fpga development Date: 28 Mar 2014 13:24:42 GMT Lines: 66 Message-ID: References: X-Trace: individual.net yAMCgjPZOu/Gnj6Qma8Krwxbcd7whgByL/jSv9do2OtGRd/ydo X-Orig-Path: not-for-mail Cancel-Lock: sha1:2NNqhhXMnH3nQ14tM3J+TtZI7T0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7394 comp.arch.fpga:20317 Hi Mark, In comp.arch.fpga Mark Curry wrote: [] >>In the past I've always followed two simple rules: >> 1. never break the trunk >> 2. commit often > > I'll add my 2 cents. Rule 1 is not as important in my experience. > Having a regular regression (nightly, weekly, whatever), that runs > on a clean checkout of the trunk is more important. Then you > can easily identify what broke the trunk. The version control > tools allow's everyone to continue working (by unmerging the > offending commit). and this is where I wanted to go in the first place, but there's no regression running regularly. Indeed the whole verification process is a bit of a mess, but that's another story! [1] In the event you *do not* have a regular regression you may now understand why rule 1 is in place. Without it, any commit may break the trunk silently until the next guy performs a sim and nothing works anymore. Without a regression in place every commit can break the trunk and it will take time before the issue comes out. Being able to branch and commit without fearing to break anything allows much more freedom to the developer to trace her/his changes. > Rules 2 is spot on. Check in early, check in often. this one is vital. You want to keep track of what you are doing, but you need to preserve the team sanity as well, so it would be too risky to allow everyone to commit early and often on a trunk. > Working on branches is great, but as you indicated, merging > sucks. The tools (SVN at least) allow easy branching, > but are shitty when it comes to merges. This happens because people branch and do not sync with the trunk regularly. I'm quite interested in understanding the technical reasons behind the merging issue in svn, sure is that without this possibility there's no way out of using only the trunk. > If you've got a version control tool that allows for > easy merging back to the trunk, then you've got the best > of all. The reason for this post is because I'm trying to raise arguments to convince people in the team to use svn and to profit from it. Proposing yet another tool to somebody who doesn't even see why we need a vcs is pointless and will only undermine the whole effort. > I've no experience with the more modern distributed vcs (git, mercurial). > Someone else hopefully will chime in here on how well they > handle branches and merges... I'm tempted about moving on to git, but I guess that it would be already a big success if the team accepts a fair usage of svn. On my own, I'll probably experiment with git-svn which seems to be a valuable tool to profit of git performances in an svn environment. Al [1] I'll soon post something about regression testing...and yes, that's a menace! From newsfish@newsfish Tue Dec 29 16:43:21 2015 X-Received: by 10.224.113.202 with SMTP id b10mr3214936qaq.3.1396015516462; Fri, 28 Mar 2014 07:05:16 -0700 (PDT) X-Received: by 10.182.88.133 with SMTP id bg5mr80275obb.24.1396015516344; Fri, 28 Mar 2014 07:05:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.88.MISMATCH!hw13no9484392qab.1!news-out.google.com!gi6ni488igc.0!nntp.google.com!l13no12157021iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Mar 2014 07:05:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [cross-post][long] svn workflow for fpga development From: Chris Higgs Injection-Date: Fri, 28 Mar 2014 14:05:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7395 On Thursday, March 27, 2014 1:44:34 PM UTC, alb wrote: > If you find this flow somehow lacking important features and/or missing > completely essential points which are relevant to fpga development flow > I'd appreciate if you could share your thoughts. Why on earth would anybody still be using SVN? It's over a decade old, all of the issues you mention have been more than adequately solved by distributed version control systems (for example git and mercurial). It's perfectly possible to migrate an SVN repository into git and maintain the history. If your engineers aren't willing to learn a new tool or your company structure makes it impossible to effect such changes then you have bigger problems than just your choice of version control software! If you haven't already seen it you should watch Linus's tech-talk on Git[1] which gives a good explanation of why choosing a non-distributed version control system is nonsensical. EDA is conservative but this was almost 7 years ago, the approach has been well proven and widely adopted, there's no good reason for us not to move forward. Regarding regressions - you should really have a suite of quick-running tests that run every check-in, ideally that run in under a minute. I run block-level simulations using Jenkins that achieve 100% coverage in 10s of seconds. Quick feedback is essential and it's well worth investing effort in ensuring you have some tests that run quickly and tell you with at least some confidence that the system isn't completely broken. With freely available tools such as Jenkins, there's no excuse for not having tests running automatically, e-mail notifications going out to anybody who broke the build etc. In short, we should be adopting development practices that the software world has been using successfully for years. RTL development is really just software a niche form of software development, we're just incredibly slow to realise it and capitalise on their experience and tools. [1] https://www.youtube.com/watch?v=4XpnKHJAok8 From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: [cross-post][long] svn workflow for fpga development Date: Fri, 28 Mar 2014 15:18:48 +0100 Lines: 51 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net ckc4hKKhK9+XXIZu+LQgsgm9goNpb1ang1Ck09aBzU/iTKI4Ic Cancel-Lock: sha1:YqdxtKEvdAOn4pWhEAGN6hq/aQo= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:7396 comp.arch.fpga:20318 alb wrote: >> Working on branches is great, but as you indicated, merging >> sucks. The tools (SVN at least) allow easy branching, >> but are shitty when it comes to merges. > > This happens because people branch and do not sync with the trunk > regularly. I'm quite interested in understanding the technical reasons > behind the merging issue in svn, sure is that without this possibility > there's no way out of using only the trunk. In my experience merging in SVN works fine if every file is touched only by a single person. It only breaks in this situation: - Alice and Bob check out the latest trunk or create local branchges for themselves - they start making their changes - Bob is done and commits a change to file XYZ or merges his changed branch to the trunk. - Alice also works on her stuff, but also on file XYZ, but on the version that she originally checked out, not the one Bob has changed in the meantime. - Now Alice wants to merge her changes. Amongst others, her merge includes a changed version of file XYZ. But her version does not have the changes Bob made earlier. So now the SVN client sees that that file's revision in her branch that this new file is based on is older than the one in the trunk. Committing her file would probably mean reversing Bob's changes to XYZ, which could be intentional or a mistake. There's no way for the client to know for sure, so it just quits and complains and forces the user to manually decide which changes to apply. If this happens for a single file in a merge, the entire merge doesn't work, because half a merge would probably break everything. As long as every file is edited exclusively by one person, there should be no problem (at least I haven't had any). In past projects, this was mostly a problem with top-level files. Everyone is responsible for a module they work on exclusively, but if they add or change ports of that module, that has to be accounted for up through the hierarchy. So instead of changing the top-level-file, they should inform the person responsible for that file that the ports need to be changed. This is additional overhead but better than breaking merges completely; it never was a big problem for us, but I see it can be problematic in bigger projects with more people. I guess (don't know since I haven't looked into it) git and mercurial have some sort of mechanism to lock files or portions of files or track every detail you change, so during a merge the client can do step-by-step modifications of shared files, which maybe can resolve more uncertainties. Have fun, Sean From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx12.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: [cross-post][long] svn workflow for fpga development Newsgroups: comp.lang.vhdl,comp.arch.fpga References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 44 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1396098886 62.49.20.82 (Sat, 29 Mar 2014 13:14:46 UTC) NNTP-Posting-Date: Sat, 29 Mar 2014 13:14:46 UTC Date: Sat, 29 Mar 2014 13:14:46 GMT X-Received-Body-CRC: 2351139759 X-Received-Bytes: 2667 Xref: news.eternal-september.org comp.lang.vhdl:7397 comp.arch.fpga:20323 On Fri, 28 Mar 2014 13:24:42 +0000, alb wrote: > Hi Mark, > > In comp.arch.fpga Mark Curry wrote: > [] >>>In the past I've always followed two simple rules: >>> 1. never break the trunk 2. commit often >> >> I'll add my 2 cents. Rule 1 is not as important in my experience. >> Having a regular regression (nightly, weekly, whatever), that runs on a >> clean checkout of the trunk is more important. Then you can easily >> identify what broke the trunk. The version control tools allow's >> everyone to continue working (by unmerging the offending commit). > In the event you *do not* have a regular regression you may now > understand why rule 1 is in place. Without it, any commit may break the > trunk silently until the next guy performs a sim and nothing works > anymore. And this is the strength of distributed version control : rules 1 and 2 are not mutually incompatible. http://hginit.com/00.html for a rather (OK extremely!) biased account of the difference; any good links giving the reverse side of the story? (Mercurial, but Git is similar) You clone the trunk into a local repo, where you checkin broken code as often as you want. At last, when you are done and the new feature is working, you have a consistent set of changes you can push back to the trunk without breaking it. If someone else has pushed to the trunk, you end up with two heads in the trunk, which require merging. Which isn't too bad in Mercurial but occasionally involves manual intervention. The simplest way to deal with this, I find, is to *pull* the new head from the trunk, merge locally, re-test your change, then push. (Yes you can branch as well, and I do that for stable versions, i.e. releases, but cloning the repo is the most convenient way to branch). - Brian From newsfish@newsfish Tue Dec 29 16:43:21 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: [cross-post][long] svn workflow for fpga development Date: 30 Mar 2014 22:07:09 GMT Lines: 77 Message-ID: References: X-Trace: individual.net dsTCAzevclgcXGi8VZoxSQuVC3vzQTpLa7UIjN+RYAIlkAQEo5 X-Orig-Path: not-for-mail Cancel-Lock: sha1:IQt2xeQ8ULT+DHnFwU369/LsHHs= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:20329 comp.lang.vhdl:7398 Hi Tom, (I'm answering reposting to vhdl as well to keep the thread cross-posted) Tom Gardner wrote: [] >> In the past I've always followed two simple rules: >> 1. never break the trunk >> 2. commit often > > So, what do you put on the trunk and what's on the branches? The trunk has only merges from the branches [1]. When you start a project from scratch you certainly need to start from the trunk, but that situation lasts a very small amount of time (few days if not less) and as soon as possible you branch from it. Branches are - only - for two reasons [2]: 1. adding features 2. removing bugs/problems both of them start from the trunk and both of them should merge back in the trunk. > One strategy which works for some types of system and > some ways of team working is: > - to have the trunk for development Is the trunk always functioning? If this is the case it cannot be really for development since every commit should be done only when the whole changeset is working (tested). > - whenever you reach a milestone of some sort, > create a branch containing the milestone this is what I call 'tagging'. Yes it is a branch, but its purpose is to freeze the status of your development at some known state. These tags are essential when multiple repositories are pointing at each other for the purpose of reuse. You can point to version 1.2.3 and stick to it or follow its evolution to whatever version. > - whenever the regression tests have passed, > check in to the trunk (hopefully frequently) so the regression test are run from your local copy? or from the branches? I think I missed this part. > - if it is necessary to save when regression > tests have not been passed, checkin to a branch uhm...at this point you branched to fix something while the trunk is being developed. When do you decide that is time to merge back into the trunk? > > Thus > - the head of the trunk always contains the latest > working system. This contraddicts your earlier statement or I might have misunderstood what you mean by keeping the trunk for development. If no one pair of consecutive commits breaks the trunk than we are on the same page, but while I'm suggesting to branch and therefore commit even if you break something, you are suggesting that noone should commit to the trunk unless her/his piece is working (system wise). > - significant historical waypoints can be found on > a branch Yes, including the ones that broke your regression tests... [1] The only one exception is for modifications which are straight forward and do not require more than few minutes of work. [2] refactoring is more delicate since it requires a solid regression suite in place to be sure that functionality is not affected From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: [cross-post][long] svn workflow for fpga development Date: 30 Mar 2014 22:07:39 GMT Lines: 81 Message-ID: References: X-Trace: individual.net eATC4/187Uo9tO++siOAjgMqFu9zeTKnTQl2PVSuai/8P37YCO X-Orig-Path: not-for-mail Cancel-Lock: sha1:6w9CyOMdbazgScdhPH155zvlV00= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7399 comp.arch.fpga:20330 Hi Chris, Chris Higgs wrote: [] >> If you find this flow somehow lacking important features and/or missing >> completely essential points which are relevant to fpga development flow >> I'd appreciate if you could share your thoughts. > > Why on earth would anybody still be using SVN? It's over a decade old, > all of the issues you mention have been more than adequately solved by > distributed version control systems (for example git and mercurial). I think this graph does answer your question: http://www.ohloh.net/repositories/compare > It's > perfectly possible to migrate an SVN repository into git and maintain the > history. If your engineers aren't willing to learn a new tool or your > company structure makes it impossible to effect such changes then you have > bigger problems than just your choice of version control software! 'Living is easy with eyes closed' - John Lennon (Amen!) > If you haven't already seen it you should watch Linus's tech-talk on > Git[1] which gives a good explanation of why choosing a non-distributed > version control system is nonsensical. EDA is conservative but this was > almost 7 years ago, the approach has been well proven and widely adopted, > there's no good reason for us not to move forward. Behind conservative enterprises there are conservative managers by choice and/or by nature, but this is not the whole story! Some fields are more conservative than others (defense, aerospace, ...). A distributed version control while more attractive for its rich sets of features it may scare away whoever feels the lack of control behind it. The Cathedral vs. the Bazaar' is a nice essay by E. Raymond, but its advocacy for the bazaar style that brought the *nix community where it is nowadays does not necessarily apply in a much more controlled regime like you may have on a project for the Department of Defense. > Regarding regressions - you should really have a suite of quick-running > tests that run every check-in, ideally that run in under a minute. I run > block-level simulations using Jenkins that achieve 100% coverage in 10s > of seconds. Quick feedback is essential and it's well worth investing > effort in ensuring you have some tests that run quickly and tell you with > at least some confidence that the system isn't completely broken. With > freely available tools such as Jenkins, there's no excuse for not having > tests running automatically, e-mail notifications going out to anybody who > broke the build etc. I fully agree with you here, that would be my next item on my personal agenda...but revolutionary change requires time and patience ;-). The main problem I see currently is the lack of 'command line' mindset in the designers mindset. They are all too used to graphical interfaces and manual wave tracing (sigh!). I suspect it is an habit related to the complexity they used to handle, which does not fit well nowadays systems. Together with building a regression environment we should train people on a different verification model and workflow. Anyhow Continuous Integration is built around version control, so I need to get this fixed before moving on. > In short, we should be adopting development practices that the software > world has been using successfully for years. RTL development is really > just software a niche form of software development, we're just incredibly > slow to realise it and capitalise on their experience and tools. I agree here as well, but the software development world has an infrastructure around it that hardware designers unfortunately do not have. On my *nix box I can install nearly any type of software in a matter of seconds, look at the sources, discuss with the authors and benefit of a storm of developers who are constantly improving the quality of these product. They sell support and make a living out of it. In the hardware world instead we close everything, live behind patrolled fences and sustain licensing policies which are close to insanity, essentially limiting progress and fair competition. Al From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.67.30.197 with SMTP id kg5mr12541241pad.36.1396346670299; Tue, 01 Apr 2014 03:04:30 -0700 (PDT) X-Received: by 10.182.200.163 with SMTP id jt3mr560529obc.25.1396346670170; Tue, 01 Apr 2014 03:04:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ur14no372050igb.0!news-out.google.com!xg2ni0igc.0!nntp.google.com!l13no1138302iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 1 Apr 2014 03:04:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> Subject: How dofor using generate or loop for this process ? From: Olivier Dir Injection-Date: Tue, 01 Apr 2014 10:04:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7400 Hi all, for this code I would like write this code with loop or generate. I don't know if it's possible. pSelFifo : process(Clk, SRst) begin if SRst = '1' then SelFifo <= (others=>'0'); elsif Clk'event and Clk='1' then if DataAvlble(1) = '1' then SelFifo <= "000001" elsif DataAvlble(2) = '1' then SelFifo <= "000010" elsif DataAvlble(3) = '1' then SelFifo <= "000100" elsif DataAvlble(4) = '1' then SelFifo <= "001000" elsif DataAvlble(5) = '1' then SelFifo <= "010000" elsif DataAvlble(6) = '1' then SelFifo <= "100000" else SelFifo <= (others=>'0'); end if; end if; end process; thank for your help. Olive From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx22.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: How dofor using generate or loop for this process ? Newsgroups: comp.lang.vhdl References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 38 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1396351502 62.49.20.82 (Tue, 01 Apr 2014 11:25:02 UTC) NNTP-Posting-Date: Tue, 01 Apr 2014 11:25:02 UTC Date: Tue, 01 Apr 2014 11:25:02 GMT X-Received-Body-CRC: 1930554143 X-Received-Bytes: 1759 Xref: news.eternal-september.org comp.lang.vhdl:7401 On Tue, 01 Apr 2014 03:04:29 -0700, Olivier Dir wrote: > Hi all, > for this code I would like write this code with loop or generate. > I don't know if it's possible. > > > > pSelFifo : process(Clk, SRst) > begin > if SRst = '1' then > SelFifo <= (others=>'0'); > elsif Clk'event and Clk='1' then > if DataAvlble(1) = '1' then > SelFifo <= "000001" > elsif DataAvlble(2) = '1' then > SelFifo <= "000010" ... > thank for your help. > > Olive pSelFifo : process(Clk, SRst) begin if SRst = '1' then SelFifo <= (others=>'0'); elsif rising_edge(Clk) then SelFifo <= (others=>'0'); for i in DataAvlble'low to DataAvlble'high loop if DataAvlble(i) = '1' then SelFifo(i) <= '1'; exit; -- prevent multiple bit set, as in original end if; end loop; end if; end process; From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.50.62.106 with SMTP id x10mr3334710igr.2.1396420883189; Tue, 01 Apr 2014 23:41:23 -0700 (PDT) X-Received: by 10.182.60.228 with SMTP id k4mr3117obr.35.1396420882892; Tue, 01 Apr 2014 23:41:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1640801iga.0!news-out.google.com!gi6ni106igc.0!nntp.google.com!l13no1640796iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 1 Apr 2014 23:41:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <324f8c12-b7ff-41d9-adf2-c2d4f49182c5@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Olivier Dir Injection-Date: Wed, 02 Apr 2014 06:41:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7402 Le mardi 1 avril 2014 13:25:02 UTC+2, Brian Drummond a =E9crit=A0: > On Tue, 01 Apr 2014 03:04:29 -0700, Olivier Dir wrote: >=20 >=20 >=20 > > Hi all, >=20 > > for this code I would like write this code with loop or generate. >=20 > > I don't know if it's possible. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > pSelFifo : process(Clk, SRst) >=20 > > begin >=20 > > if SRst =3D '1' then >=20 > > SelFifo <=3D (others=3D>'0'); >=20 > > elsif Clk'event and Clk=3D'1' then >=20 > > if DataAvlble(1) =3D '1' then >=20 > > SelFifo <=3D "000001" >=20 > > elsif DataAvlble(2) =3D '1' then >=20 > > SelFifo <=3D "000010" >=20 > ... >=20 >=20 >=20 > > thank for your help. >=20 > >=20 >=20 > > Olive >=20 >=20 >=20 > pSelFifo : process(Clk, SRst) >=20 > begin >=20 > if SRst =3D '1' then >=20 > SelFifo <=3D (others=3D>'0'); >=20 > elsif rising_edge(Clk) then >=20 > SelFifo <=3D (others=3D>'0'); >=20 > for i in DataAvlble'low to DataAvlble'high loop >=20 > if DataAvlble(i) =3D '1' then >=20 > SelFifo(i) <=3D '1'; >=20 > exit; -- prevent multiple bit set, as in original >=20 > end if; >=20 > end loop; >=20 > end if; >=20 > end process; Thank you. From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Wed, 02 Apr 2014 11:57:12 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 2 Apr 2014 15:56:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="3139"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18H9jiZGLynspNz6l0NXb5M" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:vL3Mqwhy5ynoR7xFNJo2qit4+V8= Xref: news.eternal-september.org comp.lang.vhdl:7403 On 3/17/2014 11:44 AM, alb wrote: > Dear all, > > I have a microcontroller with an FPU which is delivered as an IP (I mean > the FPU). In order to run at a decent frequency, some of the operations > are allowed to complete in within a certain amount of cycles, but the > main problem is that we do not know how many. > > That said, if we run the synthesis tool without timing constraints on > those paths, we have a design that is much slower than can be. > Multicycle constraints are out of question because they are hard to > verify and maintain, so we decided to set false paths and perform > post-layout sims to extract those values to be used in the RTL in a > second iteration. > > There are several reasons why I do not particularly like this approach: > > 1. it relies on post-layout sims which are resource consuming > 2. if we change technology we will likely need to do the whole process > again > 3. we are obliged to perform incremental place&route since an optimized > implementation (maybe done automatically) may have an impact on our > delays. > > So far we have not come out with an alternative solution that is not > going to imply redesign (like pipelining, c-slowing, retiming, ...). > > Any ideas/suggestions? > > Al If I understand you correctly, you have a piece of combinatorial logic and you need to know how fast it will run in your design. This will then let your surrounding circuitry wait some number of clock cycles to read the result, that give you a longer delay than the delay though the logic. I think your starting premise that multi-cycle constraints are "out of the question" is where you have erred. Multi-cycle constraints are exactly what are required and if you don't understand how to use them you are not likely to get a good result. Post P&R simulation is not a good way to validate timing because it is so hard to cover every path through the logic. Static timing analysis is the right way to do this and you need to learn to use it properly. -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 07:05:40 GMT Lines: 62 Message-ID: References: X-Trace: individual.net 0a/rtJ5zboBDtPERxzWHKAadCLF2Pm1ZJn9uzP0+rJNZyW6fcJ X-Orig-Path: not-for-mail Cancel-Lock: sha1:gjM3aZbTDua2sLSUUZ93939sDzM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7404 Hi Rick, rickman wrote: [] >> I have a microcontroller with an FPU which is delivered as an IP (I mean >> the FPU). In order to run at a decent frequency, some of the operations >> are allowed to complete in within a certain amount of cycles, but the >> main problem is that we do not know how many. >> >> That said, if we run the synthesis tool without timing constraints on >> those paths, we have a design that is much slower than can be. >> Multicycle constraints are out of question because they are hard to >> verify and maintain, so we decided to set false paths and perform >> post-layout sims to extract those values to be used in the RTL in a >> second iteration. [] > > If I understand you correctly, you have a piece of combinatorial logic > and you need to know how fast it will run in your design. This will > then let your surrounding circuitry wait some number of clock cycles to > read the result, that give you a longer delay than the delay though the > logic. Precisely. > I think your starting premise that multi-cycle constraints are "out of > the question" is where you have erred. Multi-cycle constraints are > exactly what are required and if you don't understand how to use them > you are not likely to get a good result. There are two aspects here to consider: 1. multicycle constraints need not only a /from/ and /to/ parameter, they also need a /through/ parameter. When you have a logic depth of 111 gates you start to understand why a multicycle constraint cannot be a sustainable solution. 2. My experience in setting up multicycle constraints is nearly zero and starting off with such an approach on this type of project would be begging for troubles. > Post P&R simulation is not a good way to validate timing because it is > so hard to cover every path through the logic. Static timing analysis > is the right way to do this and you need to learn to use it properly. I've read several times on this group the skepticism behind static timing analysis when multicycle constraints are in place. I have to search back in the archives to really understand the technical motivations, but the bottom line is: a. is difficult to maintain them; if the logic path has been optimized the constraint does not work anymore b. is difficult to verify them; if the path *is not* multicycle you may wrongly relax the timing too much and never realize until another optimization takes place and your circuit does not work any more. If anyone sees a flaw in my points above I'd be glad to be corrected. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx11.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140402-5, 02/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 45 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396514969 86.29.12.221 (Thu, 03 Apr 2014 08:49:29 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 08:49:29 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 09:49:27 +0100 X-Received-Body-CRC: 1106746054 X-Received-Bytes: 2616 Xref: news.eternal-september.org comp.lang.vhdl:7405 On 03/04/2014 08:05, alb wrote: Hi Al, .. > I've read several times on this group the skepticism behind static timing analysis > when multicycle constraints are in place. I have to search back in the archives to > really understand the technical motivations, but the bottom line is: > > a. is difficult to maintain them; if the logic path has been optimized the > constraint does not work anymore I think you are confusing propagation (or false path) delay with multicycle path delay. A multicycle delay is a synchronous "number of clock cycle" based delay, it does not depend on the clock frequency. You use this delay if you know your circuit takes n clock cycles to propagate the result to the destination register. > b. is difficult to verify them; You can easily verify them using assertions, see end of the pdf below: https://www.synopsys.com/Community/Interoperability/Documents/devforum_pres/2005april/17_SystemVerilog_FishTail.pdf As I mentioned in another thread, learn PSL, it is a real eye opener for verification. if the path *is not* multicycle you may wrongly > relax the timing too much and never realize until another optimization takes place > and your circuit does not work any more. Not exactly, you will simply not get timing closure and your will probably end up using more resources then necessary. Regards, Hans. www ht-lab.com > > If anyone sees a flaw in my points above I'd be glad to be corrected. > > Al > From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 10:48:15 GMT Lines: 68 Message-ID: References: X-Trace: individual.net KeC53Blmp0Mbt2Xfp4f2+AuM0ofFpqbLhIYiQb6ls68OPo8KW8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:z2o/EZc6APH7mOB42jwxOmA7zq0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7406 Hi Hans, HT-Lab wrote: [removed text and added reference in square brackets] >> a. is difficult to maintain them [multicycle constraints]; if the >> logic path has been optimized the constraint does not work anymore > > I think you are confusing propagation (or false path) delay with > multicycle path delay. A multicycle delay is a synchronous "number of > clock cycle" based delay, it does not depend on the clock frequency. IMHO a multicycle path delay is a propagation delay specified as relative to the clock period. Hence it *does* depend on the clock frequency, while the propagation through your gates does not (it depends on the technology). If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one. A false path is a different story. You want to inform your synthesis tool that a certain path is never going to be used so do not bother optimizing it. > You > use this delay if you know your circuit takes n clock cycles to > propagate the result to the destination register. If I know when I will be reading the result on the destination register I may relax the time it will take to propagate the result, but on the contrary if I want to know when is the earliest moment to go and get the result, the multicycle path is of no use. >> b. is difficult to verify them; > > You can easily verify them using assertions, see end of the pdf below: > > https://www.synopsys.com/Community/Interoperability/Documents/devforum_pres/2005april/17_SystemVerilog_FishTail.pdf > > As I mentioned in another thread, learn PSL, it is a real eye opener for > verification. It's in the pipe...a very long one unfortunately ;-) But thanks for the pointer. Can you verify if a certain path is not violating the setup time of your register? Can you verify what is the delay it takes to go from register A to register B through some logic? > > if the path *is not* multicycle you may wrongly >> relax the timing too much and never realize until another optimization takes place >> and your circuit does not work any more. > > Not exactly, you will simply not get timing closure and your will > probably end up using more resources then necessary. Assume a single cycle path that you set to be multicycle because of mistake in your analysis. The synthesis tool will not know if your multicycle path is correct or wrong, therefore it will relax the timing between the selected end points and you will sample the result at the wrong time. The STA will correctly report the path is indeed fulfilling the constraint, but the logic will take the result too early. If you decided not to roll your postlayout sim because you relied on your STA, then you are set to find nasty surprises on the bench. Al From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 50 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396528421 86.29.12.221 (Thu, 03 Apr 2014 12:33:41 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 12:33:41 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 13:33:39 +0100 X-Received-Body-CRC: 4197442378 X-Received-Bytes: 2754 Xref: news.eternal-september.org comp.lang.vhdl:7407 Hi Al, On 03/04/2014 11:48, alb wrote: > Hi Hans, > > HT-Lab wrote: > [removed text and added reference in square brackets] >>> a. is difficult to maintain them [multicycle constraints]; if the >>> logic path has been optimized the constraint does not work anymore >> >> I think you are confusing propagation (or false path) delay with >> multicycle path delay. A multicycle delay is a synchronous "number of >> clock cycle" based delay, it does not depend on the clock frequency. > > IMHO a multicycle path delay is a propagation delay specified as > relative to the clock period. Hence it *does* depend on the clock > frequency, while the propagation through your gates does not (it depends > on the technology). You still have your terminology wrong, here is a SDC example of an typical MCP constraint: set_multicycle_path 2 -from reg_alu* -to reg_mult* Notice there is no time, just a natural number of clock cycles. > > If your path takes 12.3 ns you would have to set a multicycle constraint > of 2 with a 100MHz clock, but 3 with a 200MHz one. You are mixing your constraints. If your combinational path takes 12.3 ns you set a clock constraint of 81MHz. If you have a MCP in your design you are most likely controlling the output register with an enable pin. You do not use a MCP to constraint a propagation delay. .. > > Can you verify if a certain path is not violating the setup time of your > register? Can you verify what is the delay it takes to go from > register A to register B through some logic? Not with assertions, Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.204.71.78 with SMTP id g14mr875956bkj.3.1396531855864; Thu, 03 Apr 2014 06:30:55 -0700 (PDT) X-Received: by 10.50.61.144 with SMTP id p16mr442164igr.16.1396531855391; Thu, 03 Apr 2014 06:30:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!z11no3080511lbi.1!news-out.google.com!vq6ni1257lbb.1!nntp.google.com!ur14no1814658igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Apr 2014 06:30:52 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Thu, 03 Apr 2014 13:30:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7408 On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: > > IMHO a multicycle path delay is a propagation delay specified as > > relative to the clock period. Hence it *does* depend on the clock > > frequency, while the propagation through your gates does not (it depends > > on the technology). > > You still have your terminology wrong, here is a SDC example of an > typical MCP constraint: > > set_multicycle_path 2 -from reg_alu* -to reg_mult* > > Notice there is no time, just a natural number of clock cycles. The value of '2' though is computed based on the clock period. Alb already pointed that out earlier in the thread "If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one." Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 3 Apr 2014 13:48:52 GMT Lines: 57 Message-ID: References: X-Trace: individual.net RZAfnu56yKov/Ga/LwuVpwnok30/TWqjN5dgSTQtvusgJHgL/g X-Orig-Path: not-for-mail Cancel-Lock: sha1:b4dtBtDCpYtTCKSqabUa6BBuxfU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7409 Hi Hans, HT-Lab wrote: [] >> IMHO a multicycle path delay is a propagation delay specified as >> relative to the clock period. Hence it *does* depend on the clock >> frequency, while the propagation through your gates does not (it depends >> on the technology). > > You still have your terminology wrong, here is a SDC example of an > typical MCP constraint: > > set_multicycle_path 2 -from reg_alu* -to reg_mult* > I apologize but I did not understand from this example what is wrong in my terminology. > Notice there is no time, just a natural number of clock cycles. > reading out loud your MCP constraint: 'the propagation delay from reg_alu* to reg_mult* has to be smaller than 2 clock cycles (minus setup time)' Notion of time is automatically inferred by your tool since it knows what is the clock period for those particular registers. If the two registers are in two different clock domains I doubt you can really set a multicycle path constraint (at least it does not make sense to me). >> If your path takes 12.3 ns you would have to set a multicycle constraint >> of 2 with a 100MHz clock, but 3 with a 200MHz one. > > You are mixing your constraints. If your combinational path takes 12.3 > ns you set a clock constraint of 81MHz. If you have a MCP in your design > you are most likely controlling the output register with an enable pin. I have to find out how much time I need to wait before sampling the logic with my output enable. There are several (in the 100s) paths between input and output (it's an fpu), therefore I can die under a pile of multicycle path constraints. > You do not use a MCP to constraint a propagation delay. IMHO yes you do. You are telling the synthesis tool that a particular path (or branch of a graph) can have a propagation delay: Tp < N * clock_period - Tsetup rather than the usual: Tp < clock_period - Tsetup Why would you think the MCP does not constraint the propagation delay? Al From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> In-Reply-To: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: <19e%u.484$%U7.400@fx05.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396534973 86.29.12.221 (Thu, 03 Apr 2014 14:22:53 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 14:22:53 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 15:22:51 +0100 X-Received-Body-CRC: 1980667029 X-Received-Bytes: 2258 Xref: news.eternal-september.org comp.lang.vhdl:7410 On 03/04/2014 14:30, KJ wrote: > On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: >>> IMHO a multicycle path delay is a propagation delay specified as >>> relative to the clock period. Hence it *does* depend on the clock >>> frequency, while the propagation through your gates does not (it depends >>> on the technology). >> >> You still have your terminology wrong, here is a SDC example of an >> typical MCP constraint: >> >> set_multicycle_path 2 -from reg_alu* -to reg_mult* >> >> Notice there is no time, just a natural number of clock cycles. > > The value of '2' though is computed based on the clock period. Alb already pointed that out earlier in the thread "If your path takes 12.3 ns you would have to set a multicycle constraint of 2 with a 100MHz clock, but 3 with a 200MHz one." > We are taking about different issues here. My argument is that you should not exchange a clock constraint for an MCP one, Regards, Hans. www.ht-lab.com > Kevin Jennings > From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140403-0, 03/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 71 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396535525 86.29.12.221 (Thu, 03 Apr 2014 14:32:05 UTC) NNTP-Posting-Date: Thu, 03 Apr 2014 14:32:05 UTC Organization: virginmedia.com Date: Thu, 03 Apr 2014 15:32:03 +0100 X-Received-Body-CRC: 2509449848 X-Received-Bytes: 3516 Xref: news.eternal-september.org comp.lang.vhdl:7411 On 03/04/2014 14:48, alb wrote: Hi AL, > Hi Hans, > > HT-Lab wrote: > [] >>> IMHO a multicycle path delay is a propagation delay specified as >>> relative to the clock period. Hence it *does* depend on the clock >>> frequency, while the propagation through your gates does not (it depends >>> on the technology). >> >> You still have your terminology wrong, here is a SDC example of an >> typical MCP constraint: >> >> set_multicycle_path 2 -from reg_alu* -to reg_mult* >> > > I apologize but I did not understand from this example what is wrong in > my terminology. > >> Notice there is no time, just a natural number of clock cycles. >> > > reading out loud your MCP constraint: > > 'the propagation delay from reg_alu* to reg_mult* has to be smaller than > 2 clock cycles (minus setup time)' > > Notion of time is automatically inferred by your tool since it knows > what is the clock period for those particular registers. If the two > registers are in two different clock domains I doubt you can really set > a multicycle path constraint (at least it does not make sense to me). > >>> If your path takes 12.3 ns you would have to set a multicycle constraint >>> of 2 with a 100MHz clock, but 3 with a 200MHz one. >> >> You are mixing your constraints. If your combinational path takes 12.3 >> ns you set a clock constraint of 81MHz. If you have a MCP in your design >> you are most likely controlling the output register with an enable pin. > > I have to find out how much time I need to wait before sampling the > logic with my output enable. There are several (in the 100s) paths > between input and output (it's an fpu), therefore I can die under a pile > of multicycle path constraints. > >> You do not use a MCP to constraint a propagation delay. Poor choice of words on my part, I should have said you don't use an MCP constraint as a clock constraint. Regards, Hans. www.ht-lab.com > > IMHO yes you do. You are telling the synthesis tool that a particular > path (or branch of a graph) can have a propagation delay: > > Tp < N * clock_period - Tsetup > > rather than the usual: > > Tp < clock_period - Tsetup > > Why would you think the MCP does not constraint the propagation delay? > > Al > From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.15.53.136 with SMTP id r8mr2086915eew.5.1396543343899; Thu, 03 Apr 2014 09:42:23 -0700 (PDT) X-Received: by 10.50.9.71 with SMTP id x7mr484565iga.6.1396543340540; Thu, 03 Apr 2014 09:42:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!p9no3261021lbv.0!news-out.google.com!vq6ni1257lbb.1!nntp.google.com!ur14no1891891igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Apr 2014 09:42:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [cross-post]path verification From: KJ Injection-Date: Thu, 03 Apr 2014 16:42:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7412 On Thursday, April 3, 2014 9:48:52 AM UTC-4, alb wrote: > I have to find out how much time I need to wait before sampling the > logic with my output enable. There are several (in the 100s) paths > between input and output (it's an fpu), therefore I can die under a pile > of multicycle path constraints. You should be able to wild card the path sources inside your block and specify exactly the output enable signal. There should be no need to specify each path source explicitly. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Thu, 03 Apr 2014 18:12:29 -0400 Organization: A noiseless patient Spider Lines: 96 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Apr 2014 22:12:10 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="21453"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+YPgF9JgjAir02We0iCDhw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:dJ4gV/2r8wlYqyQ57KoHwRVax6Y= Xref: news.eternal-september.org comp.lang.vhdl:7413 On 4/3/2014 3:05 AM, alb wrote:> Hi Rick, > > rickman wrote: > [] >>> I have a microcontroller with an FPU which is delivered as an IP (I mean >>> the FPU). In order to run at a decent frequency, some of the operations >>> are allowed to complete in within a certain amount of cycles, but the >>> main problem is that we do not know how many. >>> >>> That said, if we run the synthesis tool without timing constraints on >>> those paths, we have a design that is much slower than can be. >>> Multicycle constraints are out of question because they are hard to >>> verify and maintain, so we decided to set false paths and perform >>> post-layout sims to extract those values to be used in the RTL in a >>> second iteration. > [] >> >> If I understand you correctly, you have a piece of combinatorial logic >> and you need to know how fast it will run in your design. This will >> then let your surrounding circuitry wait some number of clock cycles to >> read the result, that give you a longer delay than the delay though the >> logic. > > Precisely. > >> I think your starting premise that multi-cycle constraints are "out of >> the question" is where you have erred. Multi-cycle constraints are >> exactly what are required and if you don't understand how to use them >> you are not likely to get a good result. > > There are two aspects here to consider: > > 1. multicycle constraints need not only a /from/ and /to/ parameter, they also > need a /through/ parameter. When you have a logic depth of 111 gates you start to > understand why a multicycle constraint cannot be a sustainable solution. I can't say I follow that. I have only ever specified a from and to parameter for a timing constraint. I have never needed to indicate a "through" parameter. If you have special sections of the logic that need a shorter timing constraint than others, I would expect that to be a subset of the from and to, not a special "though" path. Is there something unique about your design that a simple from and to spec doesn't capture the nuance? > 2. My experience in setting up multicycle constraints is nearly zero and starting > off with such an approach on this type of project would be begging for troubles. How much experience do you have with any of the other approaches you are trying? I mean, you are here asking for advice. So clearly there are things about each of these approaches you are not familiar with. >> Post P&R simulation is not a good way to validate timing because it is >> so hard to cover every path through the logic. Static timing analysis >> is the right way to do this and you need to learn to use it properly. > > I've read several times on this group the skepticism behind static timing analysis > when multicycle constraints are in place. I have to search back in the archives to > really understand the technical motivations, but the bottom line is: > > a. is difficult to maintain them; if the logic path has been optimized the > constraint does not work anymore I don't follow that either. It is seldom that any from/to path would be optimized away. If it is, it is likely due to an error in your code which you will need to fix anyway. > b. is difficult to verify them; if the path *is not* multicycle you may wrongly > relax the timing too much and never realize until another optimization takes place > and your circuit does not work any more. ALL timing constraints are difficult to verify... no, make that impossible. That has always been one of my complaints about static timing analysis, there is no way to verify the constraints other than the coverage number which is just a pass/fail sort of thing. > If anyone sees a flaw in my points above I'd be glad to be corrected. Perhaps I am missing something. ??? -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Thu, 03 Apr 2014 18:21:53 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 3 Apr 2014 22:21:33 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="24042"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9R37M+2jCkQ+wm66euWRo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <19e%u.484$%U7.400@fx05.am4> Cancel-Lock: sha1:uHEqh49miEZZLZ1w3ARFWGj3XaU= Xref: news.eternal-september.org comp.lang.vhdl:7414 On 4/3/2014 10:22 AM, HT-Lab wrote:> On 03/04/2014 14:30, KJ wrote: >> On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: >>>> IMHO a multicycle path delay is a propagation delay specified as >>>> relative to the clock period. Hence it *does* depend on the clock >>>> frequency, while the propagation through your gates does not (it >>>> depends >>>> on the technology). >>> >>> You still have your terminology wrong, here is a SDC example of an >>> typical MCP constraint: >>> >>> set_multicycle_path 2 -from reg_alu* -to reg_mult* >>> >>> Notice there is no time, just a natural number of clock cycles. >> >> The value of '2' though is computed based on the clock period. Alb >> already pointed that out earlier in the thread "If your path takes >> 12.3 ns you would have to set a multicycle constraint of 2 with a >> 100MHz clock, but 3 with a 200MHz one." >> > > We are taking about different issues here. My argument is that you > should not exchange a clock constraint for an MCP one, I think you are misreading what is intended. It is assumed there is already a clock timing constraint of 100 MHz. That is for the general logic in this clock domain. But for a certain section of logic the output of the logic is not used for some number of clock cycles that will be determined by the delay through the logic which is expected to be longer than one clock cycle. The OP wants to set this number of clock cycles in the timing constraints of that special path to verify that the P&R output will work with the timing he has picked. If the timing fails he has the options of working to improve the timing in the P&R or changing the logic of the register enable to allow more clock cycles for this path. In no case would he want to change the timing constraint on the clock since that constraint is set by other aspects of his design goals. Do I misunderstand what you are trying to say? -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 14:09:46 GMT Lines: 44 Message-ID: References: X-Trace: individual.net FKgR5kH/xYpARDDJ1AdfTgpO01nQpD/9M5VHPEY/8N3nouRkYi X-Orig-Path: not-for-mail Cancel-Lock: sha1:wT54wFsHemaiYDcfSOnsmnSQBaE= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7415 Hi Kevin, KJ wrote: >> I have to find out how much time I need to wait before sampling the >> logic with my output enable. There are several (in the 100s) paths >> between input and output (it's an fpu), therefore I can die under a pile >> of multicycle path constraints. > > You should be able to wild card the path sources inside your block and > specify exactly the output enable signal. There should be no need to > specify each path source explicitly. Imagine an fpu, with two input registers for the operands, one for the operator and an output register for the result. The result register is the one that will receive the output enable. Depending on the operator I will have a different path. If I wildcard the path sources than I'm overly constraining and a 'nop' operation will take as much as a division operation, which is not what we want. Since most of the combinatorial functions are reused several times in each operation, the datapath starts to be painfully complicated. That is the main reason why I discarded the option to setup multicycle constraints. The alternative, though, is not very palatable either. We decided to set false paths between the above mentioned registers and let post-par sim figure out whether we are in or out with our output enable. The problem is that post-par simulation may not cover the whole set of timing scerarios the logic will encounter. For instance I do not know if a backannotated simulation includes clock skew, while AFAIK it shoudl be taken into account in STA. The described approach tries to verify timing, but I'm not sure this is really going to be risk free. Certainly I can add some jitter to my clock within the simulation itself to make it more /realistic/ , but I will certainly not cover all the cases. Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of unconfortable to proceed without a fully consistent picture. Al From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 14:09:49 GMT Lines: 69 Message-ID: References: X-Trace: individual.net uVTN+L/pUHIyi4rGq0B3jQv7389nc5bWPUeVQXTxWZgdZqDcXQ X-Orig-Path: not-for-mail Cancel-Lock: sha1:WJHPLxHltwSOk8ef7xupOayRi1U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7416 Hi Rick, rickman wrote: [] > > 1. multicycle constraints need not only a /from/ and /to/ > parameter, they also > > need a /through/ parameter. When you have a logic depth of 111 gates > you start to > > understand why a multicycle constraint cannot be a sustainable solution. > > I can't say I follow that. I have only ever specified a from and to > parameter for a timing constraint. I have never needed to indicate a > "through" parameter. If you have special sections of the logic that > need a shorter timing constraint than others, I would expect that to be > a subset of the from and to, not a special "though" path. Is there > something unique about your design that a simple from and to spec > doesn't capture the nuance? Imagine your path between two registers (A and B) is set by another register C. The resulting operation is to be stored in register D. If you do not set a /through/ clause you will constraint each path with the maximum delay, which is not desirable. > > > 2. My experience in setting up multicycle constraints is nearly > zero and starting > > off with such an approach on this type of project would be begging > for troubles. > > How much experience do you have with any of the other approaches you are > trying? I mean, you are here asking for advice. So clearly there are > things about each of these approaches you are not familiar with. I've often done post-par sims, but it was combined with an STA, therefore I've always been sure the design was correct as long as STA did not report anything fishy *and* post-par sim succeeded. Recently I started to look at post-par sims as an additional step which is not necessarily required for synchronous logic as long as your input constraints are well defined. In this case we cannot use STA to do time analysis and I'm unconfortable. > > > a. is difficult to maintain them; if the logic path has been > optimized the > > constraint does not work anymore > > I don't follow that either. It is seldom that any from/to path would be > optimized away. If it is, it is likely due to an error in your code > which you will need to fix anyway. I certainly was talking about the /through/ clause I mentioned earlier. The synthesis tool might optimize away (or maybe rename) certain nets and you're constraint will not be applicable anymore. > > b. is difficult to verify them; if the path *is not* multicycle you > may wrongly > > relax the timing too much and never realize until another > optimization takes place > > and your circuit does not work any more. > > ALL timing constraints are difficult to verify... no, make that > impossible. That has always been one of my complaints about static > timing analysis, there is no way to verify the constraints other than > the coverage number which is just a pass/fail sort of thing. That is why you'd be better off if you didn't have them! :-) From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.182.81.7 with SMTP id v7mr6507obx.28.1396625269036; Fri, 04 Apr 2014 08:27:49 -0700 (PDT) X-Received: by 10.182.241.70 with SMTP id wg6mr423obc.19.1396625268818; Fri, 04 Apr 2014 08:27:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2815268iga.0!news-out.google.com!xg2ni98igc.0!nntp.google.com!ur14no2451962igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 08:27:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Fri, 04 Apr 2014 15:27:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7417 > >> I have to find out how much time I need to wait before sampling the=20 > >> logic with my output enable. There are several (in the 100s) paths=20 > >> between input and output (it's an fpu), therefore I can die under a pi= le=20 > >> of multicycle path constraints.=20 > >=20 > > You should be able to wild card the path sources inside your block and= =20 > > specify exactly the output enable signal. There should be no need to= =20 > > specify each path source explicitly.=20 >=20 > Imagine an fpu, with two input registers for the operands, one for the=20 > operator and an output register for the result. The result register is=20 > the one that will receive the output enable.=20 >=20 > Depending on the operator I will have a different path. If I wildcard=20 > the path sources than I'm overly constraining and a 'nop' operation will= =20 > take as much as a division operation, which is not what we want.=20 >=20 You're assuming (and you may be correct since you know the design better th= an I) that the logic path taken by the 'nop' operation is in fact segregate= d from that of the division operation. Certainly at the instruction opcode= decode level they're not separate...but maybe that occurs on a different c= lock cycle. > Since most of the combinatorial functions are reused several times in=20 > each operation, the datapath starts to be painfully complicated. That is= =20 > the main reason why I discarded the option to setup multicycle=20 > constraints.=20 >=20 And makes me think that things are not implemented in the logic in a segreg= ated fashion which could mean that seemingly unrelated instructions like 'n= op' might depend on logic used by division. > The alternative, though, is not very palatable either. We decided to set= =20 > false paths between the above mentioned registers and let post-par sim=20 > figure out whether we are in or out with our output enable. The problem= =20 > is that post-par simulation may not cover the whole set of timing=20 > scerarios the logic will encounter.=20 >=20 That's correct. Post route sim really tells you nothing about timing. The= only use I've found for that sim can be for finding that something wasn't = implemented correctly which then resulted in finding a work around and subm= itting a service request to the software provider. That has only happened = once (for me). > For instance I do not know if a backannotated simulation includes clock= =20 > skew, while AFAIK it shoudl be taken into account in STA. Sims do not take into account any timing variation. You may be able to run= them with 'min', 'typical' or 'maximum' but not combinations. It is no su= bstitute for static timing analysis (nor is it intended to be). > The described=20 > approach tries to verify timing, but I'm not sure this is really going=20 > to be risk free.=20 >=20 > Certainly I can add some jitter to my clock within the simulation itself= =20 > to make it more /realistic/ , but I will certainly not cover all the=20 > cases.=20 >=20 > Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of=20 > unconfortable to proceed without a fully consistent picture.=20 My suggestions: 1. Since this is purchased IP, go back to the supplier, pay them some money= and tell them you need validated timing constraints for their design. 2. If #1 is not feasible for whatever reason, then see about altering the I= P to insert pipeline registers. This may be ugly and means you will have t= o reverse engineer the design but it is verifiable since you will be able t= o get through STA without having to wonder if your constraints are correct = and you can run original and modified sims to verify function is unchanged. 3. This might actually be the best option but I don't know how well it rea= lly works since I've never tried it. You can buy software that claims to v= erify that timing constraints are correct [1] Kevin Jennings [1] http://www.bluepearlsoftware.com/sdc/ From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.58.169.198 with SMTP id ag6mr4356573vec.22.1396631221570; Fri, 04 Apr 2014 10:07:01 -0700 (PDT) X-Received: by 10.50.59.179 with SMTP id a19mr116737igr.10.1396631221429; Fri, 04 Apr 2014 10:07:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w5no593295qac.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no2573485igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 10:07:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Andy Injection-Date: Fri, 04 Apr 2014 17:07:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7418 It is not clear from the example what is the index range on SelFifo, and if= that range matches the range of DataAvlble. We do know that Selfifo has 6 = bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, bu= t we do not know DataAvlble's index range direction. The loop would only work if SelFifo'range is 6 downto 1. The following would work if the index diretion of both DataAvlble and SelFi= fo is "downto", given the correct value for DaOffset: pSelFifo : process(Clk, SRst)=20 constant DaOffset : integer :=3D 1; begin=20 if SRst =3D '1' then=20 SelFifo <=3D (others=3D>'0');=20 elsif rising_edge(Clk) then=20 SelFifo <=3D (others=3D>'0');=20 for i in SelFifo'reverse_range loop -- right to left in SelFifo if DataAvlble(i + DaOffset) =3D '1' then=20 SelFifo(i) <=3D '1';=20 exit; -- prevent multiple bit set, as in original=20 end if;=20 end loop;=20 end if;=20 end process;=20 The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop. Andy From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 4 Apr 2014 21:53:20 GMT Lines: 115 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> X-Trace: individual.net is1Yj9rGx6h15qUyF320VQhI45tXza3dukrOjaaWJydnzIeYNZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Tzb/m29/qt1aR6U94QrPyt4LFsc= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7419 Hi Kevin, KJ wrote: [] >> Imagine an fpu, with two input registers for the operands, one for the >> operator and an output register for the result. The result register is >> the one that will receive the output enable. >> >> Depending on the operator I will have a different path. If I wildcard >> the path sources than I'm overly constraining and a 'nop' operation will >> take as much as a division operation, which is not what we want. >> > > You're assuming (and you may be correct since you know the design > better than I) that the logic path taken by the 'nop' operation is in > fact segregated from that of the division operation. Certainly at the > instruction opcode decode level they're not separate...but maybe that > occurs on a different clock cycle. there are a certain number of 'atomic' operations that are reused among several floating point ops, so there's no such a clear separation among them. The decode is performed on a different cycle, therefore is not of a concern. >> Since most of the combinatorial functions are reused several times in >> each operation, the datapath starts to be painfully complicated. That is >> the main reason why I discarded the option to setup multicycle >> constraints. >> > > And makes me think that things are not implemented in the logic in a > segregated fashion which could mean that seemingly unrelated > instructions like 'nop' might depend on logic used by division. That is correct. And this is why the need of a set of /through/ clauses need to be in place. Imagine the following: opcode path multicycle constraint X a + b + c -through a -through b -through c Y a + d + e + f -through a -through d -through e -through f Z q + r + t + a + d ... The rest of the constraint definition is the /from/ and /to/ clause which are simpler since they are the input registers and the output one. Now, since 'atomic' operations are separated into different entities (as far as I can tell) I may take the input ports to identify a path through that entity and maybe survive net renaming and the like, but you can imagine how much fun it might be to trace all individual paths. Oh and I forgot! some of the operations (notably the division) they do need registers to hold temporary results, therefore they will have to be treated separately (so I cannot really false path the whole block...jeez). >> The alternative, though, is not very palatable either. We decided to set >> false paths between the above mentioned registers and let post-par sim >> figure out whether we are in or out with our output enable. The problem >> is that post-par simulation may not cover the whole set of timing >> scerarios the logic will encounter. >> > > That's correct. Post route sim really tells you nothing about timing. > The only use I've found for that sim can be for finding that something > wasn't implemented correctly which then resulted in finding a work > around and submitting a service request to the software provider. you mean it wasn't implemented correctly in the p&r tool? >> For instance I do not know if a backannotated simulation includes clock >> skew, while AFAIK it shoudl be taken into account in STA. > > Sims do not take into account any timing variation. You may be able > to run them with 'min', 'typical' or 'maximum' but not combinations. > It is no substitute for static timing analysis (nor is it intended to > be). This is indeed what I also thought (I hate to be right!). > My suggestions: > 1. Since this is purchased IP, go back to the supplier, pay them some > money and tell them you need validated timing constraints for their > design. out of question, the developer is a chinese who left to Brazil hoping to find his karma... (cannot truly blame him) > 2. If #1 is not feasible for whatever reason, then see about altering > the IP to insert pipeline registers. This may be ugly and means you > will have to reverse engineer the design but it is verifiable since > you will be able to get through STA without having to wonder if your > constraints are correct and you can run original and modified sims to > verify function is unchanged. This was my very first proposal. Rejected with a simple: 'no design changes'. I understant - partially - the philosophy to keep the IP as is (considering that has been functionally verified), but maybe here it would be simpler and _safer_ to add a pipeline. I thought about C-slowing and retiming, I can start with large logic depth (maximum is 113!) and maybe add registers at the input ports of the 'atomic' operations I mentioned earlier. > 3. This might actually be the best option but I don't know how well > it really works since I've never tried it. You can buy software that > claims to verify that timing constraints are correct [1] I was wondering if they let us try their tool for a short period of time (maybe a couple of weeks), enough to get ourselves out of this painful situation and maybe convince the management is really a must have tool. > [1] http://www.bluepearlsoftware.com/sdc/ any user here? From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Fri, 04 Apr 2014 21:20:40 -0400 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Apr 2014 01:20:20 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="9608"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19v+X/gygwKQBTCNFrofVAY" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> Cancel-Lock: sha1:mBOO9CY1g0gpgnEiyaA3PTL3Q/U= Xref: news.eternal-september.org comp.lang.vhdl:7420 On 4/4/2014 11:27 AM, KJ wrote: ...snip... >> The described >> approach tries to verify timing, but I'm not sure this is really going >> to be risk free. >> >> Certainly I can add some jitter to my clock within the simulation itself >> to make it more /realistic/ , but I will certainly not cover all the >> cases. >> >> Considering the target FPGA is an RTAX2000 (~20'000$), we are kind of >> unconfortable to proceed without a fully consistent picture. > > My suggestions: > 1. Since this is purchased IP, go back to the supplier, pay them some money and tell them you need validated timing constraints for their design. > 2. If #1 is not feasible for whatever reason, then see about altering the IP to insert pipeline registers. This may be ugly and means you will have to reverse engineer the design but it is verifiable since you will be able to get through STA without having to wonder if your constraints are correct and you can run original and modified sims to verify function is unchanged. > 3. This might actually be the best option but I don't know how well it really works since I've never tried it. You can buy software that claims to verify that timing constraints are correct [1] > > Kevin Jennings I concur. Right now I don't see how the design can be analyzed for timing. If the OP wants to set different timing constraints for different paths through the combinatorial logic, there either has to be some clearly identifiable approach to isolating the paths for static timing analysis or the design has to change. I guess one question would be why use the IP from this particular vendor? Another would be if there are clearly different paths within the combinatorial logic, can these could be broken out in some way to allow timing constraints to be applied separately? It would not be unreasonable to duplicate the input registers so that each differently timed operation would not have the same starting point in the design allowing separate from/to timing constraints. If information on the operation is available at the time the input registers are loaded each one could have a separate enable so the tools would clearly know they are equivalent. Otherwise the tools might try to be too smart for their own good and you may need to use modifiers to keep the duplicate registers from being optimized away. -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: Fri, 04 Apr 2014 21:22:41 -0400 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Apr 2014 01:22:33 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="9608"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y3S7x/LmE22yQaFxvCkFz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:GAK09NqxX7B7fcJ901wZzIWSZFA= Xref: news.eternal-september.org comp.lang.vhdl:7421 On 4/4/2014 10:09 AM, alb wrote: > Hi Rick, > > rickman wrote: > [] >>> 1. multicycle constraints need not only a /from/ and /to/ >> parameter, they also >>> need a /through/ parameter. When you have a logic depth of 111 gates >> you start to >>> understand why a multicycle constraint cannot be a sustainable solution. >> >> I can't say I follow that. I have only ever specified a from and to >> parameter for a timing constraint. I have never needed to indicate a >> "through" parameter. If you have special sections of the logic that >> need a shorter timing constraint than others, I would expect that to be >> a subset of the from and to, not a special "though" path. Is there >> something unique about your design that a simple from and to spec >> doesn't capture the nuance? > > Imagine your path between two registers (A and B) is set by another > register C. The resulting operation is to be stored in register D. If > you do not set a /through/ clause you will constraint each path with the > maximum delay, which is not desirable. Ok, so where is the problem with specifying the through parameters if you know them? >>> 2. My experience in setting up multicycle constraints is nearly >> zero and starting >>> off with such an approach on this type of project would be begging >> for troubles. >> >> How much experience do you have with any of the other approaches you are >> trying? I mean, you are here asking for advice. So clearly there are >> things about each of these approaches you are not familiar with. > > I've often done post-par sims, but it was combined with an STA, > therefore I've always been sure the design was correct as long as STA > did not report anything fishy *and* post-par sim succeeded. I have never done post-par sims because they are pointless for timing verification and the logic should be good by construction. In essence this is only verifying the synthesis tools, not the design. > Recently I started to look at post-par sims as an additional step which > is not necessarily required for synchronous logic as long as your input > constraints are well defined. > > In this case we cannot use STA to do time analysis and I'm > unconfortable. I think uncomfortable would be an understatement. There is no other way to properly and fully verify timing than STA. Either make it work or find a different way to implement your design is my advice. >>> a. is difficult to maintain them; if the logic path has been >> optimized the >>> constraint does not work anymore >> >> I don't follow that either. It is seldom that any from/to path would be >> optimized away. If it is, it is likely due to an error in your code >> which you will need to fix anyway. > > I certainly was talking about the /through/ clause I mentioned earlier. > The synthesis tool might optimize away (or maybe rename) certain nets > and you're constraint will not be applicable anymore. If the tool optimizes away some part of your design you have problems. I believe the renaming is done with synonyms so that a constraint should still apply. You might want to get in touch with support. Who's parts are you using? If a specified through target can be optimized out it isn't a very useful feature to have in the STA tool is it? >>> b. is difficult to verify them; if the path *is not* multicycle you >> may wrongly >>> relax the timing too much and never realize until another >> optimization takes place >>> and your circuit does not work any more. >> >> ALL timing constraints are difficult to verify... no, make that >> impossible. That has always been one of my complaints about static >> timing analysis, there is no way to verify the constraints other than >> the coverage number which is just a pass/fail sort of thing. > > That is why you'd be better off if you didn't have them! I think of it like getting old. It is the worst thing in the world except for the alternative. -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.182.230.168 with SMTP id sz8mr3423385obc.9.1396662295526; Fri, 04 Apr 2014 18:44:55 -0700 (PDT) X-Received: by 10.182.110.167 with SMTP id ib7mr89073obb.5.1396662295382; Fri, 04 Apr 2014 18:44:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no2777038igb.0!news-out.google.com!gi6ni200igc.0!nntp.google.com!l13no3085360iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 18:44:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Sat, 05 Apr 2014 01:44:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7422 On Friday, April 4, 2014 5:53:20 PM UTC-4, alb wrote: >=20 > > And makes me think that things are not implemented in the logic in a=20 > > segregated fashion which could mean that seemingly unrelated=20 > > instructions like 'nop' might depend on logic used by division. >=20 > That is correct. And this is why the need of a set of /through/ clauses= =20 > need to be in place. Imagine the following: >=20 > opcode path multicycle constraint > X a + b + c -through a -through b -through c > Y a + d + e + f -through a -through d -through e -through f > Z q + r + t + a + d ... >=20 > The rest of the constraint definition is the /from/ and /to/ clause=20 > which are simpler since they are the input registers and the output one. >=20 Unless you obtain a deep knowledge of the design, if you try to do what you= described above, you're likely screwed. There's always the chance that it= 's not quite as bad as it appears right now, but there is an equally good c= hance that it is actually worse...and you won't know it until it's too late= and you're shipping product and 'wierd' things are happening when the boar= d warms up or cools down or whatever. > > That's correct. Post route sim really tells you nothing about timing. = =20 > > The only use I've found for that sim can be for finding that something= =20 > > wasn't implemented correctly which then resulted in finding a work=20 > > around and submitting a service request to the software provider. =20 >=20 > you mean it wasn't implemented correctly in the p&r tool? >=20 That's correct. Actually, I had two instances. One was if you passed into= an entity a generic that happened to be a vector, it treated the elements = of the vector as '1 to n', even though the entity definition specifically d= efined them as 'n downto 1'. The other case had to do with not initializin= g the contents of an inferred memory. Using the post-route sim model was conclusive evidence of an improper build= and the cool thing is that the sim really only had to run for a couple nan= oseconds to prove the memory initialization problem; an assertion printing = out the details of the vector comes out simply from starting the simulator. > > My suggestions: >=20 > > 3. This might actually be the best option but I don't know how well=20 > > it really works since I've never tried it. You can buy software that= =20 > > claims to verify that timing constraints are correct [1] > I was wondering if they let us try their tool for a short period of time= =20 > (maybe a couple of weeks), enough to get ourselves out of this painful=20 > situation and maybe convince the management is really a must have tool. >=20 Seems like this would be your best option. Right now, you're caught in the= project management iron triangle: you don't have the right resource (off = in Brazil), you don't have schedule time to modify the design and it sounds= like management might not want to spend the $$ to get the design correct. = The only end result that will have a functional design in this case is to = punt on performance and accept whatever slow speed you can get out of the I= P core by only specifying constraints that you know for absolute fact are c= orrect and stop trying to figure out if this path through this hunk really = can wait a clock or not. Even if you spend the money and the tool happens to guarantee that they wil= l produce valid constraints, there is no guarantee that the end performance= will actually be any better...you will simply know that you've got it prop= erly constrained. You might also want to do some more Google searching for= some other tools that perform this constraint validation. I don't think t= he link I gave you previously is the one I remember from a while back eithe= r in this forum or possibly comp.lang.vhdl so there might be at least one o= ther company to look for to generate valid constraints. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.50.73.132 with SMTP id l4mr3662668igv.5.1396663590207; Fri, 04 Apr 2014 19:06:30 -0700 (PDT) X-Received: by 10.182.142.38 with SMTP id rt6mr109obb.10.1396663590025; Fri, 04 Apr 2014 19:06:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no3087690iga.0!news-out.google.com!gi6ni200igc.0!nntp.google.com!l13no3087688iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Apr 2014 19:06:29 -0700 (PDT) In-Reply-To: <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77d6bb14-5b18-4f77-af8f-f793abcccd0c@googlegroups.com> Subject: Re: [cross-post]path verification From: KJ Injection-Date: Sat, 05 Apr 2014 02:06:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7423 On Friday, April 4, 2014 9:44:55 PM UTC-4, KJ wrote: > Even if you spend the money and the tool happens to guarantee that they will > produce valid constraints, there is no guarantee that the end performance > will actually be any better...you will simply know that you've got it > properly constrained. You might also want to do some more Google searching > for some other tools that perform this constraint validation. I don't think > the link I gave you previously is the one I remember from a while back either > in this forum or possibly comp.lang.vhdl so there might be at least one other > company to look for to generate valid constraints. > Here is another company that seems to have a timing constraint verification product http://www.averant.com/products-solidtc.html Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.66.139.231 with SMTP id rb7mr8887479pab.33.1396725616244; Sat, 05 Apr 2014 12:20:16 -0700 (PDT) X-Received: by 10.50.59.179 with SMTP id a19mr265577igr.10.1396725616092; Sat, 05 Apr 2014 12:20:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no3154333igb.0!news-out.google.com!gi6ni228igc.0!nntp.google.com!l13no3346708iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:20:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.140.40.14; posting-account=tKKUQAoAAABSFlLwwB8ig4AeRm5W6Gbz NNTP-Posting-Host: 14.140.40.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Subject: how to avoidind multisourcing on signal From: yogesh malekar Injection-Date: Sat, 05 Apr 2014 19:20:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7424 How to avoi multisourcing on the signal,and bad synchronois descrption From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.236.175.66 with SMTP id y42mr10425721yhl.38.1396725784158; Sat, 05 Apr 2014 12:23:04 -0700 (PDT) X-Received: by 10.50.80.10 with SMTP id n10mr265450igx.2.1396725783989; Sat, 05 Apr 2014 12:23:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no108462qab.1!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3155151igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:23:03 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.140.40.14; posting-account=tKKUQAoAAABSFlLwwB8ig4AeRm5W6Gbz NNTP-Posting-Host: 14.140.40.14 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <898f8fc4-586b-4e14-9849-59fef44b0f91@googlegroups.com> Subject: how to avoidind multisourcing on signal From: yogesh malekar Injection-Date: Sat, 05 Apr 2014 19:23:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7425 Anybody give me vhdl program for non restoring division algorithm To burn it on cpld working on 4 MHZ frequency From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.66.139.231 with SMTP id rb7mr8895601pab.33.1396725876345; Sat, 05 Apr 2014 12:24:36 -0700 (PDT) X-Received: by 10.182.119.133 with SMTP id ku5mr133862obb.4.1396725876170; Sat, 05 Apr 2014 12:24:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no3155711igb.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3155693igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Apr 2014 12:24:35 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: how to avoidind multisourcing on signal From: KJ Injection-Date: Sat, 05 Apr 2014 19:24:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7426 On Saturday, April 5, 2014 3:20:15 PM UTC-4, yogesh malekar wrote: > How to avoi multisourcing on the signal,and bad synchronois descrption Perhaps by asking someone other than you to write the code. From newsfish@newsfish Tue Dec 29 16:43:22 2015 X-Received: by 10.43.18.133 with SMTP id qg5mr12904496icb.13.1396820418444; Sun, 06 Apr 2014 14:40:18 -0700 (PDT) X-Received: by 10.50.143.1 with SMTP id sa1mr410435igb.12.1396820418341; Sun, 06 Apr 2014 14:40:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no3742447iga.0!news-out.google.com!gi6ni194igc.0!nntp.google.com!ur14no3701813igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Apr 2014 14:40:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.37.244.164; posting-account=dRhSmgoAAABgGYf0yu8Eg4Q7x1BVxe66 NNTP-Posting-Host: 72.37.244.164 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Subject: verilog questions From: sandhya pochiraju Injection-Date: Sun, 06 Apr 2014 21:40:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7427 Hi All, I have few questions in verilog. please can someone here help me un= derstand this.=20 Let's say, db_count =3D debounce_cnt at 10th positive edge.=20 will "IF" condition in second always block be true at 10th positive edge? or will "IF" condition in second always block be true at 11th positive edge= ? but on 11th positive edge db_count will be set to 0 by first always block= .=20 what is order of operation between "IF" and "Case" ? Though everything is in one always block and non blocking statements are us= ed, "IF" and "Case" are two seperate blocks in themselves. Is the non-block= ing behaviour of statements not confined seperately to "IF" and "Case" bloc= ks? i.e. statements inside "IF" are non-blocking but are they non-blocking = to statements inside "case" and vice versa? Code: `timescale 1 ns / 1 ns module debounce ( //inputs // what value is stored in pbtn_in and switch_in input clk, // clock=09 input [3:0] pbtn_in, // pushbutton inputs input [7:0] switch_in, // slider switch inputs =09 //outputs output reg [3:0] pbtn_db =3D 3'h0, // debounced outputs of pushbuttons= =09 output reg [7:0] swtch_db =3D 8'h0 // debounced outputs of slider switche= s ); parameter simulate =3D 0; // these are two ways to simulate.=20 // simulate is a parameter.=20 // what is the difference in two waits.=20 =09 localparam debounce_cnt =3D simulate ? 22'd5 // debounce clock= when simulating : 22'd4_000_000; // debounce count w= hen running on HW //shift registers used to debounce switches and buttons=09 reg [21:0] db_count =3D 22'h0; //counter for debouncer // 8 switches.=20 // 5 buttons.=20 reg [4:0] shift_pb0 =3D 5'h0, shift_pb1 =3D 5'h0, shift_pb2 =3D 5'h0, shif= t_pb3 =3D 5'h0, shift_pb4 =3D 5'h0; reg [3:0] shift_swtch0 =3D 4'h0, shift_swtch1 =3D 4'h0, shift_swtch2 =3D 4= 'h0, shift_swtch3 =3D 4'h0;=09 reg [3:0] shift_swtch4 =3D 4'h0, shift_swtch5 =3D 4'h0, shift_swtch6 = =3D 4'h0, shift_swtch7 =3D 4'h0; =09 // debounce clock // at positive edge, count is incremented always @(posedge clk) begin=20 if (db_count =3D=3D debounce_cnt) // it is 5 for simulation.=20 db_count <=3D 1'b0; //takes 40mS to reach 4,000,000 else db_count <=3D db_count + 1'b1; end =09 always @(posedge clk)=20 begin // if this always and one is line 51 race condition.=20 // if 51 runs first, then db_count will be set to szero when below conditi= on is true.=20 if (db_count =3D=3D debounce_cnt) begin //sample every 40mS //shift registers for pushbuttons // i am shifting left once and doing a bitwise OR it with 0th bit of pbt= h_in // why // what is the value in pbtn_in shift_pb0 <=3D (shift_pb0 << 1) | pbtn_in[0]; =09 shift_pb1 <=3D (shift_pb1 << 1) | pbtn_in[1]; =09 shift_pb2 <=3D (shift_pb2 << 1) | pbtn_in[2]; =09 shift_pb3 <=3D (shift_pb3 << 1) | pbtn_in[3]; shift_pb4 <=3D (shift_pb4 << 1) | pbtn_in[4];=20 =09 //shift registers for slider switches // i am doing same operation here.=20 // all these happen at same time.=20 // what is the value in switch_in shift_swtch0 <=3D (shift_swtch0 << 1) | switch_in[0]; shift_swtch1 <=3D (shift_swtch1 << 1) | switch_in[1]; shift_swtch2 <=3D (shift_swtch2 << 1) | switch_in[2]; shift_swtch3 <=3D (shift_swtch3 << 1) | switch_in[3]; shift_swtch4 <=3D (shift_swtch4 << 1) | switch_in[4]; shift_swtch5 <=3D (shift_swtch5 << 1) | switch_in[5]; shift_swtch6 <=3D (shift_swtch6 << 1) | switch_in[6]; shift_swtch7 <=3D (shift_swtch7 << 1) | switch_in[7]; end =09 //debounced pushbutton outputs // if first four bits are zero then bit zero is set to 0=20 // if first four bits are one then bit zero is set to 1 case(shift_pb0) 4'b0000: pbtn_db[0] <=3D 0; 4'b1111: pbtn_db[0] <=3D 1; e= ndcase case(shift_pb1) 4'b0000: pbtn_db[1] <=3D 0; 4'b1111: pbtn_db[1] <=3D 1; e= ndcase case(shift_pb2) 4'b0000: pbtn_db[2] <=3D 0; 4'b1111: pbtn_db[2] <=3D 1; e= ndcase case(shift_pb3) 4'b0000: pbtn_db[3] <=3D 0; 4'b1111: pbtn_db[3] <=3D 1; e= ndcase case(shift_pb4) 4'b0000: pbtn_db[4] <=3D 0; 4'b1111: pbtn_db[4] <=3D 1; e= ndcase =09 //debounced slider switch outputs case(shift_swtch0) 4'b0000: swtch_db[0] <=3D 0; 4'b1111: swtch_db[0] <= =3D 1; endcase case(shift_swtch1) 4'b0000: swtch_db[1] <=3D 0; 4'b1111: swtch_db[1] <= =3D 1; endcase case(shift_swtch2) 4'b0000: swtch_db[2] <=3D 0; 4'b1111: swtch_db[2] <= =3D 1; endcase case(shift_swtch3) 4'b0000: swtch_db[3] <=3D 0; 4'b1111: swtch_db[3] <= =3D 1; endcase=09 case(shift_swtch4) 4'b0000: swtch_db[4] <=3D 0; 4'b1111: swtch_db[4] <= =3D 1; endcase case(shift_swtch5) 4'b0000: swtch_db[5] <=3D 0; 4'b1111: swtch_db[5] <= =3D 1; endcase case(shift_swtch6) 4'b0000: swtch_db[6] <=3D 0; 4'b1111: swtch_db[6] <= =3D 1; endcase case(shift_swtch7) 4'b0000: swtch_db[7] <=3D 0; 4'b1111: swtch_db[7] <= =3D 1; endcase end // if and case happen in parallel as it is non blocking statement. right.= =20 // for simulation i am not waiting for as much as i am waiting for synthes= is.=20 endmodule From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: verilog questions Date: Sun, 06 Apr 2014 19:48:07 -0400 Organization: A noiseless patient Spider Lines: 121 Message-ID: References: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 6 Apr 2014 23:47:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="25454"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/UXCLRFoK4AKQlWTOhOcZn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <7fe4843d-15cc-4a6d-91fc-75c6354ab2b9@googlegroups.com> Cancel-Lock: sha1:SlAsgvxDGlOKWDLwOSn4esWsf1g= Xref: news.eternal-september.org comp.lang.vhdl:7428 comp.lang.verilog:3707 Not trying to be a jerk, but have you considered asking in a Verilog group? This is a VHDL group. I'm just sayin'... Tell you what, I've cross posted it for you. :) Rick On 4/6/2014 5:40 PM, sandhya pochiraju wrote: > > Hi All, I have few questions in verilog. please can someone here help me understand this. > > > Let's say, db_count = debounce_cnt at 10th positive edge. > will "IF" condition in second always block be true at 10th positive edge? > > or will "IF" condition in second always block be true at 11th positive edge? but on 11th positive edge db_count will be set to 0 by first always block. > > > what is order of operation between "IF" and "Case" ? > Though everything is in one always block and non blocking statements are used, "IF" and "Case" are two seperate blocks in themselves. Is the non-blocking behaviour of statements not confined seperately to "IF" and "Case" blocks? i.e. statements inside "IF" are non-blocking but are they non-blocking to statements inside "case" and vice versa? > > Code: > > > > `timescale 1 ns / 1 ns > module debounce ( > //inputs > // what value is stored in pbtn_in and switch_in > input clk, // clock > input [3:0] pbtn_in, // pushbutton inputs > input [7:0] switch_in, // slider switch inputs > > //outputs > output reg [3:0] pbtn_db = 3'h0, // debounced outputs of pushbuttons > output reg [7:0] swtch_db = 8'h0 // debounced outputs of slider switches > ); > parameter simulate = 0; > // these are two ways to simulate. > // simulate is a parameter. > // what is the difference in two waits. > > localparam debounce_cnt = simulate ? 22'd5 // debounce clock when simulating > : 22'd4_000_000; // debounce count when running on HW > > //shift registers used to debounce switches and buttons > reg [21:0] db_count = 22'h0; //counter for debouncer > // 8 switches. > // 5 buttons. > reg [4:0] shift_pb0 = 5'h0, shift_pb1 = 5'h0, shift_pb2 = 5'h0, shift_pb3 = 5'h0, shift_pb4 = 5'h0; > reg [3:0] shift_swtch0 = 4'h0, shift_swtch1 = 4'h0, shift_swtch2 = 4'h0, shift_swtch3 = 4'h0; > reg [3:0] shift_swtch4 = 4'h0, shift_swtch5 = 4'h0, shift_swtch6 = 4'h0, shift_swtch7 = 4'h0; > > // debounce clock > // at positive edge, count is incremented > always @(posedge clk) > begin > if (db_count == debounce_cnt) // it is 5 for simulation. > db_count <= 1'b0; //takes 40mS to reach 4,000,000 > else > db_count <= db_count + 1'b1; > end > > always @(posedge clk) > begin > // if this always and one is line 51 race condition. > // if 51 runs first, then db_count will be set to szero when below condition is true. > if (db_count == debounce_cnt) begin //sample every 40mS > //shift registers for pushbuttons > // i am shifting left once and doing a bitwise OR it with 0th bit of pbth_in > // why > // what is the value in pbtn_in > shift_pb0 <= (shift_pb0 << 1) | pbtn_in[0]; > shift_pb1 <= (shift_pb1 << 1) | pbtn_in[1]; > shift_pb2 <= (shift_pb2 << 1) | pbtn_in[2]; > shift_pb3 <= (shift_pb3 << 1) | pbtn_in[3]; > shift_pb4 <= (shift_pb4 << 1) | pbtn_in[4]; > > //shift registers for slider switches > // i am doing same operation here. > // all these happen at same time. > // what is the value in switch_in > shift_swtch0 <= (shift_swtch0 << 1) | switch_in[0]; > shift_swtch1 <= (shift_swtch1 << 1) | switch_in[1]; > shift_swtch2 <= (shift_swtch2 << 1) | switch_in[2]; > shift_swtch3 <= (shift_swtch3 << 1) | switch_in[3]; > shift_swtch4 <= (shift_swtch4 << 1) | switch_in[4]; > shift_swtch5 <= (shift_swtch5 << 1) | switch_in[5]; > shift_swtch6 <= (shift_swtch6 << 1) | switch_in[6]; > shift_swtch7 <= (shift_swtch7 << 1) | switch_in[7]; > end > > //debounced pushbutton outputs > // if first four bits are zero then bit zero is set to 0 > // if first four bits are one then bit zero is set to 1 > case(shift_pb0) 4'b0000: pbtn_db[0] <= 0; 4'b1111: pbtn_db[0] <= 1; endcase > case(shift_pb1) 4'b0000: pbtn_db[1] <= 0; 4'b1111: pbtn_db[1] <= 1; endcase > case(shift_pb2) 4'b0000: pbtn_db[2] <= 0; 4'b1111: pbtn_db[2] <= 1; endcase > case(shift_pb3) 4'b0000: pbtn_db[3] <= 0; 4'b1111: pbtn_db[3] <= 1; endcase > case(shift_pb4) 4'b0000: pbtn_db[4] <= 0; 4'b1111: pbtn_db[4] <= 1; endcase > > //debounced slider switch outputs > case(shift_swtch0) 4'b0000: swtch_db[0] <= 0; 4'b1111: swtch_db[0] <= 1; endcase > case(shift_swtch1) 4'b0000: swtch_db[1] <= 0; 4'b1111: swtch_db[1] <= 1; endcase > case(shift_swtch2) 4'b0000: swtch_db[2] <= 0; 4'b1111: swtch_db[2] <= 1; endcase > case(shift_swtch3) 4'b0000: swtch_db[3] <= 0; 4'b1111: swtch_db[3] <= 1; endcase > case(shift_swtch4) 4'b0000: swtch_db[4] <= 0; 4'b1111: swtch_db[4] <= 1; endcase > case(shift_swtch5) 4'b0000: swtch_db[5] <= 0; 4'b1111: swtch_db[5] <= 1; endcase > case(shift_swtch6) 4'b0000: swtch_db[6] <= 0; 4'b1111: swtch_db[6] <= 1; endcase > case(shift_swtch7) 4'b0000: swtch_db[7] <= 0; 4'b1111: swtch_db[7] <= 1; endcase > end > // if and case happen in parallel as it is non blocking statement. right. > // for simulation i am not waiting for as much as i am waiting for synthesis. > endmodule > -- Rick From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx30.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140406-0, 06/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 68 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396859171 86.29.12.221 (Mon, 07 Apr 2014 08:26:11 UTC) NNTP-Posting-Date: Mon, 07 Apr 2014 08:26:11 UTC Organization: virginmedia.com Date: Mon, 07 Apr 2014 09:26:11 +0100 X-Received-Body-CRC: 2284247576 X-Received-Bytes: 4197 Xref: news.eternal-september.org comp.lang.vhdl:7429 On 03/04/2014 23:21, rickman wrote: Hi Rick, > On 4/3/2014 10:22 AM, HT-Lab wrote:> On 03/04/2014 14:30, KJ wrote: > >> On Thursday, April 3, 2014 8:33:39 AM UTC-4, HT-Lab wrote: > >>>> IMHO a multicycle path delay is a propagation delay specified as > >>>> relative to the clock period. Hence it *does* depend on the clock > >>>> frequency, while the propagation through your gates does not (it > >>>> depends > >>>> on the technology). > >>> > >>> You still have your terminology wrong, here is a SDC example of an > >>> typical MCP constraint: > >>> > >>> set_multicycle_path 2 -from reg_alu* -to reg_mult* > >>> > >>> Notice there is no time, just a natural number of clock cycles. > >> > >> The value of '2' though is computed based on the clock period. Alb > >> already pointed that out earlier in the thread "If your path takes > >> 12.3 ns you would have to set a multicycle constraint of 2 with a > >> 100MHz clock, but 3 with a 200MHz one." > >> > > > > We are taking about different issues here. My argument is that you > > should not exchange a clock constraint for an MCP one, > > I think you are misreading what is intended. It is assumed there is > already a clock timing constraint of 100 MHz. That is for the general > logic in this clock domain. But for a certain section of logic the > output of the logic is not used for some number of clock cycles that > will be determined by the delay through the logic which is expected to > be longer than one clock cycle. > > The OP wants to set this number of clock cycles in the timing > constraints of that special path to verify that the P&R output will work > with the timing he has picked. If the timing fails he has the options > of working to improve the timing in the P&R or changing the logic of the > register enable to allow more clock cycles for this path. > > In no case would he want to change the timing constraint on the clock > since that constraint is set by other aspects of his design goals. > > Do I misunderstand what you are trying to say? > Yes, let me try again. What I am saying is that you should not use an MCP for a path that is not controlled. What Al seems to be doing is to use P&R to extract a path delay, he then chops it up into a number of clock delays and use that to set an MCP constraint. This create a design which will be difficult to maintain. Changing speed grade/device type/synthesis tool/version/settings/P&R settings etc will all make this process pretty painful for the next user. I also believe Al is working on some mission critical design (satellite?) so his current method will definitely fail the CDR. As suggested by others his only option is to modify the design and add e.g. output control to his FP paths, then set an MCP constraint on it and add some assertions to verify it. This should pass the CDR. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 08:55:28 GMT Lines: 55 Message-ID: References: X-Trace: individual.net 1YIqq/YQ0y8bBN1IdSEzrw73wCdrZ3rzfukwr/a9QO+WW0SYOE X-Orig-Path: not-for-mail Cancel-Lock: sha1:DdfkSRMS2WBHtgbGipHF0NCviHM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7430 Hi Rick, rickman wrote: [] > > Imagine your path between two registers (A and B) is set by another > > register C. The resulting operation is to be stored in register D. If > > you do not set a /through/ clause you will constraint each path with the > > maximum delay, which is not desirable. > > Ok, so where is the problem with specifying the through parameters if > you know them? The main problem is that I do not know them all and is a PITA to trace them. > I think uncomfortable would be an understatement. There is no other way > to properly and fully verify timing than STA. Either make it work or > find a different way to implement your design is my advice. I share your point, my manager doesn't! Ouch! [] > > The synthesis tool might optimize away (or maybe rename) certain nets > > and you're constraint will not be applicable anymore. > > If the tool optimizes away some part of your design you have problems. I > believe the renaming is done with synonyms so that a constraint should > still apply. You might want to get in touch with support. Who's parts > are you using? If a specified through target can be optimized out it > isn't a very useful feature to have in the STA tool is it? Is not only a matter of optimization, which might happen since a resource might be shared and suddenly a gate does not have the same nets' names anymore. On top of that I'm not quite familiar with synthesis tools name mangling techniques, therefore I cannot be sure the name I use for my /through/ clause will remain constant throughout several synthesis runs. I guess there are other attributes I can set to maintain certain names as they are, but the exercise becomes more and more difficult to maintain. [] > > That is why you'd be better off if you didn't have them [timing > > constraints]! > > I think of it like getting old. It is the worst thing in the world > except for the alternative. Someone said the same about democracy :-) Al p.s.: FYI I guess your Thunderbird 24.4.0 has serious issues with quoting, I'm not use if it might be related to your Win8 or a combination of the two, but your quoting is all screwed up. From newsfish@newsfish Tue Dec 29 16:43:22 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:13 GMT Lines: 14 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> <77d6bb14-5b18-4f77-af8f-f793abcccd0c@googlegroups.com> X-Trace: individual.net Unj03dpTraqwRiONIYHPKQ+YKtzipEoIPNK3tjhnl7gLvn8sox X-Orig-Path: not-for-mail Cancel-Lock: sha1:mhiTVJ4dX4J8KowVxAP8uxVCOzY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7431 Hi Kevin, KJ wrote: [] > Here is another company that seems to have a timing constraint verification product > http://www.averant.com/products-solidtc.html thanks a lot, Hans suggested me this a week or so ago. http://www.fishtail-da.com/ I hope one of them has a trial period. Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:19 GMT Lines: 61 Message-ID: References: <41ba4be6-b8ab-40fb-a527-b5ef9e921121@googlegroups.com> <956f88a1-a5e8-4e67-bdf7-6cc7c72b234d@googlegroups.com> X-Trace: individual.net Xt0mzOsqomBqPukDeHVjXAwlnrbqjjenMTLvRCh+BbpynsoYR0 X-Orig-Path: not-for-mail Cancel-Lock: sha1:DIujtbf9UJOJWbmdO+tkPCETaXs= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7432 Hi Kevin, KJ wrote: [] >> opcode path multicycle constraint >> X a + b + c -through a -through b -through c >> Y a + d + e + f -through a -through d -through e -through f >> Z q + r + t + a + d ... >> >> The rest of the constraint definition is the /from/ and /to/ clause >> which are simpler since they are the input registers and the output one. >> > > Unless you obtain a deep knowledge of the design, if you try to do > what you described above, you're likely screwed. There's always the > chance that it's not quite as bad as it appears right now, but there > is an equally good chance that it is actually worse...and you won't > know it until it's too late and you're shipping product and 'wierd' > things are happening when the board warms up or cools down or > whatever. I guess I have no choice but trace all the paths. Do port names get completely wiped out when the netlist is generated? I ask because I was thinking about using ports' names for /through/ clauses and I was wondering whether they are kept in some form on the output netlist (I'm using synplify_pro). [] >> > 3. This might actually be the best option but I don't know how well >> > it really works since I've never tried it. You can buy software that >> > claims to verify that timing constraints are correct [1] >> I was wondering if they let us try their tool for a short period of time >> (maybe a couple of weeks), enough to get ourselves out of this painful >> situation and maybe convince the management is really a must have tool. >> > > Seems like this would be your best option. Right now, you're caught > in the project management iron triangle: you don't have the right > resource (off in Brazil), you don't have schedule time to modify the > design and it sounds like management might not want to spend the $$ to > get the design correct. The only end result that will have a > functional design in this case is to punt on performance and accept > whatever slow speed you can get out of the IP core by only specifying > constraints that you know for absolute fact are correct and stop > trying to figure out if this path through this hunk really can wait a > clock or not. Uhm, that would be a show stopper. The 'hunk' limits the speed to 1/5th of the target one and this will compromise system performances beyond an acceptable level. We must constraint the 'hunk' properly. > Even if you spend the money and the tool happens to guarantee that > they will produce valid constraints, there is no guarantee that the > end performance will actually be any better...you will simply know > that you've got it properly constrained. [] A set of multicycle constraints should allow the tool to make the design meet the system clock frequency target and keep the 'hunk' running at a lower pace (through the output enable). Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification Date: 7 Apr 2014 09:00:22 GMT Lines: 36 Message-ID: References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> X-Trace: individual.net 5PXuRqkjNU0kvKV5mmUOIA7r3Hua/ytDRKvv/Yy2Ox2v9BZTUk X-Orig-Path: not-for-mail Cancel-Lock: sha1:O/QC1TwsLFjU4gohbwKgtmIAC1A= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7433 Hi Hans, HT-Lab wrote: [] >> The OP wants to set this number of clock cycles in the timing >> constraints of that special path to verify that the P&R output will work >> with the timing he has picked. If the timing fails he has the options >> of working to improve the timing in the P&R or changing the logic of the >> register enable to allow more clock cycles for this path. [] > What I am saying is that you should not use an MCP for a path that is > not controlled. What Al seems to be doing is to use P&R to extract a > path delay, he then chops it up into a number of clock delays and use > that to set an MCP constraint. Thanks for rephrasing it so clearly! > This create a design which will be > difficult to maintain. Changing speed grade/device type/synthesis > tool/version/settings/P&R settings etc will all make this process pretty > painful for the next user. I also believe Al is working on some mission > critical design (satellite?) so his current method will definitely fail > the CDR. I agree with you. This exercise will be needed every time we will change target, clock frequency, etc... We advocated for the design change path, but, as you may know, there might be other factors to consider in the equation for the best choice and only time will say if not changing the design would be the best one (even if rarely it is). > As suggested by others his only option is to modify the design and add > e.g. output control to his FP paths, then set an MCP constraint on it > and add some assertions to verify it. This should pass the CDR. How would the assertions help me in verifying it? From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.236.141.11 with SMTP id f11mr15445130yhj.54.1396862698971; Mon, 07 Apr 2014 02:24:58 -0700 (PDT) X-Received: by 10.182.44.233 with SMTP id h9mr604obm.41.1396862698803; Mon, 07 Apr 2014 02:24:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no399444qab.0!news-out.google.com!gi6ni264igc.0!nntp.google.com!ur14no3904103igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 02:24:58 -0700 (PDT) In-Reply-To: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: how to avoidind multisourcing on signal From: Thomas Stanka Injection-Date: Mon, 07 Apr 2014 09:24:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7434 Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: > How to avoi multisourcing on the signal,and bad synchronois descrption The best way is avoid it during code writing. Second best solution is to detect such issues as fast as possible. Multisourcing can be detected during compile of code, if you use no resolved signal types (only std_ulogic or std_ulogic_vector). So if you use only unresolved type you know if code can be simulated, it has no multisourcing at all. For bad synchronous description you could identify all clock domain crosings (CDC) by hand and verify their correct handling. Alternative spend money in license for tools to help in identifying and verifying of CDC. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx13.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: [cross-post]path verification References: <422676b7-ed30-4663-aee8-46cb66f276da@googlegroups.com> <19e%u.484$%U7.400@fx05.am4> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140406-0, 06/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 58 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1396865544 86.29.12.221 (Mon, 07 Apr 2014 10:12:24 UTC) NNTP-Posting-Date: Mon, 07 Apr 2014 10:12:24 UTC Organization: virginmedia.com Date: Mon, 07 Apr 2014 11:12:25 +0100 X-Received-Body-CRC: 1193679158 X-Received-Bytes: 3498 Xref: news.eternal-september.org comp.lang.vhdl:7435 On 07/04/2014 10:00, alb wrote: > Hi Hans, > > HT-Lab wrote: > [] >>> The OP wants to set this number of clock cycles in the timing >>> constraints of that special path to verify that the P&R output will work >>> with the timing he has picked. If the timing fails he has the options >>> of working to improve the timing in the P&R or changing the logic of the >>> register enable to allow more clock cycles for this path. > [] > >> What I am saying is that you should not use an MCP for a path that is >> not controlled. What Al seems to be doing is to use P&R to extract a >> path delay, he then chops it up into a number of clock delays and use >> that to set an MCP constraint. > > Thanks for rephrasing it so clearly! > >> This create a design which will be >> difficult to maintain. Changing speed grade/device type/synthesis >> tool/version/settings/P&R settings etc will all make this process pretty >> painful for the next user. I also believe Al is working on some mission >> critical design (satellite?) so his current method will definitely fail >> the CDR. > > I agree with you. This exercise will be needed every time we will change > target, clock frequency, etc... We advocated for the design change path, > but, as you may know, there might be other factors to consider in the > equation for the best choice and only time will say if not changing the > design would be the best one (even if rarely it is). > >> As suggested by others his only option is to modify the design and add >> e.g. output control to his FP paths, then set an MCP constraint on it >> and add some assertions to verify it. This should pass the CDR. > > How would the assertions help me in verifying it? > Hi Al, The assertion is on the control logic of the MCP path. Thus the assertion will fail if data can flow from your input to your output registers in less than the specified number of cycles (your MCP clock value). Look at the Fishtail link I send earlier, you might want to read up on the term sensitization before looking at the example. Good luck with your project, Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: how to avoidind multisourcing on signal Date: Mon, 07 Apr 2014 10:30:43 -0400 Organization: Alacron, Inc. Lines: 24 Message-ID: References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 7 Apr 2014 14:32:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9431"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190X6h1ZTZIVnJPubTpzGWIUgQKyTNF6vw=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:6aAIVq3cv3YBeXtpOOgJH7Hoe4U= Xref: news.eternal-september.org comp.lang.vhdl:7436 Thomas Stanka wrote: > Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: >> How to avoi multisourcing on the signal,and bad synchronois descrption > > The best way is avoid it during code writing. Second best solution is to detect such issues as fast as possible. > > Multisourcing can be detected during compile of code, if you use no resolved signal types (only std_ulogic or std_ulogic_vector). > So if you use only unresolved type you know if code can be simulated, it has no multisourcing at all. > > For bad synchronous description you could identify all clock domain crosings (CDC) by hand and verify their correct handling. Alternative spend money in license for tools to help in identifying and verifying of CDC. > > regards Thomas "multi-source" happens when you drive (assign) a signal in more than one process. Don't do that for synthesis. "bad synchronous description" is a term used by Xilinx to tell you that your sequential logic does not match a standard flip-flop template. To avoid that use the language templates to see what the synthesis tools expect. For xilinx this is available in the GUI (light bulb icon) as well as in the XST user guide. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.66.66.109 with SMTP id e13mr595259pat.1.1396926725812; Mon, 07 Apr 2014 20:12:05 -0700 (PDT) X-Received: by 10.50.25.4 with SMTP id y4mr60256igf.10.1396926725612; Mon, 07 Apr 2014 20:12:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!newsreader4.netcologne.de!news.netcologne.de!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!l13no4208181iga.0!news-out.google.com!gi6ni272igc.0!nntp.google.com!ur14no4334089igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 20:12:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=218.111.12.216; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 218.111.12.216 References: <78eb66a4-a2fa-474e-9f88-d02906c14d16@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9df171c9-0bba-43a0-aba7-90fe3bec0c98@googlegroups.com> Subject: Re: how to avoidind multisourcing on signal From: Daniel Kho Injection-Date: Tue, 08 Apr 2014 03:12:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3639 X-Received-Body-CRC: 707312435 Xref: news.eternal-september.org comp.lang.vhdl:7437 On Monday, 7 April 2014 22:30:43 UTC+8, Gabor Sz wrote: > Thomas Stanka wrote: >=20 > > Am Samstag, 5. April 2014 21:20:15 UTC+2 schrieb yogesh malekar: >=20 > >> How to avoi multisourcing on the signal,and bad synchronois descrption >=20 > >=20 >=20 > > The best way is avoid it during code writing. Second best solution is t= o detect such issues as fast as possible. >=20 > >=20 >=20 > > Multisourcing can be detected during compile of code, if you use no res= olved signal types (only std_ulogic or std_ulogic_vector). >=20 > > So if you use only unresolved type you know if code can be simulated, i= t has no multisourcing at all. >=20 > >=20 >=20 > > For bad synchronous description you could identify all clock domain cro= sings (CDC) by hand and verify their correct handling. Alternative spend mo= ney in license for tools to help in identifying and verifying of CDC.=20 >=20 > >=20 >=20 > > regards Thomas >=20 >=20 >=20 > "multi-source" happens when you drive (assign) a signal in more than >=20 > one process. Don't do that for synthesis. >=20 >=20 >=20 > "bad synchronous description" is a term used by Xilinx to tell you that >=20 > your sequential logic does not match a standard flip-flop template. To >=20 > avoid that use the language templates to see what the synthesis tools >=20 > expect. For xilinx this is available in the GUI (light bulb icon) as >=20 > well as in the XST user guide. >=20 >=20 >=20 > --=20 >=20 > Gabor Yes, like Gabor said, "multi-source" is a term used when you have multiple = drivers to a signal. If you don't intend to have multiple sources for a sig= nal (which is the case for most designs), I recommend the use of the unreso= lved VHDL types, such as std_ulogic, std_ulogic_vector, or unresolved_unsig= ned. By declaring signals to be unresolved, and if you accidentally drive t= hem from multiple sources, your simulator must give you an error. OTOH, if you use resolved types, your simulator will automatically resolve = the value of the signal as a function of all the input drivers (resolution = function). However, most synthesis tools (those that I know of) don't honour this thou= gh. They still give you an error even for a resolved signal and doesn't aut= omatically resolve the signal based on some function of its inputs. But sim= ulators are very strict in this sense. -daniel From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.58.22.70 with SMTP id b6mr406124vef.13.1396928676033; Mon, 07 Apr 2014 20:44:36 -0700 (PDT) X-Received: by 10.50.13.97 with SMTP id g1mr633927igc.0.1396928675916; Mon, 07 Apr 2014 20:44:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no225315qaj.1!news-out.google.com!gi6ni272igc.0!nntp.google.com!ur14no4341127igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Apr 2014 20:44:35 -0700 (PDT) In-Reply-To: <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=218.111.12.216; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 218.111.12.216 References: <1fa8be11-f4dc-429a-88f2-187995654382@googlegroups.com> <121818ae-9da8-4d75-a3f7-a92f92bfe92e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51188dfd-035b-4792-86d1-8068d50bd957@googlegroups.com> Subject: Re: How dofor using generate or loop for this process ? From: Daniel Kho Injection-Date: Tue, 08 Apr 2014 03:44:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3310 X-Received-Body-CRC: 441551736 Xref: news.eternal-september.org comp.lang.vhdl:7438 On Saturday, 5 April 2014 01:07:00 UTC+8, Andy wrote: > It is not clear from the example what is the index range on SelFifo, and = if that range matches the range of DataAvlble. We do know that Selfifo has = 6 bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, = but we do not know DataAvlble's index range direction. >=20 >=20 >=20 > The loop would only work if SelFifo'range is 6 downto 1. >=20 >=20 >=20 > The following would work if the index diretion of both DataAvlble and Sel= Fifo is "downto", given the correct value for DaOffset: >=20 >=20 >=20 > pSelFifo : process(Clk, SRst)=20 >=20 > constant DaOffset : integer :=3D 1; >=20 > begin=20 >=20 > if SRst =3D '1' then=20 >=20 > SelFifo <=3D (others=3D>'0');=20 >=20 > elsif rising_edge(Clk) then=20 >=20 > SelFifo <=3D (others=3D>'0');=20 >=20 > for i in SelFifo'reverse_range loop -- right to left in SelFifo >=20 > if DataAvlble(i + DaOffset) =3D '1' then=20 >=20 > SelFifo(i) <=3D '1';=20 >=20 > exit; -- prevent multiple bit set, as in original=20 >=20 > end if;=20 >=20 > end loop;=20 >=20 > end if;=20 >=20 > end process;=20 >=20 >=20 >=20 > The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop= . >=20 >=20 >=20 > Andy Something like this might just work (not tested): signal n: positive; ... pSelFifo : process(Clk, SRst) begin if SRst =3D '1' then=20 SelFifo <=3D (others=3D>'0');=20 elsif Clk'event and Clk=3D'1' then if n>6 then SelFifo <=3D (others=3D>'0'); else if DataAvlble(n) then SelFifo <=3D to_unsigned(2**(n-1),6); end if= ; end if; end if;=20 end process; Not sure though if this will synthesise. Probably not, since the expression= (2**(n-1)) is not a constant. However, this can be replaced by a shift-lef= t operation for synthesis. We could try that as well. -daniel From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: [cross-post][long] svn workflow for fpga development Date: 8 Apr 2014 07:21:22 GMT Lines: 63 Message-ID: References: <99563aff-ed56-4973-8fd3-578761768223@googlegroups.com> X-Trace: individual.net EST2KnSJwcAnSEbLbDB5tQoJlzu4j7ktiHENp28xfk+X8OvYkW X-Orig-Path: not-for-mail Cancel-Lock: sha1:PFfE0Lq9IbFSgbMyNKrGkwahS64= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:20374 comp.lang.vhdl:7439 Hi Chris, Chris Higgs wrote: [] > In my own experience, I've found it's far easier to lead by example > than battle the internal corporate structure - I soon got tired of > arguing! Leading by example is certainly far more powerful than arguing, I agree. The problem is that in an environment where your hours are counted for each activity you are carrying on it becomes obvious that I should take all these activities back home and do them on my 'spare' time. The good thing is that I find these activities quite amusing and enjoy a lot in building these kind of environment. > If the company is wedded to out-dated version control software I'll > still use git locally. There are often wrappers[1] that make > interfacing easy. I'll run GitLab to provide myself a nice HTTP > code/diff browser etc. If there's no bug-tracker(!!) I'll use GitLab > issues to track things locally. I'll certainly give a shot to git-svn, as far as code/diff browsing, I'm far too used to emacs and I consider html browsing quite cumbersome (no keyboard bindings! How can you live without key bindings!). We do have bugzilla but people are not using it effectively so there's not really a list of bugs, rather a list of 'actions' which are assigned to a specific person. In this way you have no chance to check what bugs other people have and you cannot even contribute to them (I know it sounds pretty silly!). > If the company has no regression, I'll > run a Jenkins server on my box. If tests aren't scripted, I'll spend > some time writing some Makefiles. If the tests aren't self-checking, > I'll gradually add some pass/fail criteria so the tests become useful. > I'll then start plotting graphs for things like simulation coverage, > FPGA resource utilisation etc. using Jenkins. This is my secret plan indeed, but you need to be careful though, you do not want to step on somebody else's foot! Moreover I'm not specifically asked to do so, therefore I need to sneak these activities in the middle of my 'official' ones. > > Unless you're working in an extremely restrictive environment with no > control over your development box, none of this requires sign-off from > the powers that be. You'll find other developers and then management > are suddenly curious to know how you can spot only a few minutes after > they've checked something in that the resource utilisation for their > block has doubled... or how you can say with such confidence that a > certain feature has never been tested in simulation. Once they see > the nice web interface of Jenkins and the pretty graphs, understand > the ease with which you can see what's happening in the repository, > they'll soon be asking for you to centralise your development set-up > so they can all benefit :) At least I managed to install a vbox on my windoz station and now I'm practically behind my fence ;-) > PS apologies for breaking the cross-post again... curse GG news.individual.net charges you 10$ a year... A reasonable price to get rid of GG! From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.43.14.137 with SMTP id pq9mr10092373icb.12.1397222999461; Fri, 11 Apr 2014 06:29:59 -0700 (PDT) X-Received: by 10.140.90.111 with SMTP id w102mr1130qgd.41.1397222999433; Fri, 11 Apr 2014 06:29:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no5585807iga.0!news-out.google.com!dz10ni6221qab.1!nntp.google.com!m5no863893qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Apr 2014 06:29:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.233.80.250; posting-account=PjyGrQoAAAAh4lKqW0lEgUEckVv3_YxK NNTP-Posting-Host: 41.233.80.250 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL code error From: Youssef Ahmed Injection-Date: Fri, 11 Apr 2014 13:29:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7440 Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else. my code is this: "library ieee; use ieee.std_logic_1164.all; package andpackage is component and2 is port (a, b: IN std_logic; c: OUT std_logic); end component and2; end package andpackage; entity circuit2 is port (a, b, x, y: IN std_logic; d: OUT std_logic); end entity circuit2; architecture mixed of circuit2 is for gate: and2 use entity work.and2(and2); signal c,z: std_logic; begin gate: and2 port map (a,b,c); d <= c XOR z; op: process (x,y) is begin z <= x OR y; end process op; end architecture mixed;" i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance. From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 11 Apr 2014 14:11:22 GMT Lines: 21 Message-ID: References: X-Trace: individual.net kAPNU8d57wSnqu92zbU3PQPDgX51JOXh5JUJCAK8BP/XS3axv8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:dkB1wf15xjh0VvZmMe2TV6LpiPY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7441 Hi Youssef, Youssef Ahmed wrote: [] > i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier > "std_logic"." while the 3rd just says "VHDL Compiler exiting", any > help would be greatly appreciated, thanks in advance. the information you are providing is not sufficient to spot the problem. In order to compile the code the compiler should know *where* to look for the ieee library and use the package you are referring to. Do not focus only on the code, try to see if the environment you have is setup properly. If possible, try to compile something you *know* should work (like an example from a project tutorial of your tools [1] or something you borrow from a colleague). Once you are sure your environment is properly setup then you can focus on the code. Al [1] I think long ago I did the exercise for an Orcad project, something like a Chebyshev filter...it failed miserably!! From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140411-0, 11/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 45 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397226760 86.29.12.221 (Fri, 11 Apr 2014 14:32:40 UTC) NNTP-Posting-Date: Fri, 11 Apr 2014 14:32:40 UTC Organization: virginmedia.com Date: Fri, 11 Apr 2014 15:32:39 +0100 X-Received-Body-CRC: 3128341135 X-Received-Bytes: 2206 Xref: news.eternal-september.org comp.lang.vhdl:7442 On 11/04/2014 14:29, Youssef Ahmed wrote: > Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else. > > my code is this: > "library ieee; > use ieee.std_logic_1164.all; > > package andpackage is > component and2 is > port (a, b: IN std_logic; > c: OUT std_logic); > end component and2; > end package andpackage; library ieee; use ieee.std_logic_1164.all; use work.andpackage.all; > > entity circuit2 is > port (a, b, x, y: IN std_logic; > d: OUT std_logic); > end entity circuit2; > > architecture mixed of circuit2 is -- for gate: and2 use entity work.and2(and2); > signal c,z: std_logic; > begin > gate: and2 port map (a,b,c); > d <= c XOR z; > op: process (x,y) is > begin > z <= x OR y; > end process op; > end architecture mixed;" > > i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance. > Hope this help, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.66.139.9 with SMTP id qu9mr6874912pab.41.1397228909051; Fri, 11 Apr 2014 08:08:29 -0700 (PDT) X-Received: by 10.140.20.75 with SMTP id 69mr47082qgi.17.1397228908993; Fri, 11 Apr 2014 08:08:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!border3.nntp.dca.giganews.com!nntp.giganews.com!l13no5615971iga.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no1879740qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Apr 2014 08:08:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> Subject: Re: VHDL code error From: KJ Injection-Date: Fri, 11 Apr 2014 15:08:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 13 Xref: news.eternal-september.org comp.lang.vhdl:7443 On Friday, April 11, 2014 9:29:59 AM UTC-4, Youssef Ahmed wrote: You need to place the following... library ieee;=20 use ieee.std_logic_1164.all; ...before both the package definition (where you have it now) AND before th= e entity definition. Packages and entities are considered 'primary design = units'. Any libraries you want to include must be listed prior to each one= . The 'architecture' is considered a 'secondary design unit' which does no= t need yet another round of 'library ieee...' because it has been immediate= ly preceded by the primary design unit. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 09:46:40 +0200 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Apr 2014 07:46:24 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="29540"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+pW7GBrRz6xF9WxxiqQ42q" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:jiDYLO5W40a+sxvlMPV0esXmLys= Xref: news.eternal-september.org comp.lang.vhdl:7444 Hi everybody, the question above has been come up between a colleague and me. Should the toplevel module be created as schematic plan or written as text in VHDL? I prefer the second one, my colleague the first. The only advantage I see for using schematic coding, is that I have a visual overview of my toplevel modul and I quickly can find which blocks are connected together. On the other side, the development process is much slower because of using the mouse instead of keyboard. I also think that using textfiles are much easier to handle for revision controlling software like git or svn. Maybe someone can give me a few impressions how you handle the toplevel module. Before I started my new job, we worked at CERN on very large designs with hundreds of moduls in a team with about 10 VHDL engineers. We avoided to use graphical coding and this worked excellent, so I don't see any reason, why to change this. Thanks a lot, Tobias From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 14 Apr 2014 08:56:50 GMT Lines: 50 Message-ID: References: X-Trace: individual.net t/ySa0xM1SUSFpUV1GMA4w49g7Mf1hF6apYBdmR5jD5hfgmsmV X-Orig-Path: not-for-mail Cancel-Lock: sha1:3U9mtreeyYlx8f5RlDp68dkE5aM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7445 Hi Tobias, Tobias Baumann wrote: [] > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in VHDL? After discussing with myself for quite some time I tend to avoid using schematics for two main reasons: 1. portability 2. readability No matter which tool you use as schematic entry you will certainly face some portability problem when you have to switch target if the tool chain is different. Even if you generate vhdl out of it, you cannot simply generate a schematic out of vhdl with the same level of care you did your trace routing. Text is written to be read while a schematic is drawn to be looked at. Without going to far in perception psicology, we often overestimate visual representation. On top of it, in most *nix environment you are supported by a wealth of text manipulation tools. How could you live without *grep* or *sed*. > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. use emacs speedbar to see which components are instantiated and if you did a good interface job than there's not such an added value in graphical representation. > On the other side, the development process is much slower because of > using the mouse instead of keyboard. I also think that using textfiles > are much easier to handle for revision controlling software like git or svn. > SVN handles binaries as well, but I guess that portability is more of an issue rather than revision tracking. [] > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. If you do not see any reason, why don't you ask what are the reasons to your colleague instead. It may simply be "tradition" and then you can simply forget all your reasonings. Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 13:05:50 +0200 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Apr 2014 11:05:35 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="11503"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+5vfnTZwErkypyDU5KN/5" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:EQMDpnAtPGj0jyCTYWlVWhL9Paw= Xref: news.eternal-september.org comp.lang.vhdl:7446 Am 14.04.2014 10:56, schrieb alb: > Text is written to be read while a schematic is drawn to be looked at. > Without going to far in perception psicology, we often overestimate > visual representation. I think that too, but there's the problem. Today the project leader came and wanted to see the schematic of my toplevel. So he made some trouble, because he as a none FPGA designer (but with experience in designing ASICs) wants to see a schmeatic to understand. Me as developer want to produce results, so I use textfile. If someone wants a schematic, I draw on a sheet of paper. The discussion ends up with "everybody uses schematic coding for the toplevel and it's silly to use VHDL for the toplevel". I really doubt this statement, so I started this discussion to see how others handle the toplevel. > On top of it, in most *nix environment you are supported by a wealth of text > manipulation tools. How could you live without *grep* or *sed*. > > use emacs speedbar to see which components are instantiated and if you > did a good interface job than there's not such an added value in > graphical representation. > I use Sigasi, which is perfect for me. It helps me to get quickly through a design. But even editors with VHDL highlighting are enough. It depends a bit on the quality of the source code. > If you do not see any reason, why don't you ask what are the reasons to > your colleague instead. It may simply be "tradition" and then you can > simply forget all your reasonings. The argument is, that it is standard for ASICs, so it has to be standard for FPGAs. But I think the real reason is: He wanted to see a schematic and becasue I have none he created an argument which fits his needs. Thanks a lot for sharing your opinion on this topic. From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.52.29.171 with SMTP id l11mr17305922vdh.0.1397479984989; Mon, 14 Apr 2014 05:53:04 -0700 (PDT) X-Received: by 10.140.26.77 with SMTP id 71mr1260qgu.38.1397479984947; Mon, 14 Apr 2014 05:53:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no2858986qab.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no2858985qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 05:53:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.65.126.58; posting-account=Eai9nQoAAADWhSIVdc0G4Z9jh8TwVNw0 NNTP-Posting-Host: 80.65.126.58 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00fe738d-2716-4a33-b7cc-e32a40f4ab63@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: devas Injection-Date: Mon, 14 Apr 2014 12:53:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7447 On Monday, April 14, 2014 9:46:40 AM UTC+2, Tobias Baumann wrote: > Hi everybody, > > > > the question above has been come up between a colleague and me. Should > > the toplevel module be created as schematic plan or written as text in VHDL? > > > > I prefer the second one, my colleague the first. The only advantage I > > see for using schematic coding, is that I have a visual overview of my > > toplevel modul and I quickly can find which blocks are connected together. > > Same discussion in our company. Some designers do not like schematic design (including me) and others like it and are angry when they have to made changes in your text based design. I see advantages of schematic design when you get an existing design but a good design description with some figures about the main path etc. helps a lot. > > On the other side, the development process is much slower because of > > using the mouse instead of keyboard. I also think that using textfiles > > are much easier to handle for revision controlling software like git or svn. > I agree. Text based is faster and easier to use in revision control. > > > Maybe someone can give me a few impressions how you handle the toplevel > > module. Before I started my new job, we worked at CERN on very large > > designs with hundreds of moduls in a team with about 10 VHDL engineers. > > We avoided to use graphical coding and this worked excellent, so I don't > > see any reason, why to change this. > > > > Thanks a lot, > > Tobias From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 14 Apr 2014 13:21:38 GMT Lines: 39 Message-ID: References: X-Trace: individual.net xnCiqN9Q/4MMvoljEfI8LgNBEFblje5kl128WpEBIKS83RqlU8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:Ky1z4pQStaEVI3LbU7aDJdRaEdU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7448 Hi Tobias, Tobias Baumann wrote: [] >> Text is written to be read while a schematic is drawn to be looked at. >> Without going to far in perception psicology, we often overestimate >> visual representation. > > I think that too, but there's the problem. Today the project leader came > and wanted to see the schematic of my toplevel. So he made some trouble, > because he as a none FPGA designer (but with experience in designing > ASICs) wants to see a schmeatic to understand. Me as developer want to > produce results, so I use textfile. If someone wants a schematic, I draw > on a sheet of paper. The discussion ends up with "everybody uses > schematic coding for the toplevel and it's silly to use VHDL for the > toplevel". I really doubt this statement, so I started this discussion > to see how others handle the toplevel. IIRC Quartus generates top level block level view from your top level code and a quick search 'vhdl to schematic converter' can help you out. Your project leader point might be a valid one since it reflects an habit that is difficult to fight with. You may point out what you *can* do with a text file and how much portable the resulting code might be. But "there's none so deaf as those who will not hear". >> If you do not see any reason, why don't you ask what are the reasons to >> your colleague instead. It may simply be "tradition" and then you can >> simply forget all your reasonings. > > The argument is, that it is standard for ASICs, so it has to be standard > for FPGAs. But I think the real reason is: He wanted to see a schematic > and becasue I have none he created an argument which fits his needs. Assuming he does not have an argument is not going to help you easing the dispute. Try to see if he accepts an automatically generated schematic, this will make everybody happy ;-). HTH. Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!news.astraweb.com!border6.a.newsrouter.astraweb.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx20.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140414-0, 14/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 79 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397492141 86.29.12.221 (Mon, 14 Apr 2014 16:15:41 UTC) NNTP-Posting-Date: Mon, 14 Apr 2014 16:15:41 UTC Organization: virginmedia.com Date: Mon, 14 Apr 2014 17:15:41 +0100 X-Received-Body-CRC: 2616113814 X-Received-Bytes: 4237 Xref: news.eternal-september.org comp.lang.vhdl:7449 On 14/04/2014 08:46, Tobias Baumann wrote: Hi Tobias, > Hi everybody, > > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in > VHDL? > > I prefer the second one, my colleague the first. I also prefer schematics. If you take 2 groups of engineers and you show an FSM bubble diagram to the first group and a few pages of RTL to the second, which one do you think will understand the circuit the quickest? I also know that most engineers (myself included) still draw bubble diagram and flow charts in their log book, so why not use a tool to capture that and generate some nice RTL for you. Some engineers like ASM's again this is something which is ideally suited for a graphical tool. > The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. Not only that, it can also aid debugging as most of the visual tools allow you to back annotate your simulation results onto the schematics. This makes it very easy to single step through your FSM and see what is happening. Similarly, if you have a block diagram with a number of blocks, when an assertion or breakpoint triggers you can get an immediately overview of all the signals to each block. > > On the other side, the development process is much slower because of > using the mouse instead of keyboard. Not true, I can open a new diagram in my graphical editor, drag a few components from my library, connect the similar names signals with another mouse click and finally press the generate button to create some nicely formatted VHDL or Verilog. > I also think that using textfiles > are much easier to handle for revision controlling software like git or > svn. It is true that AFAIK you can't diff a schematic. > > Maybe someone can give me a few impressions how you handle the toplevel > module. Before I started my new job, we worked at CERN on very large > designs with hundreds of moduls in a team with about 10 VHDL engineers. > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. I suspect you have never tried it. If you have a design with hundreds of modules a spreadsheet like entry method might have helped you connect them. When RTL languages came out there was also "a bit" of resistance towards them (me included as I firmly believed my Viewlogic was all I needed to design my FPGA's) and now we can't live without them. Schematic editors are useful addition to an RTL designers tool set. However, the reality is that EDA has a small user base and developing these tools cost a lot of money so not many engineers can effort them and hence their uptake is low. You mentioned in a follow-up that you are using Sigasi, have you noticed they are adding more and more graphical visualisation to their product, I am sure that graphical editing capabilities will come next. As with everything in life, "horses for courses". Regards, Hans. www.ht-lab.com > > Thanks a lot, > Tobias From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.50.51.68 with SMTP id i4mr2628582igo.5.1397493819348; Mon, 14 Apr 2014 09:43:39 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr77849qga.15.1397493819235; Mon, 14 Apr 2014 09:43:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!ur14no8027249igb.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no2924024qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 09:43:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3877de94-f08c-4e02-8f4f-9db26b93ac1b@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Mon, 14 Apr 2014 16:43:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7450 As Hans has noted, The entity needs its context defined too. In VHDL, there is no "file scope." Each design unit (entity/architecture/package/package body declaration) in a file includes the context clause (lib..., use... statements) immediately preceding the design unit. However, an architecture inherits the context of its entity, and a package body inherits the context of its package. This often leads many to mistakenly infer that a "file scope" exists for VHDL. Andy From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Mon, 14 Apr 2014 10:05:48 -0700 Organization: Highland Technology, Inc. Lines: 28 Message-ID: <20140414100548.1b134002@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="fb1f8d326b6b433116d0372735136b8e"; logging-data="28785"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PxLH7fgSScQ2f5yn/yA+F" X-Newsreader: Claws Mail 3.8.1 (GTK+ 2.24.17; x86_64-pc-linux-gnu) Cancel-Lock: sha1:oDRXMGZBY6q/9MMzL7cgn3YgRJQ= Xref: news.eternal-september.org comp.lang.vhdl:7451 On Mon, 14 Apr 2014 17:15:41 +0100 HT-Lab wrote: > I also know that most engineers (myself included) still draw bubble > diagram and flow charts in their log book, so why not use a tool to > capture that and generate some nice RTL for you. Some engineers like > ASM's again this is something which is ideally suited for a graphical tool. > Actually, I've found that I haven't drawn a straight up bubble diagram in ages, and only very rarely bother with flow charts any more. One major problem with graphical design is that you're tied to the idea that there is a "page size", rather than an infinite 2D plane. That's good, because the infinite plane very quickly explodes in complexity. But when you've got a page of finite size, then for a design above what you can visualize in your head, now you're having to span multiple pages. At that point, the continuous visualization is shot and you're back to having to mentally stitch together text tags. Easier to just write VHDL. Although for the last particularly large flowchart I really really needed I threw everyone else out of the conference room and designed the flow across the entirety of the conference table with 3 colors of Post-Its, tape, and butcher's twine. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.58.154.228 with SMTP id vr4mr21663714veb.0.1397496245841; Mon, 14 Apr 2014 10:24:05 -0700 (PDT) X-Received: by 10.140.102.136 with SMTP id w8mr112404qge.9.1397496245818; Mon, 14 Apr 2014 10:24:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no1944981qaj.1!news-out.google.com!dz10ni7240qab.1!nntp.google.com!m5no1944980qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 10:24:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: Andy Injection-Date: Mon, 14 Apr 2014 17:24:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7452 When in Rome, do as the Romans do. If your team is expecting a top level sc= hematic, you'll probably have to give it to them, at least until you can de= monstrate alternate means of giving them the "benefits" they currently thin= k they get from a top level schematic.=20 I started out using schematics a long time ago. After initially resisting V= HDL, I embraced it and would NEVER go back! I will not allow developers to use a schematic at any level to generate the= ir RTL. Schematics generate the VHDL code that may "look pretty", but machi= ne-generated VHDL is not maintainable (unless it can modify the schematic p= er RTL code changes), so you have to maintain the schematic, which then rai= ses some other questions that should be evaluated: Is the schematic tool freely distributable (not just the viewer)? Does the schematic provide for generate statements? Does the schematic provide for top-level generics? What about code comments? There are also techniques that can be used to simplify a purely structural = VHDL architecture to provide some of the understandability of a WELL-CRAFTE= D schematic. Use more complex data types than SL & SLV to group related sig= nals together (doues your schematic tool do that?) By the time the user generates symbols for each underlying component/entity= , and places them and connects them, naming each net, in a WELL CRAFTED sch= ematic, they will have spent FAR more time than writing the code. I have ye= t to see a decent "beautifier" for schematics. Plenty exist for VHDL. However, it takes a lot more than a beautifier to create human-understandab= le VHDL. Good coding standards, coding for function rather than netlist, et= c. go a long way. As previously noted, there are good tools for generating graphical document= ation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand (sci-tools) a= nd many synthesis tools.=20 Displaying single-stepped simulation results on a schematic has got to be t= he worst excuse I have ever heard! That sounds like something a marketing m= anager would want to see (or a tool vendor would talk up).=20 Andy From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.58.7.134 with SMTP id j6mr22169377vea.29.1397512161635; Mon, 14 Apr 2014 14:49:21 -0700 (PDT) X-Received: by 10.50.73.69 with SMTP id j5mr493317igv.14.1397512161382; Mon, 14 Apr 2014 14:49:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no3011862qab.0!news-out.google.com!en3ni100igc.0!nntp.google.com!ur14no8172545igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Apr 2014 14:49:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a04ce67-9ec8-4797-85ef-0087683897e0@googlegroups.com> Subject: Re: Design toplevel module as schematic? From: Dio Gratia Injection-Date: Mon, 14 Apr 2014 21:49:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5507 X-Received-Body-CRC: 3812630094 Xref: news.eternal-september.org comp.lang.vhdl:7453 On Monday, April 14, 2014 7:46:40 PM UTC+12, Tobias Baumann wrote: > Hi everybody, >=20 >=20 >=20 > the question above has been come up between a colleague and me. Should=20 >=20 > the toplevel module be created as schematic plan or written as text in VH= DL? >=20 >=20 >=20 > I prefer the second one, my colleague the first. The only advantage I=20 >=20 > see for using schematic coding, is that I have a visual overview of my=20 >=20 > toplevel modul and I quickly can find which blocks are connected together= . >=20 >=20 >=20 > On the other side, the development process is much slower because of=20 >=20 > using the mouse instead of keyboard. I also think that using textfiles=20 >=20 > are much easier to handle for revision controlling software like git or s= vn. >=20 >=20 >=20 > Maybe someone can give me a few impressions how you handle the toplevel= =20 >=20 > module. Before I started my new job, we worked at CERN on very large=20 >=20 > designs with hundreds of moduls in a team with about 10 VHDL engineers.= =20 >=20 > We avoided to use graphical coding and this worked excellent, so I don't= =20 >=20 > see any reason, why to change this. >=20 >=20 >=20 > Thanks a lot, >=20 > Tobias I once wrote a chip design methodology for implementing ASICs at a large co= rporation. If you look at a chip design process (not that different for an FPGA and an= ASIC) a design specification provides another level of abstraction view of= a design and in general is a superset after implementation of what would g= o in a data sheet. =20 You progress from the most abstract representation to the most detailed (st= ructural based on primitives) implementation. At some point your design sp= ecification is updated with pin numbers and other implementation details. A design specification is intended to represent agreement between all inter= ested parties what is intended to be (and when updated what is actually) bu= ilt. It should contain all the necessary information to interact with the t= arget device at a system or software level. Whether or not there are pictu= res in it (e.g. detailed block diagrams) can be based on whether or not a p= ictorial representation conveys more information than it occludes. Historically the purpose of providing detailed top level information would = be to show drive strengths and areas of buffers, allow annular rings to be = determined and provide a basis along with a gate count for determining die = size, leading to bonding diagrams. All that sort of goes away in FPGAs, wh= ere necessary information is generally not kept in VHDL source files, rathe= r part of a design database dependent on a particular vendor's implementati= on methodology. A design specification can add a one stop shop method of l= ocating the information no matter the implementation method. We do design entry at the behavioral level of abstraction for portability w= hich is historically higher for VHDL than Verilog. Schematic entry is likel= y to prove useless for later incorporating a design specification into an A= SIC should volumes dictate. That level of structural detail requires repli= cation in any event. The only helpful thing might be a hierarchical abstra= ction where the top level does bidirectional to single rail break out. And= that also tends to define what's in a top level detailed block diagram. Note this is implementation detail while VHDL is design entry, optionally w= ith a structural view post synthesis. It's generally not necessary in an F= PGA design flow which provides the same information through other means. In= general you don't design to the structural level instead counting on synth= esis which uses a vendor's established methodology typically not including = a structural schematic top level. Now add to that that some of us have done large pin count chip designs wher= e no matter what you do a top level schematic showing all the pins - potent= ially buffer types, signal name switches and bidirectional to single rail c= onversions becomes nothing but a glorified net list. You could also note that the objective is to build hardware not win argumen= ts. If it likely means extra work for you it ought to be justified by the desig= n process deliverables and you could always argue schedule time. From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 15 Apr 2014 07:39:39 GMT Lines: 19 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> X-Trace: individual.net qSXba9ps9n+quRLTxOn75QLDJp++yZFT9Rhu4WsERSGa3xstd2 X-Orig-Path: not-for-mail Cancel-Lock: sha1:ZhxzjbrESsBloXdI4rVbH8RjjzM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7454 Hi Kevin, KJ wrote: [] > ...before both the package definition (where you have it now) AND > before the entity definition. Packages and entities are considered > 'primary design units'. Any libraries you want to include must be > listed prior to each one. The 'architecture' is considered a > 'secondary design unit' which does not need yet another round of > 'library ieee...' because it has been immediately preceded by the > primary design unit. I'm so used to have packages and entities in separate files that I guess I forgot about library and use clause scope! But now that we are at it, what is the reason behind such a language 'feature'? I like the idea that secondary units inherit primary units' libraries and use clauses, but scoping those only to the 'first primary unit in a file' seems quite...quirk. From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.50.43.228 with SMTP id z4mr838005igl.0.1397550138205; Tue, 15 Apr 2014 01:22:18 -0700 (PDT) X-Received: by 10.140.81.166 with SMTP id f35mr11271qgd.8.1397550138173; Tue, 15 Apr 2014 01:22:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no8335284igb.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no3103586qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 01:22:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.180.251 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code error From: Thomas Stanka Injection-Date: Tue, 15 Apr 2014 08:22:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7455 Am Dienstag, 15. April 2014 09:39:39 UTC+2 schrieb alb: > I forgot about library and use clause scope! But now that we are at it, > what is the reason behind such a language 'feature'? > > I like the idea that secondary units inherit primary units' libraries > and use clauses, but scoping those only to the 'first primary unit in a > file' seems quite...quirk. Assume your design contains two packages that define the type unsigned (first is the prefered one for your design, second due to IP-usage of bad designed IP). If every primary unit would inherit from all primaries above, you could compile the design if each primary is in an individual file, but not if you combine several primary units in one file. That would be real ....quirk. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx27.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> In-Reply-To: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140414-1, 14/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 127 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397555145 86.29.12.221 (Tue, 15 Apr 2014 09:45:45 UTC) NNTP-Posting-Date: Tue, 15 Apr 2014 09:45:45 UTC Organization: virginmedia.com Date: Tue, 15 Apr 2014 10:45:43 +0100 X-Received-Body-CRC: 2829737313 X-Received-Bytes: 6718 Xref: news.eternal-september.org comp.lang.vhdl:7456 Hi Andy, On 14/04/2014 18:24, Andy wrote: > When in Rome, do as the Romans do. If your team is expecting a top level schematic, you'll probably have to give it to them, at least until you can demonstrate alternate means of giving them the "benefits" they currently think they get from a top level schematic. I can see a clear "benefit" if you have to explain your design to somebody not familiar with your design. > > I started out using schematics a long time ago. After initially resisting VHDL, I embraced it and would NEVER go back! The point is that you are not going back, tool and technology evolve and so have graphical design entry tools (although they are actually design entry and management tools to use the proper marketing term, graphics is only a small part of their capabilities). We are not talking about connecting AND/OR gate together, we are talking about parts of the design process which can benefit from schematics. > > I will not allow developers to use a schematic at any level to generate their RTL. Glad I am not working for you ;-) > Schematics generate the VHDL code that may "look pretty", but machine-generated VHDL is not maintainable (unless it can modify the schematic per RTL code changes), With modern design entry tools the sole aim is to generate perfect RTL, the output of the tool is VHDL/Verilog not schematics! The schematic is just a method to help you create your RTL. > so you have to maintain the schematic, No why? I often use my design entry tool to connect some blocks together, generate a testbench framework, or an FSM and then I continue in VHDL, this is quicker and less error prone then doing it manually. > which then raises some other questions that should be evaluated: > > Is the schematic tool freely distributable (not just the viewer)? AFAIK no, most viewers are. > Does the schematic provide for generate statements? Yes. > Does the schematic provide for top-level generics? Of course. > What about code comments? Real man don't use comments.... Clearly you have never looked at a modern (graphical) design entry tool. > > There are also techniques that can be used to simplify a purely structural VHDL architecture to provide some of the understandability of a WELL-CRAFTED schematic. Use more complex data types than SL & SLV to group related signals together (doues your schematic tool do that?) Yes, you can use records. > > By the time the user generates symbols for each underlying component/entity, and places them and connects them, naming each net, in a WELL CRAFTED schematic, they will have spent FAR more time than writing the code. Again, you should really have a look at a modern design entry tool. The symbols are generated automatically, connecting them can be done with a single mouse click. The funny thing is that I now find it very tedious to connect blocks manually, it is much quicker to let the tool do it for me. The same applies to FSM, if somebody doesn't like my n-process FSM, no problem a few mouse clicks and I have an m-process one. > I have yet to see a decent "beautifier" for schematics. yes, don't believe there are any, I have also never seen a tool that can create nice graphics from RTL no matter how expensive they are. > Plenty exist for VHDL. mmmmm, I wouldn't say plenty and the once I looked at all have issues. > > However, it takes a lot more than a beautifier to create human-understandable VHDL. Good coding standards, coding for function rather than netlist, etc. go a long way. I agree and for this reasons most design entry tools will give you a lot of options to generate the code you want, again these tools are designed to generate RTL not schematics. Some of the design entry tool also provide linting capabilities so you can check that your code is adhering to your coding standards. > > As previously noted, there are good tools for generating graphical documentation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand (sci-tools) and many synthesis tools. If you like these tools then you will be amazed what a high-end purposely designed design entry tool can do for you. Unfortunately as I mentioned in my previous post you need a healthy EDA budget to purchase them. > > Displaying single-stepped simulation results on a schematic has got to be the worst excuse I have ever heard! That sounds like something a marketing manager would want to see (or a tool vendor would talk up). So when you use your simulator (assuming Modelsim) do you use the list window or do you look at the waveform window, perhaps the FSM window or dataflow window? If you look at simulator development over the years you will see more and more graphical windows. Mentor's Questa includes a schematic window similar to what you get from a synthesis tool. The point is that graphics may help you debug your code being it by back annotating your simulation results on a block diagram or even animation of your FSM (exists). I am not advocating people should use them, I would just say use whatever works for you. I can understand why somebody might be sceptical but to re-iterate my point, these are tools to help you design your RTL, they are not moving your design into some graphical tools domain from which there is no escape. The output is always nicely formatted, readable, editable RTL as that is what they are designed for. Now back to debugging my SystemC code with printf statements.... Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 15 Apr 2014 10:14:29 GMT Lines: 20 Message-ID: References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> X-Trace: individual.net Ag9ATyPVK+0VPW46vRi2Qg4ZcJXpEMcflYpCN7fNA2lBFRraJp X-Orig-Path: not-for-mail Cancel-Lock: sha1:nAF+108SXrQcw2qUraEop19UapY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7457 Andy wrote: > As previously noted, there are good tools for generating graphical > documentation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand > (sci-tools) and many synthesis tools. there's this interesting tool out there which does not convert vhdl to schematics but does the opposite [1]. Unfortunately the developers do not want to release the code, but among the 'enhancements' they list: - ability to import VHDL or Verilog code for viewing as block-diagram. I find the GUI pretty slick and straight forward but the tool is way too rudimental and it seg. faults quite too often to be usable. Last update of the project page is 2003... :-/ The tool is distributed free of charge. Al [1] http://www.atl.external.lmco.com/projects/rassp2/vgui/index.html From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: systemC and OSVVM Date: 15 Apr 2014 10:59:30 GMT Lines: 35 Message-ID: References: X-Trace: individual.net AOKDZOtR89PKMETPppATuAPWRB3kC4zeLR/kx3Vws6VEpXjp1p X-Orig-Path: not-for-mail Cancel-Lock: sha1:rH5hXK7RhB7qU9TXhXs5kz8avL4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.arch.fpga:20451 comp.lang.vhdl:7458 My apologies, I should have really cross-posted this subthread to comp.lang.vhdl as well in the first place. alb wrote: > Hi Hans, > In comp.arch.fpga HT-Lab wrote: > [] >>> I'm considering the possibility to have my model written in SystemC >>> while the testbench written in vhdl, leveraging the benefits of the >>> OSVVM library. >> >> That is unusual, I suspect you are better off using SCV as you might hit >> some mix language interface issues (records are not always >> straightforward on a SC/VHDL interface, use simple structs on SC only). > > There are two motivations behind this choice: > > 1. our system engineer is willing to dig into systemC for architecture > exploration in the first place. We can profit of the model in order to > build our verification environment *soon* in the project. > > 2. our fpga guys are not so much willing to spend time in learning > systemC, while they could feel more confortable with the OSVVM since > they know already the language. > > The first point is a structural element that we are missing in our > design flow. Too often the architecture is based on not so well founded > choices and as the systems grow more complex, there's an increasing need > to get the architecture right at the very beginning. > > The second point is to enhance our current verification flow which is > too often lagging behind. There's an unreasonable perception that going > to the bench soon will reveal problems quicker. If we had a reference > model and a verification environment early in the project I believe we > can shift our mindset and spend less time in testing/debugging the > hardware. From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 15 Apr 2014 12:45:26 GMT Lines: 31 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> X-Trace: individual.net rQY0kyr4Y0yW6xB2L1+P6geYEhpvAZ/QYbF9oUdIiIe5OuHq66 X-Orig-Path: not-for-mail Cancel-Lock: sha1:TkLNGvVC8HWf7pT4LsgvMJC8M68= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7459 Hi Thomas, Thomas Stanka wrote: [] >> I like the idea that secondary units inherit primary units' libraries >> and use clauses, but scoping those only to the 'first primary unit in a >> file' seems quite...quirk. > > Assume your design contains two packages that define the type unsigned > (first is the prefered one for your design, second due to IP-usage of > bad designed IP). > > If every primary unit would inherit from all primaries above, you > could compile the design if each primary is in an individual file, but > not if you combine several primary units in one file. That would be > real ....quirk. I have to assume the offending type definition is not on the entity's ports, otherwise you would need a wrapper around it in order to convert the two unsigned definitions from/to eachother. Now your primary unit has no indication that a different type defintion should be used instead, hiding the subtle /feature/ in its context clause. While I see how in your case a 'file scope' for context clause would not work, I only see troubles in combining primary units in such a case. I still see it as an overhead that for each primary unit I have to have a separate context all of which are most likely the same (library ieee; use ieee.std_logic_1164.all;). Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 15 Apr 2014 12:46:50 GMT Lines: 13 Message-ID: References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> X-Trace: individual.net yMLUvyNjhNTDSQtRZMsgCQCYufU1RRN9zXM9H6srMQGPrgq9Yw X-Orig-Path: not-for-mail Cancel-Lock: sha1:ktDj2EQYbAS6jXvT1JHVz+A4A2U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7460 Hi Hans, HT-Lab wrote: [] > Now back to debugging my SystemC code with printf statements.... The greatest advantage of 'tracing' (debugging with printf) over other debugging techniques is that you are forced to *read* your code and understand it! We often brag about new tools and the power they have, simply forgetting old ones together with their values ;-) Al From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.236.188.134 with SMTP id a6mr1078998yhn.11.1397580631720; Tue, 15 Apr 2014 09:50:31 -0700 (PDT) X-Received: by 10.140.91.180 with SMTP id z49mr71255qgd.3.1397580631703; Tue, 15 Apr 2014 09:50:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no3217917qab.0!news-out.google.com!du2ni6534qab.0!nntp.google.com!cm18no3217907qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 09:50:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design toplevel module as schematic? From: Andy Injection-Date: Tue, 15 Apr 2014 16:50:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3501 X-Received-Body-CRC: 1095105221 Xref: news.eternal-september.org comp.lang.vhdl:7461 Hans,=20 Which (single) Graphical Design Entry tool provides all these features you = mention?=20 Several years ago one of our sister sites was using a Mentor graphics tool = ("HDL Designer" or something like that?) but it was very primitive. I have = not looked at it lately... perhaps I should. I am always open to new ways o= f doing things, but only if they are actually better ways! Do you only use the tool as the initial entry for the VHDL, and then mainta= in the design at the vhdl level? If so, how good is that initial schematic = after you've made maintenance modifications to the VHDL? As Dio mentioned above, many organizations believe that a schematic represe= ntation of the top (few) structural level(s) of the design eliminates the n= eed for a Design Specification (including requirements, interface specifica= tions, block diagrams, design constraints etc.) before a single block is pl= aced on a schematic, or a single line of code is written.=20 Schematic diagrams tend to be too detailed to serve as an overview, yet not= detailed enough to dismiss with reviewing/augmenting the code itself, espe= cially if the code is maintained outside the graphical environement.=20 If, on the other hand, the design is always maintained at the graphical lev= el, then you have to keep that tool around for the life of the product (whi= ch, depending on your market, may be decades longer than the tool vendor in= tends to support the tool). If my favorite VHDL editor is no longer available or supported, I can seaml= essly bring the design up in a new editor. I can't tell you how many editor= s I have used over the decades I've been designing FPGAs in VHDL, and none = of them had any problem with even the oldest code I opened in them! I take = that back... a recent new-to-me editor (IDE) tried to tell me I had a bug f= or using a reserved PSL keyword in a non-PSL context. While most IDEs will not automatically generate an acceptable block/state d= iagram (visually unorganized), many will export that diagram in an editable= form (not pixels!) for augmenting documentation.=20 BTW, Who I will work for (or allow to work for me) also has a lot to do wit= h how bad I want my paycheck! Andy From newsfish@newsfish Tue Dec 29 16:43:23 2015 X-Received: by 10.236.109.169 with SMTP id s29mr1124268yhg.43.1397582012005; Tue, 15 Apr 2014 10:13:32 -0700 (PDT) X-Received: by 10.140.97.117 with SMTP id l108mr75999qge.1.1397582011659; Tue, 15 Apr 2014 10:13:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ur14no8557234igb.0!news-out.google.com!en3ni100igc.0!nntp.google.com!ur14no8557231igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Apr 2014 10:13:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Tue, 15 Apr 2014 17:13:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7462 I have seen designs where each file contained a package, an entity and its architecture. The package contained a component declaration corresponding to the entity in that file. The instantiating architecture would use the packages associated with entities it will use, and the packages are guaranteed to be compiled if the entities are compiled. This is probably the cleanest way of keeping component declarations easily usable, yet in sync with their entities, that I have seen (if you have to use components at all.) Including, in the same file, a package with a component declaration that the architecture will/may instantiate (the OP's apparent use case) is less useful. Andy From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx22.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: <25873572-140b-4179-9a9a-4749adb15dcc@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140415-1, 15/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 58 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397644691 86.29.12.221 (Wed, 16 Apr 2014 10:38:11 UTC) NNTP-Posting-Date: Wed, 16 Apr 2014 10:38:11 UTC Organization: virginmedia.com Date: Wed, 16 Apr 2014 11:38:08 +0100 X-Received-Body-CRC: 3587807789 X-Received-Bytes: 4397 Xref: news.eternal-september.org comp.lang.vhdl:7463 Hi Andy, On 15/04/2014 17:50, Andy wrote: > Hans, > > Which (single) Graphical Design Entry tool provides all these features you mention? > > Several years ago one of our sister sites was using a Mentor graphics tool ("HDL Designer" or something like that?) but it was very primitive. I have not looked at it lately... perhaps I should. I am always open to new ways of doing things, but only if they are actually better ways! Yes, that is the one I am using. Perhaps you looked at it in the old days when it was called Renoir. Nowadays it is a (massive) design entry and management tool, graphics is just a minor part of it. > > Do you only use the tool as the initial entry for the VHDL, and then maintain the design at the vhdl level? I do both, I sometimes use the tool to prototype the structure/testbench and other times I stay within the tool for the duration of the project. I only use graphics for the top level (unless I have lots of components at a lower level), testbench and FSM's. > If so, how good is that initial schematic after you've made maintenance modifications to the VHDL? Unfortunately you can't, you can only have one master (you can however easily switch between a VHDL and schematic version for the same module). > > As Dio mentioned above, many organizations believe that a schematic representation of the top (few) structural level(s) of the design eliminates the need for a Design Specification (including requirements, interface specifications, block diagrams, design constraints etc.) before a single block is placed on a schematic, or a single line of code is written. > Schematic diagrams tend to be too detailed to serve as an overview, yet not detailed enough to dismiss with reviewing/augmenting the code itself, especially if the code is maintained outside the graphical environement. > > If, on the other hand, the design is always maintained at the graphical level, then you have to keep that tool around for the life of the product (which, depending on your market, may be decades longer than the tool vendor intends to support the tool). I agree it is never a good idea to have a design locked to a particular tool although nowadays this is becoming increasingly difficult. But this is not an issue with HDL Designer as the output is always a set of RTL files. > > If my favorite VHDL editor is no longer available or supported, I can seamlessly bring the design up in a new editor. I can't tell you how many editors I have used over the decades I've been designing FPGAs in VHDL, and none of them had any problem with even the oldest code I opened in them! I take that back... a recent new-to-me editor (IDE) tried to tell me I had a bug for using a reserved PSL keyword in a non-PSL context. Same here, my current favourite is notepad++. > > While most IDEs will not automatically generate an acceptable block/state diagram (visually unorganized), many will export that diagram in an editable form (not pixels!) for augmenting documentation. > > BTW, Who I will work for (or allow to work for me) also has a lot to do with how bad I want my paycheck! I understand, Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 17 Apr 2014 03:54:09 -0500 Date: Thu, 17 Apr 2014 09:54:05 +0100 From: MK User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 37 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-J3hp5doHKgg7wHZHUo8GTFag4fpnVyarLSgdTuF4TRf3Y2Q9XtA1WcOD0SYNmvl/kjJZh7qzg57ZLQD!fjwxJwaYgKQ3/0vlJHTiEjZtzNMAJ4ubBgfNyVsn4rj4TD8HUe2TBz2QOdmsuo/Hvz4hF9mnuY/t X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2838 Xref: news.eternal-september.org comp.lang.vhdl:7464 On 14/04/2014 08:46, Tobias Baumann wrote: > Hi everybody, > > the question above has been come up between a colleague and me. Should > the toplevel module be created as schematic plan or written as text in > VHDL? > > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected together. > > On the other side, the development process is much slower because of > using the mouse instead of keyboard. I also think that using textfiles > are much easier to handle for revision controlling software like git or > svn. > > Maybe someone can give me a few impressions how you handle the toplevel > module. Before I started my new job, we worked at CERN on very large > designs with hundreds of moduls in a team with about 10 VHDL engineers. > We avoided to use graphical coding and this worked excellent, so I don't > see any reason, why to change this. > > Thanks a lot, > Tobias I always use Aldec-HDL's schematic editor for the top level of any VHDL project - it generates perfectly readable VHDL and saves reams of tedious error prone typing, as well as providing a much more understandable high level view of the project. Most of my clients don't use VHDL so showing them 20 pages of top level net-list-like VHDL conveys absolutely nothing. A nice block diagram representation is understood by a far wider audience. Because the top level block diagram is the top level master I know it is up to date and accurate - unlike stuff in note books or other non-linked documents. Michael Kellett From newsfish@newsfish Tue Dec 29 16:43:23 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Fri, 18 Apr 2014 14:02:50 -0400 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Apr 2014 18:02:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="22013"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX197j5uBfuTSGsytXIgsNIth" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:E5DVokBxmaL51owqflFTRlYGMgc= Xref: news.eternal-september.org comp.lang.vhdl:7465 On 4/14/2014 7:05 AM, Tobias Baumann wrote: > Am 14.04.2014 10:56, schrieb alb: >> Text is written to be read while a schematic is drawn to be looked at. >> Without going to far in perception psicology, we often overestimate >> visual representation. > > I think that too, but there's the problem. Today the project leader came > and wanted to see the schematic of my toplevel. So he made some trouble, > because he as a none FPGA designer (but with experience in designing > ASICs) wants to see a schmeatic to understand. Me as developer want to > produce results, so I use textfile. If someone wants a schematic, I draw > on a sheet of paper. The discussion ends up with "everybody uses > schematic coding for the toplevel and it's silly to use VHDL for the > toplevel". I really doubt this statement, so I started this discussion > to see how others handle the toplevel. I work for myself so I have no boss over me to impose restrictions. But I can "see" a lot better than I can read through all the minutiae of a text file. A picture is worth a kiloword. Still, I never use a top level diagram for HDL. But I do draw a diagram as part of the documentation... sometimes. I used a tool many years ago that represented the requirements decomposition graphically. In the grand scheme of things it didn't work out but mostly because we had no idea how to decompose requirements rather than any limitation of the tool. However I never saw any advantage to the tool either. Manipulating the information graphically was some extra work I think and I never saw much return in the way of verification or other checking our work. :( > I use Sigasi, which is perfect for me. It helps me to get quickly > through a design. But even editors with VHDL highlighting are enough. It > depends a bit on the quality of the source code. Just like your boss is used to diagrams, code bangers are used to text tools. That is preference rather than advantage I think. >> If you do not see any reason, why don't you ask what are the reasons to >> your colleague instead. It may simply be "tradition" and then you can >> simply forget all your reasonings. > > The argument is, that it is standard for ASICs, so it has to be standard > for FPGAs. But I think the real reason is: He wanted to see a schematic > and becasue I have none he created an argument which fits his needs. What? Since when is a top level diagram standard for ASICs? I'd be willing to bet just the opposite is true. ASICs are nearly *all* HDL with no diagrams. -- Rick From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx26.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140418-0, 18/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1397848536 86.29.12.221 (Fri, 18 Apr 2014 19:15:36 UTC) NNTP-Posting-Date: Fri, 18 Apr 2014 19:15:36 UTC Organization: virginmedia.com Date: Fri, 18 Apr 2014 20:15:32 +0100 X-Received-Body-CRC: 782650341 X-Received-Bytes: 1720 Xref: news.eternal-september.org comp.lang.vhdl:7466 On 18/04/2014 19:02, rickman wrote: .. >> >> The argument is, that it is standard for ASICs, so it has to be standard >> for FPGAs. But I think the real reason is: He wanted to see a schematic >> and becasue I have none he created an argument which fits his needs. > > What? Since when is a top level diagram standard for ASICs? I'd be > willing to bet just the opposite is true. ASICs are nearly *all* HDL > with no diagrams. > I also question that, however, look at some of the comments from an relative old 2004 DeepChip postings: http://www.deepchip.com/items/dac03-07.html looks like graphics are used, Regards, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Sat, 19 Apr 2014 03:16:40 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 19 Apr 2014 07:16:19 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="25369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+GNj49aSd19kwiYNBWMN0q" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:gIrbbxzBSu3IqEOFH7zBniLxXLE= Xref: news.eternal-september.org comp.lang.vhdl:7467 On 4/18/2014 3:15 PM, HT-Lab wrote: > On 18/04/2014 19:02, rickman wrote: > .. >>> >>> The argument is, that it is standard for ASICs, so it has to be standard >>> for FPGAs. But I think the real reason is: He wanted to see a schematic >>> and becasue I have none he created an argument which fits his needs. >> >> What? Since when is a top level diagram standard for ASICs? I'd be >> willing to bet just the opposite is true. ASICs are nearly *all* HDL >> with no diagrams. >> > > I also question that, however, look at some of the comments from an > relative old 2004 DeepChip postings: > > http://www.deepchip.com/items/dac03-07.html > > looks like graphics are used, I don't follow. There are a lot of comments and many were negative regarding the schematic capture. Further, it is not clear which of these are used for FPGA and which are used for ASICs. I see no evidence that drawing schematics is "standard" for designing ASICs. -- Rick From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.236.181.74 with SMTP id k50mr12032511yhm.46.1397935151643; Sat, 19 Apr 2014 12:19:11 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr321702qge.4.1397935151625; Sat, 19 Apr 2014 12:19:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no4366643qab.0!news-out.google.com!dz10ni13939qab.1!nntp.google.com!m5no3374410qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Apr 2014 12:19:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.185.0.95; posting-account=ThB-RgoAAACC9oQPd2YxYqTJwmumn6xz NNTP-Posting-Host: 24.185.0.95 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL Synchronizer Function From: genogiapasetti@gmail.com Injection-Date: Sat, 19 Apr 2014 19:19:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1731 X-Received-Body-CRC: 1173287018 Xref: news.eternal-september.org comp.lang.vhdl:7468 Is there a way to write a VHDL synchronizer function that could be called from a section of sequential code as: if sync(clock, a) = '1' then... where "a" is a signal from another clock domain and "clock" is the clock in the present domain? I've tried function sync(clock, in: std_logic) return std_logic is variable med, result: std_logic; begin if clock'event and clock = '1' then med := input; result := med; end if; return result; end sync; The result in the Xilinx simulator is syntactically accepted but is always undefined, no matter how many variations of the above I tried. Is there a technique which preserves the convenience of my approach but works? Geno From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.67.5.165 with SMTP id cn5mr16121353pad.9.1397941239039; Sat, 19 Apr 2014 14:00:39 -0700 (PDT) X-Received: by 10.50.29.110 with SMTP id j14mr278660igh.5.1397941238688; Sat, 19 Apr 2014 14:00:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no724110igq.0!news-out.google.com!gi6ni537igc.0!nntp.google.com!c1no724108igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 19 Apr 2014 14:00:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5d470a0f-4784-4d2d-8145-a394aaee786b@googlegroups.com> Subject: Re: VHDL Synchronizer Function From: Dio Gratia Injection-Date: Sat, 19 Apr 2014 21:00:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7469 On Sunday, April 20, 2014 7:19:11 AM UTC+12, genogia...@gmail.com wrote: > Is there a way to write a VHDL synchronizer function that could be called= from a section of sequential code as: >=20 >=20 >=20 > if sync(clock, a) =3D '1' then... >=20 >=20 >=20 > where "a" is a signal from another clock domain and "clock" is the clock = in the present domain? >=20 >=20 >=20 > I've tried >=20 >=20 >=20 > function sync(clock, in: std_logic) return std_logic is >=20 > variable med, result: std_logic; >=20 > begin >=20 > if clock'event and clock =3D '1' then >=20 > med :=3D input; >=20 > result :=3D med; >=20 > end if; >=20 > return result; >=20 > end sync; >=20 >=20 >=20 >=20 >=20 > The result in the Xilinx simulator is syntactically accepted but is alway= s undefined, no matter how many variations of the above I tried. >=20 >=20 >=20 > Is there a technique which preserves the convenience of my approach but w= orks? >=20 >=20 >=20 > Geno Local variables in a function are created new each function call. Also not= e your sequential assignments of med and result don't imply a clock delay b= etween them the value of med is updated immediately. While your simulation= might work it doesn't synchronize. You could try a procedure: library ieee; use ieee.std_logic_1164.all; entity foo is end entity; architecture fum of foo is procedure sync ( signal clk: in std_logic; signal a: in std_logic; signal med: inout std_logic; signal result: inout std_logic ) is begin if clk'event and clk =3D '1' then med <=3D a; result <=3D med; end if; end ; =20 signal a: std_logic; signal clk: std_logic :=3D '0'; signal med: std_logic; signal result: std_logic; begin SYNCHRO: sync (clk,a,med,result); EVALUATE: process (result) begin if result =3D '1' then =20 end if; end process; end architecture; Notice this is the equivalent of using a sync component because a procedure= doesn't have a return value, with various restrictions on using signals in= a procedure effectively limiting this to one level of hierarchy. You might as well create a sync component and use and output signal name th= at's descriptive (e.g. a_sync). From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.182.254.10 with SMTP id ae10mr17318403obd.43.1398025626940; Sun, 20 Apr 2014 13:27:06 -0700 (PDT) X-Received: by 10.50.176.227 with SMTP id cl3mr419965igc.11.1398025626805; Sun, 20 Apr 2014 13:27:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no1231949igq.0!news-out.google.com!gi6ni537igc.0!nntp.google.com!c1no1231948igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 20 Apr 2014 13:27:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL Synchronizer Function From: Dio Gratia Injection-Date: Sun, 20 Apr 2014 20:27:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7470 You could note in your function, besides the formal 'in' in 'clock, in:' be= ing illegal (appears to have been intended to be 'clock, input:'), the form= al 'clock' hasn't been declared as class signal, meaning as class variable = (the default) the expression 'clock'event' is illegal and should result in = an error. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error Date: 22 Apr 2014 07:56:36 GMT Lines: 24 Message-ID: References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> X-Trace: individual.net gKq1/xF/x4c2fD8hxWR8MwHR0ZGpeVOWMeCIkGy/wnStD5Jpju X-Orig-Path: not-for-mail Cancel-Lock: sha1:hrLjhdVMg2M/ll+J15/sjfvsEKs= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7471 Hi Andy, Andy wrote: > I have seen designs where each file contained a package, an entity and > its architecture. The package contained a component declaration > corresponding to the entity in that file. > > The instantiating architecture would use the packages associated with > entities it will use, and the packages are guaranteed to be compiled > if the entities are compiled. the main drawback is that you end up with a package for each component, which is less useful as a package in the end. A possibility maybe is to define a 'context' (vhdl-2008) and maintain the list of packages in there. > This is probably the cleanest way of keeping component declarations > easily usable, yet in sync with their entities, that I have seen (if > you have to use components at all.) Another would be to generate a package with component declarations automatically from a list of entities. Emacs has keybindings to copy an entity declaration and paste it as a component, maybe with a little bit of lisp would be possible to generate an entire package with all necessary components in the same way. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 22 Apr 2014 03:31:56 -0500 From: rahnahnf Subject: interpolation Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 7d5ec473-520d-4a2b-812b-9c81385a79cd Message-ID: Date: Tue, 22 Apr 2014 03:31:56 -0500 Lines: 4 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-dlwIzbafPNWhcRurUtZr76Jl8JOozGHtNk5ytj+3epBVGTPWNZ9UZ5yudm7jBID8EAevmb0rLr6FjEG!RR9BHtr3PoqYUhSr9lW99VjhzV4ybQm4fqINNrbzc6s3KPKNvApX7D1cqZaXYceWYjwtUs9S27v/!yw== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1045 Xref: news.eternal-september.org comp.lang.vhdl:7472 hi, I need to code the interp2 function in Verilog.anybody have any idea about it? From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: interpolation Date: 22 Apr 2014 09:37:30 GMT Lines: 8 Message-ID: References: X-Trace: individual.net 26m8NQwKQUzi2EgCo8W9vAYIeHOzqF+ECiM+yqNdwxeI4jJUoA X-Orig-Path: not-for-mail Cancel-Lock: sha1:08zO6H1hXT3vxGgtW1pLsV7BWUU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7473 rahnahnf wrote: > I need to code the interp2 function in Verilog.anybody have any idea > about it? what about asking in the appropriate group? I give you a hint: it ends with 'verilog'. Al From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140422-0, 22/04/2014), Outbound message X-Antivirus-Status: Clean Lines: 37 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1398179175 86.29.12.221 (Tue, 22 Apr 2014 15:06:15 UTC) NNTP-Posting-Date: Tue, 22 Apr 2014 15:06:15 UTC Organization: virginmedia.com Date: Tue, 22 Apr 2014 16:06:12 +0100 X-Received-Body-CRC: 980653641 X-Received-Bytes: 2331 Xref: news.eternal-september.org comp.lang.vhdl:7474 On 19/04/2014 08:16, rickman wrote: > On 4/18/2014 3:15 PM, HT-Lab wrote: >> On 18/04/2014 19:02, rickman wrote: >> .. >>>> >>>> The argument is, that it is standard for ASICs, so it has to be >>>> standard >>>> for FPGAs. But I think the real reason is: He wanted to see a schematic >>>> and becasue I have none he created an argument which fits his needs. >>> >>> What? Since when is a top level diagram standard for ASICs? I'd be >>> willing to bet just the opposite is true. ASICs are nearly *all* HDL >>> with no diagrams. >>> >> >> I also question that, however, look at some of the comments from an >> relative old 2004 DeepChip postings: >> >> http://www.deepchip.com/items/dac03-07.html >> >> looks like graphics are used, > > I don't follow. There are a lot of comments and many were negative > regarding the schematic capture. Further, it is not clear which of > these are used for FPGA and which are used for ASICs. > > I see no evidence that drawing schematics is "standard" for designing > ASICs. > That was not the point, I agree that schematics are not standard in the ASIC world, the link was to counter your *all* argument. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!rt.uk.eu.org!border4.nntp.ams.giganews.com!backlog4.nntp.ams.giganews.com!border2.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 22 Apr 2014 15:35:19 -0500 Date: Tue, 22 Apr 2014 21:35:19 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL code error References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <0fOdnQoSvqIaT8vOnZ2dnUVZ8tednZ2d@brightview.co.uk> Lines: 35 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-2JRgKTUhAQjWxfd2XA5gc5bcpjNTexxYd0mtNtQ7KMyjDBkFPgHyzyisMRdfeXE1TNw8NYDYjm2+yDo!2DDjGI9GEsj+hjQxRelp2hky1gFTU7XJk1d0wibbCCIyxldhv4/EqWUujJXACrha2IhLBPZ9K9Zx!6T3lLoqlyqTYKlPBDbIlCyz/ZN0= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2580 Xref: news.eternal-september.org comp.lang.vhdl:7475 On 15/04/14 08:39, alb wrote: > Hi Kevin, > > KJ wrote: > [] >> ...before both the package definition (where you have it now) AND >> before the entity definition. Packages and entities are considered >> 'primary design units'. Any libraries you want to include must be >> listed prior to each one. The 'architecture' is considered a >> 'secondary design unit' which does not need yet another round of >> 'library ieee...' because it has been immediately preceded by the >> primary design unit. > > I'm so used to have packages and entities in separate files that I guess > I forgot about library and use clause scope! But now that we are at it, > what is the reason behind such a language 'feature'? > > I like the idea that secondary units inherit primary units' libraries > and use clauses, but scoping those only to the 'first primary unit in a > file' seems quite...quirk. > I think one answer is (as Microsoft always say in their knowledge base) "this behaviour is by design". I suspect the main reason is to minimise the compilation dependencies for efficiency reasons. In the early days of VHDL, I suspect that compilation time was significant while on modern computers it is not such a problem. regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.182.128.166 with SMTP id np6mr8465115obb.16.1398206888314; Tue, 22 Apr 2014 15:48:08 -0700 (PDT) X-Received: by 10.140.44.75 with SMTP id f69mr108720qga.11.1398206888281; Tue, 22 Apr 2014 15:48:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no9674355iga.0!news-out.google.com!du2ni14151qab.0!nntp.google.com!m5no4228397qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Apr 2014 15:48:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <814c36fa-9db2-464e-b882-23603ecff054@googlegroups.com> <2fa9691c-650a-489f-9d0a-413b5ba265bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57292bfb-6fd1-43f0-8a07-8a65d2cf52d7@googlegroups.com> Subject: Re: VHDL code error From: Andy Injection-Date: Tue, 22 Apr 2014 22:48:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7476 On Tuesday, April 22, 2014 2:56:36 AM UTC-5, alb wrote: > the main drawback is that you end up with a package for each component, w= hich is less useful as a package in the end.=20 Using a package that declares the component, even if it is only one compone= nt, is much easier than repeating (and maintaining!) the component declarat= ion in every architecture that instantiates it. Also, with one package per component declaration, the list of packages used= by a given architecture will be fairly small (only for those components in= stantiated in that architecture.) It also gives the reader a heads-up regar= ding which components are instantiated in the file. If either a common package containing all componentes is used, or a common = context using all the packages is employed, then anytime any one of the pac= kages/components is updated (perhaps due to its corresponding entity being = updated), everything has to be recompiled.=20 On the other hand, compilers (and the computers they run on) have gotten pr= etty fast these days, especially compared to when VHDL was first introduced= (1987)! Andy From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.236.39.99 with SMTP id c63mr25854222yhb.31.1398289771436; Wed, 23 Apr 2014 14:49:31 -0700 (PDT) X-Received: by 10.182.97.195 with SMTP id ec3mr88485obb.30.1398289771265; Wed, 23 Apr 2014 14:49:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!cm18no5805293qab.0!news-out.google.com!en3ni276igc.0!nntp.google.com!c1no2820385igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Apr 2014 14:49:31 -0700 (PDT) In-Reply-To: <48ee3cb5$0$6577$9b4e6d93@newsspool4.arcor-online.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.228.40.15; posting-account=Eve5lQoAAADdQ5XZCrU9ZCEsz1ivMYnI NNTP-Posting-Host: 41.228.40.15 References: <48ee3cb5$0$6577$9b4e6d93@newsspool4.arcor-online.net> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2f1b6829-ce57-44bd-a520-3a6d5bb73dd2@googlegroups.com> Subject: Re: Virtex-5 clocking From: salahc4@gmail.com Injection-Date: Wed, 23 Apr 2014 21:49:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7477 Le jeudi 9 octobre 2008 18:18:30 UTC+1, Saul Bernstein a =E9crit=A0: > Hi Folks, >=20 >=20 >=20 > altough brand new I hope someone already made some experience with Virtex= -5.=20 > I just switched from Virtex-4 to Virtex-5 and I must admit that the clock= =20 > managment is... and remains... somewhat unclear to me! >=20 > It's plain to see that the clock management is handled a bit differently= =20 > than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers)= =20 > technology for delay control and PLL (phased lock loop) technology for lo= wer=20 > jitter clock generation. But what does that mean to me, practically? What= =20 > should I account for when designing a PCB with Virtex-5? Which IOs am I= =20 > supposed to use? >=20 > In Virtex-4 I had Global Clock and Regional Clock Inputs. So far so good.= In=20 > Virtex-5 I have plenty of different clock inputs and it is almost impossi= ble=20 > to arrange for an optimal clock management at the time prior to developin= g=20 > the internal VHDL logic for the FPGA. Basically I'd like to know how to= =20 > connect my global clock sources to the FPGA without catching problems lat= er=20 > in implementing the VHDL and getting confronted with timing errors, etc. >=20 > Same problem - still much worse - with the RocketIO reference clocks! Ple= nty=20 > of clock inputs but. much too confusing! For example I'd like to take one= =20 > reference clock for an arrangement of 10 RocketIOs. No problem with=20 > Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 for th= e=20 > clocks can only supply 4 RocketIOs at once... as far as I can judge. >=20 >=20 >=20 > Still, I may be wrong! So any help is highly appreciated. >=20 >=20 >=20 > Saul From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.58.88.136 with SMTP id bg8mr29959006veb.21.1398290010050; Wed, 23 Apr 2014 14:53:30 -0700 (PDT) X-Received: by 10.182.158.167 with SMTP id wv7mr208838obb.29.1398290009673; Wed, 23 Apr 2014 14:53:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no4808789qaj.1!news-out.google.com!gi6ni613igc.0!nntp.google.com!l13no10241653iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 23 Apr 2014 14:53:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.228.40.15; posting-account=Eve5lQoAAADdQ5XZCrU9ZCEsz1ivMYnI NNTP-Posting-Host: 41.228.40.15 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: conv N/A _ with_Virtex5 From: Salah Kortli Injection-Date: Wed, 23 Apr 2014 21:53:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1393 X-Received-Body-CRC: 3301471314 Xref: news.eternal-september.org comp.lang.vhdl:7478 Hello world I just use a low frequency sinusoidal signals, the frequency range of alternative reports will be about 2 Hz. I want to clock the FPGA to manage the reports. I think I need to reduce or divide the frequency of the clock signals to 2 Hz to 1MHz. Then comes the use of Digital / Analog converter DAC. Is it possible to go down to values mHz. Will he links, tutorials, etc ... that guides me to it. cordially From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Thu, 24 Apr 2014 11:50:52 +0300 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 08:50:57 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4109"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CAQzoGZvIL8iIEt1WspFdAHfqonnWcKw=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:ezZPTw9ts/oerPYxc2DryK+/Ulg= Xref: news.eternal-september.org comp.lang.vhdl:7479 > I also prefer schematics. If you take 2 groups of engineers and you show > an FSM bubble diagram to the first group and a few pages of RTL to the > second, which one do you think will understand the circuit the quickest? I wonder how many people confuse top-level structure from the FSM (behavioural diagram). Might be your tools can generate nice VHDL out of Abstract State Machines. And What it has to do with the question? From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: 24 Apr 2014 09:10:45 GMT Lines: 13 Message-ID: References: X-Trace: individual.net /FFydqM2tiJxYkon3LZ9GAs52j8Nwo5IXSPy5THipYq34UEWzA X-Orig-Path: not-for-mail Cancel-Lock: sha1:y5U7lSiOFRZB4wfwwEEhf05uUZU= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7480 Hi valtih1978, valtih1978 wrote: >> I also prefer schematics. If you take 2 groups of engineers and you show >> an FSM bubble diagram to the first group and a few pages of RTL to the >> second, which one do you think will understand the circuit the quickest? > > I wonder how many people confuse top-level structure from the FSM > (behavioural diagram). Might be your tools can generate nice VHDL out of > Abstract State Machines. And What it has to do with the question? To some extent, Hans's point is about conveying information through a graphical mean rather than a listing and have the two means synchronized. IMHO his point of view is not OT. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Thu, 24 Apr 2014 15:46:44 +0300 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 12:46:49 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="24272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19cYM3VfAe05GpFyvm45pk9Aq05wsBPdWg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:080+9iW55LnAqSiXMwJaAzS8R+A= Xref: news.eternal-september.org comp.lang.vhdl:7481 I like to explain students that representation is more structural at the higher levels of abstraction. It is because you start design at the top level. You refine the design by implementing the components (defining their structure). At the bottom level you have the gates. As VHDL designer you know that components do not have the structure at the bottom level. You describe the elementary components by behavioral processes. Now, you understand that the top level is necessarily has known structure. Might be this intuition is taken too far by some bigots but the big picture of the World seems to be really useful in any case. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Separate elaboration and parsing Date: Thu, 24 Apr 2014 15:48:39 +0300 Organization: A noiseless patient Spider Lines: 14 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Apr 2014 12:48:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="24272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/w38ntwIDdfa3Uw51yyXlUR0YS0VILdPg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:hbtV9dFCndGEXfrz7wLGYmX5fhI= Xref: news.eternal-september.org comp.lang.vhdl:7482 It seems that VHDL tools separate parsing from elaboration. However, it seems that some constructions are ambigous at syntax level. For instnance, http://cs.stackexchange.com/questions/24032, target <= prefix(argument) can be treated as either element <= composite_name(10) // selecting an element or int_target <= integer(1.1) // conversion How do the tools handle this case? How do they communicate to the elaborator whether elements should be addressed or conversion function instantiated? From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.68.180.132 with SMTP id do4mr1840470pbc.4.1398360113263; Thu, 24 Apr 2014 10:21:53 -0700 (PDT) X-Received: by 10.140.97.182 with SMTP id m51mr60079qge.12.1398360113199; Thu, 24 Apr 2014 10:21:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!backlog3.nntp.dca3.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!c1no3143668igq.0!news-out.google.com!dz10ni20896qab.1!nntp.google.com!m5no5038398qaj.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Apr 2014 10:21:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Subject: Re: Separate elaboration and parsing From: KJ Injection-Date: Thu, 24 Apr 2014 17:21:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 37 X-Original-Bytes: 2318 Xref: news.eternal-september.org comp.lang.vhdl:7483 On Thursday, April 24, 2014 8:48:39 AM UTC-4, valtih1978 wrote: > It seems that VHDL tools separate parsing from elaboration. However, it= =20 >=20 > seems that some constructions are ambigous at syntax level. For=20 >=20 > instnance, http://cs.stackexchange.com/questions/24032, target <=3D=20 >=20 > prefix(argument) can be treated as either >=20 >=20 >=20 > element <=3D composite_name(10) // selecting an element >=20 >=20 >=20 > or >=20 >=20 >=20 > int_target <=3D integer(1.1) // conversion >=20 >=20 >=20 > How do the tools handle this case? How do they communicate to the=20 >=20 > elaborator whether elements should be addressed or conversion function=20 >=20 > instantiated? They don't communicate. When the names 'composite_name' and 'integer' come= across, that name must have already been defined. If they are not defined= , you get an error saying that 'composite_name' is unrecognized. If they a= re defined but you are using them incorrectly (for example by passing in an= integer argument to something that is expecting a real) then you will get = an error pointing out what you're doing wrong. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 08:10:12 +0300 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 05:10:16 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4557"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+81ayynIEydQwADUGFvCn9esYLpkf9tmc=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Cancel-Lock: sha1:RSeNiSKyZnbBZLk++Pe+HEWIxo0= Xref: news.eternal-september.org comp.lang.vhdl:7484 On 24.04.2014 20:21, KJ wrote: > They don't communicate. When the names 'composite_name' and > 'integer' come across, that name must have already been defined. If > they are not defined, you get an error saying that 'composite_name' > is unrecognized. If they are defined but you are using them > incorrectly (for example by passing in an integer argument to > something that is expecting a real) then you will get an error > pointing out what you're doing wrong. You basically say that parser does the elaboration (if "The process by which a declaration achieves its effect is called the elaboration of the declaration" is not elaboration then what is elaboration?) for the purpose of mantaining the list of defined objects and, thereby, is not related with elaboration. Try once more. That statement as it is is pure nonsense. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!backlog3.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 25 Apr 2014 01:29:27 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 25 Apr 2014 01:29:27 -0500 Lines: 41 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-F1CrvK0Ty5pm6rQiA3fi1CcVhGndbazlK/WBxm4zAlYaI5SlvP7D1iEz/r8+xKAc7TbWn+/TQ8tGDQN!8xgVv8wJwwwIwS1fz6yh5ymxyMqC74whjmssBv+voHo5T7uHHr+/Ey+em365fRYoVrQVInSYYTVr!pIXtlPxHtD/svvDHAPEx5qKgMvxuFBPbu6xh X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2857 Xref: news.eternal-september.org comp.lang.vhdl:7485 On Fri, 25 Apr 2014 08:10:12 +0300, valtih1978 wrote: > On 24.04.2014 20:21, KJ wrote: >> They don't communicate. When the names 'composite_name' and 'integer' >> come across, that name must have already been defined. If they are not >> defined, you get an error saying that 'composite_name' is unrecognized. >> If they are defined but you are using them incorrectly (for example by >> passing in an integer argument to something that is expecting a real) >> then you will get an error pointing out what you're doing wrong. > > You basically say that parser does the elaboration (if "The process by > which a declaration achieves its effect is called the elaboration of the > declaration" is not elaboration then what is elaboration?) for the > purpose of mantaining the list of defined objects and, thereby, is not > related with elaboration. Try once more. That statement as it is is pure > nonsense. Kevin is correct and does not need to try once more. The parser will have resolved any ambiguity or will have issued an error. The elaboration has all the necessary information to elaborate the definition (in your phraseology). To keep the syntax similar consider the following FORTRAN code I=C(10) Is "C" a function or array? Or consider IF(IF(10).NE.0) GOTO JAIL And yes, that is legal FORTRAN code (actually it could be IF(IF(10).NE.0)GOTOJAIL). How does the compiler know what "IF" is? The lexer/parser does not know from the BNF. It has to resolve the issue by dealing with the symbol table and then building the correct node or whatever AST type structure you are using. -- Chisolm Republic of Texas From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 13:37:57 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 10:38:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="6622"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX189b8lMS9UcWdl0ej+1Cu/wyj8JH9SuYYU=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:c6ysqjOaZHhXOMmjaOlqQSkSDYA= Xref: news.eternal-september.org comp.lang.vhdl:7486 Why Fortran? Do you know that meaning of the symbol depends on the scope? So, how many tables do you need in VHDL? Do you mean that there is a difference between elaborating the definitions and building all those tables? From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Fri, 25 Apr 2014 15:43:58 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Apr 2014 12:44:03 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="18212"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IZItDGfB2z6ReYmX8Y/htgdkLwmoPaZk=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:4uH0aOex5rnqqz+mXQ6rfE2F1wQ= Xref: news.eternal-september.org comp.lang.vhdl:7487 Particularly, parser works at per-file basis. Yet, file may refer objects defined in another file (package), which parser have no idea of. Only elaborator is aware of their nature. How do you build your symbol table without elaborating the design? From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.58.94.232 with SMTP id df8mr4519177veb.23.1398437439089; Fri, 25 Apr 2014 07:50:39 -0700 (PDT) X-Received: by 10.140.51.137 with SMTP id u9mr15222qga.34.1398437439048; Fri, 25 Apr 2014 07:50:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no5259036qaj.1!news-out.google.com!du2ni15315qab.0!nntp.google.com!cm18no6256446qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Apr 2014 07:50:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99c938f7-cbd9-4ff2-b697-20e584e042b1@googlegroups.com> Subject: Re: Separate elaboration and parsing From: KJ Injection-Date: Fri, 25 Apr 2014 14:50:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7488 On Friday, April 25, 2014 8:43:58 AM UTC-4, valtih1978 wrote: > Particularly, parser works at per-file basis. Yet, file may refer > > objects defined in another file (package), which parser have no idea of. > "which parser have no idea of"...That is not correct > Only elaborator is aware of their nature. How do you build your symbol > > table without elaborating the design? - In one word 'library'. - In two questions to guide the reader to the solution 'Where do you think the output of parsing the file ends up?' and 'What do you think then happens with that output?' Hint: The 'one word' will help you on both questions. I would be more helpful, but your misstating what I did say and then your statement to me "That statement as it is is (sic) pure nonsense" when in fact it is correct leads me to make you do some work for yourself. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 25 Apr 2014 12:36:51 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 25 Apr 2014 12:36:51 -0500 Lines: 31 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-pRRVPS9V4V04KnaCi+tDNyXG1YlDXI7Kef5vK8iseQJlpM1E/8SclfVfczk7OhwxYL1sCq4zosDsUYu!/XWl5kLWe5KnSmhz1ii+iAHRX7NZDg589V2q0u63KLjLeF6XAk8MPtxMMOLZ7m1c+DOobki8ytjv!YUrVhzOZZ4MEjxJ/UTVmmjFDCvkAhhlkjtvP X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2434 Xref: news.eternal-september.org comp.lang.vhdl:7489 On Fri, 25 Apr 2014 15:43:58 +0300, valtih1978 wrote: > Particularly, parser works at per-file basis. Yet, file may refer > objects defined in another file (package), which parser have no idea of. > Only elaborator is aware of their nature. How do you build your symbol > table without elaborating the design? Because parsing the language and actually running a sim (or building a final bit stream to program a device) are separate task. The parser takes the language and creates "object code". The "object code" is going to be in your work library or in some other library you "use". The LRM has some rules. The "object code" or other data in the library, has all the necessary information for references by other design units. I have no idea how Xilinx, Altera, or any of the other tools represent and save this data. Consider: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.my_widget_library_pkg.all; This is telling the parser where to find the definition of the symbol "to_integer" or perhaps "my_widget". Take a look at ghdl and see how they do it. -- Chisolm Republic of Texas From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Separate elaboration and parsing Date: Sat, 26 Apr 2014 09:22:12 +0300 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Apr 2014 06:22:18 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10606"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Ce1897d5d1tSNugoS93wW7u+M934GNqM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:eRZk/DMlH3g9vuc1RbYX+m5G2dM= Xref: news.eternal-september.org comp.lang.vhdl:7490 > Because parsing the language and actually running a sim (or building > a final bit stream to program a device) are separate task. Thanks for even more nonsense. > The LRM has some rules. The "object code" or LRM says that there is analyzis stage and elaboration, which check the design semantics and bind the objects. Thanks for attributing all that activity to the parser and ignoring any analysis/elaboration that perform on top of it. Since I asked about the difference between parser and elaboration, it makes a great sense to silence any analysis/elaboration and lead astray to the higher level tasks. This should be really convincing. From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Sat, 26 Apr 2014 03:47:17 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Apr 2014 07:46:49 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="46945bb1625eab38aa80926eba1ef6d5"; logging-data="2324"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/wJ0PDQrEYZeOYM89bLA0C" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:vv+a35bPup+LwnVMAQXp7MNDkjo= Xref: news.eternal-september.org comp.lang.vhdl:7491 On 4/22/2014 11:06 AM, HT-Lab wrote: > On 19/04/2014 08:16, rickman wrote: >> On 4/18/2014 3:15 PM, HT-Lab wrote: >>> On 18/04/2014 19:02, rickman wrote: >>> .. >>>>> >>>>> The argument is, that it is standard for ASICs, so it has to be >>>>> standard >>>>> for FPGAs. But I think the real reason is: He wanted to see a >>>>> schematic >>>>> and becasue I have none he created an argument which fits his needs. >>>> >>>> What? Since when is a top level diagram standard for ASICs? I'd be >>>> willing to bet just the opposite is true. ASICs are nearly *all* HDL >>>> with no diagrams. >>>> >>> >>> I also question that, however, look at some of the comments from an >>> relative old 2004 DeepChip postings: >>> >>> http://www.deepchip.com/items/dac03-07.html >>> >>> looks like graphics are used, >> >> I don't follow. There are a lot of comments and many were negative >> regarding the schematic capture. Further, it is not clear which of >> these are used for FPGA and which are used for ASICs. >> >> I see no evidence that drawing schematics is "standard" for designing >> ASICs. >> > > That was not the point, I agree that schematics are not standard in the > ASIC world, the link was to counter your *all* argument. And that is why I say "nearly" all. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.236.85.131 with SMTP id u3mr6342075yhe.40.1398530323625; Sat, 26 Apr 2014 09:38:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!cm18no6541676qab.0!news-out.google.com!dz10ni23331qab.1!nntp.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 26 Apr 2014 11:38:43 -0500 From: Joe Chisolm Subject: Re: Separate elaboration and parsing Newsgroups: comp.lang.vhdl References: <7d6e24b7-b2c7-4617-9f81-285d59257930@googlegroups.com> User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) MIME-Version: 1.0 Message-ID: Date: Sat, 26 Apr 2014 11:38:43 -0500 Lines: 25 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.195.192.194 X-Trace: sv3-zIvUBmILdtUBYuXK1etqtF/bz7MKbNYSOEn5o6+4rh3JvkqSEAOfinGcR4cUnkAuxA6I4Q01tV8KXt+!2OWm60cNSPh3sM2K8anAINZ1A/mlEBuw1lpt+ijzDMh94N6oKX/RwnQWENF9dQfC2zOe1kcQoI4N!Z8+WTDqLLRPqej9L1ZL/PlMsB56CM8OXKKLa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2349 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Received-Bytes: 2655 X-Received-Body-CRC: 1664181927 Xref: news.eternal-september.org comp.lang.vhdl:7492 On Sat, 26 Apr 2014 09:22:12 +0300, valtih1978 wrote: >> Because parsing the language and actually running a sim (or building a >> final bit stream to program a device) are separate task. > > Thanks for even more nonsense. > >> The LRM has some rules. The "object code" or > > LRM says that there is analyzis stage and elaboration, which check the > design semantics and bind the objects. Thanks for attributing all that > activity to the parser and ignoring any analysis/elaboration that > perform on top of it. Since I asked about the difference between parser > and elaboration, it makes a great sense to silence any > analysis/elaboration and lead astray to the higher level tasks. This > should be really convincing. You must be really fun to work with.... What Kevin and I were trying to *help* you with and explain is the way the major players in the industry do this with their tools. Unlike you, these people have had working tool sets for probably longer than you have been on this planet. Bye. I'm done with you. From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.43.139.66 with SMTP id iv2mr7315303icc.17.1398530771818; Sat, 26 Apr 2014 09:46:11 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr304007qgf.2.1398530771775; Sat, 26 Apr 2014 09:46:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4029090igq.0!news-out.google.com!dz10ni23056qab.1!nntp.google.com!cm18no6543039qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 26 Apr 2014 09:46:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=189.122.242.230; posting-account=u_lMxwoAAAB6CFFgDwMyXRGKYCgzWgkH NNTP-Posting-Host: 189.122.242.230 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Cache Memory From: belchel01@gmail.com Injection-Date: Sat, 26 Apr 2014 16:46:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7493 Did u get it? Em quinta-feira, 1 de dezembro de 2011 18h46min38s UTC-2, rykardu escreveu: > I'm working on a processor model written in vhdl and I'm looking for a > > model for a cache memory written in vhdl. > > > > The architecture of an embedded cache microarchitectureproposed by > > Tannenbaum. This cache must be of type copy back, set associative > > using two sets (2-way), with 64 positions, each set with a capacity to > > store blocks of 4 words of 16 bits. > > > > When a memory read is requested, the cache controller must determine > > whether it is a success or a failure and if the block stored in the > > cache is valid. If a hit, the word address must be supplied to the > > processor. If one fails, the main memory to be accessed, the cache > > should be refreshed and the bit of validity must be activated before > > the word to be supplied to the processor. > > > > When a write memory is requested, the cache controller must > > immediately determine whether it is a success or a failure. If a hit, > > the cache should be updated with the new word. If one fails, the cache > > must be updated with the new block and then the new word must be > > written in the cache. > > > > The replacement policy chooses the set of blocks that used less often. > > Only blocks that have been modified to be written back to main > > memory. > > > > This will need to add a bit of modification, indicating that that > > block was changed while in cache. The cache control is done by the > > microprogram. The main memory to the processor in question is 4K words > > of 16 bits. > > > > So, some components i have built but other not (for copy back, > > data_buffer) etc. > > > > I read here to try the website (www.gaisler.com) but 404. > > > > tks From newsfish@newsfish Tue Dec 29 16:43:24 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.cs.hut.fi!newsfeed3.funet.fi!newsfeeds.funet.fi!news.utu.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Design toplevel module as schematic? Date: Tue, 29 Apr 2014 16:22:08 +0300 Lines: 44 Message-ID: References: NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1398777728 32624 2001:708:310:3430:213:21ff:fe1b:b396 (29 Apr 2014 13:22:08 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Tue, 29 Apr 2014 13:22:08 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:Hk0jB+8QItyA3nHCLZHXWL/0Yn4= Xref: news.eternal-september.org comp.lang.vhdl:7494 Tobias Baumann writes: > I prefer the second one, my colleague the first. The only advantage I > see for using schematic coding, is that I have a visual overview of my > toplevel modul and I quickly can find which blocks are connected > together. But that kind of overview is usually provided by synthesis tools, no? Quartus does, years ago when I used Precision it did it too. Can't remember off hand if other tools can do that. > Maybe someone can give me a few impressions how you handle the > toplevel module. Once upon a time a coworker created an automated tool to build the toplevel or in fact the whole hierarchy. It operated on a simple config file and some very simple rules for connecting signals. Basically if two modules on the same level had a matching input and output those would be connected together, otherwise the signal would be pushed up in the hierarchy. It was for Verilog though and the IP is owned by Ericsson so not available for general consuption. Too bad really. But automation over tedium is my first choice. These days, as Emacs can copy a VHDL entity and paste it as an instance and signals it's fairly obvious what I prefer as an Emacs user. I had to take a look at an old hybrid schematic / VHDL design recently which was done in MaxPlus and I thought it was a filthy mess and very difficult to figure out what connected where. Of course the readability of a schematic depends on whoever did the schematic. I guess you could obfuscate a VHDL toplevel too if you really wanted to. Some years ago I was in a company where they used I think HDL Designer. It at least generated reasonable VHDL from the visual representation so portability wasn't an issue. OTOH, the GUI drawing part was pretty awful. Autosave with no undo made for a pretty terrible experience. One false move and spend hours fixing the result... Related to this, I'd like to get the top level entity and FPGA pin list from the schematic automagically. I had the pin list part once upon a time and it was great. I wonder how common this is in schematic tools? Recently I wrote a few lines of Python to convert from some kind of pin info from PADS to Quartus pin assignments. Another time years ago some other Mentor schematic tool could produce a UCF file for Xilinx. Very handy as the FPGA in that project had over 1000 pins... From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.182.104.200 with SMTP id gg8mr368208obb.45.1398812745586; Tue, 29 Apr 2014 16:05:45 -0700 (PDT) X-Received: by 10.182.142.38 with SMTP id rt6mr6698obb.10.1398812745464; Tue, 29 Apr 2014 16:05:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no511734igb.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no511730igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:05:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Subject: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:05:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7495 I want to implement a bitsplit entity but can't figure out how to get it to= work. Basically I get some input of NB_BITS_PER_CLK length and I want to b= e able to select any possible rotation of the bits. Example: Input : 010 Possible outputs depending on tap_sel: 010 100 001 Can also work if tap_sel is std_logic and every time it gets pulsed you get= a different bit arrangement. But this is streaming so it is about selectin= g the appropriate arrangement not doing x rotations. Below is what I came u= p with but sort of stuck. Help would be greatly appreciated entity capture_bitslip is generic ( NB_BITS_PER_CLK : integer :=3D 4 =20 ); port( clk : in std_logic; rst : in std_logic; tap_sel : in std_logic_vector(3 downto 0); -- 2**4 =3D 16 bits_in : in std_logic_vector(NB_BITS-1 downto 0); -- bit unaligned = comming in bits_out : out std_logic_vector(NB_BITS-1 downto 0) -- bit aligned go= ing out ); end capture_bitslip; ---------------------------------------------------------------------------= ---------- -- Architecture declaration ---------------------------------------------------------------------------= ---------- architecture Behavioral of capture_bitslip is ---------------------------------------------------------------------------= ---------- -- CONSTANTS ---------------------------------------------------------------------------= ---------- type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 dow= nto 0); ---------------------------------------------------------------------------= ---------- -- SIGNALS ---------------------------------------------------------------------------= ---------- signal delay_registers : register_tbl_type; signal data_out : std_logic_vector(NB_BITS_PER_CLK-1 downto 0); signal mux_ctrl : std_logic_vector(NB_BITS_PER_CLK-1 downto 0); --2= **5 =3D 32 --*************************************************************************= ********** begin --*************************************************************************= ********** --generate_pattern_table:=20 for X in 0 to NB_BITS_PER_CLK-1 generate pattern_table(X) <=3D unsigned(bit_in) ror X; end generate; bit_out <=3D pattern_table(tap_sel); From newsfish@newsfish Tue Dec 29 16:43:24 2015 X-Received: by 10.58.228.201 with SMTP id sk9mr403077vec.35.1398813144261; Tue, 29 Apr 2014 16:12:24 -0700 (PDT) X-Received: by 10.182.33.4 with SMTP id n4mr6017obi.9.1398813144147; Tue, 29 Apr 2014 16:12:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no108971qab.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no512837igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:12:23 -0700 (PDT) In-Reply-To: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 References: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:12:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7496 ------------------------------------------------------------------------------------- -- Specified libraries ------------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------------- -- Entity declaration ------------------------------------------------------------------------------------- entity capture_bitslip is generic ( NB_BITS_PER_CLK : integer := 4 ); port( clk : in std_logic; rst : in std_logic; delay_sel : in std_logic_vector(3 downto 0); -- 2**4 = 16 bits_in : in std_logic_vector(NB_BITS_PER_CLK-1 downto 0); -- bit unaligned comming in bits_out : out std_logic_vector(NB_BITS_PER_CLK-1 downto 0) -- bit aligned going out ); end capture_bitslip; ------------------------------------------------------------------------------------- -- Architecture declaration ------------------------------------------------------------------------------------- architecture Behavioral of capture_bitslip is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type register_tbl_type is array (0 to 15) of unsigned(NB_BITS_PER_CLK-1 downto 0); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal delay_registers : register_tbl_type; --*********************************************************************************** begin --*********************************************************************************** generate_pattern_table: for X in 0 to NB_BITS_PER_CLK-1 generate delay_registers(X) <= unsigned(bits_in) ror X; end generate; bits_out <= delay_registers(delay_sel); From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.50.108.47 with SMTP id hh15mr475836igb.3.1398813561363; Tue, 29 Apr 2014 16:19:21 -0700 (PDT) X-Received: by 10.182.1.202 with SMTP id 10mr4891obo.31.1398813561229; Tue, 29 Apr 2014 16:19:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no514137igb.0!news-out.google.com!en3ni366igc.0!nntp.google.com!uq10no514132igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Apr 2014 16:19:20 -0700 (PDT) In-Reply-To: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=24.242.131.190; posting-account=z0BiiAoAAABd_vM40LOrWNyVczlX5yAG NNTP-Posting-Host: 24.242.131.190 References: <4e5ca130-1981-45f3-8dac-6c1a94b6614f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ee3c29c-34de-438b-8612-12ef14b933ad@googlegroups.com> Subject: Re: code question From: sk3ptic@gmail.com Injection-Date: Tue, 29 Apr 2014 23:19:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7497 Finally came up with this. Is this synthesizable and can anyone think of a better way to do it? generate_pattern_table: for X in 0 to NB_BITS_PER_CLK-1 generate delay_registers(X) <= unsigned(bits_in) ror X; end generate; data <= delay_registers(to_integer(unsigned(delay_sel))); bits_out <= std_logic_vector(data); From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.182.28.99 with SMTP id a3mr5476581obh.40.1398942743320; Thu, 01 May 2014 04:12:23 -0700 (PDT) X-Received: by 10.140.101.107 with SMTP id t98mr196796qge.5.1398942743251; Thu, 01 May 2014 04:12:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!l13no12469473iga.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no314334qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 04:12:23 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.232.223.221; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 85.232.223.221 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 01 May 2014 11:12:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7498 Hi, I have managed to transmit some character (one after the other) using this code from; http://eewiki.net/pages/viewpage.action?pageId=4096096 I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? I am planning to interface with MAX1416 ADC. Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? Shall I use the same method I used for transmitting but this time in the test bench? I am using quartus and ModelSim. thanks From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.236.66.169 with SMTP id h29mr4855666yhd.34.1398943067377; Thu, 01 May 2014 04:17:47 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr46qga.15.1398943067191; Thu, 01 May 2014 04:17:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border4.nntp.dca.giganews.com!backlog4.nntp.dca3.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!s7no314949qap.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no314945qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 04:17:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.232.223.221; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 85.232.223.221 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <625d4289-c200-478b-9a34-76ff8d1dfb41@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 01 May 2014 11:17:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 X-Original-Bytes: 1222 Xref: news.eternal-september.org comp.lang.vhdl:7499 https://dl.dropboxusercontent.com/u/34708989/SPI_tx_test.bmp From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: SPI; simulating an input (rx) Date: Thu, 01 May 2014 09:10:55 -0400 Organization: Alacron, Inc. Lines: 32 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 May 2014 13:11:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="17959"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XBF7SuJ/kNaFentJJwXK121AnFfNEev0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:WVN+A55T3JUfpyXCNLhHAwFZgKU= Xref: news.eternal-september.org comp.lang.vhdl:7500 Brandon Spiteri wrote: > Hi, > I have managed to transmit some character (one after the other) using this code from; > > http://eewiki.net/pages/viewpage.action?pageId=4096096 > > I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? > > I am planning to interface with MAX1416 ADC. > > > Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? > > Shall I use the same method I used for transmitting but this time in the test bench? > > I am using quartus and ModelSim. > > thanks From your screen-shot, it looks like the high-Z occurs when the receiver is not looking at the data, so it should be OK. On the other hand it might be a good idea to go through your code to see why that's happening. As for simulating data in the opposite direction, there's no reason you can't instantiate a synthesizable module from the testbench to provide stimulus. That assumes of course that the module behaves the way you expect the ADC to behave. Have checked whether Maxim (or whoever makes the ADC) has a simulation model? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.236.39.99 with SMTP id c63mr5771284yhb.31.1398963310294; Thu, 01 May 2014 09:55:10 -0700 (PDT) X-Received: by 10.140.94.169 with SMTP id g38mr29508qge.13.1398963310232; Thu, 01 May 2014 09:55:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s7no385026qap.0!news-out.google.com!du2ni19614qab.0!nntp.google.com!ih12no1422650qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 09:55:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.227.212.2; posting-account=VXDpvQoAAAB9FwBy5EHXKCikwLvVmTDX NNTP-Posting-Host: 88.227.212.2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Subject: Re: how create an 8 bit binary to BCD decoder? From: emirogluengin@gmail.com Injection-Date: Thu, 01 May 2014 16:55:10 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7501 15 May=C4=B1s 2002 =C3=87ar=C5=9Famba 23:07:03 UTC+3 tarihinde Christian ya= zd=C4=B1: > Hello! > I know this newsgroup is specially ybout VHDL. But I am curently working > with Altera's derivation AHDL. > My question isn't quite language related but more general: >=20 > How would you create a decoder which generates BCD-coding from normal 8bi= t > binary coding? > I want to control several 7 segment displays and therefore have to use BC= D > coding. >=20 > I'd be very happy to get any kind of help. > Regards > Chris. From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.50.136.198 with SMTP id qc6mr1851248igb.4.1398964754323; Thu, 01 May 2014 10:19:14 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr234116qgr.0.1398964754255; Thu, 01 May 2014 10:19:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no212075igq.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no390229qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 10:19:13 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.191.171.253; posting-account=x2hcxAoAAADSdaw31IXuu3z4q8DZR-f9 NNTP-Posting-Host: 2.191.171.253 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: meyasm.masoudi@gmail.com Injection-Date: Thu, 01 May 2014 17:19:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7502 hi would you please tell me if you have solution for "wireless communication" by Andrea GoldSmith. From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.66.233.65 with SMTP id tu1mr6068230pac.35.1398964919535; Thu, 01 May 2014 10:21:59 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr231932qge.4.1398964919447; Thu, 01 May 2014 10:21:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!l13no12563420iga.0!news-out.google.com!dz10ni27706qab.1!nntp.google.com!s7no391218qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 May 2014 10:21:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.191.163.181; posting-account=x2hcxAoAAADSdaw31IXuu3z4q8DZR-f9 NNTP-Posting-Host: 2.191.163.181 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7954a117-8f3b-4d25-8b8f-16ada31a1525@googlegroups.com> Subject: Re: instructor solution manual for Wireless Communications (Andrea Goldsmith) From: meyasm.masoudi@gmail.com Injection-Date: Thu, 01 May 2014 17:21:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7503 hi would you please tell me if you have solution for "wireless communication" by Andrea GoldSmith. From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.182.186.103 with SMTP id fj7mr13414220obc.9.1399154538788; Sat, 03 May 2014 15:02:18 -0700 (PDT) X-Received: by 10.140.50.83 with SMTP id r77mr1302qga.15.1399154538764; Sat, 03 May 2014 15:02:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no1089421igq.0!news-out.google.com!dz10ni30394qab.1!nntp.google.com!hw13no149173qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 May 2014 15:02:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.87.120; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.87.120 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Sat, 03 May 2014 22:02:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7504 > > > > From your screen-shot, it looks like the high-Z occurs when the receiver > > is not looking at the data, so it should be OK. On the other hand it > > might be a good idea to go through your code to see why that's > > happening. > > > > As for simulating data in the opposite direction, there's no reason you > > can't instantiate a synthesizable module from the testbench to provide > > stimulus. That assumes of course that the module behaves the way you > > expect the ADC to behave. Have checked whether Maxim (or whoever makes > > the ADC) has a simulation model? > > > > -- > > Gabor Thanks for your reply Gabor, I looked in the datasheet of the ADC but there wasn't much SPI waveforms to check with. Do you have any idea where can I look for a valid waveform example for MAX1416 please? From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.58.105.105 with SMTP id gl9mr12697759veb.17.1399155480317; Sat, 03 May 2014 15:18:00 -0700 (PDT) X-Received: by 10.182.220.232 with SMTP id pz8mr158657obc.13.1399155479938; Sat, 03 May 2014 15:17:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!ih12no256349qab.1!news-out.google.com!gi6ni725igc.0!nntp.google.com!c1no1094917igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 May 2014 15:17:59 -0700 (PDT) In-Reply-To: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <82185e7b-b9ef-45a1-b863-68b1d0751049@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <676744df-2796-4ae0-963f-932eb0ac857e@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Sat, 03 May 2014 22:17:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1505 X-Received-Body-CRC: 3893919415 Xref: news.eternal-september.org comp.lang.vhdl:7505 On Saturday, May 3, 2014 6:02:18 PM UTC-4, Brandon Spiteri wrote: > Thanks for your reply Gabor, I looked in the datasheet of the ADC but there > wasn't much SPI waveforms to check with. Do you have any idea where can I look > for a valid waveform example for MAX1416 please? Datasheet, page 23 KJ From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.43.31.81 with SMTP id sf17mr14988452icb.4.1399288061289; Mon, 05 May 2014 04:07:41 -0700 (PDT) X-Received: by 10.140.51.70 with SMTP id t64mr17388qga.23.1399288061218; Mon, 05 May 2014 04:07:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!c1no1604806igq.0!news-out.google.com!dz10ni30394qab.1!nntp.google.com!hw13no445551qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 May 2014 04:07:40 -0700 (PDT) In-Reply-To: <8opbg4$gl7$1@news1.skynet.be> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.27.69.217; posting-account=66RXwAoAAAASPYbdczIbUgB22XjTHa0z NNTP-Posting-Host: 212.27.69.217 References: <8oilkh$g22$1@soap.pipex.net> <8opbg4$gl7$1@news1.skynet.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8020210a-f957-481c-8088-256effbcb73d@googlegroups.com> Subject: Re: VHDL Syntax Highlighting in MS Visual Studio From: markus.ferringer@gmail.com Injection-Date: Mon, 05 May 2014 11:07:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7506 I realize that this is a rather old thread, but it's still one of the first Google search results, so I think it's worth a note here. On www.vide-software.at (or directly from Visual Studio's Extension Manager) you can download an extension for Visual Studio. It offers syntax & semantic highlighting, code completion, code snippets, enhanced navigation features, etc. etc. It's free for students & teachers, there is a 30-day trial license, and there is a rather cheap private license for non-commercial use. Regards, Markus From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.236.123.68 with SMTP id u44mr696981yhh.19.1399373552148; Tue, 06 May 2014 03:52:32 -0700 (PDT) X-Received: by 10.182.200.163 with SMTP id jt3mr84229obc.25.1399373551755; Tue, 06 May 2014 03:52:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no686572qab.0!news-out.google.com!qf4ni19igc.0!nntp.google.com!c1no1987803igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 03:52:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.177.216.253; posting-account=V5rwAwoAAABbcDl8qd8AM9dp1Lh1besi NNTP-Posting-Host: 122.177.216.253 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Subject: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: ajit yadav Injection-Date: Tue, 06 May 2014 10:52:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1644 X-Received-Body-CRC: 4019351138 Xref: news.eternal-september.org comp.lang.vhdl:7507 Fast Fourier transform(FFT) is used in digital spectral analysis, filter si= mulations, autocorrelation and pattern recognition applications. The FFT is= based on decomposition and breaking the transform into smaller transforms = and combining them to get the total transform. The FFT reduces the computat= ion time required to compute a discrete Fourier transform and thus improves= speed of computation. The speed of computation can be further enhanced by = the use of distributive Arithmetic (DA) method. DA method is very efficient= in terms of speed and accuracy. pLEASE HELP ME TO WRITE FPGA CODE From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.236.209.97 with SMTP id r61mr751717yho.33.1399373582047; Tue, 06 May 2014 03:53:02 -0700 (PDT) X-Received: by 10.182.72.228 with SMTP id g4mr265361obv.14.1399373581844; Tue, 06 May 2014 03:53:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hw13no686709qab.0!news-out.google.com!qf4ni19igc.0!nntp.google.com!c1no1987891igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 03:53:01 -0700 (PDT) In-Reply-To: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.177.216.253; posting-account=V5rwAwoAAABbcDl8qd8AM9dp1Lh1besi NNTP-Posting-Host: 122.177.216.253 References: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66413fd0-e4b8-4912-bd14-e101e687c2db@googlegroups.com> Subject: Re: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: ajit yadav Injection-Date: Tue, 06 May 2014 10:53:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1904 X-Received-Body-CRC: 2049408777 Xref: news.eternal-september.org comp.lang.vhdl:7508 On Tuesday, May 6, 2014 4:22:31 PM UTC+5:30, ajit yadav wrote: > Fast Fourier transform(FFT) is used in digital spectral analysis, filter = simulations, autocorrelation and pattern recognition applications. The FFT = is based on decomposition and breaking the transform into smaller transform= s and combining them to get the total transform. The FFT reduces the comput= ation time required to compute a discrete Fourier transform and thus improv= es speed of computation. The speed of computation can be further enhanced b= y the use of distributive Arithmetic (DA) method. DA method is very efficie= nt in terms of speed and accuracy. pLEASE HELP ME WRITE VHDL CODE >=20 >=20 >=20 > pLEASE HELP ME TO WRITE FPGA CODE From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.50.43.228 with SMTP id z4mr1166525igl.0.1399383682678; Tue, 06 May 2014 06:41:22 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr139192qge.10.1399383682650; Tue, 06 May 2014 06:41:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no2055352igq.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no836810qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 06:41:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.83; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.83 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: erreur VHDL From: Ayoub Injection-Date: Tue, 06 May 2014 13:41:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7509 Hello! In fact,i have a small problem but I don't understand what I should do here is my code: library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_signed .all ; entity M is port( clk : in std_logic ; rst : in std_logic ; data : in std_ulogic_vector(1 downto 0); CD : in std_logic_vector(3 downto 0); s : out std_logic_vector (1 downto 0)); end entity ; architecture beh of M is signal com :std_logic_vector(3 downto 0); begin code :process(clk,rst) begin if (rst='1') then (others=>'0')<=data; --data<='0' !!! ; (others=>'0')<=CD; --"0000"<=CD ; s <=(others=>'0'); else for i in 0 to 3 loop if (clk'event and clk='1')then --for i in 0 to 3 loop com(i)<= not(CD(i) xor data) ; end if ; end loop ; end if ; end process ; s<=com(i) ; end architecture ; This is my problem : """Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type""" Thanks in advanced. From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL Date: Tue, 06 May 2014 16:44:52 +0200 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 6 May 2014 14:44:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="30411"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18x7evCHuQD+lbEJV+PLItL" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: Cancel-Lock: sha1:MwQC3MzC0yEyyIz1r0uKzYSIbLY= Xref: news.eternal-september.org comp.lang.vhdl:7510 Am 06.05.2014 15:41, schrieb Ayoub: > com(i)<= not(CD(i) xor data) ; Check this line. What type/size has data and compare it with type/size of CD(i). Tobias From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.182.213.5 with SMTP id no5mr1297069obc.15.1399388526100; Tue, 06 May 2014 08:02:06 -0700 (PDT) X-Received: by 10.140.109.203 with SMTP id l69mr13152qgf.32.1399388526034; Tue, 06 May 2014 08:02:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r10no1173357igi.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no862914qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 08:02:05 -0700 (PDT) In-Reply-To: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <5f12afb9-e2de-4615-a665-b79b428dc510@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5280f381-ab42-4338-924f-3bdb221c32b3@googlegroups.com> Subject: Re: FFT CALCULATION USING DISTRIBUTIVE ALGORITHM. From: KJ Injection-Date: Tue, 06 May 2014 15:02:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7511 On Tuesday, May 6, 2014 6:52:31 AM UTC-4, ajit yadav wrote: > Fast Fourier transform(FFT) is used in digital spectral analysis, filter > pLEASE HELP ME TO WRITE FPGA CODE 1. Post your code so somebody can help. 2. If you have no code, then you should write some and start debugging. When you run across a problem, then go back to step 1. KJ From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.58.22.166 with SMTP id e6mr1370312vef.6.1399388757267; Tue, 06 May 2014 08:05:57 -0700 (PDT) X-Received: by 10.140.49.234 with SMTP id q97mr53655qga.22.1399388757187; Tue, 06 May 2014 08:05:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no760889qab.0!news-out.google.com!dz10ni33449qab.1!nntp.google.com!ih12no863871qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 08:05:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <41caf9be-1f3d-4e40-9f50-3c3da0bd02a5@googlegroups.com> Subject: Re: erreur VHDL From: KJ Injection-Date: Tue, 06 May 2014 15:05:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7512 On Tuesday, May 6, 2014 9:41:22 AM UTC-4, Ayoub wrote: > com(i)<= not(CD(i) xor data) ; should be com(i)<= not(CD(i) xor std_logic_vector(data)) ; Or compile the file using VHDL-2008 syntax. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!nntp.giganews.com!news.osn.de!diablo2.news.osn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL Date: Tue, 06 May 2014 17:53:28 +0200 Lines: 95 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net z3MvLpw+IHKWvKmzoHHDFAtQ494riJW6JNEByjcnTqeame4SkH Cancel-Lock: sha1:FdOWKHQyWXS/yHi04zjKHp0F7PY= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:7513 Hi Ayoub, Ayoub wrote: > Hello! > > In fact,i have a small problem but I don't understand what I should do there's a few problems that should cause compilation errors, not only one. > here is my code: > > library ieee ; > use ieee.std_logic_1164.all ; > use ieee.std_logic_signed .all ; Get used to never using ieee.std_logic_signed.all. Use ieee.numeric_std.all instead and use the signed/unsigned types as needed. > > entity M is > port( > clk : in std_logic ; > rst : in std_logic ; > data : in std_ulogic_vector(1 downto 0); > CD : in std_logic_vector(3 downto 0); > s : out std_logic_vector (1 downto 0)); > > end entity ; > > architecture beh of M is > > signal com :std_logic_vector(3 downto 0); > > begin > > code :process(clk,rst) > > begin > > if (rst='1') then > (others=>'0')<=data; This line should cause an error, too. Delete it, it doesn't make sense. (others=>'0') is not a signal you can assign something to. > --data<='0' !!! ; > (others=>'0')<=CD; See above. It looks like you're trying to clear "data" and "CD" here in reset. You cannot do that, since both "data" and "CD" are inputs to your entity, meaning they are generated OUTSIDE of your module; hence you have no way of influencing their values. If you want to clear them, you need to do that in another module that connects to yours or a testbench that instantiates this module and drives its inputs. > --"0000"<=CD ; > s <=(others=>'0'); > else > for i in 0 to 3 loop > > if (clk'event and clk='1')then ... the "for" loop should be outside the clock condition. Otherwise you'd basically have 4 clock conditions. Not sure what simulation and synthesis tools would do with that. It's legal VHDL, but makes no sense in practice. > > --for i in 0 to 3 loop > > com(i)<= not(CD(i) xor data) ; > > end if ; > end loop ; > > end if ; > end process ; > s<=com(i) ; There's another bunch of problems here... - You have two sources for signal "s". It is assigned inside your process and outside of it. When you synthesize this, you'll probably get a "multiple drivers" error. - You use the i-index that is only known inside the process. - com(i) is of length 1, s is of length 2, so the assignment won't work here, anyway... Same applies to "com(i)<= not(CD(i) xor data) ;". Data is of length 2, so you can't xor it with a single bit. I'm surprised the first thing your simulation tool finds is the problem in line 38... I don't know what you are trying to do, so I can't tell you what to do exactly, but first I suggest you get a book on VHDL or read up on the web. You seem to lack basic understanding of the language constructs... HTH, Sean From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.66.254.101 with SMTP id ah5mr2107442pad.8.1399407095367; Tue, 06 May 2014 13:11:35 -0700 (PDT) X-Received: by 10.140.95.112 with SMTP id h103mr773109qge.4.1399407095281; Tue, 06 May 2014 13:11:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!r10no1302413igi.0!news-out.google.com!dz10ni33693qab.1!nntp.google.com!hw13no861102qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 6 May 2014 13:11:35 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> Subject: erreur VHDL 2 From: Ayoub Injection-Date: Tue, 06 May 2014 20:11:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7514 Hi My friends ! there is an option to attach file ?! because I would like to attache the design for more detail but I can't do it !! anybody help me please !! Thank you very much From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: erreur VHDL 2 Date: 7 May 2014 15:18:26 GMT Lines: 21 Message-ID: References: <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> X-Trace: individual.net g4KEIi3+hv8S8UVjAx8FigcDuw9lmN62kabAT+pWvmMAy9emP1 X-Orig-Path: not-for-mail Cancel-Lock: sha1:Qpx9Q62WBs1mvld7KB2XVr35Y9I= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7515 Hi Ayoub, In article <9e163e2c-b05c-4cae-aa4e-14644b9d7765@googlegroups.com> you wrote: [] > there is an option to attach file ?! try http://pastebin.com/ You'll get a link you can paste here. There are other websites like that, google is your friend. > because I would like to attache the design for more detail but I can't > do it !! even if most of us are 'friendly' people, I will never open a file from a stranger (and IMHO you shouldn't either). > anybody help me please !! check your keyboard, I guess your exclamation mark key is stuck ;-) HTH, Al From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.43.67.67 with SMTP id xt3mr4315956icb.23.1399642738669; Fri, 09 May 2014 06:38:58 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr215821qgf.2.1399642738638; Fri, 09 May 2014 06:38:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no3656758igq.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no1784920qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 06:38:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Fri, 09 May 2014 13:38:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7516 This cropped up today while writing a testbench. Please look at the followi= ng code - it manages a linked list: type queue is protected procedure add_data(a : unsigned); procedure get_data(a : out unsigned); end protected queue; =20 =20 type queue is protected body type link_t; type link_ptr_t is access link_t; =20 type link_t is record data : unsigned; next_link : link_ptr_t; end record link_t; =20 variable start_of_list : link_ptr_t; =20 procedure add_data(a : unsigned) is variable ptr : link_ptr_t :=3D null; begin ptr :=3D new link_t'( (a, start_of_list) ); start_of_list :=3D ptr; end procedure add_data; =20 =20 procedure get_data(a : out unsigned) is variable ptr : link_ptr_t :=3D null; begin a :=3D start_of_list.data; =20 ptr :=3D start_of_list.next_link; DEALLOCATE(start_of_list); =20 start_of_list :=3D ptr; end procedure get_data; =20 end protected body queue; Ideally, the get_data procedure would actually be a function (as I have don= e in the past) but as the data field in the link_t is unconstrained in the = type, I cannot create a temporary variable to place the data into before re= turning it from the function, as I dont know the length of the data field b= efore pulling it out of the list.=20 Would the above be the best way of doing it, or can some others of you work= out a way a function would work instead? From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.50.108.47 with SMTP id hh15mr2387202igb.3.1399647465449; Fri, 09 May 2014 07:57:45 -0700 (PDT) X-Received: by 10.182.221.225 with SMTP id qh1mr62037obc.1.1399647465007; Fri, 09 May 2014 07:57:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!c1no3688984igq.0!news-out.google.com!gi6ni790igc.0!nntp.google.com!c1no3688978igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 07:57:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: KJ Injection-Date: Fri, 09 May 2014 14:57:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7517 On Friday, May 9, 2014 9:38:58 AM UTC-4, Tricky wrote: > This cropped up today while writing a testbench. Please look at the follo= wing >=20 > Ideally, the get_data procedure would actually be a function (as I have d= one=20 > in the past) but as the data field in the link_t is unconstrained in the= =20 > type, I cannot create a temporary variable to place the data into before= =20 > returning it from the function, as I dont know the length of the data fie= ld=20 > before pulling it out of the list.=20 Actually you do know the length of the data field, it is start_of_list.data= 'length >=20 > Would the above be the best way of doing it, or can some others of you wo= rk=20 > out a way a function would work instead? Below is a function that should be equivalent to your procedure. It compil= es and accomplishes your goal of having a function, but whether it actually= works or not I didn't test. I kind of have my doubts since the 'data' element of your record is not con= strained it's not immediately obvious where you're allocating space for the= actual data element when you go to 'put' the data. I'm guessing that alth= ough it compiles, neither your procedure nor my function will actually run.= But in any case, I believe that what I have posted for the function is th= e equivalent to your procedure. Kevin Jennings impure function get_data2 return unsigned is variable ptr : link_ptr_t :=3D null;=20 variable a: unsigned(start_of_list.data'range); begin=20 a :=3D start_of_list.data;=20 =20 ptr :=3D start_of_list.next_link;=20 DEALLOCATE(start_of_list);=20 =20 start_of_list :=3D ptr;=20 return(a); end function get_data2; From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.66.252.198 with SMTP id zu6mr2796433pac.25.1399650600056; Fri, 09 May 2014 08:50:00 -0700 (PDT) X-Received: by 10.140.51.231 with SMTP id u94mr19612qga.34.1399650600009; Fri, 09 May 2014 08:50:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no2427178igi.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no1819310qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 May 2014 08:49:59 -0700 (PDT) In-Reply-To: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Fri, 09 May 2014 15:50:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7518 This is fine, but if the start_of_list is null, you will get an error from = a null pointer access. In the real code I have a record type instead of just an unsigned. If the s= tart_of_list is null it returns a NULL version of the record type I have as= a constant. I actually worked around the problem by creating a pointer to = the record type, pulling the data off the linked list into the pointer, the= n returning the de-referenced data: impure function get_packet return packet_info_t is variable ptr : packet_ll_ptr_t :=3D null; variable ret : packet_info_ptr_t :=3D null; begin if end_of_list =3D null then=20 ret :=3D new packet_info_t'(NULL_PACKET); =20 else ptr :=3D end_of_list.next_packet; ret :=3D new packet_info_t'( ptr.pi ); =20 DEALLOCATE(end_of_list); end_of_list :=3D ptr; =20 end if; =20 return ret.all; end function get_packet; On Friday, 9 May 2014 15:57:44 UTC+1, KJ wrote: > On Friday, May 9, 2014 9:38:58 AM UTC-4, Tricky wrote: >=20 > > This cropped up today while writing a testbench. Please look at the fol= lowing >=20 >=20 > > Ideally, the get_data procedure would actually be a function (as I have= done=20 >=20 > > in the past) but as the data field in the link_t is unconstrained in th= e=20 >=20 > > type, I cannot create a temporary variable to place the data into befor= e=20 >=20 > > returning it from the function, as I dont know the length of the data f= ield=20 >=20 > > before pulling it out of the list.=20 >=20 >=20 >=20 > Actually you do know the length of the data field, it is start_of_list.da= ta'length >=20 >=20 >=20 > >=20 >=20 > > Would the above be the best way of doing it, or can some others of you = work=20 >=20 > > out a way a function would work instead? >=20 >=20 >=20 > Below is a function that should be equivalent to your procedure. It comp= iles and accomplishes your goal of having a function, but whether it actual= ly works or not I didn't test. >=20 >=20 >=20 > I kind of have my doubts since the 'data' element of your record is not c= onstrained it's not immediately obvious where you're allocating space for t= he actual data element when you go to 'put' the data. I'm guessing that al= though it compiles, neither your procedure nor my function will actually ru= n. But in any case, I believe that what I have posted for the function is = the equivalent to your procedure. >=20 >=20 >=20 > Kevin Jennings >=20 >=20 >=20 > impure function get_data2 return unsigned is >=20 > variable ptr : link_ptr_t :=3D null;=20 >=20 > variable a: unsigned(start_of_list.data'range); >=20 > begin=20 >=20 > a :=3D start_of_list.data;=20 >=20 > =20 >=20 > ptr :=3D start_of_list.next_link;=20 >=20 > DEALLOCATE(start_of_list);=20 >=20 > =20 >=20 > start_of_list :=3D ptr;=20 >=20 > return(a); >=20 > end function get_data2; From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Writing testbench tools. Suggestions? Date: Fri, 09 May 2014 19:11:08 +0200 Organization: A noiseless patient Spider Lines: 67 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 May 2014 17:11:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="23351"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+4pZz7j90fK8k5FmHP2hHx" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 Cancel-Lock: sha1:jWtfnUP+lcUmiMev5kWm1QL32Js= Xref: news.eternal-september.org comp.lang.vhdl:7519 I am trying to write some helper tools to generate testbench signals. For instance, I have written this data_stream generator: procedure data_stream( signal y : out std_logic; -- Output signal constant data : std_logic_vector; -- Data, e.g. "11110101" constant bit_period : time; -- Duration of each bit constant start_time : time := 0 ns; -- Initial time offset constant def_out : std_logic := 'U') is begin y <= def_out; wait for start_time; for ix in data'left to data'right loop (*) y<=data(ix); wait for bit_period; end loop; y <= def_out; (*) actually I look if data'left < data'right and iterate "to" or "downto" otherwise. (Could probably be improved) Using this procedure, in the test bench I can build: data_stream(slv(1),"0011",1 us, 0 us,'Z'); data_stream(slv(0),"1101",1 us, 5 us,'Z'); Now, I would like to merge each signal onto one. Thanks to the default value of 'Z' this is simple. For instance, in the test bench, this code works fine: join: for i in slv'range generate tot <= slv(i); end generate; y <='U' when tot='Z' else tot; where the 'U' could be changed to whatever makes sense. Now, I would like to have the last lines in a _function_ or _procedure_. Unfortunately, I only have been able to bring this together, which works but looks ugly compared to the 4 lines before: procedure signal_join( signal y : out std_logic; constant slv : std_logic_vector; constant def_out : std_logic := 'U') is variable tot: std_logic; begin tot := 'Z'; join: for i in slv'range loop if slv(i)/='Z' then tot := slv(i); end if; end loop; if tot='Z' then y<=def_out; else y<=tot; end if; end; I would appreciate any suggestion on this. Especially, if I am making big mistakes! Furthermore, I have been unable to find functions that ease the generation of test signals, say to simulate some bursts of an SPI master or whatever, which is why I am writing this stuff. Any pointers on this? Pere From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: how create an 8 bit binary to BCD decoder? Date: Fri, 09 May 2014 14:33:46 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 9 May 2014 18:33:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="1f290bac804f6cd54e3c0a5f7ad6fb70"; logging-data="27599"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xbSvXhlriyM35Y9wkY19U" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Cancel-Lock: sha1:DcY48J6CfIxyLbaILsTKC6Oqr+w= Xref: news.eternal-september.org comp.lang.vhdl:7520 On 5/1/2014 12:55 PM, emirogluengin@gmail.com wrote: > 15 Mayıs 2002 ÇarÅŸamba 23:07:03 UTC+3 tarihinde Christian yazdı: >> Hello! >> I know this newsgroup is specially ybout VHDL. But I am curently working >> with Altera's derivation AHDL. >> My question isn't quite language related but more general: >> >> How would you create a decoder which generates BCD-coding from normal 8bit >> binary coding? >> I want to control several 7 segment displays and therefore have to use BCD >> coding. >> >> I'd be very happy to get any kind of help. >> Regards >> Chris. I see this message has not been answered so let me try. I remember seeing some fairly elegant ways to convert binary to decimal, but none of them seem to have stuck in my mind. I bet a google search would pull up a few. In your case I think you could do some fairly simple shortcuts which take advantage of the fact that you are only converting an 8 bit sample. With larger numbers it is usually done iteratively, converting one digit at a time, LSB first. -- Rick From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.182.219.226 with SMTP id pr2mr7921784obc.44.1399714550111; Sat, 10 May 2014 02:35:50 -0700 (PDT) X-Received: by 10.140.49.70 with SMTP id p64mr6483qga.21.1399714550046; Sat, 10 May 2014 02:35:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no2664821igi.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no2030936qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 May 2014 02:35:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.23.53.3; posting-account=rOfGEwkAAACFroalPzX-5MFVPhTYgaRI NNTP-Posting-Host: 188.23.53.3 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL to SystemC From: moogyd@yahoo.co.uk Injection-Date: Sat, 10 May 2014 09:35:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7521 Hi, Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. Thanks, Steven From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.66.230.226 with SMTP id tb2mr6910304pac.41.1399765492083; Sat, 10 May 2014 16:44:52 -0700 (PDT) X-Received: by 10.182.99.199 with SMTP id es7mr101890obb.17.1399765491817; Sat, 10 May 2014 16:44:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4344999igq.0!news-out.google.com!gi6ni804igc.0!nntp.google.com!c1no4344992igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 10 May 2014 16:44:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=173.167.190.129; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 173.167.190.129 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Subject: Writing testbench tools. Suggestions? From: KJ Injection-Date: Sat, 10 May 2014 23:44:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7522 When writing test benches for something that attaches to the top level of a= design, I find it best to simply model the physical part on the actual boa= rd. When you do that, you will start building up a library of part models = that can be reused down the road. The verification of the part model is do= ne by verifying to the data sheet. Your design then gets verified by using= your validated part model. Will lead to less surprises when you power up = your board. Since you mentioned emulating a SPI master you are likely in t= his situation. If writing testbenches for internal modules, you will find it can be produc= tive to standardize on an interface protocol such as Avalon or Wishbone. O= ne benefit will be that testbench writing will be more standardized. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.lang.vhdl Subject: Re: VHDL to SystemC Date: Sun, 11 May 2014 13:46:44 +0100 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: Injection-Date: Sun, 11 May 2014 12:46:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d1343ad59d23d554448c77c3a5a8e031"; logging-data="11769"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/8+/q6CE5GOo7Jq5YNlLov" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:puobIwXiz95RZyL8szGlfEdGJ1E= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.lang.vhdl:7523 wrote in message news:aeddf515-3f70-4b02-9f36-025a8f2b5f78@googlegroups.com... > Hi, > Has anybody successfully used VDHL to SystemC conversion tools. Google > returns one or two options, but I'd like to hear from people who have used > them. > Thanks, > Steven It's like converting foot toe to hands thumb. Do you really want that? From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx28.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL to SystemC References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140511-0, 11/05/2014), Outbound message X-Antivirus-Status: Clean Lines: 24 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1399827424 86.29.12.221 (Sun, 11 May 2014 16:57:04 UTC) NNTP-Posting-Date: Sun, 11 May 2014 16:57:04 UTC Organization: virginmedia.com Date: Sun, 11 May 2014 17:57:04 +0100 X-Received-Body-CRC: 2817037900 X-Received-Bytes: 2020 Xref: news.eternal-september.org comp.lang.vhdl:7524 On 10/05/2014 10:35, moogyd@yahoo.co.uk wrote: > Hi, > Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. > Thanks, > Steven > Hi Steven, I briefly played with Carbon (http://www.carbondesignsystems.com) and I must say that I was quite impressed. I only tried a few test cases but from what I remember the resulting C++ (with a SystemC top layer) ran much faster than the original VHDL. If you are looking into building a virtual prototype then I would recommend you speak to these guys. If you just want to import some VHDL models to an OSCI environment than you can try my VHDL to SystemC converter as a template generator. However, expect much worse simulation time (3x slower), minimum language support, requirement to fix/tweak the code and on top of that a developer not willing to fix the translator ;-) Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Sun, 11 May 2014 20:08:42 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 11 May 2014 18:08:44 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="e1ca11cb030fe122572a5bbc5f30875d"; logging-data="19135"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Dj9Az01sL7ykdHDATO9Qkjh08pYGDZz8=" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> Cancel-Lock: sha1:bIwpuWIaWC3nCp5tg1XZKDDLD0A= Xref: news.eternal-september.org comp.lang.vhdl:7525 On 05/11/2014 01:44 AM, KJ wrote: > When writing test benches for something that attaches to the top level of a design, I find it best to simply model the physical part on the actual board. When you do that, you will start building up a library of part models that can be reused down the road. The verification of the part model is done by verifying to the data sheet. Your design then gets verified by using your validated part model. Will lead to less surprises when you power up your board. Since you mentioned emulating a SPI master you are likely in this situation. > > If writing testbenches for internal modules, you will find it can be productive to standardize on an interface protocol such as Avalon or Wishbone. One benefit will be that testbench writing will be more standardized. > > Kevin Jennings > I feel this is exactly what I am doing: My design will talk to an SPI master, hence I am generating the waveforms that the master is expected to give, according to the datasheet. In my post, I included some code that allows me to build an arbitrary burst (usable for clock, data, whatever). The question remains: what is the best way to combine these individual bursts onto a single signal, so that I can model an arbitrary number of occurrences of each stream at arbitrary time points? Pere From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.43.79.196 with SMTP id zr4mr11606013icb.3.1399860992021; Sun, 11 May 2014 19:16:32 -0700 (PDT) X-Received: by 10.182.191.98 with SMTP id gx2mr1049obc.22.1399860991863; Sun, 11 May 2014 19:16:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no4918763igq.0!news-out.google.com!gi6ni796igc.0!nntp.google.com!r10no3340867igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 11 May 2014 19:16:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Subject: Re: Writing testbench tools. Suggestions? From: KJ Injection-Date: Mon, 12 May 2014 02:16:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7526 On Sunday, May 11, 2014 2:08:42 PM UTC-4, o pere o wrote: > I feel this is exactly what I am doing: My design will talk to an SPI=20 > master, hence I am generating the waveforms that the master is expected= =20 > to give, according to the datasheet.=20 It is not evident in what you posted that there would be any connection wit= h the datasheet at all. Not a very obvious one at least. You don't want t= o make validating the model to be an even bigger task than using the model = to validate your design. >=20 > In my post, I included some code that allows me to build an arbitrary=20 > burst (usable for clock, data, whatever).=20 Not really. Most parts respond to signals from other external parts (i.e. = a processor interface to an FPGA). What you have shown is something where = you give it a list of outputs and you crank them out at some fixed interval= . In effect it is nothing more than this: xyz <=3D '1', '0' after bit_period, '1' after 2*bit_period, '1' after 3*bit= _period ... While use of your procedure would be a better shorthand than the above line= of code, there really isn't much call for the above line of code in the fi= rst place so your shorthand procedure wouldn't have much utility. A SPI master model would instead respond to some higher level control (i.e.= a model for the code running in a processor) and then chunk out the bits a= nd clock as they are specified in the datasheet. So a snippet of the SPI m= aster for a processor with a SPI master might look like this... process begin Spi_Cs_n <=3D '1'; Spi_Sclk <=3D '0'; wait until Spi_Master_Write_This_Out'event; -- Some example of this SPI = master process waiting for something to do Spi_Cs_n <=3D '0'; wait for Spi_Cs_To_Sclk_Time; -- Spec'ed on the datasheet for i in Spi_Data_To_Write'low to Spi_Data_To_Write'high loop Spi_Sclk <=3D '1', '0' after Spi_Clock_Period/2; -- Note: Spi_Clock_= Period could be a signal so you can vary the Spi clock period during the si= m Spi_Mosi <=3D Spi_Data_To_Write(i) after Tco; -- Models the clock = to output delay per the datasheet, in case that ends up mattering wait until Spi_Sclk'falling edge Spi_Sclk; wait for Spi_Clock_Period/2; end loop; Spi_Cs_n <=3D '1'; wait for Spi_Cs_Inactive_To_Spi_Cs_Active_Again; -- Again, likely spec'e= d on datasheet end process; > The question remains: what is=20 > the best way to combine these individual bursts onto a single signal, so= =20 > that I can model an arbitrary number of occurrences of each stream at=20 > arbitrary time points?=20 >=20 I don't have an answer for that question since I don't think it's the right= approach. What physical parts can you think of that would have in their d= atasheet listed something where it shoots out a particular pattern at some = periodic rate? Can you think of more than one part? However, if you create a model of an actual part instead, then you'll find that you don't n= eed to answer your stated question in order to get a working and reaonably realistic model. You might not agree, and that's fine, I'm just putting in= my two cents and giving you an example to consider instead. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:25 2015 X-Received: by 10.58.168.137 with SMTP id zw9mr13787495veb.15.1399880108458; Mon, 12 May 2014 00:35:08 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr20426qge.10.1399880108432; Mon, 12 May 2014 00:35:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hw13no2640906qab.0!news-out.google.com!dz10ni36309qab.1!nntp.google.com!hw13no2640902qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 May 2014 00:35:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=81.223.253.45; posting-account=rOfGEwkAAACFroalPzX-5MFVPhTYgaRI NNTP-Posting-Host: 81.223.253.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04f0535a-dbdd-4537-8e72-ec4d86e5aac0@googlegroups.com> Subject: Re: VHDL to SystemC From: moogyd@yahoo.co.uk Injection-Date: Mon, 12 May 2014 07:35:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7527 On Sunday, 11 May 2014 18:57:04 UTC+2, HT-Lab wrote: > On 10/05/2014 10:35, ******yahoo.co.uk wrote: > > > Hi, > > > Has anybody successfully used VDHL to SystemC conversion tools. Google returns one or two options, but I'd like to hear from people who have used them. > > > Thanks, > > > Steven > > > > > Hi Steven, > I briefly played with Carbon (http://www.carbondesignsystems.com) and I > must say that I was quite impressed. I only tried a few test cases but > from what I remember the resulting C++ (with a SystemC top layer) ran > much faster than the original VHDL. If you are looking into building a > virtual prototype then I would recommend you speak to these guys. > If you just want to import some VHDL models to an OSCI environment than > you can try my VHDL to SystemC converter as a template generator. > However, expect much worse simulation time (3x slower), minimum language > support, requirement to fix/tweak the code and on top of that a > developer not willing to fix the translator ;-) > Good luck, > Hans > www.ht-lab.com Hi Hans, you are correct - I am looking to produce a virtual prototype for FW development. The plan is to do initial conversion automatically, and then analyze performance of resulting models, perhaps performing some optimizations where possibly. I'll have a look at you suggestions. Thanks, Steven From newsfish@newsfish Tue Dec 29 16:43:25 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: how create an 8 bit binary to BCD decoder? Date: Mon, 12 May 2014 08:40:08 -0400 Organization: Alacron, Inc. Lines: 50 Message-ID: References: <179bb941-0582-42c6-9d53-e68c435b1c5f@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 12 May 2014 12:42:04 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="7136"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18VinQY25CTZmbdkffq7mqM9I9At+CbaAk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:XCw6YU/6037RwczbVfGTNGNC6Lg= Xref: news.eternal-september.org comp.lang.vhdl:7528 rickman wrote: > On 5/1/2014 12:55 PM, emirogluengin@gmail.com wrote: >> 15 Mayıs 2002 ÇarÅŸamba 23:07:03 UTC+3 tarihinde Christian yazdı: >>> Hello! >>> I know this newsgroup is specially ybout VHDL. But I am curently working >>> with Altera's derivation AHDL. >>> My question isn't quite language related but more general: >>> >>> How would you create a decoder which generates BCD-coding from normal >>> 8bit >>> binary coding? >>> I want to control several 7 segment displays and therefore have to >>> use BCD >>> coding. >>> >>> I'd be very happy to get any kind of help. >>> Regards >>> Chris. > > I see this message has not been answered so let me try. > > I remember seeing some fairly elegant ways to convert binary to decimal, > but none of them seem to have stuck in my mind. I bet a google search > would pull up a few. > > In your case I think you could do some fairly simple shortcuts which > take advantage of the fact that you are only converting an 8 bit sample. > With larger numbers it is usually done iteratively, converting one > digit at a time, LSB first. > When I had to do this with an 8-bit micro, I made use of the DAA (decimal adjust after addition) instruction. The basic loop was: shift input left into carry add accumulator + carry in to accumulator decimal adjust accumulator The combination of addition and DAA effectively created a BCD adder. Note that the accumulator must be zeroed out before the loop, and you need a loop counter, but that was the basic idea. In an FPGA, I'd probably use a lookup table if there were only 8 bits. I assume that since this information is going to a display, that you have lots of time (many clock cycles) available to get the job done? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Mon, 12 May 2014 19:25:50 +0200 Organization: A noiseless patient Spider Lines: 81 Message-ID: References: <093bfe77-b164-4a51-8fac-0ac6f28d2f59@googlegroups.com> <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 12 May 2014 17:25:50 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="9449"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SMU8m3oLlXN9LB73gmMpR" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <775dfba4-6e6e-46c3-82ac-9500c6b24fa0@googlegroups.com> Cancel-Lock: sha1:Qz0xPat16DFt0KIHl7cqRy/VdPU= Xref: news.eternal-september.org comp.lang.vhdl:7529 On 05/12/2014 04:16 AM, KJ wrote: > On Sunday, May 11, 2014 2:08:42 PM UTC-4, o pere o wrote: >> I feel this is exactly what I am doing: My design will talk to an SPI >> master, hence I am generating the waveforms that the master is expected >> to give, according to the datasheet. > > It is not evident in what you posted that there would be any connection with the datasheet at all. Not a very obvious one at least. You don't want to make validating the model to be an even bigger task than using the model to validate your design. > >> >> In my post, I included some code that allows me to build an arbitrary >> burst (usable for clock, data, whatever). > > Not really. Most parts respond to signals from other external parts (i.e. a processor interface to an FPGA). What you have shown is something where you give it a list of outputs and you crank them out at some fixed interval. In effect it is nothing more than this: > > xyz <= '1', '0' after bit_period, '1' after 2*bit_period, '1' after 3*bit_period ... True. A simple helper function for this is exactly the goal that I had in mind. > While use of your procedure would be a better shorthand than the above line of code, there really isn't much call for the above line of code in the first place so your shorthand procedure wouldn't have much utility. Well, I have had the need to generate arbitrary data bursts at arbitrary time positions quite often... Of course, a model for the generator of these bursts gives more information... As always, it is a balance! > A SPI master model would instead respond to some higher level control (i.e. a model for the code running in a processor) and then chunk out the bits and clock as they are specified in the datasheet. So a snippet of the SPI master for a processor with a SPI master might look like this... > > process > begin > Spi_Cs_n <= '1'; > Spi_Sclk <= '0'; > wait until Spi_Master_Write_This_Out'event; -- Some example of this SPI master process waiting for something to do > Spi_Cs_n <= '0'; > wait for Spi_Cs_To_Sclk_Time; -- Spec'ed on the datasheet > for i in Spi_Data_To_Write'low to Spi_Data_To_Write'high loop > Spi_Sclk <= '1', '0' after Spi_Clock_Period/2; -- Note: Spi_Clock_Period could be a signal so you can vary the Spi clock period during the sim > Spi_Mosi <= Spi_Data_To_Write(i) after Tco; -- Models the clock to output delay per the datasheet, in case that ends up mattering > wait until Spi_Sclk'falling edge Spi_Sclk; > wait for Spi_Clock_Period/2; > end loop; > Spi_Cs_n <= '1'; > wait for Spi_Cs_Inactive_To_Spi_Cs_Active_Again; -- Again, likely spec'ed on datasheet > end process; Now I see your point clearer. However, I will still need to to generate the Spi_Master_Write_This_Out'event at an arbitrary time instant. Then I will need to be able to change the data that is being written, depending on the particular data burst. This can be done, and is probably the way to go if you want maximum flexibility. However, if I just need a couple of bursts, my quick-and-dirty approach gives me a suitable waveform without having to go into the SPI details... Of course your approach gives more insight although at a higher initial coding cost. >> The question remains: what is >> the best way to combine these individual bursts onto a single signal, so >> that I can model an arbitrary number of occurrences of each stream at >> arbitrary time points? >> > > I don't have an answer for that question since I don't think it's the right approach. What physical parts can you think of that would have in their datasheet listed something where it shoots out a particular pattern at some periodic rate? Can you think of more than one part? However, if you > create a model of an actual part instead, then you'll find that you don't need to answer your stated question in order to get a working and reaonably > realistic model. You might not agree, and that's fine, I'm just putting in my two cents and giving you an example to consider instead. I really appreciate your inputs and thank you for your time. My effort is just to have something a little more elaborate than the practice of just drawing waveforms in a waveform editor. The SPI example I mentioned is however just one of the inputs of my current design. The other will be a physical IEEE 802.15.4 frame. Here, I am currently able to generate a burst corresponding to some data, following the original idea I posted. Again, a simple combination of individual signals might do the job of simulating a typical transaction. Perhaps I can come up with something similar as the example you posted... Pere From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.42.236.68 with SMTP id kj4mr14878981icb.6.1399986549796; Tue, 13 May 2014 06:09:09 -0700 (PDT) X-Received: by 10.140.18.194 with SMTP id 60mr28qgf.36.1399986549748; Tue, 13 May 2014 06:09:09 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no5617034igq.0!news-out.google.com!dz10ni40603qab.1!nntp.google.com!hw13no3018801qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 May 2014 06:09:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> Subject: Help code VHDL From: Ayoub Injection-Date: Tue, 13 May 2014 13:09:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7530 hi everybody ! I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data and the result would be S . Can you help me correcting this code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Premier is port( clk:in std_logic ; rst:in std_logic ; data:in std_logic ; CD :in std_logic_vector(3 downto 0); S :out std_logic ); end entity ; architecture beh of Premier is signal i :integer range 0 to 3; signal iCD :std_logic_vector(3 downto 0); signal idata:std_logic ; begin code:process(clk,rst) begin if(rst='1') then S<='0'; i<=0; idata<=data ; iCD <=CD ; else if(clk'event and clk='1')then if(CD(0)='0')then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(1)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(2)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; if(CD(3)='0') then iCD(3 downto 0)<="1111"; else iCD(3 downto 0)<="0001"; end if ; S<=not(iCD(i) xor (idata)); i<= i+1; if i=3 then idata<= data ; end if ; end if ; end if ; end process ; end architecture ; Thank you ! From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.stack.nl!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: Help code VHDL Date: Tue, 13 May 2014 08:28:12 -0700 Organization: Aioe.org NNTP Server Lines: 20 Message-ID: References: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7531 On 5/13/2014 6:09 AM, Ayoub wrote: > I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data > and the result would be S . According to my interpretation of the stated requirements, this pseudo code should work: func([in] CD, [in] data, [out] S) if CD == 0 S = -1 else if CD == 1 S = 1 else S = CD + data func end No registers or clocking are needed. It is basic combinatorial logic. JJS From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!newsfeed.xs4all.nl!newsfeed3a.news.xs4all.nl!xs4all!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 11:30:25 +0200 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 65 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1400059825 dreader35.news.xs4all.nl 27153 puiterl/195.242.97.150:51618 Xref: news.eternal-september.org comp.lang.vhdl:7532 Tricky wrote: > This is fine, but if the start_of_list is null, you will get an error from > a null pointer access. > > In the real code I have a record type instead of just an unsigned. If the > start_of_list is null it returns a NULL version of the record type I have > as a constant. I actually worked around the problem by creating a pointer > to the record type, pulling the data off the linked list into the pointer, > then returning the de-referenced data: > > impure function get_packet return packet_info_t is > variable ptr : packet_ll_ptr_t := null; > variable ret : packet_info_ptr_t := null; > begin > if end_of_list = null then > ret := new packet_info_t'(NULL_PACKET); > > else > ptr := end_of_list.next_packet; > ret := new packet_info_t'( ptr.pi ); > > DEALLOCATE(end_of_list); > end_of_list := ptr; > > end if; > > return ret.all; > end function get_packet; You create a memory leak in this way, so don't do it this way. Every time get_packet is called, a packet is allocated, never deallocated and the pointer to it (ret) is lost upon exiting the function. VHDL does not know the concept of garbage collection, so this is a memory leak. To verify this, put the get_packet in a loop, endless, or a lot of times (increasing it tenfold with each run) and observe the memory usage of your machine. Or, in case of the endless loop, watch the simulator crash (and/or see you machine getting irresponsive). To get around the unconstrained issue, I would put the code in a package. Put a generic on that package, specifying the width of the data. Or better still, put the datatype in the generic of the package! When instantiating the package, you specify the datatype. In that way you can use your queue for any data type. Check out the book "VHDL-2008, just the new stuff" by Peter Ashenden and Jim Lewis. It is all described there, in the first chapter. One more thing: when declaring a variable of an access type, it is not necessary to initialize it to null. The initial value of variables and signals automatically is "the most left value" of the type of the variable or signal. For natural it is 0, for boolean false, for enumeration types the first member, for access types it is null. People sometimes complain that VHDL is overly verbose, but at the same time they type needless things... ;-) -- Paul Uiterlinden www.aimvalley.nl From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!newsfeed.xs4all.nl!newsfeed3.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Writing testbench tools. Suggestions? Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 11:41:19 +0200 References: Organization: AimValley User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 17 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1400060479 dreader35.news.xs4all.nl 27127 puiterl/195.242.97.150:51653 Xref: news.eternal-september.org comp.lang.vhdl:7533 o pere o wrote: > I am trying to write some helper tools to generate testbench signals. [snip] > > I would appreciate any suggestion on this. Especially, if I am making > big mistakes! Furthermore, I have been unable to find functions that > ease the generation of test signals, say to simulate some bursts of an > SPI master or whatever, which is why I am writing this stuff. Any > pointers on this? I would suggest reading a book like "Writing Testbenches" by Janick Bergeron and look at the client/server model suggested there. -- Paul Uiterlinden www.aimvalley.nl From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.58.22.70 with SMTP id b6mr1983067vef.13.1400083072217; Wed, 14 May 2014 08:57:52 -0700 (PDT) X-Received: by 10.140.106.67 with SMTP id d61mr7695qgf.41.1400083072077; Wed, 14 May 2014 08:57:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!c1no6539701igq.0!news-out.google.com!qf4ni926igc.0!nntp.google.com!c1no6539679igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 08:57:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.83; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.83 References: <9b9bc77a-b6d4-41a7-a18f-e9d405b8864f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help code VHDL From: Ayoub Injection-Date: Wed, 14 May 2014 15:57:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7534 On Tuesday, May 13, 2014 5:28:12 PM UTC+2, John Speth wrote: > On 5/13/2014 6:09 AM, Ayoub wrote: > > > I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data > > > and the result would be S . > > > > According to my interpretation of the stated requirements, this pseudo > > code should work: > > > > func([in] CD, [in] data, [out] S) > > if CD == 0 > > S = -1 > > else if CD == 1 > > S = 1 > > else > > S = CD + data > > func end > > > > No registers or clocking are needed. It is basic combinatorial logic. > > > > JJS Thank you very much ^^ From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.66.138.17 with SMTP id qm17mr1962938pab.34.1400083162968; Wed, 14 May 2014 08:59:22 -0700 (PDT) X-Received: by 10.50.62.6 with SMTP id u6mr142061igr.15.1400083162833; Wed, 14 May 2014 08:59:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no6540688igq.0!news-out.google.com!qf4ni1019igc.0!nntp.google.com!r10no4491818igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 08:59:22 -0700 (PDT) In-Reply-To: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.71.10.236; posting-account=3tUCQgoAAACv9-0KuHrdfl7c9q886ho5 NNTP-Posting-Host: 118.71.10.236 References: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> Subject: Re: ASIC gate count estimation From: toanbkfet@gmail.com Injection-Date: Wed, 14 May 2014 15:59:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7535 hello you have document speak of count gate nand 2 ?? if you have ?? can you spent document that?? From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.236.125.6 with SMTP id y6mr2706550yhh.3.1400106603563; Wed, 14 May 2014 15:30:03 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr81170qgd.16.1400106603353; Wed, 14 May 2014 15:30:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no6836851igq.0!news-out.google.com!qf4ni926igc.0!nntp.google.com!c1no6836843igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 May 2014 15:30:03 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Subject: Array VHDL From: Ayoub Injection-Date: Wed, 14 May 2014 22:30:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7536 Hi everybody ! I have a small problemIo want to do a not xor for 4 input of 4 bit with input data 1 bit to have a 4 bit output using a table of input here is my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdm is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; CD : in std_logic_vector(15 downto 0) ; S : out std_logic(3 downto 0 ); end entity ; architecture beh of cdm is signal i :integer range 0 to 3 ; signal idata :std_logic ; begin code :process(clk,rst) begin if(rst='1')then S<='0'; i<=0 ; idata<=data ; else if(clk'event and clk='1')then type tab is array(3 downto 0)of std_logic_vector ???? ?? S<=not(CD(i) xor (idata)); i<= i+1 ; if i=3 then idata<=data ; end if ; end if ; end if ; end process ; end architecture ; Thank you in advance for your answer !! From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.224.72.66 with SMTP id l2mr4372505qaj.8.1400162011586; Thu, 15 May 2014 06:53:31 -0700 (PDT) X-Received: by 10.140.92.82 with SMTP id a76mr195636qge.1.1400162011477; Thu, 15 May 2014 06:53:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.stack.nl!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!c1no7294129igq.0!news-out.google.com!qf4ni1806igc.0!nntp.google.com!c1no7294123igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 May 2014 06:53:31 -0700 (PDT) In-Reply-To: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Ayoub Injection-Date: Thu, 15 May 2014 13:53:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7537 On Thursday, May 15, 2014 12:30:03 AM UTC+2, Ayoub wrote: > Hi everybody ! > > > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data > > 1 bit to have a 4 bit output using a table of input > > > > here is my code: > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > > > entity cdm is > > port ( > > clk : in std_logic ; > > rst : in std_logic ; > > data: in std_logic ; > > CD : in std_logic_vector(15 downto 0) ; > > S : out std_logic(3 downto 0 ); > > end entity ; > > > > architecture beh of cdm is > > > > signal i :integer range 0 to 3 ; > > signal idata :std_logic ; > > begin > > code :process(clk,rst) > > begin > > if(rst='1')then > > S<='0'; > > i<=0 ; > > idata<=data ; > > else > > if(clk'event and clk='1')then > > > > type tab is array(3 downto 0)of std_logic_vector > > ???? > > ?? > > > > S<=not(CD(i) xor (idata)); > > i<= i+1 ; > > if i=3 then > > idata<=data ; > > end if ; > > end if ; > > end if ; > > end process ; > > end architecture ; > > > > Thank you in advance for your answer !! Are You Here ? From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.182.24.5 with SMTP id q5mr5020525obf.23.1400162152721; Thu, 15 May 2014 06:55:52 -0700 (PDT) X-Received: by 10.140.95.141 with SMTP id i13mr200450qge.3.1400162152583; Thu, 15 May 2014 06:55:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no4951375igi.0!news-out.google.com!qf4ni1806igc.0!nntp.google.com!c1no7295972igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 May 2014 06:55:52 -0700 (PDT) In-Reply-To: <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2.84.30.178; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2.84.30.178 References: <1da53656-f7dd-4825-8334-6179605e9e5c@k39g2000hsf.googlegroups.com> <488e4fec-54b3-4c4e-bccc-de3dee012ba2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4707a363-9a89-4fa6-b87b-98e9d840cd81@googlegroups.com> Subject: Re: ASIC gate count estimation From: Nikolaos Kavvadias Injection-Date: Thu, 15 May 2014 13:55:52 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Xref: news.eternal-september.org comp.lang.vhdl:7538 VGhpcyBpcyBhIDYteWVhciBvbGQgdGhyZWFkLCBubyBtdWNoIHBvaW50IGluIGFkZGluZyBuZXcg cG9zdHMuDQoNCs6kzrcgzqTOtc+EzqzPgc+EzrcsIDE0IM6czrHOkM6/z4UgMjAxNCA2OjU5OjIy IM68Ls68LiBVVEMrMywgzr8gz4fPgc6uz4PPhM63z4IgdG9hbi4uLkBnbWFpbC5jb20gzq3Os8+B zrHPiM61Og0KPiBoZWxsbyB5b3UgaGF2ZSBkb2N1bWVudCBzcGVhayBvZiBjb3VudCBnYXRlIG5h bmQgMiA/Pw0KPiANCj4gIA0KPiANCj4gaWYgeW91IGhhdmUgPz8gY2FuIHlvdSBzcGVudCBkb2N1 bWVudCB0aGF0Pz8NCg0K From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.182.28.136 with SMTP id b8mr12438698obh.19.1400366368606; Sat, 17 May 2014 15:39:28 -0700 (PDT) X-Received: by 10.140.101.147 with SMTP id u19mr3597qge.10.1400366368486; Sat, 17 May 2014 15:39:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no611398igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no9295251igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 May 2014 15:39:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.100.228; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.100.228 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Nikolaos Kavvadias Injection-Date: Sat, 17 May 2014 22:39:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7539 Hi I am here. I would happily provide help. > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data My consulting services are better explained here: www.nkavvadias.com Best regards N > > > > > > 1 bit to have a 4 bit output using a table of input > > > > > > > > > > > > here is my code: > > > > > > > > > > > > library ieee; > > > > > > use ieee.std_logic_1164.all; > > > > > > use ieee.numeric_std.all; > > > > > > > > > > > > entity cdm is > > > > > > port ( > > > > > > clk : in std_logic ; > > > > > > rst : in std_logic ; > > > > > > data: in std_logic ; > > > > > > CD : in std_logic_vector(15 downto 0) ; > > > > > > S : out std_logic(3 downto 0 ); > > > > > > end entity ; > > > > > > > > > > > > architecture beh of cdm is > > > > > > > > > > > > signal i :integer range 0 to 3 ; > > > > > > signal idata :std_logic ; > > > > > > begin > > > > > > code :process(clk,rst) > > > > > > begin > > > > > > if(rst='1')then > > > > > > S<='0'; > > > > > > i<=0 ; > > > > > > idata<=data ; > > > > > > else > > > > > > if(clk'event and clk='1')then > > > > > > > > > > > > type tab is array(3 downto 0)of std_logic_vector > > > > > > ???? > > > > > > ?? > > > > > > > > > > > > S<=not(CD(i) xor (idata)); > > > > > > i<= i+1 ; > > > > > > if i=3 then > > > > > > idata<=data ; > > > > > > end if ; > > > > > > end if ; > > > > > > end if ; > > > > > > end process ; > > > > > > end architecture ; > > > > > > > > > > > > Thank you in advance for your answer !! > > > > Are You Here ? From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.58.29.14 with SMTP id f14mr3284072veh.32.1400485748942; Mon, 19 May 2014 00:49:08 -0700 (PDT) X-Received: by 10.140.104.202 with SMTP id a68mr16334qgf.30.1400485748686; Mon, 19 May 2014 00:49:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no1126436igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1126435igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 00:49:08 -0700 (PDT) In-Reply-To: <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 07:49:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7540 > > You create a memory leak in this way, so don't do it this way. > The memory leak is a concern, but this is best way around my problem. I cannot put the type in a package, because the the packet length is variable at run time. The whole point is the packet generator generates variable length packets for the UUT to handle. So even the package generics do not help here. Because of this, I do not know the length of the packet until it is pulled out of the queue, so I cannot create a temporary variable ----- Actually, I just thought, it wouldnt be very hard just to access the length of the packet on the end of the queue to return the length to create the temporary variable, so it is not a pointer. From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.50.119.164 with SMTP id kv4mr5597159igb.3.1400486295410; Mon, 19 May 2014 00:58:15 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr19122qgd.16.1400486295316; Mon, 19 May 2014 00:58:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no10275261igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10275254igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 00:58:15 -0700 (PDT) In-Reply-To: <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 07:58:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7541 So all I needed was an extra function to check if the end of queue was already null, or just return the length: ------------------------------------------------------------------ --Removes a packet from the FIFO Queue ------------------------------------------------------------------ impure function get_packet return packet_info_t is impure function get_payload_len return integer is begin if end_of_queue = null then return 0; else return end_of_queue.payload'length; end if; end function get_payload_len; variable ptr : packet_ll_ptr_t := null; variable ret : packet_info_t( payload(0 to get_payload_len-1)); begin if end_of_list = null then ret := NULL_PACKET; else ret := end_of_list.pi; ptr := end_of_list.next_packet; DEALLOCATE(end_of_list); end_of_list := ptr; ------------------------------------------------------------------------------------------- --The list has been emptied, so to prevent a null pointer reference, reset the start of --list too to prevent a dangling pointer ------------------------------------------------------------------------------------------- if end_of_list = null then start_of_list := null; end if; end if; return ret; end function get_packet; From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.66.157.138 with SMTP id wm10mr1714577pab.23.1400486526825; Mon, 19 May 2014 01:02:06 -0700 (PDT) X-Received: by 10.140.95.141 with SMTP id i13mr642953qge.3.1400486526710; Mon, 19 May 2014 01:02:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no1130904igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1130889igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 01:02:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Tricky Injection-Date: Mon, 19 May 2014 08:02:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7542 Doh must remember to syntax check first! ------------------------------------------------------------------ --Removes a packet from the FIFO Queue ------------------------------------------------------------------ impure function get_packet return packet_info_t is impure function get_payload_len return integer is begin if end_of_list= null then return 0; else return end_of_list.pi.payload'length; end if; end function get_payload_len; variable ptr : packet_ll_ptr_t := null; variable ret : packet_info_t( payload(0 to get_payload_len-1)); begin if end_of_list = null then ret := NULL_PACKET; else ret := end_of_list.pi; ptr := end_of_list.next_packet; DEALLOCATE(end_of_list); end_of_list := ptr; ------------------------------------------------------------------------------------------- --The list has been emptied, so to prevent a null pointer reference, reset the start of --list too to prevent a dangling pointer ------------------------------------------------------------------------------------------- if end_of_list = null then start_of_list := null; end if; end if; return ret; end function get_packet; From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.66.66.35 with SMTP id c3mr13613228pat.7.1400489588941; Mon, 19 May 2014 01:53:08 -0700 (PDT) X-Received: by 10.140.44.75 with SMTP id f69mr25274qga.11.1400489588783; Mon, 19 May 2014 01:53:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no1147329igb.0!news-out.google.com!qf4ni2875igc.0!nntp.google.com!hl10no1147326igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 01:53:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: demande plz From: Ayoub Injection-Date: Mon, 19 May 2014 08:53:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7543 Hi ! How are you ? Do you have an example of demodulation bpsk in vhdl ?! thank you in advance for your answer. From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.68.216.230 with SMTP id ot6mr16110437pbc.3.1400496776508; Mon, 19 May 2014 03:52:56 -0700 (PDT) X-Received: by 10.140.92.227 with SMTP id b90mr31901qge.25.1400496776345; Mon, 19 May 2014 03:52:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!c1no10382977igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10382970igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 03:52:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.67.100.228; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 94.67.100.228 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> Subject: Re: demande plz From: Nikolaos Kavvadias Injection-Date: Mon, 19 May 2014 10:52:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7544 Hi, I don't have one at hand, but I could develop one. From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.236.137.50 with SMTP id x38mr15323391yhi.9.1400497346056; Mon, 19 May 2014 04:02:26 -0700 (PDT) X-Received: by 10.140.101.111 with SMTP id t102mr637935qge.5.1400497345943; Mon, 19 May 2014 04:02:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no1195822igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10389931igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 04:02:25 -0700 (PDT) In-Reply-To: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <1ebdb1ed-8ecd-4991-a1e7-800acdcc8535@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Array VHDL From: Tricky Injection-Date: Mon, 19 May 2014 11:02:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7545 Well, for a start, you need to make S a std_logic_vector then you probably want a for loop around the xor A good tutorial will help. Or just pay nikolaos a small fortune On Wednesday, 14 May 2014 23:30:03 UTC+1, Ayoub wrote: > Hi everybody ! > > > > I have a small problemIo want to do a not xor for 4 input of 4 bit with input data > > 1 bit to have a 4 bit output using a table of input > > > > here is my code: > > > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.numeric_std.all; > > > > entity cdm is > > port ( > > clk : in std_logic ; > > rst : in std_logic ; > > data: in std_logic ; > > CD : in std_logic_vector(15 downto 0) ; > > S : out std_logic(3 downto 0 ); > > end entity ; > > > > architecture beh of cdm is > > > > signal i :integer range 0 to 3 ; > > signal idata :std_logic ; > > begin > > code :process(clk,rst) > > begin > > if(rst='1')then > > S<='0'; > > i<=0 ; > > idata<=data ; > > else > > if(clk'event and clk='1')then > > > > type tab is array(3 downto 0)of std_logic_vector > > ???? > > ?? > > > > S<=not(CD(i) xor (idata)); > > i<= i+1 ; > > if i=3 then > > idata<=data ; > > end if ; > > end if ; > > end if ; > > end process ; > > end architecture ; > > > > Thank you in advance for your answer !! From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.236.141.11 with SMTP id f11mr2804198yhj.54.1400507832733; Mon, 19 May 2014 06:57:12 -0700 (PDT) X-Received: by 10.182.247.2 with SMTP id ya2mr21116obc.20.1400507832445; Mon, 19 May 2014 06:57:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!hl10no1266723igb.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10507571igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 06:57:12 -0700 (PDT) In-Reply-To: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 References: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: demande plz From: Ayoub Injection-Date: Mon, 19 May 2014 13:57:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7546 On Monday, May 19, 2014 12:52:56 PM UTC+2, Nikolaos Kavvadias wrote: > Hi, I don't have one at hand, but I could develop one. Hi , Good ;I go to see ; because I want to have just an idea Knowing that I want to make the bpsk demodulating . Thank you . From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.182.213.37 with SMTP id np5mr16785439obc.36.1400511329552; Mon, 19 May 2014 07:55:29 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr56699qgt.17.1400511329426; Mon, 19 May 2014 07:55:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no10551281igq.0!news-out.google.com!qf4ni2017igc.0!nntp.google.com!c1no10551279igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 May 2014 07:55:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4157474d-c812-40f3-967f-7a85f9e1acac@googlegroups.com> Subject: Array of Modulation BPSK From: Ayoub Injection-Date: Mon, 19 May 2014 14:55:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7547 Hi everybody ! I want to add(xor) data with CD in shape array and the result would be S Can you help me correcting this code : """" library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdm is --generic ( -- width : natural :=4); port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; odata: out std_logic ; CD : in std_logic_vector(15 downto 0) ; isis :out integer range 0 to 15 ; S : inout std_logic_vector(3 downto 0 )); end entity ; architecture beh of cdm is type tab is array(3 downto 0)of std_logic_vector(15 downto 0); signal i :integer range 0 to 15 ; signal idata :std_logic ; signal itab :tab ; begin code :process(clk,rst) begin if(rst='1')then itab(i)<="0000" ; else if(clk'event and clk='1')then S(i)<=(CD(i) xor (data)); i<= i+1 ; if i=15 then idata<=data ; end if ; end if ; end if ; end process ; isis<=i; odata<=idata ; end architecture ; "" Thank you in advance for your answer !!!^^ From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.66.231.68 with SMTP id te4mr17570381pac.29.1400606376096; Tue, 20 May 2014 10:19:36 -0700 (PDT) X-Received: by 10.140.97.119 with SMTP id l110mr44175qge.21.1400606375918; Tue, 20 May 2014 10:19:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl10no1790742igb.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no11385206igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 May 2014 10:19:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.203.78.247; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.203.78.247 References: <368ec752-043a-40f4-8dea-56cb9bbe3c03@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ca57374-1fdc-4b37-8b14-e787e5c3939a@googlegroups.com> Subject: Re: demande plz From: Nikolaos Kavvadias Injection-Date: Tue, 20 May 2014 17:19:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7548 Dear Ayoub, > > Hi, I don't have one at hand, but I could develop one. > > Good ;I go to see ; > because I want to have just an idea I mean that I *could* develop one, given a specific precondition. Best regards Nikolaos Kavvadias http://www.nkavvadias.com > > > > Knowing that I want to make the bpsk demodulating . > > > > Thank you . From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.66.216.161 with SMTP id or1mr24465213pac.38.1400687640819; Wed, 21 May 2014 08:54:00 -0700 (PDT) X-Received: by 10.140.80.5 with SMTP id b5mr59225qgd.20.1400687640700; Wed, 21 May 2014 08:54:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no12920273igq.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no12920262igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 May 2014 08:54:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <679614bb-e568-418b-868c-2860a9889866@googlegroups.com> Subject: code vhdl From: Ayoub Injection-Date: Wed, 21 May 2014 15:54:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7549 Hi guys ! Can you help me correcting this code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdma_testbipo is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic ; odata: out std_logic ; type Re is array(0 to 3)of integer range 0 to 15; signal CD: Re ; isis :out integer range 0 to 3 ; S :out integer range -8 to 7 ); end entity ; architecture beh of cdma_testbipo is type RAM is array (0 to 3) of integer range -8 to 7; signal i :integer range 0 to 3 ; signal code : RAM; signal idata :std_logic ; begin code(0)<=CD(15 downto 12); code(1)<=CD(11 downto 8) ; code(2)<=CD(7 downto 4) ; code(3)<=CD(3 downto 0) ; bpsk :process(clk,rst) begin if(rst='1')then i<= 0; else if(clk'event and clk='1')then i<=i+1 ; if(idata='0') then s<=-code(i); else s<=code(i); end if; if(i=3) then idata<=data; end if; end if ; end if ; end process ; isis<=i; odata<=idata ; end architecture ; I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15; signal CD: Re ; "" Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" "" Thank you :! From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: code vhdl Date: Wed, 21 May 2014 09:31:33 -0700 Organization: Highland Technology, Inc. Lines: 94 Message-ID: <20140521093133.2ce99a1c@rg.highlandtechnology.com> References: <679614bb-e568-418b-868c-2860a9889866@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="fb1f8d326b6b433116d0372735136b8e"; logging-data="15492"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nIo+HsQvrZx55ZXPXICxb" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:GWlMRpkkgPSv4I+4V9THKqqny8w= Xref: news.eternal-september.org comp.lang.vhdl:7550 On Wed, 21 May 2014 08:54:00 -0700 (PDT) Ayoub wrote: > Hi guys ! > > > Can you help me correcting this code : > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity cdma_testbipo is > > port ( > clk : in std_logic ; > rst : in std_logic ; > data: in std_logic ; > odata: out std_logic ; > type Re is array(0 to 3)of integer range 0 to 15; > signal CD: Re ; > isis :out integer range 0 to 3 ; > S :out integer range -8 to 7 ); > end entity ; > > architecture beh of cdma_testbipo is > > type RAM is array (0 to 3) of integer range -8 to 7; > signal i :integer range 0 to 3 ; > signal code : RAM; > signal idata :std_logic ; > > begin > > code(0)<=CD(15 downto 12); > code(1)<=CD(11 downto 8) ; > code(2)<=CD(7 downto 4) ; > code(3)<=CD(3 downto 0) ; > bpsk :process(clk,rst) > begin > if(rst='1')then > i<= 0; > else > if(clk'event and clk='1')then > > i<=i+1 ; > if(idata='0') then > s<=-code(i); > else > s<=code(i); > end if; > > if(i=3) then > idata<=data; > end if; > > end if ; > end if ; > end process ; > isis<=i; > > odata<=idata ; > end architecture ; > > > I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15; > signal CD: Re ; "" > > Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" "" > > Thank you :! A) You can't declare a type inside of a port list. A type that you need to in in a port list should be in a separate package. B) "clk'event and clk == '1'" is ancient style. You weren't even born yet when they added the rising_edge() function to the standard library. For the love of god use it. C) Whatever it is you're trying to do with "CD" and "code" is so tangled and full of misunderstandings of the language that I can't even begin to guess what it is you think it SHOULD accomplish. But an unresolved signal, such as an integer, can only have one driver. It can be in a process, or in a freefloating statement (which is just a shorthand for a process), but you can't do it in both. D) Pertinent to C, your code is entirely devoid of documentation. Therefore, not only won't you know what you're doing, but no one will know what you're doing. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: o pere o Newsgroups: comp.lang.vhdl Subject: Re: Writing testbench tools. Suggestions? Date: Thu, 22 May 2014 10:35:00 +0200 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 22 May 2014 08:35:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="d50e3f26ee7886ceb9de424a7ed3d9fe"; logging-data="15307"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/SR4SrkfLODXSNNCKQa5fJ" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Cancel-Lock: sha1:RQUH0zUR2y7cOEAA9204VXfzwtg= Xref: news.eternal-september.org comp.lang.vhdl:7551 On 05/14/2014 11:41 AM, Paul Uiterlinden wrote: > o pere o wrote: > >> I am trying to write some helper tools to generate testbench signals. > [snip] >> >> I would appreciate any suggestion on this. Especially, if I am making >> big mistakes! Furthermore, I have been unable to find functions that >> ease the generation of test signals, say to simulate some bursts of an >> SPI master or whatever, which is why I am writing this stuff. Any >> pointers on this? > > I would suggest reading a book like "Writing Testbenches" by Janick Bergeron > and look at the client/server model suggested there. Thanks for this pointer. I just had the opportunity to have a quick look at this book and it looks *very* promising. OTOH, I just keep wondering why there is so little material on this subject out there... Especially considering that a lot of the development effort is spent here -Janick Bargeron even puts figures into this in the book's preface: reportedly, 60% to 80% of the design effort goes into verification... Pere From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx33.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: PSHDL Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140521-1, 21/05/2014), Outbound message X-Antivirus-Status: Clean Lines: 14 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1400767856 86.29.12.221 (Thu, 22 May 2014 14:10:56 UTC) NNTP-Posting-Date: Thu, 22 May 2014 14:10:56 UTC Organization: virginmedia.com Date: Thu, 22 May 2014 15:10:54 +0100 X-Received-Body-CRC: 304460096 X-Received-Bytes: 1168 Xref: news.eternal-september.org comp.lang.vhdl:7552 For those that haven't seen it: http://pshdl.org/ Here is some more info on the project: http://www.youtube.com/watch?v=nTg6f6NGbZg Looks like good effort to me although I would have preferred if he used VHDL rather than developing a new language, nevertheless he gets some kudos from me. Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.236.19.7 with SMTP id m7mr12282350yhm.35.1400774587817; Thu, 22 May 2014 09:03:07 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr1149418qgr.0.1400774587663; Thu, 22 May 2014 09:03:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no3513040igb.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no13738487igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 May 2014 09:03:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.50.193.72; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 193.50.193.72 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Demodulator bpsk From: Ayoub Injection-Date: Thu, 22 May 2014 16:03:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7553 Hi guys ! Do you have in idea about demodulator bpsk in VHDL ! I'm not sure where to begin . Thank you in advance for your reponse From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.67.30.197 with SMTP id kg5mr456196pad.36.1400798163563; Thu, 22 May 2014 15:36:03 -0700 (PDT) X-Received: by 10.140.37.148 with SMTP id r20mr12830qgr.0.1400798163428; Thu, 22 May 2014 15:36:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no14215208igq.0!news-out.google.com!qf4ni5721igc.0!nntp.google.com!c1no14215199igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 May 2014 15:36:03 -0700 (PDT) In-Reply-To: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <53733a3f$0$27127$e4fe514c@dreader35.news.xs4all.nl> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c70ab1d-7153-4a0c-8032-7101b2344cb8@googlegroups.com> Subject: Re: Writing testbench tools. Suggestions? From: Andy Injection-Date: Thu, 22 May 2014 22:36:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7554 On Wednesday, May 14, 2014 4:41:19 AM UTC-5, Paul Uiterlinden wrote: > I would suggest reading a book like "Writing Testbenches" by Janick Berge= ron and look at the client/server model suggested there. -- Paul Uiterlinde= n www.aimvalley.nl Excellent book recommendation! However, the second edition was revised to c= over more SystemVerilog, at the expense of VHDL/Verilog. The first edition = (light blue cover, rather than red for the 2nd edition) is just VHDL & veri= log, and more appropriate if you are working on VHDL testbenches. Jim Lewis/Synthworks has an excellent advanced VHDL verification class, and= his freely available Open Source VHDL Verification Methodology (OSVVM.org)= is a huge step in the right direction. Other than being a very satisfied s= tudent, I have no connection with Synthworks.=20 The use of protected types/methods is extremely powerful for testbenches (t= oo bad they are not synthesizeable yet). The constrained randomization and = coverage packages in OSVVM provide great examples to illustrate some of the= uses of protected types. Andy From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.236.140.42 with SMTP id d30mr15198813yhj.2.1401252681180; Tue, 27 May 2014 21:51:21 -0700 (PDT) X-Received: by 10.50.61.170 with SMTP id q10mr335543igr.16.1401252681088; Tue, 27 May 2014 21:51:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no18799926igq.0!news-out.google.com!gi6ni15574igc.0!nntp.google.com!hl10no6598309igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 27 May 2014 21:51:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=196.1.105.91; posting-account=LIltwAoAAABu4LbjMvWqcvikTJr4Qyzo NNTP-Posting-Host: 196.1.105.91 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Subject: Parallel load register 4 bit without using instantiation From: chirag.nitb@gmail.com Injection-Date: Wed, 28 May 2014 04:51:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7555 Need to design a 4 bit register with parallel loading using D flip flop . I= wrote the following code in xilinx but the simulation shows an undefined s= tate and the code does not work if the initial values of the out put are se= t to zero . Please help correcting the code=20 Here is the code=20 ---------------------------------------------------------------------------= ------- -- Company:=20 -- Engineer:=20 --=20 -- Create Date: 14:06:13 05/27/2014=20 -- Design Name:=20 -- Module Name: code - Behavioral=20 -- Project Name:=20 -- Target Devices:=20 -- Tool versions:=20 -- Description:=20 -- -- Dependencies:=20 -- -- Revision:=20 -- Revision 0.01 - File Created -- Additional Comments:=20 -- ---------------------------------------------------------------------------= ------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity code is Port ( din : in STD_LOGIC_VECTOR (3 downto 0); dout :inout STD_LOGIC_VECTOR (3 downto 0):=3D"0000"; rd,clk,rst : in STD_LOGIC); end code; architecture registerdesign of code is signal wr: STD_LOGIC; signal OPA_0, OPA_1, OPA_2, OPA_3: STD_LOGIC; signal OPB_0, OPB_1, OPB_2, OPB_3: STD_LOGIC; signal FOP_0, FOP_1, FOP_2, FOP_3: STD_LOGIC; begin wr <=3D not(rd); OPA_0 <=3D rd and dout(0); OPA_1 <=3D rd and dout(1); OPA_2 <=3D rd and dout(2); OPA_3 <=3D rd and dout(3); OPB_0 <=3D wr and din(0); OPB_1 <=3D wr and din(1); OPB_2 <=3D wr and din(2); OPB_3 <=3D wr and din(3); FOP_0 <=3D OPA_0 or OPB_0; FOP_1 <=3D OPA_1 or OPB_1; FOP_2 <=3D OPA_2 or OPB_2; FOP_3 <=3D OPA_3 or OPB_3; process(clk,rst) begin if (rst=3D'1')then dout <=3D"0000"; =09 else=20 if(clk'event and clk=3D'1')then dout(0)<=3D FOP_0; dout(1)<=3D FOP_1; dout(2)<=3D FOP_2; dout(3)<=3D FOP_3; end if; =20 end if; end process; end registerdesign; From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Parallel load register 4 bit without using instantiation Date: Wed, 28 May 2014 02:40:55 -0400 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 May 2014 06:40:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="6601"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/D2who6uYQlLjweETF/B4P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <4f8a4204-46e0-4132-b207-34fb8ef1f4cc@googlegroups.com> Cancel-Lock: sha1:h3jTP0iY5Amqm5JrVFegn2BeoTI= Xref: news.eternal-september.org comp.lang.vhdl:7556 On 5/28/2014 12:51 AM, chirag.nitb@gmail.com wrote: > Need to design a 4 bit register with parallel loading using D flip flop . I wrote the following code in xilinx but the simulation shows an undefined state and the code does not work if the initial values of the out put are set to zero . Please help correcting the code > > > Here is the code > > ---------------------------------------------------------------------------------- > -- Company: > -- Engineer: > lol, the -- at the beginning of a line in your code made the newsreader think it was the start of the signature. Your code will only reset the FFs if rst is equal to '1'. Do you set rst = '1' in your simulation? I don't see anything wrong with the code for the register. I would recommend that you use rising_edge(clk) rather than the clk'event, etc. but that won't cause a failure. Also, the use of these libraries is *not* recommended... use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Use numeric_std instead. If you want to know more about these recommendations, do some google searches and come back if you still have questions. -- Rick From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.58.234.164 with SMTP id uf4mr15602573vec.13.1401262639110; Wed, 28 May 2014 00:37:19 -0700 (PDT) X-Received: by 10.140.27.244 with SMTP id 107mr14136qgx.18.1401262638990; Wed, 28 May 2014 00:37:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl10no6638442igb.0!news-out.google.com!gi6ni15574igc.0!nntp.google.com!hl10no6638434igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 00:37:18 -0700 (PDT) In-Reply-To: <3667EF03.D7CFC73@techno.forem.be> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.13.72.195; posting-account=YN8QFwoAAABAPoRKu1qtT_1G9FlRfdVL NNTP-Posting-Host: 129.13.72.195 References: <3667EF03.D7CFC73@techno.forem.be> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Subject: Re: GPS and DCF-77, synchronised clock From: suhas sajjan Injection-Date: Wed, 28 May 2014 07:37:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7557 On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: > Hello, > > I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 > signal (an AM signal at 77.5kHz emitted in Frankfurt used for > synchronisation). > I want to do a synchronised clock on an IC, I need any information on > this subject. > Thank you for your attention. > > Gaetan Brichet > Student at the University of Liege - Belgium > brichet@stud.montefiore.ulg.ac.be Hi George, Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? Regards, Suhas Sajjan From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: GPS and DCF-77, synchronised clock Date: Wed, 28 May 2014 04:01:08 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 May 2014 08:01:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="4133"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19nfZDQDmkK5CyRh74VZq/J" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Cancel-Lock: sha1:5V2zUVnYnK/3SluRO284AtupBLQ= Xref: news.eternal-september.org comp.lang.vhdl:7558 On 5/28/2014 3:37 AM, suhas sajjan wrote: > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >> Hello, >> >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >> synchronisation). >> I want to do a synchronised clock on an IC, I need any information on >> this subject. >> Thank you for your attention. >> >> Gaetan Brichet >> Student at the University of Liege - Belgium >> brichet@stud.montefiore.ulg.ac.be > > Hi George, > > Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? I have not looked at DCF-77 in detail, but I believe it is very similar to the time code transmitted by NIST in the US which I am familiar with. I have designed a decoder/encoder for the IRIG-B signal which is again very similar. I can't share any of the code, but I can offer you some advice in how to proceed. You might want to be aware of two things. One is that there are commercial chips which do exactly this. I believe they are complete receivers needing only passive devices to form the antenna. The one I am thinking of decodes the US and German signals as well as the related Japanese signal. So why reinvent the wheel? Is this a project for a class rather than development of a product? btw, GPS will be a much harder task than the simple audio time codes. -- Rick From newsfish@newsfish Tue Dec 29 16:43:26 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.tele2net.at!news.panservice.it!feed.xsnews.nl!border02.ams.xsnews.nl!feeder01.ams.xsnews.nl!abuse.newsxs.nl!not-for-mail Newsgroups: comp.lang.vhdl From: Stef Subject: Re: GPS and DCF-77, synchronised clock References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> Mail-Copies-To: nobody User-Agent: slrn/0.9.8.1pl1 (Linux) Message-ID: X-Complaints-To: abuse@newsxs.nl Organization: Newsxs Date: Wed, 28 May 2014 10:11:24 +0200 Lines: 35 X-Upload: Secured through NewsXS SSL NNTP-Posting-Date: Wed, 28 May 2014 10:11:24 +0200 Xref: news.eternal-september.org comp.lang.vhdl:7559 In comp.lang.vhdl, suhas sajjan wrote: > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >> Hello, >> >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-77 >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >> synchronisation). >> I want to do a synchronised clock on an IC, I need any information on >> this subject. >> Thank you for your attention. >> >> Gaetan Brichet >> Student at the University of Liege - Belgium >> brichet@stud.montefiore.ulg.ac.be > > Hi George, > > Do you have any idea regarding this project.I am doing the same and i m in need of VHDL for decoding dcf77 time signal and display it on a nixie tube which is like a 8 segment dispaly? > > Regards, > Suhas Sajjan I hope he has finished his study project after 15 1/2 years! For information about DCF77, start reading here: http://en.wikipedia.org/wiki/DCF77 Also have a look at the external links. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "I found out why my car was humming. It had forgotten the words." From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.58.218.232 with SMTP id pj8mr15727417vec.3.1401268800049; Wed, 28 May 2014 02:20:00 -0700 (PDT) X-Received: by 10.140.104.52 with SMTP id z49mr22418qge.12.1401268799941; Wed, 28 May 2014 02:19:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!c1no18941173igq.0!news-out.google.com!qf4ni13600igc.0!nntp.google.com!c1no18941170igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 02:19:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.73.199.96; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 85.73.199.96 References: <3667EF03.D7CFC73@techno.forem.be> <06b3753f-3bf3-49ef-b3ac-951acba0dd4b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54430c68-0161-4182-9b8e-2c586e9a88e0@googlegroups.com> Subject: Re: GPS and DCF-77, synchronised clock From: Nikolaos Kavvadias Injection-Date: Wed, 28 May 2014 09:19:59 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7560 Hi Suhan and all, around 2012 I had implemented both a DCF77 and an MSF decoder in RTL-style = VHDL. (for the UK and German signals) The design had been put to work with success on a specific lab facility. I think there is no such open-source core, so it possible that you might be= interested. Best regards Nikolaos Kavvadias http://www.nkavvadias.com =CE=A4=CE=B7 =CE=A4=CE=B5=CF=84=CE=AC=CF=81=CF=84=CE=B7, 28 =CE=9C=CE=B1=CE= =90=CE=BF=CF=85 2014 11:11:24 =CF=80.=CE=BC. UTC+3, =CE=BF =CF=87=CF=81=CE= =AE=CF=83=CF=84=CE=B7=CF=82 Stef =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > In comp.lang.vhdl, >=20 > suhas sajjan wrote: >=20 > > On Friday, 4 December 1998 09:00:00 UTC+1, Georges wrote: >=20 > >> Hello, >=20 > >>=20 >=20 > >> I'm looking for vhdl programs for decoding the GPS signal or the DCF-7= 7 >=20 > >> signal (an AM signal at 77.5kHz emitted in Frankfurt used for >=20 > >> synchronisation). >=20 > >> I want to do a synchronised clock on an IC, I need any information on >=20 > >> this subject. >=20 > >> Thank you for your attention. >=20 > >>=20 >=20 > >> Gaetan Brichet >=20 > >> Student at the University of Liege - Belgium >=20 > >> brichet@stud.montefiore.ulg.ac.be >=20 > > >=20 > > Hi George, >=20 > > >=20 > > Do you have any idea regarding this project.I am doing the same and i m= in need of VHDL for decoding dcf77 time signal and display it on a nixie t= ube which is like a 8 segment dispaly? >=20 > > >=20 > > Regards, >=20 > > Suhas Sajjan >=20 >=20 >=20 > I hope he has finished his study project after 15 1/2 years! >=20 >=20 >=20 > For information about DCF77, start reading here: >=20 > http://en.wikipedia.org/wiki/DCF77 >=20 > Also have a look at the external links. >=20 >=20 >=20 >=20 >=20 >=20 >=20 > --=20 >=20 > Stef (remove caps, dashes and .invalid from e-mail address to reply by= mail) >=20 >=20 >=20 > "I found out why my car was humming. It had forgotten the words." Hi, From newsfish@newsfish Tue Dec 29 16:43:26 2015 X-Received: by 10.43.31.81 with SMTP id sf17mr1347437icb.4.1401319890567; Wed, 28 May 2014 16:31:30 -0700 (PDT) X-Received: by 10.140.107.35 with SMTP id g32mr68560qgf.2.1401319890477; Wed, 28 May 2014 16:31:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7040758igb.0!news-out.google.com!qf4ni13600igc.0!nntp.google.com!c1no19521600igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 16:31:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.82.92; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.82.92 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Wed, 28 May 2014 23:31:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7561 Hi, thanks a lot for the help, I managed to understand a lot and perform some simulations with success. I followed the flow chart and got the correct sequences on the logic analyser for the transmission (MOSI) Now I have this dilemma on how to amalgamate the DRDY pin of the ADC mentioned: http://datasheets.maximintegrated.com/en/ds/MAX1415-MAX1416.pdf page. 29 is the flow chart with the SPI code found here: https://www.eewiki.net/display/LOGIC/Serial+Peripheral+Interface+(SPI)+Master+(VHDL) If I understand correctly, this is used mainly when reading from MISO. Is it a good idea to use DRDY as an enable for SCLK in order to wait for the data to be ready? Or is there a better way? thanks On Thursday, 1 May 2014 13:12:23 UTC+2, Brandon Spiteri wrote: > Hi, > > I have managed to transmit some character (one after the other) using this code from; > > > > http://eewiki.net/pages/viewpage.action?pageId=4096096 > > > > I used continuous mode and I got the right characters on MOSI, one after the other, the only thing is that there are 4 clock cycles of high impedance between each 8-bit char. Is this oki? > > > > I am planning to interface with MAX1416 ADC. > > > > > > Also, I need to simulate an SPI input coming from the ADC. What is the best way to do it? > > > > Shall I use the same method I used for transmitting but this time in the test bench? > > > > I am using quartus and ModelSim. > > > > thanks From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.42.206.77 with SMTP id ft13mr1559816icb.22.1401326773956; Wed, 28 May 2014 18:26:13 -0700 (PDT) X-Received: by 10.182.63.7 with SMTP id c7mr1411obs.28.1401326773631; Wed, 28 May 2014 18:26:13 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hl10no7068214igb.0!news-out.google.com!qf4ni17234igc.0!nntp.google.com!c1no19574040igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 May 2014 18:26:13 -0700 (PDT) In-Reply-To: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Thu, 29 May 2014 01:26:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7562 I would suggest that you use DRDY as an input to the 'user logic' that drives the SPI controller. It should not be used to directly modify SCLK, that defeats the purpose of re-using an existing design. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.182.22.133 with SMTP id d5mr2466931obf.27.1401352567583; Thu, 29 May 2014 01:36:07 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr13458qgt.17.1401352567476; Thu, 29 May 2014 01:36:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c1no19791027igq.0!news-out.google.com!qf4ni17234igc.0!nntp.google.com!c1no19791021igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 01:36:07 -0700 (PDT) In-Reply-To: <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.11.82.92; posting-account=oFi9ygoAAABxAvsC17BaL45PeFFVCoGH NNTP-Posting-Host: 46.11.82.92 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: Brandon Spiteri Injection-Date: Thu, 29 May 2014 08:36:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7563 thanks for the fast reply. What do you think of this modification of spi.vhdl with DRDY ? WHEN execute => busy <= '1'; --set busy signal ss_n(slave) <= '0'; --set proper slave select output --system clock to sclk ratio is met IF(count = clk_ratio) THEN count <= 1; --reset system-to-spi clock counter assert_data <= NOT assert_data; --switch transmit/receive indicator IF(clk_toggles = d_width*2 + 1) THEN -- (==17) clk_toggles <= 0; --reset spi clock toggles counter ELSE clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter END IF; --spi clock toggle needed IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN sclk <= NOT sclk; --toggle spi clock END IF; --receive spi clock toggle IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0' AND DRDY = '0') THEN rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit END IF; --transmit spi clock toggle IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN mosi <= tx_buffer(d_width-1); --clock out data bit tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer END IF; --last data receive, but continue IF(clk_toggles = last_bit_rx AND cont = '1' AND DRDY = '0') THEN tx_buffer <= tx_data; --reload transmit buffer clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter continue <= '1'; --set continue flag END IF; --normal end of transaction, but continue IF(continue = '1') THEN continue <= '0'; --clear continue flag busy <= '0'; --clock out signal that first receive data is ready rx_data <= rx_buffer; --clock out received data to output port END IF; --end of transaction IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN busy <= '0'; --clock out not busy signal ss_n <= (OTHERS => '1'); --set all slave selects high mosi <= 'Z'; --set mosi output high impedance rx_data <= rx_buffer; --clock out received data to output port state <= ready; --return to ready state ELSE --not end of transaction state <= execute; --remain in execute state END IF; ELSE --system clock to sclk ratio not met count <= count + 1; --increment counter state <= execute; --remain in execute state END IF; On Thursday, 29 May 2014 03:26:13 UTC+2, KJ wrote: > I would suggest that you use DRDY as an input to the 'user logic' that drives the SPI controller. It should not be used to directly modify SCLK, that defeats the purpose of re-using an existing design. > > > > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.182.109.231 with SMTP id hv7mr3557236obb.2.1401381393299; Thu, 29 May 2014 09:36:33 -0700 (PDT) X-Received: by 10.140.96.41 with SMTP id j38mr180091qge.8.1401381393040; Thu, 29 May 2014 09:36:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7376417igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20116983igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 09:36:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.193.64.121; posting-account=kAX7RQoAAACtFFhwlRbLNk9NJBz9PTm8 NNTP-Posting-Host: 46.193.64.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Subject: Multiplication VHDL From: Ayoub Injection-Date: Thu, 29 May 2014 16:36:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7564 Hi, I have problems with my vhdl code.=20 can you help me plz=20 This is the code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity correla is port ( clk : in std_logic ; rst : in std_logic ; data: in std_logic_vector(11 downto 0) ; code: in std_logic_vector(15 downto 0 ) ; =20 Q :out std_logic_vector(17 downto 0) ) ; end entity ; architecture arch of correla is =20 =20 type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ; signal CD : RAM; signal temp :integer range 0 to 15; =20 signal idata :std_logic_vector(11 downto 0) ; signal sum :integer range 0 to 16 ; signal AB :integer range 0 to 17 ; =20 begin =20 CD(0)<=3D(code(15 downto 12)); CD(1)<=3D(code(11 downto 8)) ; CD(2)<=3D(code(7 downto 4 )); CD(3)<=3D(code(3 downto 0)); =20 =E9talement:process(clk,rst) =20 begin=20 if(rst=3D'1') then=20 Q <=3D(others=3D>'0'); =20 temp<=3D0; AB <=3D0; =20 else=20 if(clk'event and clk =3D'1') then=20 sum<=3D0; =20 for i in 0 to 3 loop=20 temp(i)<=3Dto_integer(data(i)*CD(i)) ; sum(i)<=3Dsum(i) +temp(i) ; i<=3D i+1 ; if(i=3D3) then=20 idata<=3Ddata; end if; end loop ; =20 AB<=3Dsum ; Q<=3Dstd_logic_vector(AB) ; =20 =20 =20 end if ; end if ; =20 =20 =20 =20 end process ; end architecture ;=20 Thanks a lot=20 From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.144.136 with SMTP id n8mr3641983yhj.22.1401396954096; Thu, 29 May 2014 13:55:54 -0700 (PDT) X-Received: by 10.50.142.104 with SMTP id rv8mr571847igb.13.1401396953962; Thu, 29 May 2014 13:55:53 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl10no7492176igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20289757igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 13:55:53 -0700 (PDT) In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiplication VHDL From: Jim Lewis Injection-Date: Thu, 29 May 2014 20:55:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7565 Ayoub It looks like you are doing a college exercise. Multiplication is nothing more than Y <= A * B ; If you need some help with that or with pipelining, see the papers, "VHDL Math tricks of the Trade" and "Coding a 40 x 40 Multipler" at http://www.synthworks.com/papers/index.htm Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.19.7 with SMTP id m7mr2603506yhm.35.1401397359296; Thu, 29 May 2014 14:02:39 -0700 (PDT) X-Received: by 10.50.25.4 with SMTP id y4mr283914igf.10.1401397359157; Thu, 29 May 2014 14:02:39 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl10no7495252igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20294035igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 14:02:38 -0700 (PDT) In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <61b9f7fe-3db5-46a1-93a6-9a78bb9f3e24@googlegroups.com> Subject: Re: Multiplication VHDL From: Jim Lewis Injection-Date: Thu, 29 May 2014 21:02:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7566 Ayoub The objects temp, data, and sum are not arrays. If you did not intend to index these and instead you intended the scalar value to update between iterations of your for loop, then they will need to be variables. Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.182.58.71 with SMTP id o7mr5046963obq.3.1401413802942; Thu, 29 May 2014 18:36:42 -0700 (PDT) X-Received: by 10.182.137.129 with SMTP id qi1mr981obb.37.1401413802765; Thu, 29 May 2014 18:36:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no7569982igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no20426640igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 May 2014 18:36:42 -0700 (PDT) In-Reply-To: <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1a56e251-8955-45fb-8d37-82302a8a77d1@googlegroups.com> <101eea39-688c-48cf-8d5f-2881712bd4f0@googlegroups.com> <692f46df-8211-46b4-89ac-4c2b6e2c2f45@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <11d5751f-8830-4cea-bf43-2ca28b7ac699@googlegroups.com> Subject: Re: SPI; simulating an input (rx) From: KJ Injection-Date: Fri, 30 May 2014 01:36:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7567 On Thursday, May 29, 2014 4:36:07 AM UTC-4, Brandon Spiteri wrote: > thanks for the fast reply. What do you think of this modification of spi.= vhdl=20 > with DRDY ? >=20 I think=20 - You completely ignored my suggestion to use DRDY as an input to the 'user= logic' that drives the SPI controller. - Assuming you started from known working SPI controller code, you've hobbl= ed it at best to make it into something that will only work under very spec= ial circumstances. Had you followed my suggestion, your new code would be generating the follo= wing outputs from a 'User_Logic' entity: - Enable, Addr and Tx_Data. How these are generated could be made to be a = function of Drdy. - You would likely have to only define constants for the following outputs:= cpol, cpha, cont and clk_div. The 'User_Logic' entity would then be connected to the 'Spi_Master' entity.= Then as you think of other requirements you would modify 'User_Logic' som= e more until everything is working properly. Some modifications like: - What should you do if DRDY never comes back? You have no timeout, probab= ly a hard reset is the only escape - Do you really want every SPI operation to depend on DRDY? The basic idea is that if you have some known working code for some widget,= and you modify it, you're more likely to break it then to improve it if yo= u didn't write it yourself in the first place. Instead, you should present= an interface to the widget (i.e. the entity) that encourages one to use th= e widget, not modify the widget. The SPI_Master interface looks like it pr= esented a simple address/data interface with handshaking that would be fair= ly easy to understand then simply use. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.99.7 with SMTP id w7mr7133984yhf.4.1401501207243; Fri, 30 May 2014 18:53:27 -0700 (PDT) X-Received: by 10.50.73.98 with SMTP id k2mr28779igv.0.1401501207145; Fri, 30 May 2014 18:53:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl10no8064879igb.0!news-out.google.com!gi6ni17440igc.0!nntp.google.com!hl10no8064871igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 May 2014 18:53:26 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=205.175.97.117; posting-account=IgXoAQkAAABjWBXMvqT0qPYUz09IMzj4 NNTP-Posting-Host: 205.175.97.117 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Subject: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? From: kaiyutony@gmail.com Injection-Date: Sat, 31 May 2014 01:53:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7568 Any Help Will Be Appreciated! I wrote this module in order to keep track of the score (<=3D 99) for a gam= e written in verilog and runs on a LED Array. I want it to be able to maint= ain a max score. When the current count is greater than maxcount, the maxco= unt will be equal to the current count, else it keeps its value. The Problem is, I do not know why the maxcount changes its value whenever c= ount changes (It cannot keep its value when count is less, but instead beco= me less along with the count) Is there any logical error? Or is there any Verilog Error that I missed? Thank you very much! module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, h= ex2); input Clock, Reset; input signed [3:0] pt_0, pt_1, pt_2, pt_3; output [6:0] hex1, hex0, hex3, hex2; wire signed [6:0] count; wire signed [6:0] maxcount; score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount= ); display(count, maxcount, hex1, hex0, hex3, hex2); endmodule=20 module display (count, maxcount, hex1, hex0, hex3, hex2); input [6:0] count, maxcount; output [6:0] hex1, hex0, hex3, hex2; wire [4:0] unit, unit_m; wire [4:0] tens, tens_m; assign unit =3D count % 10; assign tens =3D count / 10; assign unit_m =3D count % 10; assign tens_m =3D count / 10; seg7 ud (unit, hex0); seg7 td (tens, hex1); seg7 umd (unit_m, hex2); seg7 tmd (tens_m, hex3); endmodule=20 module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount)= ; input Clock, Reset; //input signed [3:0] sum; input [3:0] pt_0, pt_1, pt_2, pt_3; parameter signed [3:0] no_point =3D 4'b0000, plus_one =3D 4'b0001, plus= _two =3D 4'b0010, neg_two =3D 4'b1110; //input zero, negative, carry, overflow; output signed [6:0] count, maxcount; reg signed [6:0] count, maxcount; ////wire PS; //reg NS; always @(posedge Clock) if (Reset) begin count <=3D 7'b0; maxcount <=3D 7'b0; end else begin if (count > maxcount) begin maxcount <=3D count; end=20 if (pt_0 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_0; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_1 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_1; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_2 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_2; if (count > 7'b100010) begin count <=3D 7'b0; end end if (pt_3 =3D=3D neg_two) begin if (count < 2) begin count <=3D 7'b0; end else begin count <=3D count - 2; end end else begin count <=3D count + pt_3; if (count > 7'b100010) begin count <=3D 7'b0; end end end endmodule From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sat, 31 May 2014 01:39:52 -0400 Organization: A noiseless patient Spider Lines: 135 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 31 May 2014 05:39:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="31857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MF956QYhRry/O/elFbX9p" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Cancel-Lock: sha1:dQJRdAwi/mvQMILWrYg2KEeUUbc= Xref: news.eternal-september.org comp.lang.vhdl:7569 I'm not an expert in Verilog, but I don't see anything obvious in the code. I do see two possible issues. One is that maxcount is passed into display, but not used for anything. Are unit_m and tens_m supposed to be updated from maxcount? Is that where you are checking the value of maxcount? The other is that maxcount is declared as both an output and a reg. In VHDL that does not work. Is that ok in Verilog? Rick On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote: > Any Help Will Be Appreciated! > > I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value. > > The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count) > > Is there any logical error? Or is there any Verilog Error that I missed? > > Thank you very much! > > module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2); > input Clock, Reset; > input signed [3:0] pt_0, pt_1, pt_2, pt_3; > output [6:0] hex1, hex0, hex3, hex2; > > wire signed [6:0] count; > wire signed [6:0] maxcount; > score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > > display(count, maxcount, hex1, hex0, hex3, hex2); > > endmodule > > module display (count, maxcount, hex1, hex0, hex3, hex2); > input [6:0] count, maxcount; > output [6:0] hex1, hex0, hex3, hex2; > > wire [4:0] unit, unit_m; > wire [4:0] tens, tens_m; > > assign unit = count % 10; > assign tens = count / 10; > > assign unit_m = count % 10; > assign tens_m = count / 10; > > seg7 ud (unit, hex0); > seg7 td (tens, hex1); > seg7 umd (unit_m, hex2); > seg7 tmd (tens_m, hex3); > > > endmodule > > module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > input Clock, Reset; > //input signed [3:0] sum; > input [3:0] pt_0, pt_1, pt_2, pt_3; > parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110; > //input zero, negative, carry, overflow; > > output signed [6:0] count, maxcount; > reg signed [6:0] count, maxcount; > > ////wire PS; > //reg NS; > > always @(posedge Clock) > if (Reset) begin > count <= 7'b0; > maxcount <= 7'b0; > end else begin > if (count > maxcount) begin > maxcount <= count; > end > if (pt_0 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_0; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_1 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_1; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_2 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_2; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_3 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_3; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > end > endmodule > -- Rick From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.43.56.134 with SMTP id wc6mr1147167icb.17.1401614608028; Sun, 01 Jun 2014 02:23:28 -0700 (PDT) X-Received: by 10.50.110.42 with SMTP id hx10mr190770igb.0.1401614607897; Sun, 01 Jun 2014 02:23:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!hl10no8390627igb.0!news-out.google.com!qf4ni17772igc.0!nntp.google.com!c1no21799673igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Jun 2014 02:23:27 -0700 (PDT) In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? From: Dio Gratia Injection-Date: Sun, 01 Jun 2014 09:23:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7570 Perhaps you could try in comp.lang.verilog. VHDL stands for VHSIC Hardware Design Language, not Verilog Hardware Design Language. The former is typically referred to as VHDL, while the latter is sometimes referred to as Verilog HDL, or just Verilog. From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Sun, 01 Jun 2014 21:49:51 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Multiplication VHDL References: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> In-Reply-To: <75f75a5e-92cb-4583-8f62-931d6af33f30@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 26 Message-ID: <538b83e0$0$2176$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 01 Jun 2014 21:49:52 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1401652192 news-2.free.fr 2176 88.185.146.198:1167 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7571 Le 29/05/2014 18:36, Ayoub a écrit : > Hi, > > I have problems with my vhdl code. Maybe if you described the problems you have we'd be able to help you. > code: in std_logic_vector(15 downto 0 ) ; ... > type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ; > signal CD : RAM; ... > CD(0)<=(code(15 downto 12)); > CD(1)<=(code(11 downto 8)) ; > CD(2)<=(code(7 downto 4 )); > CD(3)<=(code(3 downto 0)); Now here we have a problem. RAM is defined as an array of 4 16-bits std_logic_vector, and you try to assign 4 bits to each of these 16-bits element. I haven't looked any further but this must be fixed. Nicolas From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sun, 01 Jun 2014 21:12:42 -0400 Organization: A noiseless patient Spider Lines: 133 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 2 Jun 2014 01:12:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="42d31eb8e7ba6748611c57063fee3e99"; logging-data="19157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GA+CmKg7yhtGH6QNnPyaW" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Cancel-Lock: sha1:lYVpN+bv3tSIfXRfiVcC7ib4UXA= Xref: news.eternal-september.org comp.lang.vhdl:7572 comp.lang.verilog:3747 On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote: > Any Help Will Be Appreciated! > > I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value. > > The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count) > > Is there any logical error? Or is there any Verilog Error that I missed? > > Thank you very much! > > module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2); > input Clock, Reset; > input signed [3:0] pt_0, pt_1, pt_2, pt_3; > output [6:0] hex1, hex0, hex3, hex2; > > wire signed [6:0] count; > wire signed [6:0] maxcount; > score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > > display(count, maxcount, hex1, hex0, hex3, hex2); > > endmodule > > module display (count, maxcount, hex1, hex0, hex3, hex2); > input [6:0] count, maxcount; > output [6:0] hex1, hex0, hex3, hex2; > > wire [4:0] unit, unit_m; > wire [4:0] tens, tens_m; > > assign unit = count % 10; > assign tens = count / 10; > > assign unit_m = count % 10; > assign tens_m = count / 10; > > seg7 ud (unit, hex0); > seg7 td (tens, hex1); > seg7 umd (unit_m, hex2); > seg7 tmd (tens_m, hex3); > > > endmodule > > module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount); > input Clock, Reset; > //input signed [3:0] sum; > input [3:0] pt_0, pt_1, pt_2, pt_3; > parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110; > //input zero, negative, carry, overflow; > > output signed [6:0] count, maxcount; > reg signed [6:0] count, maxcount; > > ////wire PS; > //reg NS; > > always @(posedge Clock) > if (Reset) begin > count <= 7'b0; > maxcount <= 7'b0; > end else begin > if (count > maxcount) begin > maxcount <= count; > end > if (pt_0 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_0; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_1 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_1; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_2 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_2; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > > if (pt_3 == neg_two) begin > if (count < 2) begin > count <= 7'b0; > end else begin > count <= count - 2; > end > end else begin > count <= count + pt_3; > if (count > 7'b100010) begin > count <= 7'b0; > end > end > end > endmodule > There's nothing obvious to me. Is it failing in behavioral simulation or only in hardware (you did simulate, right)? I've had issues with signed arithmetic in Verilog, but in this case count and maxcount have the same type, so I don't see an issue with the logic. Could there be a problem with synchronization to the clock? All inputs need to be synchronous to the clock, especially Reset. Obviously a Reset pulse could cause maxcount to go down. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Verilog: Why the "maxcount" cannot keep its max value but changes with the "count"? Date: Sun, 01 Jun 2014 21:31:44 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <0e1d220f-503e-4cd5-ac18-79c5a085b91d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 2 Jun 2014 01:31:45 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="24127"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IT2Adf85hKw2Y3DTLj7cn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: Cancel-Lock: sha1:g2yB77jqp6UXERDgu+rT525b9ng= Xref: news.eternal-september.org comp.lang.vhdl:7573 comp.lang.verilog:3748 On 6/1/2014 9:12 PM, Gabor wrote: > assign unit_m = count % 10; > assign tens_m = count / 10; I think the problem are these lines. He didn't say how he was checking the result, but I bet it was by looking at the display of unit_m and tens_m. I bet we never hear back from him... -- Rick From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Verilog or VLDL? Date: Wed, 04 Jun 2014 20:58:26 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 5 Jun 2014 00:58:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="3081"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+gwkfWlvaBePvZ+uBWyq2Y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 In-Reply-To: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> Cancel-Lock: sha1:5pgByiPdrKjMFlcHEjBNhhB518c= Xref: news.eternal-september.org comp.lang.verilog:3750 comp.lang.vhdl:7574 On 6/4/2014 5:06 PM, dhruvin bhadani wrote: > helooo sir, > > i am intrested in VLSI as a carrer, and i dont know with what should i start, with verilog? or VLHD? and i also dont knw any computer language much , i know basic C and little bit of core JAVA, hoping for your positive response I would recommend that you be fluent in both HDLs. In particular know how the problems and shortcomings of each language. Neither is hard to learn, but finding the problems each one creates is not so easy. VHDL has a steeper learning curve, but I think Verilog is harder to learn it's issues. I'm cross posting so you can get feedback from both groups. I hope all replies are to this branch of the thread. -- Rick From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.news.elisa.fi!uutiset.elisa.fi!7564ea0f!not-for-mail From: Kim Enkovaara User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Verilog or VLDL? References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 30 Message-ID: <4FTjv.43606$SH2.32503@uutiset.elisa.fi> Date: Thu, 05 Jun 2014 08:57:21 +0300 NNTP-Posting-Host: 138.111.130.175 X-Complaints-To: newsmaster@saunalahti.com X-Trace: uutiset.elisa.fi 1401947840 138.111.130.175 (Thu, 05 Jun 2014 08:57:20 EEST) NNTP-Posting-Date: Thu, 05 Jun 2014 08:57:20 EEST Organization: Elisa Customer Xref: news.eternal-september.org comp.lang.verilog:3751 comp.lang.vhdl:7575 On 5.6.2014 3:58, rickman wrote: > On 6/4/2014 5:06 PM, dhruvin bhadani wrote: >> helooo sir, >> >> i am intrested in VLSI as a carrer, and i dont know with what should i >> start, with verilog? or VLHD? and i also dont knw any computer >> language much , i know basic C and little bit of core JAVA, hoping for >> your positive response > > I would recommend that you be fluent in both HDLs. In particular know > how the problems and shortcomings of each language. Neither is hard to > learn, but finding the problems each one creates is not so easy. VHDL > has a steeper learning curve, but I think Verilog is harder to learn > it's issues. > > I'm cross posting so you can get feedback from both groups. I hope all > replies are to this branch of the thread. I agree that both languages are important. I have not seen for a long time design that would not have both languages (verilog/sv + vhdl) but I'm on the Europe side of the pond ;) The language is quite minor part of the design, more important is to understand what logic the RTL generates. For real ASIC stuff etc. schematic level understanding is also quite important (getting netlist simulations to work, metal fixes, tinkering at gate level for last timings etc.). If you understand digital design and its principles the language is just a way to express those ideas. --Kim From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.224.12.14 with SMTP id v14mr23485177qav.8.1401980492871; Thu, 05 Jun 2014 08:01:32 -0700 (PDT) X-Received: by 10.182.153.200 with SMTP id vi8mr198824obb.23.1401980492719; Thu, 05 Jun 2014 08:01:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no1716372qaq.1!news-out.google.com!gi6ni19621igc.0!nntp.google.com!h18no751659igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Jun 2014 08:01:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=209.118.190.4; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 209.118.190.4 References: <02bb614c-9866-4fea-a4fa-d321bbdd5605@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0dfe98b8-291f-4aa7-8499-7bc1e2949add@googlegroups.com> Subject: Re: Verilog or VLDL? From: Jim Lewis Injection-Date: Thu, 05 Jun 2014 15:01:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1370 X-Received-Body-CRC: 310395520 Xref: news.eternal-september.org comp.lang.vhdl:7576 Hi, If you know where you want to work and who you are interested in working for, look at what they currently use, if you can ask them if they plan on changing. Then learn that. While it is nice to be general, I would put my first focus on a job you want. Jim From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.50.18.20 with SMTP id s20mr4206178igd.3.1402096351165; Fri, 06 Jun 2014 16:12:31 -0700 (PDT) X-Received: by 10.140.38.199 with SMTP id t65mr61401qgt.17.1402096351122; Fri, 06 Jun 2014 16:12:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!h18no1011744igc.0!news-out.google.com!k18ni6553qav.1!nntp.google.com!hw13no5064918qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Jun 2014 16:12:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.99.164.46; posting-account=sAdkPAoAAACGN9LhffdAv3Mpxzde2fYO NNTP-Posting-Host: 188.99.164.46 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Job - Promotion - 2D/3D Bildverarbeitug - FPGA From: sim2a2z@googlemail.com Injection-Date: Fri, 06 Jun 2014 23:12:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7577 Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Am Institut f=FCr Parallele und Verteilte Systeme der Universit=E4t Stuttga= rt ist ab sofort eine Stelle f=FCr wiss. Mitarbeiter / wiss. Mitarbeiterin = Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf= dem folgenden Gebiet: Echtzeit-Bildverarbeitung zur schnellen messtechnischen=20 2D/3D Erfassung aufsteigender Blasen Voraussetzung ist ein =FCberdurchschnittlicher Abschluss in einem Studium d= er Informatik, Elektrotechnik, Physik oder einem verwandten Gebiet. Vertief= te Kenntnisse im Bereich FPGA-Entwurf oder der Technischen Informatik sind = von Vorteil. Wir bieten eine attraktive Arbeitsumgebung im internationalen = Umfeld mit einem hervorragend ausgestatteten Arbeitsplatz.=20 Anstellung und Verg=FCtung erfolgen nach TV-L, Verg. Gr. 13. Die Forschungs= t=E4tigkeit bietet die M=F6glichkeit zur Promotion. Die Universit=E4t Stuttgart m=F6chte den Anteil der Frauen im wissenschaftl= ichen Bereich erh=F6hen und ist deshalb an Bewerbungen von Frauen besonders= interessiert. Schwerbehinderte werden bei gleicher Eignung vorrangig einge= stellt. Bitte schicken Sie Ihre Bewerbung in elektronischer Form an: applic= ation-pas@ipvs.uni-stuttgart.de Professor Dr.-Ing. Sven Simon Universit=E4t Stuttgart Institut f=FCr Parallele und Verteilte Systeme Abteilung Parallele Systeme Universit=E4tsstr. 38 70569 Stuttgart Tel.: +49-711-685-88450 Email: application-pas@ipvs.uni-stuttgart.de From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.202.143 with SMTP id d15mr74753yho.18.1402133987396; Sat, 07 Jun 2014 02:39:47 -0700 (PDT) X-Received: by 10.140.91.245 with SMTP id z108mr356qgd.16.1402133987328; Sat, 07 Jun 2014 02:39:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.albasani.net!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!j5no2068238qaq.1!news-out.google.com!k18ni6554qav.1!nntp.google.com!j5no2068237qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Jun 2014 02:39:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.112.194.42; posting-account=-bKUXwoAAABskFGI8l3tcZRKpFmG6DfT NNTP-Posting-Host: 80.112.194.42 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Ethernet Switch on Configurable Logic now available From: Logixa Injection-Date: Sat, 07 Jun 2014 09:39:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7578 Now available from our Opencores.org repository a highly configurable Ethernet Switch for FPGA implementations. Check http://opencores.org/project,esoc for more details. From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.24.196 with SMTP id x44mr191201yhx.15.1402734899497; Sat, 14 Jun 2014 01:34:59 -0700 (PDT) X-Received: by 10.140.48.101 with SMTP id n92mr3935qga.15.1402734899409; Sat, 14 Jun 2014 01:34:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no1162980qae.1!news-out.google.com!q9ni6501qaj.0!nntp.google.com!w8no1418054qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Jun 2014 01:34:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cd2212d-9782-46a2-aba2-92ce84be32a5@googlegroups.com> Subject: Hash 256 function From: niv Injection-Date: Sat, 14 Jun 2014 08:34:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1660 X-Received-Body-CRC: 522616185 Xref: news.eternal-september.org comp.lang.vhdl:7579 Trying to build a standard HASh256 function based on some web articles I've read. Generally it takes 64 steps per message slice, & I have a sample printout-out of the 8 intermediate register (a to h) values for the 64 steps for the simple (hex) message X"61626380" I don't get the expected intermediate value(s). I thought the8 regs were initialised to '0's, then apply the first 16 words with the K(i) constant, then the remaining 48 words from the message expander. Finally, the 8 regs are then added to the 8 pre-initialised Hash regs (H0 to H7) I thought the first a reg value would just be thesum of K(0) & the first message word, but it isn't. Anyone tell me where I'm going wrong please? From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.43.92.195 with SMTP id br3mr245641icc.1.1402827042502; Sun, 15 Jun 2014 03:10:42 -0700 (PDT) X-Received: by 10.140.101.51 with SMTP id t48mr208382qge.4.1402827042474; Sun, 15 Jun 2014 03:10:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h3no3060136igd.0!news-out.google.com!q9ni6501qaj.0!nntp.google.com!w8no2276960qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Jun 2014 03:10:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.119.230; posting-account=5nUoRQoAAADYeHmRcKPapDdzL7RxIl26 NNTP-Posting-Host: 197.32.119.230 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <289d1575-97f6-4bc7-bcae-80076a7d70f6@googlegroups.com> Subject: Al madinah international university opening apply for university colleges (September season) From: marwa kotb Injection-Date: Sun, 15 Jun 2014 10:10:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7580 MR/ MiSS * al madinah international university which win dependence Malaysian Minist= ry of Higher Education Malaysia (MOHE) and also winning the adoption of all= academic programs and courses, the university that are approved by the Mal= aysian funds and private academy, which deals with quality control and effi= ciency Academy, known for short as [MQA ] to congratulate you on the occasi= on of the new academic September year - 2014 . Its pleasure to tell you th= at the university opening apply for university colleges. The flowing colleges : * faculty of Islamic Sciences * faculty of languages *faculty of computer Science . *faculty of education . * Faculty of Science, Finance and Administration . *Language center=20 *.faculty of engineering ( soon) The university offer : * Bachelor degree * Master degree * PH degree Both online and on campus learning for more information you can visit=20 http://www.mediu.edu.my/ar/admissions/requirments for more information about Bachelor degree=20 http://www.mediu.edu.my/ar/admissions/undergraduateprograms for more information about master degree=20 http://www.mediu.edu.my/ar/admissions/postgraduateprograms Best Regard international city university=20 //www.mediu.edu.my/ar/ From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: VHDL 2008/ PSL Verification: Book Recommendation Date: Tue, 17 Jun 2014 15:56:29 +0200 Organization: A noiseless patient Spider Lines: 20 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 17 Jun 2014 13:55:11 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="12312"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tHFopkWocnbYyMLbGSeOB" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:SHiFRFoh+rVG8qhjR1xXgq9zPK0= Xref: news.eternal-september.org comp.lang.vhdl:7581 Hi, I'm trying to improve my verification processes for VHDL designs and IP cores with VHDL 2008 and PSL. Therefore I used "The designers guide to VHDL - Third Edition" (Peter J. Ashenden). Now I want to go further and need some more specific literature. Maybe someone has a hint which book is recommendable to buy? There are two references in the Ashenden book: [1] A Practical Introduction to PSL, C. Eisner and D. Fisman, 2006 [2] Assertion-Based Design, H. D. Foster et al, 2003 Are there any other good books on the market you can suggest? Thanks a lot! Best regards Tobias From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.43.65.4 with SMTP id xk4mr7605435icb.12.1403029515631; Tue, 17 Jun 2014 11:25:15 -0700 (PDT) X-Received: by 10.140.47.15 with SMTP id l15mr489096qga.5.1403029515594; Tue, 17 Jun 2014 11:25:15 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!a13no6735706igq.0!news-out.google.com!q9ni6501qaj.0!nntp.google.com!w8no4853742qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Jun 2014 11:25:15 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.32.177.252; posting-account=zwwrhQoAAABkSgLoXR0QdgJVC-UJXTHy NNTP-Posting-Host: 185.32.177.252 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Subject: Help needed debugging high impedance on RAM read From: David Kaplan Injection-Date: Tue, 17 Jun 2014 18:25:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7582 Hi I'm having an issue with a cpu that I'm building and no matter what I try, I can't seem to resolve it (so any help would greatly be appreciated): Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. You can see the issue in the simulation screenie: https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). The code is at: https://github.com/DepletionMode/cupcake/blob/master/cpu/cpu.vhd https://github.com/DepletionMode/cupcake/blob/master/cpu/mmu.vhd https://github.com/DepletionMode/cupcake/blob/master/cpu/simpleram.vhd Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) Thanks in advance! :) From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed!lightspeed.eweka.nl!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx30.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008/ PSL Verification: Book Recommendation References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140617-1, 17/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 39 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403086029 86.29.12.221 (Wed, 18 Jun 2014 10:07:09 UTC) NNTP-Posting-Date: Wed, 18 Jun 2014 10:07:09 UTC Organization: virginmedia.com Date: Wed, 18 Jun 2014 11:07:06 +0100 X-Received-Body-CRC: 2580723100 X-Received-Bytes: 2429 Xref: news.eternal-september.org comp.lang.vhdl:7583 On 17/06/2014 14:56, Tobias Baumann wrote: > Hi, > > I'm trying to improve my verification processes for VHDL designs and IP > cores with VHDL 2008 and PSL. Therefore I used "The designers guide to > VHDL - Third Edition" (Peter J. Ashenden). Now I want to go further and > need some more specific literature. > > Maybe someone has a hint which book is recommendable to buy? There are > two references in the Ashenden book: > > [1] A Practical Introduction to PSL, C. Eisner and D. Fisman, 2006 > [2] Assertion-Based Design, H. D. Foster et al, 2003 > > Are there any other good books on the market you can suggest? > > Thanks a lot! > > Best regards > Tobias > Hi Tobias, I have Ben Cohen's book which is OKish but I only started to appreciate PSL (or I hope I do) after going onto a PSL course. I know they are not particular cheap but it will get you up to speed in just a few days. There is no problem learning PSL (or SVA) from a book but there are certain constructs like multiple clocks which you really need to have explained (multiple times in my case) by an expert. I would suggest you look into sequences and the cover directive first so that you can impress your boss with some quick functional coverage, then ask for about a training budget.....;-) Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008/ PSL Verification: Book Recommendation Date: Wed, 18 Jun 2014 16:09:42 +0200 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Jun 2014 14:08:25 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="6294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GTuDwAXK9q3J0OKSs92LL" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:08VaXDCOXK8oJyqMrOTn/mfaC/s= Xref: news.eternal-september.org comp.lang.vhdl:7584 Am 18.06.2014 12:07, schrieb HT-Lab: > I have Ben Cohen's book which is OKish but I only started to appreciate > PSL (or I hope I do) after going onto a PSL course. I know they are not > particular cheap but it will get you up to speed in just a few days. > There is no problem learning PSL (or SVA) from a book but there are > certain constructs like multiple clocks which you really need to have > explained (multiple times in my case) by an expert. > > I would suggest you look into sequences and the cover directive first so > that you can impress your boss with some quick functional coverage, then > ask for about a training budget.....;-) > Hello Hans, thank you for sharing your experiences. I think if I want to visit a PSL course, my boss would let me go. But honestly, I'm a person who needs to learn autodidactically, at least the basics. If I have a good basic knowledge, then it makes sense to go deeper with courses. So maybe the Ben Cohen book is a good start. If not - 60$ is not the world :) Thanks a lot, Tobias From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed2.funet.fi!newsfeeds.funet.fi!news.utu.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Help needed debugging high impedance on RAM read Date: Wed, 18 Jun 2014 17:23:23 +0300 Lines: 20 Message-ID: References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1403101409 16272 2001:708:310:3430:213:21ff:fe1b:b396 (18 Jun 2014 14:23:29 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Wed, 18 Jun 2014 14:23:29 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:WjZmg2q8TFv1At+lxt0ohLmAbA0= Xref: news.eternal-september.org comp.lang.vhdl:7585 David Kaplan writes: > Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. > > You can see the issue in the simulation screenie: > > https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp > > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). Well, with a (very) quick look, your mem_data control requires zero in mem_wr and mem_en but you have zero only in mem_en so mem_data remains Z. So I guess your tristating isn't really correct then? Do you really need this and do you really need both enable and write enable for RAM? > Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) It seems a little odd with the white space and I hate it when people wrap their if conditions in useless brackets. Oh, I also like active low signals to end in _n but maybe that's just my preference. From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Help needed debugging high impedance on RAM read Date: Wed, 18 Jun 2014 18:16:00 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 18 Jun 2014 22:16:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="612ea0f75d5623a06f5f0026beed276a"; logging-data="17210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199MkvuYDhTPJREdWGDiEvs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Cancel-Lock: sha1:YKmiMMpZucH/PExhuXFTg+gS2Fg= Xref: news.eternal-september.org comp.lang.vhdl:7586 On 6/17/2014 2:25 PM, David Kaplan wrote: > Hi > > I'm having an issue with a cpu that I'm building and no matter what I try, I can't seem to resolve it (so any help would greatly be appreciated): > > Basically, when I issue a POP instruction, my processor will read from RAM at the stack pointer address (minus 1). However, the value does not appear on the tristate data bus (it remains in hi-Z); even though it seems to be successfully read from RAM. > > You can see the issue in the simulation screenie: > > https://www.dropbox.com/s/s9ctbcpqilzzqmc/pop1.bmp > > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and therefore r0 is hi-Z). > > The code is at: > > https://github.com/DepletionMode/cupcake/blob/master/cpu/cpu.vhd > https://github.com/DepletionMode/cupcake/blob/master/cpu/mmu.vhd > https://github.com/DepletionMode/cupcake/blob/master/cpu/simpleram.vhd > > Apologies for the quality of the code; VHDL isn't my thing (I'm learning I guess.. :)) > > Thanks in advance! :) Try looking at your write enable inside the ram module. I think the sense is reversed somewhere. Also, in the read process of the MMU is purely combinatorial, but you have not completely specified all the cases in the IFs and CASE statements. That generate latches where they are not intended. An easy way to fix this is to include a single assignment outside of all the conditional code that sets a default. data_out <= 0x"ff"; -- Rick From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.19.7 with SMTP id m7mr688662yhm.35.1403137261874; Wed, 18 Jun 2014 17:21:01 -0700 (PDT) X-Received: by 10.50.17.100 with SMTP id n4mr33908igd.3.1403137261678; Wed, 18 Jun 2014 17:21:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no6156371qac.0!news-out.google.com!qf4ni6igc.0!nntp.google.com!hn18no309285igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Jun 2014 17:21:01 -0700 (PDT) In-Reply-To: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> Subject: Re: Help needed debugging high impedance on RAM read From: Dio Gratia Injection-Date: Thu, 19 Jun 2014 00:21:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3238 X-Received-Body-CRC: 3968116736 Xref: news.eternal-september.org comp.lang.vhdl:7587 On Wednesday, June 18, 2014 6:25:15 AM UTC+12, David Kaplan wrote: > At 110ns mmu1/ram_data is '11111111', however mem_data remains hi-Z (and = therefore r0 is hi-Z). >=20 The read process in mmu has ram_data on the right hand side of a conditiona= l signal assignment statement but ram_data isn't in the sensitivity list. What happens if the ram_data goes valid (non-'Z') in the next delta cycle f= ollowing some combination of events on n_wr, n_en and addr? You'll have as= signed data_out to the ram_data (others =3D> 'Z'). Until another transacti= on on n_wr, n_en or addr data_out will remain all 'Z's. Try putting ram_data in the sensitivity list. (This is speculation. It's t= oo much work to write an mmu test bench to test the hypothesis. The operat= ive delay would be the delta delay assigning ram_we - else '0'.) I also notice that simple_ram_tb_1 transitions the address while the ram en= able and write are both true, in general a no-no in an asynchronous RAM (de= spite the presence of a clock in the test bench). The reason for this is b= ecause you can have different propagation times for address signals and cou= ld corrupt RAM contents. The issue wouldn't show up in a zero time single = dimension array type representation simulation. It also says at some point you should be concerned with ram_we to ram_addr = delay as well as ram_addr to ram_we delay (t=3D85ns to t=3D90ns in your BMP= ). Perhaps you could 'form' the write enable? Also because the write occurs in 5 ns, you might consider using a synchrono= us RAM which would cure any potential issues anyway. Trying to find or crea= te two other clock phases to form both edges of ram_we could be tough in an= FPGA at that speed and I'd suspect an FPGA vendor would point you at a syn= chronous RAM. You'd be highly dependent on routing to get the holdovers wo= rking. (In other words a 200 MHz internal RAM may not be a simple RAM). Or is the clock rate a polite fiction at this point? I didn't see any actu= al specs on your web site. From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.182.226.166 with SMTP id rt6mr817814obc.47.1403137579503; Wed, 18 Jun 2014 17:26:19 -0700 (PDT) X-Received: by 10.50.60.7 with SMTP id d7mr44683igr.10.1403137579316; Wed, 18 Jun 2014 17:26:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no4384454igi.0!news-out.google.com!gf2ni1igb.0!nntp.google.com!r2no4384440igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Jun 2014 17:26:18 -0700 (PDT) In-Reply-To: <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <39a1d363-4685-4cd6-9cea-62e3d098fa70@googlegroups.com> <4bd8deff-9b7b-4964-ad42-e8951b8b8b32@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54569bd1-9e32-4fac-b00f-53e2d7729491@googlegroups.com> Subject: Re: Help needed debugging high impedance on RAM read From: Dio Gratia Injection-Date: Thu, 19 Jun 2014 00:26:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7588 On Thursday, June 19, 2014 12:21:01 PM UTC+12, Dio Gratia wrote: > Try putting ram_data in the sensitivity list. (This is speculation. It's too much work to write an mmu test bench to test the hypothesis. The operative delay would be the delta delay assigning ram_we - else '0'.) And I see you already implemented the sensitivity list change: https://github.com/DepletionMode/cupcake/commit/e836c96016e253fd6d44d73d629fdf46ab794405 From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.236.35.5 with SMTP id t5mr2684149yha.9.1403196872376; Thu, 19 Jun 2014 09:54:32 -0700 (PDT) X-Received: by 10.50.103.104 with SMTP id fv8mr151630igb.2.1403196872192; Thu, 19 Jun 2014 09:54:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!xlned.com!feeder1.xlned.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.85.216.88.MISMATCH!i13no6469754qae.1!news-out.google.com!gf2ni6igb.0!nntp.google.com!hn18no1198530igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Jun 2014 09:54:31 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.195; posting-account=8_pC6AoAAACWbtLE3A_sMKwe3ztVOfyh NNTP-Posting-Host: 119.235.52.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d89d4a0-97fa-4aca-be09-bab6300c7b60@googlegroups.com> Subject: Graphic Design Company in Chennai From: pmptraining66@gmail.com Injection-Date: Thu, 19 Jun 2014 16:54:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7589 Postlor Interactive is the best Graphic Design Company in Chennai, India specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com/ From newsfish@newsfish Tue Dec 29 16:43:27 2015 X-Received: by 10.58.67.129 with SMTP id n1mr1712656vet.35.1403280788819; Fri, 20 Jun 2014 09:13:08 -0700 (PDT) X-Received: by 10.140.95.176 with SMTP id i45mr79539qge.10.1403280788800; Fri, 20 Jun 2014 09:13:08 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no7287602qae.1!news-out.google.com!a8ni10892qaq.1!nntp.google.com!w8no7541345qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Jun 2014 09:13:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=149.156.64.122; posting-account=tsG57AoAAAD-1jped8Dtw3E8dJDyinwH NNTP-Posting-Host: 149.156.64.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Subject: Simple counter in verilog (Lattice MachXO2 7000H) From: krzysztof.pelczar@gmail.com Injection-Date: Fri, 20 Jun 2014 16:13:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2122 X-Received-Body-CRC: 3310269923 Xref: news.eternal-september.org comp.lang.vhdl:7590 Hi, I am working on a simple multi-channel pulse counter. The pulses counted ar= e infrequent (up to 100 kHz), and slow (at least 1 us), coming form a compa= rator. In total I have 20 parallel channels (identical). Every 0.5 s I read= out the counters and reset them to 0 using SPI. The counter code is simple, contained in a module: ... reg [17:0] counter_ripple_high; always @(posedge slow_gate, posedge reset) begin : b1 /*synopsys resource r0: map_to_module =3D "DW01_inc", implementation =3D "csa", ops =3D "inc1";*/ if (reset) counter_ripple_high <=3D 18'b0; else counter_ripple_high <=3D counter_ripple_high + 1'b1; // synopsys label in= c1 end assign counter =3D counter_ripple_high; ... Some channels (not more than 3 out of 20) count two times the input frequen= cy. How is it possible? One channel is not counting properly at all. I woul= d expect the latter to be obviously caused by the speed of arithmetic logic= , but the former..? I am looking forward for your opinions. Regards, Krzysztof From newsfish@newsfish Tue Dec 29 16:43:27 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simple counter in verilog (Lattice MachXO2 7000H) Date: Fri, 20 Jun 2014 13:13:41 -0400 Organization: Alacron, Inc. Lines: 3 Message-ID: References: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 20 Jun 2014 17:15:52 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="30419"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/H7JYMQfavQxQVbcOSgNSAfMFOWKNXctE=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <0788f3e7-44bb-483c-aafe-4bc8f29a7864@googlegroups.com> Cancel-Lock: sha1:mdl7orSZKPvZzaTmLSiQPTEC6TE= Xref: news.eternal-september.org comp.lang.vhdl:7591 Cross-posted. See thread in comp.lang.verilog From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.42.229.194 with SMTP id jj2mr3777660icb.18.1403699143249; Wed, 25 Jun 2014 05:25:43 -0700 (PDT) X-Received: by 10.50.112.36 with SMTP id in4mr207525igb.7.1403699143128; Wed, 25 Jun 2014 05:25:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no9372447igb.0!news-out.google.com!gf2ni11igb.0!nntp.google.com!hn18no10704372igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jun 2014 05:25:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=198.182.52.26; posting-account=DmMQNwoAAAAW6z46wNj7BIBvw750QZWq NNTP-Posting-Host: 198.182.52.26 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> Subject: Predefined Attributes From: NK Injection-Date: Wed, 25 Jun 2014 12:25:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7592 IS 'element a Predefined Attributes similar to 'Range ? From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.66.144.228 with SMTP id sp4mr6760737pab.5.1403750836918; Wed, 25 Jun 2014 19:47:16 -0700 (PDT) X-Received: by 10.140.50.131 with SMTP id s3mr73547qga.7.1403750836867; Wed, 25 Jun 2014 19:47:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!hn18no12114173igb.0!news-out.google.com!q9ni968qaj.0!nntp.google.com!i13no754758qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Jun 2014 19:47:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Why does it use shared variable? From: fl Injection-Date: Thu, 26 Jun 2014 02:47:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7593 Hi, When I learn Modelsim, I find that there is shared variable in its single port memory example. Every architecture of sp_syn_ram has its SHARED VARIABLE mem : mem_type; I do not see one mem variable accessed by other process signals. I only copy two architectures below of the four similar structures. Do you think what purpose it uses shared variable here? Thanks, ......................... ARCHITECTURE constrainedintarch OF sp_syn_ram IS SUBTYPE constrained_int is integer range 0 to 2**data_width-1; TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; SHARED VARIABLE mem : mem_type; BEGIN ASSERT data_width <= 32 REPORT "### Illegal data width detected" SEVERITY failure; control_proc : PROCESS (inclk, outclk) VARIABLE inner_addr : integer; VARIABLE outer_addr : integer; BEGIN IF (inclk'event AND inclk = '1') THEN IF (we = '1') THEN mem(to_integer(addr)) := to_integer(unsigned(data_in)); END IF; END IF; IF (outclk'event AND outclk = '1') THEN data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); END IF; END PROCESS; END constrainedintarch; ARCHITECTURE \3D\ OF sp_syn_ram IS TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; SHARED VARIABLE mem : mem_type; BEGIN control_proc : PROCESS (inclk, outclk) VARIABLE inner_addr : integer; VARIABLE outer_addr : integer; BEGIN IF (inclk'event AND inclk = '1') THEN inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); IF (we = '1') THEN mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); END IF; END IF; IF (outclk'event AND outclk = '1') THEN inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); END IF; END PROCESS; END \3D\; From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Thu, 26 Jun 2014 09:59:09 -0400 Organization: Alacron, Inc. Lines: 80 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 Jun 2014 14:02:56 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="5925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Ic5C+o0JBXQFDObr+oj/Mo1cv3hD0fQQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:hmSgi4DCvRAtV3Rn44Lt8oQocFQ= Xref: news.eternal-september.org comp.lang.vhdl:7594 fl wrote: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; Just a guess, perhaps the one-port memory example was chopped down from a two-port memory example? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx02.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-1, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 85 Message-ID: <54Xqv.464124$Mx1.439821@fx02.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403796865 86.29.12.221 (Thu, 26 Jun 2014 15:34:25 UTC) NNTP-Posting-Date: Thu, 26 Jun 2014 15:34:25 UTC Organization: virginmedia.com Date: Thu, 26 Jun 2014 16:34:24 +0100 X-Received-Body-CRC: 4133677316 X-Received-Bytes: 3746 Xref: news.eternal-september.org comp.lang.vhdl:7595 On 26/06/2014 03:47, fl wrote: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. There are 2 different clocks, one for reading and one for writing used in the same process. Run the simulation and check the result, next change the shared variable to a signal and see what happens, Good luck, Hans. www.ht-lab.com > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; > From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx07.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Predefined Attributes References: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> In-Reply-To: <5cfdcb37-07e0-4960-aeb7-1dce7e9ace7d@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-1, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 13 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403798119 86.29.12.221 (Thu, 26 Jun 2014 15:55:19 UTC) NNTP-Posting-Date: Thu, 26 Jun 2014 15:55:19 UTC Organization: virginmedia.com Date: Thu, 26 Jun 2014 16:55:18 +0100 X-Received-Body-CRC: 2350826076 X-Received-Bytes: 1228 Xref: news.eternal-september.org comp.lang.vhdl:7596 On 25/06/2014 13:25, NK wrote: > IS 'element a Predefined Attributes similar to 'Range ? > Yes, see: http://stackoverflow.com/questions/21907520/get-range-attribute-of-array-subtype-in-vhdl Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Thu, 26 Jun 2014 14:58:20 -0400 Organization: Alacron, Inc. Lines: 100 Message-ID: References: <54Xqv.464124$Mx1.439821@fx02.am4> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 26 Jun 2014 19:02:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="15643"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dT7cNEuRwHOEA2VR/OOnvcNinKdEJE8g=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Cancel-Lock: sha1:nF0a7WNEJitOCoL2SFlnC4A5kqs= Xref: news.eternal-september.org comp.lang.vhdl:7597 HT-Lab wrote: > On 26/06/2014 03:47, fl wrote: >> Hi, >> When I learn Modelsim, I find that there is shared variable in its >> single port >> memory example. Every architecture of sp_syn_ram has its >> SHARED VARIABLE mem : mem_type; >> >> I do not see one mem variable accessed by other process signals. > > There are 2 different clocks, one for reading and one for writing used > in the same process. Run the simulation and check the result, next > change the shared variable to a signal and see what happens, > > Good luck, > Hans. > www.ht-lab.com > >> >> I only copy two architectures below of the four similar structures. >> >> Do you think what purpose it uses shared variable here? >> >> Thanks, >> >> >> >> ......................... >> ARCHITECTURE constrainedintarch OF sp_syn_ram IS >> >> SUBTYPE constrained_int is integer range 0 to 2**data_width-1; >> TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; >> SHARED VARIABLE mem : mem_type; >> >> BEGIN >> >> ASSERT data_width <= 32 >> REPORT "### Illegal data width detected" >> SEVERITY failure; >> >> control_proc : PROCESS (inclk, outclk) >> VARIABLE inner_addr : integer; >> VARIABLE outer_addr : integer; >> BEGIN >> IF (inclk'event AND inclk = '1') THEN >> IF (we = '1') THEN >> mem(to_integer(addr)) := to_integer(unsigned(data_in)); >> END IF; >> END IF; >> >> IF (outclk'event AND outclk = '1') THEN >> data_out <= >> std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); >> END IF; >> END PROCESS; >> >> END constrainedintarch; >> >> >> ARCHITECTURE \3D\ OF sp_syn_ram IS >> >> TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF >> integer; >> SHARED VARIABLE mem : mem_type; >> >> BEGIN >> >> control_proc : PROCESS (inclk, outclk) >> VARIABLE inner_addr : integer; >> VARIABLE outer_addr : integer; >> BEGIN >> IF (inclk'event AND inclk = '1') THEN >> inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); >> outer_addr := to_integer(addr(addr_width-1 DOWNTO >> addr_width-2)); >> IF (we = '1') THEN >> mem(outer_addr, inner_addr) := >> to_integer(unsigned(data_in)); >> END IF; >> END IF; >> >> IF (outclk'event AND outclk = '1') THEN >> inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); >> outer_addr := to_integer(addr(addr_width-1 DOWNTO >> addr_width-2)); >> data_out <= std_logic_vector(to_unsigned(mem(outer_addr, >> inner_addr), data_out'length)); >> END IF; >> END PROCESS; >> >> END \3D\; >> > I think the question was about sharing, rather than whether this should be a signal. i.e. if it's only used in one process, why does the variable "mem" need to be shared? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.58.209.227 with SMTP id mp3mr8993642vec.29.1403809504269; Thu, 26 Jun 2014 12:05:04 -0700 (PDT) X-Received: by 10.182.143.4 with SMTP id sa4mr22075obb.38.1403809504003; Thu, 26 Jun 2014 12:05:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!i13no1255782qae.1!news-out.google.com!gf2ni200igb.0!nntp.google.com!hn18no13500196igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jun 2014 12:05:03 -0700 (PDT) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <54Xqv.464124$Mx1.439821@fx02.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why does it use shared variable? From: Andy Injection-Date: Thu, 26 Jun 2014 19:05:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7598 On Thursday, June 26, 2014 10:34:24 AM UTC-5, HT-Lab wrote: > There are 2 different clocks, one for reading and one for writing used in the same process. Run the simulation and check the result, next change the shared variable to a signal and see what happens, Good luck, Hans. I think the OP was referring to changing the shared variable to a local variable declared in the process, not to a signal. A local variable would behave exactly the same as the shared variable in this context. Using a shared variable, IINM, allows the memory content to be accessed with a hierarchical reference, say in a testbench, etc. Local variables do not allow that (yet). Andy From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.43.151.207 with SMTP id kt15mr9434746icc.15.1403831523616; Thu, 26 Jun 2014 18:12:03 -0700 (PDT) X-Received: by 10.182.220.133 with SMTP id pw5mr228obc.30.1403831523389; Thu, 26 Jun 2014 18:12:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!hn18no13954106igb.0!news-out.google.com!gf2ni202igb.0!nntp.google.com!uq10no12626108igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Jun 2014 18:12:02 -0700 (PDT) In-Reply-To: <54Xqv.464124$Mx1.439821@fx02.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.21.248.204; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 72.21.248.204 References: <54Xqv.464124$Mx1.439821@fx02.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> Subject: Re: Why does it use shared variable? From: KJ Injection-Date: Fri, 27 Jun 2014 01:12:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7599 Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!feeder.erje.net!eu.feeder.erje.net!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? References: <54Xqv.464124$Mx1.439821@fx02.am4> <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> In-Reply-To: <0ba338ef-d2ee-4b80-8e96-0710c9297590@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140626-2, 26/06/2014), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1403858680 86.29.12.221 (Fri, 27 Jun 2014 08:44:40 UTC) NNTP-Posting-Date: Fri, 27 Jun 2014 08:44:40 UTC Organization: virginmedia.com Date: Fri, 27 Jun 2014 09:44:36 +0100 X-Received-Body-CRC: 1217973053 X-Received-Bytes: 1573 Xref: news.eternal-september.org comp.lang.vhdl:7600 On 27/06/2014 02:12, KJ wrote: > Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP. > > Kevin Jennings > you are all correct, I misread the OP's question. A shared variable in this case is not required and a local process variable should behave the same. Regards, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Markus Michel Newsgroups: comp.lang.vhdl Subject: Re: Why does it use shared variable? Date: Sun, 29 Jun 2014 21:00:59 +0200 Organization: A noiseless patient Spider Lines: 82 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 29 Jun 2014 19:00:59 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="931432146a9ecb6d48ecc33a58ac477b"; logging-data="9274"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+GnViaUaXwp1BlgQw5E8hB" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:f9tADhSMfeBCAK7ti4tEB/ckStA= Xref: news.eternal-september.org comp.lang.vhdl:7601 Am 26.06.2014 04:47, schrieb fl: > Hi, > When I learn Modelsim, I find that there is shared variable in its single port > memory example. Every architecture of sp_syn_ram has its > SHARED VARIABLE mem : mem_type; > > I do not see one mem variable accessed by other process signals. > > I only copy two architectures below of the four similar structures. > > Do you think what purpose it uses shared variable here? > > Thanks, > > > > ......................... > ARCHITECTURE constrainedintarch OF sp_syn_ram IS > > SUBTYPE constrained_int is integer range 0 to 2**data_width-1; > TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int; > SHARED VARIABLE mem : mem_type; > > BEGIN > > ASSERT data_width <= 32 > REPORT "### Illegal data width detected" > SEVERITY failure; > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > IF (we = '1') THEN > mem(to_integer(addr)) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length)); > END IF; > END PROCESS; > > END constrainedintarch; > > > ARCHITECTURE \3D\ OF sp_syn_ram IS > > TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer; > SHARED VARIABLE mem : mem_type; > > BEGIN > > control_proc : PROCESS (inclk, outclk) > VARIABLE inner_addr : integer; > VARIABLE outer_addr : integer; > BEGIN > IF (inclk'event AND inclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > IF (we = '1') THEN > mem(outer_addr, inner_addr) := to_integer(unsigned(data_in)); > END IF; > END IF; > > IF (outclk'event AND outclk = '1') THEN > inner_addr := to_integer(addr(addr_width-3 DOWNTO 0)); > outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2)); > data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length)); > END IF; > END PROCESS; > > END \3D\; > signals have attributes which the simulator must maintain. (shared) variables do not. This makes simulation (much) faster. Like signals, shared variables can be used for communication between processes. Regards, Markus From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.236.92.69 with SMTP id i45mr6483448yhf.20.1404314238780; Wed, 02 Jul 2014 08:17:18 -0700 (PDT) X-Received: by 10.182.128.131 with SMTP id no3mr112276obb.9.1404314238667; Wed, 02 Jul 2014 08:17:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no5256365qac.0!news-out.google.com!gf2ni2855igb.0!nntp.google.com!uq10no863908igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 08:17:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=120.56.167.175; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 120.56.167.175 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> Subject: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Wed, 02 Jul 2014 15:17:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2316 X-Received-Body-CRC: 2245080976 Xref: news.eternal-september.org comp.lang.vhdl:7602 Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a r= andom number generator but I'm stuck on the Transmitter part. I've written = this code : entity Knapsack_Tx is port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); end Knapsack_Tx; =20 architecture Encipher of Knapsack_Tx is type rndnum is array(7 downto 0) of std_logic; type easy is array(7 downto 0) of std_logic; --type index is array (0 to 7) of integer; function elf(rnum:rndnum) return easy is=20 variable knap1:easy; variable i: integer :=3D 0; variable rnum1 : rndnum :=3Drnum; variable int1, int2 :integer :=3D0; begin =09 int1:=3D to_integer(rnum1(i-1)); int2:=3D to_integer(rnum1(i)); for i in 0 to 7 loop if int1 <=3D int2 then knap1(i) :=3D rnum1(i); end if; end loop; return knap1; end function elf; begin end architecture Encipher; The rnum1 variable is an array which is used to store the random values obt= ained from the RNG. The code is obviously incomplete but essentially it rev= olves around this. Check Syntax reveals that to_integer is not recognised. = If anyone can help it would be nice :) From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.182.125.4 with SMTP id mm4mr30678198obb.49.1404316766464; Wed, 02 Jul 2014 08:59:26 -0700 (PDT) X-Received: by 10.182.165.36 with SMTP id yv4mr111815obb.18.1404316766360; Wed, 02 Jul 2014 08:59:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no1961282igb.0!news-out.google.com!gf2ni2855igb.0!nntp.google.com!uq10no878470igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 08:59:26 -0700 (PDT) In-Reply-To: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=166.20.224.10; posting-account=Hhan4goAAAC6R91Dbv381087p9kjKRkY NNTP-Posting-Host: 166.20.224.10 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Russell Merrick Injection-Date: Wed, 02 Jul 2014 15:59:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7603 On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote: > Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained a= random number generator but I'm stuck on the Transmitter part. I've writte= n this code : >=20 > entity Knapsack_Tx is >=20 > port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; >=20 > data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); >=20 > end Knapsack_Tx; =20 >=20 >=20 >=20 >=20 >=20 > architecture Encipher of Knapsack_Tx is >=20 >=20 >=20 > type rndnum is array(7 downto 0) of std_logic; >=20 > type easy is array(7 downto 0) of std_logic; >=20 > --type index is array (0 to 7) of integer; >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 > function elf(rnum:rndnum) return easy is=20 >=20 >=20 >=20 > variable knap1:easy; >=20 > variable i: integer :=3D 0; >=20 > variable rnum1 : rndnum :=3Drnum; >=20 > variable int1, int2 :integer :=3D0; >=20 >=20 >=20 > begin >=20 > =09 >=20 > int1:=3D to_integer(rnum1(i-1)); >=20 > int2:=3D to_integer(rnum1(i)); >=20 >=20 >=20 > for i in 0 to 7 loop >=20 > if int1 <=3D int2 then >=20 > knap1(i) :=3D rnum1(i); >=20 > end if; >=20 > end loop; >=20 >=20 >=20 > return knap1; >=20 >=20 >=20 > end function elf; >=20 >=20 >=20 > begin >=20 >=20 >=20 >=20 >=20 > end architecture Encipher; >=20 >=20 >=20 > The rnum1 variable is an array which is used to store the random values o= btained from the RNG. The code is obviously incomplete but essentially it r= evolves around this. Check Syntax reveals that to_integer is not recognised= . If anyone can help it would be nice :) First of all, why are you creating an array of std_logic? Just use a std_l= ogic_vector. You should be including std_logic_1164 package file. =20 Once that's complete, use the numeric_std package file for your math. =20 Your conversion will be: output <=3D to_integer(unsigned(input_slv)); Read more about how to convert std_logic_vector to integer and why using st= d_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-convert= -numeric-std-logic-vector-to-integer.html From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.52.121.13 with SMTP id lg13mr1127570vdb.8.1404363591943; Wed, 02 Jul 2014 21:59:51 -0700 (PDT) X-Received: by 10.50.25.168 with SMTP id d8mr782569igg.1.1404363591691; Wed, 02 Jul 2014 21:59:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no5448372qae.1!news-out.google.com!bp9ni2742igb.0!nntp.google.com!uq10no1106094igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 21:59:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.1.60.114; posting-account=SpxwwwoAAAAuxDZPgTWiDB6veugmX1-d NNTP-Posting-Host: 121.1.60.114 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: MEGAWIZARD PLUG IN From: edgedetection fpga Injection-Date: Thu, 03 Jul 2014 04:59:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1112 X-Received-Body-CRC: 553425998 Xref: news.eternal-september.org comp.lang.vhdl:7604 what is the default adder of addition in megawizard plugin??? like ripple carry,. or can we modify it to assign what kind of adder will be used? From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.43.94.71 with SMTP id bx7mr4072974icc.2.1404365301082; Wed, 02 Jul 2014 22:28:21 -0700 (PDT) X-Received: by 10.50.45.67 with SMTP id k3mr412257igm.1.1404365300989; Wed, 02 Jul 2014 22:28:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no2331330igb.0!news-out.google.com!bp9ni2742igb.0!nntp.google.com!uq10no1111777igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Jul 2014 22:28:20 -0700 (PDT) In-Reply-To: <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.27.8.45; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 103.27.8.45 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Thu, 03 Jul 2014 05:28:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7605 On Wednesday, July 2, 2014 9:29:26 PM UTC+5:30, Russell wrote: > On Wednesday, July 2, 2014 11:17:18 AM UTC-4, Gandalf wrote: >=20 > > Hi all, I'm trying to develop the mentioned cryptosystem. I've obtained= a random number generator but I'm stuck on the Transmitter part. I've writ= ten this code : >=20 > >=20 >=20 > > entity Knapsack_Tx is >=20 > >=20 >=20 > > port(rnum:in std_logic_vector(7 downto 0);clk : in std_logic; >=20 > >=20 >=20 > > data:std_logic_vector;cip:out std_logic_vector(7 downto 0)); >=20 > >=20 >=20 > > end Knapsack_Tx; =20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > architecture Encipher of Knapsack_Tx is >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > type rndnum is array(7 downto 0) of std_logic; >=20 > >=20 >=20 > > type easy is array(7 downto 0) of std_logic; >=20 > >=20 >=20 > > --type index is array (0 to 7) of integer; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > function elf(rnum:rndnum) return easy is=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > variable knap1:easy; >=20 > >=20 >=20 > > variable i: integer :=3D 0; >=20 > >=20 >=20 > > variable rnum1 : rndnum :=3Drnum; >=20 > >=20 >=20 > > variable int1, int2 :integer :=3D0; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > begin >=20 > >=20 >=20 > > =09 >=20 > >=20 >=20 > > int1:=3D to_integer(rnum1(i-1)); >=20 > >=20 >=20 > > int2:=3D to_integer(rnum1(i)); >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > for i in 0 to 7 loop >=20 > >=20 >=20 > > if int1 <=3D int2 then >=20 > >=20 >=20 > > knap1(i) :=3D rnum1(i); >=20 > >=20 >=20 > > end if; >=20 > >=20 >=20 > > end loop; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > return knap1; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > end function elf; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > begin >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > end architecture Encipher; >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > The rnum1 variable is an array which is used to store the random values= obtained from the RNG. The code is obviously incomplete but essentially it= revolves around this. Check Syntax reveals that to_integer is not recognis= ed. If anyone can help it would be nice :) >=20 >=20 >=20 > First of all, why are you creating an array of std_logic? Just use a std= _logic_vector. You should be including std_logic_1164 package file. =20 >=20 >=20 >=20 > Once that's complete, use the numeric_std package file for your math. =20 >=20 > Your conversion will be: >=20 > output <=3D to_integer(unsigned(input_slv)); >=20 >=20 >=20 > Read more about how to convert std_logic_vector to integer and why using = std_logic_arith is a bad idea. http://www.nandland.com/vhdl/tips/tip-conve= rt-numeric-std-logic-vector-to-integer.html Hey Thanks, But I need several random numbers in my array so that a private= key may be derived. The module is connected to a random number generator w= hich generates a std_logic_vector of 8 bits. From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems Date: Thu, 03 Jul 2014 12:05:01 +0200 Lines: 34 Message-ID: References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net LxT2vKBrOIKGekwvAlSdpwJqXi+hxIGcZtlJLlkkcE9iL0AVba Cancel-Lock: sha1:01DcR94p/A5+AmGLPE36pq4XaGA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:7606 Gandalf wrote: > Hey Thanks, But I need several random numbers in my array so that a > private key may be derived. The module is connected to a random > number generator which generates a std_logic_vector of 8 bits. Then you need an array of std_logic_vectors, not an array of std_logic. Right now what you're doing here: int1:= to_integer(rnum1(i-1)); ... is accessing a single bit in a std_logic_vector. Not sure how useful it is to convert a single bit to an integer. I suppose you expect rnum1(i-1) to be a random number of 8 bits length instead? You probably want to declare "rndnum" and "easy" as arrays of std_logic_vectors(7 downto 0) to be able to store incoming rnum values or something. I have no idea about the algorithm, so I'm guessing here... Besides, a std_logic or a std_logic_vector is not a numerical value, it's a bit or a collection of bits. That's why you cannot convert it to integer. You either have to declare the elements of your rnum1 array as some sort of numerical value (for example unsigned(7 downto 0)) or you have to cast before trying to convert: int1:= to_integer(unsigned(rnum1(i-1))); (or maybe signed, depending on what values that random number generator delivers). The whole conversion doesn't make a whole lot of sense if what you're converting is a single it, though. HTH, Sean From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.66.185.9 with SMTP id ey9mr2717551pac.26.1404402594447; Thu, 03 Jul 2014 08:49:54 -0700 (PDT) X-Received: by 10.50.43.227 with SMTP id z3mr247600igl.11.1404402594161; Thu, 03 Jul 2014 08:49:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!news.glorb.com!hn18no2585868igb.0!news-out.google.com!bp9ni2743igb.0!nntp.google.com!hn18no2585865igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Jul 2014 08:49:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5f168893-4680-4ea8-a1b1-7aa7d0ddd5fb@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Thu, 03 Jul 2014 15:49:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7607 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.182.70.74 with SMTP id k10mr4879863obu.34.1404457783543; Fri, 04 Jul 2014 00:09:43 -0700 (PDT) X-Received: by 10.50.138.133 with SMTP id qq5mr1132605igb.4.1404457783393; Fri, 04 Jul 2014 00:09:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hn18no2819401igb.0!news-out.google.com!bp9ni2745igb.0!nntp.google.com!hn18no2819383igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Jul 2014 00:09:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.27.8.45; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 103.27.8.45 References: <29742763-d5c9-4616-b5e3-c90af3a3c1c1@googlegroups.com> <74401667-74bf-400d-aee9-951a3acabcbc@googlegroups.com> <04208bb3-7e0e-4a47-892d-b5aa4a5a63fe@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Synthesis issues in Merkle Hellman Knapsack Cryptosystems From: Gandalf Injection-Date: Fri, 04 Jul 2014 07:09:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7608 On Thursday, July 3, 2014 3:35:01 PM UTC+5:30, Sean Durkin wrote: > Gandalf wrote: > > > > > Hey Thanks, But I need several random numbers in my array so that a > > > private key may be derived. The module is connected to a random > > > number generator which generates a std_logic_vector of 8 bits. > > > > Then you need an array of std_logic_vectors, not an array of std_logic. > > > > Right now what you're doing here: > > > > int1:= to_integer(rnum1(i-1)); > > > > ... is accessing a single bit in a std_logic_vector. Not sure how useful > > it is to convert a single bit to an integer. I suppose you expect > > rnum1(i-1) to be a random number of 8 bits length instead? > > > > You probably want to declare "rndnum" and "easy" as arrays of > > std_logic_vectors(7 downto 0) to be able to store incoming rnum values > > or something. I have no idea about the algorithm, so I'm guessing here... > > > > Besides, a std_logic or a std_logic_vector is not a numerical value, > > it's a bit or a collection of bits. That's why you cannot convert it to > > integer. You either have to declare the elements of your rnum1 array as > > some sort of numerical value (for example unsigned(7 downto 0)) or you > > have to cast before trying to convert: > > > > int1:= to_integer(unsigned(rnum1(i-1))); > > > > (or maybe signed, depending on what values that random number generator > > delivers). The whole conversion doesn't make a whole lot of sense if > > what you're converting is a single it, though. > > > > HTH, > > Sean Hey Sean, that was pretty helpful! I'll try to do the things you mentioned. From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.236.136.231 with SMTP id w67mr6502481yhi.37.1404532881414; Fri, 04 Jul 2014 21:01:21 -0700 (PDT) X-Received: by 10.50.45.67 with SMTP id k3mr618641igm.1.1404532881180; Fri, 04 Jul 2014 21:01:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no6083670qae.1!news-out.google.com!bp9ni2744igb.0!nntp.google.com!uq10no1700170igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Jul 2014 21:01:20 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <076a62ef-f79a-453b-8982-68960e8b0e7a@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Sat, 05 Jul 2014 04:01:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:7609 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.43.58.137 with SMTP id wk9mr13345433icb.10.1404667173780; Sun, 06 Jul 2014 10:19:33 -0700 (PDT) X-Received: by 10.50.2.73 with SMTP id 9mr679962igs.13.1404667173652; Sun, 06 Jul 2014 10:19:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!hn18no4100713igb.0!news-out.google.com!bp9ni2747igb.0!nntp.google.com!hn18no4100709igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Jul 2014 10:19:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ce2d2ca-9f27-42d9-b68d-68e0c1418d51@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Sun, 06 Jul 2014 17:19:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7610 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.66.182.130 with SMTP id ee2mr9252737pac.37.1405007011167; Thu, 10 Jul 2014 08:43:31 -0700 (PDT) X-Received: by 10.182.28.71 with SMTP id z7mr154028obg.16.1405007010966; Thu, 10 Jul 2014 08:43:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!r10no645937igi.0!news-out.google.com!gf2ni5igb.0!nntp.google.com!hn18no249931igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 10 Jul 2014 08:43:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.235.52.206; posting-account=7MoFvwoAAABDSlSivIE9GEbIeBJFr7-i NNTP-Posting-Host: 119.235.52.206 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9cc79afa-c26e-44e7-aa13-384112177062@googlegroups.com> Subject: Graphic Design Company in Chennai From: chkumar357@gmail.com Injection-Date: Thu, 10 Jul 2014 15:43:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7611 Postlor Interactive is the best Graphic Design Company in ChennaiIndia specializing in Brochure design, Digital Photography, Flimmaking, 2d 3d animation. http://www.postlor.com From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: scoreboards, checkers and golden models Date: 11 Jul 2014 14:40:42 GMT Lines: 60 Message-ID: X-Trace: individual.net GwT11v8mP7510TZ86fIvXgwKeePl0/v1Z6+jVD9wZAHZnjnqtz X-Orig-Path: not-for-mail Cancel-Lock: sha1:oezWN/ttBBVUaE7FwPKd+J4sPMo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7612 Hi everyone, I'm designing a verification environment for our fpga designs which essentially allows to incrementally test the whole system without the need to break the verification effort in several block level testcases which are often not reusable and too often not sufficiently debugged either. In order to perform CI (continuous integration) it would be better to have in place selfchecking testbenches which run autonomously and regularly (each build or each nth build). When talking about a selfchecking testbench I've often heard about a 'golden model' against which we compare our results and here I'd like to explain why I do not clearly see the reason for it. In a 'verification plan' I have to match the 'requirements specification', therefore I need to check that a) I've covered all requirements and b) the criteria specified as a requirement is met. Taking one example I'm currently working with: /The time between the SYNC assertion and the REF assertion shall be less than 5 microseconds/ My selfchecking testbench needs to have a coverage model to verify that my transactions a) do generate a transaction of the SYNC signal and b) the corresponding REF signal has arrived withing the 5 microseconds. So in my mind I consider a scoreboard as a mechanism to 'store' transactions out of which I fill my coverage model, while a checker is a mechanism which goes through each transaction and verify that the requirement is met. In the above example I may imagine to have my bfm which generates the SYNC and samples the REF signal, storing the 'transaction' as a data structure, possibly containing the 'time interval' between the two events. The transaction is stored in the scoreboard which fills a sort of coverage db while in the meantime the checker may, asynchronously, examine the transaction and raise a flag pass/failed. If all what I said does make sense to, at least some of, you then could someone explain me where is the need for a 'golden model' in this context? Isn't the requirement specification sufficient to fill our needs? Remaining in the hypothesis that I did understand something of what I said, when it is time to do the 'verification report', how do we bind the pass/failed criteria to the coverage db? I hinted the possibility for the checker to be completely out of sync w.r.t. the coverage db. On a side note, if any has some source code for scoreboards and checkers, whose willing to share as a reference for this discussion I'd appreciate. Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.52.121.13 with SMTP id lg13mr22993419vdb.8.1405094940221; Fri, 11 Jul 2014 09:09:00 -0700 (PDT) X-Received: by 10.182.250.195 with SMTP id ze3mr20094obc.34.1405094939947; Fri, 11 Jul 2014 09:08:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no100526igc.0!news-out.google.com!gf2ni6igb.0!nntp.google.com!r10no1044532igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Jul 2014 09:08:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00510750-5d33-424d-bc8e-cbf51e284519@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: KJ Injection-Date: Fri, 11 Jul 2014 16:08:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2673 X-Received-Body-CRC: 1542455812 Xref: news.eternal-september.org comp.lang.vhdl:7613 On Friday, July 11, 2014 10:40:42 AM UTC-4, alb wrote: > If all what I said does make sense to, at least some of, you then could= =20 > someone explain me where is the need for a 'golden model' in this=20 > context? Isn't the requirement specification sufficient to fill our=20 > needs?=20 In your case, it appears that your 'golden model' implementation happens wi= th "I may imagine to have my bfm which generates the SYNC and samples the R= EF signal, storing the 'transaction' as a data structure, possibly containi= ng the 'time interval' between the two events". Since you do not appear to be performing any function on the data then simp= ly making sure that what goes in, comes out at the appropriate time is suff= icient, but that then is your golden model. Your design may be translating= between interfaces or other such useful things, but if at the end of the d= ay you're simply moving data from a source to a destination with the expect= ation that everything sent gets received, then the golden model for that wo= uld be to take whatever is sent and post that to the expected output queue. Now consider a case where the input data gets operated on to produce the ou= tput. The specification might say something like "JPEG compression" where = what comes out is radically different than what went in. Now you have to a= ctually compute what the expected output is and you have to use a known goo= d model for producing that golden output so you have to question the source= of that model. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.50.126.9 with SMTP id mu9mr1364436igb.6.1405097712442; Fri, 11 Jul 2014 09:55:12 -0700 (PDT) X-Received: by 10.50.12.70 with SMTP id w6mr121876igb.9.1405097712262; Fri, 11 Jul 2014 09:55:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!r10no1059830igi.0!news-out.google.com!gf2ni6igb.0!nntp.google.com!r10no1059817igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Jul 2014 09:55:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Jim Lewis Injection-Date: Fri, 11 Jul 2014 16:55:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3223 X-Received-Body-CRC: 2205373041 Xref: news.eternal-september.org comp.lang.vhdl:7614 Hi Al,=20 The first problem is that the terminology is evolving and means different t= hings to different people. One good source of terminology is the book, "Co= mprehensive Functional Verification". =20 A "golden model" or reference model answers the question, how do I predict = what is going on in the system. Some designs need them, some don't. A scoreboard is simply a means for correlating transactions into a DUT with= responses. =20 A checker simply provides a means for collecting outputs of a design and va= lidating functionality of a design. =20 A checker may operate alone or in conjunction with a reference model and/or= a scoreboard. For example, if Sync and Ref are simple std_logic values (i= e: =3D '1'), for every Sync there is a Ref, and there is no additional Sync= until the first Ref is received, then a checker model can validate this al= l by itself.=20 OTOH, if Sync and Ref are actually transaction values (such as Integer) and= the Ref value depends not only on Sync, but also on prior transactions, th= en it would be appropriate to use a reference model. If Ref depends only = on Sync, then again the checker model can validate it alone. Also if the system allows for pipelining of Sync and Ref, meaning, multiple= Sync transactions may be received before a Ref response, then you will nee= d a scoreboard. The scoreboard would store both the expected Ref value (if= not just a '1') and the time at which it must occur by (ie: Sync Time + 5 = us). This is a great example as it also demonstrates that a scoreboard mus= t support more than just simple "=3D" comparisons - in this case, the actua= l time value of receiving Ref must be less than or equal the expected time. BTW, the scoreboard model that we discuss and comes with SynthWorks' VHDL T= estbenches and Verification class, handles both inorder and out of order tr= ansaction responses, and also, supports parametrization so that it can hand= le cases like the last one described above (less than equal to comparisons = or more complex "ad hoc"). Cheers, Jim From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 12 Jul 2014 21:49:01 GMT Lines: 80 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> X-Trace: individual.net 09iViCiIv8r5VbTb3yQ1agSNTSWLKxtWqqo+48wcanRmOElOw8 X-Orig-Path: not-for-mail Cancel-Lock: sha1:LAVQycCJYL8DslZcQWV8RKbOI9Q= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7615 Hi Jim, Jim Lewis wrote: > The first problem is that the terminology is evolving and means > different things to different people. One good source of terminology > is the book, "Comprehensive Functional Verification". I went through it once...maybe it's time to go through it once again ;-) > A "golden model" or reference model answers the question, how do I > predict what is going on in the system. Some designs need them, some > don't. A golden model, as defined, does not need to be part of a test. Indeed it needs to be part of the 'test report', where you go through your collected data and check for each test if you passed or fail. > A scoreboard is simply a means for correlating transactions into a DUT > with responses. That is an extremely nice definition. A sort of a 'dictionary' where for each transaction there's a reply. Such a definition imply the need to be able to associate a reply to a transaction, no matter the order of the replies and or transactions. > A checker simply provides a means for collecting outputs of a design > and validating functionality of a design. As defined, I see this step as separate element in my verification effort, that not necessarily lives in the same moment of the result collections. Is like if I first pick up the mushrooms and only then select the good from the bad ones. > A checker may operate alone or in conjunction with a reference model > and/or a scoreboard. For example, if Sync and Ref are simple > std_logic values (ie: = '1'), for every Sync there is a Ref, and there > is no additional Sync until the first Ref is received, then a checker > model can validate this all by itself. > OTOH, if Sync and Ref are actually transaction values (such as > Integer) and the Ref value depends not only on Sync, but also on prior > transactions, then it would be appropriate to use a reference model. > If Ref depends only on Sync, then again the checker model can validate > it alone. If Ref 'depends' on multiple Sync, than the real 'transaction' is that multitude of Sync it is required to generate that Ref. Indeed there's always a one-to-one relation between an input transaction and an output one (unless the system is undeterministic and its output is not predictable only from the inputs and its state). At this point the transaction itself is made out of multiple packets (or events), which need to be stored in a suitable structure in the scoreboard. > > Also if the system allows for pipelining of Sync and Ref, meaning, > multiple Sync transactions may be received before a Ref response, then > you will need a scoreboard. The scoreboard would store both the > expected Ref value (if not just a '1') and the time at which it must > occur by (ie: Sync Time + 5 us). This is a great example as it also > demonstrates that a scoreboard must support more than just simple "=" > comparisons - in this case, the actual time value of receiving Ref > must be less than or equal the expected time. I would rather remove the checking from the scoreboard and leave it to the checker (possibly outside the simulation itself), in order to keep the scoreboard logic as simple as possible. > BTW, the scoreboard model that we discuss and comes with SynthWorks' > VHDL Testbenches and Verification class, handles both inorder and out > of order transaction responses, and also, supports parametrization so > that it can handle cases like the last one described above (less than > equal to comparisons or more complex "ad hoc"). If the scoreboard stores information in a file, a python dictionary would be a very simple and powerful structure to handle out of order transactions since it's a keyed list. That is why I'm actually thinking about separating the two tasks. As for the class...one day, I hope! ;-) From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 12 Jul 2014 21:49:16 GMT Lines: 49 Message-ID: References: <00510750-5d33-424d-bc8e-cbf51e284519@googlegroups.com> X-Trace: individual.net DigmiLW4kVBZIaNa8y6QTQa3JvLhnppptMy0WIc81jWetP+X0t X-Orig-Path: not-for-mail Cancel-Lock: sha1:UQgg1CZmLACEygSDnq3y5w5kIB8= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7616 Hi Kevin, KJ wrote: >> If all what I said does make sense to, at least some of, you then could >> someone explain me where is the need for a 'golden model' in this >> context? Isn't the requirement specification sufficient to fill our >> needs? > Now consider a case where the input data gets operated on to produce > the output. The specification might say something like "JPEG > compression" where what comes out is radically different than what > went in. Now you have to actually compute what the expected output is > and you have to use a known good model for producing that golden > output so you have to question the source of that model. Ok, I think I didn't pick the right example and therefore I failed to see the need of a 'complex' model and indeed, as you said, I was using a model anyway. And I'm also not particularly smart either since we do have more complex examples that would need a reference model, but I guess I was too fast in discarding its need. So the checker would need to *know* what to expect for a particular transaction and rise a flag if the test fails or pass. But, while I see some benefits in having a 'protocol checker' embedded in the testbench in order to /validate/ the transactions, I have some issues in understanding why would I need the checker with a golden model to be also embedded in my testbench. Wouldn't it be easier to record transactions, say on a file, and then post-process it? Unless the stimulus has to adapt to the checker status, I don't see a particular benefit in venturing with complex models in either vhdl or any other language in a mixed language simulation (too much money and too many quirks). A post-processing phase instead could be easily handled with any high-level language and has the advantage that does not need any co-simulation environment to deal with. Moreover it decouples completely the model from the test, the output could be compared with simple tools and you keep the freedom to write your reference in what suits best for the application. While I see the benefit of a model when I need to emulate the hardware/software environment *around* my DUT, I fail to see its use in verifying the DUT behavior. But, as already proved by my shortsightedness in the OP, I may miss again the bigger picture. From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Concurrent assignments vs. assignments inside a process Date: Sun, 13 Jul 2014 11:13:58 +0200 Lines: 23 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net 6Fq8QpZzZ34N343KnHYKlgMmapxuD0p0oxGR9CTE1vadhmtYhA Cancel-Lock: sha1:G54Axb9z88ISGbF1ROPrHFF4mVk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Xref: news.eternal-september.org comp.lang.vhdl:7617 Hi *, I'm sure one of you can clear this up: During debugging recently I discovered a bug in a module of mine: I had assigned a signal inside of a clocked process, but had also assigned it elsewhere concurrently (before writing the process, I had assigned it a different signal). Now, the result in simulation is as expected: the concurrent assignment usually "wins", with occasional 'X' in simulation. But what is unexpected to me is that the synthesis tools did not complain about this. I would have expected a "multiple drivers" error/warning or something similar. Why isn't there any? I always thought that a concurrent signal assignment is more or less just a less verbose version of a process with the right-hand-side signals in the sensitivity list. So basically what I had was assignments to the same signal from two different processes (one sequential one combinatorial), which should cause multiple drivers warnings. What would the hardware really do in that case, anyway? Sean From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Sun, 13 Jul 2014 20:38:47 -0400 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Jul 2014 00:38:56 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="131d71abdca206f852e85f753b3a8167"; logging-data="24886"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18LG/7nUZ3qFLlXvz2c8JO7" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:/4PGSqv9r4UMtp40A2Jur3jupFE= Xref: news.eternal-september.org comp.lang.vhdl:7618 On 7/13/2014 5:13 AM, Sean Durkin wrote: > Hi *, > > I'm sure one of you can clear this up: > > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? > > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? I would agree with what you about a concurrent statement being a shorthand version of a combinational process. I would have expected a multiple driver warning too. There may be something odd going on because one is clocked and the other combinational. But I expect this is a bug in any case. -- Rick From newsfish@newsfish Tue Dec 29 16:43:28 2015 X-Received: by 10.42.222.198 with SMTP id ih6mr8243484icb.18.1405299377129; Sun, 13 Jul 2014 17:56:17 -0700 (PDT) X-Received: by 10.182.225.162 with SMTP id rl2mr31194obc.13.1405299377001; Sun, 13 Jul 2014 17:56:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!h18no1173207igc.0!news-out.google.com!bp9ni7igb.0!nntp.google.com!h18no1173202igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 13 Jul 2014 17:56:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about driver, variable? From: fl Injection-Date: Mon, 14 Jul 2014 00:56:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7619 Hi, On VHDL books, it says that each signal having an assignment has a driver. I have a question about variable. Has a variable a driver? Please clarify the concept for me. Thanks, From newsfish@newsfish Tue Dec 29 16:43:28 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 14 Jul 2014 06:31:46 GMT Lines: 50 Message-ID: References: X-Trace: individual.net 7gd2Xi3FROhd1FQVqtyTZARWvxMbhfpI6BaewaEE01OCH15lgr X-Orig-Path: not-for-mail Cancel-Lock: sha1:MlwvpNgBk6oZxL9LvxWId66oDzY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7620 Hi Sean, Sean Durkin wrote: [] > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). I'm assuming your signal is of a resolved type, say std_logic or std_logic_vector. These types *can* have multiple drivers since they have a resolution function to resolve the conflict. Nevertheless I would not recommend resolved types for synthesis unless strictly necessary (bus), they may hide nasty bugs. > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? An unresolved signal cannot be synthesized because the synthesis tool does not have a way to know what would be the output driving the signal for a specific configuration of its drivers. A resolved signal allows you to have multiple sources driving the signal and it would be up to the designer to make sure the result is what it is expected (think of a bus). > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. I would rather think they are two different language constructs, each with its own characteristics. You can infer a register with a concurrent assignment, but not a latch. Which one you use is a matter of style, as long as it matches your desired behavior. > So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? If I were you I'd program the device and see what happens (if the target is a ram/flash based device). Otherwise you can always simulate the postsynth results and verify it through your testbench (which you should anyhow). I'm not sure what the hardware will do when the signal is 'U' or 'X' Al From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 11:55:51 +0200 Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net BwnzxdNoqZwSUzmVDyqBBQsUqjs+BpZcOOdjw644WuAKR/PVRz Cancel-Lock: sha1:yrAJp9iCfKJuOV5vzafCTtTlHPA= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:7621 alb wrote: > A resolved signal allows you to have multiple sources driving the signal > and it would be up to the designer to make sure the result is what it is > expected (think of a bus). Then why does the synthesis tool ALWAYS issue a "multiple drivers" error when a (resolved!) signal is being driven from two processes? It just doesn't if one of the assignments is concurrent and not inside a process. - signal driven from two processes -> "multiple drivers" error - signal driven from one process and a concurrent assignment -> nothing The signal might be resolved, but to 'X'. How is that going to help a synthesis tool decide what to do? It's not, and that's why I had expected it to complain. >> I always thought that a concurrent signal assignment is more or less >> just a less verbose version of a process with the right-hand-side >> signals in the sensitivity list. > I would rather think they are two different language constructs, each > with its own characteristics. You can infer a register with a concurrent > assignment, but not a latch. Which one you use is a matter of style, as > long as it matches your desired behavior. I looked it up in Ashenden's "Designer's Guide": "Concurrent signal assignment statements are equivalent to sequential signal assignments contained in process statements." So that doesn't really help explain anything here, unfortunately. I'm sure there's something more specific in the LRM... > If I were you I'd program the device and see what happens (if the target > is a ram/flash based device). Of course I did that already. The concurrent assignment wins. The question is: why? > I'm not sure what the hardware will do when the signal is 'U' or 'X' Neither am I, and that is really the question here. With 'U' I would assume it just sets everything to '0', because at least in Xilinx FPGAs everything's initialized to '0' as a default. So that is more or less "well-defined" and "logical" behaviour. If undriven, default to '0' (or even optimize away). Not so much for 'X', don't know how the decision process works there. If I had the time right now, I'd try using an unresolved signal to see if that makes any difference in synthesis. Greetings, Sean From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.70.43.77 with SMTP id u13mr7411028pdl.0.1405331790862; Mon, 14 Jul 2014 02:56:30 -0700 (PDT) X-Received: by 10.182.236.10 with SMTP id uq10mr10948obc.18.1405331790606; Mon, 14 Jul 2014 02:56:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no1305414igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no486512igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 02:56:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Thomas Stanka Injection-Date: Mon, 14 Jul 2014 09:56:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2975 X-Received-Body-CRC: 785147415 Xref: news.eternal-september.org comp.lang.vhdl:7622 Am Sonntag, 13. Juli 2014 11:13:58 UTC+2 schrieb Sean Durkin: > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? I would expect Warning, no Error. In fact this is legal and the resulting h= ardware is legal, but very likely to do real bad things, as each time you s= ee an X in simulation, your HW might have a bus conflict with shortcut from= power supply to ground. Therefore it is good idea to use std_ulogic instea= d of std_logic to detect those errors in compile phase of your design. > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side You are right, if you remove the "or less" :). A concurrent signal is a pro= cess with right hand side as sensitivity list. > combinatorial), which should cause multiple drivers warnings. What would= =20 > the hardware really do in that case, anyway? Depending on technology and synthesis tool, you have a bus with multiple dr= iver=20 directly or through some wired-or constructs. A bus with multiple driver is= considered legal for technologies with internal tristate buffer, but it is= up to you(the designer) to ensure no condition of the bus can occure that = damages the device permanently. Therefore be carefule with the "try and err= or" suggestion of alb. While a lot of technologies and synthesis tools will= come up with a solution that is harmless for the device, there is no guara= ntee of such in general. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.43.70.132 with SMTP id yg4mr9278667icb.30.1405338170307; Mon, 14 Jul 2014 04:42:50 -0700 (PDT) X-Received: by 10.182.66.131 with SMTP id f3mr12143obt.25.1405338170207; Mon, 14 Jul 2014 04:42:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1344864igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no506754igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:42:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:42:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7623 On Sunday, July 13, 2014 5:13:58 AM UTC-4, Sean Durkin wrote: >=20 > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" >=20 > error/warning or something similar. Why isn't there any? >=20 You should submit a ticket to the synthesis vendor. Without the code or kn= owing which tool you're using nobody here can help unless they happen to ha= ve run across the exact same problem. But you are correct, you should get = a multiple drivers error on this. A way to catch this sooner (i.e. while you're still in simulation mode) is = to use std_ulogic rather than std_logic. That way you'll have the error re= ported to you either when you first compile the file or when the simulation= starts up. There is no reason to use std_logic in an FPGA design except at the top lev= el for signals such as a data bus that are driven by multiple sources. FPG= As do not allow for this internally, so there is no reason to use std_logic= , use the proper type, std_ulogic/std_ulogic_vector. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.66.182.130 with SMTP id ee2mr7918288pac.37.1405338461999; Mon, 14 Jul 2014 04:47:41 -0700 (PDT) X-Received: by 10.182.249.108 with SMTP id yt12mr13491obc.17.1405338461886; Mon, 14 Jul 2014 04:47:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no1346943igc.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no507678igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:47:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:47:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2311 X-Received-Body-CRC: 3072080712 Xref: news.eternal-september.org comp.lang.vhdl:7624 On Monday, July 14, 2014 2:31:46 AM UTC-4, alb wrote: > > I'm assuming your signal is of a resolved type, say std_logic or > std_logic_vector. These types *can* have multiple drivers since they > have a resolution function to resolve the conflict. Nevertheless I would > not recommend resolved types for synthesis unless strictly necessary > (bus), they may hide nasty bugs. > There are no nasty bugs to be hidden. Multiple drivers of a signal no longer exist in FPGAs with the exception of I/O pins. > > An unresolved signal cannot be synthesized because the synthesis tool > does not have a way to know what would be the output driving the signal > for a specific configuration of its drivers. > This makes absolutely no sense. All of the signals inside an FPGA come from exactly one driver. That is basically the definition of unresolved (i.e std_ulogic, std_ulogic_vector). > > A resolved signal allows you to have multiple sources driving the signal > and it would be up to the designer to make sure the result is what it is > expected (think of a bus). > Just don't think of using it in an FPGA design except on the I/O pins. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.236.159.198 with SMTP id s46mr6652739yhk.17.1405338816090; Mon, 14 Jul 2014 04:53:36 -0700 (PDT) X-Received: by 10.182.29.38 with SMTP id g6mr89360obh.12.1405338815984; Mon, 14 Jul 2014 04:53:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no383514qac.1!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no508955igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 04:53:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26ef915d-f0c0-46d3-8b48-934a3d6c8873@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: KJ Injection-Date: Mon, 14 Jul 2014 11:53:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1981 X-Received-Body-CRC: 2091072233 Xref: news.eternal-september.org comp.lang.vhdl:7625 On Monday, July 14, 2014 5:56:30 AM UTC-4, Thomas Stanka wrote: > I would expect Warning, no Error. In fact this is legal and the resulting > hardware is legal, No, it would be an error, not a warning. If a synthesis tool actually allows two drivers to be connected, there is a bug in the synthesis tool. Since by design they do not, the following that you wrote is completely wrong... > but very likely to do real bad things, as each time you see > an X in simulation, your HW might have a bus conflict with shortcut from power > supply to ground But the following is sound advice. All internal FPGA signals should be std_ulogic / std_ulogic_vector. > Therefore it is good idea to use std_ulogic instead of > std_logic to detect those errors in compile phase of your design. > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: Mon, 14 Jul 2014 14:59:30 +0100 Organization: TRW Conekt Lines: 18 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net YLHcnKGRcrGG+LoGA36/dgt+r4meiwkvB+VcHZJn6oEiYGx08= Cancel-Lock: sha1:Rl++mP1LSfPmHxRcdChNHQPWo9Q= sha1:QvvShGNPQPL7CTkvJoSKUODaV2A= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:7626 al.basili@gmail.com (alb) writes: > I would rather remove the checking from the scoreboard and leave it to > the checker (possibly outside the simulation itself), in order to keep > the scoreboard logic as simple as possible. One reason to keep the checker inside the simulation is to make sure you fail as soon as possible. You don't want to have to wait for the simulation to finish after many hours only to find that the error could have been flagged only minutes into the test! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 17:20:05 +0200 Lines: 60 Message-ID: References: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net GM/DyZvFttDGN6ASct8ocAMpfgHbB9B69GywpPl/OeABy9NJLI Cancel-Lock: sha1:91HGIDFZhihNVOkHBSESnc/lpsU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <853610dc-bb2c-4fee-b65f-13fc75f33d3d@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:7627 Hi KJ, KJ wrote: > You should submit a ticket to the synthesis vendor. Without the code > or knowing which tool you're using nobody here can help unless they > happen to have run across the exact same problem. But you are > correct, you should get a multiple drivers error on this. That's what I wanted to know. It's not that I didn't find the bug or anything, my testbench caught it quickly (although not as quickly as it would have when using std_ulogic), it's that I didn't understand the synth tool's reaction, or better non-reaction. This was just one of those occasions where you do a tiny adjustment shortly before going to a meeting, start up a simulation-run before leaving and then decide that the probability of it working now is so high that you might just start synthesis as well to save some time. When I came back it turned out simulation had failed but synthesis had completed successfully, without as much as a warning message in the logfiles. (FWIW, this was Xilinx Vivado synthesis, and there's no easy way anymore to submit tickets unless you're a big customer. You always have to go through your FAE, who was hopelessly overloaded before being responsibly for accepting tickets in addition to all his other duties. So before going through him I at least want to make sure that I'm not just misunderstanding things and this is all perfectly expected behaviour. The only alternative is to post in their user forums and hope someone feels responsible.) > There is no reason to use std_logic in an FPGA design except at the > top level for signals such as a data bus that are driven by multiple > sources. FPGAs do not allow for this internally, so there is no > reason to use std_logic, use the proper type, > std_ulogic/std_ulogic_vector. You are of course right. But someone should tell Xilinx... Almost every IP-Core, every example design, every code snippet or template they provide uses std_logic(_vector) exclusively. In fact, what I was doing was to drive an IP-Core-FIFO control signal, and of course they use std_logic as the type for all ports, not std_ulogic, so I hooked it up to a std_logic as well instead of using std_ulogic (which probably would have caught it right at the start of simulation). Just for some of their hardmacros, they provide component declarations with some (not all) ports being of type std_ulogic(_vector), the rest is std_logic. Because of this, trying to enforce usage of std_ulogic usually results in type casting madness whenever Xilinx-stuff is involved (or is there some elegant, less verbose way to solve this?). This seems to be easier, less-verbose in VHDL-2008 (it seems that e.g. connecting a core's std_logic_vector output port to a std_ulogic_vector signal is now accepted; compiling with VHDL-2002 I get a type mismatch error in ModelSim), but that's not yet supported in most synthesis tools so I can't really use it. Greetings, Sean From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Mon, 14 Jul 2014 11:30:44 -0400 Organization: Alacron, Inc. Lines: 24 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 14 Jul 2014 15:32:09 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="7710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wv4fcObUV6BciwHoJs64dO3S6JXBg+zo=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:gaQHCqaPPbIaxXq19QIhvJbVO1E= Xref: news.eternal-september.org comp.lang.vhdl:7628 Sean Durkin wrote: [snip] >> If I were you I'd program the device and see what happens (if the target >> is a ram/flash based device). > Of course I did that already. The concurrent assignment wins. The > question is: why? > This is only a guess, but if a truly concurrent assignment is continuous - i.e. doesn't really depend on inputs changing, but acts like a wire to constantly update the output. One of these constantly updated drivers would "win" against any other procedural driver because the output of the process would only affect the net for a zero time period (say one delta delay for simulation) after the process runs. Again it's only a guess, and I agree that synthesis should complain about multiple drivers rather than going ahead and letting the concurrent assignment "win." -- Gabor From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.182.19.138 with SMTP id f10mr784047obe.25.1405354351034; Mon, 14 Jul 2014 09:12:31 -0700 (PDT) X-Received: by 10.182.104.226 with SMTP id gh2mr14896obb.37.1405354350895; Mon, 14 Jul 2014 09:12:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no574821igc.0!news-out.google.com!bp9ni28igb.0!nntp.google.com!h18no1453108igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 09:12:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46008d37-d320-41be-bdb1-48d42ec2a28d@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Mon, 14 Jul 2014 16:12:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7629 Multiple driver warnings in synthesis are usually triggered by multiple ass= ignments without any 'Z' values being conditionally driven.=20 If both of your assignments conditionally drive data or 'Z' onto the signal= , then some synthesis tools will handle converting the multiple tri-state s= ignals to muxed data, and if that signal is for chip-level IO, synthesis wi= ll handle the output enable control (for the implied TS buffer in the IOB). Depending on the synthesis tool and what options are set, some synthesis to= ols will convert internal tri-state "busses" into multiplexers, etc. genera= ting an output for single net. Some will even split up bi-directional tri-s= tate busses, and replace them with multiplexers, etc. I don't necessarily r= ecommend using this feature. Otherwise, I'm not sure what your problem might be. Andy From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.182.95.40 with SMTP id dh8mr8596166obb.5.1405355186187; Mon, 14 Jul 2014 09:26:26 -0700 (PDT) X-Received: by 10.182.153.200 with SMTP id vi8mr27054obb.23.1405355186054; Mon, 14 Jul 2014 09:26:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no1459887igc.0!news-out.google.com!bp9ni28igb.0!nntp.google.com!h18no1459881igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 14 Jul 2014 09:26:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05910271-f443-42f2-a961-7218a99a8f49@googlegroups.com> Subject: Re: Question about driver, variable? From: Andy Injection-Date: Mon, 14 Jul 2014 16:26:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7630 No, variables do not have a sense of time or scheduled updates, so they do = not have "drivers" like signals do.=20 Note that unless the variable is shared, only one process can update and re= ad it anyway. The variable contents are updated immediately upon execution of an assignme= nt statement for that variable. The value persists as long as the variable = persists (which, in a process, is for the duration of the simulation), unti= l it is updated by a subsequently executed assignment.=20 The persistence of a variable's values, in synthesis, can imply either a wi= re or storage (latch or register), depending on the context of updates and = accesses to the value. Andy From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models Date: 15 Jul 2014 06:15:09 GMT Lines: 32 Message-ID: References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> X-Trace: individual.net 6Sbba8je0SKFbLt9Epa+sAJajqhjZF2n2BKUugAlxitn2XAKL9 X-Orig-Path: not-for-mail Cancel-Lock: sha1:9CGj6gbu5IMFPEhbonRuk1Rhk/U= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7631 Hi Martin, Martin Thompson wrote: [] >> I would rather remove the checking from the scoreboard and leave it to >> the checker (possibly outside the simulation itself), in order to keep >> the scoreboard logic as simple as possible. > > One reason to keep the checker inside the simulation is to make sure you > fail as soon as possible. You don't want to have to wait for the > simulation to finish after many hours only to find that the error could > have been flagged only minutes into the test! True, I believe though that running many hours simulation is not really necessary and often you can break it up in several testcases. Unless you need many hours to 'configure' properly the DUT for a specific test, you could generally think that a test case is a finite and relatively small number of transactions. If you are thinking about Constrained Randomization, you can always break the verification in several simulation runs by merging the coverage collected on the way. The real issue is that modelling is not extremely straight forward with vhdl and you immediately find yourself in a mixed language simulation environment which requires expensive licenses. I found for instance that python is extremely powerful at producing relatively accurate models with very small efforts. The issue is how to embed a python model into a vhdl based testbench? I've recently heard about 'cocotb', maybe I should give it a try, but I've read it has problems with Modelsim/Questa, which is the simulator we are using. From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 15 Jul 2014 06:35:40 GMT Lines: 56 Message-ID: References: X-Trace: individual.net z/qndFymWCiTRxOlncNeUQMZn1dIOnB8IJkhnzQauAVL/l7k/h X-Orig-Path: not-for-mail Cancel-Lock: sha1:m+LbKXo9EPWDlQy8M9EmxPV2kq0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7632 Hi Kevin, KJ wrote: > On Monday, July 14, 2014 2:31:46 AM UTC-4, alb wrote: >> >> I'm assuming your signal is of a resolved type, say std_logic or >> std_logic_vector. These types *can* have multiple drivers since they >> have a resolution function to resolve the conflict. Nevertheless I would >> not recommend resolved types for synthesis unless strictly necessary >> (bus), they may hide nasty bugs. >> > There are no nasty bugs to be hidden. Multiple drivers of a signal no > longer exist in FPGAs with the exception of I/O pins. I was referring to the fact that the OP didn't realize about the multiple drivers issue during simulation therefore hiding a 'bug' for a long time before being uncovered. >> An unresolved signal cannot be synthesized because the synthesis tool >> does not have a way to know what would be the output driving the signal >> for a specific configuration of its drivers. >> > This makes absolutely no sense. All of the signals inside an FPGA > come from exactly one driver. That is basically the definition of > unresolved (i.e std_ulogic, std_ulogic_vector). Oops, you are right! It didn't make sense at all! I wanted to say that an unresolved type signal driven by multiple drivers cannot be implemented because the tool does not have a way to know what to drive when a conflict arise. Using resolved signals internally to an FPGA is not necessarily bad though. There's an interesting AN from B.Cohen (klabs.org/richcontent/software_content/vhdl/force_errors.pdf) which is using user defined resolution functions to inject errors onto a signal. Interestingly enough you could use a configuration to wrap your architecture with the extra component for error injection *only* during verification and removing it when performing synthesis. A very useful usecase is when you need to verify an EDAC. >> A resolved signal allows you to have multiple sources driving the signal >> and it would be up to the designer to make sure the result is what it is >> expected (think of a bus). >> > > Just don't think of using it in an FPGA design except on the I/O pins. I've often used resolved signals inside FPGAs to describe tristated busses with multiple drivers, I find the syntax much more readable. Synplify Pro AE has always been relatively useful to understand the code and implement the necessary muxes, it is also documented in their language guideline. Al From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.70.24.163 with SMTP id v3mr4715807pdf.8.1405429710079; Tue, 15 Jul 2014 06:08:30 -0700 (PDT) X-Received: by 10.182.128.131 with SMTP id no3mr147785obb.9.1405429709960; Tue, 15 Jul 2014 06:08:29 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!h18no904686igc.0!news-out.google.com!bp9ni210igb.0!nntp.google.com!h18no1941736igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Jul 2014 06:08:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Tue, 15 Jul 2014 13:08:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7633 On Tuesday, July 15, 2014 1:35:40 AM UTC-5, alb wrote: > Interestingly enough you could use a configuration to wrap your architect= ure with the extra component for error injection *only* during verification= and removing it when performing synthesis. A very useful usecase is when y= ou need to verify an EDAC.=20 You don't even need to use a configuration (which then requires component d= eclarations and instantiations from the top, all the way down to the module= of interest) to try this. If your EDAC module is instantiated as an entity, WITHOUT an architecture s= pecification (e.g. rtl), then, after you compile all your RTL into the simu= lator, compile a wrapper architecture for your EDAC module. Inside that wra= pper, you re-instantiate the module again, but WITH the architecture specif= ication (rtl). Then you can do anything you want between the module and the= rest of the design, inside that wrapper architecture. You can modify/monit= or interface signals, insert funnctional coverage (OSVVM), and even use hie= rarchical references to check on signals inside EDAC (like covering the EDA= C's FSM state signal). Andy From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 15 Jul 2014 19:47:48 GMT Lines: 36 Message-ID: References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> X-Trace: individual.net pGvwMAcVrXpV0hp58Xxj8QofTc98UnlEx/kcNdMJglVF6dOI+3 X-Orig-Path: not-for-mail Cancel-Lock: sha1:2VbZgwPU/UivLygl3Mt4IewC9gg= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7634 Hi Andy, Andy wrote: >> Interestingly enough you could use a configuration to wrap your >> architecture with the extra component for error injection *only* >> during verification and removing it when performing synthesis. A very >> useful usecase is when you need to verify an EDAC. [] > If your EDAC module is instantiated as an entity, WITHOUT an > architecture specification (e.g. rtl), then, after you compile all > your RTL into the simulator, compile a wrapper architecture for your > EDAC module. Inside that wrapper, you re-instantiate the module again, > but WITH the architecture specification (rtl). So you are suggesting to have the entity and architecture on separate files, compile all of them and compile *last* the wrapper with the component instantiated. You are leveraging the fact the last 'object' compiled for that entity's architecture is the wrapper one therefore would be the one used for the sim. In synthesis though you would certainly not compile the wrapper and have only the rtl architecture. What about post-synth sims then? Do you perform the same amount of testing you do for your verification? (it seems not so). > Then you can do > anything you want between the module and the rest of the design, > inside that wrapper architecture. You can modify/monitor interface > signals, insert funnctional coverage (OSVVM), and even use > hierarchical references to check on signals inside EDAC (like covering > the EDAC's FSM state signal). I'm trying to convince my team to work with OSVVM and leverage these capabilities, unfortunately not everyone is onboard and sometimes the we are entrenched behind beliefs which are extremely wrong and hopelessly misleading (sob). From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: coverage collection Date: 15 Jul 2014 20:25:27 GMT Lines: 64 Message-ID: X-Trace: individual.net F2tvlesWJNDzkrw2oTF3xwyTkudDkQwWHfvQ8wVcB4r58RzNmR X-Orig-Path: not-for-mail Cancel-Lock: sha1:GT7SA2qs16Ogp04ikJmShP+gP+0= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7635 Hi everyone, this morning a member of the verification team found a bug in a testbench which lead to think we were testing a particular feature of the design while we were not (that's bad)! Likely enough the feature did fail at system level and we are now busy fixing it (that's good). We are too smart to perform any functional coverage collection and therefore rely on the fact that our direct tests are actually testing what they are supposed to do. Everyone seems pretty confortable with this situation while I'm not really. My argument against the current organization is that if we do not 'collect' our functional coverage we cannot know when and if we are done. Even though some boss believes that code coverage is all you need (and hopefully most of us know that that's not the case!), when I try to argument the need of a functional coverage collection I start to wander: wait a minute, what if our coverage model is not correct. What if we believe we are done just because we are doing functional coverage verification and we 'measure' that function A has been exercised. What if we 'believe' we have done a test against function A, happily recording the transaction which was supposedly defined to test it, while in reality the transaction got sidetracked by a stupid bug which did not cause the function A to be tested at all? I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, and I found it very interesting, especially when he talked about Intelligent Coverage but then something stroke me, let's see this snippet of code [1]: -- from the presentation, available to registered users. while not ACov.IsCovered loop (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins DoAluOp(Trec, Reg1, Reg2); -- do transaction Acov.Icover((Reg1, Reg2)); -- mark it covered end loop; In the above snippet the real transaction is DoAluOp, which is supposed to do something with registers Reg[12], but we mark the bin as covered even though there's no real feedback from the transaction result. We are measuring coverage, we generate a transaction, but where did it ended? how can we be sure that we really tested what we believed? Isn't this the very same situation my colleague met this morning? On top of that, how can we collect coverage when using direct testing? Al [1] I hope Jim does not get upset for having used a snippet from his presentation :-/ -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: OSVVM vs UVM/OVM w.r.t. processor resources Date: 15 Jul 2014 20:47:17 GMT Lines: 31 Message-ID: X-Trace: individual.net 2IeofNaSHdvCbg6SZRT6pAj7AImCKf55isvTjwyQfGDL53BuF1 X-Orig-Path: not-for-mail Cancel-Lock: sha1:brXM850KkhT+/wq6x5Cb8JbGkcI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7636 Hi everyone, while trying to convince someone to have a look at the OSVVM package I got told that vhdl-2008 cannot be as efficient as SystemVerilog or SystemC in handling processor resources therefore a bench with UVM/OVM is certainly far more efficient [1] than one with OSVVM. Not knowing what are the performances of UVM/OVM I couldn't certainly argue against it, but is it really the case? I know about the Intelligent Coverage in OSVVM is o(log(N)) more efficient than its companion Constrained Random in SV, but what about memory allocation for instance? Or task switching? SystemC is certainly very flexible being derived from C++, but is that factor so important in simulation? What about the synchronization messages between the two simulation cores (if that is how they are called)? Any comment is appreciated, Al [1] we talk only about processor's resources here, nothing related to ease of adoption of the package, licenses cost and features set. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.236.92.69 with SMTP id i45mr11712390yhf.20.1405477821870; Tue, 15 Jul 2014 19:30:21 -0700 (PDT) X-Received: by 10.182.61.9 with SMTP id l9mr189618obr.1.1405477821634; Tue, 15 Jul 2014 19:30:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no1003218qaq.0!news-out.google.com!bp9ni9igb.0!nntp.google.com!h18no1202716igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 15 Jul 2014 19:30:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8b4cb4f2-5149-40cb-af32-fdca33ff9f4b@googlegroups.com> Subject: Re: coverage collection From: KJ Injection-Date: Wed, 16 Jul 2014 02:30:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7637 On Tuesday, July 15, 2014 4:25:27 PM UTC-4, alb wrote: > this morning a member of the verification team found a bug in a=20 > testbench which lead to think we were testing a particular feature of=20 > the design while we were not (that's bad)!=20 No, actually that's good. If your verification team does not find bugs, th= en most likely they are not trying or the design is very mature and only su= bject to relatively minor changes. > Likely enough the feature did=20 > fail at system level and we are now busy fixing it (that's good).=20 Yes it is > My argument against the current organization is that if we do not=20 > 'collect' our functional coverage we cannot know when and if we are done.= =20 That is typically the case. There aren't a whole lot of real world designs= where everything gets specified exactly enough and the test cases get defi= ned exactly enough so that you can get an a priori view that you can then t= rack to completion. > Even though some boss believes that code coverage is all you need (and=20 > hopefully most of us know that that's not the case!), when I try to=20 > argument the need of a functional coverage collection I start to wander:= =20 > wait a minute, what if our coverage model is not correct. What if we=20 > believe we are done just because we are doing functional coverage=20 > verification and we 'measure' that function A has been exercised. What=20 > if we 'believe' we have done a test against function A, happily=20 > recording the transaction which was supposedly defined to test it, while= =20 > in reality the transaction got sidetracked by a stupid bug which did not= =20 > cause the function A to be tested at all?=20 What you described seems to me to have nothing to do with functional covera= ge. Instead it sounds like the checking was not quite robust enough. The intended test was performed (albeit incorrectly), but the checker did n= ot catch that the correct response to the intended test did not occur. Sou= nds to me that there were two errors, not one as you reported. The checker= should first be upgraded to detect and report the incorrect (or lack of) r= esponse to the test as it was originally written. Then the stimulus should= be updated to perform the intended test. > =20 > -- from the presentation, available to registered users.=20 >=20 > while not ACov.IsCovered loop=20 >=20 > (Reg1, Reg2) :=3D Acov.RandCovPoint; -- randomize uncovered bins=20 > DoAluOp(Trec, Reg1, Reg2); -- do transaction=20 > Acov.Icover((Reg1, Reg2)); -- mark it covered=20 >=20 > end loop;=20 >=20 > =20 > In the above snippet the real transaction is DoAluOp, which is supposed= =20 > to do something with registers Reg[12], but we mark the bin as covered=20 > even though there's no real feedback from the transaction result.=20 Not sure about your point here. Are you saying - It is not possible to check that Reg[12] responded properly? - Reg1 and Reg2 were used where Reg[12] should have been used? The answer to the first scenario is that will never be the case unless Reg[= 12] controls nothing. There should be a verifiable response to everything.= Getting that response might be rather involved but if it is intended to d= o something then it can be verified in theory. Sometimes those tests need = to be performed at a unit level if the system level test is impossibly long= to run. In that case, one would have to verify at the system level on act= ual hardware rather than in simulation. The answer to the second scenario is that right now you have some additiona= l checking of Reg1 and Reg2 that you had not really intended (but it's ther= e now and works) and you need to add some more code to test Reg12. This ju= st means the testbench needs some more work. If you're thinking that havin= g a bug in a testbench is somehow worse than a bug in the design than you a= re a bit shortsighted. You should view every line of code written equally.= A given line of code is just as likely to be wrong no matter where it is = located. > We are measuring coverage, we generate a transaction, but where did it=20 > ended? how can we be sure that we really tested what we believed? Isn't= =20 > this the very same situation my colleague met this morning?=20 The short answer is that in most situations is that you can't be sure. Som= e niches of designs might be able to be provably correct but most will not.= That's not to say that you shouldn't be using good testing and design tec= hniques, but don't expect those techniques to be implemented flawlessly. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: coverage collection Date: 16 Jul 2014 07:54:32 GMT Lines: 120 Message-ID: References: <8b4cb4f2-5149-40cb-af32-fdca33ff9f4b@googlegroups.com> X-Trace: individual.net cWhePI8v3CYh3OgHXiVPwgtTC/HUuVE6yoaVckX3EPdJydmV77 X-Orig-Path: not-for-mail Cancel-Lock: sha1:CmfSyph9zGhDpIGbJ8s4PlcftWI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7638 Hi Kevin, KJ wrote: > On Tuesday, July 15, 2014 4:25:27 PM UTC-4, alb wrote: >> this morning a member of the verification team found a bug in a >> testbench which lead to think we were testing a particular feature of >> the design while we were not (that's bad)! > > No, actually that's good. If your verification team does not find > bugs, then most likely they are not trying or the design is very > mature and only subject to relatively minor changes. Indeed, I was focused on the 'half empty' glass... ;-) >> Even though some boss believes that code coverage is all you need (and >> hopefully most of us know that that's not the case!), when I try to >> argument the need of a functional coverage collection I start to wander: >> wait a minute, what if our coverage model is not correct. What if we >> believe we are done just because we are doing functional coverage >> verification and we 'measure' that function A has been exercised. What >> if we 'believe' we have done a test against function A, happily >> recording the transaction which was supposedly defined to test it, while >> in reality the transaction got sidetracked by a stupid bug which did not >> cause the function A to be tested at all? [] > The intended test was performed (albeit incorrectly), but the checker > did not catch that the correct response to the intended test did not > occur. Sounds to me that there were two errors, not one as you > reported. The checker should first be upgraded to detect and report > the incorrect (or lack of) response to the test as it was originally > written. Then the stimulus should be updated to perform the intended > test. Yes, you are right. There was a combination of two errors, one in the stimulus and one in the checker. None of them were spotted in time and only 'luck' helped us out. We were actually lucky that the issue came out at system level, but I'd like to understand why not earlier and what can we do to improve this situation. >> >> -- from the presentation, available to registered users. >> >> while not ACov.IsCovered loop >> >> (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins >> DoAluOp(Trec, Reg1, Reg2); -- do transaction >> Acov.Icover((Reg1, Reg2)); -- mark it covered >> >> end loop; >> >> >> In the above snippet the real transaction is DoAluOp, which is supposed >> to do something with registers Reg[12], but we mark the bin as covered >> even though there's no real feedback from the transaction result. > > Not sure about your point here. Are you saying > - It is not possible to check that Reg[12] responded properly? In the above example we assume that injecting Reg1 and Reg2 we are covering the intended case, *assuming* DoAluOp does what is supposed to do. > - Reg1 and Reg2 were used where Reg[12] should have been used? negative. My regexp notation for Reg1 and Reg2 was a bad choice that lead confusion. There's no Reg[12], only Reg1 and Reg2. > The answer to the first scenario is that will never be the case unless > Reg[12] controls nothing. There should be a verifiable response to > everything. That's is what it *should*, but here it was not the case. Is it a matter of code review? plan? report? model? > Getting that response might be rather involved but if it > is intended to do something then it can be verified in theory. Assume we inject Reg1 and Reg2 in order to have a Reg3=0 (I'm oversimplifying here). It is possible that Reg1 and Reg2 did not operate at all on Reg3, but for some reason the value of Reg3 is still correct. I realize the example is a bit too stupid to be representative but the point is still valid. The functional coverage should aim at generating the /condition/ *and* /measuring/ that something *did* happen (like a transition in Reg3 from one value to another). [] > If you're thinking that having a bug in a testbench is somehow worse > than a bug in the design than you are a bit shortsighted. You should > view every line of code written equally. A given line of code is just > as likely to be wrong no matter where it is located. It was not my intention to make you believe that I consider a testbench bug worse than a design one. All bugs are born equal, they only become severe if they have time to grow unnoticed. >> We are measuring coverage, we generate a transaction, but where did it >> ended? how can we be sure that we really tested what we believed? Isn't >> this the very same situation my colleague met this morning? > > The short answer is that in most situations is that you can't be sure. What I'm saying is that if a state of your sistem is controllable and observable there *must* be a way to A) define the inputs to control it to a particular value and B) observe that value happen. If we 'collect' only the fact that we have covered A) does not necessarily mean that B) is covered as well. > Some niches of designs might be able to be provably correct but most > will not. That's not to say that you shouldn't be using good testing > and design techniques, but don't expect those techniques to be > implemented flawlessly. My point here is not to point fingers on a wrong implementation, bugs are most likely there and will be there even if the final product behaves 'correctly'. My point is about trying to define a methodology which allows to anticipate these issues early in the development/verification cycle. From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx19.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: coverage collection References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405499944 86.29.12.221 (Wed, 16 Jul 2014 08:39:04 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 08:39:04 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 09:39:02 +0100 X-Received-Body-CRC: 132118099 X-Received-Bytes: 2648 Xref: news.eternal-september.org comp.lang.vhdl:7639 On 15/07/2014 21:25, alb wrote: Hi Al, .. > > I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, > and I found it very interesting, especially when he talked about > Intelligent Coverage but then something stroke me, let's see this > snippet of code [1]: > > > -- from the presentation, available to registered users. > > while not ACov.IsCovered loop > > (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins > DoAluOp(Trec, Reg1, Reg2); -- do transaction > Acov.Icover((Reg1, Reg2)); -- mark it covered > > end loop; > > > > In the above snippet the real transaction is DoAluOp, which is supposed > to do something with registers Reg[12], but we mark the bin as covered > even though there's no real feedback from the transaction result. > > We are measuring coverage, we generate a transaction, but where did it > ended? how can we be sure that we really tested what we believed? Isn't > this the very same situation my colleague met this morning? > Coverage (not code) is only measuring that we have applied all the required and corner test cases, is not concerned with checking correct behaviour. So you are right in the above code snipped there must be another module that checks the ALU operations. In most cases Coverage Based Verification and Assertion Based Verification goes hand in hand. > On top of that, how can we collect coverage when using direct testing? Simply use an assertion, PSL is IMHO the easiest as it support sequences but you can also use OVL or write a simple FSM that confirms the sequence. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!npeersf04.am4!fx06.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: OSVVM vs UVM/OVM w.r.t. processor resources References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 52 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405502382 86.29.12.221 (Wed, 16 Jul 2014 09:19:42 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 09:19:42 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 10:19:40 +0100 X-Received-Body-CRC: 1380895920 X-Received-Bytes: 3271 Xref: news.eternal-september.org comp.lang.vhdl:7640 Hi Al, On 15/07/2014 21:47, alb wrote: > Hi everyone, > > while trying to convince someone to have a look at the OSVVM package I > got told that vhdl-2008 cannot be as efficient as SystemVerilog or > SystemC in handling processor resources therefore a bench with UVM/OVM > is certainly far more efficient [1] than one with OSVVM. It is true that (SystemVerilog/SystemC) can run faster than VHDL, however, I suspect the difference will be too small to be concerned about unless you are running a regression test for several days. You also have to ask yourself the question, would you swap language and verification environment just to get a few extra % of performance? Wouldn't it be more cost effective to improve your code (Modelsim has a nice code/memory profiler) or just get a faster PC. > > Not knowing what are the performances of UVM/OVM I couldn't certainly > argue against it, but is it really the case? I suspect that UVM(SV) will be quite fast (and faster in the future unless another acronym is invented) for the simple reason that this is where EDA vendors are spending their R&D budget on. However, the UVM/OVM is IMHO hugely complex and a total overkill for the fast majority of us. Unless you are working on a huge xxM gate ASIC design, have a large verification team or have lots of re-usable/verification IP I would forget about the UVM (or OVM/VVM). > > I know about the Intelligent Coverage in OSVVM is o(log(N)) more > efficient than its companion Constrained Random in SV, but what about > memory allocation for instance? Or task switching? > > SystemC is certainly very flexible being derived from C++, but is that > factor so important in simulation? What about the synchronization > messages between the two simulation cores (if that is how they are > called)? Yes, I believe that you are right that dual language simulation is not as efficient as a single language one as the simulator has to handle 2 simulation kernels. For SystemC and VHDL the overhead is probably not that great as they are both based on the same scheduler model, however, (System)Verilog is quite different (has a lot more scheduler stages). Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx13.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> In-Reply-To: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140715-1, 15/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 19 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405503957 86.29.12.221 (Wed, 16 Jul 2014 09:45:57 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 09:45:57 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 10:45:55 +0100 X-Received-Body-CRC: 1061429652 X-Received-Bytes: 2634 Xref: news.eternal-september.org comp.lang.vhdl:7641 On 15/07/2014 14:08, Andy wrote: > On Tuesday, July 15, 2014 1:35:40 AM UTC-5, alb wrote: >> Interestingly enough you could use a configuration to wrap your architecture with the extra component for error injection *only* during verification and removing it when performing synthesis. A very useful usecase is when you need to verify an EDAC. > > You don't even need to use a configuration (which then requires component declarations and instantiations from the top, all the way down to the module of interest) to try this. > > If your EDAC module is instantiated as an entity, WITHOUT an architecture specification (e.g. rtl), then, after you compile all your RTL into the simulator, compile a wrapper architecture for your EDAC module. Inside that wrapper, you re-instantiate the module again, but WITH the architecture specification (rtl). Then you can do anything you want between the module and the rest of the design, inside that wrapper architecture. You can modify/monitor interface signals, insert funnctional coverage (OSVVM), and even use hierarchical references to check on signals inside EDAC (like covering the EDAC's FSM state signal). > > Andy > Or to make life even easier just use a bit of Tcl to force some errors in your EDAC code, this is how I tested my EDAC many many years ago. You only have to learn 3 Modelsim Tcl commands, "force/noforce", "when" and "examine". Regards, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: 16 Jul 2014 13:30:19 GMT Lines: 28 Message-ID: References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> X-Trace: individual.net qZ+e+LCFOxvFg2GgtgWxNQlD6bnezD7lBOP7eCiMKoOXLalHcZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:3URJzh28fM/nBLghRFDm1ny+rcI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: news.eternal-september.org comp.lang.vhdl:7642 Hi Hans, HT-Lab wrote: [] >> If your EDAC module is instantiated as an entity, WITHOUT an >> architecture specification (e.g. rtl), then, after you compile all >> your RTL into the simulator, compile a wrapper architecture for your >> EDAC module. Inside that wrapper, you re-instantiate the module >> again, but WITH the architecture specification (rtl). Then you can do >> anything you want between the module and the rest of the design, >> inside that wrapper architecture. You can modify/monitor interface >> signals, insert funnctional coverage (OSVVM), and even use >> hierarchical references to check on signals inside EDAC (like >> covering the EDAC's FSM state signal). >> > Or to make life even easier just use a bit of Tcl to force some errors > in your EDAC code, this is how I tested my EDAC many many years ago. You > only have to learn 3 Modelsim Tcl commands, "force/noforce", "when" and > "examine". The issue with your suggestion is that is not portable and will depend on the tcl implementation of your simulator. On top of this what Andy proposed is much more than just force some values; he is suggesting to implement coverage collection and/or protocol checkers or the likes. Indeed you may be capable to embed, within the wrapper, a verification IP to your module that allows you to perform much more than just forcing signals. From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx16.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: coverage collection References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140716-0, 16/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 44 Message-ID: <64wxv.226799$xk2.102762@fx16.am4> NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405521282 86.29.12.221 (Wed, 16 Jul 2014 14:34:42 UTC) NNTP-Posting-Date: Wed, 16 Jul 2014 14:34:42 UTC Organization: virginmedia.com Date: Wed, 16 Jul 2014 15:34:41 +0100 X-Received-Body-CRC: 3974387229 X-Received-Bytes: 2433 Xref: news.eternal-september.org comp.lang.vhdl:7643 On 16/07/2014 09:39, HT-Lab wrote: > On 15/07/2014 21:25, alb wrote: > Hi Al, > .. >> >> I recently followed a recorded webinar on OSVVM at Aldec, by J.Lewis, >> and I found it very interesting, especially when he talked about >> Intelligent Coverage but then something stroke me, let's see this >> snippet of code [1]: >> >> >> -- from the presentation, available to registered users. >> >> while not ACov.IsCovered loop >> >> (Reg1, Reg2) := Acov.RandCovPoint; -- randomize uncovered bins >> DoAluOp(Trec, Reg1, Reg2); -- do transaction >> Acov.Icover((Reg1, Reg2)); -- mark it covered >> >> end loop; >> >> >> >> In the above snippet the real transaction is DoAluOp, which is supposed >> to do something with registers Reg[12], but we mark the bin as covered >> even though there's no real feedback from the transaction result. >> >> We are measuring coverage, we generate a transaction, but where did it >> ended? how can we be sure that we really tested what we believed? Isn't >> this the very same situation my colleague met this morning? >> > > Coverage (not code) is only measuring that we have applied all the > required and corner test cases, is not concerned with checking correct > behaviour. Sorry it should read "is not normally concerned with", obviously you can use coverage to check behaviour. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Question about driver, variable? Date: Wed, 16 Jul 2014 18:34:06 +0100 Organization: TRW Conekt Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain X-Trace: individual.net xCqVzOHQZ0ELyWzGzyVu4AgbTAmCvyvUFdB9alUHeKQxHd8R0= Cancel-Lock: sha1:Ywwmh7a9AV2u0tWE/gPTjQFzE3g= sha1:cNFe0+5/X+0txYp2aKHKMCJ92YY= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (windows-nt) Xref: news.eternal-september.org comp.lang.vhdl:7644 fl writes: > Hi, > > On VHDL books, it says that each signal having an assignment has a driver. I > have a question about variable. Has a variable a driver? > Please clarify the concept for me. > No, a variable does not have a driver. Variables can only be changed within a process (unlike signals which can be changed - driven - from multiple processes) and the order in which assignment happen within that process define what the value of a variable is at any particular instant during the flow of execution. HTH, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.42.37.71 with SMTP id x7mr18371977icd.4.1405579353497; Wed, 16 Jul 2014 23:42:33 -0700 (PDT) X-Received: by 10.50.88.9 with SMTP id bc9mr434145igb.14.1405579353382; Wed, 16 Jul 2014 23:42:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no2925646igc.0!news-out.google.com!gf2ni864igb.0!nntp.google.com!h18no1546659igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 16 Jul 2014 23:42:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <565bc83c-554b-47b6-bb27-4afcfa69404c@googlegroups.com> Subject: Re: coverage collection From: Jim Lewis Injection-Date: Thu, 17 Jul 2014 06:42:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7645 Hi Al, I think the need for functional coverage revolves around complexity. As co= mplexity increases, the need for functional coverage increases. The need f= or it also increases as the design goes through revision cycles. As we go = to new chips, they have bigger memory resources. We may decide to leverage= this and increase FIFO size. We re-run the old directed testbench and it = passes, however, did we validate that the testbench still hits the boundary= conditions - some may, some may not. =20 Code coverage measures execution of lines of code. However, if the item we= need to make sure happens is not in the code, then we need functional cove= rage (both of the examples from the presentation require functional coverag= e). =20 Code coverage works well for code that only runs once per clock cycle. OTO= H, it is optimistic for combinational logic coded in a process with a sensi= tivity list. This process runs on delta cycles and may run multiple times = during a given clock cycle - as a result, it may report you have covered so= mething that you did not.=20 While code coverage works great for software, it seems some put too much co= nfidence in it without understanding its limitations. > > while not ACov.IsCovered loop > (Reg1, Reg2) :=3D Acov.RandCovPoint; -- randomize uncovered bins > DoAluOp(Trec, Reg1, Reg2); -- do transaction > Acov.Icover((Reg1, Reg2)); -- mark it covered > end loop; > >=20 >=20 > In the above snippet the real transaction is DoAluOp, which is supposed= =20 > to do something with registers Reg[12], but we mark the bin as covered=20 > even though there's no real feedback from the transaction result. The example in the presentation is somewhat simplified. You have valid abo= ut concerns whether the input vectors are really applied or not. More form= ally you could (and perhaps should) have a input monitor that watches the i= nterface and collects the functional coverage - hard to show that on one sl= ide :). It would definitely reduce the risk. It is in some ways extra wor= k and the value it delivers will depend on the situation. =20 The value of a separate monitor will depend some on complexity. If I issue= a DoAluOp transaction, can I validate it in such a way that I am confident= that it always does what the transaction implies? For the ALU or even a U= ART transmitter - these are fairly simple and I should be able to validate = the testbench model well enough. =20 The value of a separate monitor will also depend on the response checking m= ethdology. For example, as KJ suggested, sometimes while doing result chec= king we also validate that the correct stimulus was applied. For example, = with UART or Ethernet traffic, I send a transaction, I put the expected val= ue into the scoreboard, and then when the RX side receives the transaction = and checks it via the scoreboard. In this case, the monitor is not adding = significant value since I am validating it on the receive side of the inter= face anyway. =20 OTOH, for the ALU logic, my testbench may simultaneously apply the inputs t= o the DUT and a behavioral math model. In this case, the response checker = is not going to me anything about what inputs were applied. However, in th= is case, DoAluOp may almost be trivial to write. If I were doing a safety critical design, I would require a separate monito= r process or model all of the time, just to add to the confidence level of = the testing. =20 > [1] I hope Jim does not get upset for having used a snippet from his=20 > presentation :-/ Certainly permitted. Especially when it promotes good discussion. Cheers, Jim From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.236.123.68 with SMTP id u44mr15763371yhh.19.1405595925588; Thu, 17 Jul 2014 04:18:45 -0700 (PDT) X-Received: by 10.182.91.37 with SMTP id cb5mr275796obb.0.1405595925479; Thu, 17 Jul 2014 04:18:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no1200251qaq.0!news-out.google.com!bp9ni940igb.0!nntp.google.com!h18no1609355igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Jul 2014 04:18:45 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Chris Higgs Injection-Date: Thu, 17 Jul 2014 11:18:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2246 X-Received-Body-CRC: 1857038375 Xref: news.eternal-september.org comp.lang.vhdl:7646 On Tuesday, July 15, 2014 7:15:09 AM UTC+1, alb wrote: > I found for instance that python is extremely powerful at producing > relatively accurate models with very small efforts. The issue is how to > embed a python model into a vhdl based testbench? I've recently heard > about 'cocotb', maybe I should give it a try, but I've read it has > problems with Modelsim/Questa, which is the simulator we are using. The problem with Modelsim/Questa is that Mentor have yet to implement the full VHDL-2008 standard, specifically the VHPI C API, which Cocotb uses to communicate with VHDL simulations. If you have a mixed-language simulator license you can wrap the toplevel in Verilog wrapper, allowing Cocotb to use VPI to access the simulator. The only other alternative is implementing an FLI layer for Cocotb, which due to the rather limited functionality offered by FLI is non-trivial. You could also open a ticket with Mentor to demonstrate that there is demand for VHPI. Thanks, Chris From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed!lightspeed.eweka.nl!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx24.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> In-Reply-To: <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140717-0, 17/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 44 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405602128 86.29.12.221 (Thu, 17 Jul 2014 13:02:08 UTC) NNTP-Posting-Date: Thu, 17 Jul 2014 13:02:08 UTC Organization: virginmedia.com Date: Thu, 17 Jul 2014 14:02:07 +0100 X-Received-Body-CRC: 3051967956 X-Received-Bytes: 3196 Xref: news.eternal-september.org comp.lang.vhdl:7647 On 17/07/2014 12:18, Chris Higgs wrote: > On Tuesday, July 15, 2014 7:15:09 AM UTC+1, alb wrote: >> I found for instance that python is extremely powerful at producing >> relatively accurate models with very small efforts. The issue is how to >> embed a python model into a vhdl based testbench? I've recently heard >> about 'cocotb', maybe I should give it a try, but I've read it has >> problems with Modelsim/Questa, which is the simulator we are using. > > The problem with Modelsim/Questa is that Mentor have yet to implement the full VHDL-2008 standard, specifically the VHPI C API, which Cocotb uses to communicate with VHDL simulations. > > If you have a mixed-language simulator license you can wrap the toplevel in Verilog wrapper, allowing Cocotb to use VPI to access the simulator. > > The only other alternative is implementing an FLI layer for Cocotb, which due to the rather limited functionality offered by FLI is non-trivial. FLI has "rather limited functionality", hum? what do you base that on? IMHO the FLI give you more functionality than you can shake a stick at. As per Aldec's presentation last week nobody is willing to pay Potential Ventures to port the code to the FLI, this is purely a financial issue and definitely not a technical one. During the Q&A session they mentioned that the FLI didn't have the right functionality to create processes in memory and creates signals to trigger on them, this is basic(core) FLI stuff! // Get pointer to port signal ip->signala = mti_FindPort(ports, "signala"); // Create a process in memory proc = mti_CreateProcess("myprocess", eval_int, ip); // Create sensitivity mti_Sensitize(proc, ip->signala, MTI_EVENT); Regards, Hans. www.ht-lab.com > > You could also open a ticket with Mentor to demonstrate that there is demand for VHPI. > > Thanks, > > Chris > From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.236.62.165 with SMTP id y25mr16748146yhc.26.1405618614973; Thu, 17 Jul 2014 10:36:54 -0700 (PDT) X-Received: by 10.182.104.226 with SMTP id gh2mr21982obb.37.1405618614858; Thu, 17 Jul 2014 10:36:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no1182383qac.1!news-out.google.com!bp9ni941igb.0!nntp.google.com!h18no3186620igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Jul 2014 10:36:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.0.40.221; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 82.0.40.221 References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> Subject: Re: scoreboards, checkers and golden models From: Chris Higgs Injection-Date: Thu, 17 Jul 2014 17:36:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3655 X-Received-Body-CRC: 2969806915 Xref: news.eternal-september.org comp.lang.vhdl:7648 On Thursday, July 17, 2014 2:02:07 PM UTC+1, HT-Lab wrote: > FLI has "rather limited functionality", hum? what do you base that on? > IMHO the FLI give you more functionality than you can shake a stick at. It's likely that FLI provides all the required functionality, it's just more awkward to use than VPI or VHPI. Creating and tracking a process in order to generate a callback is one example of the inconvenience, although that in itself is minor. However if you look at the GPI layer we also need to create callbacks for various phases in the simulation scheduler loop. While with FLI it's possible to set a process priority referring to the scheduler phase, it's still not obvious how you might simply register a callback for entering a given phase, since you'd have to sensitise a process to *something*. Ensuring that Cocotb interacts correctly with the simulation scheduling loop was a major challenge and it doesn't look like FLI makes this any easier. > As per Aldec's presentation last week nobody is willing to pay Potential > Ventures to port the code to the FLI, this is purely a financial issue > and definitely not a technical one. During the Q&A session they > mentioned that the FLI didn't have the right functionality to create > processes in memory and creates signals to trigger on them, this is > basic(core) FLI stuff! I'm glad you listened to the presentation. I have to take issue with this statement though as this is actually the opposite of what I said. I appreciate that the sound quality of the recording is not great but if you listen from 41:55 you'll hear the following: > I believe it would be possible to create processes using FLI and trigger > them on signals, which is effectively the functionality we need. But you're correct that it's more a question of incentive - it's very likely that whatever technical issues arise are solvable. It's still a non-trivial task. The most biggest obstacle is that it's not possible to gain access to an FLI simulator without paying Mentor actual cash in not insignificant amounts. If somebody would like to contribute a license to enable us to develop an FLI interface I'm sure it would happen... or better yet if you have the skills and access to FLI contribute some code! Thanks, Chris From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!rt.uk.eu.org!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx21.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: scoreboards, checkers and golden models References: <957db02e-242e-41ce-9b1f-13fddd6e62b8@googlegroups.com> <7defa5a5-3ec6-4881-8fb8-725682690598@googlegroups.com> <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> In-Reply-To: <3ba0ac73-564a-44c4-b7a6-893ea92d665d@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140718-0, 18/07/2014), Outbound message X-Antivirus-Status: Clean Lines: 95 Message-ID: NNTP-Posting-Host: 86.29.12.221 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1405677049 86.29.12.221 (Fri, 18 Jul 2014 09:50:49 UTC) NNTP-Posting-Date: Fri, 18 Jul 2014 09:50:49 UTC Organization: virginmedia.com Date: Fri, 18 Jul 2014 10:50:46 +0100 X-Received-Body-CRC: 2404468501 X-Received-Bytes: 4911 Xref: news.eternal-september.org comp.lang.vhdl:7649 Hi Chris, On 17/07/2014 18:36, Chris Higgs wrote: > On Thursday, July 17, 2014 2:02:07 PM UTC+1, HT-Lab wrote: >> FLI has "rather limited functionality", hum? what do you base that on? >> IMHO the FLI give you more functionality than you can shake a stick at. > > It's likely that FLI provides all the required functionality, it's just > more awkward to use than VPI or VHPI. Its all in the eye of the beholder. > > Creating and tracking a process in order to generate a callback is one > example of the inconvenience, although that in itself is minor. However > if you look at the GPI layer we also need to create callbacks for various > phases in the simulation scheduler loop. While with FLI it's possible to > set a process priority referring to the scheduler phase, it's still not > obvious how you might simply register a callback for entering a given > phase, I must admit I didn't check the GPI layer but I would expect the mti_CreateProcessWithPriority function to do the trick (which is the FLI function I assume you are referring to). If you look at the example of this function in the reference manual you will see it includes callbacks for different scheduler regions. >since you'd have to sensitise a process to *something*. I am not sure what you mean, do you need to activate the process other than by sensitivity signals? Perhaps mti_schedulewakeup is what you are after. > > Ensuring that Cocotb interacts correctly with the simulation scheduling > loop was a major challenge and it doesn't look like FLI makes this any > easier. > > >> As per Aldec's presentation last week nobody is willing to pay Potential >> Ventures to port the code to the FLI, this is purely a financial issue >> and definitely not a technical one. During the Q&A session they >> mentioned that the FLI didn't have the right functionality to create >> processes in memory and creates signals to trigger on them, this is >> basic(core) FLI stuff! > > I'm glad you listened to the presentation. I have to take issue with this > statement though as this is actually the opposite of what I said. > > I appreciate that the sound quality of the recording is not great but if you > listen from 41:55 you'll hear the following: > >> I believe it would be possible to create processes using FLI and trigger >> them on signals, which is effectively the functionality we need. I downloaded the recording and yes you are correct, my memory is not what it used to be. > > But you're correct that it's more a question of incentive - it's very likely > that whatever technical issues arise are solvable. It's still a non-trivial > task. Yes, I can imagine this is not an easy task. However, given the popularity of VHDL and Modelsim I assume this is high on your todo list. > > The most biggest obstacle is that it's not possible to gain access to > an FLI simulator without paying Mentor actual cash in not insignificant > amounts. Yes Modelsim (DE) is not particular low-cost, however, as with most large corporations it is "just" a question of finding the right person. If somebody would like to contribute a license to enable us to > develop an FLI interface I'm sure it would happen... or better yet if you > have the skills and access to FLI contribute some code! Looks like an interesting challenge, unfortunately my brain is already overloaded with to many languages and there is no more room not even for a powerful language like Python. Good luck, Regards, Hans. www.ht-lab.com > > Thanks, > > Chris > From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Martin Trummer Newsgroups: comp.lang.vhdl Subject: Optimize VHDL snippet for area Date: Thu, 24 Jul 2014 12:15:38 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: mx05.eternal-september.org; posting-host="4b81f6907e2ae697561d06650f07d4c6"; logging-data="17293"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX194enfzViRQanDg3fmoJsn0" User-Agent: Unison/2.1.9 Cancel-Lock: sha1:x5DDx2zCtULl6G/dWeMFxyAzWFU= Xref: news.eternal-september.org comp.lang.vhdl:7650 Hi, Having following VHDL snippet. This masks put bits from an input at a certain position if mask_ctrl > 0 then for i in 0 to DWITH-1 loop if i < mask_ctrl then next_data(i) <= data(i); mask_data(i) <= alu_out(i); else next_data(i) <= '0'; mask_data(i) <= '0'; end if; end loop; end if; next_data is an input for a FF, mask_data is a combinatorical output. Are possibilities to optimize this behavior with respect to chip area? Thanks! Best regards M. T. From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 24 Jul 2014 14:52:48 -0400 Organization: Alacron, Inc. Lines: 40 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Jul 2014 18:53:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="13215"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/StqS26pWmV4ZWy6J+Lr7PP0z2EJrO4eY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:13wCRbTKVNlPNZbOduPJYRqEm34= Xref: news.eternal-september.org comp.lang.vhdl:7651 Martin Trummer wrote: > Hi, > > Having following VHDL snippet. This masks put bits from an input at a > certain position > > if mask_ctrl > 0 then > for i in 0 to DWITH-1 loop > if i < mask_ctrl then > next_data(i) <= data(i); > mask_data(i) <= alu_out(i); > else > next_data(i) <= '0'; > mask_data(i) <= '0'; > end if; > end loop; > end if; > > next_data is an input for a FF, mask_data is a combinatorical output. > Are possibilities to optimize this behavior with respect to chip area? > > Thanks! > > Best regards > M. T. > You say "mask_data is a combinatorical output," but I don't see any assignment to it if mask_ctrl is not > 0. That could create a latche unless you have a default assignment outside the code you posted. As for optimization, I would think a good synthesizer could give you a pretty optimal result. However you also didn't mention what architecture you're trying to build this in (FPGA, ASIC...) so there may be something you could do to help the optimization. However it's likely that even if you changed the code, for example by not using a loop, that the synthesis output wouldn't change. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.50.85.42 with SMTP id e10mr10464478igz.0.1406232200561; Thu, 24 Jul 2014 13:03:20 -0700 (PDT) X-Received: by 10.182.191.39 with SMTP id gv7mr90555obc.10.1406232200350; Thu, 24 Jul 2014 13:03:20 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no4021917igc.0!news-out.google.com!eg1ni0igc.0!nntp.google.com!h18no4021914igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Jul 2014 13:03:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45ec9210-49d0-4182-89cd-639aa9b3bf6a@googlegroups.com> Subject: Re: OSVVM vs UVM/OVM w.r.t. processor resources From: Andy Injection-Date: Thu, 24 Jul 2014 20:03:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7652 Most of the simulation performance difference between vhdl and verilog/SV is due to the data types used by VHDL (SLV, etc.), how much memory they consume, etc. But most good testbenches minimize the use of slv/unsigned/etc. and use variables, integers and booleans as much as possible. That narrows the performance gap between VHDL and Verilog/SV tremendously. Thankfully, OSVVM supports integer coverage and randomization natively, so it should be more comparable to SV/UVM (especially if the DUT is in VHDL), and even faster if intelligent coverage is used. Alas, I have no benchmarking to back any of this up. YMMV, Closed Course Professional Driver, do not try this at home, void where prohibited by law, etc. Andy From newsfish@newsfish Tue Dec 29 16:43:29 2015 X-Received: by 10.236.129.2 with SMTP id g2mr4875506yhi.2.1406233002256; Thu, 24 Jul 2014 13:16:42 -0700 (PDT) X-Received: by 10.182.2.107 with SMTP id 11mr3849obt.41.1406233001980; Thu, 24 Jul 2014 13:16:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no2389091qaq.0!news-out.google.com!eg1ni2igc.0!nntp.google.com!h18no6966541igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Jul 2014 13:16:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <254cbbd9-c3fe-4f72-9321-afd9ddda5fe4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Andy Injection-Date: Thu, 24 Jul 2014 20:16:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1969 X-Received-Body-CRC: 2934864748 Xref: news.eternal-september.org comp.lang.vhdl:7653 Yes, that's it in a nutshell (wrapper architectures). Doing anything except black box testing on the gate level model generally t= akes lots of work, and is not often portable between gate level and RTL ver= ification. What wrapper architectures (and other similar techniques using configuratio= ns) are best at is observing internal interfaces and making sure they are o= perating per spec, sometimes including inserting errors to see how the rest= of the system responds. This often has more to do with ensuring a robust, = maintainable implementation rather than just a functional implementation. Andy From newsfish@newsfish Tue Dec 29 16:43:29 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Marc Jenkins Newsgroups: comp.lang.vhdl Subject: Wired Or in VHDL Date: Fri, 25 Jul 2014 11:58:07 +0200 Organization: A noiseless patient Spider Lines: 10 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: mx05.eternal-september.org; posting-host="4b81f6907e2ae697561d06650f07d4c6"; logging-data="28758"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19EyHPbYRkWqjSAclsBiCe4" User-Agent: Unison/2.1.9 Cancel-Lock: sha1:vo/oFa4DW+jm7Ov+1LEvbPOgT9U= Xref: news.eternal-september.org comp.lang.vhdl:7654 Hello folks, Verilog supports the net type "wor" to implement a wired or logic. Is something similar possible in VHDL? Target plattform is an ASIC. Thanks, Marc From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.50.80.111 with SMTP id q15mr2351191igx.0.1406298802103; Fri, 25 Jul 2014 07:33:22 -0700 (PDT) X-Received: by 10.140.101.120 with SMTP id t111mr5084qge.39.1406298802031; Fri, 25 Jul 2014 07:33:22 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no7407976igc.0!news-out.google.com!j6ni12934qas.0!nntp.google.com!v10no2465439qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Jul 2014 07:33:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: KJ Injection-Date: Fri, 25 Jul 2014 14:33:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7655 On Friday, July 25, 2014 5:58:07 AM UTC-4, Marc Jenkins wrote: > Hello folks, > Verilog supports the net type "wor" to implement a wired or logic. > Is something similar possible in VHDL? > > Target plattform is an ASIC. Wired-or simply means that there are multiple drivers on a net. In VHDL land, the std_logic that nearly everybody uses for every signal definition can have multiple drivers. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 13:42:47 -0400 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 17:43:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="31530"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tVrtEJzebBxyRpoN8TPVR" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:r85bmNn1p+AEZZ2UeM7W60gS1+I= Xref: news.eternal-september.org comp.lang.vhdl:7656 On 7/25/2014 5:58 AM, Marc Jenkins wrote: > Hello folks, > > Verilog supports the net type "wor" to implement a wired or logic. > Is something similar possible in VHDL? > > Target plattform is an ASIC. The question is why would you want that? To use a wired or you would need to have open collector (or open drain) outputs with a pull up resistor. Compared to just adding an OR gate this is a very slow method or very power hungry, take your pick. Do you really plan to use a wired or? Or do you expect this to be replaced with a real gate and are using it as shorthand? -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 18:41:21 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 33 Message-ID: References: Injection-Date: Fri, 25 Jul 2014 18:41:21 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="17814"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ka7vUjrZcSTj4POku33w9" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:1nNpglZaN1zZxhEimUxNg1DMAqE= Xref: news.eternal-september.org comp.lang.vhdl:7657 In article , rickman wrote: >On 7/25/2014 5:58 AM, Marc Jenkins wrote: >> Hello folks, >> >> Verilog supports the net type "wor" to implement a wired or logic. >> Is something similar possible in VHDL? >> >> Target plattform is an ASIC. > >The question is why would you want that? To use a wired or you would >need to have open collector (or open drain) outputs with a pull up >resistor. Compared to just adding an OR gate this is a very slow method >or very power hungry, take your pick. > >Do you really plan to use a wired or? Or do you expect this to be >replaced with a real gate and are using it as shorthand? Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net to a logical 'or' gate. It's perfectly synthesizable, and quite useful. We've been using this construct for over 10 years on our Xilinx FPGAs on our CPU register bus. The returned read data (for when the CPU is issuing a read) is collected on a "wor" bus. All the slaves drive 0 when NOT addressed. When addressed, and issued a read, the one slave drives the actual read data on the bus. Works a charm, and greatly simplifies our code. Regards, Mark From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 16:30:18 -0400 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 20:30:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6549"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/H5Q63tVdsdtyTjOuhB9tp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:JTBTHEPTrQg7ctgi/uIL1mNDQP4= Xref: news.eternal-september.org comp.lang.vhdl:7658 On 7/25/2014 2:41 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>> Hello folks, >>> >>> Verilog supports the net type "wor" to implement a wired or logic. >>> Is something similar possible in VHDL? >>> >>> Target plattform is an ASIC. >> >> The question is why would you want that? To use a wired or you would >> need to have open collector (or open drain) outputs with a pull up >> resistor. Compared to just adding an OR gate this is a very slow method >> or very power hungry, take your pick. >> >> Do you really plan to use a wired or? Or do you expect this to be >> replaced with a real gate and are using it as shorthand? > > Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net > to a logical 'or' gate. It's perfectly synthesizable, and quite useful. > > We've been using this construct for over 10 years on our Xilinx FPGAs > on our CPU register bus. The returned read data (for when the CPU > is issuing a read) is collected on a "wor" bus. All the slaves > drive 0 when NOT addressed. When addressed, and issued a read, the > one slave drives the actual read data on the bus. > > Works a charm, and greatly simplifies our code. Synthesizable yes, useful...? -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 21:56:58 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 45 Message-ID: References: Injection-Date: Fri, 25 Jul 2014 21:56:58 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="6504"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX191ctctT6G5DQFpb4Ki/eQ5" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:xoEjeIHKwGoAlU0QPMYd14YN2I4= Xref: news.eternal-september.org comp.lang.vhdl:7659 In article , rickman wrote: >On 7/25/2014 2:41 PM, Mark Curry wrote: >> In article , rickman wrote: >>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>> Hello folks, >>>> >>>> Verilog supports the net type "wor" to implement a wired or logic. >>>> Is something similar possible in VHDL? >>>> >>>> Target plattform is an ASIC. >>> >>> The question is why would you want that? To use a wired or you would >>> need to have open collector (or open drain) outputs with a pull up >>> resistor. Compared to just adding an OR gate this is a very slow method >>> or very power hungry, take your pick. >>> >>> Do you really plan to use a wired or? Or do you expect this to be >>> replaced with a real gate and are using it as shorthand? >> >> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >> >> We've been using this construct for over 10 years on our Xilinx FPGAs >> on our CPU register bus. The returned read data (for when the CPU >> is issuing a read) is collected on a "wor" bus. All the slaves >> drive 0 when NOT addressed. When addressed, and issued a read, the >> one slave drives the actual read data on the bus. >> >> Works a charm, and greatly simplifies our code. > >Synthesizable yes, useful...? Very useful. We've got a much cleaner, reusable structure setup for register configuration. There's nothing to do to add/subtract (sometimes via the setting of a parameter) more registers on the bus. It just works. It's a bit hard to describe in a small example. But we've got significant code size reduction using this structure. Some were uncomfortable at first with the "multi-driver" implications, or collision problems. But we've found that neither are a problem at all. Regards, Mark From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 19:04:23 -0400 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Jul 2014 23:04:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="378"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18UUoAd0+mBMzg3AB5IFExs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:kFsGmO4vLLUxVF5+zqLzhMnq5jU= Xref: news.eternal-september.org comp.lang.vhdl:7660 On 7/25/2014 5:56 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 2:41 PM, Mark Curry wrote: >>> In article , rickman wrote: >>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>> Hello folks, >>>>> >>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>> Is something similar possible in VHDL? >>>>> >>>>> Target plattform is an ASIC. >>>> >>>> The question is why would you want that? To use a wired or you would >>>> need to have open collector (or open drain) outputs with a pull up >>>> resistor. Compared to just adding an OR gate this is a very slow method >>>> or very power hungry, take your pick. >>>> >>>> Do you really plan to use a wired or? Or do you expect this to be >>>> replaced with a real gate and are using it as shorthand? >>> >>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>> >>> We've been using this construct for over 10 years on our Xilinx FPGAs >>> on our CPU register bus. The returned read data (for when the CPU >>> is issuing a read) is collected on a "wor" bus. All the slaves >>> drive 0 when NOT addressed. When addressed, and issued a read, the >>> one slave drives the actual read data on the bus. >>> >>> Works a charm, and greatly simplifies our code. >> >> Synthesizable yes, useful...? > > Very useful. We've got a much cleaner, reusable structure setup for > register configuration. There's nothing to do to add/subtract (sometimes > via the setting of a parameter) more registers on the bus. It just works. > > It's a bit hard to describe in a small example. But we've got significant > code size reduction using this structure. Some were uncomfortable at first > with the "multi-driver" implications, or collision problems. But we've found > that neither are a problem at all. No need for examples. I understand perfectly what you are describing. But this is a construct that is in some respects the equivalent of a global variable and creates issues for verifying code depending on your methods. If it works for you then great. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Sat, 26 Jul 2014 00:06:23 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 67 Message-ID: References: Injection-Date: Sat, 26 Jul 2014 00:06:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="18744"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/opioylKF+vDkBg2s/l4Sz" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:45I5dPeOO4kQQpNAkt0Jf+NhgXY= Xref: news.eternal-september.org comp.lang.vhdl:7661 In article , rickman wrote: >On 7/25/2014 5:56 PM, Mark Curry wrote: >> In article , rickman wrote: >>> On 7/25/2014 2:41 PM, Mark Curry wrote: >>>> In article , rickman wrote: >>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>>> Hello folks, >>>>>> >>>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>>> Is something similar possible in VHDL? >>>>>> >>>>>> Target plattform is an ASIC. >>>>> >>>>> The question is why would you want that? To use a wired or you would >>>>> need to have open collector (or open drain) outputs with a pull up >>>>> resistor. Compared to just adding an OR gate this is a very slow method >>>>> or very power hungry, take your pick. >>>>> >>>>> Do you really plan to use a wired or? Or do you expect this to be >>>>> replaced with a real gate and are using it as shorthand? >>>> >>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>>> >>>> We've been using this construct for over 10 years on our Xilinx FPGAs >>>> on our CPU register bus. The returned read data (for when the CPU >>>> is issuing a read) is collected on a "wor" bus. All the slaves >>>> drive 0 when NOT addressed. When addressed, and issued a read, the >>>> one slave drives the actual read data on the bus. >>>> >>>> Works a charm, and greatly simplifies our code. >>> >>> Synthesizable yes, useful...? >> >> Very useful. We've got a much cleaner, reusable structure setup for >> register configuration. There's nothing to do to add/subtract (sometimes >> via the setting of a parameter) more registers on the bus. It just works. >> >> It's a bit hard to describe in a small example. But we've got significant >> code size reduction using this structure. Some were uncomfortable at first >> with the "multi-driver" implications, or collision problems. But we've found >> that neither are a problem at all. > >No need for examples. I understand perfectly what you are describing. >But this is a construct that is in some respects the equivalent of a >global variable and creates issues for verifying code depending on your >methods. If it works for you then great. :) Rickman, I was among those that cast a suspicious eye on the construct when I first saw it. But it really works fine and is NOT comparable to a global variable at all IMHO. I think of it as the same mux as others do by hand to mux the readdata back - just broken up. i.e. think of the readmux as a sum of products: y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... Where we force the slave modules themselves to do the "AND" masking. Then the 'OR' is taken care of automatically with the 'wor' multi-driver. There's really no verification issues that we have with using this. It's very straightforward. --Mark From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 25 Jul 2014 22:15:54 -0400 Organization: A noiseless patient Spider Lines: 97 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Jul 2014 02:16:06 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25268"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ser5+mHtbw6lSsLdyt1/L" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:bnqDTPLZZ7urr9S2C+Cs9PB5DWA= Xref: news.eternal-september.org comp.lang.vhdl:7662 On 7/25/2014 8:06 PM, Mark Curry wrote: > In article , rickman wrote: >> On 7/25/2014 5:56 PM, Mark Curry wrote: >>> In article , rickman wrote: >>>> On 7/25/2014 2:41 PM, Mark Curry wrote: >>>>> In article , rickman wrote: >>>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: >>>>>>> Hello folks, >>>>>>> >>>>>>> Verilog supports the net type "wor" to implement a wired or logic. >>>>>>> Is something similar possible in VHDL? >>>>>>> >>>>>>> Target plattform is an ASIC. >>>>>> >>>>>> The question is why would you want that? To use a wired or you would >>>>>> need to have open collector (or open drain) outputs with a pull up >>>>>> resistor. Compared to just adding an OR gate this is a very slow method >>>>>> or very power hungry, take your pick. >>>>>> >>>>>> Do you really plan to use a wired or? Or do you expect this to be >>>>>> replaced with a real gate and are using it as shorthand? >>>>> >>>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net >>>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. >>>>> >>>>> We've been using this construct for over 10 years on our Xilinx FPGAs >>>>> on our CPU register bus. The returned read data (for when the CPU >>>>> is issuing a read) is collected on a "wor" bus. All the slaves >>>>> drive 0 when NOT addressed. When addressed, and issued a read, the >>>>> one slave drives the actual read data on the bus. >>>>> >>>>> Works a charm, and greatly simplifies our code. >>>> >>>> Synthesizable yes, useful...? >>> >>> Very useful. We've got a much cleaner, reusable structure setup for >>> register configuration. There's nothing to do to add/subtract (sometimes >>> via the setting of a parameter) more registers on the bus. It just works. >>> >>> It's a bit hard to describe in a small example. But we've got significant >>> code size reduction using this structure. Some were uncomfortable at first >>> with the "multi-driver" implications, or collision problems. But we've found >>> that neither are a problem at all. >> >> No need for examples. I understand perfectly what you are describing. >> But this is a construct that is in some respects the equivalent of a >> global variable and creates issues for verifying code depending on your >> methods. If it works for you then great. :) > > Rickman, > > I was among those that cast a suspicious eye on the construct when I > first saw it. But it really works fine and is NOT comparable to > a global variable at all IMHO. > > I think of it as the same mux as others do by hand to > mux the readdata back - just broken up. i.e. think > of the readmux as a sum of products: > y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... > > Where we force the slave modules themselves to do the "AND" masking. > Then the 'OR' is taken care of automatically with the 'wor' multi-driver. > > There's really no verification issues that we have with using this. > It's very straightforward. I might not understand this correctly since I am much more the VHDL programmer (where the wire or is seldom used, in fact, can that be done?) than a Verilog programmer... So there is one net with multiple drivers. When *any* of the drivers outputs a 1 the net is a 1, hence the wire or name. So if you have a 1 on the net when you aren't expecting a 1, how do you identify the driver unless you look at the inputs to all the drivers in all the different modules? To me that is a problem and is one of the reasons why buses like this are a PITA to debug in real hardware. This is commonly referred to as "hanging" the bus. By using an explicit mux the only signal that can drive the output of the mux is the signal that is selected at that moment. Look at the select lines, look at the corresponding input and continue to trace back from there. This is not an insurmountable problem. As I said this is commonly used in real hardware, just not inside chips very often. You say it makes the code easier to read, I think it splits the logic for a simple mux across multiple modules and makes it harder to debug. Consider a software technique of encapsulating decisions and functions. The wire or is the opposite of that since the mux logic is spread across modules. Different horses for different courses. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.10.66 with SMTP id p2mr9742545icp.28.1406353679611; Fri, 25 Jul 2014 22:47:59 -0700 (PDT) X-Received: by 10.50.50.205 with SMTP id e13mr234118igo.17.1406353679524; Fri, 25 Jul 2014 22:47:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no4548340igc.0!news-out.google.com!px9ni0igc.0!nntp.google.com!h18no7789787igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Jul 2014 22:47:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e816e99-8bce-40b2-99e8-bacfed6b5e47@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Dio Gratia Injection-Date: Sat, 26 Jul 2014 05:47:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7663 On Monday, July 14, 2014 6:31:46 PM UTC+12, alb wrote: > > I would rather think they are two different language constructs, each > with its own characteristics. You can infer a register with a concurrent > assignment, but not a latch. Which one you use is a matter of style, as > long as it matches your desired behavior. >From IEEE Std 1076.6-2004 6.2.1.2 Level-sensitive storage from concurrent signal assignment A level-sensitive storage element shall be modeled for a signal that is assigned in a concurrent signal assignment statement that can be mapped to a process that adheres to the rules in 6.2.1.1. Example 1: LEV_SENS_7: Q <= '0' when RESET ='1' else -- This is identical D when ENABLE; -- to LEV_SENS_1 in 6.2.1.1, Example 2: LEV_SENS_8: With ENABLE select Q <= D when '1', Q when others; -- Identical to LEV_SENS_2 in 6.2.1.1, -- and models combinational logic. Example 3: LEV_SENS_9: with ENABLE select Q <= D when '1', unaffected when others; (There's more). From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.43.85.201 with SMTP id ap9mr6646536icc.11.1406742465013; Wed, 30 Jul 2014 10:47:45 -0700 (PDT) X-Received: by 10.140.93.181 with SMTP id d50mr71366qge.0.1406742464883; Wed, 30 Jul 2014 10:47:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no6544330igc.0!news-out.google.com!px9ni176igc.0!nntp.google.com!h18no10628324igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 10:47:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Subject: Could you explain "BUT NOT signal_declaration" in this tutorial? From: fl Injection-Date: Wed, 30 Jul 2014 17:47:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7664 Hi, I learn concurrent clause from this link: http://www.csee.umbc.edu/portal/help/VHDL/concurrent.html I do not understand "BUT NOT signal_declaration", see below please. Could you explain what it intends to say? Thanks, process_declarative_items are any of: subprogram declaration subprogram body type declaration subtype declaration constant, object declaration variable, object declaration file, object declaration alias declaration attribute declaration attribute specification use clause group template declaration group declaration BUT NOT signal_declaration, all signals must be declared outside the process. sig1 <= sig2 and sig3; -- considered here as a sequential statement -- sig1 is set outside the process upon exit or wait From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.119.82 with SMTP id a18mr7074737icr.19.1406748445801; Wed, 30 Jul 2014 12:27:25 -0700 (PDT) X-Received: by 10.182.108.165 with SMTP id hl5mr23016obb.27.1406748445613; Wed, 30 Jul 2014 12:27:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no6607370igc.0!news-out.google.com!px9ni176igc.0!nntp.google.com!h18no10705995igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 12:27:24 -0700 (PDT) In-Reply-To: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.150; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.150 References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1cecf7c0-7e73-46d0-aa9f-46c034f727dc@googlegroups.com> Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? From: Jim Lewis Injection-Date: Wed, 30 Jul 2014 19:27:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7665 It simply notes that signal declarations are not allowed in a process. Instead for most applications you declare them in the architecture. >From the perspective of a process with a sensitivity list that is intended to create combinatorial logic, this makes sense. However, from the perspective of a process with a wait statement (used frequently in testbenches), perhaps not. From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx02.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? Newsgroups: comp.lang.vhdl References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 17 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1406749346 62.49.20.82 (Wed, 30 Jul 2014 19:42:26 UTC) NNTP-Posting-Date: Wed, 30 Jul 2014 19:42:26 UTC Date: Wed, 30 Jul 2014 19:42:26 GMT X-Received-Body-CRC: 1375691008 X-Received-Bytes: 1259 Xref: news.eternal-september.org comp.lang.vhdl:7666 On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: > Hi, > > I learn concurrent clause from this link: > > http://www.csee.umbc.edu/portal/help/VHDL/concurrent.html > > I do not understand "BUT NOT signal_declaration", see below please. > Could you explain what it intends to say? > Simply put, signals are the means of communicating between processes. So declaring a signal within a process, visible only within that process, doesn't make a lot of sense. - Brian From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.68.137.99 with SMTP id qh3mr2724332pbb.2.1406751837175; Wed, 30 Jul 2014 13:23:57 -0700 (PDT) X-Received: by 10.140.100.182 with SMTP id s51mr25473qge.29.1406751837118; Wed, 30 Jul 2014 13:23:57 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no10741146igc.0!news-out.google.com!b3ni3606qac.1!nntp.google.com!j15no3492446qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Jul 2014 13:23:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? From: fl Injection-Date: Wed, 30 Jul 2014 20:23:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7667 On Wednesday, July 30, 2014 3:42:26 PM UTC-4, Brian Drummond wrote: > On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: > > I do not understand "BUT NOT signal_declaration", see below please. > > Could you explain what it intends to say? > > > Simply put, signals are the means of communicating between processes. So > declaring a signal within a process, visible only within that process, > doesn't make a lot of sense. > > - Brian Thanks. I am clear about the signal declaration. For "BUT NOT", it is a typo for "BUT NOTE"? Or something else? From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Could you explain "BUT NOT signal_declaration" in this tutorial? Date: Wed, 30 Jul 2014 21:41:13 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <40b73493-1be1-4a96-b145-a6d510f208b9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 01:41:31 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="27666"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19bE4cgWT9A2zeWIYnXOpdx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:UCD3dsW341zAyS634UHJjSbKKn8= Xref: news.eternal-september.org comp.lang.vhdl:7668 On 7/30/2014 4:23 PM, fl wrote: > On Wednesday, July 30, 2014 3:42:26 PM UTC-4, Brian Drummond wrote: >> On Wed, 30 Jul 2014 10:47:44 -0700, fl wrote: >>> I do not understand "BUT NOT signal_declaration", see below please. >>> Could you explain what it intends to say? >>> >> Simply put, signals are the means of communicating between processes. So >> declaring a signal within a process, visible only within that process, >> doesn't make a lot of sense. >> >> - Brian > > Thanks. I am clear about the signal declaration. > For "BUT NOT", it is a typo for "BUT NOTE"? Or something else? It is just English, not part of the formal language for VHDL. process_declarative_items may be any of this list, but not a signal_declaration. -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Concurrent assignments vs. assignments inside a process Date: Thu, 31 Jul 2014 15:28:28 +0200 Lines: 42 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit X-Trace: individual.net og3QS8FN70CHeWOD+UDYfAf2o2SC48xZ81HHhhFcm5pT21zTNu Cancel-Lock: sha1:V5fmKBnVSAHWMIjIdFckLuQDghQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.0 In-Reply-To: Xref: news.eternal-september.org comp.lang.vhdl:7669 In case anyone's still interested: This gets even worse in Vivado. Not even driving a std_ulogic from two different places causes an error or warning during synthesis... The best you can do is to receive a critical warning, but only under certain circumstances (as it turns out, it makes a difference if one of the drivers drives a constant value or not, for whatever reason...). I've reported it to Xilinx, but as of now they don't believe me that this is a problem: http://tinyurl.com/lkzgsgj I'll be on vacation for awhile now, maybe the problem will have magically disappeared when I'm back... Am 13.07.2014 um 11:13 schrieb Sean Durkin: > Hi *, > > I'm sure one of you can clear this up: > > During debugging recently I discovered a bug in a module of mine: I had > assigned a signal inside of a clocked process, but had also assigned it > elsewhere concurrently (before writing the process, I had assigned it a > different signal). > > Now, the result in simulation is as expected: the concurrent assignment > usually "wins", with occasional 'X' in simulation. > But what is unexpected to me is that the synthesis tools did not > complain about this. I would have expected a "multiple drivers" > error/warning or something similar. Why isn't there any? > > I always thought that a concurrent signal assignment is more or less > just a less verbose version of a process with the right-hand-side > signals in the sensitivity list. So basically what I had was assignments > to the same signal from two different processes (one sequential one > combinatorial), which should cause multiple drivers warnings. What would > the hardware really do in that case, anyway? > > Sean > From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.188.84 with SMTP id cz20mr14361505icb.1.1406831063925; Thu, 31 Jul 2014 11:24:23 -0700 (PDT) X-Received: by 10.50.138.69 with SMTP id qo5mr8718igb.7.1406831063799; Thu, 31 Jul 2014 11:24:23 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no7213366igc.0!news-out.google.com!px9ni1igc.0!nntp.google.com!h18no7213356igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 11:24:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 18:24:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7670 On Thursday, 31 July 2014 21:28:28 UTC+8, Sean Durkin wrote: > In case anyone's still interested: >=20 >=20 >=20 > This gets even worse in Vivado. Not even driving a std_ulogic from two >=20 > different places causes an error or warning during synthesis... The best >=20 > you can do is to receive a critical warning, but only under certain >=20 > circumstances (as it turns out, it makes a difference if one of the >=20 > drivers drives a constant value or not, for whatever reason...). >=20 >=20 >=20 > I've reported it to Xilinx, but as of now they don't believe me that >=20 > this is a problem: >=20 >=20 >=20 > http://tinyurl.com/lkzgsgj >=20 >=20 >=20 > I'll be on vacation for awhile now, maybe the problem will have >=20 > magically disappeared when I'm back... >=20 I've had a similar problem with Altera before, but in my case it had to do = with Quartus optimising away the signals when they aren't used in the desig= n (e.g. not read by another signal, or not used as an output, etc.). Quartus has the bad habit of optimising away (reducing) multiple drivers to= an unresolved net, BEFORE checking that the net is unresolved and it has m= ultiple drivers (and therefore should give an error). I'm not sure if this = changed for the latest version. For those interested, you can try the follo= wing code and see if Quartus incorrectly optimises away the design without = giving any errors: entity test is port(a0,a1:in std_ulogic; q0:out std_ulogic); end entity test; architecture shouldErrorAndNotOptimise of test is signal q1:std_ulogic; begin q0<=3Da0; -- wire synthesised from a0 to q0. correct behaviour. q1<=3Da1; -- assignment to an internal net. q1<=3Da0; -- multiple assignment to an unresolved net. -- should report error here. =20 --q0<=3Da1; -- if this line is enabled, Quartus correctly=20 -- gives an error on multiple drivers driving q0. end architecture shouldErrorAndNotOptimise; I wrote this from memory, and have not tested this code on the latest Quart= us. But yes, I did have these problems before when using the tool. The reas= on why Quartus errored out for q0 and not q1 was because q0 was "used" - it= was the output of the design, while q1 was an internal signal that got opt= imised away. Anyway, I still perceive this as a bug in Quartus, as the code= is incorrect as per my understanding of the LRM. Quartus should have throw= n me an error, as ModelSim correctly did. Now, to the topic about having multiple drivers to a RESOLVED net. Altera has partial support for resolution functions (which is good), but th= ere are still problems with the feature. Having multiple drivers on a resol= ved net is fine; simulation tools usually resolve to an 'X' (or whatever th= e resolution function resolves to) and this will be correctly displayed in = the simulator. For synthesis tools however, I believe they should give eith= er a Warning or a Critical Warning, but should not give an error. At least = warn us that they are multiple drivers to a resolved signal. Both Altera an= d Xilinx choke at this. For Altera, I think resolved types only work correctly when a custom resolu= tion function is used - when you try to have multiple drivers to a signal o= f a predefined resolved type (such as std_logic / std_logic_vector), you wo= uld, incorrectly, be puked by Quartus with an error. The tool should have i= nvoked the predefined resolution function and automatically resolve the mul= tiple drivers, while also giving us a Critical Warning. Again, I'm not sure= if this behaviour changed for the latest version - last I tried this was a= t least a couple of years back. Anyway, I have supported your claim in Xilinx's forum. For those who really= need this, do rally your support. -dan From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.236.26.206 with SMTP id c54mr39798yha.44.1406832830910; Thu, 31 Jul 2014 11:53:50 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr14475igl.8.1406832830555; Thu, 31 Jul 2014 11:53:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v10no3578058qac.1!news-out.google.com!px9ni1igc.0!nntp.google.com!h18no7231513igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 11:53:49 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 18:53:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 7378 X-Received-Body-CRC: 292099030 Xref: news.eternal-september.org comp.lang.vhdl:7671 On Saturday, 26 July 2014 10:15:54 UTC+8, rickman wrote: > On 7/25/2014 8:06 PM, Mark Curry wrote: > > > In article , rickman wrote: > > >> On 7/25/2014 5:56 PM, Mark Curry wrote: > > >>> In article , rickman wrote: > > >>>> On 7/25/2014 2:41 PM, Mark Curry wrote: > > >>>>> In article , rickman wrote: > > >>>>>> On 7/25/2014 5:58 AM, Marc Jenkins wrote: > > >>>>>>> Hello folks, > > >>>>>>> > > >>>>>>> Verilog supports the net type "wor" to implement a wired or logic. > > >>>>>>> Is something similar possible in VHDL? > > >>>>>>> > > >>>>>>> Target plattform is an ASIC. > > >>>>>> > > >>>>>> The question is why would you want that? To use a wired or you would > > >>>>>> need to have open collector (or open drain) outputs with a pull up > > >>>>>> resistor. Compared to just adding an OR gate this is a very slow method > > >>>>>> or very power hungry, take your pick. > > >>>>>> > > >>>>>> Do you really plan to use a wired or? Or do you expect this to be > > >>>>>> replaced with a real gate and are using it as shorthand? > > >>>>> > > >>>>> Most synthesis tools I'm aware of correctly map multiple drivers on a "wor" net > > >>>>> to a logical 'or' gate. It's perfectly synthesizable, and quite useful. > > >>>>> > > >>>>> We've been using this construct for over 10 years on our Xilinx FPGAs > > >>>>> on our CPU register bus. The returned read data (for when the CPU > > >>>>> is issuing a read) is collected on a "wor" bus. All the slaves > > >>>>> drive 0 when NOT addressed. When addressed, and issued a read, the > > >>>>> one slave drives the actual read data on the bus. > > >>>>> > > >>>>> Works a charm, and greatly simplifies our code. > > >>>> > > >>>> Synthesizable yes, useful...? > > >>> > > >>> Very useful. We've got a much cleaner, reusable structure setup for > > >>> register configuration. There's nothing to do to add/subtract (sometimes > > >>> via the setting of a parameter) more registers on the bus. It just works. > > >>> > > >>> It's a bit hard to describe in a small example. But we've got significant > > >>> code size reduction using this structure. Some were uncomfortable at first > > >>> with the "multi-driver" implications, or collision problems. But we've found > > >>> that neither are a problem at all. > > >> > > >> No need for examples. I understand perfectly what you are describing. > > >> But this is a construct that is in some respects the equivalent of a > > >> global variable and creates issues for verifying code depending on your > > >> methods. If it works for you then great. :) > > > > > > Rickman, > > > > > > I was among those that cast a suspicious eye on the construct when I > > > first saw it. But it really works fine and is NOT comparable to > > > a global variable at all IMHO. > > > > > > I think of it as the same mux as others do by hand to > > > mux the readdata back - just broken up. i.e. think > > > of the readmux as a sum of products: > > > y = ( sel0 & in0 ) | ( sel1 & in1 ) | ( sel2 & in2 ) | ... > > > > > > Where we force the slave modules themselves to do the "AND" masking. > > > Then the 'OR' is taken care of automatically with the 'wor' multi-driver. > > > > > > There's really no verification issues that we have with using this. > > > It's very straightforward. > > > > I might not understand this correctly since I am much more the VHDL > > programmer (where the wire or is seldom used, in fact, can that be > > done?) than a Verilog programmer... So there is one net with multiple > > drivers. When *any* of the drivers outputs a 1 the net is a 1, hence > > the wire or name. > > > > So if you have a 1 on the net when you aren't expecting a 1, how do you > > identify the driver unless you look at the inputs to all the drivers in > > all the different modules? To me that is a problem and is one of the > > reasons why buses like this are a PITA to debug in real hardware. This > > is commonly referred to as "hanging" the bus. > > > > By using an explicit mux the only signal that can drive the output of > > the mux is the signal that is selected at that moment. Look at the > > select lines, look at the corresponding input and continue to trace back > > from there. > > > > This is not an insurmountable problem. As I said this is commonly used > > in real hardware, just not inside chips very often. You say it makes > > the code easier to read, I think it splits the logic for a simple mux > > across multiple modules and makes it harder to debug. > > > > Consider a software technique of encapsulating decisions and functions. > > The wire or is the opposite of that since the mux logic is spread > > across modules. > > > > Different horses for different courses. :) > > > > -- > > > > Rick Haven't tried resolution functions on Xilinx. But from the sound of it, I believe your 'wor' can be easily done with a custom resolution function in VHDL: entity test is port(d0,d1:in std_ulogic; q:out resolved_wor std_ulogic); end entity test; architecture rtl of test is begin q<=d0; q<=d1; end architecture rtl; Not sure if Vivado supports this though. With a bit of hacking, you can get Quartus to support this. Last I know, Quartus chokes on custom resolved ports, so you need to declare an internal signal that uses the custom resolution function: signal s:resolved_wor std_ulogic; and treat s as having multiple drivers from d0 and d1. Then drive the output q from the internal resolved signal s. You can write custom resolution functions to resolve outputs on OR, AND, or anything you want. We prefer not to have special keywords like wor, wand, etc. that clutter our language. :) These things can be easily written as custom functions by the designer. -dan From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.236.78.70 with SMTP id f46mr294697yhe.24.1406840158960; Thu, 31 Jul 2014 13:55:58 -0700 (PDT) X-Received: by 10.50.138.70 with SMTP id qo6mr11217igb.0.1406840158675; Thu, 31 Jul 2014 13:55:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no3665502qaq.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11583727igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 13:55:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 20:55:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7672 On Thursday, 24 July 2014 18:15:38 UTC+8, Martin Trummer wrote: > Hi, >=20 >=20 >=20 > Having following VHDL snippet. This masks put bits from an input at a=20 >=20 > certain position >=20 >=20 >=20 > if mask_ctrl > 0 then >=20 > for i in 0 to DWITH-1 loop >=20 > if i < mask_ctrl then >=20 > next_data(i) <=3D data(i); >=20 > mask_data(i) <=3D alu_out(i); >=20 > else >=20 > next_data(i) <=3D '0'; >=20 > mask_data(i) <=3D '0'; >=20 > end if; >=20 > end loop; >=20 > end if; >=20 >=20 >=20 > next_data is an input for a FF, mask_data is a combinatorical output.=20 >=20 > Are possibilities to optimize this behavior with respect to chip area? >=20 >=20 >=20 > Thanks! >=20 >=20 >=20 > Best regards >=20 > M. T. Guessing from your post on what you're trying to do, why not create a mask = variable and assign it accordingly based upon the condition you want? Your = condition "if i'1', others=3D>'0'); =20 next_data(DWIDTH-1 downto 0)<=3Ddata(DWIDTH-1 downto 0) and mask; mask_data(DWIDTH-1 downto 0)<=3Dalu_out(DWIDTH-1 downto 0) and mask; end process; -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 20:58:39 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 50 Message-ID: References: Injection-Date: Thu, 31 Jul 2014 20:58:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="15168"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+a4H0CE18RbjdWOGhM3+Ia" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:j+eM//VW9AG3Bs6Ft6TkKLXcWcQ= Xref: news.eternal-september.org comp.lang.vhdl:7673 In article , Daniel Kho wrote: > >Haven't tried resolution functions on Xilinx. But from the sound of it, I >believe your 'wor' can be easily done with a custom resolution function in > VHDL: > >entity test is port(d0,d1:in std_ulogic; q:out resolved_wor std_ulogic); >end entity test; > >architecture rtl of test is begin > q<=d0; > q<=d1; >end architecture rtl; > >Not sure if Vivado supports this though. With a bit of hacking, you can get >Quartus to support this. Last I know, Quartus chokes on custom resolved ports, >so you need to declare an internal signal >that uses the custom resolution function: > signal s:resolved_wor std_ulogic; > >and treat s as having multiple drivers from d0 and d1. Then drive the output >q from the internal resolved signal s. > >You can write custom resolution functions to resolve outputs on OR, AND, or >anything you want. We prefer not to have special keywords like wor, wand, etc. >that clutter our language. :) These things >can be easily written as custom functions by the designer. Dan, I'm not a VHDL person - can you detail more? How's the custom resolution function written? I.e. How's it support the variable number of inputs to the function? i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the net. There's only one net. The net may driven locally, or thru a connection to a sub-entity's output port. Can I do this with VHDL, using custom resolution functions? Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've always supported it in ISE at least since ISE 6.xx, probably forever. If I can give them a VHDL example too, it might help. Thanks, Mark From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 31 Jul 2014 17:14:19 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 21:14:34 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22313"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/edm6RM3Yl5E8dyBEfNrM" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:DAgAZzCy/U1BiI3e/1AL+aRPSzg= Xref: news.eternal-september.org comp.lang.vhdl:7674 On 7/24/2014 6:15 AM, Martin Trummer wrote: > Hi, > > Having following VHDL snippet. This masks put bits from an input at a > certain position > > if mask_ctrl > 0 then > for i in 0 to DWITH-1 loop > if i < mask_ctrl then > next_data(i) <= data(i); > mask_data(i) <= alu_out(i); > else > next_data(i) <= '0'; > mask_data(i) <= '0'; > end if; > end loop; > end if; > > next_data is an input for a FF, mask_data is a combinatorical output. > Are possibilities to optimize this behavior with respect to chip area? Trying to outsmart the compiler is hard to do. The only way I have found to do this is to design my own hardware and then code to describe that hardware. Others have pointed out the mistakes in your code that need to be addressed. I would suggest that you drop your thinking back to logic design 101 and draw a diagram of how you think the circuit should work. Then think of how this would best be implemented in your technology and only then think about how to describe it in the HDL to get what you want. A key point is to know what the source of mask_ctrl is. Is this a configuration register? Why is it encoded rather than specifying the mask directly?.... that would be the lowest chip area I think.... no area at all other than the mask logic itself. -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.39.140 with SMTP id h12mr1002346ice.9.1406842161422; Thu, 31 Jul 2014 14:29:21 -0700 (PDT) X-Received: by 10.50.222.41 with SMTP id qj9mr23826igc.1.1406842161303; Thu, 31 Jul 2014 14:29:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11602241igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11602235igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 14:29:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 21:29:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7675 On Friday, 1 August 2014 05:14:19 UTC+8, rickman wrote: > > A key point is to know what the source of mask_ctrl is. Is this a > > configuration register? Why is it encoded rather than specifying the > > mask directly?.... that would be the lowest chip area I think.... no > > area at all other than the mask logic itself. > Exactly. I believe all the OP wants is just to mask the inputs. It should synthesise to all wires (from I/P to O/P) for the masked bits, and for the rest of the output bits - tied to ground. -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.94.69 with SMTP id a5mr1014464icn.29.1406842687601; Thu, 31 Jul 2014 14:38:07 -0700 (PDT) X-Received: by 10.50.39.16 with SMTP id l16mr15684igk.7.1406842687506; Thu, 31 Jul 2014 14:38:07 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11605703igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11605698igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 14:38:06 -0700 (PDT) In-Reply-To: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 21:38:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7676 On Friday, 1 August 2014 04:55:57 UTC+8, Daniel Kho wrote: > process(all) is > > variable mask:std_ulogic_vector(DWIDTH-1 downto 0); > > begin > > mask:=(0 to mask_ctrl-1=>'1', others=>'0'); > > > > next_data(DWIDTH-1 downto 0)<=data(DWIDTH-1 downto 0) and mask; > > mask_data(DWIDTH-1 downto 0)<=alu_out(DWIDTH-1 downto 0) and mask; > > end process; > > > > -- > > Daniel | www.tauhop.com > > ~eats, drinks, sleeps, and breathes VHDL Since the ranges are all the same, we can simplify this to: process(all) is variable mask:std_ulogic_vector(DWIDTH-1 downto 0); begin mask:=(0 to mask_ctrl-1=>'1', others=>'0'); next_data<=data and mask; mask_data<=alu_out and mask; end process; -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.62.73 with SMTP id x9mr1181765ich.15.1406844269095; Thu, 31 Jul 2014 15:04:29 -0700 (PDT) X-Received: by 10.50.18.50 with SMTP id t18mr19816igd.10.1406844268925; Thu, 31 Jul 2014 15:04:28 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11617632igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11617621igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 15:04:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 22:04:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7677 On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > Dan, > > > > I'm not a VHDL person - can you detail more? How's the custom resolution > > function written? I.e. How's it support the variable number of inputs to > > the function? > > > > i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the > > net. There's only one net. The net may driven locally, or thru a connection > > to a sub-entity's output port. > > > > Can I do this with VHDL, using custom resolution functions? > > > > Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've > > always supported it in ISE at least since ISE 6.xx, probably forever. > > If I can give them a VHDL example too, it might help. > > > > Thanks, > > > > Mark Hi Mark, There are some pretty good references on designing your own custom resolution functions in VHDL. I just did a search and found this: http://vhdl.renerta.com/source/vhd00058.htm There are also predefined (standard) resolution functions within the standard VHDL packages, and anyone can read them. An example of resolved_or (or resolved_wor in my previous post): function resolved_or(s:std_ulogic_vector) return std_logic is variable result:std_ulogic:='0'; begin for i in s'range loop result:=result or s(i); end loop; return result; end function resolved_or; These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. -dan From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.43.70.132 with SMTP id yg4mr1304886icb.30.1406845424319; Thu, 31 Jul 2014 15:23:44 -0700 (PDT) X-Received: by 10.50.79.201 with SMTP id l9mr21072igx.5.1406845424230; Thu, 31 Jul 2014 15:23:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11626780igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11626769igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 15:23:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Thu, 31 Jul 2014 22:23:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7678 On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > I'm not a VHDL person - can you detail more? How's the custom resolution= =20 > function written? I.e. How's it support the variable number of inputs to > the function? >=20 Sorry for the multiple posting. Posted too quickly without reading your ent= ire question. :| A resolution function accepts as argument, a vector (or array) of the signa= l you wish to have multiple drivers on. Say for example you have a signal (= or output) net q as in my previous example, that you wish to have multiple = sources driving it. q is of an unresolved type std_ulogic, but you can appl= y the resolution function "resolved_wor" to resolve q to a deterministic va= lue from multiple sources driving it. q:out resolved_wor std_ulogic; To write a resolution function for q, you create one that accepts a vector = of std_ulogic (we can use the predefined std_ulogic_vector), and this array= contains all the multiple drivers that would be driving q. The resolution = function can then be written to resolve the output based on any resolution = logic you want. This can be a simple OR or AND, or can as complex as need b= e. The output (return value) of a resolution function must therefore be of = a resolved type (such as std_logic). function resolved_wor(s:std_ulogic_vector) return std_logic is begin ... end function resolved_wor; -dan From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Optimize VHDL snippet for area Date: Thu, 31 Jul 2014 19:17:23 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:17:39 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3882"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18TIZIL/kT3VcRoyZBS1cEr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <9f1da2de-0517-4853-8ed8-2f8ca2c3d237@googlegroups.com> Cancel-Lock: sha1:UFYUzjnZhjvz0Oe53vfc7eDazyI= Xref: news.eternal-september.org comp.lang.vhdl:7679 On 7/31/2014 5:29 PM, Daniel Kho wrote: > On Friday, 1 August 2014 05:14:19 UTC+8, rickman wrote: >> >> A key point is to know what the source of mask_ctrl is. Is this a >> >> configuration register? Why is it encoded rather than specifying the >> >> mask directly?.... that would be the lowest chip area I think.... no >> >> area at all other than the mask logic itself. >> > > Exactly. I believe all the OP wants is just to mask the inputs. It should synthesise to all wires (from I/P to O/P) for the masked bits, and for the rest of the output bits - tied to ground. That would only be true if the mask value is constant. I assume it's a control register setting and can be changed from an encoded value 0, 1, 2, 3,... to a mask value 0...0000, 0...0001, 0...0011, 0...0111,... If the mask value changes depending on a real time logic function, then he will need to design the decoder too. If optimization is truly important (this is not a hugely large circuit after all) I bet I can beat the standard decoder design. -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 23:18:47 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 65 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Injection-Date: Thu, 31 Jul 2014 23:18:47 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="4215"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PRP4yQsGrzqW5OlpipAEl" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:MMPF0LjxEtl0vFADUZE80JbMJbk= Xref: news.eternal-september.org comp.lang.vhdl:7680 In article <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com>, Daniel Kho wrote: >On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > >> I'm not a VHDL person - can you detail more? How's the custom resolution >> function written? I.e. How's it support the variable number of inputs to >> the function? >> > >Sorry for the multiple posting. Posted too quickly without reading >your entire question. :| > >A resolution function accepts as argument, a vector (or array) of >the signal you wish to have multiple drivers on. Say for example >you have a signal (or output) net q as in my previous example, that >you wish to have multiple sources driving it. q is of an unresolved >type std_ulogic, but you can apply the resolution function >"resolved_wor" to resolve q to a deterministic value from multiple >sources driving it. > q:out resolved_wor std_ulogic; > >To write a resolution function for q, you create one that accepts a >vector of std_ulogic (we can use the predefined std_ulogic_vector), >and this array contains all the multiple drivers that would be >driving q. The resolution function can then be written to resolve the >output based on any resolution logic you want. This can be a simple OR >or AND, or can as complex as need be. The output (return >value) of a resolution function must therefore be of a resolved type >(such as std_logic). > > function resolved_wor(s:std_ulogic_vector) return std_logic is begin > ... > end function resolved_wor; > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the input to the function. There's only *ONE* net. The one net with multiple (resolved type) drivers on it. I don't see how this is "custom resolution function" is different than any other function? (Again, I'm not VHDL person). What I'm trying to do (verilog speak, sorry): cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); ... The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) in VHDL) that hooks up the CPU bus interface. All the read data, is a wor net. Theres only one "read_data" net (an output of this entity) on BUS_CONNECT. (Think of it as 1 bit to make the testcase easier). "read_data" is 'wor' resolved for the multiple drivers on it. Generics/etc will conditionally compile in/out many cpu_regs. So I don't know how many drivers "read_data" has apriori. Nor could I easily define the width of the "std_ulogic_vector" input to your function. --Mark From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 19:23:38 -0400 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:23:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5825"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Et4cA8l5IBunRTES7rsQV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Cancel-Lock: sha1:YwXr601GhDT6aPZoeOl4NIKyoEc= Xref: news.eternal-september.org comp.lang.vhdl:7681 On 7/31/2014 6:04 PM, Daniel Kho wrote: > On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: >> Dan, >> >> >> >> I'm not a VHDL person - can you detail more? How's the custom resolution >> >> function written? I.e. How's it support the variable number of inputs to >> >> the function? >> >> >> >> i.e. I want the 'resolved_wor' to resolve a variable number of drivers on the >> >> net. There's only one net. The net may driven locally, or thru a connection >> >> to a sub-entity's output port. >> >> >> >> Can I do this with VHDL, using custom resolution functions? >> >> >> >> Xilinx is dragging their feet supporting wor's in verilog thru Vivado. They've >> >> always supported it in ISE at least since ISE 6.xx, probably forever. >> >> If I can give them a VHDL example too, it might help. >> >> >> >> Thanks, >> >> >> >> Mark > > Hi Mark, > There are some pretty good references on designing your own custom resolution functions in VHDL. I just did a search and found this: > http://vhdl.renerta.com/source/vhd00058.htm > > There are also predefined (standard) resolution functions within the standard VHDL packages, and anyone can read them. > > An example of resolved_or (or resolved_wor in my previous post): > > function resolved_or(s:std_ulogic_vector) return std_logic is > variable result:std_ulogic:='0'; > begin > for i in s'range loop > result:=result or s(i); > end loop; > return result; > end function resolved_or; > > These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. The resolved_or function you posted does not implement a wired or. The type used is just std_ulogic and the assignment is result := result or s(i); This is the or of all the bits in a bus. -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 16:39:58 -0700 Organization: Highland Technology, Inc. Lines: 32 Message-ID: <20140731163958.633a719e@rg.highlandtechnology.com> References: <4a9a5bcb-8b89-4656-b201-6c712f92a573@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx05.eternal-september.org; posting-host="e25680cee057b0c034ced785d61acc50"; logging-data="18671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cgu/nDN34f2alz2eGRDJf" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:k4j+5APXLpUPlOj46t/VDxjHRlw= Xref: news.eternal-september.org comp.lang.vhdl:7682 On Thu, 31 Jul 2014 19:23:38 -0400 rickman wrote: > On 7/31/2014 6:04 PM, Daniel Kho wrote: > > On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: > > > > An example of resolved_or (or resolved_wor in my previous post): > > > > function resolved_or(s:std_ulogic_vector) return std_logic is > > variable result:std_ulogic:='0'; > > begin > > for i in s'range loop > > result:=result or s(i); > > end loop; > > return result; > > end function resolved_or; > > > > These custom functions may be defined within an architecture (before the BEGIN), or within a VHDL package. > > The resolved_or function you posted does not implement a wired or. The > type used is just std_ulogic and the assignment is > result := result or s(i); > > This is the or of all the bits in a bus. > Which, when used as a resolution function, makes the signal equal to the OR of all its drivers, i.e. a wired OR. Doesn't it? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:30 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Thu, 31 Jul 2014 19:42:08 -0400 Organization: A noiseless patient Spider Lines: 74 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 31 Jul 2014 23:42:24 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11750"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DPSWd8I6FMC2846aR1P8U" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:SHbTwAuGj4nDPgCJkR+h3sx+INE= Xref: news.eternal-september.org comp.lang.vhdl:7683 On 7/31/2014 7:18 PM, Mark Curry wrote: > In article <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com>, > Daniel Kho wrote: >> On Friday, 1 August 2014 04:58:39 UTC+8, Mark Curry wrote: >> >>> I'm not a VHDL person - can you detail more? How's the custom resolution >>> function written? I.e. How's it support the variable number of inputs to >>> the function? >>> >> >> Sorry for the multiple posting. Posted too quickly without reading >> your entire question. :| >> >> A resolution function accepts as argument, a vector (or array) of >> the signal you wish to have multiple drivers on. Say for example >> you have a signal (or output) net q as in my previous example, that >> you wish to have multiple sources driving it. q is of an unresolved >> type std_ulogic, but you can apply the resolution function >> "resolved_wor" to resolve q to a deterministic value from multiple >> sources driving it. >> q:out resolved_wor std_ulogic; >> >> To write a resolution function for q, you create one that accepts a >> vector of std_ulogic (we can use the predefined std_ulogic_vector), >> and this array contains all the multiple drivers that would be >> driving q. The resolution function can then be written to resolve the >> output based on any resolution logic you want. This can be a simple OR >> or AND, or can as complex as need be. The output (return >> value) of a resolution function must therefore be of a resolved type >> (such as std_logic). >> >> function resolved_wor(s:std_ulogic_vector) return std_logic is begin >> ... >> end function resolved_wor; >> > > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the > input to the function. There's only *ONE* net. The one net with multiple > (resolved type) drivers on it. > > I don't see how this is "custom resolution function" is different > than any other function? (Again, I'm not VHDL person). > > What I'm trying to do (verilog speak, sorry): > cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); > > cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); > > cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); > .... > > The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) > in VHDL) that hooks up the CPU bus interface. All the read data, is a > wor net. > > Theres only one "read_data" net (an output of this entity) on BUS_CONNECT. > (Think of it as 1 bit to make the testcase easier). "read_data" is 'wor' > resolved for the multiple drivers on it. > > Generics/etc will conditionally compile in/out many cpu_regs. So I don't > know how many drivers "read_data" has apriori. Nor could I easily define > the width of the "std_ulogic_vector" input to your function. I think I see where Daniel is coming from. Try reading this link. I guess the function resolved_wor gets applied to your multiple drivers when you declare the signal q:out resolved_wor std_ulogic; http://vhdl.renerta.com/mobile/source/vhd00058.htm So disregard my prior post..... :( -- Rick From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.82.79 with SMTP id c15mr1861202icl.7.1406851799967; Thu, 31 Jul 2014 17:09:59 -0700 (PDT) X-Received: by 10.50.138.69 with SMTP id qo5mr31243igb.7.1406851799799; Thu, 31 Jul 2014 17:09:59 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11664868igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no11664865igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 17:09:58 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Concurrent assignments vs. assignments inside a process From: Dio Gratia Injection-Date: Fri, 01 Aug 2014 00:09:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7684 On Friday, August 1, 2014 1:28:28 AM UTC+12, Sean Durkin wrote: > In case anyone's still interested: > > This gets even worse in Vivado. Not even driving a std_ulogic from two > different places causes an error or warning during synthesis... The best > you can do is to receive a critical warning, but only under certain > circumstances (as it turns out, it makes a difference if one of the > drivers drives a constant value or not, for whatever reason...). > > I've reported it to Xilinx, but as of now they don't believe me that > this is a problem: > > http://tinyurl.com/lkzgsgj > Your test case you provided to Xilinx demonstrates your issue admirably. There's actually support for Xilinx's position in the now withdrawn 1076.6-2004, Section 5, Verification methodology: "... The process of verifying synthesis results using simulation consists of applying equivalent inputs to both the original model and synthesized model and then comparing their outputs to ensure that they are equivalent. Equivalent in this context means that a synthesis tool shall produce a circuit that is equivalent at the input, output, and bidirectional ports of the model. ..." This issue here is that shall is directive. See 1.3 Terminology: "The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to)." And note that synthesis only deals with a subset of VHDL: See 1.1 Scope: " This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis tools may be compliant and yet have features beyond those required by this standard. This standard defines how the semantics of VHDL shall be used, for example, to model level-sensitive and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be sup- ported for interoperability. Use of this standard should minimize the potential for functional simulation mismatches between models before they are synthesized and after they are synthesized." There is no requirement that a synthesis tool provide a valid synthesis output for an invalid model. See the title page: "... The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors." There are only two errors defined in 1076.6, 6.3 Three-state logic and busses and 7.1 Attributes. The one on three-state logic pivots on guarded assignment. And your test case is invalid, you can't have multiple drivers for unresolved types. And back to 5. Verification methodology: "... The input stimulus shall comply with the following criteria: a) Input data does not contain metalogical or high-impedance values. b) Input data may only contain 'H' and 'L' on inputs that are converted to '1' and '0', respectively." There's no requirement that any metavalue on internal_sig be evaluated for matching behavior in top. Resolution can be ignored. The underlying issue here is that your model is invalid and your asking Xilinx detect errors where they've never been required to and historically (prior to reconfigurable FPGAs) it would have been imprudent to synthesize and implement hardware based on an invalid model. The cost implications would have demanded you simulate first where the invalid model would be filtered out. When Daniel also mentions similar issues with a second synthesis vendor the message here is that you need an RTL synthesis standard, and that if resurrected 1076.6 might be updated to require further error detection. Until then you have no leverage. And any standard on synthesis would represent a consensus between vendors (the same ones you're collectively complaining about.) From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.42.188.84 with SMTP id cz20mr4056295icb.1.1406875020865; Thu, 31 Jul 2014 23:37:00 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr72145igb.4.1406875020685; Thu, 31 Jul 2014 23:37:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11792489igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7383964igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 31 Jul 2014 23:37:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5dd43b00-79f3-47ef-abea-82faeafeffa1@googlegroups.com> Subject: Re: Concurrent assignments vs. assignments inside a process From: Daniel Kho Injection-Date: Fri, 01 Aug 2014 06:37:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7685 On Friday, 1 August 2014 08:09:58 UTC+8, Dio Gratia wrote: > The underlying issue here is that your model is invalid and your asking X= ilinx >=20 > detect errors where they've never been required to and historically (prio= r to >=20 > reconfigurable FPGAs) it would have been imprudent to synthesize and impl= ement >=20 > hardware based on an invalid model. The cost implications would have dema= nded >=20 > you simulate first where the invalid model would be filtered out. >=20 >=20 >=20 > When Daniel also mentions similar issues with a second synthesis vendor t= he >=20 > message here is that you need an RTL synthesis standard, and that if >=20 > resurrected 1076.6 might be updated to require further error detection. >=20 >=20 >=20 > Until then you have no leverage. And any standard on synthesis would repr= esent >=20 > a consensus between vendors (the same ones you're collectively complainin= g >=20 > about.) While 1076.6 may not have described about signal resolutions and driving va= lues, the main standard P1076-2008 specifies this very clearly: ------------------------------------------------------- Section 6.4.2.3 Signal declarations [scroll down to Pg. 69] ... A signal may have one or more sources. For a signal of a scalar type, each = source is either a driver (see 14.7.2) or an out, inout, buffer, or linkage= port of a component instance or of a block statement with which the signal= is associated. For a signal of a composite type, each composite source is = a collection of scalar sources, one for each scalar subelement of the signa= l. It is an error if, after the elaboration of a description, a signal has = multiple sources and it is not a resolved signal. It is also an error if, a= fter the elaboration of a description, a resolved signal has more sources t= han the number of elements in the index range of the type of the formal par= ameter of the resolution function associated with the resolved signal. ------------------------------------------------------- It specifically mentions "It is an error if, after the elaboration of a des= cription, a signal has multiple sources and it is not a resolved signal." Therefore, as per my understanding of the LRM, we actually do have some lev= erage when trying to press vendors to actually comply to the standard. We s= hould (and could) tell them that their tools are not compliant to the stand= ard until they get this fixed. IMHO, wrong code stays wrong, and it would b= e wrong for vendors to not give any errors, or worse, optimise away the inc= orrect design. -- Daniel | www.tauhop.com ~eats, drinks, sleeps, and breathes VHDL From newsfish@newsfish Tue Dec 29 16:43:30 2015 X-Received: by 10.43.153.196 with SMTP id lb4mr4529407icc.2.1406877880874; Fri, 01 Aug 2014 00:24:40 -0700 (PDT) X-Received: by 10.50.61.145 with SMTP id p17mr76502igr.16.1406877880764; Fri, 01 Aug 2014 00:24:40 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no11808710igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7394636igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 00:24:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.93; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.93 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Fri, 01 Aug 2014 07:24:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7686 On Friday, 1 August 2014 07:18:47 UTC+8, Mark Curry wrote: > Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the >=20 > input to the function. There's only *ONE* net. The one net with multip= le=20 >=20 > (resolved type) drivers on it. >=20 Yes, the 'q' in my previous example is also a single net, with multiple dri= vers driving it. > What I'm trying to do (verilog speak, sorry): >=20 > cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); > cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); > cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); >=20 > ... >=20 > The `BUS_CONNECT is simple a verilog macro (probably a structure (record?= ) > in VHDL) that hooks up the CPU bus interface. All the read data, is a= =20 > wor net.=20 >=20 Don't really understand this Verilog code, sorry. Is that within an @always= block? So are those transactions? > Generics/etc will conditionally compile in/out many cpu_regs. So I don't= =20 > know how many drivers "read_data" has apriori. Nor could I easily define > the width of the "std_ulogic_vector" input to your function. As long as you leave the vector width unconstrained in your resolution func= tion, you don't need to specify how many drivers there are. Upon elaboratio= n of your design, the resolution function takes in the vector of all multip= le drivers - it finds all the multiple driving nets, and groups them into a= n array automatically. The size of the array is automatically calculated up= on elaboration. It's all done behind the scenes for you. -dan From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.207.146 with SMTP id fy18mr6982810icb.12.1406904917430; Fri, 01 Aug 2014 07:55:17 -0700 (PDT) X-Received: by 10.182.4.1 with SMTP id g1mr32084obg.3.1406904917276; Fri, 01 Aug 2014 07:55:17 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!news.glorb.com!h18no7546043igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7546011igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 07:55:16 -0700 (PDT) In-Reply-To: <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Andy Injection-Date: Fri, 01 Aug 2014 14:55:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7687 IINM, Kho's solution will not compile. When "others" is used in an index expression, any accompanying indices/ranges must be locally static. This is because the value of "others" must be staticly determinable during compilation (unit analysis), before elaboration or exeution. Andy From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Fri, 1 Aug 2014 17:47:30 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 46 Message-ID: References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Injection-Date: Fri, 1 Aug 2014 17:47:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="9275"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/5sdEacbONe8sNZKjZYfFf" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:TDTwon6VeqRL/10BdfQA/EMCxEs= Xref: news.eternal-september.org comp.lang.vhdl:7688 In article <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com>, Daniel Kho wrote: >On Friday, 1 August 2014 07:18:47 UTC+8, Mark Curry wrote: >> Yeah - doesn't solve my problem. There's no "std_ulogic_vector" for the >> >> input to the function. There's only *ONE* net. The one net with multiple >> >> (resolved type) drivers on it. >> > >Yes, the 'q' in my previous example is also a single net, with multiple >drivers driving it. > > >> What I'm trying to do (verilog speak, sorry): >> >> cpu_reg cpu_reg1 ( `BUS_CONNECT, .data_o( reg1_val ) ); >> cpu_reg cpu_reg2 ( `BUS_CONNECT, .data_o( reg2_val ) ); >> cpu_reg cpu_reg3 ( `BUS_CONNECT, .data_o( reg3_val ) ); >> >> ... >> >> The `BUS_CONNECT is simple a verilog macro (probably a structure (record?) >> in VHDL) that hooks up the CPU bus interface. All the read data, is a >> wor net. >> > >Don't really understand this Verilog code, sorry. Is that within an >@always block? So are those transactions? Sorry, should have been more clear. Those are all just instaciations. The "multiple driver" read_data is all within `BUS_CONNNECT. To expand it (leaving some connections out to synplify): wor rddata_o; cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" to the single net "rddata_o". "rddata_o" is both the input, and output of the function... How do I hook it up? --Mark From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.43.85.201 with SMTP id ap9mr12000671icc.11.1406954710894; Fri, 01 Aug 2014 21:45:10 -0700 (PDT) X-Received: by 10.50.29.13 with SMTP id f13mr238719igh.15.1406954710755; Fri, 01 Aug 2014 21:45:10 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12349478igc.0!news-out.google.com!px9ni585igc.0!nntp.google.com!h18no7750143igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 1 Aug 2014 21:45:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Sat, 02 Aug 2014 04:45:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7689 On Saturday, August 2, 2014 5:47:30 AM UTC+12, Mark Curry wrote: > rddata_o has multiple drivers. I want them resolved like a verilog 'wor'= , but=20 > in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution= function" "resolved_wor"=20 > to the single net "rddata_o". "rddata_o" is both the input, and output o= f the function... > How do I hook it up? You specify a resolution function to use in a subtype indication declaring = signals. The simulator provides an array type of the base type of the sign= al having a value for every driver on the net and calls the function inter= nally. A resolution function has one argument, an array vector and returns a resul= t that is of the same base type. This is from package std_logic_1164 for std_logic: type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; ------------------------------------------------------------------- =20 -- resolution function ------------------------------------------------------------------- =20 constant resolution_table : stdlogic_table :=3D ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | =20 -- --------------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 | ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 | ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z | ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W | ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L | ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is variable result : STD_ULOGIC :=3D 'Z'; -- weakest state default begin -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. if (s'length =3D 1) then return s(s'low); else for i in s'range loop result :=3D resolution_table(result, s(i)); end loop; end if; return result; end function resolved; Additionally if you were to look at the truth table for wor and trior in th= e 1064 (Verilog) standard you'd find that wor works identically to using th= e std_ulogic subtype X01Z (which is also resolved, using the same resolutio= n function shown above). Further package std_logic_1164 provides To_X01Z conversion functions that c= an be used to pre-filter std_logic and std_logic_vector values to X01Z valu= es. They are conversion functions (1 input, a return value from a pure fun= ction) and functions are expressions ( can be used for example in port map = associations) and the result is base type compatible with std_logic. If you only ever assign 'X', '0', '1' or 'Z' to a standard logic value And= you provide a default value that is one of those four values you don't nee= d to do anything to get the same effect as using wor in Verilog. =20 The To_X01Z functions can be used to filter MVL9 signal values ('U','X','0'= , '1', 'Z', 'W', 'L','H', '-') to 'X', '0', '1', 'Z' when assignment is out= of your control. VHDL's std_logic_1164 package already provides the functionality you're aft= er. From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.235.132 with SMTP id kg4mr13716068icb.22.1406968835831; Sat, 02 Aug 2014 01:40:35 -0700 (PDT) X-Received: by 10.50.4.6 with SMTP id g6mr264075igg.4.1406968835711; Sat, 02 Aug 2014 01:40:35 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12426060igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no12426057igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 2 Aug 2014 01:40:35 -0700 (PDT) In-Reply-To: <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.113; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.113 References: <27a7f7a2-0a85-4851-9727-865e0429d854@googlegroups.com> <45ab2df7-ca44-4c9f-a219-18818d92d074@googlegroups.com> <8de054de-16f1-4a41-b28b-3e2cd0c4fab0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <809f5d70-0c39-4704-8066-a2c1244d688a@googlegroups.com> Subject: Re: Optimize VHDL snippet for area From: Daniel Kho Injection-Date: Sat, 02 Aug 2014 08:40:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7690 On Friday, 1 August 2014 22:55:16 UTC+8, Andy wrote: > IINM, Kho's solution will not compile. When "others" is used in an index expression, any accompanying indices/ranges must be locally static. > > > > This is because the value of "others" must be staticly determinable during compilation (unit analysis), before elaboration or exeution. > > > > Andy Yes, like what Rick has said as well. If mask_ctrl were a register, my example won't work. However, if it was a constant (as I originally assumed), my example would compile. Anyway, it's still unclear what mask_ctrl is for. If mask_ctrl were some register, then I believe 'mask' can be changed accordingly depending upon what the value of mask_ctrl is. This will probably be where the bulk of the logic is. Perhaps the OP needs something like this (assuming mask_ctrl is a register): architecture rtl of masker is signal mask:std_ulogic_vector(data'range); signal i:natural range data'range; begin /* Use a clocked process to set mask values. This saves you timing problems later (if you were to use a purely combinatorial process, e.g. a for-loop). */ process(reset,clk) is begin if reset then i<=0; ready<=false; mask<=(others=>'0'); elsif rising_edge(clk) then if i Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.113; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.113 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Sat, 02 Aug 2014 09:21:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7691 On Saturday, 2 August 2014 12:45:10 UTC+8, Dio Gratia wrote: > Additionally if you were to look at the truth table for wor and trior in the 1064 (Verilog) standard you'd find that wor works identically to using the std_ulogic subtype X01Z (which is also resolved, using the same resolution function shown above). > Sorry, does the Verilog wor resolve '0' and '1' to an 'X'? Or will it be resolved to a '1'? -dan From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.38.15 with SMTP id a15mr9978018ice.30.1407019671630; Sat, 02 Aug 2014 15:47:51 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr338165igb.4.1407019671543; Sat, 02 Aug 2014 15:47:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no12792318igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no12792309igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 2 Aug 2014 15:47:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Sat, 02 Aug 2014 22:47:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7692 On Saturday, August 2, 2014 9:21:37 PM UTC+12, Daniel Kho wrote: > Sorry, does the Verilog wor resolve '0' and '1' to an 'X'? Or will it be resolved to a '1'? Opps! Wrong table, Dan is right. My bad. 4-4 from 1364-2005: wor/trior 0 1 x z 0 0 1 x 0 1 1 1 1 1 x x 1 x x z 0 1 x z std_logic matches 4-2, wire/tri. Which says yes a different resolution function for wor, and begs the question of who can synthesize logic from single rail transfer gate models in VHDL. A demo case for penance: library ieee; use ieee.std_logic_1164.all; package wor_stuff is type wortrior is ('X', '0', '1', 'Z'); type wortrior_vector is array (natural range <>) of wortrior; function wor_trior (s: wortrior_vector) return wortrior; subtype wor is wor_trior wortrior; type wor_vector is array (natural range <>) of wor; function wor_image(inp: wor_vector) return string; end package; package body wor_stuff is type wor_table is array (wortrior, wortrior) of wortrior; constant resolution_table : wor_table := ( -- -------------------------------- -- | X 0 1 Z | | -- -------------------------------- ('X', 'X', '1', 'X'), -- | X | ('X', '0', '1', '0'), -- | 0 | ('1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z') -- | Z | ); function wor_trior ( s: wortrior_vector ) return wortrior is variable result: wortrior := 'Z'; begin if (s'length = 1) then return (s(s'low)); else for i in s'range loop result := resolution_table(result, s(i)); end loop; end if; return result; end wor_trior; function wor_image(inp: wor_vector) return string is variable image_str: string (1 to inp'length); alias input_str: wor_vector (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) := character'VALUE(wortrior'IMAGE(input_str(i))); end loop; return image_str; end; end package body; library ieee; use ieee.std_logic_1164.all; use work.wor_stuff.all; entity cpu_reg_dummy is generic ( value: wor_vector(3 downto 0) := (others => 'Z') ); port ( rddata_o: out wor_vector(3 downto 0) ); end entity; architecture foo of cpu_reg_dummy is begin rddata_o <= value after 0.5 ns; end architecture; library ieee; use ieee.std_logic_1164.all; use work.wor_stuff.all; entity foo is end entity; architecture fum of foo is component cpu_reg_dummy generic ( value: wor_vector(3 downto 0) := (others => 'Z') ); port ( rddata_o: out wor_vector(3 downto 0) ); end component; signal rddata_o: wor_vector (3 downto 0); begin CPU_REG1: cpu_reg_dummy generic map (value => "0000") port map (rddata_o => rddata_o); CPU_REG2: cpu_reg_dummy generic map (value => "1001") port map (rddata_o => rddata_o); CPU_REG3: cpu_reg_dummy generic map (value => "ZZZZ") port map (rddata_o => rddata_o); CPU_REG4: cpu_reg_dummy generic map (value => "ZZZX") port map (rddata_o => rddata_o); WHAT: process begin wait for 0.6 ns; report "rddata_o = " & wor_image(rddata_o); wait; end process; end architecture; Which analyzes, elaborates and simulates the test case foowith the following assertion output: ** Note: 600ps+0: Report Note: rddata_o = 1001 Process :foo:what File wor.vhdl, Line 113 (and yes the resolution function wor_trior is shamelessly derived from package std_logic_1164's resolution function). From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.62.73 with SMTP id x9mr26259020ich.15.1407078468848; Sun, 03 Aug 2014 08:07:48 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr426433igl.8.1407078468758; Sun, 03 Aug 2014 08:07:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no13198488igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no13198479igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Aug 2014 08:07:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.12; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.12 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Daniel Kho Injection-Date: Sun, 03 Aug 2014 15:07:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7693 On Saturday, 2 August 2014 01:47:30 UTC+8, Mark Curry wrote: > Sorry, should have been more clear. Those are all just instaciations. > > The "multiple driver" read_data is all within `BUS_CONNNECT. > > To expand it (leaving some connections out to synplify): > > > > wor rddata_o; > > cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); > > > > rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but > > in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" > > to the single net "rddata_o". "rddata_o" is both the input, and output of the function... > > How do I hook it up? > > > > --Mark architecture rtl of test is signal rddata_o:resolved_wor std_ulogic; /* declare the other internal non-resolved signals here (addr_i, cs_i, wrdata_i, rwn_i). */ begin cpu_reg1: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); cpu_reg2: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); cpu_reg3: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); end architecture rtl; Here all the 3 entity instances (cpu_reg1, cpu_reg2, cpu_reg3) will be driving the single resolved wire "rddata_o". The resolved_wor resolution function will be used to resolve the multiple drivers. Of course, you can have more instances driving the net, without needing to specify the array width (or the number of drivers) into the resolution function, provided your function does not constrain the input argument's width. To write the resolution function 'resolved_wor', you can use the examples Dio or I provided earlier. Just place it within a VHDL package, and remember to add a library-use clause to 'import' this package into your design. -dan From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.212.207 with SMTP id gt15mr17688395icb.31.1407126799966; Sun, 03 Aug 2014 21:33:19 -0700 (PDT) X-Received: by 10.50.4.6 with SMTP id g6mr491715igg.4.1407126799839; Sun, 03 Aug 2014 21:33:19 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no13517454igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no13517453igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 3 Aug 2014 21:33:19 -0700 (PDT) In-Reply-To: <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <078f85e7-b935-403d-896e-9d8493b63fb9@googlegroups.com> <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> <6f3c515b-99a7-41dc-9261-111534779be7@googlegroups.com> <8d2e7da7-f731-4499-a61a-7d724b8f43ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wired Or in VHDL From: Dio Gratia Injection-Date: Mon, 04 Aug 2014 04:33:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7694 VHDL2008 also has this neat feature the Jim and Peter call Resolved Element= s in 3.2 of their book VHDL2008 Just the New Stuff. If you were to look th= rough previous versions of the standard you'd find it's new, although parts= those standards imply you can do it while otherwise explicitly not allowin= g it. The idea is that you can specify the resolution function to use on elements= of a composite types subtype declaration. Previously if I provided a resolution indication on a composite type: signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range); The resolution function would have to be of the signal's type in this case = std_logic_vector (and it can be, because a composite type resolution functi= on will replace any element resolution). =20 So they've added a feature to the language to allow you to specify element = resolution: signal rddata_o: (wor_trior) std_logic_vector (rddata_o_range); And this works for records two, where you'd specify multiple resolution fun= ction names inside the parentheses. Resolution is subtype bound and every declaration of a signal is a subtype = declaration. So, historically why this is important can be demonstrated by writing a VHD= L design specification compatible with a previous edition of the spec. This is the previous demonstration re-written to specify a resolution funct= ion for a std_logic_vector array subtype: library ieee; use ieee.std_logic_1164.all; package wor_std is subtype rddata_o_range is integer range 3 downto 0; type rddata_o_array is array (natural range <>) of std_logic_vector(rdd= ata_o_range); =20 function rddata_o_resolv (s: rddata_o_array) return std_logic_vector; = =20 =20 function wor_trior (s: std_logic_vector) return std_logic; function slv_image(inp: std_logic_vector) return string; end package; package body wor_std is =20 type wor_table is array (X01Z, X01Z) of std_ulogic; constant resolution_table : wor_table :=3D ( -- -------------------------------- -- | X 0 1 Z | | =20 -- -------------------------------- ('X', 'X', '1', 'X'), -- | X | ('X', '0', '1', '0'), -- | 0 | ('1', '1', '1', '1'), -- | 1 | ('X', '0', '1', 'Z') -- | Z | ); =20 function wor_trior ( s: std_logic_vector ) return std_logic is variable result: std_logic :=3D 'Z';=20 begin if (s'length =3D 1) then return (To_X01Z(s(s'low))); else for i in s'range loop result :=3D resolution_table(result, To_X01Z(s(i))); end loop; end if; return result; end wor_trior; =20 function rddata_o_resolv (s: rddata_o_array) return std_logic_vector is variable wor: std_logic_vector (s'range); variable result: std_logic_vector (rddata_o_range); begin for i in result'range loop for j in s'range loop wor(j) :=3D s(j)(i); end loop; report "wor =3D " & slv_image(wor); result(i) :=3D wor_trior(wor); end loop; return result; end function; =20 function slv_image(inp: std_logic_vector) return string is variable image_str: string (1 to inp'length); alias input_str: std_logic_vector (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) :=3D character'VALUE(std_ulogic'IMAGE(input_str(i)= )); end loop; return image_str; end; =20 end package body; library ieee; use ieee.std_logic_1164.all; use work.wor_std.all; entity cpu_reg_dummy is generic ( value: std_logic_vector(3 downto 0) :=3D (others =3D> 'Z') ); port ( rddata_o: out std_logic_vector(3 downto 0) ); end entity; architecture foo of cpu_reg_dummy is=20 =20 begin rddata_o <=3D value after 0.5 ns; end architecture; library ieee; use ieee.std_logic_1164.all; use work.wor_std.all; entity foe is end entity; architecture fum of foe is =20 component cpu_reg_dummy generic ( value: std_logic_vector(rddata_o_range) :=3D (others =3D> = 'Z') ); port ( rddata_o: out std_logic_vector(rddata_o_range) ); end component; =20 signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range); -- signal rddata_o: (wor_trior) std_logic_vector (rddata_o_range); -- = -2008 =20 begin =20 CPU_REG1: cpu_reg_dummy generic map (value =3D> "0000") port map (rddata_o =3D> rddata_o); CPU_REG2: cpu_reg_dummy generic map (value =3D> "1001") port map (rddata_o =3D> rddata_o); CPU_REG3: cpu_reg_dummy generic map (value =3D> "ZZZZ") port map (rddata_o =3D> rddata_o); =20 CPU_REG4: cpu_reg_dummy generic map (value =3D> "ZZZX") port map (rddata_o =3D> rddata_o); =20 WHAT: process begin wait for 0.6 ns; report "rddata_o =3D " & slv_image(rddata_o); wait; end process; end architecture; The really harsh part of using a tool complying to an earlier standard is f= or the resolution function rddata_o_resolv we can't specify an array type w= ith a unconstrained element type, which means for the demo the index range = of rddata_o has been fixed where everything can see it in the package wor_s= td. =20 This gives you an idea what a simulator does, assembling arrays of each ele= ment and resolving those.=20 wor_std.vhdl:50:13:@500ps:(report note): wor =3D 01zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 00zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 00zz wor_std.vhdl:50:13:@500ps:(report note): wor =3D 01zx wor_std.vhdl:126:9:@600ps:(report note): rddata_o =3D 1001 And the line 50 reports are in the resolution function and taking those val= ues vertically we see values written out by the cpu_reg_dummy instantiation= s. Take horizontally the wor_trior resolution of those tells us what each of t= he index values for rdata_o is going to be. You can also note that those logical operators for std_ulogic related types= use table look up to speed things up. From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.66.66.3 with SMTP id b3mr3499864pat.6.1407167781459; Mon, 04 Aug 2014 08:56:21 -0700 (PDT) X-Received: by 10.140.105.200 with SMTP id c66mr312031qgf.4.1407167781410; Mon, 04 Aug 2014 08:56:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no8702978igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4325991qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 08:56:21 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Help for function calling From: fl Injection-Date: Mon, 04 Aug 2014 15:56:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7695 Hi, I want to program a CRC project originating from a past discussion: function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned; constant D_vec : in unsigned ; constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned is variable X_out : unsigned(X_load'range); begin X_out := X_load; for I in D_vec'range loop -- call serial version for each bit X_out := crc_shift(X_out, D_vec(I), Poly); end loop; return X_out; end function crc_shift; end package body crc_package; library IEEE; use IEEE.std_logic_1164.all; use WORK.crc_package.all; entity tb is end tb; architecture structural of bit8_adder is signal internal_carry : std_logic; signal sum1: std_logic_vector(15 downto 0); begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); end; The code has an error when compiling: ** Error: C:\Users\Jeff\crc_ccitt.vhd(100): No feasible entries for subprogram "crc_shift". I am new to VHDL, especially to function. Could you help me on what is wrong with my code? Thanks. From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.68.209.130 with SMTP id mm2mr9397088pbc.3.1407169167925; Mon, 04 Aug 2014 09:19:27 -0700 (PDT) X-Received: by 10.140.36.198 with SMTP id p64mr39065qgp.10.1407169167877; Mon, 04 Aug 2014 09:19:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no13830407igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4329910qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 09:19:27 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Subject: Re: Help for function calling From: fl Injection-Date: Mon, 04 Aug 2014 16:19:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 5308 X-Received-Body-CRC: 1127044844 Xref: news.eternal-september.org comp.lang.vhdl:7696 On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > Hi, > I guess that there are two overloading crc_shift function in previous post causing error. Then I explicitly define two crc_shift(0) function inside the package. It has a new error: ** Error: C:\Users\Jeff\crc_ccitt.vhd(15): (vcom-1115) Subtype indication found where type mark is required. Could anybody help me on what is wrong? Thanks, library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package crc_package is function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned (15 downto 0); constant D_vec : in unsigned (15 downto 0); constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned (15 downto 0); end package crc_package; package body crc_package is function crc_shift0 -- Mike Treseler -- serial data version, see overload for parallel data below -- Purpose : Single bit shift for a CRC register using any polynomial. -- Inputs : X_load : Current CRC vector. -- D_bit : Data to shift into CRC vector. -- Poly : CRC polynomial. Default is Frame Relay. -- -- Outputs : CRC vector after CRC shift. ( constant X_load : in unsigned; -- register start value constant D_bit : in std_ulogic := '0'; -- input bit constant Poly : in unsigned := x"3223" --Poly_16_12_5 -- poly bits ) return unsigned is variable X_out : unsigned(X_load'range); -- CRC register begin ---------------------------------------------------------------------- -- we assume that X and Poly are in downto format -- to match the textbook definition of LSFR -- and to match the CCITT FCS bit assigments -- for frame relay, note that X(15) becomes the lsb of octet n-2 -- and that X(7 ) becomes the lsb of octet n-1 ---------------------------------------------------------------------- -- Procedure: Left shift a '0' into the current X0 -- and the previous X(14) into the current X15 etc. -- if the original X15 is '1' or the data is '1' -- but not both, then invert the poly bit locations ---------------------------------------------------------------------- -- Sample Invocation: -- crc_shift( "0001000100010001", '1')); -- SLL 0010001000100010 -- shift the variable -- D (not X15) [ ! ! !] -- invert poly locations? -- expect("shift1 0011001000000011"); -- expected result ---------------------------------------------------------------------- assert X_load'length = Poly'length report "crc_shift: Vectors X_load and Poly must be of equal length." severity error; X_out := X_load sll 1; if (X_load(X_load'left) xor D_bit) = '1' then X_out := X_out xor Poly; end if; return unsigned(X_out); -- returns each shift end function crc_shift0; ----------------------------------------------- function crc_shift -- Mike Treseler -- parallel data version (constant X_load : in unsigned (15 downto 0); constant D_vec : in unsigned (15 downto 0); constant Poly : in unsigned := x"3223") --Poly_16_12_5) return unsigned is variable X_out : unsigned(X_load'range); begin X_out := X_load; for I in D_vec'range loop -- call serial version for each bit X_out := crc_shift0(X_out, D_vec(I), Poly); end loop; return X_out; end function crc_shift; end package body crc_package; library IEEE; use IEEE.std_logic_1164.all; use WORK.crc_package.all; entity tb is end tb; architecture structural of tb is signal internal_carry : std_logic; signal sum1: unsigned (15 downto 0); begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); end; From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.68.222.194 with SMTP id qo2mr10001030pbc.6.1407182082475; Mon, 04 Aug 2014 12:54:42 -0700 (PDT) X-Received: by 10.140.27.102 with SMTP id 93mr41713qgw.23.1407182082403; Mon, 04 Aug 2014 12:54:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h18no13956234igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4373984qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 12:54:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com> Subject: How to understand the different CRC formats? From: fl Injection-Date: Mon, 04 Aug 2014 19:54:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7697 Hi, I read a post on this forum about CRC: https://groups.google.com/forum/#!searchin/comp.lang.vhdl/crc/comp.lang.vhdl/GL1irJS6WrA/FiBxmFXal24J I can run this routine through simulation. In the same time, my Matlab can generate the same results with CCITT (x^16+x^12+x^5+1). The initial generator states are all '0'. When the message bits are 0x80000, the checksum is 0x1B98. When I check website: http://www.lammertbies.nl/comm/info/crc-calculation.html There are several kinds of CCITT, such as xModem, 0xFFFF etc. I have tried different kinds of initial states, byte order etc., but no one can generate the same results of the simulation program and Matlab result. Could you tell me what format can result in the differences? Second, the original code is very good. I know some FPGA vendors sell CRC IP. I would like to know what advantage of their design comparing to the Mike Treseler's code? Thanks, From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.182.125.37 with SMTP id mn5mr10651719obb.49.1407183883615; Mon, 04 Aug 2014 13:24:43 -0700 (PDT) X-Received: by 10.140.23.163 with SMTP id 32mr65170qgp.8.1407183883548; Mon, 04 Aug 2014 13:24:43 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h18no8813963igc.0!news-out.google.com!b3ni5177qac.1!nntp.google.com!j15no4447193qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 13:24:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: KJ Injection-Date: Mon, 04 Aug 2014 20:24:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7698 On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > I am new to VHDL, especially to function. Could you help me on what is wrong > with my code? You declared sum1 as a std_logic_vector, not an unsigned. The crc_shift function returns unsigned. Change this... signal sum1: std_logic_vector(15 downto 0); To this... signal sum1: unsigned(15 downto 0); Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.236.26.206 with SMTP id c54mr527014yha.44.1407207890007; Mon, 04 Aug 2014 20:04:50 -0700 (PDT) X-Received: by 10.50.67.98 with SMTP id m2mr671465igt.15.1407207889730; Mon, 04 Aug 2014 20:04:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j15no4508381qaq.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14144011igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 4 Aug 2014 20:04:49 -0700 (PDT) In-Reply-To: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59711d1d-e1f2-4cdc-917e-d1a7f339226a@googlegroups.com> Subject: Re: Help for function calling From: Dio Gratia Injection-Date: Tue, 05 Aug 2014 03:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7699 On Tuesday, August 5, 2014 4:19:27 AM UTC+12, fl wrote: > On Monday, August 4, 2014 11:56:21 AM UTC-4, fl wrote: > > > Hi, > > > I guess that there are two overloading crc_shift function in previous post > causing error. Then I explicitly define two crc_shift(0) function inside the > package. It has a new error: > > > ** Error: C:\Users\Jeff\crc_ccitt.vhd(15): > (vcom-1115) Subtype indication found where type mark is required. > You could consider posting code with line numbers. I believe this is line 15: return unsigned (15 downto 0); And a different error message may help: ghdl -a crc_shft.vhdl crc_shft.vhdl:47:25: index constraint not allowed here ghdl: compilation error subprogram_specification ::= procedure designator [ ( formal_parameter_list ) ] | [ pure | impure ] function designator [ ( formal_parameter_list ) ] return type_mark type_mark ::= type_name | subtype_name Notice the lack of subtype indication associated with the return type_mark. It should be: return unsigned ; -- (15 downto 0); It also doesn't match the function's subprogram specification in the package body. There are other problems with entity tb. You're missing a use statement for package ieee.numeric_std.all for the type declaration unsigned. After which your code analyzes, elaborates and runs. With a little added monitoring: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.crc_package.all; entity tb is end tb; architecture structural of tb is signal internal_carry : std_logic; signal sum1: unsigned (15 downto 0); function unsigned_image(inp: unsigned) return string is variable image_str: string (1 to inp'length); alias input_str: unsigned (1 to inp'length) is inp; begin for i in input_str'range loop image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i))); end loop; return image_str; end; begin sum1 <= crc_shift(x"3322", x"1111", x"3223"); MONITOR: process begin wait for 1 ns; report "sum1 = " & unsigned_image(sum1); wait; end process; end architecture; gives: crc_shft.vhdl:114:9:@1ns:(report note): sum1 = 1011100111100000 Which is x"B9E0" From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.68.209.130 with SMTP id mm2mr2314772pbc.3.1407252372344; Tue, 05 Aug 2014 08:26:12 -0700 (PDT) X-Received: by 10.50.41.103 with SMTP id e7mr771582igl.8.1407252372098; Tue, 05 Aug 2014 08:26:12 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no14460598igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14460593igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 08:26:11 -0700 (PDT) In-Reply-To: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.96; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.96 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: Daniel Kho Injection-Date: Tue, 05 Aug 2014 15:26:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7700 On Tuesday, 5 August 2014 00:19:27 UTC+8, fl wrote: > package crc_package is=20 > function crc_shift > -- Mike Treseler > -- parallel data version > (constant X_load : in unsigned (15 downto 0); > constant D_vec : in unsigned (15 downto 0); > constant Poly : in unsigned :=3D x"3223") --Poly_16_12_5) > return unsigned (15 downto 0); > end package crc_package;=20 >=20 > package body crc_package is=20 > function crc_shift0=20 ... Just adding to what others have said. You need to declare the function crc_= shift0 at the package declarative area as well, since you have that functio= n in the package body and intend to use it. package crc_package is function crc_shift(...) return unsigned; function crc_shift0(...) return unsigned; end package crc_package; Make sure the subprogram "signature" is the same for both the declarative r= egion and the body. E.g. if you declared your subprogram to return an 'unsi= gned(15 downto 0)', then to be consistent, you should use the same return t= ype in your subprogram specification (the one in the package body). -dan From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Wired Or in VHDL Date: Tue, 5 Aug 2014 17:01:19 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 70 Message-ID: References: <5c10d684-fcd4-4bfc-8fac-f855084ceb4e@googlegroups.com> Injection-Date: Tue, 5 Aug 2014 17:01:19 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="22846"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+hFnhCJ9+5ni49IJjdjciZ" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:iHXOH2YyGUJNkDyGmBLlGxmjPWU= Xref: news.eternal-september.org comp.lang.vhdl:7701 In article , Daniel Kho wrote: >On Saturday, 2 August 2014 01:47:30 UTC+8, Mark Curry wrote: >> Sorry, should have been more clear. Those are all just instaciations. >> >> The "multiple driver" read_data is all within `BUS_CONNNECT. >> >> To expand it (leaving some connections out to synplify): >> >> >> >> wor rddata_o; >> >> cpu_reg cpu_reg1 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> cpu_reg cpu_reg2 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> cpu_reg cpu_reg3 ( .addr_i( addr_i ), .cs_i( cs_i ), .wrdata_i( wrdata_i ), .rwn_i( rwn_i ), .rddata_o( rddata_o ) ); >> >> >> >> rddata_o has multiple drivers. I want them resolved like a verilog 'wor', but >> >> in VHDL. I'm having trouble figuring out how to tie the VHDL "resolution function" "resolved_wor" >> >> to the single net "rddata_o". "rddata_o" is both the input, and output of the function... >> >> How do I hook it up? >> >> >> >> --Mark > > >architecture rtl of test is > signal rddata_o:resolved_wor std_ulogic; > > /* declare the other internal non-resolved signals here (addr_i, > cs_i, wrdata_i, rwn_i). > */ > >begin > cpu_reg1: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > > cpu_reg2: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > > cpu_reg3: entity work.cpu_reg(rtl) port map(addr_i=>addr_i, cs_i=>cs_i, wrdata_i=>wrdata_i, rwn_i=>rwn_i, rddata_o=>rddata_o); > >end architecture rtl; > >Here all the 3 entity instances (cpu_reg1, cpu_reg2, cpu_reg3) will be driving the single resolved wire "rddata_o". The resolved_wor resolution function will be used to resolve the multiple drivers. > >Of course, you can have more instances driving the net, without needing to specify the array width (or the number of drivers) into the resolution function, provided your function does not constrain >the input argument's width. > >To write the resolution function 'resolved_wor', you can use the examples Dio or I provided earlier. Just place it within a VHDL package, and remember to add a library-use clause to 'import' this >package into your design. Dan, and all. Thanks for the detailied example (and having the patience to beat its use thru my thick skull). That is indeed a useful tool in the language. I'm going to play around with this when I get some time, and see what the tool support is like. Thanks, Mark From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: How to understand the different CRC formats? Date: Tue, 5 Aug 2014 18:53:05 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 51 Message-ID: References: <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com> Injection-Date: Tue, 5 Aug 2014 18:53:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="10668"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19rwWFVB+0lAXsR9hbYgtYv" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:HmziE1AscXkIXA6PoTHsSma39aU= Xref: news.eternal-september.org comp.lang.vhdl:7702 In article <79e0ac75-a108-424c-b982-41bd68ad1082@googlegroups.com>, fl wrote: >Hi, > >I read a post on this forum about CRC: >https://groups.google.com/forum/#!searchin/comp.lang.vhdl/crc/comp.lang.vhdl/GL1irJS6WrA/FiBxmFXal24J > >I can run this routine through simulation. In the same time, my Matlab can generate the same results with CCITT (x^16+x^12+x^5+1). The initial generator >states are all '0'. When the message bits are 0x80000, the checksum is 0x1B98. > >When I check website: > >http://www.lammertbies.nl/comm/info/crc-calculation.html > >There are several kinds of CCITT, such as xModem, 0xFFFF etc. I have tried >different kinds of initial states, byte order etc., but no one can generate >the same results of the simulation program and Matlab result. Could you tell me >what format can result in the differences? > > > >Second, the original code is very good. I know some FPGA vendors sell CRC IP. >I would like to know what advantage of their design comparing to the Mike >Treseler's code? Not specifically answering your questions but... My favorite paper on CRCs is here: http://www.ross.net/crc/download/crc_v3.txt It's old (1993) - but entire valid today. It describes, pretty much every way you can do a CRC. Ross describes CRCs in general, with examples. Then lists a way of fully specifying any CRC. Many standard examples (like CCITT) are included. Take an hour or so and read this paper. If you're looking at this from a hardware angle (which I think you are, as you're asking this question in a VHDL newsgroup), then you can STOP READING after section 8. Past this part of the paper Ross begins to describe how CRC's are efficiently done in SW. YOU DON'T NEED TO KNOW this first time. CRC's in HW are really simple. Don't let the SW "Table-Driven Implementations" cloud your head right now. Just focus on the first part of the paper. Regards, Mark From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.182.34.130 with SMTP id z2mr3408726obi.3.1407272498543; Tue, 05 Aug 2014 14:01:38 -0700 (PDT) X-Received: by 10.140.32.227 with SMTP id h90mr50097qgh.26.1407272498518; Tue, 05 Aug 2014 14:01:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no9249580igc.0!news-out.google.com!b3ni5434qac.1!nntp.google.com!v10no4612788qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 14:01:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.229.140.25; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 64.229.140.25 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Subject: How to model an internal state in a function (or a procedure)? From: fl Injection-Date: Tue, 05 Aug 2014 21:01:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7703 Hi, After I get helps from several on-line groups, I can calculate a CRC with a VHDL project. The problem now is that I can get the 16-bit checksum in one time calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs two clocks to get a 16-bit CRC checksum. My code originates from a function call, which is a combination logic (no register), from on-line post. When I modify it to get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the internal states for the next iterative CRC calculation (Is this right?) The function call seems not work in this way (It only output the result, not the internal states). The CRC problem is just like an integer division. I have to store the residue and the new divisor (dividend is polynomial, constant in this case). It looks like the residue must have attribute of 'in' and 'out'. In both function and procedure, parameters can be set to 'in', 'out' or 'inout'. I am new to VHDL function/procedure. They do not look like easy. Could you express your idea to help me? Thanks, From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to model an internal state in a function (or a procedure)? Date: Tue, 05 Aug 2014 17:26:19 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 5 Aug 2014 21:26:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="19574"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vK64IzZfBr11Qwjoxoy0i" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Cancel-Lock: sha1:1M9KC3kvyAQcQWoBzmh39lgS7HM= Xref: news.eternal-september.org comp.lang.vhdl:7704 On 8/5/2014 5:01 PM, fl wrote: > Hi, > > After I get helps from several on-line groups, I can calculate a CRC with a VHDL > project. The problem now is that I can get the 16-bit checksum in one time > calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs > two clocks to get a 16-bit CRC checksum. My code originates from a function call, > which is a combination logic (no register), from on-line post. When I modify it to > get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the > internal states for the next iterative CRC calculation (Is this right?) > The function call seems not work in this way (It only output the result, not the > internal states). The CRC problem is just like an integer division. I have to > store the residue and the new divisor (dividend is polynomial, constant in this > case). It looks like the residue must have attribute of 'in' and 'out'. In both > function and procedure, parameters can be set to 'in', 'out' or 'inout'. > > I am new to VHDL function/procedure. They do not look like easy. Could you express > your idea to help me? Thanks, Are you new to HDL in general? HDL means Hardware Description Language. There are no small number of designers who use HDL as a language and don't bother considering what hardware will be produced which can work perfectly well. In this case I think looking at what hardware you wish to produce will do you wonders. A CRC is not a complex function. It is just a register and a few exclusive or gates (XOR). The only trick is knowing what to connect to what with the XOR gates. Your function can be written to describe the XOR gates and be purely combinatorial. Then you can connect it to your inputs and a register and Bob's your uncle! Try starting with a very simple CRC that you have example data for testing. It will be much easier to see what is happening. -- Rick From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.50.103.66 with SMTP id fu2mr1838056igb.7.1407284665451; Tue, 05 Aug 2014 17:24:25 -0700 (PDT) X-Received: by 10.50.66.135 with SMTP id f7mr224941igt.3.1407284665366; Tue, 05 Aug 2014 17:24:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no9297839igc.0!news-out.google.com!px9ni584igc.0!nntp.google.com!h18no14729262igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 5 Aug 2014 17:24:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help for function calling From: Dio Gratia Injection-Date: Wed, 06 Aug 2014 00:24:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7705 On Wednesday, August 6, 2014 3:26:11 AM UTC+12, Daniel Kho wrote: > Just adding to what others have said. You need to declare the function > crc_shift0 at the package declarative area as well, since you have that function > in the package body and intend to use it. Err, no, not necessarily. A declaration in a package declaration makes the function visible through a use statement. (i.e. use work.package.all;) while the function is directly visible in the package body by through the function's subprogram body. The effect of not having the function declared in the package declaration is to make it private (only visible) to the package body. You can find examples for both locally visible functions and declarations in package std_logic_1164's body. IEEE Std 1076-2008, 4.3 Subprogram bodies, para 8: "The declaration of a subprogram is optional. In the absence of such a declaration, the subprogram specification of the subprogram body acts as the declaration. For each subprogram declaration, there shall be a corresponding body. If both a declaration and a body are given, the subprogram specification of the body shall lexically conform (see 4.10) to the subprogram specification of the declaration. Furthermore, both the declaration and the body shall occur immediately within the same declarative region (see 12.1)." Which also tells us a function declaration within the package body has to match the function body. 4.7 Package declarations, para 1: "A package declaration defines the interface to a package. The scope of a declaration within a package can be extended to other design units or to other parts of the design unit containing the package declaration." 12.4 Use clauses, para 1 - 3: "A use clause achieves direct visibility of declarations that are visible by selection. use_clause ::= use selected_name { , selected_name } ; Each selected name in a use clause identifies one or more declarations that will potentially become directly visible. If the suffix of the selected name is a simple name other than a type mark, or is a character literal or operator symbol, then the selected name identifies only the declaration(s) of that simple name, character literal, or operator symbol contained within the package or library denoted by the prefix of the selected name." 12.4 para 3: "If the suffix is the reserved word all, then the selected name identifies all declarations that are contained within the package or library denoted by the prefix of the selected name." (Which tells us that .all at the end of a use clause makes all the declarations in a package visible.) 12.3 Visibility, para 2, excerpted: "For each identifier and at each place in the text, the visibility rules determine a set of declarations (with this identifier) that define the possible meanings of an occurrence of the identifier. A declaration is said to be visible at a given place in the text when, according to the visibility rules, the declaration defines a possible meaning of this occurrence. ..." In this specific case crc_shift0 isn't visible outside crc_package, and the case presented by fi only shows it called from function crc_shift inside the crc_package body where it is visible. It only has to be declared in the crc_package declaration if it is required to be visible externally. > Make sure the subprogram "signature" is the same for both the declarative region > and the body. E.g. if you declared your subprogram to return an 'unsigned(15 > downto 0)', then to be consistent, you should use the same return type in your > subprogram specification (the one in the package body). And a return type declaration in a function declaration may not contain a subtype indication, the previously quoted EBNF in another comment is normative. Both of these and require extensive reading of the standard (and is the more difficult in the -2008 version of the standard) or can be demonstrated by simple experimentation. Those of us who don't trust tools to be right do both. The VHDL language standard is large enough those of us trying to make authoritative statements tend to keep it to hand. It's too big to keep in your head (short term memory is the first to go), which is why over time tool error messages improve. (And if I hadn't checked yesterday before a previous comment I might not have raised the issues, I too saw there was no declaration in the package and checked why. I had a tool complain about a subtype indication on the function return, but also noted fi had corrected it when presenting the entire package.) From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.66.66.196 with SMTP id h4mr6326010pat.22.1407346084150; Wed, 06 Aug 2014 10:28:04 -0700 (PDT) X-Received: by 10.140.19.213 with SMTP id 79mr225463qgh.5.1407346084057; Wed, 06 Aug 2014 10:28:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no9564679igc.0!news-out.google.com!b3ni5177qac.1!nntp.google.com!j15no5051844qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 6 Aug 2014 10:28:03 -0700 (PDT) In-Reply-To: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <5a2b7669-7dc8-416c-a820-0610903e7629@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d552a7c-d128-46ab-beb5-a61053b3eedb@googlegroups.com> Subject: Re: How to model an internal state in a function (or a procedure)? From: Andy Injection-Date: Wed, 06 Aug 2014 17:28:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7706 I use a procedure with an inout variable parameter for the CRC value, and an in parameter for the data to be CRC'd (bit, byte, word, block, etc.) Just initialize the crc variable once, and then call the procecure with (data, crc) each time you get new data, and it will update the crc variable each time. Because it can be written to accept an entire block of data (unconstrained array of bytes), such a procedure can be very useful in testbenches too. Andy From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.224.169.20 with SMTP id w20mr8659673qay.4.1407402152625; Thu, 07 Aug 2014 02:02:32 -0700 (PDT) X-Received: by 10.50.134.3 with SMTP id pg3mr220211igb.4.1407402152409; Thu, 07 Aug 2014 02:02:32 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j15no5250987qaq.0!news-out.google.com!eg1ni559igc.0!nntp.google.com!h18no15482919igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 Aug 2014 02:02:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.149.108; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.149.108 References: <7597c8aa-cb96-4a2d-afff-36c827fe9fc0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ba6d987-c0dc-482e-ad6d-a9b95290a9b6@googlegroups.com> Subject: Re: Help for function calling From: Daniel Kho Injection-Date: Thu, 07 Aug 2014 09:02:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2984 X-Received-Body-CRC: 658536411 Xref: news.eternal-september.org comp.lang.vhdl:7707 On Wednesday, 6 August 2014 08:24:24 UTC+8, Dio Gratia wrote: > On Wednesday, August 6, 2014 3:26:11 AM UTC+12, Daniel Kho wrote: >=20 >=20 >=20 > > Just adding to what others have said. You need to declare the function >=20 > > crc_shift0 at the package declarative area as well, since you have that= function >=20 > > in the package body and intend to use it. >=20 >=20 >=20 > Err, no, not necessarily. A declaration in a package declaration makes th= e >=20 > function visible through a use statement. (i.e. use work.package.all;) wh= ile the >=20 > function is directly visible in the package body by through the function'= s >=20 > subprogram body. The effect of not having the function declared in the pa= ckage >=20 > declaration is to make it private (only visible) to the package body. You= can find >=20 > examples for both locally visible functions and declarations in package >=20 > std_logic_1164's body. Yes, I agree. However, I was not speaking strictly from the LRM - instead I= was speaking based on the OP's intention. From what I guess, the OP intend= s to use the subprogram outside of the package body (i.e. probably use it i= n a real design, whose entity-architecture is probably in another file). Defining a subprogram within the package body but not in the package declar= ative part will not give you any errors (IINM), but that makes the subprogr= am private to the package body (as what you've mentioned) and you can't use= the subprogram outside of the package. I think the intent of the OP is eventually to be able to use the subprogram= outside of the package body. -dan From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.236.125.33 with SMTP id y21mr7885471yhh.20.1407584567466; Sat, 09 Aug 2014 04:42:47 -0700 (PDT) X-Received: by 10.50.97.74 with SMTP id dy10mr238180igb.1.1407584567329; Sat, 09 Aug 2014 04:42:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j15no5737236qaq.0!news-out.google.com!px9ni588igc.0!nntp.google.com!h18no16810525igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 Aug 2014 04:42:46 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=27.116.16.2; posting-account=8oA8ZwoAAAC66CVHtm8hS6fyjFuhccs0 NNTP-Posting-Host: 27.116.16.2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <508fbfc8-9bc6-4a95-ad91-2ed290c02ac2@googlegroups.com> Subject: isc books From: vaasuisc@gmail.com Injection-Date: Sat, 09 Aug 2014 11:42:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: news.eternal-september.org comp.lang.vhdl:7708 Are you looking for best isc books, then central books online is a best online book store where you can find all types of text books and competitive books. http://www.centralbooksonline.com/categories/School-Books-ISC/cid-CU00113788.aspx From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.66.66.46 with SMTP id c14mr3053682pat.21.1407865021622; Tue, 12 Aug 2014 10:37:01 -0700 (PDT) X-Received: by 10.140.36.66 with SMTP id o60mr28032qgo.28.1407865021515; Tue, 12 Aug 2014 10:37:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h18no12181193igc.0!news-out.google.com!j6ni43193qas.0!nntp.google.com!v10no6524370qac.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Aug 2014 10:37:01 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.35 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Combinatorial logic causing delta impulse From: "V." Injection-Date: Tue, 12 Aug 2014 17:37:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7709 I have sig1 and sig2 that are both driven by a synchronous process. I have a line of combinatorial logic that simply checks that both are high: out <= sig1 and sig2. In my ModelSim simulation, at the moment of the falling edge of sig1 and rising edge of sig2, I see the "out" signal pulse high just for only one delta delay cycle. I assume there's a moment in time while sig1 is falling and sig2 is rising that the simulator thinks they are both high? I am not sure if this only exists in simulation environment or will it propagate to my real world implementation? How can I prevent it in simulation? Thanks for your guidance. Regards, V. From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Combinatorial logic causing delta impulse Date: Tue, 12 Aug 2014 17:53:30 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 34 Message-ID: References: Injection-Date: Tue, 12 Aug 2014 17:53:30 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="7935"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EUUTwYinmlq1h8zMrA6lW" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:G8m1xg56QUT9VFwegYT3/91GGoU= Xref: news.eternal-september.org comp.lang.vhdl:7710 In article , V. wrote: >I have sig1 and sig2 that are both driven by a synchronous process. > >I have a line of combinatorial logic that simply checks that both are high: > >out <= sig1 and sig2. > >In my ModelSim simulation, at the moment of the falling edge of sig1 and >rising edge of sig2, I see the "out" signal pulse high just for only one >delta delay cycle. > >I assume there's a moment in time while sig1 is falling and sig2 is rising >that the simulator thinks they are both high? > >I am not sure if this only exists in simulation environment or will it >propagate to my real world implementation? How can I prevent it in simulation? Think it through more V, as it'll happen in the real world. The signals "sig1" and "sig2" are never going to have exactly matched delays. So of course in the real world perhaps "sig1" rises just a few moments before "sig2" falls. What do you get? - a glitch. Do you care? Not if you've followed proper synchronous design principles. You registers up the "out" signal one period later after everything's settled. As to the sim - again, do you care? It's a reprsentative model of what could happen in the real circuit. It's ok, no need to "prevent it in simulation". Regards, Mark From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.42.188.84 with SMTP id cz20mr900337icb.1.1407881550572; Tue, 12 Aug 2014 15:12:30 -0700 (PDT) X-Received: by 10.51.18.100 with SMTP id gl4mr49013igd.6.1407881550443; Tue, 12 Aug 2014 15:12:30 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h18no19143979igc.0!news-out.google.com!px9ni620igc.0!nntp.google.com!h18no12303560igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 12 Aug 2014 15:12:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <016d4ba9-e0cc-4201-896f-76f9ea5d12d9@googlegroups.com> Subject: Re: Combinatorial logic causing delta impulse From: Dio Gratia Injection-Date: Tue, 12 Aug 2014 22:12:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3410 X-Received-Body-CRC: 1291961352 Xref: news.eternal-september.org comp.lang.vhdl:7711 On Wednesday, August 13, 2014 5:37:01 AM UTC+12, V. wrote: > > How can I prevent it in simulation? >=20 As Mark notes it can occur in the real world. However if you never use a v= ulnerable combinatorial product as a latch enable or clock it has no meanin= g other than difference in propagation times of the inputs in delta cycles = to the expression and you can prevent it simulation. That difference in p= ropagation time can match differences in gate delays, travel times or risin= g/falling edge times in actual hardware. You could also note that in a zero timed model it tells you one of your syn= chronous processes is either using a delta delayed clock or already has a c= ombinatorial expression on a sequential storage element's output. To prevent a delta cycle impulse from propagating look to signal assignment= : signal_assignment_statement ::=3D [ label : ] target <=3D [ delay_mechanism ] waveform ; delay_mechanism ::=3D transport | [ reject time_expression ] inertial target ::=3D name | aggregate waveform ::=3D waveform_element { , waveform_element } | unaffected Where you'd use inertial impulse rejection with a time expression set to th= e smallest unit of the resolution limit selected primary or secondary time = unit (without setting the resolution limit that would be 1 fs, the default = resolution limit set to femto-second). The idea here is to prevent an impu= lse rejection interval of 0 which happens to match a delta cycle delay. Such a signal assignment should have the delay mechanism ignored by synthes= is. A rule of thumb should be to never rely on inertial rejection to insure pro= per operation of a model. =20 I recall issues we had in the late '70s and early '80s with silicon being t= oo fast, sub nanosecond gate delays in 74LSXX MSI from Japanese vendors and= AMD having DRAM with almost zero holdover on Data Out from CAS invalid. M= ixing things with different propagation delays can result in unforeseen com= plications.=20 The same sort of effects can occur on silicon devices, and the same synchro= nous design rules are used as cures. From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.182.60.36 with SMTP id e4mr27180350obr.3.1408547089854; Wed, 20 Aug 2014 08:04:49 -0700 (PDT) X-Received: by 10.140.98.243 with SMTP id o106mr17334qge.17.1408547089784; Wed, 20 Aug 2014 08:04:49 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no3552010igi.0!news-out.google.com!q8ni661qal.1!nntp.google.com!m5no1395486qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Aug 2014 08:04:49 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> Subject: VHDL 2008 - how to declare 2nd dimension for array where 1st dimension is already constrained? From: Tricky Injection-Date: Wed, 20 Aug 2014 15:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7712 so I have this type definition: type slv_array4_t is array(0 to 3) of std_logic_vector; but when I try this: signal some_thing : slv_array4_t(7 downto 0); I get this error from VCOM: ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained. I get the same error when I try signal some_thing : slv_array4_t(0 to 3)(7 downto 0); It has no problem compiling the type delcaration. So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?) From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.52.174.178 with SMTP id bt18mr9443982vdc.1.1408548651691; Wed, 20 Aug 2014 08:30:51 -0700 (PDT) X-Received: by 10.140.21.175 with SMTP id 44mr35609qgl.14.1408548651656; Wed, 20 Aug 2014 08:30:51 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i13no1402351qae.1!news-out.google.com!j6ni3084qas.0!nntp.google.com!i13no1402350qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 Aug 2014 08:30:51 -0700 (PDT) In-Reply-To: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <33ec8e85-78e5-4a05-9326-47012f4f94a0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 - how to declare 2nd dimension for array where 1st dimension is already constrained? From: Tricky Injection-Date: Wed, 20 Aug 2014 15:30:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7713 On Wednesday, 20 August 2014 16:04:49 UTC+1, Tricky wrote: > so I have this type definition: > > > > type slv_array4_t is array(0 to 3) of std_logic_vector; > > > > but when I try this: > > > > signal some_thing : slv_array4_t(7 downto 0); > > > > I get this error from VCOM: > > > > ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained. > > > > I get the same error when I try > > > > signal some_thing : slv_array4_t(0 to 3)(7 downto 0); > > > > It has no problem compiling the type delcaration. > > > > So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?) Sorry to bother you all - some light reading (2008 LRM) showed me it should be: signal some_thing : slv_array4_t(open)(7 downto 0); From newsfish@newsfish Tue Dec 29 16:43:31 2015 X-Received: by 10.236.126.103 with SMTP id a67mr7557216yhi.4.1408800718596; Sat, 23 Aug 2014 06:31:58 -0700 (PDT) X-Received: by 10.50.85.7 with SMTP id d7mr109056igz.9.1408800718456; Sat, 23 Aug 2014 06:31:58 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no2203006qae.1!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no5576841igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 06:31:58 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 13:31:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1660 X-Received-Body-CRC: 2376887552 Xref: news.eternal-september.org comp.lang.vhdl:7714 Please help me out with this code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity comple2 is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); end comple2; architecture Behavioral of comple2 is signal D : out STD_LOGIC_VECTOR (3 downto 0); begin D <= (not a); b <= D + "0001"; end Behavioral; i am getting this error ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) From newsfish@newsfish Tue Dec 29 16:43:31 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Sat, 23 Aug 2014 12:24:18 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 23 Aug 2014 16:24:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20995"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2TsQEo1HAU5gnLoMHzohq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:EAmcnzrVH+/Zeh40LjxOvbxeNCY= Xref: news.eternal-september.org comp.lang.vhdl:7715 On 8/23/2014 9:31 AM, Gaurav Agarwal wrote: > Please help me out with this code > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > library UNISIM; > use UNISIM.VComponents.all; > > entity comple2 is > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > b : out STD_LOGIC_VECTOR (3 downto 0)); > end comple2; > > architecture Behavioral of comple2 is > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > begin > > D <= (not a); > b <= D + "0001"; > > end Behavioral; > > > i am getting this error > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) > Your signal declaration should not include the keyword "out". -- Rick From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.52.174.178 with SMTP id bt18mr7774817vdc.1.1408812476429; Sat, 23 Aug 2014 09:47:56 -0700 (PDT) X-Received: by 10.50.114.69 with SMTP id je5mr126151igb.1.1408812476326; Sat, 23 Aug 2014 09:47:56 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no2248829qaj.0!news-out.google.com!ef6ni1igb.0!nntp.google.com!uq10no3976915igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 09:47:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45d893a5-5c7f-45da-94bb-62ee1b964bec@googlegroups.com> Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 16:47:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2244 X-Received-Body-CRC: 2451801752 Xref: news.eternal-september.org comp.lang.vhdl:7716 On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote: > Please help me out with this code > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.NUMERIC_STD.ALL; > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity comple2 is > > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > > b : out STD_LOGIC_VECTOR (3 downto 0)); > > end comple2; > > > > architecture Behavioral of comple2 is > > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > > > begin > > > > D <= (not a); > > b <= D + "0001"; > > > > end Behavioral; > > > > > > i am getting this error > > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) if i remove out keyword then its showing an error ERROR:HDLParsers:808 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. + can not have such operands in this context. line 43 is the operation on port b From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.182.246.70 with SMTP id xu6mr8145072obc.31.1408817966474; Sat, 23 Aug 2014 11:19:26 -0700 (PDT) X-Received: by 10.50.57.71 with SMTP id g7mr131589igq.13.1408817966380; Sat, 23 Aug 2014 11:19:26 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no4018166igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no5741111igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 11:19:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Sat, 23 Aug 2014 18:19:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7717 On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote: > Please help me out with this code > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.NUMERIC_STD.ALL; > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity comple2 is > > Port ( a : in STD_LOGIC_VECTOR (3 downto 0); > > b : out STD_LOGIC_VECTOR (3 downto 0)); > > end comple2; > > > > architecture Behavioral of comple2 is > > signal D : out STD_LOGIC_VECTOR (3 downto 0); > > > > begin > > > > D <= (not a); > > b <= D + "0001"; > > > > end Behavioral; > > > > > > i am getting this error > > ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'. > > ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block) lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!fdn.fr!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed3-a.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Sat, 23 Aug 2014 23:27:52 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 11 Message-ID: <53f90758$0$2007$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Aug 2014 23:27:52 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408829272 news-1.free.fr 2007 88.185.146.198:2427 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7718 Le 23/08/2014 20:19, Gaurav Agarwal a écrit : > lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. Learn how to use the numeric_std package instead. Declare your ports and signal as unsigned instead of std_logic_vector, you will even be able to write "b <= d + 1;" Nicolas From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.182.28.102 with SMTP id a6mr9371273obh.44.1408840057963; Sat, 23 Aug 2014 17:27:37 -0700 (PDT) X-Received: by 10.140.105.52 with SMTP id b49mr260653qgf.3.1408840057864; Sat, 23 Aug 2014 17:27:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!r2no5921908igi.0!news-out.google.com!j6ni7969qas.0!nntp.google.com!i13no2345261qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 Aug 2014 17:27:37 -0700 (PDT) In-Reply-To: <53f90758$0$2007$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <53f90758$0$2007$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Undefined Symbol error 3312 and 1209 From: Andy Injection-Date: Sun, 24 Aug 2014 00:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7719 On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: > Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages. Andy From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed4-a.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Mon, 25 Aug 2014 00:33:12 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 12 Message-ID: <53fa6828$0$2066$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Aug 2014 00:33:12 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408919592 news-3.free.fr 2066 88.185.146.198:2482 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7720 Le 24/08/2014 02:27, Andy a écrit : > On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: >> Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. > > Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages. Oh no no no no no no (shakes head) Well, technically yes you could but as a fierce advocate of strong typing, I can not support this heresy ;o) Nicolas From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Sun, 24 Aug 2014 18:59:51 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <53f90758$0$2007$426a74cc@news.free.fr> <53fa6828$0$2066$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 24 Aug 2014 22:59:57 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11656"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+SFnOBZwEqs+sCk9/rnQhp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <53fa6828$0$2066$426a74cc@news.free.fr> Cancel-Lock: sha1:9T/MsTxmyxVIlzbBTrf8FdEtkJk= Xref: news.eternal-september.org comp.lang.vhdl:7721 On 8/24/2014 6:33 PM, Nicolas Matringe wrote: > Le 24/08/2014 02:27, Andy a écrit : >> On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote: >>> Terrible mistake. Thou shalt not use the std_logic_* arithmetic >>> packages. >> >> Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. >> Then you can perform unsigned arithmetic on SLVs (with SLV or >> naturals), using an OFFICIAL package, rather than the >> synopsys-developed non-standard packages. > > Oh no no no no no no (shakes head) > Well, technically yes you could but as a fierce advocate of strong > typing, I can not support this heresy ;o) Is there some advantage to such strong typing? I think the active word in "strong typing" is "typing". There is far too much of it in VHDL. I'm happy with a few very clear, well defined *short* cuts. Actually these short cuts don't have anything to do with strong typing. The library simply defines an operator which uses the appropriate types on its inputs and output. What's wrong with that? -- Rick From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.122.101 with SMTP id lr5mr14614898pab.19.1408982076204; Mon, 25 Aug 2014 08:54:36 -0700 (PDT) X-Received: by 10.50.29.13 with SMTP id f13mr380957igh.15.1408982076101; Mon, 25 Aug 2014 08:54:36 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no4870071igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no7010298igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 Aug 2014 08:54:35 -0700 (PDT) In-Reply-To: <53f90758$0$2007$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=150.129.65.105; posting-account=gZGhxwoAAACah1cEfYemoWcb8yVumWC_ NNTP-Posting-Host: 150.129.65.105 References: <53f90758$0$2007$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> Subject: Re: Undefined Symbol error 3312 and 1209 From: Gaurav Agarwal Injection-Date: Mon, 25 Aug 2014 15:54:36 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7722 On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: > Le 23/08/2014 20:19, Gaurav Agarwal a =EF=BF=BDcrit : >=20 >=20 >=20 > > lol! i removed the keyword out and then used the package STD_LOGIC_UNSI= GNED.ALL and it worked! >=20 >=20 >=20 > Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. >=20 > Learn how to use the numeric_std package instead. Declare your ports and= =20 >=20 > signal as unsigned instead of std_logic_vector, you will even be able to= =20 >=20 > write "b <=3D d + 1;" >=20 >=20 >=20 > Nicolas can you please give the exact code using the numeric_std package? From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Mon, 25 Aug 2014 21:40:48 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> In-Reply-To: <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 37 Message-ID: <53fb9140$0$2224$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 25 Aug 2014 21:40:48 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1408995648 news-3.free.fr 2224 88.185.146.198:4379 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7723 Le 25/08/2014 17:54, Gaurav Agarwal a écrit : > On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: >> Le 23/08/2014 20:19, Gaurav Agarwal a �crit : >>> lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked! >> >> Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages. >> Learn how to use the numeric_std package instead. Declare your ports and >> signal as unsigned instead of std_logic_vector, you will even be able to >> write "b <= d + 1;" > can you please give the exact code using the numeric_std package? I can library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity comple2 is Port ( a : in unsigned (3 downto 0); b : out unsigned (3 downto 0)); end comple2; architecture Behavioral of comple2 is signal D : out unsigned (3 downto 0); begin D <= (not a); b <= D + 1; end Behavioral; Just as I said, use unsigned instead of std_logic_vector. There's no need to use the intermediate signal D, you can do it all in a single expression, BTW. Nicolas From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 Date: Mon, 25 Aug 2014 16:42:09 -0400 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> <53fb9140$0$2224$426a74cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 25 Aug 2014 20:42:15 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="29248"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18gpQNOrhRcaskYxF/rQskb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <53fb9140$0$2224$426a74cc@news.free.fr> Cancel-Lock: sha1:iYKfmE65w8XoEmd63PxuzQGwFEo= Xref: news.eternal-september.org comp.lang.vhdl:7724 On 8/25/2014 3:40 PM, Nicolas Matringe wrote: > Le 25/08/2014 17:54, Gaurav Agarwal a écrit : >> On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote: >>> Le 23/08/2014 20:19, Gaurav Agarwal a �crit : >>>> lol! i removed the keyword out and then used the package >>>> STD_LOGIC_UNSIGNED.ALL and it worked! >>> >>> Terrible mistake. Thou shalt not use the std_logic_* arithmetic >>> packages. >>> Learn how to use the numeric_std package instead. Declare your ports and >>> signal as unsigned instead of std_logic_vector, you will even be able to >>> write "b <= d + 1;" >> can you please give the exact code using the numeric_std package? > > I can > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > library UNISIM; > use UNISIM.VComponents.all; > > entity comple2 is > Port ( a : in unsigned (3 downto 0); > b : out unsigned (3 downto 0)); > end comple2; > > architecture Behavioral of comple2 is > signal D : out unsigned (3 downto 0); > begin > D <= (not a); > b <= D + 1; > end Behavioral; > > Just as I said, use unsigned instead of std_logic_vector. > > There's no need to use the intermediate signal D, you can do it all in a > single expression, BTW. > > Nicolas You used "out" in your signal declaration for D. Was that intentional? -- Rick From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.42.188.84 with SMTP id cz20mr20661589icb.1.1409053255974; Tue, 26 Aug 2014 04:40:55 -0700 (PDT) X-Received: by 10.182.131.166 with SMTP id on6mr10097obb.24.1409053255845; Tue, 26 Aug 2014 04:40:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5245789igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no7599374igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Aug 2014 04:40:55 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.21.194.1; posting-account=l6FnUwoAAAA4GdhVUFXsD7A1E1w5GF9Z NNTP-Posting-Host: 125.21.194.1 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: JK Injection-Date: Tue, 26 Aug 2014 11:40:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7725 http://en.wikipedia.org/wiki/Linear_feedback_shift_register#Galois_LFSRs From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.119.174 with SMTP id kv14mr19002109pab.23.1409077367443; Tue, 26 Aug 2014 11:22:47 -0700 (PDT) X-Received: by 10.50.79.201 with SMTP id l9mr594112igx.5.1409077367297; Tue, 26 Aug 2014 11:22:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no5432791igb.0!news-out.google.com!ef6ni1igb.0!nntp.google.com!uq10no5432790igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 Aug 2014 11:22:46 -0700 (PDT) In-Reply-To: <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.186; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.186 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> <3d5d93f3-e32f-476b-a086-66abb97e5b12@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How can I design Galois field 2^m multiplier. From: Daniel Kho Injection-Date: Tue, 26 Aug 2014 18:22:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7726 There's a Galois LFSR project in OpenCores: http://www.opencores.org/project,galois_lfsr It's a simple design, which gives you the ability to "configure" the taps of the LFSR easily. The design will automatically generate the LFSR structure with all the XOR gates accordingly based on the taps you chose (see user.vhdl). E.g.: tapVector:boolean_vector:=( 0|1|2|8=>true, 7 downto 3=>false ) Disclosure: I'm the author of the project, so may have a bias towards it. From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.68.216.231 with SMTP id ot7mr21588648pbc.2.1409138755587; Wed, 27 Aug 2014 04:25:55 -0700 (PDT) X-Received: by 10.50.57.71 with SMTP id g7mr706164igq.13.1409138755430; Wed, 27 Aug 2014 04:25:55 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no8315107igi.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no8315101igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Aug 2014 04:25:54 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <606f6d0f-1a3e-47a8-b6fa-99664bd8cc59@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: Dio Gratia Injection-Date: Wed, 27 Aug 2014 11:25:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7727 On Saturday, June 22, 2013 4:10:25 AM UTC+12, lkp wrote: > Any suggestion will be helpful. There's a gate level representation of a GF(2M) parallel Galois Field multipler in expired patent US 4,918,638, which you can find by googling. In theory a person having ordinary skill in the art is capable of implementing the claimed invention found in a patent. The gate level representation should make it fairly easy to translate into a behavioral representation in VHDL. It looks like it could synthesis pretty compactly as long as you kept it in one process. From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.182.110.130 with SMTP id ia2mr23827229obb.42.1409162625127; Wed, 27 Aug 2014 11:03:45 -0700 (PDT) X-Received: by 10.50.50.97 with SMTP id b1mr113204igo.9.1409162624985; Wed, 27 Aug 2014 11:03:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!news.glorb.com!uq10no5924068igb.0!news-out.google.com!aw9ni2igc.0!nntp.google.com!r2no8558825igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 27 Aug 2014 11:03:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.154.38.111; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 98.154.38.111 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05210d57-2fcc-4177-a328-e408ce00358a@googlegroups.com> Subject: Where can I find the limitations on length of a paper and number of its graphs and other information of JACM From: Weng Tianxiang Injection-Date: Wed, 27 Aug 2014 18:03:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7728 Hi, I am preparing to deliver my first paper to Journal of ACM. I downloaded the format file from http://www.acm.org/publications/word_style/V2-ACM-SMALL-AUGUST-2012.zip through http://www.acm.org/publications/word_style/word-style-toc/ But I cannot find the limitations on length of a paper and number of its graphs and other information, for example, fees for reviewing and publishing. Help please. Weng From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!gegeweb.org!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp3-2.free.fr!not-for-mail Date: Wed, 27 Aug 2014 21:21:10 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Undefined Symbol error 3312 and 1209 References: <53f90758$0$2007$426a74cc@news.free.fr> <009cc3d4-ac69-4280-b973-2dbd6d7793de@googlegroups.com> <53fb9140$0$2224$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 9 Message-ID: <53fe2fa6$0$5102$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 27 Aug 2014 21:21:10 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1409167270 news-2.free.fr 5102 88.185.146.198:1772 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7729 Le 25/08/2014 22:42, rickman a écrit : > You used "out" in your signal declaration for D. Was that intentional? Oops sorry no, I just copy-pasted the orignal code and replaced the types, I forgot to fix this. Nicolas From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.118.195 with SMTP id l43mr11772237yhh.52.1409212391102; Thu, 28 Aug 2014 00:53:11 -0700 (PDT) X-Received: by 10.140.37.39 with SMTP id q36mr13345qgq.10.1409212391022; Thu, 28 Aug 2014 00:53:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no3785414qae.1!news-out.google.com!q8ni3qal.1!nntp.google.com!i13no3785412qae.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 28 Aug 2014 00:53:10 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> Subject: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Thu, 28 Aug 2014 07:53:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: news.eternal-september.org comp.lang.vhdl:7730 Hi, just a message to annouce the first release of a python based documentatiion tool. pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file. pyVhdl2Sch is based on Python and is a rewrite of the QT/Latex based Vhdl2Sch. More details here : https://github.com/LaurentCabaret/pyVhdl2Sch Feel free to criticize/cheers/participate/... Laurent From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch Date: Sat, 30 Aug 2014 18:08:34 +0200 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 30 Aug 2014 16:08:36 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="f0d20ef625634cb49b5e3a4f7535e3a6"; logging-data="27463"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19MC4qKZnuJnVm24c+v7xR3" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> Cancel-Lock: sha1:a+gZHSblb+2i4O/WmUBqrlMbl7o= Xref: news.eternal-september.org comp.lang.vhdl:7731 > pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file. With a little fiddeling on MacOS X (with Macports) it run on my Mac too. Nice work! I did some changes to support signed/unsigned and std_ulogic as data types: /pyVhdl2Sch$ git diff diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py index f9576ca..9933442 100644 --- a/file_manager/vhdl_reader.py +++ b/file_manager/vhdl_reader.py @@ -99,10 +99,10 @@ class Vhdl_reader: if wire_type == "integer": nb_wires = 32 else: - if wire_type == "std_logic": + if wire_type == "std_logic" or wire_type == "std_ulogic": nb_wires = 1 else: - if wire_type == "std_logic_vector": + if wire_type == "std_logic_vector" or wire_type == "std_ulogic_vector" or wire_type == "signed" or wire_type == "unsigned": bus_direction = real_words[5].lower() bus_description = text.split("(")[1].split(")")[0] if bus_direction == "downto": diff --git a/pyV2S.py b/pyV2S.py index 8cccdf0..ced8fd6 100755 --- a/pyV2S.py +++ b/pyV2S.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python # -*- coding: utf-8 -*- Maybe you can enhance the skript to use the data type instead the number of wires for unknown data types? I use a lot of vhdl-recods defined in packages in my projects, so the number of wires is difficult to determine. regards, Bart From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.124.161 with SMTP id x21mr1178651yhh.48.1409429750813; Sat, 30 Aug 2014 13:15:50 -0700 (PDT) X-Received: by 10.50.50.205 with SMTP id e13mr213547igo.17.1409429750717; Sat, 30 Aug 2014 13:15:50 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no4467913qae.1!news-out.google.com!aw9ni2087igc.0!nntp.google.com!r2no10853553igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 30 Aug 2014 13:15:50 -0700 (PDT) In-Reply-To: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch From: Dio Gratia Injection-Date: Sat, 30 Aug 2014 20:15:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4637 X-Received-Body-CRC: 660292156 Xref: news.eternal-september.org comp.lang.vhdl:7732 On Thursday, August 28, 2014 7:53:10 PM UTC+12, Laurent Cabaret wrote: > pyVhdl2Sch is a documentation generator tool.=20 >=20 > Feel free to criticize/cheers/participate/... I noticed your tool doesn't accept the optional keyword signal in an interf= ace signal declaration on the port. interface_signal_declaration ::=3D [ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ := =3D static_expression ] "Ports of any mode are also signals." As you can see the mode is optional a= nd defaults to mode in. Also a subtype indication can be more than a name and an index range: subtype_indication ::=3D [ resolution_indication ] type_mark [ constraint ] resolution_indication ::=3D resolution_function_name | ( element_resolution ) element_resolution ::=3D array_element_resolution | record_resolution=20 array_element_resolution ::=3D resolution_indication record_resolution ::=3D record_element_resolution { , record_element_resolu= tion }=20 record_element_resolution ::=3D record_element_simple_name resolution_indic= ation (These are from IEEE Std 1076-2008). A port signal can be a record, too. A resolution indication can appear wherever there is a driver. This is val= id VHDL code: library ieee; use ieee.std_logic_1164.all; package a_pkg is function x_res (to_resolve: std_logic_vector) return std_ulogic; end a_pkg; package body a_pkg is function x_res (to_resolve: std_logic_vector) return std_ulogic is variable r: std_ulogic; begin r :=3D 'Z'; for i in to_resolve'range loop r :=3D r or to_resolve(i); end loop; return r; end function x_res; end a_pkg; library ieee; use ieee.std_logic_1164.all; use work.a_pkg.all; entity foo is port ( signal a: in std_logic; signal b: in std_logic; signal c: in std_logic; signal p: out x_res std_logic ); end entity; architecture fum of foo is =20 begin=20 p <=3D a; p <=3D b; p <=3D c; end architecture; As you can see there's a resolution function declared and because it's not = an array type or a record type there are no parentheses for an array elemen= t resolution function. A record can have a resolution function for each re= cord element, while there's only one for an array type. I've written schematic symbol generators several times over the years what = your program does isn't a surprise, the geometry familiar. =20 That you discard the subtype indication (index range) limits the use to blo= ck diagrams (for documentation). There's at least one PDF based schematic p= ackage out there (Kicad). It'd likely require your own PDF code generation= to make symbols for it. A three signal port entity generated a 10KB PDF file, you're own PDF code g= eneration could possibly reduce that should you be able to live with a stan= dard embedded font. The issue here is eventually swamping a word processor= by including embedded PDF files accumulating in size. Open Office/Libre Of= fice can slow down with a relatively few large image files, It's the redraw= times. We used to do a lot of PostScript code for this kind of stuff back in the d= ay, PDF can be on par and schematic symbols are about as hard as printing o= verlays on bank checks. You could do PostScript and rely on conversion to = PDF. From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Functional safety guidelines Date: Sun, 31 Aug 2014 23:15:43 +0100 Organization: A noiseless patient Spider Lines: 9 Sender: scrts@86-46-55-11-dynamic.b-ras3.mvw.galway.eircom.net Message-ID: Injection-Date: Sun, 31 Aug 2014 22:15:43 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="64c1fb06d5a3d01683a0def5ebfea7bc"; logging-data="8927"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19HMVtV35ZJoak9638OOq9V" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:tEYcDgWkFyhiWkbWERK86hV1LrQ= X-Priority: 3 X-MSMail-Priority: Normal Xref: news.eternal-september.org comp.arch.fpga:20956 comp.lang.vhdl:7733 Hello, I wonder maybe someone have automotive functional safety guidelines for VHDL and is willing to share? I think there's a package available from Altera, however they charge 10k for it telling that it is a small fee. Thank you. From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Functional safety guidelines Date: Mon, 01 Sep 2014 12:35:03 +0200 Organization: A noiseless patient Spider Lines: 22 Sender: ttobsen@109.192.229.0 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 1 Sep 2014 10:32:54 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="29485"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Jkumt4AtGLNtXzHGbrkqk" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.0 In-Reply-To: Cancel-Lock: sha1:TkQAohE/tn4MaQSsCSNgghMY8Kg= Xref: news.eternal-september.org comp.arch.fpga:20957 comp.lang.vhdl:7734 Am 01.09.2014 um 00:15 schrieb Tomas D.: > Hello, > I wonder maybe someone have automotive functional safety guidelines for VHDL > and is willing to share? > I think there's a package available from Altera, however they charge 10k for > it telling that it is a small fee. > > Thank you. > > Hi, maybe this one is something for you: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5712336&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5712336 It's not specially for automotive and not very informative, but maybe a first idea. Best regards, Tobias From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Functional safety guidelines Date: Mon, 01 Sep 2014 11:43:50 -0700 Organization: Aioe.org NNTP Server Lines: 17 Message-ID: References: NNTP-Posting-Host: D2xim2E4ibZVr1KRe9nhXg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.arch.fpga:20958 comp.lang.vhdl:7735 On 8/31/2014 3:15 PM, Tomas D. wrote: > Hello, > I wonder maybe someone have automotive functional safety guidelines for VHDL > and is willing to share? > I think there's a package available from Altera, however they charge 10k for > it telling that it is a small fee. > > Thank you. > It's not automotive - but the aerospace industry uses RTCA DO-254. http://en.wikipedia.org/wiki/DO-254 Rob. From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.137.68 with SMTP id qg4mr1905747pab.26.1409619666548; Mon, 01 Sep 2014 18:01:06 -0700 (PDT) X-Received: by 10.50.18.17 with SMTP id s17mr399705igd.10.1409619666398; Mon, 01 Sep 2014 18:01:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no12471935igi.0!news-out.google.com!aw9ni2087igc.0!nntp.google.com!r2no12471922igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Sep 2014 18:01:05 -0700 (PDT) In-Reply-To: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.254.107.224; posting-account=nsU3EAoAAAAqf5vHnuMw9q7IBuQvH8VA NNTP-Posting-Host: 117.254.107.224 References: <439a9ca0-3e1e-439b-bd1a-a042970b21fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <09afe5ea-576f-4ba3-b0a7-d292912f52e9@googlegroups.com> Subject: Re: How can I design Galois field 2^m multiplier. From: "saranyaece1991@gmail.c" Injection-Date: Tue, 02 Sep 2014 01:01:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7736 HI sir/madam i m doing the project in galois field multiplier.I want to design Galois field 2^m multiplier. I want to start with Galois field 8 bit and then m bit multiplier. So please help me. From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.190.67 with SMTP id go3mr18290596pac.10.1409643952501; Tue, 02 Sep 2014 00:45:52 -0700 (PDT) X-Received: by 10.140.96.228 with SMTP id k91mr11104qge.23.1409643952409; Tue, 02 Sep 2014 00:45:52 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!r2no12638352igi.0!news-out.google.com!q8ni9qal.1!nntp.google.com!m5no5107104qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Sep 2014 00:45:52 -0700 (PDT) In-Reply-To: <565bc83c-554b-47b6-bb27-4afcfa69404c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <565bc83c-554b-47b6-bb27-4afcfa69404c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <61dd5d3e-2a3c-440c-875f-2ba1158fddb7@googlegroups.com> Subject: Re: coverage collection From: hssig Injection-Date: Tue, 02 Sep 2014 07:45:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1242 X-Received-Body-CRC: 3197265935 Xref: news.eternal-september.org comp.lang.vhdl:7737 You could use stimulus coverage and DUT response coverage. Both together form the overall coverage. Cheers, hssig From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.87.46 with SMTP id x34mr5025755yhe.49.1409755803419; Wed, 03 Sep 2014 07:50:03 -0700 (PDT) X-Received: by 10.140.16.15 with SMTP id 15mr114012qga.3.1409755803403; Wed, 03 Sep 2014 07:50:03 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no841978qab.1!news-out.google.com!q8ni8qal.1!nntp.google.com!dc16no841973qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Sep 2014 07:50:03 -0700 (PDT) In-Reply-To: <5503c066.0210280120.f156642@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.254.184.22; posting-account=2KCQkAoAAACG5ZNZmVQsYiVsFxE0lpF9 NNTP-Posting-Host: 37.254.184.22 References: <5503c066.0210280120.f156642@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c5b6b8d-45d2-41bc-8560-2ca4cbc7c86b@googlegroups.com> Subject: Re: vhdl code for a 16x8 bit dual port ram From: mahdihatamigh61@gmail.com Injection-Date: Wed, 03 Sep 2014 14:50:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7738 On Monday, October 28, 2002 12:50:09 PM UTC+3:30, ameya wrote: > I need the code for the dual port ram. a single 8 bit will do . if i > have for a 16x8 then its very nice of u. the specs are : > > If data is to be written from both sides thne priority has to be > assigned to one side. Simultaneous read & write from same location > results in corect data being writen into the memory but invalid data > presented at reading port. simultaneous reads from the same location > allowed. ------------------------------------------------------- 2 -- Design Name : ram_dp_ar_aw 3 -- File Name : ram_dp_ar_aw.vhd 4 -- Function : Asynchronous read write RAM 5 -- Coder : Deepak Kumar Tala (Verilog) 6 -- Translator : Alexander H Pham (VHDL) 7 ------------------------------------------------------- 8 library ieee; 9 use ieee.std_logic_1164.all; 10 use ieee.std_logic_unsigned.all; 11 12 entity ram_dp_ar_aw is 13 generic ( 14 DATA_WIDTH :integer := 8; 15 ADDR_WIDTH :integer := 8 16 ); 17 port ( 18 address_0 :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_0 Input 19 data_0 :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_0 bi-directional 20 cs_0 :in std_logic; -- Chip Select 21 we_0 :in std_logic; -- Write Enable/Read Enable 22 oe_0 :in std_logic; -- Output Enable 23 address_1 :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_1 Input 24 data_1 :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_1 bi-directional 25 cs_1 :in std_logic; -- Chip Select 26 we_1 :in std_logic; -- Write Enable/Read Enable 27 oe_1 :in std_logic -- Output Enable 28 ); 29 end entity; 30 architecture rtl of ram_dp_ar_aw is 31 ----------------Internal variables---------------- 32 33 constant RAM_DEPTH :integer := 2**ADDR_WIDTH; 34 35 signal data_0_out :std_logic_vector (DATA_WIDTH-1 downto 0); 36 signal data_1_out :std_logic_vector (DATA_WIDTH-1 downto 0); 37 38 type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); 39 signal mem : RAM (0 to RAM_DEPTH-1); 40 begin 41 42 ----------------Code Starts Here------------------ 43 -- Memory Write Block 44 -- Write Operation : When we_0 = 1, cs_0 = 1 45 MEM_WRITE: 46 process (address_0, cs_0, we_0, data_0, address_1, cs_1, we_1, data_1) begin 47 if (cs_0 = '1' and we_0 = '1') then 48 mem(conv_integer(address_0)) <= data_0; 49 elsif (cs_1 = '1' and we_1 = '1') then 50 mem(conv_integer(address_1)) <= data_1; 51 end if; 52 end process; 53 54 -- Tri-State Buffer control 55 data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z'); 56 57 -- Memory Read Block 58 MEM_READ_0: 59 process (address_0, cs_0, we_0, oe_0, mem) begin 60 if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then 61 data_0_out <= mem(conv_integer(address_0)); 62 else 63 data_0_out <= (others=>'0'); 64 end if; 65 end process; 66 67 -- Second Port of RAM 68 -- Tri-State Buffer control 69 data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z'); 70 71 -- Memory Read Block 1 72 MEM_READ_1: 73 process (address_1, cs_1, we_1, oe_1, mem) begin 74 if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then 75 data_1_out <= mem(conv_integer(address_1)); 76 else 77 data_1_out <= (others=>'0'); 78 end if; 79 end process; 80 81 end architecture; From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.182.191.36 with SMTP id gv4mr538864obc.50.1409756021328; Wed, 03 Sep 2014 07:53:41 -0700 (PDT) X-Received: by 10.140.43.166 with SMTP id e35mr21069qga.27.1409756021252; Wed, 03 Sep 2014 07:53:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no13597452igi.0!news-out.google.com!q8ni8qal.1!nntp.google.com!dc16no842837qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Sep 2014 07:53:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.254.184.22; posting-account=2KCQkAoAAACG5ZNZmVQsYiVsFxE0lpF9 NNTP-Posting-Host: 37.254.184.22 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Subject: image median filter From: mahdihatamigh61@gmail.com Injection-Date: Wed, 03 Sep 2014 14:53:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7739 hi How to program filter the salt- pepper noise of image From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.216.67 with SMTP id f63mr10932827yhp.10.1409759945086; Wed, 03 Sep 2014 08:59:05 -0700 (PDT) X-Received: by 10.140.104.235 with SMTP id a98mr20036qgf.40.1409759945029; Wed, 03 Sep 2014 08:59:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!dc16no860381qab.1!news-out.google.com!q8ni8qal.1!nntp.google.com!dc16no860376qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 3 Sep 2014 08:59:04 -0700 (PDT) In-Reply-To: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95c04c48-b33a-496b-aff6-6f5b55c8dbb3@googlegroups.com> Subject: Re: image median filter From: KJ Injection-Date: Wed, 03 Sep 2014 15:59:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: news.eternal-september.org comp.lang.vhdl:7740 On Wednesday, September 3, 2014 10:53:41 AM UTC-4, mahdiha...@gmail.com wrote: > hi > > How to program filter the salt- pepper noise of image 1. Get an algorithm that models the noise 2. Code the algorithm in your language of choice From newsfish@newsfish Tue Dec 29 16:43:32 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.datemas.de!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!poup.poupinou.org!dedibox.gegeweb.org!gegeweb.eu!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!cleanfeed1-b.proxad.net!nnrp2-1.free.fr!not-for-mail Date: Wed, 03 Sep 2014 21:36:03 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: vhdl code for a 16x8 bit dual port ram References: <5503c066.0210280120.f156642@posting.google.com> <2c5b6b8d-45d2-41bc-8560-2ca4cbc7c86b@googlegroups.com> In-Reply-To: <2c5b6b8d-45d2-41bc-8560-2ca4cbc7c86b@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 18 Message-ID: <54076da3$0$2926$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 03 Sep 2014 21:36:03 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1409772963 news-1.free.fr 2926 88.185.146.198:1461 X-Complaints-To: abuse@proxad.net Xref: news.eternal-september.org comp.lang.vhdl:7741 Le 03/09/2014 16:50, mahdihatamigh61@gmail.com a écrit : > On Monday, October 28, 2002 12:50:09 PM UTC+3:30, ameya wrote: >> I need the code for the dual port ram. a single 8 bit will do . if i >> have for a 16x8 then its very nice of u. the specs are : [...] > ------------------------------------------------------- > 2 -- Design Name : ram_dp_ar_aw > 3 -- File Name : ram_dp_ar_aw.vhd > 4 -- Function : Asynchronous read write RAM > 5 -- Coder : Deepak Kumar Tala (Verilog) > 6 -- Translator : Alexander H Pham (VHDL) [...] Well I sincerely hope the original poster didn't wait almost 12 years for you to give an answer Nicolas From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.142.229 with SMTP id rz5mr6981428pab.17.1409927764590; Fri, 05 Sep 2014 07:36:04 -0700 (PDT) X-Received: by 10.140.92.226 with SMTP id b89mr9309qge.33.1409927764503; Fri, 05 Sep 2014 07:36:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no14941479igi.0!news-out.google.com!i10ni2qaf.0!nntp.google.com!m5no6035852qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Sep 2014 07:36:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.173.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Looking for design ideas to implement a ROM for quick lookup From: mr.jay.diem@gmail.com Injection-Date: Fri, 05 Sep 2014 14:36:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7742 Given a number between 0 and 255(8 bit input), I'd like my ROM module to respond with one of 16 different modes (4 bit output). Some modes will repeat multiple times. So the ROM lookup would be something like : 0 -> MODE_0 1 -> MODE_1 2 -> MODE_6 3 -> MODE_9 4 -> MODE_6 5 -> MODE_12 . . 128 -> MODE_15 Sounds like a 256x4 ROM would be the best way to go at this. It would be really nice to create a subtype for the outputs so I can just reference them directly as "MODE_9" and not "1001". Any insight or guidance would be appreciated! -V From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.100.134 with SMTP id z6mr7695678yhf.8.1409940754984; Fri, 05 Sep 2014 11:12:34 -0700 (PDT) X-Received: by 10.140.96.9 with SMTP id j9mr55593qge.13.1409940754942; Fri, 05 Sep 2014 11:12:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dc16no1453229qab.1!news-out.google.com!q8ni6qal.1!nntp.google.com!dc16no1453224qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Sep 2014 11:12:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Looking for design ideas to implement a ROM for quick lookup From: KJ Injection-Date: Fri, 05 Sep 2014 18:12:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3125 X-Received-Body-CRC: 1174509587 Xref: news.eternal-september.org comp.lang.vhdl:7743 On Friday, September 5, 2014 10:36:08 AM UTC-4, V. wrote: > Given a number between 0 and 255(8 bit input), I'd like my ROM module to = respond with one of 16 different modes (4 bit output). Some modes will repe= at multiple times. >=20 >=20 >=20 > So the ROM lookup would be something like :=20 >=20 >=20 >=20 > 0 -> MODE_0 >=20 > 1 -> MODE_1 >=20 > 2 -> MODE_6 >=20 > 3 -> MODE_9 >=20 > 4 -> MODE_6 >=20 > 5 -> MODE_12 >=20 > . >=20 > . >=20 > 128 -> MODE_15 >=20 >=20 >=20 >=20 >=20 > Sounds like a 256x4 ROM would be the best way to go at this. It would be = really nice to create a subtype for the outputs so I can just reference the= m directly as "MODE_9" and not "1001". >=20 >=20 >=20 > Any insight or guidance would be appreciated! >=20 >=20 >=20 > -V Not sure if you're looking for guidance on how to create the subtype or som= ething else. If for the subtype approach then type t_MY_MODES is (MODE_0, MODE_1,... MODE_15); type arr_t_MY_MODES is array(natural range <>) of t_MY_MODES; constant MY_ROM_DATA: arr_t_MY_MODES(0 to 128) :=3D ( 0 =3D> MODE_0, 1 =3D> MODE_1, ... 128 =3D> MODE_15 ); If you need to convert to/from hard index numbers you would use the 'pos or= 'val attributes of the t_MY_MODES type. Ex: t_MY_MODES'pos(MODE_1) would return the integer 2 t_MY_MODES'val(0) would return the t_MY_MODES MODE_0 If you're looking for a different approach, consider embedding the algorith= m that you have for defining the various 'MODE_x' right into the VHDL inste= ad. Typically that will compact the code, avoid fat fingering the various = MODE_x numbers at all and typically maps itself back to higher level requir= ements in a clearer manner. You would do this by creating a function that returns an integer array the = size of your intended ROM table and then calling that function to initializ= e the ROM data. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.52.74.230 with SMTP id x6mr7803665vdv.6.1409940888077; Fri, 05 Sep 2014 11:14:48 -0700 (PDT) X-Received: by 10.140.83.180 with SMTP id j49mr294335qgd.1.1409940887978; Fri, 05 Sep 2014 11:14:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no6089736qaj.0!news-out.google.com!q8ni6qal.1!nntp.google.com!dc16no1453647qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Sep 2014 11:14:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Looking for design ideas to implement a ROM for quick lookup From: KJ Injection-Date: Fri, 05 Sep 2014 18:14:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1559 X-Received-Body-CRC: 1547746675 Xref: news.eternal-september.org comp.lang.vhdl:7744 On Friday, September 5, 2014 2:12:37 PM UTC-4, KJ wrote: > If you need to convert to/from hard index numbers you would use the 'pos or 'val attributes of the t_MY_MODES type. > > Ex: t_MY_MODES'pos(MODE_1) would return the integer 1 > > t_MY_MODES'val(0) would return the t_MY_MODES MODE_0 Corrected the value returned by the 'pos attribute above KJ From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.236.118.37 with SMTP id k25mr11195047yhh.1.1410031146361; Sat, 06 Sep 2014 12:19:06 -0700 (PDT) X-Received: by 10.140.41.112 with SMTP id y103mr4686qgy.7.1410031146282; Sat, 06 Sep 2014 12:19:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!m5no6333163qaj.0!news-out.google.com!q8ni1qal.1!nntp.google.com!dc16no1697024qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Sep 2014 12:19:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.52.154.147; posting-account=h8NzEQoAAADdjogZfsTb_Lu34wy7lBWC NNTP-Posting-Host: 121.52.154.147 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: FPGA From: aamirsamejo42@gmail.com Injection-Date: Sat, 06 Sep 2014 19:19:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: news.eternal-september.org comp.lang.vhdl:7745 WHAT IS VHDL? From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.182.47.136 with SMTP id d8mr11147104obn.10.1410031233841; Sat, 06 Sep 2014 12:20:33 -0700 (PDT) X-Received: by 10.140.30.36 with SMTP id c33mr429034qgc.2.1410031233696; Sat, 06 Sep 2014 12:20:33 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r2no15748139igi.0!news-out.google.com!q8ni1qal.1!nntp.google.com!dc16no1697221qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Sep 2014 12:20:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.52.154.147; posting-account=h8NzEQoAAADdjogZfsTb_Lu34wy7lBWC NNTP-Posting-Host: 121.52.154.147 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: what is VHDL? From: aamirsamejo42@gmail.com Injection-Date: Sat, 06 Sep 2014 19:20:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7746 WHAT DO YU KNOW ABOUT VHDL?? From newsfish@newsfish Tue Dec 29 16:43:32 2015 X-Received: by 10.66.97.6 with SMTP id dw6mr7618223pab.23.1410031294847; Sat, 06 Sep 2014 12:21:34 -0700 (PDT) X-Received: by 10.182.28.102 with SMTP id a6mr3194obh.17.1410031294598; Sat, 06 Sep 2014 12:21:34 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no10318207igb.0!news-out.google.com!ht4ni0igb.0!nntp.google.com!r2no15748367igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Sep 2014 12:21:34 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=121.52.154.147; posting-account=h8NzEQoAAADdjogZfsTb_Lu34wy7lBWC NNTP-Posting-Host: 121.52.154.147 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e95e508-d241-4061-b7ad-bb389600ad9f@googlegroups.com> Subject: WHAT IS VHDL? From: aamirsamejo42@gmail.com Injection-Date: Sat, 06 Sep 2014 19:21:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7747 .. From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: what is VHDL? Date: Sat, 06 Sep 2014 16:19:09 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 6 Sep 2014 20:19:21 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13298"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/EP218grrFMi1NUMjNRe67" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:atUD/TV5xD2pO31VA1pYBG/eqis= Xref: news.eternal-september.org comp.lang.vhdl:7748 On 9/6/2014 3:20 PM, aamirsamejo42@gmail.com wrote: > WHAT DO YU KNOW ABOUT VHDL?? I know stuff... -- Rick From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: what is VHDL? Date: Sat, 06 Sep 2014 21:20:15 -0400 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 7 Sep 2014 01:21:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="23357"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X62/SK720UvlS21NWgDyo" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.0 In-Reply-To: Cancel-Lock: sha1:j+CFedEqc8Ehr9GSn29IT1Ha47E= Xref: news.eternal-september.org comp.lang.vhdl:7749 On 9/6/2014 3:20 PM, aamirsamejo42@gmail.com wrote: > WHAT DO YU KNOW ABOUT VHDL?? > http://lmgtfy.com/?q=what+is+VHDL From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: image median filter Date: Mon, 08 Sep 2014 08:55:18 -0400 Organization: Alacron, Inc. Lines: 18 Message-ID: References: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Sep 2014 13:00:46 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="8159"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++NvEMs+KKEgQLFl4nkeFoHp9gawCjhsg=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Cancel-Lock: sha1:TgX8Kl1t8WNZyJimQoyr7VvNU7I= Xref: news.eternal-september.org comp.lang.vhdl:7750 mahdihatamigh61@gmail.com wrote: > hi > How to program filter the salt- pepper noise of image You could of course look up "median filter" on Wikipedia. There really aren't that many variants to a median filter, only the kernel size. The basics are to gather the kernel pixels in one place (say 3 x 3 pixels) and then sort the values. Finally take the central value after sorting. There are algorithms that reduce the number of operations required given that you will proceed from one pixel to the next pixel to its immediate right for a typical raster image. These algorithms allow you to make partial sorts that can be re-used. It's not clear whether this would help an algorithm implemented in hardware, though. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.236.17.234 with SMTP id j70mr18380337yhj.26.1410195134852; Mon, 08 Sep 2014 09:52:14 -0700 (PDT) X-Received: by 10.140.98.237 with SMTP id o100mr22120qge.17.1410195134757; Mon, 08 Sep 2014 09:52:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no6763854qaj.0!news-out.google.com!i10ni0qaf.0!nntp.google.com!m5no6763850qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Sep 2014 09:52:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.103.23.176; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 46.103.23.176 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: FPGA From: Nikolaos Kavvadias Injection-Date: Mon, 08 Sep 2014 16:52:14 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Xref: news.eternal-september.org comp.lang.vhdl:7751 zqTOtyDOo86szrLOss6xz4TOvywgNiDOo861z4DPhM61zrzOss+Bzq/Ov8+FIDIwMTQgMTA6MTk6 MDggzrwuzrwuIFVUQyszLCDOvyDPh8+Bzq7Pg8+EzrfPgiBhYW1pcnMuLi5AZ21haWwuY29tIM6t zrPPgc6xz4jOtToNCj4gV0hBVCBJUyBWSERMPw0KDQpGb3IgbG92ZSBvZiB0aGUgZ2FtZToNCg0K aHR0cDovL2VuLndpa2lwZWRpYS5vcmcvd2lraS9WSERMDQoNClNoYW1lbGVzcyBwbHVnOiANCmh0 dHA6Ly93d3cubmthdnZhZGlhcy5jb20vdmhkbC1jb3Vyc2UuaHRtbA0KDQpCZXN0IHJlZ2FyZHMN Ck5pa29sYW9zIEthdnZhZGlhcw0KaHR0cDovL3d3dy5ua2F2dmFkaWFzLmNvbQ0K From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: image median filter Date: Mon, 08 Sep 2014 12:38:22 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Sep 2014 17:38:23 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="176ee0e61dd3a53454a4f3eb6b472df7"; logging-data="13523"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18t58v0qu8g6W6QHodvuTRz" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <77542cf2-2a81-4986-92f1-7f9a8ffa7029@googlegroups.com> Cancel-Lock: sha1:9T4OoOqfb8wdJExu9cPUr1UD1WI= Xref: news.eternal-september.org comp.lang.vhdl:7752 On 9/3/2014 9:53 AM, mahdihatamigh61@gmail.com wrote: > hi > How to program filter the salt- pepper noise of image > Here is an example of a median filter implemented for an FPGA: http://www.fpgarelated.com/showarticle/578.php Note, the article's main topic is not a median filter, but it uses it as a simple example. Regards, Chris From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.43.85.198 with SMTP id ap6mr1743511icc.29.1410912378721; Tue, 16 Sep 2014 17:06:18 -0700 (PDT) X-Received: by 10.50.92.40 with SMTP id cj8mr39257igb.14.1410912378497; Tue, 16 Sep 2014 17:06:18 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1992365igc.0!news-out.google.com!ef6ni3693igb.0!nntp.google.com!h18no1992355igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Sep 2014 17:06:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:9:400:11:e896:dc1c:57a:cde0; posting-account=T7JSRQoAAABGcGdf21_0hms30k9cEuiu NNTP-Posting-Host: 2601:9:400:11:e896:dc1c:57a:cde0 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0fa5221d-bcc4-4c30-96c8-66ec14622b81@googlegroups.com> Subject: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification From: jayadeep90kodali@gmail.com Injection-Date: Wed, 17 Sep 2014 00:06:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7753 Hi Guys, I was asked to prepare a presentation on the topic below for a job interview: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification Someone plz educate me. I am new to these. Thank you. Regards, Jay From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.68.196.161 with SMTP id in1mr1162138pbc.5.1410999218027; Wed, 17 Sep 2014 17:13:38 -0700 (PDT) X-Received: by 10.182.4.1 with SMTP id g1mr17915obg.3.1410999217841; Wed, 17 Sep 2014 17:13:37 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no501153igd.0!news-out.google.com!ht4ni15124igb.0!nntp.google.com!h3no282298igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Sep 2014 17:13:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> Subject: Unconstrained Array of Unconstrained Array From: Weng Tianxiang Injection-Date: Thu, 18 Sep 2014 00:13:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7754 Hi, This is a 16 years old problem. I want to know if VHDL-2008 resolved the problem or not. Why? Thank you. Weng Unconstrained Array of Unconstrained Array 5 posts by 4 authors Jose Paredes 2/12/98 Is it possible to define an unconstrained array of unconstrained arrays? Something like this: type array_type is array(natural range <>) of std_logic_vector; I find myself needing something like this where it would be used in an entity definition like this: entity ... port( a : in array_type(0 to width1-1)(0 to width2-1) ... ... Of course, I know that the above is wrong syntax, but is there something equivalent other than a double dimensional unconstrained array? Ultimately what I want is for the entity to be used like this: signal bus1 : std_logic_vector(0 to 31); signal bus2 : std_logic_vector(0 to 31); ... -- instantiate entity ENTITY1 : ENTITY_NAME generic map( width1 => 2, width2 => 32); port map(a(0) => bus1, a(1) => bus2); This essentially creates 2 ports called a(0) and a(1) into my entity that are 32 bits wide. Surely something very close to this has been done before. Thanks for any help, Jose -- Jose A. Paredes IBM 11400 Burnet Road Internal Mail 4362 Austin, TX 78758 office: 512-838-3855 fax: 512-838-1258 email: jo...@austin.ibm.com Click here to Reply Pam Rissmann 2/12/98 Jose, Unfortunately, VHDL doesn't allow an unconstrained array of an unconstrained array. The element type and size (what the array holds) must be a known quantity. >type array_type is array(natural range <>) of std_logic_vector; ^^^^^^^^^^^^^^^^^ element type However, you can have an unconstrained array of a std_logic_vector(31 downto 0). And like you said, a unconstrained 2 dimensional array of std_logic is allowed. For your application, maybe you can workaround this by creating a package that defines a constrained subtype of std_logic_vector by using a constant set to the same value as your width2 generic. something like: constant c_width2: integer := 32; -- can also make this deferred subtype stdv32 is std_logic_vector(c_width2-1 downto 0); type array_type is array(natural range <>) of stdv32; Hope this helps. --Pam _______________________________________________ Pam Rissmann - Magenta Designs - 650.325.1162 - show quoted text - - Dave Jacobowitz 2/16/98 Pam Rissmann wrote: > > Jose, > Unfortunately, VHDL doesn't allow an unconstrained array > of an unconstrained array. The element type and size (what the array > holds) must be a known quantity. Not to belabor this point, but I have a similar question. I want to do something that I thought would be pretty easy: create a memory that would take generics to set the depth and width and number each of read, write, and cam ports. I tried something like what I have included below. Here none of the arrays are unconstrained, their sizes are all set by the generics given. My problem is that the the VHDL syntax does not seem to support the definition of arrays within the port section. Creating subtypes ahead of time in a package solves this problem, but only partially, since if I want to include multiple instances of this entity with varying sizes and ports, I'll have to make multiple copies of the source and actually change them, defeating the purpose of the generics altogether. Can VHDL really not do this? -- dave jacobowitz (dja...@quickturn.com) ------------------------------------------------------------ entity hcam is generic ( width : integer := 32; addrwidth : integer := 5; depth : integer := 32; rports : integer := 1; wports : integer := 1; kports : integer := 1); port ( clock : std_logic; read_address_in : in array (rports-1 downto 0) of unsigned (addrwidth-1 downto 0); read_data_out : out array (rports-1 downto 0) of std_logic_vector (width-1 downto 0); read_en : in std_logic_vector(rports-1 downto 0); write_address_in : in array (wports-1 downto 0) of unsigned (addrwidth-1 downto 0); write_data_in : in array (wports-1 downto 0) of std_logic_vector (width-1 downto 0); write_en : in std_logic_vector(wports-1 downto 0); key_data_in : in array (kports-1 downto 0) of std_logic_vector (width-1 downto 0); key_match : out std_logic_vector(kports-1 downto 0); key_matchaddr : out array (kports-1 downto 0) of unsigned (addrwidth-1 downto 0); key_cam_en : in std_logic_vector(kports-1 downto 0); end hcam; Martin Radetzki 2/17/98 Dave Jacobowitz wrote: > > Pam Rissmann wrote: > > > > Jose, > > Unfortunately, VHDL doesn't allow an unconstrained array > > of an unconstrained array. The element type and size (what the array > > holds) must be a known quantity. > > Not to belabor this point, but I have a similar question. I want > to do something that I thought would be pretty easy: create a > memory that would take generics to set the depth and width and > number each of read, write, and cam ports. I tried something like > what I have included below. Here none of the arrays are unconstrained, > their sizes are all set by the generics given. My problem is that > the the VHDL syntax does not seem to support the definition of > arrays within the port section. > > Creating subtypes ahead of time in a package solves this problem, > but only partially, since if I want to include multiple instances > of this entity with varying sizes and ports, I'll have to make > multiple copies of the source and actually change them, defeating > the purpose of the generics altogether. > > Can VHDL really not do this? > > -- dave jacobowitz (dja...@quickturn.com) > Well, VHDL can do it using a 2-dimensional array declared in some package: type STD_LOGIC_ARRAY is array( NATURAL range <>, NATURAL range <> ) of STD_LOGIC; Then, declare the ports like this: read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0, addrwidth-1 downto 0 ); ... Using this approach, one can't use type UNSIGNED for the port, but conversion should be possible, the elements (single bits) of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible for assignment. However, due to type mismatch, it will not be possible to assign a complete UNSIGNED vector to a row of the 2-dim array, unfortunately. Thus, unless someone else has another solution, the approach to declare the width of ports as constants in a package may be easier to deal with than this 2-dim array approach. - show quoted text - ________________________________________________________________________ Martin Radetzki Tel.: **49-441-798-2988 OFFIS Research Institute Fax.: **49-441-798-2145 Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin 26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de Jose Paredes 2/20/98 Dave, I was trying to do the same thing as you. The only solution is to have a 2-dimensional array. This makes the code a little unreadable, because when you actually use the outputs of the RAM you can't just assign a one of the outputs to a logic vector signal, like you would have been able to if you had an array of arrays. For instance: -- somwhere in a package : -- two ram output ports of width 8 TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7); -- entity ENTITY ram is ( ... outputports : out array_type1 ... -- somewhere else you would want signal ram_port0(0 to 7); signal ram_port1(0 to 7); RAM0 : ram port map( ... outputports(0) => ram_port0, outputports(1) => ram_port1, ... This is all valid syntax. The problem is that since the second the std_logic_vector(0 to 7) must be there, you can't make the width of the port generic. So you have to implement something nasty: -- somwhere in a package : -- TYPE array_type2 is array (integer range <>, integer range <>) of std_logic; -- entity ENTITY ram is ( ... outputports : out array_type2(0 to 1, 0 to 7) ... -- somewhere else you would want signal ram_port0(0 to 7); signal ram_port1(0 to 7); RAM0 : ram port map( ... outputports(0,0) => ram_port0(0), outputports(0,1) => ram_port0(1), outputports(0,2) => ram_port0(2), ... outputports(1,0) => ram_port1(0), outputports(1,1) => ram_port1(1), outputports(1,2) => ram_port1(2), .. Which is simply ridiculous. I find the language inconsistent in this matter, because there is no reason, in my opinion, why you could not have been able to resolve both constraints of an array of arrays: -- package type array_type is array(integer range <>) of std_logic_vector; -- somewhere else entity ram is port( ... -- why is this not allowed? multi_port : array_type(0 to 1)(0 to 7); I don't understand exactly why this is not allowed, since there is really nothing magical about this (other than not being correct syntax...). I assume it has something to do with strong typing in VHDL which I also believe that in some cases it hinders productivity (like in this case). Just my 2 centavos... Jose -- Jose A. Paredes IBM 11400 Burnet Road Internal Mail 4362 Austin, TX 78758 office: 512-838-3855 fax: 512-838-1258 email: jo...@austin.ibm.com From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.52.65.180 with SMTP id y20mr1367651vds.4.1411011642459; Wed, 17 Sep 2014 20:40:42 -0700 (PDT) X-Received: by 10.182.80.170 with SMTP id s10mr2536obx.14.1411011642306; Wed, 17 Sep 2014 20:40:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m5no1653514qaj.0!news-out.google.com!ef6ni14504igb.0!nntp.google.com!h15no640836igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Sep 2014 20:40:41 -0700 (PDT) In-Reply-To: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.102; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.102 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: Daniel Kho Injection-Date: Thu, 18 Sep 2014 03:40:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7755 On Thursday, 18 September 2014 08:13:41 UTC+8, Weng Tianxiang wrote: > Hi, > > This is a 16 years old problem. > > > > I want to know if VHDL-2008 resolved the problem or not. Why? > > > > Thank you. > > > > Weng > > > > > > Unconstrained Array of Unconstrained Array > > 5 posts by 4 authors > > > > > > > > Jose Paredes > > 2/12/98 > > > > > > > > Is it possible to define an unconstrained array of unconstrained arrays? > > Something like this: > > type array_type is array(natural range <>) of std_logic_vector; > > > > I find myself needing something like this where it would be used in an > > entity definition like this: > > > > entity ... > > > > port( a : in array_type(0 to width1-1)(0 to width2-1) ... > > ... > > > > Of course, I know that the above is wrong syntax, but is there something > > equivalent other than a double dimensional unconstrained array? > > > > Ultimately what I want is for the entity to be used like this: > > > > signal bus1 : std_logic_vector(0 to 31); > > signal bus2 : std_logic_vector(0 to 31); > > ... > > > > -- instantiate entity > > > > ENTITY1 : ENTITY_NAME > > > > generic map( width1 => 2, width2 => 32); > > port map(a(0) => bus1, > > a(1) => bus2); > > > > This essentially creates 2 ports called a(0) and a(1) into my entity > > that are 32 bits wide. Surely something very close to this has been done > > before. > > > > Thanks for any help, > > Jose > > -- > > Jose A. Paredes > > > > IBM > > 11400 Burnet Road > > Internal Mail 4362 > > Austin, TX 78758 > > > > office: 512-838-3855 > > fax: 512-838-1258 > > email: jo...@austin.ibm.com > > > > Click here to Reply > > > > > > > > Pam Rissmann > > 2/12/98 > > > > > > > > Jose, > > Unfortunately, VHDL doesn't allow an unconstrained array > > of an unconstrained array. The element type and size (what the array > > holds) must be a known quantity. > > >type array_type is array(natural range <>) of std_logic_vector; > > ^^^^^^^^^^^^^^^^^ > > element type > > However, you can have > > an unconstrained array of a std_logic_vector(31 downto 0). > > And like you said, a unconstrained 2 dimensional array of > > std_logic is allowed. > > > > For your application, maybe you can workaround this > > by creating a package that defines a constrained subtype > > of std_logic_vector by using a constant set to the same > > value as your width2 generic. > > something like: > > constant c_width2: integer := 32; -- can also make this deferred > > subtype stdv32 is std_logic_vector(c_width2-1 downto 0); > > type array_type is array(natural range <>) of stdv32; > > > > > > Hope this helps. > > --Pam > > _______________________________________________ > > Pam Rissmann - Magenta Designs - 650.325.1162 > > > > - show quoted text - > > - > > > > > > > > > > Dave Jacobowitz > > 2/16/98 > > > > > > > > Pam Rissmann wrote: > > > > > > Jose, > > > Unfortunately, VHDL doesn't allow an unconstrained array > > > of an unconstrained array. The element type and size (what the array > > > holds) must be a known quantity. > > > > Not to belabor this point, but I have a similar question. I want > > to do something that I thought would be pretty easy: create a > > memory that would take generics to set the depth and width and > > number each of read, write, and cam ports. I tried something like > > what I have included below. Here none of the arrays are unconstrained, > > their sizes are all set by the generics given. My problem is that > > the the VHDL syntax does not seem to support the definition of > > arrays within the port section. > > > > Creating subtypes ahead of time in a package solves this problem, > > but only partially, since if I want to include multiple instances > > of this entity with varying sizes and ports, I'll have to make > > multiple copies of the source and actually change them, defeating > > the purpose of the generics altogether. > > > > Can VHDL really not do this? > > > > > > -- dave jacobowitz (dja...@quickturn.com) > > > > ------------------------------------------------------------ > > > > entity hcam is > > generic ( width : integer := 32; > > addrwidth : integer := 5; > > depth : integer := 32; > > rports : integer := 1; > > wports : integer := 1; > > kports : integer := 1); > > port ( clock : std_logic; > > read_address_in : in array (rports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > read_data_out : out array (rports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > read_en : in std_logic_vector(rports-1 downto 0); > > write_address_in : in array (wports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > write_data_in : in array (wports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > write_en : in std_logic_vector(wports-1 downto 0); > > key_data_in : in array (kports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > key_match : out std_logic_vector(kports-1 downto 0); > > key_matchaddr : out array (kports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > key_cam_en : in std_logic_vector(kports-1 downto 0); > > end hcam; > > > > > > > > > > Martin Radetzki > > 2/17/98 > > > > > > > > Dave Jacobowitz wrote: > > > > > > Pam Rissmann wrote: > > > > > > > > Jose, > > > > Unfortunately, VHDL doesn't allow an unconstrained array > > > > of an unconstrained array. The element type and size (what the array > > > > holds) must be a known quantity. > > > > > > Not to belabor this point, but I have a similar question. I want > > > to do something that I thought would be pretty easy: create a > > > memory that would take generics to set the depth and width and > > > number each of read, write, and cam ports. I tried something like > > > what I have included below. Here none of the arrays are unconstrained, > > > their sizes are all set by the generics given. My problem is that > > > the the VHDL syntax does not seem to support the definition of > > > arrays within the port section. > > > > > > Creating subtypes ahead of time in a package solves this problem, > > > but only partially, since if I want to include multiple instances > > > of this entity with varying sizes and ports, I'll have to make > > > multiple copies of the source and actually change them, defeating > > > the purpose of the generics altogether. > > > > > > Can VHDL really not do this? > > > > > > -- dave jacobowitz (dja...@quickturn.com) > > > > > Well, VHDL can do it using a 2-dimensional array > > declared in some package: > > type STD_LOGIC_ARRAY is > > array( NATURAL range <>, NATURAL range <> ) > > of STD_LOGIC; > > > > Then, declare the ports like this: > > read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0, > > addrwidth-1 downto 0 ); > > ... > > > > Using this approach, one can't use type UNSIGNED for the port, > > but conversion should be possible, the elements (single bits) > > of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible > > for assignment. However, due to type mismatch, it will not be > > possible to assign a complete UNSIGNED vector to a row of the > > 2-dim array, unfortunately. > > > > Thus, unless someone else has another solution, the approach > > to declare the width of ports as constants in a package > > may be easier to deal with than this 2-dim array approach. > > > > - show quoted text - > > ________________________________________________________________________ > > Martin Radetzki Tel.: **49-441-798-2988 > > OFFIS Research Institute Fax.: **49-441-798-2145 > > Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin > > 26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de > > > > > > > > Jose Paredes > > 2/20/98 > > > > > > > > Dave, > > I was trying to do the same thing as you. The only solution is to have a > > 2-dimensional array. This makes the code a little unreadable, because > > when you actually use the outputs of the RAM you can't just assign a one > > of the outputs to a logic vector signal, like you would have been able > > to if you had an array of arrays. For instance: > > > > -- somwhere in a package : > > > > -- two ram output ports of width 8 > > TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7); > > > > -- entity > > ENTITY ram is ( > > ... > > outputports : out array_type1 > > ... > > > > -- somewhere else you would want > > > > signal ram_port0(0 to 7); > > signal ram_port1(0 to 7); > > RAM0 : ram > > > > port map( > > ... > > outputports(0) => ram_port0, > > outputports(1) => ram_port1, > > ... > > > > This is all valid syntax. The problem is that since the second the > > std_logic_vector(0 to 7) must be there, you can't make the width of the > > port generic. So you have to implement something nasty: > > > > -- somwhere in a package : > > > > -- > > TYPE array_type2 is array (integer range <>, integer range <>) of > > std_logic; > > > > -- entity > > ENTITY ram is ( > > ... > > outputports : out array_type2(0 to 1, 0 to 7) > > ... > > > > -- somewhere else you would want > > > > signal ram_port0(0 to 7); > > signal ram_port1(0 to 7); > > RAM0 : ram > > > > port map( > > ... > > outputports(0,0) => ram_port0(0), > > outputports(0,1) => ram_port0(1), > > outputports(0,2) => ram_port0(2), > > ... > > outputports(1,0) => ram_port1(0), > > outputports(1,1) => ram_port1(1), > > outputports(1,2) => ram_port1(2), > > .. > > > > Which is simply ridiculous. I find the language inconsistent in this > > matter, because there is no reason, in my opinion, why you could not > > have been able to resolve both constraints of an array of arrays: > > > > -- package > > type array_type is array(integer range <>) of std_logic_vector; > > > > -- somewhere else > > entity ram is > > port( > > ... > > -- why is this not allowed? > > multi_port : array_type(0 to 1)(0 to 7); > > > > I don't understand exactly why this is not allowed, since there is > > really nothing magical about this (other than not being correct > > syntax...). I assume it has something to do with strong typing in VHDL > > which I also believe that in some cases it hinders productivity (like in > > this case). Just my 2 centavos... > > > > Jose > > -- > > Jose A. Paredes > > > > IBM > > 11400 Burnet Road > > Internal Mail 4362 > > Austin, TX 78758 > > > > office: 512-838-3855 > > fax: 512-838-1258 > > email: jo...@austin.ibm.com Hello TianXiang, I have used the following for as long as I can remember. Synthesis support was available only as far back as 2007/2008 or so, but I believe there is nothing in the language that prevents us from writing this. type memory_vector is array(0 to memoryWidth-1) of unsigned(din'range); type memory_matrix is array(0 to memoryDepth-1) of memory_vector; signal ram_matrix: memory_matrix:=(others=>(others=>(others=>'0'))); -- within the architecture body: ram_matrix(writeAddr_h)(writeAddr_v)<=din; Of course, it's always better to use multi-dimensional arrays if you can. Synthesis support for this is poor though. type memory_matrix2d is array(0 to memoryWidth-1, 0 to memoryDepth-1) of unsigned(din'range); signal ram_matrix2d: memory_matrix2d; -- within the architecture body: ram_matrix2d(writeAddr_h,writeAddr_v)<=din; regards, daniel From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained Array of Unconstrained Array Date: Thu, 18 Sep 2014 00:16:43 -0400 Organization: A noiseless patient Spider Lines: 705 Message-ID: References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 18 Sep 2014 04:17:00 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3905"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/W0DKf8rgUVSNy2R5FtIbR" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> Cancel-Lock: sha1:SW58Isn42LQhTb/RfdUWcAnVEZw= Xref: news.eternal-september.org comp.lang.vhdl:7756 On 9/17/2014 11:40 PM, Daniel Kho wrote: > On Thursday, 18 September 2014 08:13:41 UTC+8, Weng Tianxiang wrote: >> Hi, >> >> This is a 16 years old problem. >> >> >> >> I want to know if VHDL-2008 resolved the problem or not. Why? >> >> >> >> Thank you. >> >> >> >> Weng >> >> >> >> >> >> Unconstrained Array of Unconstrained Array >> >> 5 posts by 4 authors >> >> >> >> >> >> >> >> Jose Paredes >> >> 2/12/98 >> >> >> >> >> >> >> >> Is it possible to define an unconstrained array of unconstrained arrays? >> >> Something like this: >> >> type array_type is array(natural range <>) of std_logic_vector; >> >> >> >> I find myself needing something like this where it would be used in an >> >> entity definition like this: >> >> >> >> entity ... >> >> >> >> port( a : in array_type(0 to width1-1)(0 to width2-1) ... >> >> ... >> >> >> >> Of course, I know that the above is wrong syntax, but is there something >> >> equivalent other than a double dimensional unconstrained array? >> >> >> >> Ultimately what I want is for the entity to be used like this: >> >> >> >> signal bus1 : std_logic_vector(0 to 31); >> >> signal bus2 : std_logic_vector(0 to 31); >> >> ... >> >> >> >> -- instantiate entity >> >> >> >> ENTITY1 : ENTITY_NAME >> >> >> >> generic map( width1 => 2, width2 => 32); >> >> port map(a(0) => bus1, >> >> a(1) => bus2); >> >> >> >> This essentially creates 2 ports called a(0) and a(1) into my entity >> >> that are 32 bits wide. Surely something very close to this has been done >> >> before. >> >> >> >> Thanks for any help, >> >> Jose >> >> -- >> >> Jose A. Paredes >> >> >> >> IBM >> >> 11400 Burnet Road >> >> Internal Mail 4362 >> >> Austin, TX 78758 >> >> >> >> office: 512-838-3855 >> >> fax: 512-838-1258 >> >> email: jo...@austin.ibm.com >> >> >> >> Click here to Reply >> >> >> >> >> >> >> >> Pam Rissmann >> >> 2/12/98 >> >> >> >> >> >> >> >> Jose, >> >> Unfortunately, VHDL doesn't allow an unconstrained array >> >> of an unconstrained array. The element type and size (what the array >> >> holds) must be a known quantity. >> >>> type array_type is array(natural range <>) of std_logic_vector; >> >> ^^^^^^^^^^^^^^^^^ >> >> element type >> >> However, you can have >> >> an unconstrained array of a std_logic_vector(31 downto 0). >> >> And like you said, a unconstrained 2 dimensional array of >> >> std_logic is allowed. >> >> >> >> For your application, maybe you can workaround this >> >> by creating a package that defines a constrained subtype >> >> of std_logic_vector by using a constant set to the same >> >> value as your width2 generic. >> >> something like: >> >> constant c_width2: integer := 32; -- can also make this deferred >> >> subtype stdv32 is std_logic_vector(c_width2-1 downto 0); >> >> type array_type is array(natural range <>) of stdv32; >> >> >> >> >> >> Hope this helps. >> >> --Pam >> >> _______________________________________________ >> >> Pam Rissmann - Magenta Designs - 650.325.1162 >> >> >> >> - show quoted text - >> >> - >> >> >> >> >> >> >> >> >> >> Dave Jacobowitz >> >> 2/16/98 >> >> >> >> >> >> >> >> Pam Rissmann wrote: >> >>> >> >>> Jose, >> >>> Unfortunately, VHDL doesn't allow an unconstrained array >> >>> of an unconstrained array. The element type and size (what the array >> >>> holds) must be a known quantity. >> >> >> >> Not to belabor this point, but I have a similar question. I want >> >> to do something that I thought would be pretty easy: create a >> >> memory that would take generics to set the depth and width and >> >> number each of read, write, and cam ports. I tried something like >> >> what I have included below. Here none of the arrays are unconstrained, >> >> their sizes are all set by the generics given. My problem is that >> >> the the VHDL syntax does not seem to support the definition of >> >> arrays within the port section. >> >> >> >> Creating subtypes ahead of time in a package solves this problem, >> >> but only partially, since if I want to include multiple instances >> >> of this entity with varying sizes and ports, I'll have to make >> >> multiple copies of the source and actually change them, defeating >> >> the purpose of the generics altogether. >> >> >> >> Can VHDL really not do this? >> >> >> >> >> >> -- dave jacobowitz (dja...@quickturn.com) >> >> >> >> ------------------------------------------------------------ >> >> >> >> entity hcam is >> >> generic ( width : integer := 32; >> >> addrwidth : integer := 5; >> >> depth : integer := 32; >> >> rports : integer := 1; >> >> wports : integer := 1; >> >> kports : integer := 1); >> >> port ( clock : std_logic; >> >> read_address_in : in array (rports-1 downto 0) of unsigned >> >> (addrwidth-1 downto 0); >> >> read_data_out : out array (rports-1 downto 0) of >> >> std_logic_vector (width-1 downto 0); >> >> read_en : in std_logic_vector(rports-1 downto 0); >> >> write_address_in : in array (wports-1 downto 0) of unsigned >> >> (addrwidth-1 downto 0); >> >> write_data_in : in array (wports-1 downto 0) of >> >> std_logic_vector (width-1 downto 0); >> >> write_en : in std_logic_vector(wports-1 downto 0); >> >> key_data_in : in array (kports-1 downto 0) of >> >> std_logic_vector (width-1 downto 0); >> >> key_match : out std_logic_vector(kports-1 downto 0); >> >> key_matchaddr : out array (kports-1 downto 0) of unsigned >> >> (addrwidth-1 downto 0); >> >> key_cam_en : in std_logic_vector(kports-1 downto 0); >> >> end hcam; >> >> >> >> >> >> >> >> >> >> Martin Radetzki >> >> 2/17/98 >> >> >> >> >> >> >> >> Dave Jacobowitz wrote: >> >>> >> >>> Pam Rissmann wrote: >> >>>> >> >>>> Jose, >> >>>> Unfortunately, VHDL doesn't allow an unconstrained array >> >>>> of an unconstrained array. The element type and size (what the array >> >>>> holds) must be a known quantity. >> >>> >> >>> Not to belabor this point, but I have a similar question. I want >> >>> to do something that I thought would be pretty easy: create a >> >>> memory that would take generics to set the depth and width and >> >>> number each of read, write, and cam ports. I tried something like >> >>> what I have included below. Here none of the arrays are unconstrained, >> >>> their sizes are all set by the generics given. My problem is that >> >>> the the VHDL syntax does not seem to support the definition of >> >>> arrays within the port section. >> >>> >> >>> Creating subtypes ahead of time in a package solves this problem, >> >>> but only partially, since if I want to include multiple instances >> >>> of this entity with varying sizes and ports, I'll have to make >> >>> multiple copies of the source and actually change them, defeating >> >>> the purpose of the generics altogether. >> >>> >> >>> Can VHDL really not do this? >> >>> >> >>> -- dave jacobowitz (dja...@quickturn.com) >> >>> >> >> Well, VHDL can do it using a 2-dimensional array >> >> declared in some package: >> >> type STD_LOGIC_ARRAY is >> >> array( NATURAL range <>, NATURAL range <> ) >> >> of STD_LOGIC; >> >> >> >> Then, declare the ports like this: >> >> read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0, >> >> addrwidth-1 downto 0 ); >> >> ... >> >> >> >> Using this approach, one can't use type UNSIGNED for the port, >> >> but conversion should be possible, the elements (single bits) >> >> of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible >> >> for assignment. However, due to type mismatch, it will not be >> >> possible to assign a complete UNSIGNED vector to a row of the >> >> 2-dim array, unfortunately. >> >> >> >> Thus, unless someone else has another solution, the approach >> >> to declare the width of ports as constants in a package >> >> may be easier to deal with than this 2-dim array approach. >> >> >> >> - show quoted text - >> >> ________________________________________________________________________ >> >> Martin Radetzki Tel.: **49-441-798-2988 >> >> OFFIS Research Institute Fax.: **49-441-798-2145 >> >> Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin >> >> 26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de >> >> >> >> >> >> >> >> Jose Paredes >> >> 2/20/98 >> >> >> >> >> >> >> >> Dave, >> >> I was trying to do the same thing as you. The only solution is to have a >> >> 2-dimensional array. This makes the code a little unreadable, because >> >> when you actually use the outputs of the RAM you can't just assign a one >> >> of the outputs to a logic vector signal, like you would have been able >> >> to if you had an array of arrays. For instance: >> >> >> >> -- somwhere in a package : >> >> >> >> -- two ram output ports of width 8 >> >> TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7); >> >> >> >> -- entity >> >> ENTITY ram is ( >> >> ... >> >> outputports : out array_type1 >> >> ... >> >> >> >> -- somewhere else you would want >> >> >> >> signal ram_port0(0 to 7); >> >> signal ram_port1(0 to 7); >> >> RAM0 : ram >> >> >> >> port map( >> >> ... >> >> outputports(0) => ram_port0, >> >> outputports(1) => ram_port1, >> >> ... >> >> >> >> This is all valid syntax. The problem is that since the second the >> >> std_logic_vector(0 to 7) must be there, you can't make the width of the >> >> port generic. So you have to implement something nasty: >> >> >> >> -- somwhere in a package : >> >> >> >> -- >> >> TYPE array_type2 is array (integer range <>, integer range <>) of >> >> std_logic; >> >> >> >> -- entity >> >> ENTITY ram is ( >> >> ... >> >> outputports : out array_type2(0 to 1, 0 to 7) >> >> ... >> >> >> >> -- somewhere else you would want >> >> >> >> signal ram_port0(0 to 7); >> >> signal ram_port1(0 to 7); >> >> RAM0 : ram >> >> >> >> port map( >> >> ... >> >> outputports(0,0) => ram_port0(0), >> >> outputports(0,1) => ram_port0(1), >> >> outputports(0,2) => ram_port0(2), >> >> ... >> >> outputports(1,0) => ram_port1(0), >> >> outputports(1,1) => ram_port1(1), >> >> outputports(1,2) => ram_port1(2), >> >> .. >> >> >> >> Which is simply ridiculous. I find the language inconsistent in this >> >> matter, because there is no reason, in my opinion, why you could not >> >> have been able to resolve both constraints of an array of arrays: >> >> >> >> -- package >> >> type array_type is array(integer range <>) of std_logic_vector; >> >> >> >> -- somewhere else >> >> entity ram is >> >> port( >> >> ... >> >> -- why is this not allowed? >> >> multi_port : array_type(0 to 1)(0 to 7); >> >> >> >> I don't understand exactly why this is not allowed, since there is >> >> really nothing magical about this (other than not being correct >> >> syntax...). I assume it has something to do with strong typing in VHDL >> >> which I also believe that in some cases it hinders productivity (like in >> >> this case). Just my 2 centavos... >> >> >> >> Jose >> >> -- >> >> Jose A. Paredes >> >> >> >> IBM >> >> 11400 Burnet Road >> >> Internal Mail 4362 >> >> Austin, TX 78758 >> >> >> >> office: 512-838-3855 >> >> fax: 512-838-1258 >> >> email: jo...@austin.ibm.com > > Hello TianXiang, > I have used the following for as long as I can remember. Synthesis support was available only as far back as 2007/2008 or so, but I believe there is nothing in the language that prevents us from writing this. > > type memory_vector is array(0 to memoryWidth-1) of unsigned(din'range); > type memory_matrix is array(0 to memoryDepth-1) of memory_vector; > signal ram_matrix: memory_matrix:=(others=>(others=>(others=>'0'))); > > -- within the architecture body: > ram_matrix(writeAddr_h)(writeAddr_v)<=din; > > Of course, it's always better to use multi-dimensional arrays if you can. Synthesis support for this is poor though. > > type memory_matrix2d is array(0 to memoryWidth-1, 0 to memoryDepth-1) of unsigned(din'range); > signal ram_matrix2d: memory_matrix2d; > > -- within the architecture body: > ram_matrix2d(writeAddr_h,writeAddr_v)<=din; > > regards, daniel I seem to recall that there are simulation speed advantages in using integers for memory. The range of the integer within the module can be constrained to establish the memory word width. The conversion to what ever bus type outside the module is simple. Why not make your memory module an integer based interface and pass in a generic to set the range of the type for the memory itself. The integers used for wires in and out don't really care about the range, it won't affect the synthesis. -- Rick From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.50.25.129 with SMTP id c1mr2819263igg.7.1411014245591; Wed, 17 Sep 2014 21:24:05 -0700 (PDT) X-Received: by 10.182.56.228 with SMTP id d4mr49965obq.5.1411014245193; Wed, 17 Sep 2014 21:24:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no667560igd.0!news-out.google.com!ef6ni14504igb.0!nntp.google.com!h15no667535igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Sep 2014 21:24:04 -0700 (PDT) In-Reply-To: <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.148.102; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.148.102 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66fe03f0-84e2-4e5e-868d-92134f7070d6@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: Daniel Kho Injection-Date: Thu, 18 Sep 2014 04:24:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7757 Hi Tianxiang, I noticed I haven't _really_ answered your question. The short answer is yo= u can't (?) have an unconstrained array of another unconstrained array. Som= ehow you need to constrain the size of the sub-array, and then you can have= the encapsulating array be unconstrained. But, like what was mentioned in your post, a 2-D array would do what you ne= ed. So, this won't work: type array_type is array(natural range <>) of std_logic_vector; But something like this would: type array_type is array(natural range <>, natural range <>) of std_logic; Synthesis tools still don't efficiently infer memory blocks though. -daniel From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.182.213.138 with SMTP id ns10mr2178292obc.45.1411025742812; Thu, 18 Sep 2014 00:35:42 -0700 (PDT) X-Received: by 10.182.4.1 with SMTP id g1mr86549obg.3.1411025742668; Thu, 18 Sep 2014 00:35:42 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h3no443965igd.0!news-out.google.com!ht4ni15124igb.0!nntp.google.com!h3no443951igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Sep 2014 00:35:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=124.123.224.32; posting-account=2XOiVwoAAAAvAauzq_1BDrMv8djeMRxi NNTP-Posting-Host: 124.123.224.32 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <385232ea-7792-48ef-91b2-8bd895aae2bb@googlegroups.com> Subject: Freelance Web Designing in Hyderabad | Low cost Web Developer at Hyderabad | Web Designing Services at Reasonable Prices From: steeveave@gmail.com Injection-Date: Thu, 18 Sep 2014 07:35:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7758 webslavery Services Provides the Freelancing web design service at low-cost with the aim of each company, business, person get their own website and expand their business Our Services: Website designing,Website re-designing,Logo designing,ID card designing,Broucher designing,Template designing,User interface designing Our Portfolio: Please Visit Website Freelance Web Designing in Hyderabad We also provide Online Web designing training with live projects interest people For more Details Contact : E-mail: webslavery123@gmail.com Contact No: India:+91 8897931177,+91 9030361564 web : http://www.webslavery.com/ From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.182.40.197 with SMTP id z5mr3144700obk.24.1411038065307; Thu, 18 Sep 2014 04:01:05 -0700 (PDT) X-Received: by 10.182.186.34 with SMTP id fh2mr84obc.21.1411038065155; Thu, 18 Sep 2014 04:01:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!news.glorb.com!h3no531680igd.0!news-out.google.com!ef6ni14504igb.0!nntp.google.com!h15no885955igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Sep 2014 04:01:04 -0700 (PDT) In-Reply-To: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8dfdb7bb-f06a-44b2-8513-f38b15b66e43@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: KJ Injection-Date: Thu, 18 Sep 2014 11:01:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7759 On Wednesday, September 17, 2014 8:13:41 PM UTC-4, Weng Tianxiang wrote: > Hi, > > This is a 16 years old problem. > > I want to know if VHDL-2008 resolved the problem or not. Why? > If you compile with 2008 then yes you can have an unconstrained array of an unconstrained array. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.66.218.162 with SMTP id ph2mr4434368pac.3.1411057521988; Thu, 18 Sep 2014 09:25:21 -0700 (PDT) X-Received: by 10.50.2.6 with SMTP id 6mr672458igq.10.1411057521879; Thu, 18 Sep 2014 09:25:21 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1085459igd.0!news-out.google.com!ht4ni16956igb.0!nntp.google.com!h3no680529igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Sep 2014 09:25:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2da740e8-38fd-4864-86a3-82dd8a9b674e@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: Weng Tianxiang Injection-Date: Thu, 18 Sep 2014 16:25:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7760 On Wednesday, September 17, 2014 9:17:05 PM UTC-7, rickman wrote: > On 9/17/2014 11:40 PM, Daniel Kho wrote: > > > On Thursday, 18 September 2014 08:13:41 UTC+8, Weng Tianxiang wrote: > > >> Hi, > > >> > > >> This is a 16 years old problem. > > >> > > >> > > >> > > >> I want to know if VHDL-2008 resolved the problem or not. Why? > > >> > > >> > > >> > > >> Thank you. > > >> > > >> > > >> > > >> Weng > > >> > > >> > > >> > > >> > > >> > > >> Unconstrained Array of Unconstrained Array > > >> > > >> 5 posts by 4 authors > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Jose Paredes > > >> > > >> 2/12/98 > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Is it possible to define an unconstrained array of unconstrained arrays? > > >> > > >> Something like this: > > >> > > >> type array_type is array(natural range <>) of std_logic_vector; > > >> > > >> > > >> > > >> I find myself needing something like this where it would be used in an > > >> > > >> entity definition like this: > > >> > > >> > > >> > > >> entity ... > > >> > > >> > > >> > > >> port( a : in array_type(0 to width1-1)(0 to width2-1) ... > > >> > > >> ... > > >> > > >> > > >> > > >> Of course, I know that the above is wrong syntax, but is there something > > >> > > >> equivalent other than a double dimensional unconstrained array? > > >> > > >> > > >> > > >> Ultimately what I want is for the entity to be used like this: > > >> > > >> > > >> > > >> signal bus1 : std_logic_vector(0 to 31); > > >> > > >> signal bus2 : std_logic_vector(0 to 31); > > >> > > >> ... > > >> > > >> > > >> > > >> -- instantiate entity > > >> > > >> > > >> > > >> ENTITY1 : ENTITY_NAME > > >> > > >> > > >> > > >> generic map( width1 => 2, width2 => 32); > > >> > > >> port map(a(0) => bus1, > > >> > > >> a(1) => bus2); > > >> > > >> > > >> > > >> This essentially creates 2 ports called a(0) and a(1) into my entity > > >> > > >> that are 32 bits wide. Surely something very close to this has been done > > >> > > >> before. > > >> > > >> > > >> > > >> Thanks for any help, > > >> > > >> Jose > > >> > > >> -- > > >> > > >> Jose A. Paredes > > >> > > >> > > >> > > >> IBM > > >> > > >> 11400 Burnet Road > > >> > > >> Internal Mail 4362 > > >> > > >> Austin, TX 78758 > > >> > > >> > > >> > > >> office: 512-838-3855 > > >> > > >> fax: 512-838-1258 > > >> > > >> email: jo...@austin.ibm.com > > >> > > >> > > >> > > >> Click here to Reply > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Pam Rissmann > > >> > > >> 2/12/98 > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Jose, > > >> > > >> Unfortunately, VHDL doesn't allow an unconstrained array > > >> > > >> of an unconstrained array. The element type and size (what the array > > >> > > >> holds) must be a known quantity. > > >> > > >>> type array_type is array(natural range <>) of std_logic_vector; > > >> > > >> ^^^^^^^^^^^^^^^^^ > > >> > > >> element type > > >> > > >> However, you can have > > >> > > >> an unconstrained array of a std_logic_vector(31 downto 0). > > >> > > >> And like you said, a unconstrained 2 dimensional array of > > >> > > >> std_logic is allowed. > > >> > > >> > > >> > > >> For your application, maybe you can workaround this > > >> > > >> by creating a package that defines a constrained subtype > > >> > > >> of std_logic_vector by using a constant set to the same > > >> > > >> value as your width2 generic. > > >> > > >> something like: > > >> > > >> constant c_width2: integer := 32; -- can also make this deferred > > >> > > >> subtype stdv32 is std_logic_vector(c_width2-1 downto 0); > > >> > > >> type array_type is array(natural range <>) of stdv32; > > >> > > >> > > >> > > >> > > >> > > >> Hope this helps. > > >> > > >> --Pam > > >> > > >> _______________________________________________ > > >> > > >> Pam Rissmann - Magenta Designs - 650.325.1162 > > >> > > >> > > >> > > >> - show quoted text - > > >> > > >> - > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Dave Jacobowitz > > >> > > >> 2/16/98 > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Pam Rissmann wrote: > > >> > > >>> > > >> > > >>> Jose, > > >> > > >>> Unfortunately, VHDL doesn't allow an unconstrained array > > >> > > >>> of an unconstrained array. The element type and size (what the array > > >> > > >>> holds) must be a known quantity. > > >> > > >> > > >> > > >> Not to belabor this point, but I have a similar question. I want > > >> > > >> to do something that I thought would be pretty easy: create a > > >> > > >> memory that would take generics to set the depth and width and > > >> > > >> number each of read, write, and cam ports. I tried something like > > >> > > >> what I have included below. Here none of the arrays are unconstrained, > > >> > > >> their sizes are all set by the generics given. My problem is that > > >> > > >> the the VHDL syntax does not seem to support the definition of > > >> > > >> arrays within the port section. > > >> > > >> > > >> > > >> Creating subtypes ahead of time in a package solves this problem, > > >> > > >> but only partially, since if I want to include multiple instances > > >> > > >> of this entity with varying sizes and ports, I'll have to make > > >> > > >> multiple copies of the source and actually change them, defeating > > >> > > >> the purpose of the generics altogether. > > >> > > >> > > >> > > >> Can VHDL really not do this? > > >> > > >> > > >> > > >> > > >> > > >> -- dave jacobowitz (dja...@quickturn.com) > > >> > > >> > > >> > > >> ------------------------------------------------------------ > > >> > > >> > > >> > > >> entity hcam is > > >> > > >> generic ( width : integer := 32; > > >> > > >> addrwidth : integer := 5; > > >> > > >> depth : integer := 32; > > >> > > >> rports : integer := 1; > > >> > > >> wports : integer := 1; > > >> > > >> kports : integer := 1); > > >> > > >> port ( clock : std_logic; > > >> > > >> read_address_in : in array (rports-1 downto 0) of unsigned > > >> > > >> (addrwidth-1 downto 0); > > >> > > >> read_data_out : out array (rports-1 downto 0) of > > >> > > >> std_logic_vector (width-1 downto 0); > > >> > > >> read_en : in std_logic_vector(rports-1 downto 0); > > >> > > >> write_address_in : in array (wports-1 downto 0) of unsigned > > >> > > >> (addrwidth-1 downto 0); > > >> > > >> write_data_in : in array (wports-1 downto 0) of > > >> > > >> std_logic_vector (width-1 downto 0); > > >> > > >> write_en : in std_logic_vector(wports-1 downto 0); > > >> > > >> key_data_in : in array (kports-1 downto 0) of > > >> > > >> std_logic_vector (width-1 downto 0); > > >> > > >> key_match : out std_logic_vector(kports-1 downto 0); > > >> > > >> key_matchaddr : out array (kports-1 downto 0) of unsigned > > >> > > >> (addrwidth-1 downto 0); > > >> > > >> key_cam_en : in std_logic_vector(kports-1 downto 0); > > >> > > >> end hcam; > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Martin Radetzki > > >> > > >> 2/17/98 > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Dave Jacobowitz wrote: > > >> > > >>> > > >> > > >>> Pam Rissmann wrote: > > >> > > >>>> > > >> > > >>>> Jose, > > >> > > >>>> Unfortunately, VHDL doesn't allow an unconstrained array > > >> > > >>>> of an unconstrained array. The element type and size (what the array > > >> > > >>>> holds) must be a known quantity. > > >> > > >>> > > >> > > >>> Not to belabor this point, but I have a similar question. I want > > >> > > >>> to do something that I thought would be pretty easy: create a > > >> > > >>> memory that would take generics to set the depth and width and > > >> > > >>> number each of read, write, and cam ports. I tried something like > > >> > > >>> what I have included below. Here none of the arrays are unconstrained, > > >> > > >>> their sizes are all set by the generics given. My problem is that > > >> > > >>> the the VHDL syntax does not seem to support the definition of > > >> > > >>> arrays within the port section. > > >> > > >>> > > >> > > >>> Creating subtypes ahead of time in a package solves this problem, > > >> > > >>> but only partially, since if I want to include multiple instances > > >> > > >>> of this entity with varying sizes and ports, I'll have to make > > >> > > >>> multiple copies of the source and actually change them, defeating > > >> > > >>> the purpose of the generics altogether. > > >> > > >>> > > >> > > >>> Can VHDL really not do this? > > >> > > >>> > > >> > > >>> -- dave jacobowitz (dja...@quickturn.com) > > >> > > >>> > > >> > > >> Well, VHDL can do it using a 2-dimensional array > > >> > > >> declared in some package: > > >> > > >> type STD_LOGIC_ARRAY is > > >> > > >> array( NATURAL range <>, NATURAL range <> ) > > >> > > >> of STD_LOGIC; > > >> > > >> > > >> > > >> Then, declare the ports like this: > > >> > > >> read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0, > > >> > > >> addrwidth-1 downto 0 ); > > >> > > >> ... > > >> > > >> > > >> > > >> Using this approach, one can't use type UNSIGNED for the port, > > >> > > >> but conversion should be possible, the elements (single bits) > > >> > > >> of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible > > >> > > >> for assignment. However, due to type mismatch, it will not be > > >> > > >> possible to assign a complete UNSIGNED vector to a row of the > > >> > > >> 2-dim array, unfortunately. > > >> > > >> > > >> > > >> Thus, unless someone else has another solution, the approach > > >> > > >> to declare the width of ports as constants in a package > > >> > > >> may be easier to deal with than this 2-dim array approach. > > >> > > >> > > >> > > >> - show quoted text - > > >> > > >> ________________________________________________________________________ > > >> > > >> Martin Radetzki Tel.: **49-441-798-2988 > > >> > > >> OFFIS Research Institute Fax.: **49-441-798-2145 > > >> > > >> Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin > > >> > > >> 26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Jose Paredes > > >> > > >> 2/20/98 > > >> > > >> > > >> > > >> > > >> > > >> > > >> > > >> Dave, > > >> > > >> I was trying to do the same thing as you. The only solution is to have a > > >> > > >> 2-dimensional array. This makes the code a little unreadable, because > > >> > > >> when you actually use the outputs of the RAM you can't just assign a one > > >> > > >> of the outputs to a logic vector signal, like you would have been able > > >> > > >> to if you had an array of arrays. For instance: > > >> > > >> > > >> > > >> -- somwhere in a package : > > >> > > >> > > >> > > >> -- two ram output ports of width 8 > > >> > > >> TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7); > > >> > > >> > > >> > > >> -- entity > > >> > > >> ENTITY ram is ( > > >> > > >> ... > > >> > > >> outputports : out array_type1 > > >> > > >> ... > > >> > > >> > > >> > > >> -- somewhere else you would want > > >> > > >> > > >> > > >> signal ram_port0(0 to 7); > > >> > > >> signal ram_port1(0 to 7); > > >> > > >> RAM0 : ram > > >> > > >> > > >> > > >> port map( > > >> > > >> ... > > >> > > >> outputports(0) => ram_port0, > > >> > > >> outputports(1) => ram_port1, > > >> > > >> ... > > >> > > >> > > >> > > >> This is all valid syntax. The problem is that since the second the > > >> > > >> std_logic_vector(0 to 7) must be there, you can't make the width of the > > >> > > >> port generic. So you have to implement something nasty: > > >> > > >> > > >> > > >> -- somwhere in a package : > > >> > > >> > > >> > > >> -- > > >> > > >> TYPE array_type2 is array (integer range <>, integer range <>) of > > >> > > >> std_logic; > > >> > > >> > > >> > > >> -- entity > > >> > > >> ENTITY ram is ( > > >> > > >> ... > > >> > > >> outputports : out array_type2(0 to 1, 0 to 7) > > >> > > >> ... > > >> > > >> > > >> > > >> -- somewhere else you would want > > >> > > >> > > >> > > >> signal ram_port0(0 to 7); > > >> > > >> signal ram_port1(0 to 7); > > >> > > >> RAM0 : ram > > >> > > >> > > >> > > >> port map( > > >> > > >> ... > > >> > > >> outputports(0,0) => ram_port0(0), > > >> > > >> outputports(0,1) => ram_port0(1), > > >> > > >> outputports(0,2) => ram_port0(2), > > >> > > >> ... > > >> > > >> outputports(1,0) => ram_port1(0), > > >> > > >> outputports(1,1) => ram_port1(1), > > >> > > >> outputports(1,2) => ram_port1(2), > > >> > > >> .. > > >> > > >> > > >> > > >> Which is simply ridiculous. I find the language inconsistent in this > > >> > > >> matter, because there is no reason, in my opinion, why you could not > > >> > > >> have been able to resolve both constraints of an array of arrays: > > >> > > >> > > >> > > >> -- package > > >> > > >> type array_type is array(integer range <>) of std_logic_vector; > > >> > > >> > > >> > > >> -- somewhere else > > >> > > >> entity ram is > > >> > > >> port( > > >> > > >> ... > > >> > > >> -- why is this not allowed? > > >> > > >> multi_port : array_type(0 to 1)(0 to 7); > > >> > > >> > > >> > > >> I don't understand exactly why this is not allowed, since there is > > >> > > >> really nothing magical about this (other than not being correct > > >> > > >> syntax...). I assume it has something to do with strong typing in VHDL > > >> > > >> which I also believe that in some cases it hinders productivity (like in > > >> > > >> this case). Just my 2 centavos... > > >> > > >> > > >> > > >> Jose > > >> > > >> -- > > >> > > >> Jose A. Paredes > > >> > > >> > > >> > > >> IBM > > >> > > >> 11400 Burnet Road > > >> > > >> Internal Mail 4362 > > >> > > >> Austin, TX 78758 > > >> > > >> > > >> > > >> office: 512-838-3855 > > >> > > >> fax: 512-838-1258 > > >> > > >> email: jo...@austin.ibm.com > > > > > > Hello TianXiang, > > > I have used the following for as long as I can remember. Synthesis support was available only as far back as 2007/2008 or so, but I believe there is nothing in the language that prevents us from writing this. > > > > > > type memory_vector is array(0 to memoryWidth-1) of unsigned(din'range); > > > type memory_matrix is array(0 to memoryDepth-1) of memory_vector; > > > signal ram_matrix: memory_matrix:=(others=>(others=>(others=>'0'))); > > > > > > -- within the architecture body: > > > ram_matrix(writeAddr_h)(writeAddr_v)<=din; > > > > > > Of course, it's always better to use multi-dimensional arrays if you can. Synthesis support for this is poor though. > > > > > > type memory_matrix2d is array(0 to memoryWidth-1, 0 to memoryDepth-1) of unsigned(din'range); > > > signal ram_matrix2d: memory_matrix2d; > > > > > > -- within the architecture body: > > > ram_matrix2d(writeAddr_h,writeAddr_v)<=din; > > > > > > regards, daniel > > > > I seem to recall that there are simulation speed advantages in using > > integers for memory. The range of the integer within the module can be > > constrained to establish the memory word width. The conversion to what > > ever bus type outside the module is simple. Why not make your memory > > module an integer based interface and pass in a generic to set the range > > of the type for the memory itself. The integers used for wires in and > > out don't really care about the range, it won't affect the synthesis. > > > > -- > > > > Rick My applications of an unconstrained array of another unconstrained array will be used for everyone in any situations. Weng From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.66.161.199 with SMTP id xu7mr3859243pab.7.1411067026029; Thu, 18 Sep 2014 12:03:46 -0700 (PDT) X-Received: by 10.182.29.106 with SMTP id j10mr3966obh.12.1411067025834; Thu, 18 Sep 2014 12:03:45 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1183644igd.0!news-out.google.com!ht4ni16956igb.0!nntp.google.com!h3no755825igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Sep 2014 12:03:45 -0700 (PDT) In-Reply-To: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8498d19f-ef31-4189-b127-4821375a68cc@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: Weng Tianxiang Injection-Date: Thu, 18 Sep 2014 19:03:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7761 On Wednesday, September 17, 2014 5:13:41 PM UTC-7, Weng Tianxiang wrote: > Hi, > > This is a 16 years old problem. > > > > I want to know if VHDL-2008 resolved the problem or not. Why? > > > > Thank you. > > > > Weng > > > > > > Unconstrained Array of Unconstrained Array > > 5 posts by 4 authors > > > > > > > > Jose Paredes > > 2/12/98 > > > > > > > > Is it possible to define an unconstrained array of unconstrained arrays? > > Something like this: > > type array_type is array(natural range <>) of std_logic_vector; > > > > I find myself needing something like this where it would be used in an > > entity definition like this: > > > > entity ... > > > > port( a : in array_type(0 to width1-1)(0 to width2-1) ... > > ... > > > > Of course, I know that the above is wrong syntax, but is there something > > equivalent other than a double dimensional unconstrained array? > > > > Ultimately what I want is for the entity to be used like this: > > > > signal bus1 : std_logic_vector(0 to 31); > > signal bus2 : std_logic_vector(0 to 31); > > ... > > > > -- instantiate entity > > > > ENTITY1 : ENTITY_NAME > > > > generic map( width1 => 2, width2 => 32); > > port map(a(0) => bus1, > > a(1) => bus2); > > > > This essentially creates 2 ports called a(0) and a(1) into my entity > > that are 32 bits wide. Surely something very close to this has been done > > before. > > > > Thanks for any help, > > Jose > > -- > > Jose A. Paredes > > > > IBM > > 11400 Burnet Road > > Internal Mail 4362 > > Austin, TX 78758 > > > > office: 512-838-3855 > > fax: 512-838-1258 > > email: jo...@austin.ibm.com > > > > Click here to Reply > > > > > > > > Pam Rissmann > > 2/12/98 > > > > > > > > Jose, > > Unfortunately, VHDL doesn't allow an unconstrained array > > of an unconstrained array. The element type and size (what the array > > holds) must be a known quantity. > > >type array_type is array(natural range <>) of std_logic_vector; > > ^^^^^^^^^^^^^^^^^ > > element type > > However, you can have > > an unconstrained array of a std_logic_vector(31 downto 0). > > And like you said, a unconstrained 2 dimensional array of > > std_logic is allowed. > > > > For your application, maybe you can workaround this > > by creating a package that defines a constrained subtype > > of std_logic_vector by using a constant set to the same > > value as your width2 generic. > > something like: > > constant c_width2: integer := 32; -- can also make this deferred > > subtype stdv32 is std_logic_vector(c_width2-1 downto 0); > > type array_type is array(natural range <>) of stdv32; > > > > > > Hope this helps. > > --Pam > > _______________________________________________ > > Pam Rissmann - Magenta Designs - 650.325.1162 > > > > - show quoted text - > > - > > > > > > > > > > Dave Jacobowitz > > 2/16/98 > > > > > > > > Pam Rissmann wrote: > > > > > > Jose, > > > Unfortunately, VHDL doesn't allow an unconstrained array > > > of an unconstrained array. The element type and size (what the array > > > holds) must be a known quantity. > > > > Not to belabor this point, but I have a similar question. I want > > to do something that I thought would be pretty easy: create a > > memory that would take generics to set the depth and width and > > number each of read, write, and cam ports. I tried something like > > what I have included below. Here none of the arrays are unconstrained, > > their sizes are all set by the generics given. My problem is that > > the the VHDL syntax does not seem to support the definition of > > arrays within the port section. > > > > Creating subtypes ahead of time in a package solves this problem, > > but only partially, since if I want to include multiple instances > > of this entity with varying sizes and ports, I'll have to make > > multiple copies of the source and actually change them, defeating > > the purpose of the generics altogether. > > > > Can VHDL really not do this? > > > > > > -- dave jacobowitz (dja...@quickturn.com) > > > > ------------------------------------------------------------ > > > > entity hcam is > > generic ( width : integer := 32; > > addrwidth : integer := 5; > > depth : integer := 32; > > rports : integer := 1; > > wports : integer := 1; > > kports : integer := 1); > > port ( clock : std_logic; > > read_address_in : in array (rports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > read_data_out : out array (rports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > read_en : in std_logic_vector(rports-1 downto 0); > > write_address_in : in array (wports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > write_data_in : in array (wports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > write_en : in std_logic_vector(wports-1 downto 0); > > key_data_in : in array (kports-1 downto 0) of > > std_logic_vector (width-1 downto 0); > > key_match : out std_logic_vector(kports-1 downto 0); > > key_matchaddr : out array (kports-1 downto 0) of unsigned > > (addrwidth-1 downto 0); > > key_cam_en : in std_logic_vector(kports-1 downto 0); > > end hcam; > > > > > > > > > > Martin Radetzki > > 2/17/98 > > > > > > > > Dave Jacobowitz wrote: > > > > > > Pam Rissmann wrote: > > > > > > > > Jose, > > > > Unfortunately, VHDL doesn't allow an unconstrained array > > > > of an unconstrained array. The element type and size (what the array > > > > holds) must be a known quantity. > > > > > > Not to belabor this point, but I have a similar question. I want > > > to do something that I thought would be pretty easy: create a > > > memory that would take generics to set the depth and width and > > > number each of read, write, and cam ports. I tried something like > > > what I have included below. Here none of the arrays are unconstrained, > > > their sizes are all set by the generics given. My problem is that > > > the the VHDL syntax does not seem to support the definition of > > > arrays within the port section. > > > > > > Creating subtypes ahead of time in a package solves this problem, > > > but only partially, since if I want to include multiple instances > > > of this entity with varying sizes and ports, I'll have to make > > > multiple copies of the source and actually change them, defeating > > > the purpose of the generics altogether. > > > > > > Can VHDL really not do this? > > > > > > -- dave jacobowitz (dja...@quickturn.com) > > > > > Well, VHDL can do it using a 2-dimensional array > > declared in some package: > > type STD_LOGIC_ARRAY is > > array( NATURAL range <>, NATURAL range <> ) > > of STD_LOGIC; > > > > Then, declare the ports like this: > > read_address_in : in STD_LOGIC_ARRAY( rports-1 downto 0, > > addrwidth-1 downto 0 ); > > ... > > > > Using this approach, one can't use type UNSIGNED for the port, > > but conversion should be possible, the elements (single bits) > > of the UNSIGNED vector and the STD_LOGIC_ARRAY are compatible > > for assignment. However, due to type mismatch, it will not be > > possible to assign a complete UNSIGNED vector to a row of the > > 2-dim array, unfortunately. > > > > Thus, unless someone else has another solution, the approach > > to declare the width of ports as constants in a package > > may be easier to deal with than this 2-dim array approach. > > > > - show quoted text - > > ________________________________________________________________________ > > Martin Radetzki Tel.: **49-441-798-2988 > > OFFIS Research Institute Fax.: **49-441-798-2145 > > Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin > > 26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de > > > > > > > > Jose Paredes > > 2/20/98 > > > > > > > > Dave, > > I was trying to do the same thing as you. The only solution is to have a > > 2-dimensional array. This makes the code a little unreadable, because > > when you actually use the outputs of the RAM you can't just assign a one > > of the outputs to a logic vector signal, like you would have been able > > to if you had an array of arrays. For instance: > > > > -- somwhere in a package : > > > > -- two ram output ports of width 8 > > TYPE array_type1 is array (0 to 1) of std_logic_vector(0 to 7); > > > > -- entity > > ENTITY ram is ( > > ... > > outputports : out array_type1 > > ... > > > > -- somewhere else you would want > > > > signal ram_port0(0 to 7); > > signal ram_port1(0 to 7); > > RAM0 : ram > > > > port map( > > ... > > outputports(0) => ram_port0, > > outputports(1) => ram_port1, > > ... > > > > This is all valid syntax. The problem is that since the second the > > std_logic_vector(0 to 7) must be there, you can't make the width of the > > port generic. So you have to implement something nasty: > > > > -- somwhere in a package : > > > > -- > > TYPE array_type2 is array (integer range <>, integer range <>) of > > std_logic; > > > > -- entity > > ENTITY ram is ( > > ... > > outputports : out array_type2(0 to 1, 0 to 7) > > ... > > > > -- somewhere else you would want > > > > signal ram_port0(0 to 7); > > signal ram_port1(0 to 7); > > RAM0 : ram > > > > port map( > > ... > > outputports(0,0) => ram_port0(0), > > outputports(0,1) => ram_port0(1), > > outputports(0,2) => ram_port0(2), > > ... > > outputports(1,0) => ram_port1(0), > > outputports(1,1) => ram_port1(1), > > outputports(1,2) => ram_port1(2), > > .. > > > > Which is simply ridiculous. I find the language inconsistent in this > > matter, because there is no reason, in my opinion, why you could not > > have been able to resolve both constraints of an array of arrays: > > > > -- package > > type array_type is array(integer range <>) of std_logic_vector; > > > > -- somewhere else > > entity ram is > > port( > > ... > > -- why is this not allowed? > > multi_port : array_type(0 to 1)(0 to 7); > > > > I don't understand exactly why this is not allowed, since there is > > really nothing magical about this (other than not being correct > > syntax...). I assume it has something to do with strong typing in VHDL > > which I also believe that in some cases it hinders productivity (like in > > this case). Just my 2 centavos... > > > > Jose > > -- > > Jose A. Paredes > > > > IBM > > 11400 Burnet Road > > Internal Mail 4362 > > Austin, TX 78758 > > > > office: 512-838-3855 > > fax: 512-838-1258 > > email: jo...@austin.ibm.com Hi, DK, KJ, Thank you very much for your replies. Weng From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained Array of Unconstrained Array Date: Thu, 18 Sep 2014 17:54:44 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> <9f3a2a83-78e8-4069-b711-ea8f95a8f3bb@googlegroups.com> <2da740e8-38fd-4864-86a3-82dd8a9b674e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 18 Sep 2014 21:55:02 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10478"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/sRQrxtIYmES1MuSZp8BLv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <2da740e8-38fd-4864-86a3-82dd8a9b674e@googlegroups.com> Cancel-Lock: sha1:Jt02IqN3XLMvkM/evku2fnvyokY= Xref: news.eternal-september.org comp.lang.vhdl:7762 On 9/18/2014 12:25 PM, Weng Tianxiang wrote: > On Wednesday, September 17, 2014 9:17:05 PM UTC-7, rickman wrote: >> >> I seem to recall that there are simulation speed advantages in using >> >> integers for memory. The range of the integer within the module can be >> >> constrained to establish the memory word width. The conversion to what >> >> ever bus type outside the module is simple. Why not make your memory >> >> module an integer based interface and pass in a generic to set the range >> >> of the type for the memory itself. The integers used for wires in and >> >> out don't really care about the range, it won't affect the synthesis. >> >> Rick > > My applications of an unconstrained array of another unconstrained array will be used for everyone in any situations. If you use integers instead of std_logic_vector or unsigned then you don't really need double arrays, now do you? I think memory can then be modeled by a single array. BTW, you really should learn to trim your posts and/or stop using Google groups for a newsreader. Thunderbird is a good newsreader and eternal-september.org gives free access to text only newsgroups. All the double spacing of quotes in Google groups is very obnoxious. -- Rick From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.70.90.138 with SMTP id bw10mr7971041pdb.8.1411141947911; Fri, 19 Sep 2014 08:52:27 -0700 (PDT) X-Received: by 10.182.73.193 with SMTP id n1mr12529obv.27.1411141947746; Fri, 19 Sep 2014 08:52:27 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a13no160776igq.0!news-out.google.com!rp1ni1443igb.0!nntp.google.com!h15no1831222igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Sep 2014 08:52:27 -0700 (PDT) In-Reply-To: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <4e574df8-460d-4dcf-9b23-5253fb0ee8bf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <228291af-b03a-4f4b-86c2-d890ca1b443e@googlegroups.com> Subject: Re: Unconstrained Array of Unconstrained Array From: Weng Tianxiang Injection-Date: Fri, 19 Sep 2014 15:52:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7763 Rickman, I am inventing something brand new for HDL and hope to finish it within two or three months. When published, your critical comments are welcome. It has nothing to do with any type of RAM memory. I really need double arrays, but I found that I don't have to use double unconstrained arrays and found a way to avoid it. OK! I will pay attention to trimming my posts now, deleting all repeated texts. Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.224.4.196 with SMTP id 4mr18887378qas.6.1411290164358; Sun, 21 Sep 2014 02:02:44 -0700 (PDT) X-Received: by 10.140.37.39 with SMTP id q36mr4316qgq.10.1411290164302; Sun, 21 Sep 2014 02:02:44 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m5no1891188qaj.0!news-out.google.com!i10ni16qaf.0!nntp.google.com!dc16no34804qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Sep 2014 02:02:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:580:a5a3:9000:794c:767d:4880:2fa2; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:580:a5a3:9000:794c:767d:4880:2fa2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Is opencores.org dead? From: Nikolaos Kavvadias Injection-Date: Sun, 21 Sep 2014 09:02:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1394 X-Received-Body-CRC: 1824145244 Xref: news.eternal-september.org comp.lang.vhdl:7764 Hi everyone, is www.opencores.org dead for you too? Seems to be down for the last 24h or 48h (at least). There is http://www.freerangefactory.org/cores/ of course, but this is just a snapshot from 2012 (or so). Not to mention having personal projects etc BTW I haven't checked the SVN server yet. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is opencores.org dead? Date: Sun, 21 Sep 2014 07:52:47 -0400 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Sep 2014 11:53:05 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="23417"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18EL5+U74GheZDIiIeLY0Hm" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:kGqIeeoBaT6aqPL/Q8dTdFfx3sM= Xref: news.eternal-september.org comp.lang.vhdl:7765 On 9/21/2014 5:02 AM, Nikolaos Kavvadias wrote: > Hi everyone, > > is www.opencores.org dead for you too? > > Seems to be down for the last 24h or 48h (at least). > > There is http://www.freerangefactory.org/cores/ of course, but this is just a snapshot from 2012 (or so). Not to mention having personal projects etc > > BTW I haven't checked the SVN server yet. Not working for me either. http://www.downforeveryoneorjustme.com/opencores.org Also says it is down. -- Rick From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.66.66.1 with SMTP id b1mr20226515pat.38.1411317218818; Sun, 21 Sep 2014 09:33:38 -0700 (PDT) X-Received: by 10.140.27.166 with SMTP id 35mr197569qgx.5.1411317218770; Sun, 21 Sep 2014 09:33:38 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3250607igd.0!news-out.google.com!i10ni17qaf.0!nntp.google.com!m5no1920277qaj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 21 Sep 2014 09:33:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:580:a5a3:9000:794c:767d:4880:2fa2; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:580:a5a3:9000:794c:767d:4880:2fa2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Is opencores.org dead? From: Nikolaos Kavvadias Injection-Date: Sun, 21 Sep 2014 16:33:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7766 Hi Rick, > > There is http://www.freerangefactory.org/cores/ of course, but this is = just a snapshot from 2012 (or so). Not to mention having personal projects = etc thanks for the tip! This streak of putting many popular sites down (freecode.com, opencollector= .org etc) is worrying. Should we contact ORSoC (http://www.orsoc.se/) that = bought OpenCores from Damjan to see what is going on? If things persist, I = will do so anyway. From ORSoC anyone? Others will also do so, probably. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is opencores.org dead? Date: Mon, 22 Sep 2014 00:10:51 -0400 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 22 Sep 2014 04:11:12 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14568"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Kr+FaM4Q73Wj/9R+5VaKv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:xSiKeul4zYnKsVL94lTq1nG2G/o= Xref: news.eternal-september.org comp.lang.vhdl:7767 On 9/21/2014 12:33 PM, Nikolaos Kavvadias wrote: > Hi Rick, > >>> There is http://www.freerangefactory.org/cores/ of course, but this is just a snapshot from 2012 (or so). Not to mention having personal projects etc > > thanks for the tip! > > This streak of putting many popular sites down (freecode.com, opencollector..org etc) is worrying. Should we contact ORSoC (http://www.orsoc.se/) that bought OpenCores from Damjan to see what is going on? If things persist, I will do so anyway. From ORSoC anyone? > > Others will also do so, probably. Yeah, I just visited their site and they still list opencores in the marketing blurb. I've sent an email to info@orsoc.se. We'll see if they reply. -- Rick From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.lang.vhdl Subject: Re: Is opencores.org dead? Date: Sun, 21 Sep 2014 22:49:40 -0700 Organization: Aioe.org NNTP Server Lines: 26 Message-ID: References: NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.vhdl:7768 On 9/21/2014 9:10 PM, rickman wrote: > On 9/21/2014 12:33 PM, Nikolaos Kavvadias wrote: >> Hi Rick, >> >>>> There is http://www.freerangefactory.org/cores/ of course, but this >>>> is just a snapshot from 2012 (or so). Not to mention having personal >>>> projects etc >> >> thanks for the tip! >> >> This streak of putting many popular sites down (freecode.com, >> opencollector..org etc) is worrying. Should we contact ORSoC >> (http://www.orsoc.se/) that bought OpenCores from Damjan to see what >> is going on? If things persist, I will do so anyway. From ORSoC anyone? >> >> Others will also do so, probably. > > Yeah, I just visited their site and they still list opencores in the > marketing blurb. I've sent an email to info@orsoc.se. We'll see if > they reply. > Try opencores.com (note the .com domain). Not sure what the story is... Rob. From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.182.166.73 with SMTP id ze9mr18249500obb.4.1411375920457; Mon, 22 Sep 2014 01:52:00 -0700 (PDT) X-Received: by 10.140.37.39 with SMTP id q36mr6584qgq.10.1411375920404; Mon, 22 Sep 2014 01:52:00 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no3741480igd.0!news-out.google.com!i10ni18qaf.0!nntp.google.com!dc16no113612qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Sep 2014 01:52:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:580:a5a3:9000:794c:767d:4880:2fa2; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:580:a5a3:9000:794c:767d:4880:2fa2 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9ecce19b-fedf-433c-a6a4-8fd9a532254d@googlegroups.com> Subject: Re: Is opencores.org dead? From: Nikolaos Kavvadias Injection-Date: Mon, 22 Sep 2014 08:52:00 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3027 X-Received-Body-CRC: 3744555260 Xref: news.eternal-september.org comp.lang.vhdl:7769 Thanks @Rob! > Try opencores.com (note the .com domain). Not sure what the story is... BTW the .org top-level domain is up now (maybe from early Monday hours?) @Rick: i think your email helped! No admin on weekend? Anyway, interested i= n their reply if any. Best regards Nikolaos Kavvadias http://www.nkavvadias.com =CE=A4=CE=B7 =CE=94=CE=B5=CF=85=CF=84=CE=AD=CF=81=CE=B1, 22 =CE=A3=CE=B5=CF= =80=CF=84=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 8:49:54 =CF=80.=CE= =BC. UTC+3, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Rob Doyle =CE= =AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > On 9/21/2014 9:10 PM, rickman wrote: >=20 > > On 9/21/2014 12:33 PM, Nikolaos Kavvadias wrote: >=20 > >> Hi Rick, >=20 > >> >=20 > >>>> There is http://www.freerangefactory.org/cores/ of course, but this >=20 > >>>> is just a snapshot from 2012 (or so). Not to mention having personal >=20 > >>>> projects etc >=20 > >> >=20 > >> thanks for the tip! >=20 > >> >=20 > >> This streak of putting many popular sites down (freecode.com, >=20 > >> opencollector..org etc) is worrying. Should we contact ORSoC >=20 > >> (http://www.orsoc.se/) that bought OpenCores from Damjan to see what >=20 > >> is going on? If things persist, I will do so anyway. From ORSoC anyone= ? >=20 > >> >=20 > >> Others will also do so, probably. >=20 > > >=20 > > Yeah, I just visited their site and they still list opencores in the >=20 > > marketing blurb. I've sent an email to info-at-orsoc.se. We'll see if >=20 > > they reply. >=20 > > >=20 >=20 >=20 > Try opencores.com (note the .com domain). Not sure what the story is... >=20 >=20 >=20 > Rob. From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.182.29.10 with SMTP id f10mr19796198obh.23.1411407647430; Mon, 22 Sep 2014 10:40:47 -0700 (PDT) X-Received: by 10.140.101.16 with SMTP id t16mr11688qge.36.1411407647318; Mon, 22 Sep 2014 10:40:47 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4132901igd.0!news-out.google.com!q8ni28qal.1!nntp.google.com!w8no20310qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 22 Sep 2014 10:40:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:580:a5a3:9000:794c:767d:4880:2fa2; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 2a02:580:a5a3:9000:794c:767d:4880:2fa2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6886294c-234f-4a1a-bdef-2db7fecb25cc@googlegroups.com> Subject: From GMP programs to hardware: Concept high-level synthesis tool From: Nikolaos Kavvadias Injection-Date: Mon, 22 Sep 2014 17:40:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7770 Dear all, last year I did a small experiment for automatically generating RTL from gm= p programs (as in gmplib.org). These programs use API calls for performing = arbitrary-precision integer arithmetic for use in cryptography, conducting/= supporting mathematical proofs and for purposes of scientific computing in = general. I have developed a concept tool that is part of HercuLeS HLS (http://www.nk= avvadias.com/hercules/). I actually used the fgmp (public domain) implement= ation and API, due to GMP's licensing. The extensions (coded within a few d= ays or so) did not yet generate synthesizable code, but I was able to gener= ate simulatable HDL (VHDL) with gmp API calls as proof-of-concept. This pro= of-of-concept frontend for GNU multi-precision integer programs has been im= plemented along with a VHDL IP library for key library functionalities such= as mpz_set, mpz_add and mpz_mul. From this point, generating synthesizable= code using this approach is basically assuming a model of computation (hie= rarchical/communicating FSMDs) and write the backend extensions for it.=20 A number of test programs (from C, to intermediate representation, program = graphs, generated HDL code) are available and eventually will end up at my = github: http://github.com/nkkav/ My questions in order to see if this is worth pursuing further (IMHO it is = very worthy and meaningful to many experimenters out there): 1) Is there anyone prototyping algorithms using gmplib.org ints that would = investigate a hardware mapping? 2) Would a high-level synthesis tool from GMP to HW make sense?=20 3) What is the killer app for this? Cryptography or something else? Is it s= omething that I am currently missing? Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:33 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.lang.vhdl Subject: Re: Is opencores.org dead? Date: Mon, 22 Sep 2014 22:42:21 +0200 Lines: 74 Message-ID: References: <9ecce19b-fedf-433c-a6a4-8fd9a532254d@googlegroups.com> Reply-To: ghf@hoffmann-hochfrequenz.de Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net ppm8B5RHV3OydPqwb3o+JQeB8BlK5igLTyCiaRTnJylOjs9kZn Cancel-Lock: sha1:3e9GeDVmwaDK3xlD9fejk96vVms= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.1 In-Reply-To: <9ecce19b-fedf-433c-a6a4-8fd9a532254d@googlegroups.com> Xref: news.eternal-september.org comp.lang.vhdl:7771 Am 22.09.2014 um 10:52 schrieb Nikolaos Kavvadias: > Thanks @Rob! > >> Try opencores.com (note the .com domain). Not sure what the story is... > > BTW the .org top-level domain is up now (maybe from early Monday hours?) > > @Rick: i think your email helped! No admin on weekend? Anyway, interested in their reply if any. > > Best regards > Nikolaos Kavvadias > http://www.nkavvadias.com > > Τη ΔευτέÏα, 22 ΣεπτεμβÏίου 2014 8:49:54 Ï€.μ. UTC+3, ο χÏήστης Rob Doyle έγÏαψε: >> On 9/21/2014 9:10 PM, rickman wrote: >> >>> On 9/21/2014 12:33 PM, Nikolaos Kavvadias wrote: >> >>>> Hi Rick, >> >>>> >> >>>>>> There is http://www.freerangefactory.org/cores/ of course, but this >> >>>>>> is just a snapshot from 2012 (or so). Not to mention having personal >> >>>>>> projects etc >> >>>> >> >>>> thanks for the tip! >> >>>> >> >>>> This streak of putting many popular sites down (freecode.com, >> >>>> opencollector..org etc) is worrying. Should we contact ORSoC >> >>>> (http://www.orsoc.se/) that bought OpenCores from Damjan to see what >> >>>> is going on? If things persist, I will do so anyway. From ORSoC anyone? >> >>>> >> >>>> Others will also do so, probably. >> >>> >> >>> Yeah, I just visited their site and they still list opencores in the >> >>> marketing blurb. I've sent an email to info-at-orsoc.se. We'll see if >> >>> they reply. >> >>> >> >> >> >> Try opencores.com (note the .com domain). Not sure what the story is... >> >> >> >> Rob. > opencores.org works for me. Nevertheless there seems to be nobody to keep the site clean. I wonder what "Wishbone protocol to axi4 protocol" or a camera, a capacitance meter or a digital pet have to do with arithmetic cores. If that does not improve soon, I'll move my stuff to my own site. regards, Gerhard From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.50.6.78 with SMTP id y14mr15804064igy.3.1411462165419; Tue, 23 Sep 2014 01:49:25 -0700 (PDT) X-Received: by 10.182.70.39 with SMTP id j7mr46994obu.1.1411462165302; Tue, 23 Sep 2014 01:49:25 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed0.kamp.net!newsfeed.kamp.net!news.glorb.com!h15no4565988igd.0!news-out.google.com!bc9ni4973igb.0!nntp.google.com!h15no4565981igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Sep 2014 01:49:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=60.50.34.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 60.50.34.98 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <255c2ef4-efaf-40e4-a2c5-a79da9a3c338@googlegroups.com> Subject: Re: Is opencores.org dead? From: Daniel Kho Injection-Date: Tue, 23 Sep 2014 08:49:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7772 On Sunday, 21 September 2014 17:02:46 UTC+8, Nikolaos Kavvadias wrote: > Hi everyone, > > > > is www.opencores.org dead for you too? > > > > Seems to be down for the last 24h or 48h (at least). > > > > There is http://www.freerangefactory.org/cores/ of course, but this is just a snapshot from 2012 (or so). Not to mention having personal projects etc > > > > BTW I haven't checked the SVN server yet. > > > > > > Best regards > > Nikolaos Kavvadias > > http://www.nkavvadias.com Works for me too... I remember visiting it a couple of days ago, and it was working. -daniel From newsfish@newsfish Tue Dec 29 16:43:33 2015 X-Received: by 10.42.36.69 with SMTP id t5mr1477674icd.11.1411473941555; Tue, 23 Sep 2014 05:05:41 -0700 (PDT) X-Received: by 10.182.165.8 with SMTP id yu8mr4076obb.9.1411473941380; Tue, 23 Sep 2014 05:05:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4680141igd.0!news-out.google.com!rp1ni1450igb.0!nntp.google.com!a13no2093210igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 23 Sep 2014 05:05:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:7:1680:eb1:5423:d794:db04:1bcd; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 2601:7:1680:eb1:5423:d794:db04:1bcd User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about constant as input parameter? From: fl Injection-Date: Tue, 23 Sep 2014 12:05:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7773 Hi, I see the following code snippet on line. I realize that I may not understand VHDL key word "constant". If constant does not change, the logic uses constant does not change too. As a function like below, it must have input changing value: '0' or '1' in its application. How can it use constant as input parameter? Thanks, package body crc_package is function crc_shift0 -- Mike Treseler -- serial data version, see overload for parallel data below -- Purpose : Single bit shift for a CRC register using any polynomial. -- Inputs : X_load : Current CRC vector. -- D_bit : Data to shift into CRC vector. -- Poly : CRC polynomial. Default is Frame Relay. -- -- Outputs : CRC vector after CRC shift. ( constant X_load : in unsigned; -- register start value constant D_bit : in std_ulogic := '0'; -- input bit constant Poly : in unsigned := x"1021" --Poly_16_12_5 -- poly bits ) return unsigned is variable X_out : unsigned(X_load'range); -- CRC register begin ---------------------------------------------------------------------- From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!newsfeed0.kamp.net!newsfeed.kamp.net!newsfeed.freenet.ag!news.space.net!news.osn.de!diablo2.news.osn.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 23 Sep 2014 12:32:51 -0500 Date: Tue, 23 Sep 2014 18:32:51 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.1.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Question about constant as input parameter? References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 44 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-VCLr9++PPFlzgDnJFQ4mZXw+m+PwExeJEXByDlKyJqeARKVcl7yEz5kBedN4M1R4YHXFGZjHkmyKiCT!GaxK0FyV6XWpAS4EPrYk51ALT9Zvw4xuaQzOj+uMVNgi28COHCbnAAffU1mEI0+3vWBNpotF0MsQ!7D/knupmu8iXwPhYVUdG0tSX X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2744 Xref: news.eternal-september.org comp.lang.vhdl:7774 On 23/09/14 13:05, fl wrote: > Hi, > > I see the following code snippet on line. I realize that I may not understand > VHDL key word "constant". If constant does not change, the logic uses constant > does not change too. As a function like below, it must have input changing > value: '0' or '1' in its application. How can it use constant as input parameter? > > Thanks, > > > > > package body crc_package is > function crc_shift0 > -- Mike Treseler > -- serial data version, see overload for parallel data below > -- Purpose : Single bit shift for a CRC register using any polynomial. > -- Inputs : X_load : Current CRC vector. > -- D_bit : Data to shift into CRC vector. > -- Poly : CRC polynomial. Default is Frame Relay. > -- > -- Outputs : CRC vector after CRC shift. > ( > constant X_load : in unsigned; -- register start value > constant D_bit : in std_ulogic := '0'; -- input bit > constant Poly : in unsigned := x"1021" --Poly_16_12_5 -- poly bits > ) > return unsigned is > variable X_out : unsigned(X_load'range); -- CRC register > begin ---------------------------------------------------------------------- > A VHDL constant argument may be read inside a function or procedure, but may not be written. However each time the function is called, the argument may be given a different value, and hence the function will return a different result. regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.42.197.69 with SMTP id ej5mr9894998icb.7.1411607762000; Wed, 24 Sep 2014 18:16:02 -0700 (PDT) X-Received: by 10.140.105.53 with SMTP id b50mr98698qgf.3.1411607761864; Wed, 24 Sep 2014 18:16:01 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!a13no3202175igq.0!news-out.google.com!i10ni32qaf.0!nntp.google.com!w8no224868qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Sep 2014 18:16:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f385bac-6b86-45fc-bd07-4af5f6298fa3@googlegroups.com> Subject: Re: Question about constant as input parameter? From: Andy Injection-Date: Thu, 25 Sep 2014 01:16:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7775 There are three kinds of subprogram arguments: constant, variable and signal. By default, function arguments are of kind constant, and always of mode in. Constant kind arguments must be of mode in, and can be associated with any expression of constant(s), variable(s) and/or signal(s). Variable kind can only be associated with a variable actual, and signal kind can only be associated with a signal actual. Procedure out/inout ports default to variable kind. If a procedure spans time (contains a wait statement) and needs to receive updates on an in/inout argument after it is called, or to update an inout/output before it returns, then a signal kind must be used. Unlike argument types, modes or formal names, argument kinds are not used for compiler selection between multiple overloaded subprograms (signature matching). Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.70.41.162 with SMTP id g2mr4925350pdl.2.1411684875206; Thu, 25 Sep 2014 15:41:15 -0700 (PDT) X-Received: by 10.140.23.228 with SMTP id 91mr37734qgp.19.1411684874946; Thu, 25 Sep 2014 15:41:14 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6846882igd.0!news-out.google.com!i10ni32qaf.0!nntp.google.com!w8no294843qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Sep 2014 15:41:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> Subject: PSL help please From: niv Injection-Date: Thu, 25 Sep 2014 22:41:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7776 Trying to get started with PSL assertions. I've written a simple counter, code below, with a couple of PSL assertions at the end. However, the 2nd assertion fails on the transition from cntr_max-1 to cntr_max, but the rollover assertion seems to work. Any ideas please? LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL; -------------------------------------------------------------------------------- ENTITY psl_counter_test IS GENERIC( my_width : NATURAL := 6 ); PORT( rst : IN STD_LOGIC; clk : IN STD_LOGIC; my_count : OUT STD_LOGIC_VECTOR (my_width-1 DOWNTO 0) ); END ENTITY psl_counter_test ; -------------------------------------------------------------------------------- ARCHITECTURE rtl OF psl_counter_test IS SIGNAL my_counter : UNSIGNED(my_width-1 DOWNTO 0); SIGNAL en_counter : UNSIGNED(3 DOWNTO 0); SIGNAL enable : STD_LOGIC; CONSTANT cntr_max : NATURAL := 2**my_width - 1; BEGIN my_count <= STD_LOGIC_VECTOR(my_counter); -------------------------------------------------------------------------------- count_en : PROCESS (rst, clk) BEGIN IF rst = '1' THEN en_counter <= (OTHERS => '0'); -- reset to max enable <= '0'; ELSIF RISING_EDGE(clk) THEN en_counter <= en_counter + 1; -- rolls over, so div by 64. IF en_counter = 15 THEN enable <= '1'; ELSE enable <= '0'; END IF; END IF; END PROCESS count_en; -------------------------------------------------------------------------------- count_up : PROCESS (rst, clk) BEGIN IF rst = '1' THEN my_counter <= (OTHERS => '0'); -- reset to max ELSIF RISING_EDGE(clk) THEN IF enable = '1' THEN my_counter <= my_counter + 1; -- continuous count with rollover. ELSE NULL; END IF; END IF; END PROCESS count_up; -------------------------------------------------------------------------------- -- psl begin -- -- default clock is rising_edge(clk); -- -- property psl_01 is -- ({(my_counter = cntr_max) and (enable = '1')} |=> {my_counter = 0} ); -- assert always psl_01 report"ERROR: 'my_counter' did not rollover to zero."; -- -- property psl_02 is -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; -- -- end END ARCHITECTURE rtl; From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.52.181.200 with SMTP id dy8mr11869521vdc.8.1411713151139; Thu, 25 Sep 2014 23:32:31 -0700 (PDT) X-Received: by 10.140.34.208 with SMTP id l74mr153954qgl.1.1411713151080; Thu, 25 Sep 2014 23:32:31 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no310181qac.0!news-out.google.com!i10ni37qaf.0!nntp.google.com!w8no310180qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 25 Sep 2014 23:32:30 -0700 (PDT) In-Reply-To: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66ebd0b8-659f-49ef-90da-0624b3b054f3@googlegroups.com> Subject: Re: PSL help please From: niv Injection-Date: Fri, 26 Sep 2014 06:32:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4244 X-Received-Body-CRC: 180135188 Xref: news.eternal-september.org comp.lang.vhdl:7777 On Thursday, 25 September 2014 23:41:21 UTC+1, niv wrote: > Trying to get started with PSL assertions. > > > > I've written a simple counter, code below, with a couple of PSL assertions at the end. However, the 2nd assertion fails on the transition from cntr_max-1 to cntr_max, but the rollover assertion seems to work. > > Any ideas please? > > > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.all; > > USE ieee.numeric_std.ALL; > > -------------------------------------------------------------------------------- > > ENTITY psl_counter_test IS > > GENERIC( > > my_width : NATURAL := 6 > > ); > > PORT( > > rst : IN STD_LOGIC; > > clk : IN STD_LOGIC; > > my_count : OUT STD_LOGIC_VECTOR (my_width-1 DOWNTO 0) > > ); > > > > END ENTITY psl_counter_test ; > > -------------------------------------------------------------------------------- > > ARCHITECTURE rtl OF psl_counter_test IS > > SIGNAL my_counter : UNSIGNED(my_width-1 DOWNTO 0); > > SIGNAL en_counter : UNSIGNED(3 DOWNTO 0); > > SIGNAL enable : STD_LOGIC; > > CONSTANT cntr_max : NATURAL := 2**my_width - 1; > > BEGIN > > my_count <= STD_LOGIC_VECTOR(my_counter); > > -------------------------------------------------------------------------------- > > count_en : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > en_counter <= (OTHERS => '0'); -- reset to max > > enable <= '0'; > > ELSIF RISING_EDGE(clk) THEN > > en_counter <= en_counter + 1; -- rolls over, so div by 64. > > IF en_counter = 15 THEN > > enable <= '1'; > > ELSE > > enable <= '0'; > > END IF; > > END IF; > > END PROCESS count_en; > > -------------------------------------------------------------------------------- > > count_up : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > my_counter <= (OTHERS => '0'); -- reset to max > > ELSIF RISING_EDGE(clk) THEN > > IF enable = '1' THEN > > my_counter <= my_counter + 1; -- continuous count with rollover. > > ELSE > > NULL; > > END IF; > > END IF; > > END PROCESS count_up; > > -------------------------------------------------------------------------------- > > -- psl begin > > -- > > -- default clock is rising_edge(clk); > > -- > > -- property psl_01 is > > -- ({(my_counter = cntr_max) and (enable = '1')} |=> {my_counter = 0} ); > > -- assert always psl_01 report"ERROR: 'my_counter' did not rollover to zero."; > > -- > > -- property psl_02 is > > -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); > > -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; > > -- > > -- end > > END ARCHITECTURE rtl; Note; some of the comments for size etc are wrong, I cut code down to make simple example. From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> In-Reply-To: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140925-1, 25/09/2014), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1411721501 86.17.210.161 (Fri, 26 Sep 2014 08:51:41 UTC) NNTP-Posting-Date: Fri, 26 Sep 2014 08:51:41 UTC Organization: virginmedia.com Date: Fri, 26 Sep 2014 09:51:38 +0100 X-Received-Body-CRC: 462947981 X-Received-Bytes: 1970 Xref: news.eternal-september.org comp.lang.vhdl:7778 On 25/09/2014 23:41, niv wrote: > Trying to get started with PSL assertions. > > I've written a simple counter, code below, with a couple of PSL assertions at the end. However, the 2nd assertion fails on the transition from cntr_max-1 to cntr_max, but the rollover assertion seems to work. > Any ideas please? .. snip > -- property psl_02 is > -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); When my_counter reaches 62 and enable is asserted you are effectively checking that in the next cycle my_counter(which is now 63)+1=64 which of course will never happen. You probably wanted to write: |=> {prev(my_counter) + 1} The prev() operator return the value from the previous cycle. You might also want to add an abort operator for your reset, Good luck, Hans www.ht-lab.com > -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; > -- > -- end > END ARCHITECTURE rtl; > From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.70.96.239 with SMTP id dv15mr23225908pdb.3.1411807687021; Sat, 27 Sep 2014 01:48:07 -0700 (PDT) X-Received: by 10.140.89.239 with SMTP id v102mr409qgd.34.1411807686437; Sat, 27 Sep 2014 01:48:06 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7835614igd.0!news-out.google.com!i10ni38qaf.0!nntp.google.com!k15no91606qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 27 Sep 2014 01:48:06 -0700 (PDT) In-Reply-To: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> Subject: Re: PSL help please From: niv Injection-Date: Sat, 27 Sep 2014 08:48:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7779 On Thursday, September 25, 2014 11:41:21 PM UTC+1, niv wrote: > Trying to get started with PSL assertions. > > > > I've written a simple counter, code below, with a couple of PSL assertions at the end. However, the 2nd assertion fails on the transition from cntr_max-1 to cntr_max, but the rollover assertion seems to work. > > Any ideas please? > > > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.all; > > USE ieee.numeric_std.ALL; > > -------------------------------------------------------------------------------- > > ENTITY psl_counter_test IS > > GENERIC( > > my_width : NATURAL := 6 > > ); > > PORT( > > rst : IN STD_LOGIC; > > clk : IN STD_LOGIC; > > my_count : OUT STD_LOGIC_VECTOR (my_width-1 DOWNTO 0) > > ); > > > > END ENTITY psl_counter_test ; > > -------------------------------------------------------------------------------- > > ARCHITECTURE rtl OF psl_counter_test IS > > SIGNAL my_counter : UNSIGNED(my_width-1 DOWNTO 0); > > SIGNAL en_counter : UNSIGNED(3 DOWNTO 0); > > SIGNAL enable : STD_LOGIC; > > CONSTANT cntr_max : NATURAL := 2**my_width - 1; > > BEGIN > > my_count <= STD_LOGIC_VECTOR(my_counter); > > -------------------------------------------------------------------------------- > > count_en : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > en_counter <= (OTHERS => '0'); -- reset to max > > enable <= '0'; > > ELSIF RISING_EDGE(clk) THEN > > en_counter <= en_counter + 1; -- rolls over, so div by 64. > > IF en_counter = 15 THEN > > enable <= '1'; > > ELSE > > enable <= '0'; > > END IF; > > END IF; > > END PROCESS count_en; > > -------------------------------------------------------------------------------- > > count_up : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > my_counter <= (OTHERS => '0'); -- reset to max > > ELSIF RISING_EDGE(clk) THEN > > IF enable = '1' THEN > > my_counter <= my_counter + 1; -- continuous count with rollover. > > ELSE > > NULL; > > END IF; > > END IF; > > END PROCESS count_up; > > -------------------------------------------------------------------------------- > > -- psl begin > > -- > > -- default clock is rising_edge(clk); > > -- > > -- property psl_01 is > > -- ({(my_counter = cntr_max) and (enable = '1')} |=> {my_counter = 0} ); > > -- assert always psl_01 report"ERROR: 'my_counter' did not rollover to zero."; > > -- > > -- property psl_02 is > > -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); > > -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; > > -- > > -- end > > END ARCHITECTURE rtl; OK, I understand there is a "prev" command, but what I don't understand is why the assertion works (passes) for all values except the max-1 to max case. i.e. 0 to 1 ok, 1 to 2 ok........ 61 to 62 ok, but 62 to 63 fails. The special rollover assertion case works ok too. Niv. From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer03.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx03.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> In-Reply-To: <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 140926-2, 26/09/2014), Outbound message X-Antivirus-Status: Clean Lines: 26 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1411811604 86.17.210.161 (Sat, 27 Sep 2014 09:53:24 UTC) NNTP-Posting-Date: Sat, 27 Sep 2014 09:53:24 UTC Organization: virginmedia.com Date: Sat, 27 Sep 2014 10:53:20 +0100 X-Received-Body-CRC: 1304033263 X-Received-Bytes: 1959 Xref: news.eternal-september.org comp.lang.vhdl:7780 On 27/09/2014 09:48, niv wrote: > On Thursday, September 25, 2014 11:41:21 PM UTC+1, niv wrote: >> Trying to get started with PSL assertions. .. >> >> -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); >> >> -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; > > OK, I understand there is a "prev" command, but what I don't understand is why the assertion works (passes) for all values except the max-1 to max case. > i.e. 0 to 1 ok, 1 to 2 ok........ 61 to 62 ok, but 62 to 63 fails. Yes, but in the last case when my_counter=62 you are checking that in the next clock cycle (|=>) where my_counter has now changed to 63 you expect 63+1. Regards, Hans. www.ht-lab.com The special rollover assertion case works ok too. > > Niv. > From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.66.136 with SMTP id f8mr22014496pat.7.1412099645813; Tue, 30 Sep 2014 10:54:05 -0700 (PDT) X-Received: by 10.140.96.165 with SMTP id k34mr12459qge.29.1412099645721; Tue, 30 Sep 2014 10:54:05 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!uq10no1282050igb.0!news-out.google.com!i10ni54qaf.0!nntp.google.com!dc16no202549qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Sep 2014 10:54:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> Subject: Re: PSL help please From: Andy Injection-Date: Tue, 30 Sep 2014 17:54:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7781 IMHO, plain old procedural VHDL with assertion statements is so much easier to write and debug... Are you using PSL to support Formal Analysis? Andy From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.97.6 with SMTP id dw6mr41760466pab.23.1412103984208; Tue, 30 Sep 2014 12:06:24 -0700 (PDT) X-Received: by 10.140.101.235 with SMTP id u98mr15951qge.22.1412103984160; Tue, 30 Sep 2014 12:06:24 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!uq10no1330978igb.0!news-out.google.com!i10ni54qaf.0!nntp.google.com!dc16no207712qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Sep 2014 12:06:23 -0700 (PDT) In-Reply-To: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6a9626a6-7310-460b-815a-e250388553da@googlegroups.com> Subject: Re: PSL help please From: niv Injection-Date: Tue, 30 Sep 2014 19:06:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7782 On Thursday, September 25, 2014 11:41:21 PM UTC+1, niv wrote: > Trying to get started with PSL assertions. > > > > I've written a simple counter, code below, with a couple of PSL assertions at the end. However, the 2nd assertion fails on the transition from cntr_max-1 to cntr_max, but the rollover assertion seems to work. > > Any ideas please? > > > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.all; > > USE ieee.numeric_std.ALL; > > -------------------------------------------------------------------------------- > > ENTITY psl_counter_test IS > > GENERIC( > > my_width : NATURAL := 6 > > ); > > PORT( > > rst : IN STD_LOGIC; > > clk : IN STD_LOGIC; > > my_count : OUT STD_LOGIC_VECTOR (my_width-1 DOWNTO 0) > > ); > > > > END ENTITY psl_counter_test ; > > -------------------------------------------------------------------------------- > > ARCHITECTURE rtl OF psl_counter_test IS > > SIGNAL my_counter : UNSIGNED(my_width-1 DOWNTO 0); > > SIGNAL en_counter : UNSIGNED(3 DOWNTO 0); > > SIGNAL enable : STD_LOGIC; > > CONSTANT cntr_max : NATURAL := 2**my_width - 1; > > BEGIN > > my_count <= STD_LOGIC_VECTOR(my_counter); > > -------------------------------------------------------------------------------- > > count_en : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > en_counter <= (OTHERS => '0'); -- reset to max > > enable <= '0'; > > ELSIF RISING_EDGE(clk) THEN > > en_counter <= en_counter + 1; -- rolls over, so div by 64. > > IF en_counter = 15 THEN > > enable <= '1'; > > ELSE > > enable <= '0'; > > END IF; > > END IF; > > END PROCESS count_en; > > -------------------------------------------------------------------------------- > > count_up : PROCESS (rst, clk) > > BEGIN > > IF rst = '1' THEN > > my_counter <= (OTHERS => '0'); -- reset to max > > ELSIF RISING_EDGE(clk) THEN > > IF enable = '1' THEN > > my_counter <= my_counter + 1; -- continuous count with rollover. > > ELSE > > NULL; > > END IF; > > END IF; > > END PROCESS count_up; > > -------------------------------------------------------------------------------- > > -- psl begin > > -- > > -- default clock is rising_edge(clk); > > -- > > -- property psl_01 is > > -- ({(my_counter = cntr_max) and (enable = '1')} |=> {my_counter = 0} ); > > -- assert always psl_01 report"ERROR: 'my_counter' did not rollover to zero."; > > -- > > -- property psl_02 is > > -- ({(my_counter < cntr_max) and (enable = '1')} |=> {my_counter + 1} ); > > -- assert always psl_02 report"ERROR: 'my_counter' did not increment as expected."; > > -- > > -- end > > END ARCHITECTURE rtl; I sort of agree, but they're not as powerful or anywhere near as concise, but a bit of steep learning curve (& I'm at the very bottom). Both really; formal & simulation. However, once learnt (learned?) then PSL should be a powerful verification aid (I hope). Picked PSL rather than SVA as that means we wont need a mixed licence for simulator, just VHDL capable. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.182.91.69 with SMTP id cc5mr43312989obb.33.1412170924087; Wed, 01 Oct 2014 06:42:04 -0700 (PDT) X-Received: by 10.140.100.162 with SMTP id s31mr12278qge.17.1412170924060; Wed, 01 Oct 2014 06:42:04 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no171004igc.0!news-out.google.com!i10ni57qaf.0!nntp.google.com!s7no140566qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Oct 2014 06:42:03 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=4.30.68.10; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY NNTP-Posting-Host: 4.30.68.10 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Real Time Extraction in Simulation From: "M. Norton" Injection-Date: Wed, 01 Oct 2014 13:42:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7783 Good morning, I'm working on a signals testbench for a receiver. I started putting toget= her a cosine lookup table and some code to run an NCO based on a current se= tting of frequency. As I was leaving work yesterday I started thinking that maybe I'm going abo= ut this backwards, and could I create a signal in real numbers? It has som= e advantages of being more straightforward and much easier to create more s= ophisticated signals than CW (or multiple additions of CW). However I seem= to remember tinkering with this notion in the past and the major problem w= as finding out what the current time was. Since time is a physical type in VHDL, I seem to remember that when it conv= erts into a math type, it does so at its lowest physical quantized level, f= emtoseconds. Thus, it doesn't take a lot of time before femtoseconds overw= helm the integer type. I might be able to go straight to real but I'm goin= g to lose precision. Is there a simulator environment method of extracting the current simulatio= n time in real type rather than using "now"? Thanks, Mark Norton From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.227.135 with SMTP id sa7mr46307261pac.19.1412178242151; Wed, 01 Oct 2014 08:44:02 -0700 (PDT) X-Received: by 10.140.97.117 with SMTP id l108mr53127qge.3.1412178242060; Wed, 01 Oct 2014 08:44:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1931934igb.0!news-out.google.com!i10ni55qaf.0!nntp.google.com!dc16no267946qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Oct 2014 08:44:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4d24f5b6-f677-47eb-bb42-0a6c7824556a@googlegroups.com> Subject: Re: Real Time Extraction in Simulation From: KJ Injection-Date: Wed, 01 Oct 2014 15:44:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7784 On Wednesday, October 1, 2014 9:42:07 AM UTC-4, M. Norton wrote: > > Is there a simulator environment method of extracting the current simulation > time in real type rather than using "now"? > a <= real(now / 1 ps); -- For 1 ps accuracy a <= real(now / 1 ns); -- For 1 ns accuracy a <= real(now / 1 us); -- For 1 us accuracy etc. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.137.68 with SMTP id qg4mr44338289pab.26.1412187461847; Wed, 01 Oct 2014 11:17:41 -0700 (PDT) X-Received: by 10.140.21.230 with SMTP id 93mr14478qgl.25.1412187461800; Wed, 01 Oct 2014 11:17:41 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no2036495igb.0!news-out.google.com!i10ni55qaf.0!nntp.google.com!dc16no278631qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Oct 2014 11:17:41 -0700 (PDT) In-Reply-To: <4d24f5b6-f677-47eb-bb42-0a6c7824556a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=4.30.68.10; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY NNTP-Posting-Host: 4.30.68.10 References: <4d24f5b6-f677-47eb-bb42-0a6c7824556a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f54edeb-ae9c-452b-9d04-2e18c029652d@googlegroups.com> Subject: Re: Real Time Extraction in Simulation From: "M. Norton" Injection-Date: Wed, 01 Oct 2014 18:17:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7785 On Wednesday, October 1, 2014 10:44:05 AM UTC-5, KJ wrote: > On Wednesday, October 1, 2014 9:42:07 AM UTC-4, M. Norton wrote: > > > > > > Is there a simulator environment method of extracting the current simulation > > > time in real type rather than using "now"? > > > > > > > a <= real(now / 1 ps); -- For 1 ps accuracy > > a <= real(now / 1 ns); -- For 1 ns accuracy > > a <= real(now / 1 us); -- For 1 us accuracy > > etc. Alright, well that seems simple enough. Thank you. I'll try that out and see if I can make something interesting out of it. Mark From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx15.fr7.POSTED!not-for-mail From: Brian Drummond Subject: Re: Real Time Extraction in Simulation Newsgroups: comp.lang.vhdl References: <4d24f5b6-f677-47eb-bb42-0a6c7824556a@googlegroups.com> <0f54edeb-ae9c-452b-9d04-2e18c029652d@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lines: 35 Message-ID: NNTP-Posting-Host: 62.49.20.82 X-Complaints-To: abuse@demon.net X-Trace: 1412240824 62.49.20.82 (Thu, 02 Oct 2014 09:07:04 UTC) NNTP-Posting-Date: Thu, 02 Oct 2014 09:07:04 UTC Date: Thu, 02 Oct 2014 09:07:04 GMT X-Received-Body-CRC: 1872035995 X-Received-Bytes: 1891 Xref: news.eternal-september.org comp.lang.vhdl:7786 On Wed, 01 Oct 2014 11:17:41 -0700, M. Norton wrote: > On Wednesday, October 1, 2014 10:44:05 AM UTC-5, KJ wrote: >> On Wednesday, October 1, 2014 9:42:07 AM UTC-4, M. Norton wrote: >> >> >> > >> > Is there a simulator environment method of extracting the current >> > simulation >> >> > time in real type rather than using "now"? >> >> >> > >> >> >> a <= real(now / 1 ps); -- For 1 ps accuracy >> >> a <= real(now / 1 ns); -- For 1 ns accuracy >> >> a <= real(now / 1 us); -- For 1 us accuracy >> >> etc. > > Alright, well that seems simple enough. Thank you. I'll try that out > and see if I can make something interesting out of it. > You may need to set the simulator resolution appropriately to stop it rounding the physical unit. I had a 1kHz waveform simulating correctly in one simulator and producing 992Hz in another (and in synthesis!) because the clock period rounded down to nanoseconds (its default) before computing the counter compare value... - Brian From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.182.45.162 with SMTP id o2mr103710obm.20.1412256948911; Thu, 02 Oct 2014 06:35:48 -0700 (PDT) X-Received: by 10.140.100.162 with SMTP id s31mr11570qge.17.1412256948883; Thu, 02 Oct 2014 06:35:48 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no2561657igb.0!news-out.google.com!i10ni61qaf.0!nntp.google.com!dc16no329680qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 2 Oct 2014 06:35:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=4.30.68.10; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY NNTP-Posting-Host: 4.30.68.10 References: <4d24f5b6-f677-47eb-bb42-0a6c7824556a@googlegroups.com> <0f54edeb-ae9c-452b-9d04-2e18c029652d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55252dc4-93e2-448f-ac28-d1b72764ae71@googlegroups.com> Subject: Re: Real Time Extraction in Simulation From: "M. Norton" Injection-Date: Thu, 02 Oct 2014 13:35:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7787 On Thursday, October 2, 2014 4:07:08 AM UTC-5, Brian Drummond wrote: > On Wed, 01 Oct 2014 11:17:41 -0700, M. Norton wrote: > > > > > On Wednesday, October 1, 2014 10:44:05 AM UTC-5, KJ wrote: > > >> On Wednesday, October 1, 2014 9:42:07 AM UTC-4, M. Norton wrote: > > >> > > >> > > >> > > > >> > Is there a simulator environment method of extracting the current > > >> > simulation > > >> > > >> > time in real type rather than using "now"? > > >> > > >> > > >> > > > >> > > >> > > >> a <= real(now / 1 ps); -- For 1 ps accuracy > > >> > > >> a <= real(now / 1 ns); -- For 1 ns accuracy > > >> > > >> a <= real(now / 1 us); -- For 1 us accuracy > > >> > > >> etc. > > > > > > Alright, well that seems simple enough. Thank you. I'll try that out > > > and see if I can make something interesting out of it. > > > > > > > You may need to set the simulator resolution appropriately to stop it > > rounding the physical unit. I had a 1kHz waveform simulating correctly in > > one simulator and producing 992Hz in another (and in synthesis!) because > > the clock period rounded down to nanoseconds (its default) before > > computing the counter compare value... > > > > - Brian Yes I've run into that before, and every now and then when setting up a new machine because of the default 1 ns resolution in modelsim.ini. I typically have it set to picoseconds for the stuff I do. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.50.136.166 with SMTP id qb6mr7943749igb.5.1412340242402; Fri, 03 Oct 2014 05:44:02 -0700 (PDT) X-Received: by 10.140.40.85 with SMTP id w79mr553qgw.38.1412340242322; Fri, 03 Oct 2014 05:44:02 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1110224igc.0!news-out.google.com!i10ni60qaf.0!nntp.google.com!s7no282918qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 05:44:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.59.43.213; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 195.59.43.213 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> Subject: clear "endfile" flag? From: niv Injection-Date: Fri, 03 Oct 2014 12:44:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7788 I have a TBench that reads a file in a loop: i.e. while not endfile(my_file) ... ... However, later in the TBench, I need to read the file again, but it obviously see that the file has reached the end. How do I clear the endfile status please? Regards, Niv. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.191.233 with SMTP id hb9mr5053766pac.4.1412340616476; Fri, 03 Oct 2014 05:50:16 -0700 (PDT) X-Received: by 10.140.29.230 with SMTP id b93mr14098qgb.4.1412340616088; Fri, 03 Oct 2014 05:50:16 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no3222145igb.0!news-out.google.com!i10ni60qaf.0!nntp.google.com!s7no283304qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 05:50:16 -0700 (PDT) In-Reply-To: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.59.43.213; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 195.59.43.213 References: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> Subject: Re: clear "endfile" flag? From: niv Injection-Date: Fri, 03 Oct 2014 12:50:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1565 X-Received-Body-CRC: 4029614542 Xref: news.eternal-september.org comp.lang.vhdl:7789 On Friday, 3 October 2014 13:44:05 UTC+1, niv wrote: > I have a TBench that reads a file in a loop: > > > > i.e. while not endfile(my_file) > > > > ... > > ... > > > > However, later in the TBench, I need to read the file again, but it obviously see that the file has reached the end. > > > > How do I clear the endfile status please? > > > > Regards, Niv. Is it as simple as: endfile(my_file) <= FALSE; ??? Regards, Niv. From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx20.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.1.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> In-Reply-To: <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141003-0, 03/10/2014), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1412340780 86.17.210.161 (Fri, 03 Oct 2014 12:53:00 UTC) NNTP-Posting-Date: Fri, 03 Oct 2014 12:53:00 UTC Organization: virginmedia.com Date: Fri, 03 Oct 2014 13:52:56 +0100 X-Received-Body-CRC: 3168006914 X-Received-Bytes: 1767 Xref: news.eternal-september.org comp.lang.vhdl:7790 Hi Andy, On 30/09/2014 18:54, Andy wrote: > IMHO, plain old procedural VHDL with assertion statements is so much easier to write and debug... well.... perhaps, it all depends on the complexity of the assertion. You can write very simple PSL assertions and if you are already using OVL then the jump to PSL is not that difficult. The problem with PSL is that it requires an expensive license and hence not many engineers get access to it. > Are you using PSL to support Formal Analysis? Perhaps in the future when formal tools become more affordable, Regards, Hans. www.ht-lab.com > > Andy > From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.43.137.2 with SMTP id im2mr9568059icc.22.1412347734990; Fri, 03 Oct 2014 07:48:54 -0700 (PDT) X-Received: by 10.140.109.203 with SMTP id l69mr4967qgf.27.1412347734813; Fri, 03 Oct 2014 07:48:54 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no3285361igb.0!news-out.google.com!q8ni41qal.1!nntp.google.com!dc16no408955qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 07:48:54 -0700 (PDT) In-Reply-To: <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.188.153.114; posting-account=kPb-OQoAAABrjfR10Xor0FEhs2Rpst_8 NNTP-Posting-Host: 86.188.153.114 References: <3e3b5c9f-38da-4d94-bf82-d75e6f11eba7@googlegroups.com> <57acbcb9-82f8-4db4-ae9e-f7e5730664f4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0eafded7-b1a8-44f5-a622-fe22ff953046@googlegroups.com> Subject: Re: clear "endfile" flag? From: graham.p.ward@googlemail.com Injection-Date: Fri, 03 Oct 2014 14:48:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7791 I suggest that you close and re-open the file. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.182.191.36 with SMTP id gv4mr6681832obc.50.1412372471832; Fri, 03 Oct 2014 14:41:11 -0700 (PDT) X-Received: by 10.140.20.246 with SMTP id 109mr34682qgj.0.1412372471683; Fri, 03 Oct 2014 14:41:11 -0700 (PDT) Path: eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h18no1316399igc.0!news-out.google.com!q8ni41qal.1!nntp.google.com!dc16no462357qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 3 Oct 2014 14:41:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: <4930d71b-1b2f-4686-a11d-b69651878f1f@googlegroups.com> <7741882d-b5b7-4636-80b4-ff7746f7de28@googlegroups.com> <939fe762-14c5-4730-aa09-b7d7fb0f702d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <118dc6d0-4c1f-4185-834e-3d78cca2741e@googlegroups.com> Subject: Re: PSL help please From: Andy Injection-Date: Fri, 03 Oct 2014 21:41:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7792 Define "very simple" for real-world applications. If you mean "very short and cryptic," I agree completely. Andy From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.66.142.167 with SMTP id rx7mr4961284pab.12.1412614746405; Mon, 06 Oct 2014 09:59:06 -0700 (PDT) X-Received: by 10.50.57.11 with SMTP id e11mr143283igq.6.1412614746292; Mon, 06 Oct 2014 09:59:06 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5010962igb.0!news-out.google.com!bc9ni17237igb.0!nntp.google.com!h18no2183592igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Oct 2014 09:59:05 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.150.45; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.150.45 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: VHDL-2008 to -93 converter for synthesis From: Daniel Kho Injection-Date: Mon, 06 Oct 2014 16:59:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7793 Dear all, Recently I have built a small tool that eventually aims to give people the = ability to code synthesisable designs in VHDL-2008. The new P1076-2008 stan= dard has a whole bunch of new features that allow us to all write simple an= d concise designs. Many of us (me included) wouldn't want to go back to wri= ting '93 code if we hadn't needed to. Unfortunately, current synthesis supp= ort for VHDL-2008 is still lacking in many EDA tools. I like to change that, and hopefully many of you like to see better languag= e support in tools as well. An alpha version of the tool can be found here: http://www.tauhop.com (informational) http://www.tauhop.com/#!hls (the tool) Feel free to use it and test its features, currently limited to uninstantia= ted packages, generic packages, and generic types in packages. From the man= y requests I see in forums, I have decided that this is the area with which= I should focus on right now: VHDL-2008's enhanced generics, before moving = on to other features. Please let me know if there are any other specific '2008 features you like = me to spend some time on, and I will surely consider them to be added into = my roadmap. As many of you would understand, this effort is not trivial, and it does co= nsume a significant amount of my time per week. At this time, you may use t= he service for free on www.tauhop.com/#!hls but I request your kind support= in helping me bring food to the table, so I can continue working towards b= uilding something useful that all of you can use. There are a number of options you can help me financially. The webpage give= s you some options, but I also accept any arbitrary sum that you feel comfo= rtable with. Just write to me (daniel.kho tauhop.com) so we can work t= his out. One more thing. If you feel you could help me market this product, please g= et in touch as well. You will have a good share of the revenue you help gen= erate. Best regards, Daniel Kho Tauhop Solutions From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.50.134.137 with SMTP id pk9mr3022503igb.0.1412703367973; Tue, 07 Oct 2014 10:36:07 -0700 (PDT) X-Received: by 10.140.38.177 with SMTP id t46mr24907qgt.21.1412703367731; Tue, 07 Oct 2014 10:36:07 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no5894014igb.0!news-out.google.com!bc9ni17237igb.0!nntp.google.com!h18no2808292igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Oct 2014 10:36:07 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.176.51.135; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 46.176.51.135 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <98cd33e9-e9ec-4445-bce8-0cc0c802d62f@googlegroups.com> Subject: [RFC] METATOR - A look into processor synthesis From: Nikolaos Kavvadias Injection-Date: Tue, 07 Oct 2014 17:36:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.vhdl:7794 These last few months, I have been slowly moving back to my main interests,= EDA tools (as a developer and as a user), FPGA application engineering, an= d last but not least processor design. After a 5-year hiatus I have started= revamping (and modernizing) my own environment, developed as an outcome of= my PhD work on application-specific instruction-set processors (ASIPs). Th= e flow was based on SUIF/Machine-SUIF (compiler), SALTO (assembly-level tra= nsformations) and ArchC (architecture description language for producing bi= nary tools and simulators). It was a highly-successful flow that allowed me= (along with my custom instruction generator YARDstick) to explore configur= ations and extensions of processors with seconds or minutes. I have been thinking about what's next. We have tools to assist the designe= r (the processor design engineer per se) to speedup his/her development. St= ill, the processor must be designed explicitly. What would go beyond the st= ate-of-the-art is not to have to design the golden model of the processor a= t all. What I am proposing is an application-specific processor synthesis tool tha= t goes beyond the state-of-the-art. A model generator for producing the hig= h-level description of the processor, based only on application analysis an= d user-defined constraints. And for the fun of it, let's codename it METATO= R, because I tend to watch too much Supernatural these days, and METATOR (m= essenger) is a possible meaning for METATRON, an angelic being from the Apo= crypha with a human past. So think of METATOR as an upgrade (spiritual or n= ot) to the current status of both academic and commercial ASIP design tools= . 1. The Context, the Problem and its Solution ASIPs are tuned for cost-effective execution of targeted application sets. = An ASIP design flow involves profiling, architecture exploration, generatio= n and selection of functionalities and synthesis of the corresponding hardw= are while enabling the user taking certain decisions. The state-of-the-art in ASIP synthesis includes commercial efforts from Syn= opsys which has accumulated three relevant portfolios: the ARC configurable= processor cores, Processor Designer (previously LISATek) and the IP Design= er nML-based tools (previously Target Compiler Technologies); ASIPmeister b= y ASIP Solutions (site down?), Lissom/CodAL by Codasip, and the academic TC= E and NISC toolsets. Apologies if I have missed any other ASIP technology p= rovider! The key differentiation point of METATOR against existing approaches is tha= t ASIP synthesis should not require the explicit definition of a processor = model by a human developer. The solution implies the development of a novel= scheme for the extraction of a common denominator architectural model from= a given set of user applications (accounting for high-level constraints an= d requirements) that are intended to be executed on the generated processor= by the means of graph similarity extraction. From this automatically gener= ated model, an RTL description, verification IP and a programming toolchain= would be produced as part of an automated targeting process, in like "meta= -": a generated model generating models!. 2. Conceptual ASIP Synthesis Flow METATOR would accept as input the so-called algorithmic soup (narrow set of= applications) and generate the ADL (Architecture Description Language) des= cription of the processor. My first aim would be for ArchC but this could a= lso expand to the dominant ADLs, LISA 2.0 and nML. METATOR would rely upon HercuLeS high-level synthesis technology and the YA= RDstick profiling and custom instruction generation environment. In the pas= t, YARDstick has been used for generating custom instructions (CIs) for Byo= RISC (Build Your Own RISC) soft-core processors. ByoRISC is a configurable = in-order RISC design, allowing the execution of multiple-input, multiple-ou= tput custom instructions and achieving higher performance than typical VLIW= architectures. CIs for ByoRISC where generated by YARDstick, which purpose= is to perform application analysis on targeted codes, identify application= hotspots, extract custom instructions and evaluate their potential impact = on code performance for ByoRISC. = 3. Conclusion To sum this up, METATOR is a mind experiment in ASIP synthesis technology. = It automatically generates a full-fledged processor and toolchain merely fr= om its usage intent, expressed as indicative targeted application sets. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.182.241.2 with SMTP id we2mr8208162obc.38.1413585942945; Fri, 17 Oct 2014 15:45:42 -0700 (PDT) X-Received: by 10.140.100.150 with SMTP id s22mr1132qge.34.1413585942797; Fri, 17 Oct 2014 15:45:42 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!uq10no12765333igb.0!news-out.google.com!i10ni93qaf.0!nntp.google.com!s7no3497027qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 17 Oct 2014 15:45:42 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Handel-C to (VHDL or Verilog or EDIF) From: ahmedablak0@gmail.com Injection-Date: Fri, 17 Oct 2014 22:45:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7795 hi, I am trying to generate VHDL or Verlog or EDIF from Handel-C. I always end with an empty (VHDL,Verilog,EDIF) files. Any one faced this issue before ?? and how to solve it ?? Thanks From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.182.246.3 with SMTP id xs3mr15970231obc.13.1413747236242; Sun, 19 Oct 2014 12:33:56 -0700 (PDT) X-Received: by 10.140.84.21 with SMTP id k21mr3633qgd.6.1413747236093; Sun, 19 Oct 2014 12:33:56 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!uq10no13823324igb.0!news-out.google.com!i10ni95qaf.0!nntp.google.com!s7no3874903qap.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 19 Oct 2014 12:33:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.103.204.115; posting-account=YmCAXAoAAABbHW0Ist1dYHuAZjNjssNb NNTP-Posting-Host: 213.103.204.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> Subject: NFA FSM From: mohitkumar39@gmail.com Injection-Date: Sun, 19 Oct 2014 19:33:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: news.eternal-september.org comp.lang.vhdl:7796 Hi Guys! I am trying to code the following sequential re-coder/scrambler FSM in VHDL. 000 -> 110 001 -> 101 010 -> 111 011 -> 110 100 -> 010 101 -> 011 110 -> 010 111 -> 000 I understand this is an NFA and must be converted to DFA before implementing. I was able to convert into a DFA, but I am not sure how to assign the output for the merged states. Help on this would be appreciated. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.52.165.165 with SMTP id yz5mr21588153vdb.4.1413878038432; Tue, 21 Oct 2014 00:53:58 -0700 (PDT) X-Received: by 10.140.101.227 with SMTP id u90mr3498qge.18.1413878038371; Tue, 21 Oct 2014 00:53:58 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dc16no4340068qab.1!news-out.google.com!u5ni9qab.1!nntp.google.com!cm18no6693qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 00:53:58 -0700 (PDT) In-Reply-To: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Subject: Re: NFA FSM From: Thomas Stanka Injection-Date: Tue, 21 Oct 2014 07:53:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1911 X-Received-Body-CRC: 1938165863 Xref: news.eternal-september.org comp.lang.vhdl:7797 Am Sonntag, 19. Oktober 2014 21:33:58 UTC+2 schrieb mohitk...@gmail.com: > I am trying to code the following sequential re-coder/scrambler FSM in VH= DL. [..] > I understand this is an NFA and must be converted to DFA before implement= ing.=20 Why? Please explain on which details of the function you see the nondetermi= nstic behavior. In fact you have several possibilities, but I would use for the simple func= tion above a lookup table. If you consider the input as unsigned you could = just say that 0 =3D> 110, 1 =3D> 101 and so on, the conversion is than just= a lookup. Ofc you could also try to use karnaugh map to reduce the lookup = youself, but I'm sure for 3 bit input your sythesis tool will find best sol= ution. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: NFA FSM Date: Tue, 21 Oct 2014 10:20:06 +0200 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: <3745da2c-651e-4ca0-8e37-6e1ef6d976f5@googlegroups.com> <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Oct 2014 08:17:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7eb34cb03dab539a265635731164b0ad"; logging-data="6858"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19B0NMBgiWLntdfXJjwT3U9" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <7c6ee22d-643f-4dd5-8aab-29e457e503d8@googlegroups.com> Cancel-Lock: sha1:KjGrH84NvtRfVECtNxutUI9q71o= Xref: news.eternal-september.org comp.lang.vhdl:7798 I also would implement it as a LUT. But input 100 and 110 has the same output. I think one of both should be 001 on output. Then it seems a bit like Gray Counter, going backward. Best regards, Tobias From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.43.155.13 with SMTP id lg13mr9487976icc.31.1413899229635; Tue, 21 Oct 2014 06:47:09 -0700 (PDT) X-Received: by 10.182.72.161 with SMTP id e1mr1154obv.41.1413899229421; Tue, 21 Oct 2014 06:47:09 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!enother.net!enother.net!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no14931085igb.0!news-out.google.com!bc9ni31795igb.0!nntp.google.com!h18no8367675igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 06:47:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.171.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Subject: Simulation behavior for TestBench and UUT From: "V." Injection-Date: Tue, 21 Oct 2014 13:47:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1592 X-Received-Body-CRC: 2021999428 Xref: mx02.eternal-september.org comp.lang.vhdl:7799 At the top test bench level, I have something like this: PROCESS(clk, rst) BEGIN IF (rst = '1') THEN mytmp <= '1'; ELSIF RISING_EDGE(clk) THEN IF (busy = '1') THEN mytmp <= '0'; END IF; END IF; END PROCESS; At the top level, mytmp signal goes low on the same rising edge as my clock. -- I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. I am sure I am missing something very elementary here, could someone help me out? Thanks. From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT Date: Tue, 21 Oct 2014 10:05:11 -0400 Organization: Alacron, Inc. Lines: 34 Message-ID: References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Oct 2014 14:05:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="17244"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+eaQy+0sYIBl+7ZyGPqgW2ZISLCiMzVB0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Cancel-Lock: sha1:61QaVcoxLQvehfIWGOXRw5edyOk= Xref: mx02.eternal-september.org comp.lang.vhdl:7800 V. wrote: > At the top test bench level, I have something like this: > > PROCESS(clk, rst) > BEGIN > IF (rst = '1') THEN > mytmp <= '1'; > ELSIF RISING_EDGE(clk) THEN > IF (busy = '1') THEN > mytmp <= '0'; > END IF; > END IF; > END PROCESS; > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > -- > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > I am sure I am missing something very elementary here, could someone help me out? > > > Thanks. You say "the same rising edge as my clock" which doesn't say anything to me. Do you mean that in the test bench there is no delay from the assertion of "busy" to "mytmp" going low? How is busy driven in the test bench? How is it driven in the UUT? My guess is that one has a simple time-based driver and the other gets it (after a delta delay) from an edge-triggered process. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.70.131.230 with SMTP id op6mr22482819pdb.4.1413902788810; Tue, 21 Oct 2014 07:46:28 -0700 (PDT) X-Received: by 10.182.215.136 with SMTP id oi8mr182883obc.0.1413902788617; Tue, 21 Oct 2014 07:46:28 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no14965608igb.0!news-out.google.com!bc9ni31795igb.0!nntp.google.com!h18no8387665igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 07:46:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Simulation behavior for TestBench and UUT From: "V." Injection-Date: Tue, 21 Oct 2014 14:46:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7801 On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor On Tuesday, October 21, 2014 9:05:29 AM UTC-5, Gabor Sz wrote: > V. wrote: > > > At the top test bench level, I have something like this: > > > > > > PROCESS(clk, rst) > > > BEGIN > > > IF (rst = '1') THEN > > > mytmp <= '1'; > > > ELSIF RISING_EDGE(clk) THEN > > > IF (busy = '1') THEN > > > mytmp <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > At the top level, mytmp signal goes low on the same rising edge as my clock. > > > > > > -- > > > > > > I then repeat this code within my UUT (still instantiated by same testbench), but now mytmp signal goes low on the following rising edge clock after busy is asserted. > > > > > > I am sure I am missing something very elementary here, could someone help me out? > > > > > > > > > Thanks. > > > > You say "the same rising edge as my clock" which doesn't say anything > > to me. Do you mean that in the test bench there is no delay from the > > assertion of "busy" to "mytmp" going low? How is busy driven in the > > test bench? How is it driven in the UUT? My guess is that one has > > a simple time-based driver and the other gets it (after a delta delay) > > from an edge-triggered process. > > > > -- > > Gabor Sorry , I had meant to say: "At the top level, mytmp signal goes low on the same rising edge as busy". As you say, there is no delay from the assertion of "busy" to "mytmp" going low. --- Busy is generated by UUT (via clocked process), and sent out as an output to the testbench. It is essentially the same signal. The clk signal is also generated internally by UUT, and sent out to testbench. I'm using Modelsim as my simulator if it makes a difference. From newsfish@newsfish Tue Dec 29 16:43:34 2015 X-Received: by 10.236.61.132 with SMTP id w4mr25475377yhc.2.1413943523620; Tue, 21 Oct 2014 19:05:23 -0700 (PDT) X-Received: by 10.182.215.229 with SMTP id ol5mr204389obc.3.1413943523520; Tue, 21 Oct 2014 19:05:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!cm18no216712qab.0!news-out.google.com!ks2ni146igb.0!nntp.google.com!uq10no15312304igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Oct 2014 19:05:13 -0700 (PDT) In-Reply-To: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <113be19a-7e95-4c09-a7fa-90fad11f98ae@googlegroups.com> Subject: Re: Simulation behavior for TestBench and UUT From: KJ Injection-Date: Wed, 22 Oct 2014 02:05:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 47 Xref: mx02.eternal-september.org comp.lang.vhdl:7802 On Tuesday, October 21, 2014 9:47:11 AM UTC-4, V. wrote: > At the top test bench level, I have something like this:=20 >=20 > PROCESS(clk, rst) > BEGIN > IF (rst =3D '1') THEN > mytmp <=3D '1'; =20 > ELSIF RISING_EDGE(clk) THEN > IF (busy =3D '1') THEN > mytmp <=3D '0'; > END IF; > END IF; > END PROCESS; >=20 > At the top level, mytmp signal goes low on the same rising edge as my clo= ck.=20 >=20 >=20 > I then repeat this code within my UUT (still instantiated by same testben= ch),=20 > but now mytmp signal goes low on the following rising edge clock after bu= sy=20 > is asserted. >=20 > I am sure I am missing something very elementary here, could someone help= me out?=20 >=20 What you're missing is that when your testbench code hits the line 'IF (bus= y =3D '1') THEN...' the rising edge of the clock has already occurred and t= he subsequent assignment to 'mytmp' will not occur until one simulation del= ta after the rising edge of the clock. Now consider the UUT. If 'mytmp' d= oes not change until after the rising edge of the clock then really it won'= t be looked at again until the NEXT rising edge. In order to see this more= clearly, simply change the assignment to 'mytmp' to include some non-zero = delay like this 'mytmp <=3D '0' after 2 ns;'. Your testbench and UUT will = respond identically based on what you described.=20 But before you go thinking that you somehow need to curse simulation deltas= realize that what you're describing in the code you posted is a form of a = flip flop where 'busy' is an input. The 'D' input to a flip flop always sw= itches on the previous clock cycle relative to the 'Q' output of that flip = flop. There is nothing inherently wrong here unless the protocol of your s= ignals is that 'mytmp' should occur on the same clock cycle as 'busy'. If = that's the case, then 'mytmp' should be a concurrent statement, not inside = a clocked process. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: [cross-post] verification vs design Followup-To: comp.arch.fpga Date: 22 Oct 2014 08:10:37 GMT Lines: 34 Message-ID: X-Trace: individual.net 2XO2ltchnXz1RFBrYx/grg8DQHnpZ2hiO0OTygcNILUQVsm2Dn Keywords: verification,fpga X-Orig-Path: not-for-mail Cancel-Lock: sha1:8Zrf5EACgS4/1/1nRIUq/urigJM= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.arch.fpga:21099 comp.lang.vhdl:7803 Hi everyone, I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification. If you ask the FPGA developer he'd say a factor of 2/3 has to be considered for verification w.r.t. design (that I tend to agree to). I'd like to give some grounds to those estimates and I asked the fpga group leader to compare among several completed projects what is this ratio. We are usually collecting lots of data on the amount and type of work we do every day and this data can be used to verify the verification effort w.r.t. the design effort. His counter argument is that it is difficult to compare projects due to their peculiarity, implying that there's very little that we can learn from the past (that I obviously do not buy!). As of your knowledge is there any source of - trusted - data that I can point at? Is there really a ratio that can be 'generally' applied? Any comment/opinion/pointer is appreciated. Al p.s.: this thread is intentially crossposted to comp.lang.vhdl and comp.arch.fpga. Please use the followup-to field in order to avoid breaking the thread. -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT Date: Wed, 22 Oct 2014 09:50:14 -0400 Organization: Alacron, Inc. Lines: 22 Message-ID: References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 22 Oct 2014 13:50:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="29896"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/2TExtqMjuR3ElJNhdEJOXQbXB0sQgbGY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:oLAFnhypG4Bq17/SesnKOs8/QKY= Xref: mx02.eternal-september.org comp.lang.vhdl:7804 V. wrote: > > Sorry , I had meant to say: > "At the top level, mytmp signal goes low on the same rising edge as busy". > > As you say, there is no delay from the assertion of "busy" to "mytmp" going low. > > --- > > Busy is generated by UUT (via clocked process), and sent out as an output to the testbench. It is essentially the same signal. > > The clk signal is also generated internally by UUT, and sent out to testbench. I'm using Modelsim as my simulator if it makes a difference. Then you need to see how the UUT generates the clock going back to the test bench. If the clock and the busy signal are generated at the same time, then you have in effect a race condition. If your UUT is supposed to drive this (in real hardware) to another device that requires setup and hold time with respect to the generated clock, you need to fix your design that there is some real delay in the busy output. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:34 2015 Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Thu, 23 Oct 2014 00:31:07 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Simulation behavior for TestBench and UUT References: <87c35f09-ec4d-4f0e-b94b-ebc911c609de@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 13 Message-ID: <54483023$0$2335$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Oct 2014 00:30:59 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1414017059 news-3.free.fr 2335 88.185.146.198:1091 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:7805 Le 21/10/2014 16:46, V. a écrit : [loads of snipped useless lines] > > Sorry , I had meant to say: > "At the top level, mytmp signal goes low on the same rising edge as busy". > > As you say, there is no delay from the assertion of "busy" to "mytmp" going low. Did you really need to quote the whole thread (with added blank lines, courtesy of this piece of sh*t that's Google groups) just to add these three lines ? Nicolas From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.50.111.170 with SMTP id ij10mr8012793igb.1.1414179189793; Fri, 24 Oct 2014 12:33:09 -0700 (PDT) X-Received: by 10.182.22.13 with SMTP id z13mr70486obe.5.1414179189565; Fri, 24 Oct 2014 12:33:09 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!uq10no16983661igb.0!news-out.google.com!ks2ni1344igb.0!nntp.google.com!uq10no16983659igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Oct 2014 12:33:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.15.159.241; posting-account=7508ugoAAAD0yBZ9X0HzJ1jhCKp4TH7N NNTP-Posting-Host: 129.15.159.241 References: <5dd17323.0204142133.2ac6e113@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: unsigned to bit_vector From: lesya.borowska@noaa.gov Injection-Date: Fri, 24 Oct 2014 19:33:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2545 X-Received-Body-CRC: 4222427127 Xref: mx02.eternal-september.org comp.lang.vhdl:7806 On Friday, April 19, 2002 6:40:44 AM UTC-5, Renaud Pacalet wrote: > chak a =E9crit : >=20 > > hi every body, > > could any body suggest me how to convert unsigned to bit > > vector...... and bitvector to unsigned with an exmaple.i will be > > very thank full thanx in advance > > chakri >=20 > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.NUMERIC_STD.all; > ... > signal BV: BIT_VECTOR(15 downto 0); > signal UV: UNSIGNED(1 to 16); > ... > BV <=3D TO_BITVECTOR(STD_ULOGIC_VECTOR(UV)); > UV <=3D UNSIGNED(TO_STDULOGICVECTOR(BV)); >=20 > As suggested by Egbert the FAQ is a good starting point if you want > to understand all this. >=20 > Regards. > --=20 > Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13 > Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.fr > ###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ###### Dear Renaud, I also need to convert unsigned to bit vector...... and bit vector to unsig= ned. Unfortunately, I need to use USE ieee.numeric_bit.all;=20 When I add=20 use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;=20 my program gives me an error (vcom-1078) Identifier "unsigned" is not direc= tly visible. Do you know any other way to unsigned to bit vector...... and bit vector to= unsigned using USE ieee.numeric_bit.all; Thanks! Have a nice evening, Lesya From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.68.135.99 with SMTP id pr3mr9566228pbb.9.1414191304897; Fri, 24 Oct 2014 15:55:04 -0700 (PDT) X-Received: by 10.50.136.197 with SMTP id qc5mr86642igb.6.1414191304770; Fri, 24 Oct 2014 15:55:04 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no17071711igb.0!news-out.google.com!rp1ni2654igb.0!nntp.google.com!h18no9644641igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Oct 2014 15:55:04 -0700 (PDT) In-Reply-To: <5dd17323.0204142133.2ac6e113@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: <5dd17323.0204142133.2ac6e113@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: unsigned to bit_vector From: diogratia@gmail.com Injection-Date: Fri, 24 Oct 2014 22:55:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7807 On Monday, April 15, 2002 5:33:16 PM UTC+12, chak wrote: > hi every body, > could any body suggest me how to convert unsigned to bit vector...... > and bitvector to unsigned with an exmaple.i will be very thank full > thanx in advance > chakri With a context clause consisting of=20 library ieee; use ieee.numeric_bit.all; The conversion between the unsigned type declared in numeric_bit and bit_ve= ctor can be accomplished explicit type conversion between closely related t= ypes: entity foo is end entity; architecture fum of foo is signal unsigned_vector: unsigned (7 downto 0):=3D "11001010"; signal bit_val: bit_vector (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); end architecture; unsigned is defined as an array natural range of type bit in package numeri= c_bit while bit_vector is defined as an array natural range of type bit in = package standard. This makes the two types closely related, both arrays wi= th the same element type, dimensionality and index type. This context clause and associated entity/architecture pair analyzes, elabo= rates and simulates. Conversion to unsigned is also accomplished by explicit type conversion: architecture fie of foo is signal unsigned_vector: unsigned (7 downto 0):=3D "11001010"; signal bit_val: bit_vector (7 downto 0); signal un_signed: unsigned (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); un_signed <=3D unsigned(bit_val); end architecture; And this also analyzes, elaborates and simulates, differing from the previo= us architecture by doing conversion between unsigned and bit_vector and bit= _vector and unsigned. So as you can see from the rest of the answers you can see there is confusi= on on which declared unsigned to which you're referring. In those cases where you need to express a VHDL design specification with b= oth unsigned type declarations visible you could partition by visibility. F= or instance you could specify use clauses as process declarative items in a= process statement's process declarative part. You'd communicate between th= e two processes via signals declared from types visible in both declarative= regions. For example one process statement can have a use clause=20 use ieee.numeric_std.all; and use ieee.numeric_std.unsigned. While another process statement can have= =20 =20 use ieee.numeric_bit.all; and use ieee.numeric_bit.unsigned. You'd communicate between the two processes using signals whose types are v= isible to both declarations (e.g. bit_vector, std_logic_vector). Any unsign= ed types would be variables declared as process declarative items. You could also use selected names: library ieee; use ieee.numeric_bit.all; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fuu is end entity; architecture fee of fuu is signal unsigned_vector: ieee.numeric_bit.unsigned (7 downto 0) :=3D "11001010"; signal bit_val: bit_vector (7 downto 0); signal un_signed: ieee.numeric_bit.unsigned (7 downto 0); signal unsigned_slv: ieee.numeric_std.unsigned (7 downto 0); signal bit_unsigned: ieee.numeric_bit.unsigned (7 downto 0); begin bit_val <=3D bit_vector(unsigned_vector); un_signed <=3D ieee.numeric_bit.unsigned(bit_val); unsigned_slv <=3D ieee.numeric_std.unsigned(to_stdlogicvector(bit_val))= ; bit_unsigned <=3D ieee.numeric_bit.unsigned( to_bitvector(std_logic_vector(unsigned_slv)) ); end architecture; Selected names overcome the issue of ambiguity with two types named unsigne= d. (And this example also analyzes, elaborates and simulates) From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.52.188.67 with SMTP id fy3mr22305240vdc.5.1414439959900; Mon, 27 Oct 2014 12:59:19 -0700 (PDT) X-Received: by 10.50.43.233 with SMTP id z9mr265569igl.5.1414439959747; Mon, 27 Oct 2014 12:59:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no995138qap.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no388278igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 Oct 2014 12:59:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.150.156; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.150.156 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Subject: Finally some VHDL-2008 support in Xilinx Vivado From: Daniel Kho Injection-Date: Mon, 27 Oct 2014 19:59:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: mx02.eternal-september.org comp.lang.vhdl:7808 Just received word that Xilinx has implemented some features of VHDL-2008 in their Vivado tool. Some of you guys may be interested to try these new compiler features. I am sure to be trying them out: http://www.xilinx.com/support/answers/62005.html Cheers, dan From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.67.4.3 with SMTP id ca3mr8901322pad.23.1414614834251; Wed, 29 Oct 2014 13:33:54 -0700 (PDT) X-Received: by 10.182.79.104 with SMTP id i8mr33119obx.21.1414614834147; Wed, 29 Oct 2014 13:33:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no1542692igi.0!news-out.google.com!ks2ni6272igb.0!nntp.google.com!r10no1542686igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 13:33:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: An unconstrained array problem From: Weng Tianxiang Injection-Date: Wed, 29 Oct 2014 20:33:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7809 I have a problem with how to deal with an unconstrained array. Here is the code snippet: Package A_package is constant DATA_OUT_WIDTH : positive := 8; -- data out width type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDTH-1 downto 0); end A_package; -- B_module would be used as a VHDL system module shared by all designers entity B_module is generic ( MULTIPLE : positive := 1) port ( ... D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0); ... ); end B_module; architecture B of B_module is ... end B; If B_module is for use for one person or one company, there is no problem with VHDL-2002, what to do for a user to use B_module is to change DATA_OUT_WIDTH's value in A_package to meet his new width requirement for B_module. Now B_package is designed for all designers with VHDL and B_package is expected to be included into any VHDL system library. Problem comes! User cannot change DATA_OUT_WIDTH for OUT_DATA_ARRAY. What I want to do is: -- C_module would be used as a VHDL system module shared by all designers entity C_module is generic ( MULTIPLE : positive := 1; DATA_OUT_WIDTH : positive := 8; type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDTH-1 downto 0)) port ( ... D_I : in OUT_DATA_ARRAY(MULTIPLE-1 downto 0); ... ); end C_module; In other words,if new type definition can be introduced into generic, each time C_module is used, OUT_DATA_ARRAY can be any type a user wants. I think it is the easiest way to deal with unconstrained array while it complies with current VHDL grammar style. Two helps are needed: 1. For VHDL-2002, is there any method to resolve the problem? 2. For VHDL-2008, is there any method to resolve the problem as I suggested in C_module? Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.236.61.69 with SMTP id v45mr4499462yhc.57.1414628676532; Wed, 29 Oct 2014 17:24:36 -0700 (PDT) X-Received: by 10.51.16.65 with SMTP id fu1mr244899igd.10.1414628676288; Wed, 29 Oct 2014 17:24:36 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed0.kamp.net!newsfeed.kamp.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.112.MISMATCH!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no1496512qap.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no1857537igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 17:24:35 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <34fb902e-40fc-47b3-a776-ef8400a63a17@googlegroups.com> Subject: Re: An unconstrained array problem From: Jim Lewis Injection-Date: Thu, 30 Oct 2014 00:24:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1487 X-Received-Body-CRC: 3249745530 Xref: mx02.eternal-september.org comp.lang.vhdl:7810 Hi Weng, VHDL-2008 allows arrays to have unconstrained elements. Hence, you could have a package that defines type std_logic_matrix is array (natural range <>) of std_logic_vector ; And then constrain both dimensions in a signal or port: signal A : std_logic_matrix(5 downto 0)(7 downto 0) ; It is a VHDL-2008 feature, so synthesis vendor support may vary. Jim From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.50.43.228 with SMTP id z4mr22961180igl.4.1414631069227; Wed, 29 Oct 2014 18:04:29 -0700 (PDT) X-Received: by 10.50.118.9 with SMTP id ki9mr245955igb.16.1414631068924; Wed, 29 Oct 2014 18:04:28 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1872853igd.0!news-out.google.com!ks2ni4879igb.0!nntp.google.com!h15no1872850igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Oct 2014 18:04:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67a4efa8-9a75-4a41-8d73-ed67b8e11b92@googlegroups.com> Subject: Re: An unconstrained array problem From: Weng Tianxiang Injection-Date: Thu, 30 Oct 2014 01:04:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7811 Hi Jim, I haven't heard you for a long time. I hope to give you some new ideas in near future. Your comments are excellent and appreciated. Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Paul Colin de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: Finally some VHDL-2008 support in Xilinx Vivado Date: Fri, 31 Oct 2014 20:25:53 +0100 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="26902"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+HOli8JKOdni8Qwor1ejJTY6lRle9yArDWGclaaBR87g==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Cancel-Lock: sha1:V5WkN84HvioCcoKEWg5mDbEBpGE= X-X-Sender: gloster@anapnea.net Xref: mx02.eternal-september.org comp.lang.vhdl:7812 On 27th October 2014, Daniel Kho sent: |---------------------------------------------------------------------| |"Just received word that Xilinx has implemented some features of | |VHDL-2008 in their Vivado tool. Some of you guys may be interested to| |try these new compiler features. | | | |I am sure to be trying them out: | | http://www.xilinx.com/support/answers/62005.html | | | |Cheers, dan" | |---------------------------------------------------------------------| I would like to thank Dan for the good work he has been doing for standardizing VHDL. Cheers, Paul Colin From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: LRM: Double-block instantiations Date: Sun, 02 Nov 2014 11:14:39 +0200 Organization: A noiseless patient Spider Lines: 44 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 2 Nov 2014 09:14:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2749"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18fIhq3z7gv3JFGDdB3JVCsQcwyJcRAjoY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:EVl4vuFModEpvQfb0Ij7Emkhh04= Xref: mx02.eternal-september.org comp.lang.vhdl:7813 Specification says "A component instantiation is equivalent to a pair of nested block statements that couple the block hierarchy in the containing design unit to a unique copy of the block hierarchy contained in another design unit (i.e., the subcomponent). The outer block represents the component instantiation statement; the inner block represents the design entity to which the instance is bound. Each is defined by a block statement." You do not understand what is the issue unless first time look at the example entity X is port (P1, P2: inout BIT); constant Delay: TIME := 1 ms; begin ... end entity X; architecture Y of X is begin ... end architecture Y; Spec then specifies that instantiation C: entity Work.X (Y) port map (P1 => S1, P2 => S2); is identical to C: block -- Instance block. begin X: block -- Design entity block. port (P1, P2: inout BIT); -- Entity interface ports. port map (P1 => S1, P2 => S2); constant Delay: TIME := 1 ms; -- Entity declarative item. begin ... end block X; end block C; I wonder, what is the purpose of doing that and why everybody, eg. Modelsim, behave as there is only one block? For instant, I always used to refer C.P1 instead of C.X.P1 in whatever tool I use as if there is only one hierarchical block. From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.182.33.162 with SMTP id s2mr25642104obi.17.1414923932338; Sun, 02 Nov 2014 02:25:32 -0800 (PST) X-Received: by 10.140.17.69 with SMTP id 63mr2024qgc.10.1414923932156; Sun, 02 Nov 2014 02:25:32 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4009452igd.0!news-out.google.com!u5ni19qab.1!nntp.google.com!i13no688834qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 2 Nov 2014 02:25:32 -0800 (PST) In-Reply-To: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=91.7.99.227; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 91.7.99.227 References: <6ea001eb-0a91-4a4b-85f0-97853bf8b98a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c5523ff-d1a0-495b-abea-a41e4fa465db@googlegroups.com> Subject: Re: Finally some VHDL-2008 support in Xilinx Vivado From: capossio.leonardo@gmail.com Injection-Date: Sun, 02 Nov 2014 10:25:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7814 El lunes, 27 de octubre de 2014 20:59:21 UTC+1, Daniel Kho escribi=F3: > Just received word that Xilinx has implemented some features of VHDL-2008= in their Vivado tool. Some of you guys may be interested to try these new = compiler features. >=20 > I am sure to be trying them out: > http://www.xilinx.com/support/answers/62005.html >=20 > Cheers, dan Finally unconstrained element types. But it is still too early to use it in= any real design. Wish this was available two years ago. From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.224.156.69 with SMTP id v5mr225639qaw.1.1415041827866; Mon, 03 Nov 2014 11:10:27 -0800 (PST) X-Received: by 10.140.20.175 with SMTP id 44mr728195qgj.4.1415041827814; Mon, 03 Nov 2014 11:10:27 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!u7no2163561qaz.1!news-out.google.com!u5ni17qab.1!nntp.google.com!u7no2163560qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 3 Nov 2014 11:10:27 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.214.45.148; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 31.214.45.148 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Subject: Quartus II TCL or command line From: AA Injection-Date: Mon, 03 Nov 2014 19:10:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7815 Hi, how can I add vhdl files to quartus II project using TCL, or command line??? so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. Thank you, From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.66.222.135 with SMTP id qm7mr40040560pac.20.1415132400135; Tue, 04 Nov 2014 12:20:00 -0800 (PST) X-Received: by 10.50.20.198 with SMTP id p6mr306743ige.10.1415132399161; Tue, 04 Nov 2014 12:19:59 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no3878107igi.0!news-out.google.com!ks2ni7567igb.0!nntp.google.com!r10no3878087igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Nov 2014 12:19:58 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Subject: An English sentence? From: Weng Tianxiang Injection-Date: Tue, 04 Nov 2014 20:19:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7816 Hi, I am writing a paper now. I am not sure which English sentence is right in VHDL: signal A : std_logic; ... A <= '1'; 1. set A to '1'; -- I am now using. 2. set A equal to '1'; 3. set '1' to A; Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!news.astraweb.com!border5.a.newsrouter.astraweb.com!border2.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 04 Nov 2014 18:06:50 -0600 Date: Wed, 05 Nov 2014 00:06:50 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> In-Reply-To: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 33 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-9rPBO5n7j8ZZz2cZmnoqbRXS3vVkZQ2nHnnEanPK4xYmIPzIUN8GmttpuwlDcjDNP66WwmYrmH7AmW+!oT2Xm72vIMq6TBKvgtHXozu6WO6glC61SBVlsx2vuFNzmpd4iOQH9iesTdOVzVbidgaKdagq+EQ0!EFEOaeDI0h2URIbEMkdlBI8kNQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1675 Xref: mx02.eternal-september.org comp.lang.vhdl:7817 On 04/11/14 20:19, Weng Tianxiang wrote: > Hi, > > I am writing a paper now. I am not sure which English sentence is right in VHDL: > > signal A : std_logic; > > ... > > A <= '1'; > > 1. set A to '1'; -- I am now using. > 2. set A equal to '1'; > 3. set '1' to A; > > Thank you. > > Weng > Set A to '1' is fine, but I would probably say assign '1' to A or assign the value '1' to A simply because it is referred to as signal assignment in the standard, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? Date: Wed, 05 Nov 2014 15:50:29 +0200 Organization: An impatient and LOUD arachnid Lines: 12 Message-ID: References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="e5afc5bc4c110b3af5789ef5c59a038f"; logging-data="24749"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1958TlQlkNHa103I5V/JR6I" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:mwQdvLl0gVT/ZDOiIShdX8a6NwY= sha1:MkB6LgtonqFETxN+Bw9nlYidEaM= Xref: mx02.eternal-september.org comp.lang.vhdl:7818 Alan Fitch writes: > Set A to '1' is fine, but I would probably say > > assign '1' to A > or > assign the value '1' to A > > simply because it is referred to as signal assignment in the standard, OTOH, if the paper discusses generated hardware rather than pure VHDL, then I'd prefer set. From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.182.104.69 with SMTP id gc5mr45198054obb.18.1415201956972; Wed, 05 Nov 2014 07:39:16 -0800 (PST) X-Received: by 10.140.49.35 with SMTP id p32mr16284qga.38.1415201956888; Wed, 05 Nov 2014 07:39:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no6206026igd.0!news-out.google.com!u5ni24qab.1!nntp.google.com!u7no2608191qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 07:39:16 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.64.249.178; posting-account=hue4dgoAAAC_smvaZSxXtCW3n0mTOqMN NNTP-Posting-Host: 217.64.249.178 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e52d294-4e8d-4ef3-91b5-2cbb70d29d67@googlegroups.com> Subject: CAGNACCIO IN BORSA, TRUFFATORE, SEMPRE FALSO PAOLO BARRAI (BLOG "MERDATO" LIBERO). SBAGLIA SEMPRE A BREVE, MEDIO, LUNGO TERMINE! VALE 0 PURE COME SPECULATORE. VALE SOLO COME SPE-CULATONE": SODOMIZZA DA SEMPRE I FIGLI RICCARDO E COSTANZA BARRAI! From: marongiuguerrino@outlook.com Injection-Date: Wed, 05 Nov 2014 15:39:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 66193 X-Received-Body-CRC: 2332754446 Xref: mx02.eternal-september.org comp.lang.vhdl:7819 CAGNACCIO IN BORSA, TRUFFATORE, SEMPRE FALSO PAOLO BARRAI (BLOG "MERDATO" L= IBERO). SBAGLIA SEMPRE A BREVE, MEDIO, LUNGO TERMINE! VALE 0 PURE COME SPEC= ULATORE. VALE SOLO COME SPE-CULATONE": SODOMIZZA DA SEMPRE I FIGLI RICCARDO= E COSTANZA BARRAI! 1 Gruppo di risparmiatori truffati da bastardissimo criminale, pluiri pregiu= dicato, avanzo di galera Paolo Barrai ( Blog Mercato "Merdato" Libero). Da = incapace, delinquente, ladro, mega lava EURO mafiosi o "politicriminali", p= adanazista, berlusconazista, razzista, antisemita, super cocainomane, accla= rato pedofilo, frequente mandante di omicidi Paolo Barrai ( Mercato Libero = noto a tutto il mondo come Mer-d-ato Libero). Si, assolutamente, pure assas= sino Paolo Barrai ( "suicidatore" di David Rossi di Mps ma non solo). Schif= oso lava cash mafioso e killer Paolo Barrai nato a Milano il 28.6.1965. E, = prima di ora scappare come un vile ratto, a Lugano, in Svizzera (avendo pau= ra di venire arrestato, in quanto indagato da Procure di Mezza Italia) e fr= a poco ancora pi=F9 lontano: a Panama ( ove lo proteggerebbe il criminaliss= imo nazifascista corrottissimo ambasciatore lava EURO e $ mafiosi Giancarlo= Maria Curcio http://www.ambpanama.esteri.it/Ambasciata_Panama/Menu/Ambasciata/Ambasciato= re/ non per niente, vicino al noto camorrist-avanzo di galera Valter Lavitola http://www.ilfattoquotidiano.it/2012/05/01/ecco-legami-valter-lavitola-lamb= asciatore-curcio-panama/214621/ http://www.bergamonews.it/politica/lavitola-e-berlusconi-intercettazoni-e-r= icatti-hard-di-panama-183608 http://www.americaoggi.info/node/30265 https://it-it.facebook.com/notes/informazione-libera/le-pressioni-di-lavito= la-su-frattini-per-lamico-dilpomatico/10150360032099154?ref=3Dnf http://www.globalist.it/Detail_News_Display?ID=3D2828 http://www.affaritaliani.it/cronache/lavitola-e-berlusconi.html http://www.roccocipriano.it/wordpress/tag/lavitola). Verme repellente Paolo Barrai di Mercato Libero: facente sue terrificanti = delinquenze in cravatta da casa, presso Via Ippodromo 105 Milano. O DAGLI U= FFICI DI MALAVITOSA, MEGA LAVA SOLDI DI COSA NOSTRA, LADRONA, BASTARDAMENTE= CRIMINALE BSI ITALIA SRL DI VIA SOCRATE 26 MILANO. IN MANO A SUO PADRE, NO= TO PADANAZIS-T-RUFFATORE E PURE NOTO PEDERASTA VINCENZO BARRAI. ABITANTE IN= VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1938 2 Ciao, sono Antonella di Milano, e faccio parte di un foltissimo gruppo di = clienti derubati di tutto, dall'assolutamente criminale Paolo Barrai (Merca= to Libero, ormai noto nel mondo intero come Mer-d-ato Libero). Costui =E8 d= avvero un bastardo assassino sicario. A tutti noi, uniti ora in una associa= zione " Risparmiatori truffati da spietato criminale Paolo Barrai di Mercat= o Libero (e siamo gia' in centoventi, dico centiventi: di tutta Italia, Bra= sile, Germania e Svizzera)" ci fece andare corti ( al ribasso) sul mercato = azionario italiano a inizio 2009 (col Dow Jones ai minimi degli ultimi dece= nni: 6900; cosa che avrebbe potuto fare solo l'Ugo Fantozzi misto a Renato = Vallanzasca della Finanza: Paolo Barrai). Abbiam perso quasi tutti tra il 7= 0 e il 100 per cento dei nostri investimenti. E quando gli telefonavamo per= chiedere semplicemente che fare, mentre il mercato saliva rapidissimamente= , dal Marzo 2009 in avanti, egli, se non meglio dire, "esso", come un vile = ratto, scappava. Si faceva sempre negare al telefono. Mandavamo e mails, ne= ssuna risposta. Citofanavamo agli uffici di ultra truffatrice, ultra malavi= tosa, ultra ladrona Bsi Italia Srl di Via Socrate 26 a Milano di suo padre,= notoriamente pure pedofilo, oltre che mega ricicla soldi criminal-istituzi= onali o mafiosi, Vincenzo Barrai di Via Padova 282 a Milano, ci vedeva dall= a telecamera e nemmeno ci rispondeva. Nemmeno ci apriva il cancello di entr= ata. Io non sto offendendo, sto solo dicendo la mera verit=E0. E fra poco l= a faremo sapere a fior fior di Tribunali di mezza Italia, anzi, mezzo Piane= ta Terrra!!! Che i delinquenti ti debbano fare fessa, e pure non permettano= replica, no eeeee. Il neofascismo e la mafia del delinquente, del ladro, d= el truffatore, del professionalmente incapacissimo, del davvero bastardo de= ntro e fuori Paolo Barrai di Mercato Libero alias Mer-d-ato Libero, a noi n= on fa nessuna paura. Una truffata, derubata di tutto, dal verme assassino Paolo Barrai (gi=E0 r= iciclante soldi di Mafia, Camorra, Ndrangheta, come di mastodontici ladroci= nii o mega corruzione di Umberto Bossi e Silvio Berlusconi). Fra l=B4altro,= socio, non compare di malavita, ma socio di: arrestato Alessandro Proto http://www.ilfattoquotidiano.it/2013/02/14/manipolazione-del-mercato-arrest= ato-a-milano-finanziere-alessandro-proto/500117/ http://www.ilsole24ore.com/art/notizie/2013-02-14/arrestato-finanziere-ales= sandro-proto-185225.shtml?uuid=3DAbLGMWUH http://www.corriere.it/economia/13_febbraio_14/proto-arrestato-manipolazion= e-mercato_a6b59386-76cf-11e2-bad5-bab3677cbfcd.shtml http://www.repubblica.it/economia/finanza/2013/02/14/news/arrestato_anche_i= l_finanziere-immobiliarista_alessandro_proto-52651324/ http://www.unita.it/italia/arrestato-il-finanziere-br-alessandro-proto-1.48= 3688 arrestato Franco Fiorito http://www.ilfattoquotidiano.it/2012/10/02/fondi-lazio-arrestato-fiorito-ex= -capogruppo-regionale-pdl/369795/ http://www.corriere.it/politica/12_ottobre_02/arrestato-capogruppo-pdl-fior= ito_19f270a8-0c59-11e2-a61b-cf706c012f27.shtml http://www.youtube.com/watch?v=3DPVhVXILeQDw arrestato Francesco Belsito http://www.ilsole24ore.com/art/notizie/2013-04-24/arrestato-belsito-tesorie= re-lega-093844.shtml?uuid=3DAb3Bm4pH http://www.ilfattoquotidiano.it/2013/04/24/lega-arrestato-lex-tesoriere-bel= sito-per-associazione-a-delinquere-e-truffa-aggravata/573689/ http://milano.corriere.it/milano/notizie/cronaca/13_aprile_24/francesco-bel= sito-ex-tesoriere-lega-arrestato-212819720314.shtml detto questo detto tutto.. immaginerei!! Mi ha bruciato 700.000 euro. Tutto quello che avevo. Ma a tanti altri ha b= ruciato 1, 2, 3, 5, 7, 10 milioni di euro. Facendo comprare il gas naturale= a 5$ e passa, che in poche settimane crollava a 1,9$. Facendo vendere il D= ow Jones a 6900, ossia ai minimi di tanti ultimi anni. Dow Jones che ora qu= asi vale il doppio. E senza che lui prendesse telefonate, rispondesse ad em= ails. Senza dare indicazione alcuna a noi clienti terrorizzati! Come uno st= ruzzo che dalla paura e coscienza di essere incapacissimo a livello di fiut= o per investimenti, mette la testa sotto la sabbia. 3 Il verme brucia risparmi di una vita Paolo Barrai oltre ad essere il peggi= ore consulente per investimenti borsistici o di qualsiasi altro tipo, ove i= nesorabilmente sbaglia sempre (ha fatto comprare case in Brasile, a Porto S= eguro ... ove lo attendono 8 ANNI DI GALERA SE VI CI TORNA, E NE SCRIVER=D3= PRESTISSIMO.. dicevo... ha fatto comprare case in Brasile, a Porto Seguro,= col real a 2,1 contro l'euro.. e ora son state tutte sequestrate dall'anti= mafia Brasiliana, per mega riciclaggio per conto di Cosa Nostra, Camorra e= Ndrangheta.. e comunque, il real brasiliano =E8 passato dai massimi di 2,1= contro l'euro, livello di quando il cagnaccio idiota, brucia risparmi di u= na vita, Paolo Barrai, ha fatto comprare, financo a 3,2 contro euro.. crean= do perdite economiche immense, in ogni caso, a chi come " un ciuccio ei nap= ule" le avesse con lui acquistate). Ove mai, mai e ri mai ne azzecca mezza!= =C9 anche un irresponsabile, arrogante, nazista, razzista, lava soldi mafi= osi, codardo, ladro, truffatore, criminale, falsissimo, pedofilo, si, PEDOF= ILO PAOLO BARRAI (SE NO CHE BERLUSCONES SAREBBE, SCUSATE???)!!! ANCHE QUI L= O PROVER=D2 E PRESTISSIMO)!!!!!! E mi dicono che ha pregresse, pure varie condanne al carcere. A Milano (co= me da questi seguenti articoli: il criminalissimo "funzionario nei guai" di= Citibank, a seguito dell'arresto del suo "Kameraden Berlusconazisten und P= adanazisten" Pietro Terenzio, come da fine scritto che qui segue, =E8 assol= utissimamente lui: http://archiviostorico.corriere.it/2001/febbraio/02/Arrestato_imprenditore_= delle_truffe_fiscali_co_7_0102023408.shtml http://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi= -evasione-da-400-miliardi-terenzio-sotto-torchio.html). A Biella: http://www.finanzaonline.com/forum/messaggi-archiviati-fol/63768= 9-piccole-sim-con-l-acqua-alla-gola-bregliano-e-nuovi-investimenti.html Ed in Brasile, ove ha passato giornate e giornate in prigione nel Marzo 20= 11 e ove lo attendono ora, se vi ci torna: OTTO ANNI DI CARCERE! SENTENZIAT= ISSIMO!!! Come qui super provato, pure. E da siti di tutto il Globo terrest= re!!! http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D2996 http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D3000 http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D3004 http://portoseguroagora.blogspot.co.uk/2011/03/porto-seguro-o-blogueiro-ita= liano-sera.html http://noticiasdeportoseguro.blogspot.co.uk/2011/03/quem-e-pietro-paolo-bar= rai.html http://www.geraldojose.com.br/imprimir_noticia.php?cod_noticia=3D13950 http://www.emporto.com.br/index/noticia-aberta/id/8135 http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato.html http://www.uhnews.com.br/portal/ver/15604/3/blogueiro-suspeito-de-estiionat= o-e-investigado-pela-policia-civil.html http://www.osollo.com.br/online/index.php/crimes/3079-blogueiro-barrai-quer= -constituir-sindicato-so-para-estrangeiros-em-porto-seguro http://www.francodarochanews.jex.com.br/acontece+agora/policia+-+noticias+p= olicia+civil+investiga+blogueiro+suspeito+de+estelionato+blogueiro+paolo+ba= rrai+a+internet+esta+virando+cada+vez+mais+palco+para+crimes+e+investigacoe= s+que+ultrapassam+fronteiras+e+nacoes+a+policia+civil+de+porto+seguro+esta+= invest http://www.umbuzada.com/v2/imprimir_noticia.php?id=3D1869 http://inquisitore.org/2013/08/26/paolo-barrai-se-lo-conosci-lo-eviti/ http://www.consob.it/main/documenti/hide/afflittivi/pec/mercati/2013/d18579= .htm https://groups.google.com/forum/#!topic/mozilla.community.belgium/gq2RfnWxY= Nc https://groups.google.com/forum/#!search/$20PAOLO$20BARRAI$20POLLI/oc.jobs/= leUUVLIpKKQ/o7O-YQ72F9IJ http://it.comp.aiuto.narkive.com/krB4b8H3/faccendieri-mafiosi-alessandro-pr= oto-consulting-e-paolo-barrai-blog-mercato-mer-dato-libero-insieme- https://www.mail-archive.com/python@py.cz/msg06853.html http://newsgroups.derkeiler.com/Archive/Comp/comp.soft-sys.matlab/2013-06/m= sg00535.html http://list-archives.org/2013/06/23/bug-gnu-utils-gnu-org/da-arrestare-prim= a-che-faccia-ammazzare-ancora-paolo-barrai-di-mercato-libero-ha-ordinato-co= n-assassino-massimo-doris-mediolanum-lomicidio-di-david-rossi-x-1-guerra-di= -seo-lava-%E2%82%AC-di-mafia-camorra-ndrangheta-ll-lega-ladrona-pdl-popolo-= di-ladroni/f/4243206306 http://demo.njobsboard.com/consob-multa-di-ben-70-000-e-il-bastardo-assassi= no-paolo-barrai-mercato-libero-merdato-libero-ha-suicidato-david-rossi-mps-= lava-e-mafiosi-o-criminali-di-bossi-e-berlusconi-ladra-tr/ http://lists.scusting.com/index.php?t=3Dmsg&goto=3D1709843&S=3DGoogle#msg_1= 709843 http://list-archives.org/2013/06/23/bug-gnu-utils-gnu-org/da-arrestare-prim= a-che-faccia-ammazzare-ancora-paolo-barrai-di-mercato-libero-ha-ordinato-co= n-assassino-massimo-doris-mediolanum-lomicidio-di-david-rossi-x-1-guerra-di= -seo-lava-%E2%82%AC-di-mafia-camorra-ndrangheta-ll-lega-ladrona-pdl-popolo-= di-ladroni/f/4243206306 http://www.gossamer-threads.com/lists/python/python/1111003 http://lists.gnu.org/archive/html/bug-gnu-utils/2013-06/msg00001.html http://comments.gmane.org/gmane.comp.gnu.utils.bugs/18013 https://www.mail-archive.com/python@py.cz/msg06853.html http://newsgroups.derkeiler.com/Archive/Comp/comp.soft-sys.matlab/2013-06/m= sg00535.html http://it.comp.aiuto.narkive.com/krB4b8H3/faccendieri-mafiosi-alessandro-pr= oto-consulting-e-paolo-barrai-blog-mercato-mer-dato-libero-insieme- http://tech.money.pl/hi-tech/grupy/pl-misc-samochody/omicida-paolo-barrai-g= ia-in-galera-non-su-wikipedia-vuole-morte-131 http://www.cookingjunkies.com/alt-food-wine/verminoso-pederasta-paolo-barra= i-di-mercato-libero-si-vanta-di-inculare-sangue-i-figli-costanza-barrai-e-r= iccardo-barrai-da-quando-nati-ha-fatto-ammazzare-david-rossi-mps-lava-soldi= -di-mafia-e-lega-ladrona-infinter-bank-lugano-80177.html http://forums.terragame.com/VERMINOSO-PEDOFILO-PAOLO-BARRAI-DI-MERCATO-LIBE= RO-INCULA-FIG-ftopict8156.html http://lists.nongnu.org/archive/html/bug-cvs/2012-10/msg00001.html 4 Aaa, ad averlo saputo prima e non essermi fidata di sta bastarda, criminal= isssima Lega Nord =3D LL =3D Lega Ladrona, di cui ero parte, e che mi ha me= sso in contatto col loro affiliato mafioso, brucia risparmi di una vita e s= uper truffatore Paolo Barrai. Ora mi son sfogata qui. Presto lo ri far=F3 i= n fronte a Guardia di Finanza, Polizia, Carabinieri, Magistrati, Giudici! E= con me, almeno altre 120 persone! Oooo!! Non cascateci, ne scrivo proprio = per questo!!! Via subito e per sempre dal criminale, delinquente, ladro, tr= uffatore, professionalmente bestia: Paolo Barrai di Mercato Libero!!!!! E B= ASTA ANCHE CON STO EX PDL =3D POPOLO DI LADRONI!! E LL=3D LEGA LADRONA!!! C= APACI SOLO DI ACCUMULARE MAZZETTE DI FINMECCANICA, ENEL, ENI, ENAV, TECHNOS= KY, MAFIA, CAMORRA, NDRANGHETA, DITTATORI SU DITTATORI QUALI GHEDDAFI E NON= SOLO (COME DITTARORI SONO I VERMI BASTARDI ED ANCHE ASSASSINI, VI ASSICURO= : UMBERTO BOSSI E SILVIO BERLUSCONI)! E PER CENTINAIA DI MILIONI DI EURO! C= APACI SOLO DI FREGARE TONNELLATE DI SOLDI VIA QUOTE LATTE E RIMBORSI ELETTO= RALI! E POI METTERE TUTTO ALL'ESTERO PRESSO CRIMINALISSIMA FINTER BANK LUGA= NO DI DELINQUENTI IN CRAVATTA FILIPPO CRIPPA E GIOVANNI DEI CAS (MA DI CERT= O NON SOLO)!! O PRESSO SUPER LAVA SOLDI CRIMINALISSIMI, FINECO DI ALESSANDR= O FOTI. DEL BANCHIERE PREFERITO DA NDRANGHETA, CAMORRA E COSA NOSTRA: ALESS= ANDRO FOTI DI FINECO! E IL TUTTO PROPRIO ATTRAVERSO QUESTO COLLETTO VERMINO= SO, DA RINCHIUDERE IN GALERA E SUBITO, DI PAOLO BARRAI (CHE OLTRE A RICICLA= RE SOLDI CRIMINALISSIMI PRIMA CITATI, LO FA ANCHE PER I SUPER LADRONI LIGRE= STI DI SAI FONDIARIA..... OVE NON PER NIENTE LAVORAVA IL BANCHIERE CIELLINO= PREFERITO DA TUTTE LE MALAVITE: GIOVANNI RAIMONDI... ORA DI NETSYSTEM, EX = DI MALAVITOSISSIME BANCA SAI, GIOVANNI RAIMONDI SIM E GIOVANNI RAIMONDI AGE= NTE DI CAMBIO)! FRA L'ALTRO, IL PURE NOTISSIMO PEDOFILO PAOLO BARRAI (PEDOFILO COME IL PAD= RE VINCENZO BARRAI, PEDOFILO COME SILVIO BERLUSCONI, E QUINDI "BERLUSCONES = DOC" ANCHE DA QUESTO PUNTO DI VISTA, DIREI) SODOMIZZA DALLA NASCITA I FIGLI= COSTANZA BARRAI E RICCARDO BARRAI!!! IL SCHIFOSISSIMAMENTE PEDERASTA PAOLO= BARRAI INC-LA DALLA NASCITA COSTANZA BARRAI NATA A MILANO IL 1.1.1999. IL = VERMINOSAMENTE PEDERASTA PAOLO BARRAI SODOMIZZA DALLA NASCITA RICCARDO BARR= AI NATO A MILANO IL 26.11.1996. COME BEN SANNO TUTTI IN VIA IPPODROMO 105 A= MILANO OVE VIVONO!!! ED ANCHE QUI COL TUTTO PROVATISSIMO!!! NOTO AL MONDO = TUTTO!!!!!!! https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/qc.polit= ique/LpdB5tSf1dM/dfGem44vYVAJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/microsof= t.public.money/vHQMUCcJhik/yucEiMQMjAUJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/alt.pers= onals.vancouver/a_I9xd0OWZ8/NOzvsrlm2xoJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/it.polit= ica.pds/7sp6IUbsgVI/nPyc80sAwPEJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/microsof= t.public.es.win2000/ej7LBBvSNcQ/bZBqpUwnxVsJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/alt.true= -crime/K0t9JRZoM6Q/9bPC70ajn2EJ https://groups.google.com/forum/#!search/pedofilo$20paolo$20barrai/alt.drug= s.pot/YOazjqiK45w/A-asGK1epX8J Antonella di Milano. 5 PS 1 NON POCCO NON AGGIUNGERE, PER "QUASI" TERMINARE, CHE L'AVANZO DI GALERA, P= URE ASSASSINO PAOLO BARRAI ( HA FATTO SUICIDARE DAVID ROSSI DI MONTE PASCHI= PER UNA GUERRA DI SEO IN CORSO FRA DAVID ROSSI STESSO, E.. CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI MASSIMO DORIS = DI BANCA MEDIOLANUM https://groups.google.com/forum/#!search/MASSIMO$20DORIS$20MEDIOLANUM/it.co= mp.lang.c++/y8T62i1W4cA/GG83oXyfpboJ https://groups.google.com/forum/#!search/MASSIMO$20DORIS$20MEDIOLANUM/it.fa= n.startrek/FPuFR-ebkgA/qSiZMVTYZ7EJ CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI ENNIO DORIS DI= BANCA MEDIOLANUM https://groups.google.com/forum/#!search/ENNIO$20DORIS$20MEDIOLANUM/no-coke= -polesine/Pz7F0MCrwEQ/4-wsV_v5VBoJ https://groups.google.com/forum/#!search/ENNIO$20DORIS$20MEDIOLANUM/2012nat= o/KKH4ApmjJ_U/Jo6-HLPPQvcJ CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI EDOARDO LOMBAR= DI DI BANCA ESPERIA E BANCA MEDIOLANUM https://groups.google.com/forum/#!search/EDOARDO$20LOMBARDI$20MEDIOLANUM%7C= sort:relevance%7Cspell:true/it.comp.lang.javascript/Q292FD6em40/f_wFbGe8ktY= J https://groups.google.com/forum/#!search/EDOARDO$20LOMBARDI$20MEDIOLANUM%7C= sort:relevance%7Cspell:true/it.diritto.assicurazioni/nP2oEPwP_gc/67cSB7chbP= wJ CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI GIOVANNI PIROV= ANI DI BANCA MEDIOLANUM https://groups.google.com/forum/#!search/GIOVANNI$20PIROVANO$20MEDIOLANUM/p= ortalecina/EdEl5iVy0vU/RXhpdaHfWEIJ https://groups.google.com/forum/#!search/GIOVANNI$20PIROVANO$20MEDIOLANUM/h= enry-de-vito-art-group/5dkzY63-ams/zaOcjLLPiWcJ CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI OSCAR DI MONTI= GNY DI BANCA MEDIOLANUM https://groups.google.com/forum/#!search/OSCAR$20DI$20MONTIGNY/it.media.tv/= T0uOEDtVTfc/9s734-sfm5wJ https://groups.google.com/forum/#!search/OSCAR$20DI$20MONTIGNY/alt.fan.rush= -limbaugh/23gcN67dxf4/LHi-vtWZd8EJ ... GUERRA CHE DAVID ROSSI DI MONTE PASCHI STAVA VINCENDO, DA QUI IL TAGLI= ARGLI LE VENE E FARLO VOLARE DALLA FINESTRA.. ALTRO CHE SUICIDIO) HA APPENA= BECCATO "ALTRI" 70.000 EURO DI MULTA! DALLA CONSOB! PER I SUOI SOLITI BAST= ARDISSIMI CRIMINI IN CRAVATTA! http://www.consob.it/main/documenti/hide/afflittivi/pec/mercati/2013/d18579= .htm http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.bluetg.it/banche-e-reti/179-promotori/28601-qmultaq-da-70mila-eu= ro-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.finanzaonline.com/forum/trading-line/1454952-barrai-spiega-come-= non-pagare-la-tobin-2.html http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob http://inquisitore.org/2013/09/23/paolo-barrai-condannato-dalla-consob/ https://www.google.it/#q=3Dpaolo+barrai+consob https://www.google.it/#q=3DPAOLO+BARRAI+ARRESTATO https://www.google.it/#q=3DPAOLO+BARRAI+CONDAnnato https://www.google.it/#q=3DPAOLO+BARRAI+PEDOFILO https://www.google.it/#q=3DPAOLO+BARRAI+PEDERASTA https://www.google.it/#q=3DPAOLO+BARRAI+ASSASSINO https://www.google.it/#q=3DPAOLO+BARRAI+MAFIA https://www.google.it/#q=3DPAOLO+BARRAI+CAMORRA https://www.google.it/#q=3DPAOLO+BARRAI+NDRANGHETA https://www.google.it/#q=3DPAOLO+BARRAI+DAVID+ROSSI https://www.google.it/#q=3DPAOLO+BARRAI+BRASILE https://www.google.it/#q=3DALESSANDRO+PROTO+E+PAOLO+BARRAI https://www.google.it/#q=3DPAOLO+BARRAI+CACCIATO+DA+CITIBANK https://www.google.it/#q=3DTRUFFATI+DA+PAOLO+BARRAI https://www.google.it/#q=3DLADRATI+DA+PAOLO+BARRAI https://www.google.it/#q=3DCOLLETTO+LERCIO+PAOLO+BARRAI PS AGGIUNGEREI A MO' CI CONTROPROVA DEL SOPRA RIPORTATO UN TESTO BELLISSIM= O CHE HO TROVATO IN RETE. CIAO E GRAZIE PER EVENTUALE COMPRENSIONE E PAZIEN= ZA PER I TANTI LINKS SOPRA DESCRITTI, FATTI SALTARE DA STI ASSASSINI BERLUS= CONAZISTI E PADANAZISTI, PER OVVIE RAGIONI DI LORO IMMENSO IMBARAZZO!!! NAZIRAZZISTA, LADRONE, TRUFFATORE, SEMPRE FALSISSIMO, BRUCIANTE "TUTTI I R= ISPARMI DI TUTTI, TUTTE" LE VOLTE, CONDANNATO AL CARCERE "SOLO" 3 VOLTE, ME= GA RICICLA CASH MAFIOSO O POLITI-C-RIMINALE, IN QUANTO IMMENSAMENTE RUBATO = E/O FRUTTO DI MEGA MAZZETTE IN DIREZIONE LL LEGA LADRONA ED EX PDL POPOLO D= I LADRONI! BERLUSCONAZISTA, PADANAZISTA, PLURIPREGIUDICATO, MANDANTE DI OMI= CIDI E "SUICIDATE", QUINDI BASTARDO ASSASSINO PAOLO BARRAI (BLOG MERCATO "M= ERDATO' LIBERO) VUOLE LA MORTE DI GENIO BORSISTICO ED EROE CIVILE MICHELE N= ISTA (MICHELENISTA@GMX.COM LONDON +44(0)7939-508007) SU ORDINE DI FASCIOCAM= ORRISTI PEDOFILI, DA 40 ANNI IMMENSI LAVA SOLDI MALAVITOSI, VERMINOSI DITTA= TORI CHE MISCHIANO DI CONTINUO AL CAPONE AD AUGUSTO PINOCHET, E, TANTO QUAN= TO, FREQUENTISSIMI MANDANTI DI OMICIDI ("CON BERSANIANA MASCHERINA" DI FINT= ISSIMI SUICIDI, MALORI ED INCIDENTI) OLTRE CHE "SOLAMENTE" STRAGI: SILVIO B= ERLUSCONI, ENNIO DORIS, MASSIMO CRIPPA, FEDELE CONFALONIERI, LICIO GELLI!! 1) OCHO, PLEASE, A QUESTA GANG KILLER, FASCISTISSIMA, ANTISEMITA, ANTIEURO= PEA, ANTIAMERICANA, MEGA LAVA SOLDI MAFIOSI O POLITICRIMINALI A GO GO ( COM= E DETTO, PADANAZISTA E BERLUSCONAZISTA). DA TENERE MOLTO, MOLTO, MOLTISSIMO= ALL'OCCHIO! QUESTA!!! FREQUENTISSIMI MANDANTI DI OMICIDI, NAZINDRANGHETISTI, MEGA LAVA SOLDI LER= CISSIMI A GOGO : A) PERICOLOSISSIMO AVANZO DI GALERA PAOLO BARRAI DI MOVIMENTI TIPO " KU KL= UK KLAN PADANO" E SIA "FIAMMA TRICOLORE CHE FORZA NUOVA CHE CASA POUND": COLLETTO CRIMINALISSIMO PAOLO BARRAI: GIA' CACCIATO A SBERLE DA CITIBANK P= ER CRIMINI EFFERATI CHE LI EFFETTUAVA (come da questo seguente articolo: il= criminalissimo "funzionario nei guai" di Citibank di fine scritto =E8 l'as= solutamente scafatissimo delinquente Paolo Barrai: http://archiviostorico.c= orriere.it/2001/febbraio/02/Arrestato_imprenditore_delle_truffe_fiscali_co_= 7_0102023408.shtml), CON MULTE DI QUASI 100.000 EURO DA PARTE DI CONSOB htt= p://www.consob.it/main/documenti/hide/afflittivi/pec/mercati/2013/d18579.ht= m, GIA' CON GUAI LEGALI SERISSIMI A BIELLA, CONDANNATO AL CARCERE A MILANO = E, TETNETEVI FORTE, PLS, FINANCO A PORTO SEGURO IN BRASILE http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D2996 http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://www.osollo.com.br/online/index.php/crimes/3052-blogueiro-italiano-se= ra-indiciado-por-estelionato-calunia-e-difamacao-pela-policia-civil-de-port= o-seguro http://portoseguroagora.blogspot.be/2011/03/porto-seguro-o-blogueiro-italia= no-sera.html http://noticiasdeportoseguro.blogspot.nl/2011/03/quem-e-pietro-paolo-barrai= .html PUZZONE AVANZO DI GALERA PAOLO BARRAI DEL BLOG MERCATO "MERDATO' LIBERO ht= tp://it.linkedin.com/pub/dir/Paolo/Barrai. IL SUO AVER FONDATO IL VERMINOSO= , TERRORISTICO, SANGUINARIO "KU KLUK KLAN PADANO"... IL SUO ASSASSINO NAZIR= AZZISMO LO PORTA A DEFINIRE OBAMA BARACK ( PER NOI, IN QUANTO A RISULTATI, = OSSIA UNICA COSA CHE CONTA, AFFATTO MALE PRESIDENTE US), UN BASTARDO NERO http://ilpunto-borsainvestimenti.blogspot.nl/2013/01/ecco-limpatto-fiscale-= che-ha-fatto.html O CHECCA ISTERICA http://ilpunto-borsainvestimenti.blogspot.nl/2014/03/mercato-libero-e-per-l= a-grande-madre.html INNEGGIANDO INTANTO AL NAZIFASCISTA COME LUI ( E COME "SUOI" NAZIMAFIOSI E= POR-CO-RROTTI MANDANTI QUALI MATTEO SALVINI, UMBERTO BOSSI, GIULIANO FERRA= RA, MAURIZIO BELPIETRO, ENNIO DORIS, MASSIMO DORIS, MARINA BERLUSCONI E SPE= CIALMENTE, PROPRIO KAPO' PEDOFILO NUMERO UNO, PROPRIO KA-P-EDOFILO MAXIMO: = SILVIO BERLUSCONI) A VLADIMIR PUTIN, CHE NON HA ESITATO UN SECONDO A FAR SF= RACELLARE 300 PERSONE CHE NON GLI AVEVAN FATTO MAI NULLA DI MALE, CHE VOLAV= ANO A 10.000 METRI DI ALTEZZA, IN GRAN PARTE SCIENZIATI CHE SALVAVANO MIGLI= AIA DI PERSONE DALL'AIDS http://ilpunto-borsainvestimenti.blogspot.nl/2014/03/mercato-libero-e-per-l= a-grande-madre.html . L'ASSASSINO NAZIRAZZISTA PAOLO BARRAI TRAFFICA CRIMIN= ALISSIMAMENTE CON SERVIZI SEGRETI RUSSI, UNGHERESI, SIRIANI, VICINI ALL'ISI= S, DI QUALSIASI TOPAIA DI ESTREMISSIMA DESTRA. E SVIZZERI ( E' PAGATO PER S= PINGERE TUTO IL NORD DEL VERMINAIO INCIUCIARO DI "RENZUSCONIA" VERSO BERNA,= DA QUI IL SUO SPINGERE IN QUESTA DIREZIONE, OGNI GIORNO, VIA PRECIPITANTE = BLOG "MERDATO" LIBERO). PREPARANDO CON LORO OMICIDI "DI SCOMODI", RICICLAGG= I DI CASH MALAVITOSISSIMO, LADRATE, TRUFFE, FRODI ( PUR, OVVIAMENTE, CERCAN= DO VIGLIACCHISSIMAMENTE DI DEPISTARE IL TUTTO, VIA, SUO PRECIPITANTE, LETTO= ORMAI DA NESSUNO, BLOG MERCATO "MERDATO"LIBERO... PASSATO DA 10.000 LETTOR= I AL GIORNO QUANDO VI SCRIVEVA NEL 2007, 2008 E INIZIO 2009, GENIO BORSISTI= CO ED EROE CIVILE MICHELE NISTA, AI PRESENTI 90 LETTORI AL GIORNO, CHE SONO= POI 20 AL MASSIMO, AL NETTO DI SOFTWARE TAROCCONI CHE L'AVANZO DI GALERA P= AOLO BARRAI USA DA SEMPRE PER MOLTIPLICARE IL NUMERO DEI TRE PADANAZISTI E = BERLUSCONAZISTI CHE ANCORA LO LEGGONO). LAST BUT CERTAINLY NOT LEAST: MANDA= NTE DELL'OMICIDIO E AFFATTO SUICIDIO DI DAVID ROSSI DI MONTE PASCHI, PER UN= A GUERRA DI SEO, SEARCH ENGINE OPTIMIZATION, CHE DAVID ROSSI AVEVA INGAGGIA= TO CON IL SICARIO BERLUSCONAZISTA E PADANAZISTA PAOLO BARRAI E I SUOI MANDA= NTI, ALIAS GLI ASSASSINI IN CRAVATTA DOLCE E GABBANA: MASSIMO DORIS MEDIOLA= NUM, ENNIO DORIS MEDIOLANUM, EDOARDO LOMBARDI MEDIOLANUM, OSCAR DI MONTIGNY= MEDIOLANUM, GIOVANNI PIROVANO MEDIOLANUL, ETTORE PARLATO SPADAFORA MEDIOLA= NUM ( SANGUINARISSIME, ULTRA OMICIDA OVRA E GESTAPO PRIVATE DI SILVIO BERLU= SCONI ED ENNIO DORIS PRIMA TAGLIARONO LE VENE A DAVID ROSSI DI MONTE PASCHI= E POI LO FECERO VOLARE DALLA FINESTRA PER ASSICURARSI DI CERTA MORTE, LE F= AMOSE EMAILS CHE DAVID ROSSI "AVREBBE" MANDATO A VERTICI DI MONTE PASCHI PE= R ANNUNCIARE SUO SUICIDIO ERAN TUTTE TUTTE E STRA TUTTE FALSE, IN QUANTO SC= RITTE E FATTE PARTIRE DA HACKERS DEL 'BERLUSCONAZISTA E PADANAZISTA' TANTO = QUANTO, HACKING TEAM, "NON PER NIENTE" FINANZIATO DAI DUE VERMI MEGA KAPO' = DI PAOLO BARRAI E I DORIS: ROBERTO MARONI E SILVIO BERLUSCONI... COME VEDET= E TUTTO STRA QUADRA) B) TERRORISTA ASSASSINO DI ESTREMISSIMA DESTRA: MAURIZIO BARBERO DI TECHNO= SKY MONTESETTEPANI E MERCATO "MERDATO LIBERO NEWS http://it.linkedin.com/pu= b/maurizio-barbero/8/197/a52 ( ORGANIZZANTE OMICIDI DI CHIUNQUE "SCOMODO" C= ON SUO KAMERADEN, ACCLARATO KILLER DI SILVIO FANELLA, NAZISTA GENOVESE GIOV= ANNI BATTISTA FENICI CHE AL VERME OMICIDA MAURIZIO BARBERO DI TECHNOSKY MON= TESETTEPANI ERA UNITO ANCHE DA UNA STORIA OMOSESSUALE, OLTRE CHE DA COMPLOT= TI TERRORISTICI ASSASSINI NERI... "E SPECIALMENTE IN NERO") C) LA NOTA PROSTITUTA E PORNOSTAR AMATORIALE FACENTE TANTE ORGE AD (H)AR(D= )CORE, ELISA COGNO DELLA RICICLANTISSIMA DENARI DI COSA NOSTRA, CAMORRA E N= DRANGHETA: FRUIMEX DI ALBA. COME PURE DI MERCATO "MERDATO" LIBERO NEWS ( ZO= CCOLA CON SWASTIKA NEL CUORE NERO, CHE HA; MIGNOTTONA DI CORTE, PARTECIPANT= E A CENTINAIA DI ORGE AD H-AR-D-CORE E NON SOLO CON SUOI PAESANI NAZI-CUUNE= NSI: DANIELA SANTANCHE' E FLAVIO BRIATORE) http://www.linkedin.com/pub/elisa-alba-elisa-fruimex/1b/25b/212 http://www.= impresaitalia.info/MSTDB80753147/fruimex-di-cogno-elisa-e-c-sas/alba.aspx D) LA SCHIFOSA BISCIA DI ESTREMISSIMA DESTRA, MEGA RICICLANTE CASH MAFIOSO= VIA PANAMA E BTCOINS, DELINQUENTE VERMINOSO GIACOMO ZUCCO DEI NAZIRAZZISTI= TEA PARTIES DI BERLUSCONIA, ANZI, PUZZOLENTE RENZUSCONIA https://twitter.c= om/giacomozucco E) ALTRI VERMI VARI, ASSOLUTI TERRORISTI DI ESTREMA DESTRA, PARTE DI STA P= ADANAZISTA E BERLUSCONAZISTA GANG, SONO IL FONDATORE DEL, DA ASSOLUTI BRIVI= DI, "ORGOGLIO PEDOFILO PADANO": STEFANO BASSI DEL BLOG IL GRANDE BLUFF http= s://twitter.com/grandebluff ED UN CRIMINALISSIMO FACCENDIERE ROMANO, ASSOLU= TA LAVATRICE DI PROVENTI MEGASSASSINI DI BANDA DELLA MAGLIANA, NDRANGHETA E= CAMORRA: FEDERICO IZZI NOTO COME "ER ZIO ROMOLO DEI CASALESI" https://it-i= t.facebook.com/pages/Zio-Romolo/71267552792 COSTORO SONO DEI COLERA KILLER CHE ODIANO GLI EBREI, CHI DI CENTROSINISTRA= , CHIUNQUE NON SIA NAZISKIN IN CRAVATTA COME LORO. ED IN MANIERA VISCERALIS= SIMA. FAN PARTE DI MASSONERIE DI ESTREMISSIMA DESTRA, CON A CAPO, ANZI, A K= APO', COME AL SOLITO, LICIO GELLI (NOTO VERME DEPISTATORE; QUINDI, ANCHE LO= RO, OGNI TANTO, SUL WEB, OVVIAMENTE, DEPISTANO, E SI FINGONO, RIPETO, FINGO= NO, NON NEMICI DEGLI EBREI, O DEGLI USA O DELL'EUROPA; MA SONO ANTISEMITISS= IMI, ANTI USA, ANTI EUROPA, FILO HITLERIANI ALL'ESTREMO E PRESTO LO DIMOSTR= EREMO). IL TUTTO INSIEME AI BANCHIERI PIU' AMATI DALLE MALAVITE MONDIALI E = NON SOLO DEL CESSO TIRANNICO DI RENZUSCONIA: http://www.gruppoesperia.it/en= /About-Us/giuseppe-sabato.html GIUSEPPE SABATO ED EDOARDO LOMBARDI DI BANCA= ESPERIA (IL BANCHIERE PIU' "VENERATO" DA OGNI CAMORRISTA DEL MONDO: GIUSEP= PE SABATO DI BANCA ESPERIA; BASTARDISSIMO NUOVO JOSEF MENGELE DEL CREDITO, = CHE CON LICIO GELLI, NEL 1999, AVEVA FONDATO, NON PER NIENTE, IL VERMINAIO = PUZZOLENTISSIMO DELLA GRAN LOGGIA MASSONICA ITALIANA:http://vivereacomo.inf= o/2006/12/22/p2ecunia-non-olet/). UNITI AI MICHELE SINDONA DEI GIORNI NOSTR= I: ENNIO DORIS E MASSIMO DORIS DI BANCA MEDIOLANUM (BANCA ESPERIA E BANCA M= EDIOLANUM SONO DI FATTO LA STESSA FOGNA: SONO IL DETERSIVO FINANZIARIO NUME= RO UNO DI COSA NOSTRA http://espresso.repubblica.it/palazzo/2008/05/15/news/vado-riciclo-e-torno-= 1.8408 CAMORRA, NDRANGHETA, SACRA CORONA UNITA, MA ANCHE DI NARCOS COLOMBIA= NI, NARCOS MESSICANI, MAFIA RUSSA, MAFIA ALBANESE, MAFIA RUMENA)! DICEVO, A= NYWAY: I KAMERADEN MASSO-N-AZIFASCISTI, CUGINETTI DI VERMI STRAGISTI COME A= NDERS BEHRING BREIVIK, GAETANO SAYA, RICCARDO SINDOCA, MARCO MANCINI, GENNA= RO MOKBEL, GIULIANO TACAROLI, EMANUELE CIPRIANI, MARCO MANCINI, VALTER LAVI= TOLA ( L'ESCREMENTO ASSASSINO E NAZIMAFIOSO PAOLO BARRAI E' NE PIU' NE MENO= CHE IL NUOVO VALTER LAVITOLA, AL MILIARDO E BILIARDO PER CENTO), NEL CESSO= DI BERLUSCONIA, ANZI, DA ODIARE AL MASSIMO, INCIUCIARA, LADRONA, DITTATORI= ALE E CORROTTISSIMA RENZUSCONIA, SONO I MEGA LAVA SOLDI ASSASSINI, MANDANTI= DI OMICIDI A GOGO, TERRORISTI DI ESTREMISSIMA DESTRA, RAZZISTI TANTO DA AV= ER APPENA FONDATO IL "KU KLUK KLAN PADANO" E TOPAIA NERA PRIMA CITATA". UNA= COLERICISSIMA FOGNA, OVVIAMENTE, FINANZIATA, CON CASH DI AR-COR-LEONE, DAI= SCHIFOSI FASCIOCAMORRISTI SILVIO BERLUSCONI E LICIO GELLI. E COME LO SCHIF= OSISSIMO NOTO DEPISTATORE E FALSISSIMO SILVIO BERLUSCONI SI FINGE OGNI TANT= O, AMICO DEGLI EBREI, MA DA DECENNI, RIPETO, DECENNI, ABBIAMO DOZZINE DI TE= STIMONI, IN PRIVATO RAGLIA SIMIL BARZELLETTE PER DECEREBRATI VISCIDI LECCHI= NI TIPO " SCUSATE, SONO ANDATO IN BAGNO OVE HO APPENA FATTO I MIEI BISOGNI,= MA NON VI ERA ABBASTANZA CARTA IGIENICA... HO ANCORA IL DI DIETRO SPORCO E= NON HO DEL SAPONE, AVETE UN EBREO"? OPPURE: " DI SOLITO NON FUMO, MA AKCUN= I MIEI AMICI TEXANI NAZISTI DEI TEA PARTIES MI HAN APPENA REGALATO UN MEGA = SIGARO... VORREI FARMELO ( CI CHIEDIAMO: IN CHE SENSO?), MA IL MIO ACCENDIN= O HA FINITO IL GAS... AVETE PER CASO UN EBREO"? COSI', ALLO STESSO TEMPO, I= L PERICOLOSISSIMO MANDANTE DI OMICIDI, GIA' PLURI CONDANNATO AL CARCERE, NO= N SOLO A MILANO, MA ANCHEM PARREBBE, A BIELLA ED IN BRASILE, PAOLO BARRAI, = FINGE, A SCOPO DI DEPISTAGGIO, SUL WEB, DI LECCARE PERSONE CHE DEFINISCE EB= REI DI COLOMBIA E PANAMA VICINISSIMI AI CARTELLI DI CALI', BOGOTA E DI MEDE= LLIN. 2) MA GUARDATE COSA SCRIVE AD UN ASSOLUTO GENIO BORSISTICO MISTO AD EROE CIVI= LE, ANTI NAZIFASCISMO E MAFIA DI SILVIO BERLUSCONI, DI GRAN SUCCESSO, A LON= DRA: MICHELE NISTA. GUARDATE COME GLI DAVA DEL GENIO NEL 2007, 2008 E PRIMA= PARTE DEL 2009, QUANDO SCROCCAVA L'IMMENSO TALENTO BORSISTICO DI MICHELE N= ISTA FACENDOCI MILIONI DI EURO ( IN NERO "FISCALE E POLITICO") E GUARDATE, = PLS, COSA SCRIVEVA DI MICHELE DAL 2010 IN POI, A) IN QUANTO MICHELE AVENTE PARZIALE SANGUE EBREO B) UNA VOLTA CHE IL SEMPRE VINCENTISSIMO MICHELE NISTA DECISE DI NON AVER = PIU' NULLA A CHE FARE COL VERME CRIMINALISSIMO PAOLO BARRAI DOPO AVER SCOPE= RTO DEI PUTRIDISSIMI RICICLAGGI DI CASH MAFIOSO, BERLUSCONAZISTA E PADANAZI= STA CHE PAOLO BARRAI EFFETTUAVA E STRA EFFETTUA ORA PIU' CHE MAI IN GIRO PE= R IL MONDO. GUARDATE, GUARDATE, PLS, DA BRIVIDI ASSOLUTI: IL FIUTO DI UN AMICO... Post del Febbraio 2008 Qualche anno fa a Milano la borsa chiudeva poco dopo pranzo. Nel pomeriggio se un operatore istituzionale cercava titoli italiani sapeva dove andare.... Telefonava a Michele Nista. Michele Nista era un vero grandissimo broker, altro che macchina telematica. E riusciva anche a trovare prezzi migliori della macchina stessa facendo felice sia il venditore che il compratore. Anche con la chiusura dei mercati alle 17.30 Michele =E8 sempre riuscito a trovare l'introvabile. Non esisteva e ancora esiste la "missione impossibile" per Michele Nista. Un milione di Generali? Bastavano pochi minuti e venivano trovate al giusto prezzo. Poi Michele si =E8 allontanato dal mercato, ma a Novembre l= 'ho incontrato dopo tanto tempo. Abbiamo bevuto un caff=E8 e abbiamo parlato d= el mercato... Caro Michele, farai anche altre cose ora ma il fiuto per gli affari, quello no...non ti manca. Michele, non sar=E0 forse un macroeconomista, ne= uno studioso di bilanci, ma ha una particolare dote...il senso degli affari. Pochi come lui si muovono nel mercato con la stessa spavalderia. Anche nel Settembre 2007 non si =E8 sbagliato...mentre i molti urlavano al rally di Natale e il Dow Jones era intorno ai 14.000 il mio caro amico Michele mi ha guardato fisso negli occhi e mi ha detto "Ehi doctor....il Dow arriver=E0 a 11.800 fra poco e poi a 8000" Caro Michele sei stato bravo, anzi bravissimo... Ah dimenticavo di dirvi che la scorsa settimana ho incontrato Michele, questa volta non abbiamo preso un caff=E8...ma siamo passati a un pranzo anche se frugale) Sapete cosa mi ha confidato guardandomi ancora un= a volta negli occhi? "ehi Doctor fra poco il dow Jones arriva a 10.800 e poi giu, fino a 8000 e poi ulteriormente giu fin sotto 7000"??? Sapete che vi dico...che se fossi Bernanke comincerei a preoccuparmi seriament, L'INIEZIONE DI DROGA DETTATA DAL TAGLIO DEI TASSI NON E' CHE UN ESTREMO TENTATIVO DI SALVARE UN MODELLO ECONOMICO ALLO SFASCIO. Vai Michele, continua cosi'!!! ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~ ALTRO POST, IN QUESTO CASO, SCRITTO IN QUESTO CASO, A META' APRILE 2009 UN GRAZIE A MICHELE NISTA Unico ad avvisare i nostri lettori di un DOW a 7700 (quando valeva 13.000) Unico ad avvisare che i mercati americani sarebbero ripartiti con le rondini, unico che a fine febbraio ha detto di comprare e di guardare le quotazioni a luglio. Michele ha affermato pi=F9 volte che Obama riporter=E0 ai massimi il Dow a fine mandato. Io personalmente non sono daccordo sulla sua ultima vision= e. ma questo =E8 MERCATO LIBERO un blog capace di selezionare delle persone differenti ma capaci di individuare i trend. MICHELE NISTA SEI UNA FORZA, A LIVELLO DI INTUITO, IL MIGLIORE AL MONDO IN= TERO!!! Pubblicato da mercatolibero a luned=EC, aprile 13, 2009 O QUESTO. MICHELE NISTA SEI UN GRANDE!!! La scorsa settimana abbiamo scritto un articolo sulla spartizione della tv di stato e della possibile vendita di rete 4 da parte di Berlusconi. L'articolo era frutto di una chiaccherata con lo stanatartufi,= genio, in quanto a fiuto per gli affari, energie e coraggio, Guru di azioni, valute e commodities mondiali: Michele Nista. Michele =E8 in gran forma e non lo ferma pi=F9 nessuno. O il nostro articolo =E8 stato letto da Di Pietro....o qualcosa bolla in pentola nel campo delle televisioni....( segue articolo) ...Insomma, Michele Nista, ha intuito tutto al volo, ed alla perfezione, c= ome sempre. Bravo Michele sei un mito ED INFINE, POST, CHE RICEVETTE " SOLO" 203 COMMENTI MICHELE GRAZIE (MICHELE NISTA!) A nome di Mercato libero e di tutto lo staff vorrei ringraziare Michele Nista per lo stupendo lavoro fatto su questo sito da 18 mesi. Molti nuovi lettori non sanno tutto quello che ha predetto e poi si =E8 puntualmente avverato. NON HA SBAGLIATO UNA VOLTA. E francamente se anche domani dovesse prendere un abbaglio....non =E8 importante. Ha salvato il culo ha migliaia di persone predicendo il DOW a 6900 quando stava a 10.000 (e predicendo il Dow a 10.000 quando stava a 13.500). Ha detto ripetutamente che il mercato sarebbe salito con l'arrivo delle rondini e cos=EC =E8 stato (e il rialzo non =E8 stato di quelli piccoli....)! MA QUALE BLOG O BANCHIERE, O PROMOTORE, O TRADER O PRIVATE BANKER HA SAPUTO SOLO AVVICINARSI A TALI PREVISIONI (NON NASCONDO CHE ANCHE IO ERO SCETTICO QUANDO PARLAVA DI DOW A 6900!) Grazie ancora Michele Nista e ricordati che appena rientri in Italia organizziamo una bella serata con i nostri amici lettori. CHIEDO A TUTTI COLORO CHE LO APPREZZANO DI SPENDERE DUE MINUTI A POSTARE UN COMMENTO SUL SUO GRANDE LAVORO CON NOI. Pubblicato da consulenza finanziaria di Mercato Libero a marted=EC, aprile 28, 2009 203 commenti Salvarisparmio ha detto... Grnade Michele, ti dobbiamo noi lettori molto . Remigio 28 aprile 2009 18.24 Anonimo ha detto... io sono nuovo del blog e anche della borsa, non ci ho capito molto, ma di = una cosa sono sicuro:Michele Nista =E8 un grande 28 aprile 2009 18.27 Andrew234 ha detto... Inizio io: GRAZIE MICHELE PER TUTTO QUELLO CHE HAI FATTO PER NOI!!!non cur= arti di quello che dice qualche imb..... Continua ad aiutarci!! 28 aprile 2009 18.37 Anonimo ha detto... Dai Michele non guardar lo scamannato ma guarda e passa oltre. hai un big bunch di persone che ti stimano e apprezzano il contributo che = ci dai. con affetto Paolo da Bologna 28 aprile 2009 18.46 Marco sapa ha detto... Grandissimo Michele Nista, chi critica di solito =E8 invidioso oppure non = ha capito una mazza di borsa...seguendoti mi son salvato le chiappe...migli= aiai di euro di ringraziamneti!! Marco 28 aprile 2009 18.46 Anonimo ha detto... Veramente =E8 stato cos=EC incredibilmente preciso che mi chiedo come facc= ia a fare le sue previsioni. Analisi tecnica?fondamentale? intuito? Esoterismi vari? Come fai Michele?? Complimenti davvero. 28 aprile 2009 18.49 Anonimo ha detto... Michele sei il numero 1 28 aprile 2009 18.57 Anonimo ha detto... NISTA sei un mitooooooooooooooo 28 aprile 2009 19.00 Anonimo ha detto... Personalmente ritengo Michele un grande, una persona soprattutto trasparen= te, limpida, che utilizza un linguaggio diretto, senza fronzoli, ma sopratt= utto comprensibilissimo. Mi e' anche molto simpatico quando "parla" di Berl= usconi, e col quale condivido appieno la Sua interpretazione. Grazie Michele, dal profondo del cuore!!!! Felix 28 aprile 2009 19.01 Leo ha detto... Tutta la mia stima ed ammirazione per quest`uomo che ha il coraggio di dir= e quello che pensa e in cui crede nonostante correnti sfavorevoli e gente g= eneticamente scorretta. Grazie e buon lavoro 28 aprile 2009 19.03 Anonimo ha detto... sei un grande anzi grandissimo, dacci dentro 28 aprile 2009 19.03 settevoci ha detto... Io dico grazie all'uomo Michele Nista.Infatti in questo mondo di falsi mon= tati, ci vorrebbero centomila MICHELE NISTA. GRAZIE Anonimo ha detto... Sempre con te Michael Giuseppe Cagliari 28 aprile 2009 19.19 Anonimo ha detto... CONFERMO tutto !! Di fatto quanto affermato PREVENTIVAMENTE si =E8 avverato da ....diciamo .= .. circa 1 anno puntualmente. Frutto di un'ottima conoscenza dei mercati e = sicuramente di giuste entrature nel settore finanziario. COMPLIMENTI 28 aprile 2009 19.21 Anonimo ha detto... Grazie di cuore Michele! 28 aprile 2009 19.24 Anonimo ha detto... Non ho letto il post che ha angustiato il grande MICHELE Certe persone sono vili fino al midollo. Purtoppo esistono e ce ne saranno= sempre. Il Sommo Poeta non ne ebbe piet=E0 neanche all'inferno. << Fama di loro il mondo esser non lassa; misericordia e giustizia li sdegna: non ragioniam di lor, ma guarda e passa. >> Maestro Michele guarda e passa anche Tu. 28 aprile 2009 19.24 Anonimo ha detto... Di Michele Nista apprezzo ancora di pi=F9 l'uomo e le sue visioni del mond= o e della derelitta, sciagurata realt=E0 italiana piuttosto che l'esperto d= i borsa. Tenendo conto, che da 18 mesi il buon Michele ha previsto i movimenti del = Dow quasi avesse una sfera di cristallo (e migliaia di lettori del suo blog= possono testimoniarlo) credo non sia cosa di poco conto. Grazie di cuore per tutto il tempo che ci ha dedicato, Sig. Nista, e conti= nui, oltre a metterci a parte delle sue preziose e lucide intuizioni, a sfe= rzare il malaffare imperante nella nostra povera ma amata Patria. Cordiali saluti. Adriano 28 aprile 2009 19.26 Anonimo ha detto... MICHELE NISTA, THE BEST!!!!!! GOD BLESS YOU! 28 aprile 2009 19.35 Anonimo ha detto... MICHELE SEI U-N-I-C-O !!!! Aggiungo che nessuno, su nessun media che io co= nosca si =E8 espresso con la tua precisione, puntualit=E0, chiarezza, ma so= prattutto CORAGGIO E GENEROSITA'. Individuare qualche spunto di trading ric= hiede abilit=E0, ma solo in parte minima rispetto a quanta ce ne vuole per = pronosticare linee tendenza con una precisione strabiliante!!!! Un vero mag= o della finanza. Chi ti ha seguito non pu=F2 che esprimerti RISPETTO E GRAT= ITUDINE. Se qualche babbeo cerca di far lo spiritoso =E8 perch=E8 non =E8 i= nformato (ma allora =E8 buona regola tacere!), altrimenti =E8 un idiota o u= n un invidioso. Crepi l'invidia e ... W MICHELE! F.to / Un Post-Berlusconiano (se prima ci siamo turati il naso, ora basta: nani e ballerine hanno gi=E0= travolto uno grande, magari poi tocca anche ad uno ... piccolo!) Va meglio ?! Andrea ha detto... GRANDE MICHELE,SEI UN FARO PER TUTTI NOI IN QUESTA GIUNGLA BUIA, COMPLIMENTI PER L'OTTIMO LAVORO SVOLTO GRATIS,POI SEI L'UNICO CHE GIUSTAME= NTE ATTACCHI BERLUSCONI CHE =E8 UNA PIETRA AL PIEDE PER L'ITALIA. ANDREA 28 aprile 2009 19.48 lapalisse ha detto... Ah michael, ma l'Italia =E8 piena di berluscones mediolanumen rosicones...= .=E8 normale che si incazzino!!!! Pi=F9 si incazzano, e pi=F9 noi godiamooo= o...... ciao michelONE!!! e ciao anche al ns. duturun!!!! 28 aprile 2009 19.54 Anonimo ha detto... GRAZIE, GRAZIE, GRAZIE!!! per: - la simpatia - la pazienza - l'onest=E0 - la professionalit=E0 - i commenti - gli "omissis" - e anche per le previsioni. SEI INDISPENSABILE!!! Antonio 28 aprile 2009 20.06 Pier Marco ha detto... Michele sei un grande!! E' sempre un piacere leggere i tuoi post appassion= ati e profetici, continua cos=EC e fregatene degli invidiosi che provano a = sminuire il tuo grande lavoro!! 28 aprile 2009 20.15 Anonimo ha detto... Michele sei un grande, non considerare i commenti di un piccolo insignific= ante... ci hai sbalorditi e siamo convinti che lo farai ancora!!!! very very good ! 28 aprile 2009 20.20 Anonimo ha detto... Grazie a Michele NISTA! Un grande, onesto e corretto. Marco Colacci 28 aprile 2009 20.29 Anonimo ha detto... =E8 veramente una mosca bianca, =E8 l'unico a non sbagliare mai un colpo, mi piacerebbe incontralo anche in seminari. grazie ancora... 28 aprile 2009 20.36 Anonimo ha detto... A Michele, vorrei dire che leggo soprattutto con attenzione le sue visioni= extra-mercati, che mi sembrano importanti almeno quanto le sue previsioni = sui listini. Le motivazioni che stanno dietro alle sue previsioni mi regalano una visua= le e delle riflessioni che non riscontro su nessun altro blog. Ciao e buon lavoro a Michele. Claudio 28 aprile 2009 20.37 Anonimo ha detto... MYKOL NISTA: I love you forever! Arianna 28 aprile 2009 20.41 Anonimo ha detto... Caro Michele, non sono d'accordo con quanti pensano che chi ti ha scritto = facendoti inc....sia un cretino o uno sciammannato. Fosse cos=EC non ci sar= ebbe da preoccuparsi. Per=F2 tu dovresti sapere che in rete circolano i pro= fessionisti della provocazione e della disinformazione, legati ai poteri pi= =F9 o meno forti e pi=F9 o meno occulti, il cui solo scopo =E8 quello di de= stabilizzare il dissenso e renderlo non credibile. E' cos=EC che chiudono i= blog, molto pi=F9 sottilmente che vietandoli. Se poi vogliono travestirsi = da cretini =E8 solo una tattica, ma sanno benissimo quello che fanno. Quind= i in campana per non cadere nei trappoloni che tendono(depressione compresa= ), complimenti per il grande lavoro di entrambi e chi se ne frega se una vo= lta o due tu non dovessi imbroccarla. Oppure hai trovato la sfera di crista= llo buona per indovinare tutto? A parte gli scherzi auguri! Giovanni Sicola 28 aprile 2009 20.46 bebec ha detto... Grazie Michele per le tue visioni che molti soldini ci hai fatto risparmia= re e guadagnare e per la tua onesta e schietezza,dove mi ci vedo anch'io co= me persona,senza "miedo" dei nostri politicanti e imprenditori falsi e coro= tti che pensano solo al loro benessere e non a quello del Popolo. Bebec 28 aprile 2009 20.57 Anonimo ha detto... nista uber alles hasta siempre... s. 28 aprile 2009 20.59 Anonimo ha detto... Grande Michele Nista!! Spettacolare....(anche e soprattutto quando parli di quel tal.....Berlusco= ni)! Grazie. 28 aprile 2009 21.03 Stefano ha detto... Grazie a Michele per il loro lavoro. E speriamo di poter leggere Michele p= i=F9 spesso! 28 aprile 2009 21.13 Anonimo ha detto... Grazie di cuore Michele Massimo Fiorno 28 aprile 2009 21.16 Anonimo ha detto... michele the best thank you to be with us marco b. 28 aprile 2009 21.24 Anonimo ha detto... Michele Nista =E8 stato straordinariamente preciso nelle sue previsioni. D= a ottobre =E8 diventato positivo sull'equity mondiale indipendentemente dal= l'andamento di breve periodo, dicendo solo una cosa: accumulate azioni sven= dute, potrebbero diventare oro nel tempo. La pensavo cosi e lo ringrazio di= esistere perch=E8 mi ha confortato e incoraggiato, dandomi la spinta a osa= re,a rate,nei giorni di crollo. Ma ho comprato sul mercato italiano da lui = un po' detestato. Oggi sono appagato, vendo a premio, e se il mercato storn= a compro ancora. Penso che lui farebbe lo stesso. Roberto (TO) 28 aprile 2009 21.25 MARCO ha detto... SEI UN MITO, COME FAREMO SENZA DI TE! 28 aprile 2009 21.29 Anonimo ha detto... Michele Nista resta con noi please! Claudio 28 aprile 2009 21.30 TONY61 ha detto... Grazie Michele Nista!!! Grande professionalit=E0: AMMIREVOLE, COMPLIMENTI!= !!! 28 aprile 2009 21.31 Anonimo ha detto... Nista sei la verit=E0. 28 aprile 2009 21.34 pasquale ha detto... ciao Michele,ho piena fiducia in quello ke scrivi e pensi perk=E8 sei davv= ero bravo e nn hai paura di scrivere quello ke si dovrebbe sapere,mi rispek= kio nei valori sani e corretti ke ti distinguono.SEI UN GRANDE!!!!!!mi disp= iace solo di aver conosciuto questo sito troppo tardi altrimenti avrei salv= ato un bel p=F2 di risparmi...ma ti ringrazio di cuore del servizio ke ci r= endi ogni giorno...pasquale gallo 28 aprile 2009 21.37 Anonimo ha detto... Vogliamo Michele Nista presidente del consiglio! 28 aprile 2009 21.39 Anonimo ha detto... we nn scherziamo!!!! ciao mikele sei una potenza nn smettere mai di fare q= uello in cui credi soprattutto se =E8 per colpa di qualke stup.. magari ank= e in malafede 28 aprile 2009 21.42 Simone ha detto... Grazie mille per l'importantissimo lavoro svolto! 28 aprile 2009 21.42 Anonimo ha detto... ritengo michele un vero saggio... rimani con noi per sempre!!!! MARCELLO Roma 28 aprile 2009 21.47 Anonimo ha detto... anche se ti sto sulle palle seguo le tue info molto precise e puntuali... Silvio Berlusconi scherzo... sei un mito!!!! 28 aprile 2009 21.48 francesco driver ha detto... i risultati parlano per te michele tutto il resto non conta nulla! 28 aprile 2009 21.56 Anonimo ha detto... michele.sono Laura ti abbiamo scritto anche prima non =E8 apparso il comme= nto...miche non ci abbandaonare...le tue bimbe...Laura, chiara , lorenza...= avvisaci quando entrare nell'azionario...un bacio da tutte noi... 28 aprile 2009 22.03 Anonimo ha detto... GRAZIE DI TUTTO MICHELE... 28 aprile 2009 22.10 Anonimo ha detto... Grazie Michele, oltre che come Faro nella Tempesta dei mercati finanziari,= per come stai facendo aprire gli occhi agli italiani (anche se non di tutt= i) con la tue osservazioni che solo una Persona dall'estero e con il Cuore = Italiano come te puo fare. Porta Pazienza, anche se pochi non capiscono o fanno finta di non capire, = o ti provocano volutamente perch=E8 sei un personaggio Scomodo, ricordati c= he la maggior parte di noi =E8 con te. A Presto Raffaele 28 aprile 2009 22.13 Anonimo ha detto... Metaforicamente Vi potrei definire i delfini che nel mare dell'ignoranza c= i difendeno dagli squali della finanza. Forza e coraggio siamo tutti con Voi. Un grazie sincero a Michele Nista. Lapo 28 aprile 2009 22.19 luca ha detto... CHE DIRE....A ME PIACE MOLTO MICHELE ..PIACE LA SUA CULTURA..IL SUO MODO E= IL SUO CORAGGIO DI DIRE CERTE COSE, LA SUA COMPETENZA...E SOPRATTUTTO LA S= UA UMILTA'.IO SU MOLTE COSE LA PENSO COME LUI..ED HO LA SUA STESSA CAPACITA= ' DI VEDERE OGNI COSA A 360=B0.QUELLO CHE DETESTO E' LA PESSIMA CULTURA ITA= LIANA...QUELLA DELL'IMBROGLIO.GRAZIE MICHELE. 28 aprile 2009 23.03 atca ha detto... Un grazie sincero a Michele Nista. VALENTINO 28 aprile 2009 23.08 Anonimo ha detto... Michele, mi aggiungo tardi alle tante lodi che hai ricevuto. Che dire: mi = piacerebbe proprio ci fosse uno spazio proprio, per i tuoi commenti sul Blo= g. Adriano 28 aprile 2009 23.14 Anonimo ha detto... In Zi' Micheluzzo Nista We Trust!! w l'onest=E0 w la libert=E0 w il merito "Slowly but surely, avanti, come ooooon" Jack 28 aprile 2009 23.24 Anonimo ha detto... Grazie Michele, per il grande lavoro sociale che fate tutti i giorni. Noi = siamo tutti con VOI. ALESSANDRO 28 aprile 2009 23.31 Anonimo ha detto... VIVA LA LIBERT=E0, VIVA MICHELE...SEI GRANDE.IO SONO UN PICCOLO RISPARMIAT= ORE,FINO A POCO TEMPO FA ERO ALLA MERC=E8 DI PROMOTORI SENZA SCRUPOLI CHE M= I INFONDEVANO UN OTTIMISMO INFONDATO(MENTRE IL MONDO ANDAVA A ROTOLI) VENDE= NDOMI PRODOTTI TRUFFA...OGGI NE SONO ANCORA PI=F9 CONSAPEVOLE GRAZIE A SUPE= RMIKE E VOI TUTTI.SIETE LA SPERANZA DI TUTTI NOI INCASTRATI NELL'INGRANAGGI= O DEGLI INTERESSI DEI POTENTI GALLO PASQUALE MARSALA(TP) 28 aprile 2009 23.33 fokal ha detto... Michele Nista =E8 un grande senza alcun dubbio ...continuate cos=EC thanks Mimmo 28 aprile 2009 23.56 Anonimo ha detto... Cari Michele, Paolo e tutti gli altri "zii" e collaboratori di questo blog= : grazie! Per gli spunti d'investimento, ma anche perch=E8 fate informazione fuori d= al coro. E ce n'=E8 tanto bisogno .... Gabriele 29 aprile 2009 7.33 Anonimo ha detto... Complimenti a Miche Nista per i suoi ssuggerimenti finanziari, politici e = sociali ed in pi=F9 che finisca l'esilio ! Grazie Michele per gli articoli Giuseppe 29 aprile 2009 8.41 Anonimo ha detto... Il Dott. Michele Nista =E8 un grande, per quello che di dice ma anche per = lo stile con cui ce lo dice. Sarebbe una grande gioia poter incontrare una cos=EC geniale persona. Wildman 29 aprile 2009 8.54 Andrea ha detto... W michele nista abbasso psiconano malefico! 29 aprile 2009 9.03 Anonimo ha detto... =E8 incredibile quello che sei riuscito a fare, grazie per sempre .. fabrizio torino 29 aprile 2009 9.16 Anonimo ha detto... Continuiamo amici ad incoraggiare Michele, lui DEVE cambiare idea. Non pos= siamo perderlo 29 aprile 2009 9.21 Anonimo ha detto... Michele Nista =E8 il nostro guru numero uno! Bravo e simpatico! Anna 29 aprile 2009 9.54 Anonimo ha detto... Non vedo come si possa negare l'evidenza. Michele ha interpretato le tende= nze del mercato meglio di tanti altri. Si possono rileggere tutti i suoi ar= ticoli, tenendo conto della data nella quale sono stati pubblicati nel blog. "verba volant scripta manent" saluti marco 29 aprile 2009 10.32 pollodimare ha detto... Ero in viaggio e non mi sono potuto collegare prima. Leggo il blog da un a= nno e mezzo e sono rimasto veramente impressionato dalle analisi di Michele= Nista. Politicamente nutro delle opinioni diverse dalle sue, ma leggo e me= dito con attenzione quanto dice. Mi piacerebbe poter scambiare qualche opin= ione, ma non =E8 questa la sede o il momento. Complimenti ed auguri vivissi= mi da un "vecchio" che ha seguito la Bisca (Borsa) italiana dal lontano 196= 1. 29 aprile 2009 10.58 Anonimo ha detto... MICHELE non devi darla vinta a un cretino cosi fai il suo gioco sfidalo e forse si rendera' conto di quello che e' 29 aprile 2009 11.15 Anonimo ha detto... Grazie Michele!!! Da voi si impara!!! Davide Ferrari (Mantova) 29 aprile 2009 11.56 Anonimo ha detto... Michele ti vogliamo bene, sei e rimarrai la nostra luce. Non mollare mai. Thomas 29 aprile 2009 12.21 giallu ha detto... per Michele: non ti preoccupare pi=F9 di tanto, abbiamo letto i tuoi post = mano a mano che uscivano, li ricordiamo e quindi abbiamo subito capito che = il post che ti ha fatto arrabbiare non era sincero. E ci=F2 va a sfavore di= chi lo ha scritto. Per verificarlo basta andarsi a leggere i tuoi post che= sono la a testimoniarlo. Avanti tutta. 29 aprile 2009 12.49 Anonimo ha detto... GRANDE MICHELE PER IL TUO MODO DI ESSERE,TI APPREZZO NON SOLO PER LA TUA C= OMPETENZA MA PER LA TUA LEALTA'CONTINUA COSI' 29 aprile 2009 13.17 Anonimo ha detto... caro michele, oltre che essere molto bravo e competente sei soprattutto un= a persona onesta....complimeti 29 aprile 2009 13.20 Anonimo ha detto... Nella vita =E8 importante essere a posto con la propria coscienza, perch= =E8 c'=E8 sempre qualcuno che non la pensa come te. Forza Michele!!!! 29 aprile 2009 14.48 Anonimo ha detto... Grande Michele !!!!! ciao genio michele nista GUARDATE ORA, PLS, COSA EMAIL AVA, LO STESSO CRIMINALISSIMO, PURE MANDANTE= DI OMICIDI O 'RAFFINATE SUICIDATE", RAZZISTA, NAZISTA, MEGA LAVA CASH MAFI= OSO COME POLITI-C-RIMINALE, PAOLO BARRAI, DOPO CHE MICHELE NISTA NON VOLLE = AVERCI PIU' NULLA A CHE FARE, NELL'AGOSTO 2009, VENENDO A SAPERE CHE LO STE= SSO RICICLAVA SOLDI DI COSA NOSTRA, CAMORRA, NDRANGHETA, COME PURE SOLDI RU= BATI DA LL, LEGA LADRONA E PDL, POPOLO DI LADRONI, UNITI A CASH STRA COLMO = DI CORRUTELA DI PADANAZISTE E BERLUSCONAZISTE FINMECCANICA, ENAV E TECHNOSK= Y! da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Oggi sono andato a pisciare sulla tomba di tuo padre, piu' tardi ci vado= a cagare pure. Ha fatto bene Berlusconi a farlo ammazzare, ahahahah. Grazi= e per farti scroccare su euro, gas naturale e caffe robusta. Io sbaglio sem= pre nei mercati, ma grazie a te, riesco ancora a sopravvivere, ahahaha". --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com "Presto Berlusconi e il mio Bossi, manderanno sicari mafiosi o dei servizi= segreti, a Londra, a farti sparare, ahahaha. Ti scrocchiamo e poi ti spari= amo pure, come si fa con un ciupa ciupa usato, ahahah. L'Italia e' nostra, = e' nazifascista. A morte gli ebrei. A noi!!!" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Speriamo che ti venga una trombosi alla gamba, ho fatto un post di solid= arieta' su di te, per fingermi corretto, in realta', non vedo l'ora che ti = ammazzano. Voi bastardi ebrei, o amici di ebrei, dovrete tutti crepare soff= rendo" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Ti ho fatto infiltrare da Filati del Piemonte, da Angelo Pegli, da Gianl= uca Gualandri, da Stelvio Callimaci, sei pieno di mie spie. Io prendo un po= ' di prestanome, e ti infiltro. E intanto, faccio passare per mie, idee che= sono tue. E fra poco ti faro' pure sparare a Londra, ahahahah. Crepa basta= rdo, chi lavora con gli ebrei, deve bruciare nei forni". --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Stelvio Callimaci sta facendo un ottimo lavoro, mi passa tutti i tuoi in= puts e io li faccio passare per miei, ahahahahaah; manda inputs, manda, e i= o vi faccio i soldi, ahahahah; presto ti spariamo in faccia, Nista comunist= a di merda, Berlusconi e Bossi non si criticano, si adorano, ahahahaha; noi= della Lega, presto faremo migliaia di morti" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " bravo ottimi post continua cos=EC.. presto ti spariamo in faccia... Nist= a, sei il primo della lista, la Lega spara, ammazza, non perdona, il mondo = e' nostro, della destra... Paolo Barrai ammazza, la Lega ammazza, ahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " sei troppo dolce ti sta forse leccando il culo tua ma-re!!! hahahaha, vai vai.... ma non perdere lucidit=E0 per i tuoi clienti....attendono impazienti gli i= nputs" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " di infiltrati come stelvio e filati ne abbiamo tanti ahahahaah, e presto= ti verremo a trovare a Londra, io e Michele Milla, e come facemmo con Ubal= do Gaggio, ti ammazzeremo, ahaha" ---- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " non correre...la gamba potrebbe non seguirti... Nista, presto saliremo a= Londra e ti spareremo in bocca.... la mia Lega non perdona, la Lega uccide= , ahhaha.. e' vero, abbiamo ammazzato noi Giorgio Panto e Paolo Alberti, pe= rche' andarono con Prodi, e presto ammazzeremo anche a te, la Lega non perd= ona, la Lega ammazza tantissimo... ahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " credo che stai per finire...ahahahaha.. fra poco ti spariamo in bocca, N= ista bastardo, Nista primo della lista, anzi no...abbiamo bisogno dei tuoi = articoli da esaltato.. ti diamo ancora 15 giorni e poi ti spariamo in facci= a, la Lega ammazza, Bossi fa ammazzare, prepara il testamento, sei morto, a= hah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " mi dicono che a londra stanno predisponendo un forno .....e gli manca ma= teriale!!! vi ficchiamo dentro te e William Levi... voglio un nuovo nazismo= .. voglio vedere tutti gli ebrei e chi lavora con gli ebrei, come fai te, b= ruciare... evviva il nazismo.. evviva la Lega, che e' il nuovo nazismo, Ber= lusconi muove la mafia, noi i nazisti, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " buona trombosi.. Nista ti ammazziamo noi, se vuoi.. crepa presto o noi d= el Pdl e della Lega ti ammazziamo.. come gia' abbiamo fatto con tuo padre..= Berlusconi e Bossi ammazzano, e presto lo vedrai.. Heil Hitler, Heil Musso= lini, Heil Bossi, Heil Berlusconi, Heil Barrai, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " ahahahahaha, presto ti spareremo in faccia...Nista sei morto, Nista ti a= mmazzeremo, Nista sei condannato a crepare... Nista, divieni Berlusconiano,= come ti volevo fare diventare un anno fa, o ti ammazziamo, Nista morto, ah= aah" 3) da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " grazie per la fantastica azzeccata su dow jones, gas naturale e per il t= antissimo resto.. ahahahaha, vamos siamo forti! non mi morire per strada!!! come mi ha detto Don...non mi morire per strada...perche' fra poco salgo i= o a Londra, a scaricarti una p38 in bocca... Stefano Bassi de il Grande Blu= ff e io siamo assassini, terroristi neri, e presto ti ammazzeremo, ahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " sempre nemici... ognuno persegue i suoi obbiettivi.... tanto tu sei cond= annato a morte... Berlusconi e Bossi han gia deciso: Nista come Falcone e B= orsellino, Nista sparato in bocca, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " non ti deconcentro, scusa devi preparar i report che cos=EC ci dai gli inputs vincentissimi come sem= pre, scusami... dai impegnati, impegnati, che presto io, Berlusconi e Bossi= , ti faremo sparare dritto in faccia, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Marina Berlusconi ha gia' messo il pollice verso, Marina Berlusconi ti h= a condannato a morte..ha gia' avvertito la mafia di eseguire, di ammazzarti= .. e se non esegue la mafia, eseguono i servizi segreti di destra, fascisti= come me, della Lega ... Nista sei un morto ormai, ahahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " ahahahah, passa ancora un po' di dritte che qui si fanno soldi a palate.= ..lavora schiavo... lavora, che fra poco, Berlusconi e Bossi ti fanno spara= re in bocca.. via nostre Mafia e Servizi Segreti.... non criticare mai piu'= Berlusconi o ti ammazziamo, bastardo.. Berlusconi e Bossi non si criticano= , si adorano.. il problema e' che Marina Berlusconi ha gia' ordinato di amm= azzarti, e quella non perdona, la Lega e' il nuovo nazismo e tappa le bocch= e ammazzando, Nista, ormai sei morto, ahahahhah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " salutami william levi ...lo sento bruciare...come legna sul fuoco....o m= eglio ...il suo cadavere puo' essere usato per il sapone, ahahahahah..prest= o sara' nuovo nazismo, e chiunque lavora con gli ebrei come fai te... diver= ra' legna per i forni, ahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " fammi qualche articolo come nel passato .....ti prego tantissimo. A nata= le ti regalo un forno crematorio per William... Nista, noi Berlusconiani si= amo la mafia, e tu sei condannato a morte, cosi' impari a non divenire uno = dei nostri, ahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " attento a chi incontri a londra.....! ahahahaah... dai, sei bravo, azzec= chi sempre, e' vero, voglio scroccarti un po' di piu', prima di ammazzarti.= .. Nista e Levi nei forni di Auschwitz, si, nei forni di Auschwitz, w la Le= ga, w il Nazismo" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " POVERO BASTARDO CHE SI PERMETTE DI ESSERE DI CENTROSINISTRA: PRESTO TI S= CHIACCEREMO, LA LEGA UCCIDE, BERLUSCONI UCCIDE, IO, PAOLO BARRAI, UCCIDO, W= LA LEGA, W IL NAZISMO, W LA MAFIA, E INTANTO TI SCROCCO SEMPRE" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " MI DICONO CHE DI NOTTE SULLA TOMBA DI TUO PADRE CI VANNO A CAGARE I VERM= I... E ANCHE CHE PRESTO TI AMMAZZERANNO A LONDRA... FATTI SCROCCARE IN SILE= NZIO O IO E STEFANO BASSI DE IL GRANDE BLUFF TI FAREMO AMMAZZARE... ANCHE S= TEFANO BAGNOLI E' UN ASSASSINO COME NOI... NISTA, LA SENTENZA C'E', PRESTO = TI AMMAZZEREMO, W LA LEGA, W IL NAZISMO, W IL PDL, W LA MAFIA, AAAAHAHA" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " sei un bastardo che si permette l'impermettibile: essere di centrosinist= ra! e questo basta e avanza per essere sparato in faccia, la Lega uccide, B= erlusconi uccide, io, Paolo Barrai, uccido, w la Lega, e il Nazismo, w Berl= usconi, w la Mafia, a noi, a noi, sei morto, ahaahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " ahahahaha attento ai contatti che hai nella city e wall street, se non s= ono con nazifascisti come noi... presto tu, william levi, goldman sachs, tu= tti ebrei di merda ( tranne te, che pero' lavori per gli ebrei), brucerete = nei forni di Cernusco sul Naviglio, che sara' la nuova Auschwitz...ahahahah= " From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: An English sentence? Date: Wed, 05 Nov 2014 13:49:03 -0500 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Nov 2014 18:49:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14303"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/gpMPrUTFQT+rVgY2IEYfz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:YTeV313XA9Oinj4EQpigdmItDTc= Xref: mx02.eternal-september.org comp.lang.vhdl:7820 On 11/5/2014 8:50 AM, Anssi Saari wrote: > Alan Fitch writes: > >> Set A to '1' is fine, but I would probably say >> >> assign '1' to A >> or >> assign the value '1' to A >> >> simply because it is referred to as signal assignment in the standard, > > OTOH, if the paper discusses generated hardware rather than pure VHDL, > then I'd prefer set. I agree with both of you. -- Rick From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.68.212.169 with SMTP id nl9mr655098pbc.0.1415230039765; Wed, 05 Nov 2014 15:27:19 -0800 (PST) X-Received: by 10.50.4.36 with SMTP id h4mr387082igh.1.1415230039648; Wed, 05 Nov 2014 15:27:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no6487452igd.0!news-out.google.com!c9ni6259igv.0!nntp.google.com!h15no6487442igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 15:27:18 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=220.255.96.166; posting-account=dAcMTAoAAAAThaIUTdpeJSARKG5Mzqlp NNTP-Posting-Host: 220.255.96.166 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Subject: VHDl - A little help please From: Kai Injection-Date: Wed, 05 Nov 2014 23:27:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7821 A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that implements such a system. Compile and verify the functionality of the program with appropriate test cases. How do I write the statement for this ? If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented I am able to write this in C and C++ programming but how do i that in VHDL? From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.182.120.8 with SMTP id ky8mr936212obb.14.1415234674794; Wed, 05 Nov 2014 16:44:34 -0800 (PST) X-Received: by 10.50.152.100 with SMTP id ux4mr453871igb.6.1415234674579; Wed, 05 Nov 2014 16:44:34 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no6517766igd.0!news-out.google.com!c9ni6262igv.0!nntp.google.com!r10no4401566igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 16:44:33 -0800 (PST) In-Reply-To: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <1c21ab6d-b0d7-4f3d-88bd-36d34d0e2093@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: An English sentence? From: Weng Tianxiang Injection-Date: Thu, 06 Nov 2014 00:44:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 25 Xref: mx02.eternal-september.org comp.lang.vhdl:7822 On Tuesday, November 4, 2014 12:20:02 PM UTC-8, Weng Tianxiang wrote: > Hi, > > I am writing a paper now. I am not sure which English sentence is right in VHDL: > > signal A : std_logic; > > ... > > A <= '1'; > > 1. set A to '1'; -- I am now using. > 2. set A equal to '1'; > 3. set '1' to A; > > Thank you. > > Weng Alan, Anssi and rick, I am very glad that three of you gave my reply. I would like to do a great change in my paper to use "assign '1' to A". Thank you very much. Weng From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.70.61.33 with SMTP id m1mr1438170pdr.0.1415242579097; Wed, 05 Nov 2014 18:56:19 -0800 (PST) X-Received: by 10.140.94.212 with SMTP id g78mr25642qge.0.1415242578816; Wed, 05 Nov 2014 18:56:18 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6563431igd.0!news-out.google.com!u5ni26qab.1!nntp.google.com!u7no2739867qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Nov 2014 18:56:18 -0800 (PST) In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <919c067a-74a8-43b2-91bb-64df7e866ab5@googlegroups.com> Subject: Re: VHDl - A little help please From: KJ Injection-Date: Thu, 06 Nov 2014 02:56:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7823 On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? Post your code in C and then I'm sure someone will translate it into VHDL Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: Wed, 05 Nov 2014 22:52:37 -0500 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 6 Nov 2014 03:53:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26423"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/TM1cQQojdWG5b5Bzo4kXT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Cancel-Lock: sha1:v8/gL95+KoR5WDg3gpQtHgUhwMY= Xref: mx02.eternal-september.org comp.lang.vhdl:7824 On 11/5/2014 6:27 PM, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? I'm old school. I think in terms of the logic. So I design the logic in my head as I go along and code the VHDL to describe the hardware. After all, HDL stands for hardware description language. Can you picture the logic you would need to implement the above requirements? -- Rick From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: 6 Nov 2014 08:52:52 GMT Lines: 42 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> X-Trace: individual.net I32pxh3iL+o7OaoRP6mfqAruF1RjrufuBPY5Fcn1daEEsco/8n X-Orig-Path: not-for-mail Cancel-Lock: sha1:HkU3pi7OhaZP3vqm9d82VsR5QBI= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7825 Hi Kai, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive > going edge of a clock input CLK. If the current D_IN is greater than > the previous D_IN by at least 2, a 3-bit output COUNT is incremented. > If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT > will not increase further, till it is reset by giving 0s at D_IN for 3 > consecutive cycles. Write a VHDL program that implements such a > system. Compile and verify the functionality of the program with > appropriate test cases. First of all I'd suggest you post with an editor that limits the amount of columns to 78 chars since it eases the reading and increases the likelihood to get an answer. Forget about VHDL and think about the logic. Breakdown your 'specification' in semantic pieces: there are registers and combinatorial elements and you may easily spot them. COUNT is incremented when D_IN is greater than previous by 2 so you need to store the previous and the current value in order to compare them and trigger the condition for COUNT to increase. COUNT is another register since it needs to store information between events. You need to count how many times you have the condition that D_IN is 0 (here you go another counter). Once you have the elements you only need to put them together. I leave this up to you since you are learning VHDL and you should make an effort to get it done (no free lunch in here!). If you have problems with your implementation than post the code and I'm sure you'll find some help. Al p.s.: tell your professor that the specification is not clear and there's room for misunderstanding on the ALARM signal since it is not stated whether can be asynchronous or should be registerd and there's no condition for ALARM to be deasserted. You'll find out in your career that most of the issues are traced back in unclear specification of the interfaces! From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.42.194.204 with SMTP id dz12mr10339364icb.16.1415289358897; Thu, 06 Nov 2014 07:55:58 -0800 (PST) X-Received: by 10.140.21.49 with SMTP id 46mr16712qgk.30.1415289358762; Thu, 06 Nov 2014 07:55:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!r10no4749167igi.0!news-out.google.com!u5ni27qab.1!nntp.google.com!i13no1729557qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Nov 2014 07:55:58 -0800 (PST) In-Reply-To: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=216.16.247.154; posting-account=uTTtcgoAAABPqu7825DzTx7-FRSU6_LI NNTP-Posting-Host: 216.16.247.154 References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Subject: Re: VHDl - A little help please From: Anton Gunman Injection-Date: Thu, 06 Nov 2014 15:55:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7826 On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: > A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input > CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When > COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase > further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that > implements such a system. Compile and verify the functionality of the program with appropriate > test cases. > > How do I write the statement for this ? > If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output > COUNT is incremented > > I am able to write this in C and C++ programming but how do i that in VHDL? Hello, The code below was NOT TESTED, so it might have some errors. The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly). You will still need to write a nice testbench to test some of the cases :) Cheers, Anton. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_module is port ( clk : in std_logic; reset : in std_logic; din_i : in std_logic_vector(2 downto 0); count_o : out std_logic_vector(2 downto 0); alarm_o : out std_logic); end my_module; architecture rtl of my_module is -- Note: you can replace these '1d, 2d' with an array signal din_1d : std_logic_vector(2 downto 0) := (others => '0'); signal din_2d : std_logic_vector(2 downto 0) := (others => '0'); signal count : unsigned(2 downto 0) := (others => '0'); signal inc_count : std_logic := '0'; signal rst_count : std_logic := '0'; signal alarm : std_logic := '0'; begin -- rtl --------------------------------------------------------------------------- -- Delay pipes, used to save the previous value(s) --------------------------------------------------------------------------- delay_pipes : process (clk) begin if rising_edge(clk) then if reset = '1' then din_1d <= (others => '0'); din_2d <= (others => '0'); else din_1d <= unsigned(din_i); din_2d <= din_1d; end if; end if; end process delay_pipes; --------------------------------------------------------------------------- -- Count 'increment' -- * Check that current value is > than previous (to avoid wraparound) -- * Check that the difference is >= 2 -- Count and alarm 'reset' -- * Check that the data is zero for 3 consecutive clock cycles. --------------------------------------------------------------------------- inc_count <= '1' when (unsigned(din_i) > d) and ((unsigned(din_i) - din_1d) >= 2) else '0'; rst_count <= '1' when (din_i = "000" and din_1d = "000" and din_2d = "000") else '0'; counter : process (clk) begin if rising_edge(clk) then if reset = '1' then count <= (others => '0'); alarm <= '0'; else if rst_count = '1' then -- Reset the count and the alarm count <= (others => '0'); alarm <= '0'; elsif inc_count = '1' then if count < 6 then -- Saturate count at 6 count <= count + 1; else -- Set the alarm if count >= 6 alarm <= '1'; end if; end if; end if; end if; end process counter; count_o <= std_logic_vector(count); alarm_o <= alarm; end rtl; From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDl - A little help please Date: Thu, 06 Nov 2014 13:48:54 -0500 Organization: A noiseless patient Spider Lines: 115 Message-ID: References: <5dd103e1-9903-41f4-8d4f-b417faef3996@googlegroups.com> <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 6 Nov 2014 18:49:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16786"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+C0o4EVQRf8CYUyuBcKBxn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <13f665bd-aa4e-4c2e-82d9-053af49ba9c1@googlegroups.com> Cancel-Lock: sha1:Xir77kwfJs94ecD5cRekXTyfhwY= Xref: mx02.eternal-september.org comp.lang.vhdl:7827 On 11/6/2014 10:55 AM, Anton Gunman wrote: > On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote: >> A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input >> CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output >> COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When >> COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase >> further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that >> implements such a system. Compile and verify the functionality of the program with appropriate >> test cases. >> >> How do I write the statement for this ? >> If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output >> COUNT is incremented >> >> I am able to write this in C and C++ programming but how do i that in VHDL? > > Hello, > > The code below was NOT TESTED, so it might have some errors. > The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly). > > You will still need to write a nice testbench to test some of the cases :) > > Cheers, > Anton. > > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity my_module is > port ( > clk : in std_logic; > reset : in std_logic; > din_i : in std_logic_vector(2 downto 0); > count_o : out std_logic_vector(2 downto 0); > alarm_o : out std_logic); > end my_module; > > architecture rtl of my_module is > -- Note: you can replace these '1d, 2d' with an array > signal din_1d : std_logic_vector(2 downto 0) := (others => '0'); > signal din_2d : std_logic_vector(2 downto 0) := (others => '0'); > signal count : unsigned(2 downto 0) := (others => '0'); > signal inc_count : std_logic := '0'; > signal rst_count : std_logic := '0'; > signal alarm : std_logic := '0'; > > begin -- rtl > > --------------------------------------------------------------------------- > -- Delay pipes, used to save the previous value(s) > --------------------------------------------------------------------------- > delay_pipes : process (clk) > begin > if rising_edge(clk) then > if reset = '1' then > din_1d <= (others => '0'); > din_2d <= (others => '0'); > else > din_1d <= unsigned(din_i); > din_2d <= din_1d; > end if; > end if; > end process delay_pipes; > > --------------------------------------------------------------------------- > -- Count 'increment' > -- * Check that current value is > than previous (to avoid wraparound) > -- * Check that the difference is >= 2 > -- Count and alarm 'reset' > -- * Check that the data is zero for 3 consecutive clock cycles. > --------------------------------------------------------------------------- > inc_count <= '1' when (unsigned(din_i) > d) and > ((unsigned(din_i) - din_1d) >= 2) else '0'; > rst_count <= '1' when (din_i = "000" and din_1d = "000" and > din_2d = "000") else '0'; > > counter : process (clk) > begin > if rising_edge(clk) then > if reset = '1' then > count <= (others => '0'); > alarm <= '0'; > else > if rst_count = '1' then > -- Reset the count and the alarm > count <= (others => '0'); > alarm <= '0'; > elsif inc_count = '1' then > if count < 6 then > -- Saturate count at 6 > count <= count + 1; > else > -- Set the alarm if count >= 6 > alarm <= '1'; > end if; > > end if; > end if; > end if; > end process counter; > > count_o <= std_logic_vector(count); > alarm_o <= alarm; > > end rtl; You do realize you are doing his homework, right? Or it may even be a test. -- Rick From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.52.138.175 with SMTP id qr15mr6890762vdb.4.1415328137002; Thu, 06 Nov 2014 18:42:17 -0800 (PST) X-Received: by 10.50.77.6 with SMTP id o6mr7878igw.8.1415328136850; Thu, 06 Nov 2014 18:42:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no1849235qae.0!news-out.google.com!ks2ni13482igb.0!nntp.google.com!h15no7253795igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 6 Nov 2014 18:42:16 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=49.156.53.254; posting-account=tKNq2QoAAADH5KHs7Y-Di-cjhMZRhRlv NNTP-Posting-Host: 49.156.53.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> Subject: Floating point in VHDL From: Dai Tran Van Injection-Date: Fri, 07 Nov 2014 02:42:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:7828 Hi everyone. I working with foating point, and i have problem with multipile maxtrix, vetor in foating.. this i's my project to go out shool on time. help me. From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Quartus II TCL or command line Date: Fri, 07 Nov 2014 06:20:47 +0100 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 7 Nov 2014 05:20:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="dcece3cc2db339bbea1130eb9b01bab7"; logging-data="8772"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hSYgzZ9X80ncNlHrkWSXB" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Cancel-Lock: sha1:FmMv39WpRMQK6lF69gp+2e+yTO0= Xref: mx02.eternal-september.org comp.lang.vhdl:7829 > how can I add vhdl files to quartus II project using TCL, or command line??? > > so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. Does "quartus_sh --qhelp" print all avalible commands? Synplify and Vivado knows the "add_file" commad. Bart Fox From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Quartus II TCL or command line Date: Fri, 07 Nov 2014 14:58:00 +0200 Organization: An impatient and LOUD arachnid Lines: 13 Message-ID: References: <72206553-9d01-48e2-9d47-07d9eecd780f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="e5afc5bc4c110b3af5789ef5c59a038f"; logging-data="30701"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18J+CgkNOGZpfQhmt5XagA9" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:9TZ6g1AJ/NNkArlF+eh9fWcFggQ= sha1:iARI0bZkNCPJeef92FQ0QmDKzRg= Xref: mx02.eternal-september.org comp.lang.vhdl:7830 AA writes: > Hi, > how can I add vhdl files to quartus II project using TCL, or command line??? > > so far I can create project using Quartus_sh --tcl_eval, but I didn't find any tcl command to add a vhdl file to the project. > > Thank you, It's the same non-intuitive command you probably already have in your .qsf files, like this: set_global_assignment -name VHDL_FILE whatever.vhdl From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.182.120.99 with SMTP id lb3mr49181613obb.10.1415978963029; Fri, 14 Nov 2014 07:29:23 -0800 (PST) X-Received: by 10.140.93.199 with SMTP id d65mr7946qge.20.1415978963003; Fri, 14 Nov 2014 07:29:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!r10no2710542igi.0!news-out.google.com!m4ni192qag.1!nntp.google.com!u7no1650465qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 07:29:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.89; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.89 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Compile OK but simulation fails From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 15:29:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3105 X-Received-Body-CRC: 2274314540 Xref: mx02.eternal-september.org comp.lang.vhdl:7831 Hello every1, I am new to VHDL just working on my first code. I am trying to realize an sqrt(x) function in a sequential wax and simulate it with Modelsim. My code looks like this : use ieee.numeric_std.ALL; entity sqroot is generic (constant NBITS : natural := 8); --design implementation port ( signal arg : in std_logic_vector(NBITS-1 downto 0); signal roundup : in std_logic := '0'; --determine if roundup is done or not signal sqroot : out std_logic_vector(NBITS/2 downto 0)); end entity sqroot; architecture rtl of sqroot is use ieee.std_logic_1164.all; use ieee.numeric_std.ALL; --Internal signal definitions signal delta : unsigned(NBITS-1 downto 0) := (0 => '1', others => '0'); begin process( arg, roundup ) --Internal variable definitions variable delta_int : integer := 1; variable sqroot_int : integer :=0; variable res_int : integer := to_integer(unsigned(arg)); begin delta <= delta sll (NBITS-2); -- shifted // temp = delta^(NBITS-2) delta_int := to_integer(delta); while (delta_int >= 1) loop if ( (sqroot_int + delta_int) <= res_int ) then res_int := res_int -(sqroot_int + delta_int); sqroot_int := sqroot_int + 2*delta_int; end if; sqroot_int := sqroot_int/2; delta_int := delta_int/4; end loop; if ( (roundup = '1') and (res_int > sqroot_int) ) then sqroot_int := sqroot_int + 1; end if; sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); end process; end architecture rtl; I end up with an error on the sqroot line right before the end : sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); fatal error simulation terminated. I don't really understand what that error is associated to. Any1 has a hint ? Thanks in advance Mario From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.68.125.134 with SMTP id mq6mr19314832pbb.7.1415996577857; Fri, 14 Nov 2014 12:22:57 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr70547qgq.7.1415996577808; Fri, 14 Nov 2014 12:22:57 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no325638igd.0!news-out.google.com!m4ni192qag.1!nntp.google.com!u7no1714181qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 12:22:57 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.89; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.89 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: problem with sll operator From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 20:22:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7832 Hello, I am facing a pretty wierd error as regards an operation which is pretty cr= utial for my code.=20 I am trying to do a left shift operation on an unsigned vector. My NBITS is= defined generically as natural and my delta vector is unsigned. All compil= es well but when i=E0m doing the simulation my delta_shifted receives X val= ues. for me that seems to suggest that the sll operation is not performed. = Any1 has an idea as to where the problem could be ? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.ALL;=20 entity sqroot_comb is generic (constant NBITS : natural :=3D 8); --design implementation port ( signal arg : in std_logic_vector(NBITS-1 downto 0); signal roundup : in std_logic :=3D '0'; --determine if roundup is done = or not signal sqroot : out std_logic_vector(NBITS/2 downto 0)); end entity sqroot_comb; =20 architecture rtl of sqroot_comb is use ieee.std_logic_1164.all; use ieee.numeric_std.ALL;=20 =20 --Internal signal definitions signal delta : unsigned(NBITS-1 downto 0);=20 signal delta_shifted : unsigned(NBITS-1 downto 0);=20 signal delta_shifted_prev : unsigned(NBITS-1 downto 0); signal res : unsigned(NBITS-1 downto 0); signal res_prev : unsigned(NBITS-1 downto 0); signal sqroot_temp_prev : unsigned(NBITS-1 downto 0); signal sqroot_temp : unsigned(NBITS-1 downto 0); =20 --Signal Assignments =20 =20 begin =20 =20 delta <=3D to_unsigned(2**(NBITS-2),delta'length); sqroot_temp <=3D to_unsigned(0,delta'length); sqroot_temp_prev <=3D to_unsigned(0,delta'length); delta_shifted_prev <=3D to_unsigned(0,delta'length); res_prev <=3D to_unsigned(0,delta'length); =20 delta_shifted <=3D (delta sll NBITS-2); -- shifted // temp =3D delta^(N= BITS-2) =20 res <=3D unsigned(arg);=20 =20 process( arg, roundup ) =20 --Internal variable definitions --variable delta_int : integer :=3D 1; --variable sqroot_int : integer :=3D0; --variable res_int : integer :=3D to_integer(unsigned(arg)); =20 begin=20 for i in 0 to 2*NBITS-1 loop if (delta_shifted >=3D 1) then if ( (sqroot_temp + delta_shifted) <=3D res ) then res <=3D res -(sqroot_temp + delta_shifted); sqroot_temp <=3D sqroot_temp + 2*delta_shifted; else sqroot_temp <=3D sqroot_temp_prev; res <=3D res_prev; delta_shifted <=3D delta_shifted_prev; end if; end if; =20 sqroot_temp <=3D sqroot_temp/2; delta_shifted <=3D delta_shifted/4; =20 --Update previous values of sqroot and residual sqroot_temp_prev <=3D sqroot_temp; res_prev <=3D res; =20 end loop; =20 if ( (roundup =3D '1') and (res > sqroot_temp) ) then sqroot_temp <=3D sqroot_temp + 1; else=20 sqroot_temp <=3D sqroot_temp_prev; end if; =20 =20 sqroot <=3D std_logic_vector(resize( sqroot_temp,sqroot'length ))= ; =20 end process;=20 =20 end architecture rtl; From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Fri, 14 Nov 2014 15:42:18 -0500 Organization: Alacron, Inc. Lines: 92 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Fri, 14 Nov 2014 20:43:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="27712"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18lbMnyTqNtrMP24ECkOZ5kp0yOOCRSGj0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:pBVlHIrpvz9XR/t5JIzDIBU/wRM= Xref: mx02.eternal-september.org comp.lang.vhdl:7833 Marios Barlas wrote: > Hello, > > I am facing a pretty wierd error as regards an operation which is pretty crutial for my code. > > I am trying to do a left shift operation on an unsigned vector. My NBITS is defined generically as natural and my delta vector is unsigned. All compiles well but when iàm doing the simulation my delta_shifted receives X values. for me that seems to suggest that the sll operation is not performed. Any1 has an idea as to where the problem could be ? > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.ALL; > > entity sqroot_comb is > generic (constant NBITS : natural := 8); --design implementation > port ( > signal arg : in std_logic_vector(NBITS-1 downto 0); > signal roundup : in std_logic := '0'; --determine if roundup is done or not > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > end entity sqroot_comb; > > architecture rtl of sqroot_comb is > use ieee.std_logic_1164.all; > use ieee.numeric_std.ALL; > > --Internal signal definitions > signal delta : unsigned(NBITS-1 downto 0); > signal delta_shifted : unsigned(NBITS-1 downto 0); > signal delta_shifted_prev : unsigned(NBITS-1 downto 0); > signal res : unsigned(NBITS-1 downto 0); > signal res_prev : unsigned(NBITS-1 downto 0); > signal sqroot_temp_prev : unsigned(NBITS-1 downto 0); > signal sqroot_temp : unsigned(NBITS-1 downto 0); > > --Signal Assignments > > begin > > delta <= to_unsigned(2**(NBITS-2),delta'length); > sqroot_temp <= to_unsigned(0,delta'length); > sqroot_temp_prev <= to_unsigned(0,delta'length); > delta_shifted_prev <= to_unsigned(0,delta'length); > res_prev <= to_unsigned(0,delta'length); > > delta_shifted <= (delta sll NBITS-2); -- shifted // temp = delta^(NBITS-2) > res <= unsigned(arg); > > process( arg, roundup ) > > --Internal variable definitions > --variable delta_int : integer := 1; > --variable sqroot_int : integer :=0; > --variable res_int : integer := to_integer(unsigned(arg)); > > begin > > for i in 0 to 2*NBITS-1 loop > if (delta_shifted >= 1) then > if ( (sqroot_temp + delta_shifted) <= res ) then > res <= res -(sqroot_temp + delta_shifted); > sqroot_temp <= sqroot_temp + 2*delta_shifted; > else > sqroot_temp <= sqroot_temp_prev; > res <= res_prev; > delta_shifted <= delta_shifted_prev; > end if; > end if; > > sqroot_temp <= sqroot_temp/2; > delta_shifted <= delta_shifted/4; > > --Update previous values of sqroot and residual > sqroot_temp_prev <= sqroot_temp; > res_prev <= res; > > end loop; > > if ( (roundup = '1') and (res > sqroot_temp) ) then > sqroot_temp <= sqroot_temp + 1; > else > sqroot_temp <= sqroot_temp_prev; > end if; > > sqroot <= std_logic_vector(resize( sqroot_temp,sqroot'length )); > > end process; > > end architecture rtl; The first thing I noticed is that delta_shifted doesn't have enough bits to represent the shifted value. Maybe that has something to do with it? -- Gabor From newsfish@newsfish Tue Dec 29 16:43:35 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed4-a.proxad.net!nnrp1-2.free.fr!not-for-mail Date: Fri, 14 Nov 2014 22:43:20 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <54667774$0$2070$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 14 Nov 2014 22:43:16 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1416001396 news-4.free.fr 2070 88.185.146.198:1164 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:7834 Hello Le 14/11/2014 21:22, Marios Barlas a écrit : > Hello, > > I am facing a pretty wierd error as regards an operation which is pretty crutial for my code. > > I am trying to do a left shift operation on an unsigned vector. My NBITS is defined generically as natural and my delta vector is unsigned. All compiles well but when iàm doing the simulation my delta_shifted receives X values. for me that seems to suggest that the sll operation is not performed. Any1 has an idea as to where the problem could be ? You have a conflict on delta_shifted. You have a concurrent assignment (6th assignment after the architecture's "begin") and you assign values to it in the process. You're from a computer programming background, aren't you ? Nicolas From newsfish@newsfish Tue Dec 29 16:43:35 2015 X-Received: by 10.236.98.71 with SMTP id u47mr51581430yhf.30.1416004825937; Fri, 14 Nov 2014 14:40:25 -0800 (PST) X-Received: by 10.140.102.117 with SMTP id v108mr36038qge.36.1416004825909; Fri, 14 Nov 2014 14:40:25 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i13no1739899qae.0!news-out.google.com!m4ni193qag.1!nntp.google.com!u7no1739321qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 14 Nov 2014 14:40:25 -0800 (PST) In-Reply-To: <54667774$0$2070$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.254.155; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.254.155 References: <54667774$0$2070$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Fri, 14 Nov 2014 22:40:25 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7835 =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, 14 =CE= =9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE=BC.= =CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Ma= tringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > Hello >=20 > Le 14/11/2014 21:22, Marios Barlas a =C3=A9crit : > > Hello, > > > > I am facing a pretty wierd error as regards an operation which is prett= y crutial for my code. > > > > I am trying to do a left shift operation on an unsigned vector. My NBIT= S is defined generically as natural and my delta vector is unsigned. All co= mpiles well but when i=C3=A0m doing the simulation my delta_shifted receive= s X values. for me that seems to suggest that the sll operation is not perf= ormed. Any1 has an idea as to where the problem could be ? >=20 > You have a conflict on delta_shifted. You have a concurrent assignment=20 > (6th assignment after the architecture's "begin") and you assign values= =20 > to it in the process. > You're from a computer programming background, aren't you ? >=20 > Nicolas Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 y= ears master's in nanotechnology the last semester of which is in microelect= ronics. As a result us stupid physics people lack a good deal of background= that others have for granted. This is my first bit of code in VHDL. Apolog= izing for my ignorance in advance, I am guessing you are referring to=20 delta_shifted <=3D delta sll NBITS-1 but this is exactly what I would like to do, shift the bits of my vector re= presentation to the left. I was under the impression that sll would basical= ly shift the bits to the left adding zeros on the right-most columns. Also = the comment above seems logical, I probably need more bits so that I won't = lose information, right ? From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sat, 15 Nov 2014 11:59:22 +0000 (UTC) Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 15 Nov 2014 11:59:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="19791"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/K2JAHOdrhKEo+Y2Wq+k76q9ETMJA48Ck=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:mFCmf/CYao+KyQWRxo2jhmkMaO4= Xref: mx02.eternal-september.org comp.lang.vhdl:7836 On Fri, 14 Nov 2014 14:40:25 -0800, Marios Barlas wrote: > Τη ΠαÏασκευή, 14 ÎοεμβÏίου 2014 10:43:19 μ.μ. UTC+1, ο χÏήστης Nicolas > Matringe έγÏαψε: >> Hello >> >> Le 14/11/2014 21:22, Marios Barlas a écrit : >> > Hello, >> > >> > but when iàm doing the simulation my >> > delta_shifted receives X values. >> You have a conflict on delta_shifted. You have a concurrent assignment >> (6th assignment after the architecture's "begin") and you assign values >> to it in the process. > Apologizing for my ignorance in advance, I am guessing you are > referring to > > delta_shifted <= delta sll NBITS-1 > > but this is exactly what I would like to do, shift the bits of my vector > representation to the left. No, you missed Nicolas' point. You have created two pieces of circuitry driving delta_shifted - one is the process, the other is the concurrent statement delta_shifted <= (delta sll NBITS-2); -- shifted // temp = These two circuits have their outputs short circuited to each other, and that short circuit creates the Xes, not the shift operation itself. The usual solution is to decide which circuit should be permitted to drive delta_shifted, and eliminate the other. (Usually, keep the process, and move the other statement to an appropriate part of the process.) - Brian From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Compile OK but simulation fails Date: Sat, 15 Nov 2014 12:03:39 +0000 (UTC) Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 15 Nov 2014 12:03:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="19791"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+7JFAmtTHe6Yy92Ia7azW10sSbg8NAlvc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:++44N+ZJeo9pUvB3wLiACl8+McI= Xref: mx02.eternal-september.org comp.lang.vhdl:7837 On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote: > Hello every1, > > I am new to VHDL just working on my first code. I am trying to realize > an sqrt(x) function in a sequential wax and simulate it with Modelsim. > > My code looks like this : > > use ieee.numeric_std.ALL; > > entity sqroot is > generic (constant NBITS : natural := 8); --design implementation port > ( > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > end entity sqroot; > > I end up with an error on the sqroot line right before the end : > > sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); You have probably already solved this, but for completeness : there is both an entity and signal with the same name sqroot, so some expressions like sqroot'length may be ambiguous... - Brian From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.224.120.71 with SMTP id c7mr56100686qar.4.1416068296989; Sat, 15 Nov 2014 08:18:16 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr849qgq.7.1416068296945; Sat, 15 Nov 2014 08:18:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w8no24792qac.0!news-out.google.com!w7ni0qay.0!nntp.google.com!w8no24789qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Nov 2014 08:18:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.183.75; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.183.75 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9041a195-e199-4756-8890-21612a7244bc@googlegroups.com> Subject: Re: Compile OK but simulation fails From: Marios Barlas Injection-Date: Sat, 15 Nov 2014 16:18:16 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7838 =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 1:03:52 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Brian Drummond =CE=AD=CE= =B3=CF=81=CE=B1=CF=88=CE=B5: > On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote: >=20 > > Hello every1, > >=20 > > I am new to VHDL just working on my first code. I am trying to realize > > an sqrt(x) function in a sequential wax and simulate it with Modelsim. > >=20 > > My code looks like this : > >=20 > > use ieee.numeric_std.ALL; > >=20 > > entity sqroot is > > generic (constant NBITS : natural :=3D 8); --design implementation p= ort > > ( > > signal sqroot : out std_logic_vector(NBITS/2 downto 0)); > > end entity sqroot; > > =20 >=20 > > I end up with an error on the sqroot line right before the end : > >=20 > > sqroot <=3D std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); >=20 > You have probably already solved this, but for completeness : there is=20 > both an entity and signal with the same name sqroot, so some expressions= =20 > like sqroot'length may be ambiguous... >=20 > - Brian Thanks for the answer Brian! Yes I resolved it, I'm sorry for the stupid qu= estions of a rookie but newsgroups are in my opinion the best way to ask ex= perienced people.=20 With appreciation, Marios Barlas From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Sat, 15 Nov 2014 22:50:11 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator References: <54667774$0$2070$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 28 Message-ID: <5467ca8f$0$2908$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 15 Nov 2014 22:50:07 CET NNTP-Posting-Host: 88.185.146.198 X-Trace: 1416088207 news-1.free.fr 2908 88.185.146.198:1201 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:7839 Le 14/11/2014 23:40, Marios Barlas a écrit : > Τη ΠαÏασκευή, 14 ÎοεμβÏίου 2014 10:43:19 μ.μ. UTC+1, ο χÏήστης Nicolas Matringe έγÏαψε: [...] >> You're from a computer programming background, aren't you ? > Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. Sorry for my wrong guess, then. You wrote your VHDL like you'd write a program in C for example. It doesn't work like that. VHDL is a description language, not a programming language. It is like a schematics, except it is in text form. Concurrent expressions (i.e. that are outside of processes) are independent blocks in your schematics. This also means that their order in the code doesn't matter at all. As Brian explained, concurrently assigning something to a signal is like connecting the output of a logic function to this signal. Concurrently assigning several times to the same signal is connecting several outputs together. You usually don't want to do that (this causes your Xs in simulation) You seem to assume your code is executed from top to bottom. It is not. It is not even executed, since VHDL is not a programming language. What you want is a block that takes a number and, after several iterations, outputs its square root, am I right ? So you want to initialize some internal signals or variables then step by step compute the square root and finally output the result. So you need some simple sequencer (a counter will do), and a clock to make it run. Nicolas From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.67.16.99 with SMTP id fv3mr58170592pad.5.1416091090619; Sat, 15 Nov 2014 14:38:10 -0800 (PST) X-Received: by 10.50.36.9 with SMTP id m9mr138570igj.2.1416091090503; Sat, 15 Nov 2014 14:38:10 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no907991igd.0!news-out.google.com!ks2ni20433igb.0!nntp.google.com!r10no3153126igi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 15 Nov 2014 14:38:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=222.153.121.187; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 222.153.121.187 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8d5e24fd-79a6-4a17-a78e-e8dd872b721a@googlegroups.com> Subject: Re: Compile OK but simulation fails From: diogratia@gmail.com Injection-Date: Sat, 15 Nov 2014 22:38:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7840 On Saturday, November 15, 2014 4:29:26 AM UTC+13, Marios Barlas wrote: > My code looks like this : > > use ieee.numeric_std.ALL; > > > I end up with an error on the sqroot line right before the end : > > sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length)); The to_unsigned function found in package numeric_std expects a natural. Passing it a negative value would be erroneous. function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is variable RESULT: UNSIGNED(SIZE-1 downto 0); variable I_VAL: NATURAL := ARG; The variable I_VAL (and RESULT) are dynamically elaborated. Assigning a negative ARG would fail. The signature for TO_UNSIGNED allows an integer (a natural is a constrained integer, a subtype of the type integer). That would speak to a an algorithm implementation issue. You might consider adding an integer signal to receive sq_root_int, and comment out the above statement so you can see what's going on. It might help for others to know what your input was for the failed case (arg, roundup). From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.68.228.164 with SMTP id sj4mr32653568pbc.8.1416131081280; Sun, 16 Nov 2014 01:44:41 -0800 (PST) X-Received: by 10.140.37.83 with SMTP id q77mr1723qgq.7.1416131081021; Sun, 16 Nov 2014 01:44:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1135444igd.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no173043qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 01:44:40 -0800 (PST) In-Reply-To: <5467ca8f$0$2908$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.254.48; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.254.48 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 09:44:41 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7841 =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. UTC+1,= =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe =CE=AD= =CE=B3=CF=81=CE=B1=CF=88=CE=B5: > Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > > =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, 14= =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > [...] > >> You're from a computer programming background, aren't you ? > > Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a= 2 years master's in nanotechnology the last semester of which is in microe= lectronics. As a result us stupid physics people lack a good deal of backgr= ound that others have for granted. This is my first bit of code in VHDL. >=20 > Sorry for my wrong guess, then. You wrote your VHDL like you'd write a=20 > program in C for example. It doesn't work like that. >=20 > VHDL is a description language, not a programming language. It is like a= =20 > schematics, except it is in text form. Concurrent expressions (i.e. that= =20 > are outside of processes) are independent blocks in your schematics.=20 > This also means that their order in the code doesn't matter at all. > As Brian explained, concurrently assigning something to a signal is like= =20 > connecting the output of a logic function to this signal. Concurrently=20 > assigning several times to the same signal is connecting several outputs= =20 > together. You usually don't want to do that (this causes your Xs in=20 > simulation) > You seem to assume your code is executed from top to bottom. It is not.= =20 > It is not even executed, since VHDL is not a programming language. What= =20 > you want is a block that takes a number and, after several iterations,=20 > outputs its square root, am I right ? So you want to initialize some=20 > internal signals or variables then step by step compute the square root= =20 > and finally output the result. So you need some simple sequencer (a=20 > counter will do), and a clock to make it run. >=20 > Nicolas Thanks for the reply Nicolas. Finally I wrote my code in dataflow using sta= ges and it works perfectly. But I'll write it again with a process and cloc= k! thanks for your feedback ! From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.52.76.227 with SMTP id n3mr61852216vdw.9.1416153107365; Sun, 16 Nov 2014 07:51:47 -0800 (PST) X-Received: by 10.140.17.69 with SMTP id 63mr4283qgc.10.1416153107305; Sun, 16 Nov 2014 07:51:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!u7no2077365qaz.1!news-out.google.com!m4ni197qag.1!nntp.google.com!u7no2077363qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 07:51:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.178.158.91; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.178.158.91 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Subject: Warning interpretation ? From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 15:51:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2215 X-Received-Body-CRC: 2205117604 Xref: mx02.eternal-september.org comp.lang.vhdl:7842 Hello, I am getting a warning on my code like : # ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE # Time: 0 ns Iteration: 0 Region: /sqroot_comb_tb/DUV/STAGES(3) # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE ********************************************* # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE # Time: 0 ns Iteration: 4 Region: /sqroot_comb_tb/DUV/STAGES(3) My code implements the calculation of an integer square root in 4 stages in dataflow. It doesn't seem to have a negative effect on the computation or on the synthesis phase. I am using Modelsim for coding/simulation and Synopsis for synthesis. I suspect it comes from the fact that I introduce an array of vectors like this : type r_size is array (0 to NBITS/2) of unsigned(NBITS-1 downto 0); signal sqroot2 : r_size; signal delta : r_size; signal res : r_size; and I initialize only the 1st element res(0) <= unsigned(arg); with my input vector. In the algorithm however I have an assignment like : res(i+1) <= res(i); Can I circumvent the problem or should I just leave it like that? Thanks in advance! Marios Barlas From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.182.230.200 with SMTP id ta8mr65704819obc.11.1416167105143; Sun, 16 Nov 2014 11:45:05 -0800 (PST) X-Received: by 10.50.124.8 with SMTP id me8mr222554igb.3.1416167105011; Sun, 16 Nov 2014 11:45:05 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no155528igb.0!news-out.google.com!c9ni14081igv.0!nntp.google.com!h15no1451458igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 11:45:04 -0800 (PST) In-Reply-To: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5081dfd4-567a-47d5-91cc-be542b8370ba@googlegroups.com> Subject: Re: Warning interpretation ? From: Jim Lewis Injection-Date: Sun, 16 Nov 2014 19:45:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7843 Hi Marios, At startup all std_logic family has a 'U' by default. When the math functions, such as relationals (>=, <=, ...) see a 'U' (or string of them), they return FALSE. As long as this is happening before your circuit becomes active, it is ok. If it is happening later in simulation, you need to research why it is getting a 'U'. Cheers, Jim From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sun, 16 Nov 2014 14:59:36 -0500 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 16 Nov 2014 19:59:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+m+Onem7AXRIY0+K/QMMsg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> Cancel-Lock: sha1:oSWcbyWbegjVw6AmDrRr4Jv9/s0= Xref: mx02.eternal-september.org comp.lang.vhdl:7844 On 11/16/2014 4:44 AM, Marios Barlas wrote: > Τη Σάββατο, 15 ÎοεμβÏίου 2014 10:50:10 μ.μ. UTC+1, ο χÏήστης Nicolas Matringe έγÏαψε: >> Le 14/11/2014 23:40, Marios Barlas a écrit : >>> Τη ΠαÏασκευή, 14 ÎοεμβÏίου 2014 10:43:19 μ.μ. UTC+1, ο χÏήστης Nicolas Matringe έγÏαψε: >> [...] >>>> You're from a computer programming background, aren't you ? >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. >> >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a >> program in C for example. It doesn't work like that. >> >> VHDL is a description language, not a programming language. It is like a >> schematics, except it is in text form. Concurrent expressions (i.e. that >> are outside of processes) are independent blocks in your schematics. >> This also means that their order in the code doesn't matter at all. >> As Brian explained, concurrently assigning something to a signal is like >> connecting the output of a logic function to this signal. Concurrently >> assigning several times to the same signal is connecting several outputs >> together. You usually don't want to do that (this causes your Xs in >> simulation) >> You seem to assume your code is executed from top to bottom. It is not. >> It is not even executed, since VHDL is not a programming language. What >> you want is a block that takes a number and, after several iterations, >> outputs its square root, am I right ? So you want to initialize some >> internal signals or variables then step by step compute the square root >> and finally output the result. So you need some simple sequencer (a >> counter will do), and a clock to make it run. >> >> Nicolas > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using stages and it works perfectly. But I'll write it again with a process and clock! thanks for your feedback ! I'm curious about the course where you are learning VHDL. I remember about a million years ago when I was in college that I took a my first computer programming course. It was one part of six in a lab course in chemistry. I believe it was just two weeks. I now know they were doing their students a huge disservice by giving them such a limited amount of training and then releasing them into the world to write their own programs. I'm wondering if you are learning VHDL in a similar manner. VHDL is not a terrible language to learn, but any HDL is a bit different from computer programming in that they are inherently parallel rather than sequential. Computer programming languages come naturally because they are sequential reading the same as a recipe. HLDs are describing the functionality of hardware with it working in parallel. So there are different rules to it than you may be used to in software. -- Rick From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Sun, 16 Nov 2014 15:08:23 -0500 Organization: A noiseless patient Spider Lines: 53 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 16 Nov 2014 20:08:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="27671"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zI/QB4CY9V8UYJl+B8AeV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Cancel-Lock: sha1:oWYyXDKsE/iZ3wsfVkPmiPCS1HU= Xref: mx02.eternal-september.org comp.lang.vhdl:7845 On 11/16/2014 10:51 AM, Marios Barlas wrote: > Hello, > > I am getting a warning on my code like : > # ** Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE > # Time: 0 ns Iteration: 0 Region: /sqroot_comb_tb/DUV/STAGES(3) > # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE > > ********************************************* > # ** Warning: NUMERIC_STD."<=": metavalue detected, returning FALSE > # Time: 0 ns Iteration: 4 Region: /sqroot_comb_tb/DUV/STAGES(3) > > My code implements the calculation of an integer square root in 4 stages in dataflow. It doesn't seem to have a negative effect on the computation or on the synthesis phase. I am using Modelsim for coding/simulation and Synopsis for synthesis. > > I suspect it comes from the fact that I introduce an array of vectors like this : > type r_size is array (0 to NBITS/2) of unsigned(NBITS-1 downto 0); > signal sqroot2 : r_size; > signal delta : r_size; > signal res : r_size; > > and I initialize only the 1st element > > res(0) <= unsigned(arg); > > with my input vector. > > In the algorithm however I have an assignment like : > > res(i+1) <= res(i); > > Can I circumvent the problem or should I just leave it like that? This is like exploring the cold dusty areas of my mind. The problems you are having are ones I had a long time ago and have learned to simply step around. lol If I remember correctly, this warning is because the comparison operators >= and <= are seeing an input which is not all '1's and '0's (and possibly 'H's and 'L's). While it is not likely of consequence at time 0 you can easily code around it by making sure your signals and variables are initialized. Your assignment res(i+1) <= res(i); is fine assuming you start with an initialized value. It is the comparisons that are biting you. I recommend that you fix your code to get rid of warnings. Otherwise you become inured to them and eventually they will cause you to miss a valid warning that you need to pay attention to. Just initialize the full array to something that isn't a letter... ;) -- Rick From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.66.246.109 with SMTP id xv13mr62886936pac.15.1416171374476; Sun, 16 Nov 2014 12:56:14 -0800 (PST) X-Received: by 10.140.101.227 with SMTP id u90mr1425qge.18.1416171374426; Sun, 16 Nov 2014 12:56:14 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1493598igd.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no304804qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 12:56:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.70.30.51; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 195.70.30.51 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 20:56:14 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7846 =CE=A4=CE=B7 =CE=9A=CF=85=CF=81=CE=B9=CE=B1=CE=BA=CE=AE, 16 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 9:00:12 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > On 11/16/2014 4:44 AM, Marios Barlas wrote: > > =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE= =BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. = UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe = =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > >>> =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, = 14 =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> [...] > >>>> You're from a computer programming background, aren't you ? > >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing= a 2 years master's in nanotechnology the last semester of which is in micr= oelectronics. As a result us stupid physics people lack a good deal of back= ground that others have for granted. This is my first bit of code in VHDL. > >> > >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a > >> program in C for example. It doesn't work like that. > >> > >> VHDL is a description language, not a programming language. It is like= a > >> schematics, except it is in text form. Concurrent expressions (i.e. th= at > >> are outside of processes) are independent blocks in your schematics. > >> This also means that their order in the code doesn't matter at all. > >> As Brian explained, concurrently assigning something to a signal is li= ke > >> connecting the output of a logic function to this signal. Concurrently > >> assigning several times to the same signal is connecting several outpu= ts > >> together. You usually don't want to do that (this causes your Xs in > >> simulation) > >> You seem to assume your code is executed from top to bottom. It is not= . > >> It is not even executed, since VHDL is not a programming language. Wha= t > >> you want is a block that takes a number and, after several iterations, > >> outputs its square root, am I right ? So you want to initialize some > >> internal signals or variables then step by step compute the square roo= t > >> and finally output the result. So you need some simple sequencer (a > >> counter will do), and a clock to make it run. > >> > >> Nicolas > > > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using= stages and it works perfectly. But I'll write it again with a process and = clock! thanks for your feedback ! >=20 > I'm curious about the course where you are learning VHDL. I remember=20 > about a million years ago when I was in college that I took a my first=20 > computer programming course. It was one part of six in a lab course in= =20 > chemistry. I believe it was just two weeks. I now know they were doing= =20 > their students a huge disservice by giving them such a limited amount of= =20 > training and then releasing them into the world to write their own=20 > programs. >=20 > I'm wondering if you are learning VHDL in a similar manner. VHDL is not= =20 > a terrible language to learn, but any HDL is a bit different from=20 > computer programming in that they are inherently parallel rather than=20 > sequential. Computer programming languages come naturally because they= =20 > are sequential reading the same as a recipe. HLDs are describing the=20 > functionality of hardware with it working in parallel. So there are=20 > different rules to it than you may be used to in software. >=20 > --=20 >=20 > Rick The program I'm following is called "master Nanotech". It's a bit unorthodo= x in the sense that it's mainly 1 year of applied physics / SC technology i= n master's level and 6 months in pure electronics. Now we are having two co= urses on VHDL one which is theoretical + small exercises like the one you s= aw above and then a lab which is split in 3 parts ( Full custom design in += layout in digital and analog electronics and semi-custom design in VHDL + = place and route in Synopsis. ) The problem is that the courses take for gra= nted some background in electronics and this is something lacking to ppl li= ke me that come from applied physics. So, even if you are comfortable with = programming wrapping your mind around parallel execution is somewhat alien = in the beginning. From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.66.190.229 with SMTP id gt5mr60362057pac.39.1416171375721; Sun, 16 Nov 2014 12:56:15 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr1230388qgz.1.1416171375670; Sun, 16 Nov 2014 12:56:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1493614igd.0!news-out.google.com!m4ni197qag.1!nntp.google.com!u7no2139455qaz.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 16 Nov 2014 12:56:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.70.30.51; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 195.70.30.51 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Subject: Re: problem with sll operator From: Marios Barlas Injection-Date: Sun, 16 Nov 2014 20:56:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7847 =CE=A4=CE=B7 =CE=9A=CF=85=CF=81=CE=B9=CE=B1=CE=BA=CE=AE, 16 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 9:00:12 =CE=BC.=CE=BC. UTC+1, = =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3=CF= =81=CE=B1=CF=88=CE=B5: > On 11/16/2014 4:44 AM, Marios Barlas wrote: > > =CE=A4=CE=B7 =CE=A3=CE=AC=CE=B2=CE=B2=CE=B1=CF=84=CE=BF, 15 =CE=9D=CE= =BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:50:10 =CE=BC.=CE=BC. = UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicolas Matringe = =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> Le 14/11/2014 23:40, Marios Barlas a =C3=A9crit : > >>> =CE=A4=CE=B7 =CE=A0=CE=B1=CF=81=CE=B1=CF=83=CE=BA=CE=B5=CF=85=CE=AE, = 14 =CE=9D=CE=BF=CE=B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2014 10:43:19 =CE= =BC.=CE=BC. UTC+1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Nicola= s Matringe =CE=AD=CE=B3=CF=81=CE=B1=CF=88=CE=B5: > >> [...] > >>>> You're from a computer programming background, aren't you ? > >>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing= a 2 years master's in nanotechnology the last semester of which is in micr= oelectronics. As a result us stupid physics people lack a good deal of back= ground that others have for granted. This is my first bit of code in VHDL. > >> > >> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a > >> program in C for example. It doesn't work like that. > >> > >> VHDL is a description language, not a programming language. It is like= a > >> schematics, except it is in text form. Concurrent expressions (i.e. th= at > >> are outside of processes) are independent blocks in your schematics. > >> This also means that their order in the code doesn't matter at all. > >> As Brian explained, concurrently assigning something to a signal is li= ke > >> connecting the output of a logic function to this signal. Concurrently > >> assigning several times to the same signal is connecting several outpu= ts > >> together. You usually don't want to do that (this causes your Xs in > >> simulation) > >> You seem to assume your code is executed from top to bottom. It is not= . > >> It is not even executed, since VHDL is not a programming language. Wha= t > >> you want is a block that takes a number and, after several iterations, > >> outputs its square root, am I right ? So you want to initialize some > >> internal signals or variables then step by step compute the square roo= t > >> and finally output the result. So you need some simple sequencer (a > >> counter will do), and a clock to make it run. > >> > >> Nicolas > > > > Thanks for the reply Nicolas. Finally I wrote my code in dataflow using= stages and it works perfectly. But I'll write it again with a process and = clock! thanks for your feedback ! >=20 > I'm curious about the course where you are learning VHDL. I remember=20 > about a million years ago when I was in college that I took a my first=20 > computer programming course. It was one part of six in a lab course in= =20 > chemistry. I believe it was just two weeks. I now know they were doing= =20 > their students a huge disservice by giving them such a limited amount of= =20 > training and then releasing them into the world to write their own=20 > programs. >=20 > I'm wondering if you are learning VHDL in a similar manner. VHDL is not= =20 > a terrible language to learn, but any HDL is a bit different from=20 > computer programming in that they are inherently parallel rather than=20 > sequential. Computer programming languages come naturally because they= =20 > are sequential reading the same as a recipe. HLDs are describing the=20 > functionality of hardware with it working in parallel. So there are=20 > different rules to it than you may be used to in software. >=20 > --=20 >=20 > Rick The program I'm following is called "master Nanotech". It's a bit unorthodo= x in the sense that it's mainly 1 year of applied physics / SC technology i= n master's level and 6 months in pure electronics. Now we are having two co= urses on VHDL one which is theoretical + small exercises like the one you s= aw above and then a lab which is split in 3 parts ( Full custom design in += layout in digital and analog electronics and semi-custom design in VHDL + = place and route in Synopsis. ) The problem is that the courses take for gra= nted some background in electronics and this is something lacking to ppl li= ke me that come from applied physics. So, even if you are comfortable with = programming wrapping your mind around parallel execution is somewhat alien = in the beginning. From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: problem with sll operator Date: Sun, 16 Nov 2014 20:53:42 -0500 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 17 Nov 2014 01:54:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="30258"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X1dhupNd3CupXkd7QTe1o" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> Cancel-Lock: sha1:3Yr1oG04waK8uV2j/1euQE6jOKs= Xref: mx02.eternal-september.org comp.lang.vhdl:7848 On 11/16/2014 3:56 PM, Marios Barlas wrote: > Τη ΚυÏιακή, 16 ÎοεμβÏίου 2014 9:00:12 μ.μ. UTC+1, ο χÏήστης rickman έγÏαψε: >> On 11/16/2014 4:44 AM, Marios Barlas wrote: >>> Τη Σάββατο, 15 ÎοεμβÏίου 2014 10:50:10 μ.μ. UTC+1, ο χÏήστης Nicolas Matringe έγÏαψε: >>>> Le 14/11/2014 23:40, Marios Barlas a écrit : >>>>> Τη ΠαÏασκευή, 14 ÎοεμβÏίου 2014 10:43:19 μ.μ. UTC+1, ο χÏήστης Nicolas Matringe έγÏαψε: >>>> [...] >>>>>> You're from a computer programming background, aren't you ? >>>>> Thanks for your answer. Sadly nope. I'm a physicist but I'm finishing a 2 years master's in nanotechnology the last semester of which is in microelectronics. As a result us stupid physics people lack a good deal of background that others have for granted. This is my first bit of code in VHDL. >>>> >>>> Sorry for my wrong guess, then. You wrote your VHDL like you'd write a >>>> program in C for example. It doesn't work like that. >>>> >>>> VHDL is a description language, not a programming language. It is like a >>>> schematics, except it is in text form. Concurrent expressions (i.e. that >>>> are outside of processes) are independent blocks in your schematics. >>>> This also means that their order in the code doesn't matter at all. >>>> As Brian explained, concurrently assigning something to a signal is like >>>> connecting the output of a logic function to this signal. Concurrently >>>> assigning several times to the same signal is connecting several outputs >>>> together. You usually don't want to do that (this causes your Xs in >>>> simulation) >>>> You seem to assume your code is executed from top to bottom. It is not.. >>>> It is not even executed, since VHDL is not a programming language. What >>>> you want is a block that takes a number and, after several iterations, >>>> outputs its square root, am I right ? So you want to initialize some >>>> internal signals or variables then step by step compute the square root >>>> and finally output the result. So you need some simple sequencer (a >>>> counter will do), and a clock to make it run. >>>> >>>> Nicolas >>> >>> Thanks for the reply Nicolas. Finally I wrote my code in dataflow using stages and it works perfectly. But I'll write it again with a process and clock! thanks for your feedback ! >> >> I'm curious about the course where you are learning VHDL. I remember >> about a million years ago when I was in college that I took a my first >> computer programming course. It was one part of six in a lab course in >> chemistry. I believe it was just two weeks. I now know they were doing >> their students a huge disservice by giving them such a limited amount of >> training and then releasing them into the world to write their own >> programs. >> >> I'm wondering if you are learning VHDL in a similar manner. VHDL is not >> a terrible language to learn, but any HDL is a bit different from >> computer programming in that they are inherently parallel rather than >> sequential. Computer programming languages come naturally because they >> are sequential reading the same as a recipe. HLDs are describing the >> functionality of hardware with it working in parallel. So there are >> different rules to it than you may be used to in software. >> >> -- >> >> Rick > > The program I'm following is called "master Nanotech". It's a bit unorthodox in the sense that it's mainly 1 year of applied physics / SC technology in master's level and 6 months in pure electronics. Now we are having two courses on VHDL one which is theoretical + small exercises like the one you saw above and then a lab which is split in 3 parts ( Full custom design in + layout in digital and analog electronics and semi-custom design in VHDL + place and route in Synopsis. ) The problem is that the courses take for granted some background in electronics and this is something lacking to ppl like me that come from applied physics. So, even if you are comfortable with programming wrapping your mind around parallel execution is somewhat alien in the beginning. When I learned VHDL I wasn't "comfortable" with the parallel nature of it. I had been programming in conventional languages for a number of years. However, I was familiar with logic design and once it was explained to me how the HDL mapped to logic it helped a lot. I always think of my design in terms of the hardware and then code that hardware in the HDL. In your theoretical course they should have taught you that a signal can not be assigned in more than one process without a resolution function. In theory std_logic is resolved, so it is not an error to have multiple drivers. But unless you are describing a tristated bus it is not synthesizable and tristated buses are not used very often. So they give you a warning. Try this with std_ulogic and you will get an error. -- Rick From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.236.1.37 with SMTP id 25mr58271181yhc.25.1416235050126; Mon, 17 Nov 2014 06:37:30 -0800 (PST) X-Received: by 10.140.34.14 with SMTP id k14mr28834qgk.8.1416235050111; Mon, 17 Nov 2014 06:37:30 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!u7no2320466qaz.1!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no485733qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 06:37:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> Subject: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Mon, 17 Nov 2014 14:37:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7849 So Im messing arround with VHDL - Ive created a package that contains a lin= ked list with a generic type. There is one issue I cant seem to work out in my head - is it possible crea= te a generic that defaults to the initial value of the generic type? At the= moment, when the there are no values in the list, the "get_item" function = will return the default value of the generic type - so I want to give the p= ackage a "null_value" generic, so it is easy to detect a null return (ie an= empty list). package ll_test_pkg is generic ( type data_t; =20 null_value : data_t :=3D ; ); =20 type link_list_t is protected =20 procedure add_item( i : data_t ); =20 impure function get_item return data_t; =20 end protected link_list_t; =20 end package ll_test_pkg; I could just force the user to explicitly specify the null_value when insta= ntiating the package, but it would be nicer (for me) if it defaulted to the= initial value of data_t. I could also make the get_item a procedure that outputs a data_t and an emp= ty_list boolean, but I wondered if the above was possible? From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.182.165.104 with SMTP id yx8mr65606501obb.15.1416237026044; Mon, 17 Nov 2014 07:10:26 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr9451qgd.27.1416237026015; Mon, 17 Nov 2014 07:10:26 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no477679igb.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no493046qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 07:10:24 -0800 (PST) In-Reply-To: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: KJ Injection-Date: Mon, 17 Nov 2014 15:10:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7850 On Monday, November 17, 2014 9:37:31 AM UTC-5, Tricky wrote: > I could just force the user to explicitly specify the null_value when instantiating the package, but it would be nicer (for me) if it defaulted to the initial value of data_t. > I'm not sure what you mean by the 'initial value of data_t', but inside your function, if you declare a variable that is eventually the one to be returned, that variable will get initialized to the leftmost value of the type. Example: function get_item return std_logic is variable RetVal: std_logic; -- RetVal will initialize to 'U' because it is the leftmost value in the definition of std_logic begin return(RetVal); end function get_item; Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.66.231.100 with SMTP id tf4mr56890088pac.48.1416241719993; Mon, 17 Nov 2014 08:28:39 -0800 (PST) X-Received: by 10.140.87.71 with SMTP id q65mr12158qgd.39.1416241719944; Mon, 17 Nov 2014 08:28:39 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no509222igb.0!news-out.google.com!m4ni198qag.1!nntp.google.com!w8no510272qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 08:28:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Mon, 17 Nov 2014 16:28:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7851 On Monday, 17 November 2014 15:10:28 UTC, KJ wrote: > On Monday, November 17, 2014 9:37:31 AM UTC-5, Tricky wrote: > > I could just force the user to explicitly specify the null_value when i= nstantiating the package, but it would be nicer (for me) if it defaulted to= the initial value of data_t. > >=20 >=20 > I'm not sure what you mean by the 'initial value of data_t', but inside y= our function, if you declare a variable that is eventually the one to be re= turned, that variable will get initialized to the leftmost value of the typ= e. >=20 > Example: >=20 > function get_item return std_logic is > variable RetVal: std_logic; -- RetVal will initialize to 'U' because i= t is the leftmost value in the definition of std_logic > begin > return(RetVal); > end function get_item; >=20 > Kevin Jennings Well yes, that is what I already have. But I want the possibility of the us= er specifying the null_value, which needs to be done on the generics. I can= leave it without a default value, but that forces the user to explicitly s= pecify the null_return, even if it is the initial value, for every package = instantiation. From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.52.228.4 with SMTP id se4mr70885361vdc.7.1416285958729; Mon, 17 Nov 2014 20:45:58 -0800 (PST) X-Received: by 10.182.121.161 with SMTP id ll1mr1436obb.27.1416285958290; Mon, 17 Nov 2014 20:45:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no136908qap.1!news-out.google.com!ks2ni22429igb.0!nntp.google.com!uq10no709066igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 20:45:58 -0800 (PST) In-Reply-To: <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Andy Injection-Date: Tue, 18 Nov 2014 04:45:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:7852 if data_t is always scalar, then use data_t'left as the initializer for null_value: null_value : data_t := data_t'left; If data_t can be scalar, array or record type, you may be outa luck... Andy From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.236.32.204 with SMTP id o52mr71944439yha.53.1416287700472; Mon, 17 Nov 2014 21:15:00 -0800 (PST) X-Received: by 10.182.28.10 with SMTP id x10mr70267obg.11.1416287700355; Mon, 17 Nov 2014 21:15:00 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no633733qac.0!news-out.google.com!c9ni14081igv.0!nntp.google.com!h15no2399917igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Nov 2014 21:14:59 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <54667774$0$2070$426a34cc@news.free.fr> <5467ca8f$0$2908$426a74cc@news.free.fr> <0f61ed91-d463-46bd-ab40-fef3aa8d741b@googlegroups.com> <4dcad4a2-6e44-435c-bb23-9f37f58addbf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <101864e2-b23f-467d-a84c-129811ea9313@googlegroups.com> Subject: Re: problem with sll operator From: Andy Injection-Date: Tue, 18 Nov 2014 05:15:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2820 X-Received-Body-CRC: 1456568327 Xref: mx02.eternal-september.org comp.lang.vhdl:7853 There's a very fine line between what a parallelizing compiler can do for S= W, and what a synthesis tool does for HDL. Both understand how to transform= sequential statements into parallel threads based on dependency. Once you understand the HDL behavior (not the template) that synthesizes to= registers vs combinatorial logic, then you are free to code your HDL at th= e behavioral level, on a clock-cycle by clock-cycle basis, and let the synt= hesis tool worry about the HW. If the synthesis results won't run with a fa= st enough clock, then (and only then) start thinking/coding at a lower leve= l. Often the "cure" for slow HW is to do something more often, not less oft= en. In SW we are taught not to perform a task if it is not needed. In HW, w= e learn to perform the task all the time, and only use the results if we ne= ed to. That takes less logic (and ns) than the decision whether to do the t= ask or not. In practice, this is nothing more than reducing dependency, whi= ch aids in parallelizing. I have always thought VHDL should be taught using variables first (use sign= als only for inter-process communication), so the student can fully underst= and what constitutes the behavior of a register, or storage of any kind (la= tches, ram, etc.) Once you fully understand that, you can reliably use stor= age, or avoid unwanted storage. Andy From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.67.14.232 with SMTP id fj8mr17480112pad.16.1416393601020; Wed, 19 Nov 2014 02:40:01 -0800 (PST) X-Received: by 10.140.27.214 with SMTP id 80mr11908qgx.23.1416393600862; Wed, 19 Nov 2014 02:40:00 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3522532igd.0!news-out.google.com!c9ni18079igv.0!nntp.google.com!w8no759316qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 02:40:00 -0800 (PST) In-Reply-To: <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.255.5.90; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 146.255.5.90 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Wed, 19 Nov 2014 10:40:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7854 On Tuesday, 18 November 2014 04:46:00 UTC, Andy wrote: > if data_t is always scalar, then use data_t'left as the initializer for null_value: > > null_value : data_t := data_t'left; > > If data_t can be scalar, array or record type, you may be outa luck... > > Andy Yup, I suspect outta luck - as the whole point is it could be any data type. You cant even use 'left as you dont know at that point what type of type it is. From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.182.58.105 with SMTP id p9mr53779170obq.25.1416396295176; Wed, 19 Nov 2014 03:24:55 -0800 (PST) X-Received: by 10.140.20.175 with SMTP id 44mr1525325qgj.4.1416396295029; Wed, 19 Nov 2014 03:24:55 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1406024igb.0!news-out.google.com!ks2ni24749igb.0!nntp.google.com!s7no275312qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:24:54 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.179.179.200; posting-account=OgqQbQoAAACwXkic-8LOzu6UOUzFugbN NNTP-Posting-Host: 128.179.179.200 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Subject: Speeding up computations in sequential algorithm From: Marios Barlas Injection-Date: Wed, 19 Nov 2014 11:24:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7855 Dear all, I'm trying to figure out how to speed up my computation on the following al= gorithm: Following my previous post, I wrote a code that implements an FSMD of 3 sta= tes calculating the square root of a number according to a clock. All is wo= rking fine, but i'lm trying to figure out if I can make it more efficient b= y making more calculations on the same clock cycle.=20 I have a process and in this a case statement with me FSMD states. Since I = can't use the for...generate command inside the process I tried to use some= buffer variables like this :=20 res_buff <=3D (res_c-(root_c + delta_c)) when (((root_c + = delta_c) <=3D res_c) ) else res_c; root_buff <=3D shift_right(root_c + shift_left(delta_c,1),1) = when ((root_c + delta_c) <=3D res_c) else=20 shift_right(root_c,1); delta_buff <=3D shift_right(delta_c,2); -- Parallelization=20 res_next <=3D (res_buff-(root_buff + delta_buff)) when (((ro= ot_buff + delta_buff) <=3D res_buff) ) else res_buff; root_next <=3D shift_right(root_buff + shift_left(delta_buff,= 1),1) when ((root_buff + delta_buff) <=3D res_buff) else=20 shift_right(root_buff,1); delta_next <=3D shift_right(delta_buff,2); but it seems to mess up my results. From the little I know I think this is = pipelining but I'm not sure how to infer this logic in VHDL. Anyone could g= ive me an idea? Thanks in Advance, Marios Barlas From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.66.142.106 with SMTP id rv10mr79268799pab.21.1416396752239; Wed, 19 Nov 2014 03:32:32 -0800 (PST) X-Received: by 10.140.41.11 with SMTP id y11mr16199qgy.16.1416396752075; Wed, 19 Nov 2014 03:32:32 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3548735igd.0!news-out.google.com!ks2ni24749igb.0!nntp.google.com!s7no277160qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:32:32 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Wed, 19 Nov 2014 11:32:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7856 Le samedi 30 ao=FBt 2014 18:08:34 UTC+2, Bart Fox a =E9crit=A0: > > pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd= ) as entry and generates a pdf schematic for each input file. > With a little fiddeling on MacOS X (with Macports) it run on my Mac too. >=20 > Nice work! >=20 > I did some changes to support signed/unsigned and std_ulogic as data type= s: >=20 > /pyVhdl2Sch$ git diff > diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py > index f9576ca..9933442 100644 > --- a/file_manager/vhdl_reader.py > +++ b/file_manager/vhdl_reader.py > @@ -99,10 +99,10 @@ class Vhdl_reader: > if wire_type =3D=3D "integer": > nb_wires =3D 32 > else: > - if wire_type =3D=3D "std_logic": > + if wire_type =3D=3D "std_logic" or wire_type =3D=3D "std_ulo= gic": > nb_wires =3D 1 > else: > - if wire_type =3D=3D "std_logic_vector": > + if wire_type =3D=3D "std_logic_vector" or wire_type =3D= =3D=20 > "std_ulogic_vector" or wire_type =3D=3D "signed" or wire_type =3D=3D "uns= igned": > bus_direction =3D real_words[5].lower() > bus_description =3D text.split("(")[1].split(")")[0= ] > if bus_direction =3D=3D "downto": > diff --git a/pyV2S.py b/pyV2S.py > index 8cccdf0..ced8fd6 100755 > --- a/pyV2S.py > +++ b/pyV2S.py > @@ -1,4 +1,4 @@ > -#!/usr/bin/python > +#!/usr/bin/env python > # -*- coding: utf-8 -*- >=20 >=20 >=20 > Maybe you can enhance the skript to use the data type instead the number= =20 > of wires for unknown data types? > I use a lot of vhdl-recods defined in packages in my projects, so the=20 > number of wires is difficult to determine. >=20 > regards, > Bart Hi, I inserted your interesting message as an issue in the github space. I think i solved it. Many Thanks, Laurent From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.182.234.108 with SMTP id ud12mr79436300obc.0.1416397241957; Wed, 19 Nov 2014 03:40:41 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr1550661qgz.1.1416397241813; Wed, 19 Nov 2014 03:40:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1410662igb.0!news-out.google.com!c9ni18079igv.0!nntp.google.com!w8no773281qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 03:40:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.182.238.172; posting-account=DanITAoAAADZRQ3INvxcdLr4w4QwYv0X NNTP-Posting-Host: 88.182.238.172 References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94d990e4-54d5-408d-bbea-a97856766f4a@googlegroups.com> Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch From: Laurent Cabaret Injection-Date: Wed, 19 Nov 2014 11:40:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7857 Hi,=20 I inserted your interesting message as an issue in the github space. here is the current state of his resolution : - Signals are now allowed in port definition - Still working on resolution functions! - cairocffi embed all fonts (even standard ones) so Jura seems to be smalle= r than times or helvetica. - Not sure to understand the kicad part - pyVhdl2Sch now support pdf/svg/ps/png output Many Thanks,=20 Laurent=20 =20 Le samedi 30 ao=FBt 2014 22:15:52 UTC+2, Dio Gratia a =E9crit=A0: > On Thursday, August 28, 2014 7:53:10 PM UTC+12, Laurent Cabaret wrote: >=20 > > pyVhdl2Sch is a documentation generator tool.=20 > >=20 > > Feel free to criticize/cheers/participate/... >=20 > I noticed your tool doesn't accept the optional keyword signal in an inte= rface signal declaration on the port. >=20 > interface_signal_declaration ::=3D > [ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ = :=3D static_expression ] >=20 > "Ports of any mode are also signals." As you can see the mode is optional= and defaults to mode in. >=20 > Also a subtype indication can be more than a name and an index range: >=20 > subtype_indication ::=3D > [ resolution_indication ] type_mark [ constraint ] >=20 > resolution_indication ::=3D > resolution_function_name | ( element_resolution ) >=20 > element_resolution ::=3D array_element_resolution | record_resolution=20 >=20 > array_element_resolution ::=3D resolution_indication >=20 > record_resolution ::=3D record_element_resolution { , record_element_reso= lution }=20 >=20 > record_element_resolution ::=3D record_element_simple_name resolution_ind= ication >=20 > (These are from IEEE Std 1076-2008). A port signal can be a record, too. >=20 > A resolution indication can appear wherever there is a driver. This is v= alid VHDL code: >=20 > library ieee; > use ieee.std_logic_1164.all; >=20 > package a_pkg is >=20 > function x_res (to_resolve: std_logic_vector) return std_ulogic; >=20 > end a_pkg; >=20 > package body a_pkg is >=20 > function x_res (to_resolve: std_logic_vector) return std_ulogic is > variable r: std_ulogic; > begin > r :=3D 'Z'; > for i in to_resolve'range loop > r :=3D r or to_resolve(i); > end loop; > return r; > end function x_res; >=20 > end a_pkg; >=20 > library ieee; > use ieee.std_logic_1164.all; > use work.a_pkg.all; >=20 > entity foo is > port ( > signal a: in std_logic; > signal b: in std_logic; > signal c: in std_logic; > signal p: out x_res std_logic > ); > end entity; >=20 > architecture fum of foo is > =20 > begin=20 > p <=3D a; > p <=3D b; > p <=3D c; > end architecture; >=20 > As you can see there's a resolution function declared and because it's no= t an array type or a record type there are no parentheses for an array elem= ent resolution function. A record can have a resolution function for each = record element, while there's only one for an array type. >=20 > I've written schematic symbol generators several times over the years wha= t your program does isn't a surprise, the geometry familiar. =20 >=20 > That you discard the subtype indication (index range) limits the use to b= lock diagrams (for documentation). There's at least one PDF based schematic= package out there (Kicad). It'd likely require your own PDF code generati= on to make symbols for it. >=20 > A three signal port entity generated a 10KB PDF file, you're own PDF code= generation could possibly reduce that should you be able to live with a st= andard embedded font. The issue here is eventually swamping a word process= or by including embedded PDF files accumulating in size. Open Office/Libre = Office can slow down with a relatively few large image files, It's the redr= aw times. >=20 > We used to do a lot of PostScript code for this kind of stuff back in the= day, PDF can be on par and schematic symbols are about as hard as printing= overlays on bank checks. You could do PostScript and rely on conversion t= o PDF. From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.52.253.102 with SMTP id zz6mr39485285vdc.1.1416459026278; Wed, 19 Nov 2014 20:50:26 -0800 (PST) X-Received: by 10.182.213.36 with SMTP id np4mr242925obc.4.1416459026085; Wed, 19 Nov 2014 20:50:26 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no518239qap.1!news-out.google.com!w7ni66qay.0!nntp.google.com!h15no4069690igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 19 Nov 2014 20:50:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Andy Injection-Date: Thu, 20 Nov 2014 04:50:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:7858 You could provide a procedure to set the null value. Until/unless the user calls the procedure, use the default value of data_t. You could also implement a lockout to prevent using the set_null_value() procedure after add_item() has been called. Andy From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.182.234.108 with SMTP id ud12mr85262269obc.0.1416483224817; Thu, 20 Nov 2014 03:33:44 -0800 (PST) X-Received: by 10.140.36.231 with SMTP id p94mr7637qgp.13.1416483224785; Thu, 20 Nov 2014 03:33:44 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4272028igd.0!news-out.google.com!w7ni49qay.0!nntp.google.com!s7no588938qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Nov 2014 03:33:44 -0800 (PST) In-Reply-To: <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Thu, 20 Nov 2014 11:33:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7859 On Thursday, 20 November 2014 04:50:28 UTC, Andy wrote: > You could provide a procedure to set the null value. Until/unless the user calls the procedure, use the default value of data_t. You could also implement a lockout to prevent using the set_null_value() procedure after add_item() has been called. > > Andy This is all a bit proof of concept anyway at the moment - but these are good ideas. Linked lists have often featured in my testbenches, so having a linked list in a package would mean I wouldnt have to essentially do a copy/paste into every new testbench that uses different storage types. Looking forward to it :) From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.66.161.40 with SMTP id xp8mr579385pab.33.1416483596162; Thu, 20 Nov 2014 03:39:56 -0800 (PST) X-Received: by 10.140.21.49 with SMTP id 46mr3210qgk.30.1416483596108; Thu, 20 Nov 2014 03:39:56 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!uq10no1860493igb.0!news-out.google.com!w7ni50qay.0!nntp.google.com!w8no1083940qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 20 Nov 2014 03:39:55 -0800 (PST) In-Reply-To: <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm NNTP-Posting-Host: 78.154.109.115 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Tricky Injection-Date: Thu, 20 Nov 2014 11:39:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7860 One thing that is going to infuriate me though is the protected type limitations: Cannot have arrays of protected types. Cannot have function/procedure arguments that are access types (or records that contain access types) in protected type member functions. So I may have to move away from protected types to define the linked list in the package, and just store the linked list in the package itself, as you can now define variables in a package if the package is local to a process/function/procedure. From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Speeding up computations in sequential algorithm Date: Thu, 20 Nov 2014 13:21:30 +0000 (UTC) Organization: A noiseless patient Spider Lines: 36 Message-ID: References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 20 Nov 2014 13:21:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="11272"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1963e7t3xkFL4WBauqFp3kUf+DqkQMZ1Ek=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vzTBY22E0W9gK3pykHN3gFCZ7a8= Xref: mx02.eternal-september.org comp.lang.vhdl:7861 On Wed, 19 Nov 2014 03:24:54 -0800, Marios Barlas wrote: > Dear all, > > I'm trying to figure out how to speed up my computation on the following > algorithm: ... > I have a process and in this a case statement with me FSMD states. Since > I can't use the for...generate command inside the process I tried to use > some buffer variables like this : ... > but it seems to mess up my results. From the little I know I think this > is pipelining but I'm not sure how to infer this logic in VHDL. Anyone > could give me an idea? The first stage is to have a clear idea what you want to happen in each cycle of the pipeline - I find it helps to name signals appropriately and to organise the pipelined process into its logical stages. Here's a simple example of a badly pipelined design (WARNING : I am not recommending this practice!) http://vhdlguru.blogspot.com/2011/01/what-is-pipelining-explanation- with.html and my approach to cleaning it up, in response to a StackExchange question on this topic. http://stackoverflow.com/questions/14765205/how-can-i-speed-up-my-math- operations-in-vhdl/14777458#14777458 These may help get you started - Brian From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Speeding up computations in sequential algorithm Date: Thu, 20 Nov 2014 11:30:43 -0500 Organization: A noiseless patient Spider Lines: 95 Message-ID: References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 20 Nov 2014 16:31:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="8f56c4083975a6c8d296f9d83087445c"; logging-data="27183"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+BMSicG3uG0YbD4XDZJBLR" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> Cancel-Lock: sha1:qDgcGE3CaP8SAUufkZIZTF88QP0= Xref: mx02.eternal-september.org comp.lang.vhdl:7862 On 11/19/2014 6:24 AM, Marios Barlas wrote: > Dear all, > > I'm trying to figure out how to speed up my computation on the following algorithm: > > Following my previous post, I wrote a code that implements an FSMD of 3 states calculating the square root of a number according to a clock. All is working fine, but i'lm trying to figure out if I can make it more efficient by making more calculations on the same clock cycle. > > I have a process and in this a case statement with me FSMD states. Since I can't use the for...generate command inside the process I tried to use some buffer variables like this : > > > > res_buff <= (res_c-(root_c + delta_c)) when (((root_c + delta_c) <= res_c) ) else > res_c; > root_buff <= shift_right(root_c + shift_left(delta_c,1),1) when ((root_c + delta_c) <= res_c) else > shift_right(root_c,1); > delta_buff <= shift_right(delta_c,2); > -- Parallelization > res_next <= (res_buff-(root_buff + delta_buff)) when (((root_buff + delta_buff) <= res_buff) ) else > res_buff; > root_next <= shift_right(root_buff + shift_left(delta_buff,1),1) when ((root_buff + delta_buff) <= res_buff) else > shift_right(root_buff,1); > delta_next <= shift_right(delta_buff,2); > > but it seems to mess up my results. From the little I know I think this is pipelining but I'm not sure how to infer this logic in VHDL. Anyone could give me an idea? > > Thanks in Advance, > Marios Barlas To start with, I don't know what an FSMD is. Is this like an FSM (Finite State Machine)? I can't comment on the correctness of your code because I don't know what it is supposed to do. You are only showing part of your work. Should we assume this is inside a clocked process? I am guessing yes since you talk about pipelining and clocks. In that case, each of the signal assignment statements above will generate registers. The assignment to res_buff looks like it only includes signals from outside the process. The assignment to root_buff looks the same so this will run in parallel without depending on the assignment to res_buff. The assignment to delta_buff is the same. So all three of these are running at the same point in the pipeline. The assignment to res_next depends on all three of the above, so it would be in the second stage of the pipeline. Same for root_next and delta_next. So all three of these signals are in the second stage of the pipeline and will produce results with the same cycle timing. This is a two stage pipeline producing a result every clock cycle with a two clock cycle latency. There are some things you can do to improve the efficiency of this algorithm. The expression root_c + delta_c is used more than once, but will likely produce multiple adders coded this way. This sum is subtracted from res_c as well as compared to res_c. This can share the same logic if coded to do so. This is where variables can be used. Variables in a clocked process will not generate registers if they are assigned before they are used. So you could do this... sum_c := root_c + delta_c; diff_c := res_c - sum_c; res_buff <= res_c when diff_c < 0 else diff_c; This provides the tools a better chance at using just two adders (or subtractor - same thing) and using the carry out from the second one to control the mux selecting the input to res_buff. In addition the same variables can be used to control the assignment for root_buff since it uses the same comparison, again saving logic and likely improving the speed at least a little. If you want to speed this up further, you can pipeline the above two variable assignments as signal assignments giving two more stages to your pipeline. You will need to delay the use of root_c and delta_c in the assignment to root_buff to keep them at the same delay. Likewise for delta_buff so all three x_buff results are ready at the same time. You can use all the same methods to improve the assignments to res_next, root_next and delta_next. If you are not familiar with variable assignments, they work like variables in a regular C program completing their assignments as they are executed while signal assignments are not completed until the process stops. Using a variable in a clocked process gets you the current value while using a signal inside the process gets you the old value no matter what. I hope this helps some. -- Rick From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch Date: 21 Nov 2014 11:12:21 GMT Lines: 38 Message-ID: References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> X-Trace: individual.net D9Of1pxqo5+ZNUYj2YzEpgqG00uVK6P6Z7k2Z3lmQQYqBtH4+g X-Orig-Path: not-for-mail Cancel-Lock: sha1:vwfo4MClRc5j3HZkmlx3sOvNGmY= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7863 Hi Laurent, Laurent Cabaret wrote: [] > pyVhdl2Sch is a documentation generator tool. It takes VHDL files > (.vhd) as entry and generates a pdf schematic for each input file. tried and got this: Warning - a special port type is used or your entity is not well formated. by default I used your type name as a wire name Here is the official supported type list : - integer - natural - positive - signed - std_logic - std_logic_vector - std_ulogic - unsigned Traceback (most recent call last): File "./pyV2S.py", line 30, in reader = Vhdl_reader(filename, options) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 31, in __init__ self.parse_entity_part() File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 141, in parse_entity_part self.extract_wire(raw_line) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 166, in extract_wire wire_type = vhdl_wire_words[3].lower() IndexError: list index out of range The vhdl synthesizes correctly and all ports are std_logic[_vector]. I'm actually very motivated for introducing these tools for documentation purposes, especially considering the possibility to include it in a LaTeX document. Al From newsfish@newsfish Tue Dec 29 16:43:36 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: [VHDL Documentation tool] First release of pyVhdl2Sch Date: 21 Nov 2014 11:14:57 GMT Lines: 22 Message-ID: References: <0f09d759-6a9a-4a80-985e-f2295938a843@googlegroups.com> X-Trace: individual.net /BsLZiNLxQhuSUnCdmOUxwOlvCXUL2aUoBEIb5mvOs0P14yhTo X-Orig-Path: not-for-mail Cancel-Lock: sha1:uVuVfHO/yF6dEDigFQZ6DNGEz+4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7864 Hi Laurent, Laurent Cabaret wrote: [] > pyVhdl2Sch is a documentation generator tool. It takes VHDL files > (.vhd) as entry and generates a pdf schematic for each input file. Additionally this is what I get on the example provided in the repo: debian@debian:pyVhdl2Sch-master$ ./pyV2S.py tb_None.vhd Traceback (most recent call last): File "./pyV2S.py", line 30, in reader = Vhdl_reader(filename, options) File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 30, in __init__ self.parse_vhdl_file() File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 118, in parse_vhdl_file if real_words[locate_end + 1] == self.entity.name: IndexError: list index out of range Am I missing something? Al From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.236.26.200 with SMTP id c48mr6703774yha.46.1416612388520; Fri, 21 Nov 2014 15:26:28 -0800 (PST) X-Received: by 10.140.94.150 with SMTP id g22mr134243qge.0.1416612388496; Fri, 21 Nov 2014 15:26:28 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no1470194qac.0!news-out.google.com!w7ni319qay.0!nntp.google.com!s7no976089qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Nov 2014 15:26:28 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.56.197; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.56.197 References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> Subject: Re: Speeding up computations in sequential algorithm From: Nikolaos Kavvadias Injection-Date: Fri, 21 Nov 2014 23:26:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 82 Xref: mx02.eternal-september.org comp.lang.vhdl:7865 Dear Marios and rickman, > > @rickman: An FSMD (Finite-State Machine with Datapath) is a microarchitectural paradi= gm for implementing non-programmable/hardwired processors with their contro= l unit and datapath combined/merged. Essentially, the datapath actions are = embedded within the actual next state and output logic decoder of your RTL = FSM description (if you view it this way). I have a published work on FSMDs: http://cdn.intechweb.org/pdfs/29207.pdf w= hile my high-level synthesis tool, HercuLeS ( http://www.nkavvadias.com/her= cules/ ) produces such FSMDs. A manual for HercuLeS is here: http://www.nka= vvadias.com/hercules-reference-manual/hercules-refman.pdf. I have based my version of FSMDs to Prof. Gajski's and Pong P. Chu's work, = mostly on some of their books and published papers. I had rented a couple o= f Gajski's books from the local library [I was a lecturer at the time, now = I ain't but still can drive 2km to closest higher education library and ren= t various works] and have actually bought two of P.P. Chu's works; the RTL = Hardware Design using VHDL book is brilliant. Further, Gajski's work on Spe= cC and the classic TRs (technical reports) from his group were at some poin= t night (by the bed) and day (by the desk) readings... I believe Vivado HLS (aka AutoESL/xPilot) and the others do the same thing,= with one key difference on how the actual RTL FSMD code is presented. Thei= r datapath code is implemented with concurrent assignments and there are lo= ts of control and status signals going in and out of the next state logic d= ecoder. On the contrary I prefer datapath actions embedded within state dec= oding; produces a little slower and fatter (sic) hardware overall, but the = user's intention in the RTL is much more clear and it is to grasp and follo= w. > > @Marios: > > I'm trying to figure out how to speed up my computation on the followin= g algorithm: I know this might not be an scientifically appropriate proposal from my sid= e, but do you have a plain software description of the algorithm? E.g. when= I was enumerating topological sorts I started from Knuth's pseudocode, the= n coded an ANSI/ISO C version, then modified it for HLS with HercuLeS, and = voila: a meaningless hardware version for the code as well :) > > Following my previous post, I wrote a code that implements an FSMD of 3= =20 > > states calculating the square root of a number according to a clock. Al= l is=20 > > working fine, but i'm trying to figure out if I can make it more effici= ent by > > making more calculations on the same clock cycle. Having an FSMD with only 3 states for a square-rooting algorithm seems coun= ter-intuitive, unless one of the states is a multi-cycle state or a "multi-= state". Or you are doing a lot of operation chaining within a single state. Try to follow basic principles from Pong P. Chu: 1) Have a _reg and _next version for each register as declared signals in V= HDL code. 2) In each state, read the _reg's and assign the _next's. 3) Donnot reassign the same _next version of a register within a single FSM= D state. 4) You can totally avoid variables from your code. Not all tools provide eq= ually mature support for synthesizing code with variables. 5) Operation chaining is possible but requires that you write _next version= s and read them in the same state. Then these are plain wires and donnot im= plement registers. Again, you can peruse the same _next version more than o= nce in the same state. I had developed an ingenious technique for automatically modifying a VHDL F= SMD code for adding controlled operation chaining; I was about to patent it= but spared on the money of course. My technique just uses a lexer and to r= ead more about it, see chapter III.E of this work: http://www.nkavvadias.co= m/publications/kavvadias_asap12_cr.pdf There are also newer works on HercuLeS like: http://www.nkavvadias.com/publ= ications/hercules-pci13.pdf and a journal paper accepted for publication. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:36 2015 X-Received: by 10.236.16.194 with SMTP id h42mr9263541yhh.13.1416657533780; Sat, 22 Nov 2014 03:58:53 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr177737qgd.3.1416657533764; Sat, 22 Nov 2014 03:58:53 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no1554244qac.0!news-out.google.com!w7ni50qay.0!nntp.google.com!w8no1554240qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 22 Nov 2014 03:58:53 -0800 (PST) In-Reply-To: <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.56.197; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.56.197 References: <8e2a0f8b-38f9-41a3-b966-59f57996261c@googlegroups.com> <8610158a-7e65-43a0-b1a3-601e5da566a1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7633f1d6-72fe-4d9b-aafd-a2a96f3e3dc5@googlegroups.com> Subject: Re: Speeding up computations in sequential algorithm From: Nikolaos Kavvadias Injection-Date: Sat, 22 Nov 2014 11:58:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: mx02.eternal-september.org comp.lang.vhdl:7866 > 5) Operation chaining is possible but requires that you write _next versions and read them in the same state. Then these are plain wires and donnot implement registers. Again, you can peruse the same _next version more than once in the same state. Of course I meant that you cannot peruse **for writing** the same _next version more than once in the same state! I just needed to clarify this. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.42.194.204 with SMTP id dz12mr39012883icb.16.1416954209790; Tue, 25 Nov 2014 14:23:29 -0800 (PST) X-Received: by 10.50.114.134 with SMTP id jg6mr298532igb.13.1416954208932; Tue, 25 Nov 2014 14:23:28 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7681515igd.0!news-out.google.com!c9ni23798igv.0!nntp.google.com!h15no422878igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 25 Nov 2014 14:23:28 -0800 (PST) In-Reply-To: <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <347c8b62-452d-4aab-a732-ef42ba864e5a@googlegroups.com> <8c7f365e-4f4f-423e-8afc-07893b9762f7@googlegroups.com> <96d99358-f87b-43ec-96a4-95a318004e3a@googlegroups.com> <1adbd383-9ed3-4d03-b9b4-e9c7bbfec7be@googlegroups.com> <618a2d08-80c0-4b77-8068-db37295a51d8@googlegroups.com> <9d17a65e-ba88-4d0e-a69b-b4a21cb56f8e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43261795-7850-4358-bf20-e947dfa8d2d1@googlegroups.com> Subject: Re: VHDL 2008 : How to set a generic default to be the initial value of the generic type? From: Jim Lewis Injection-Date: Tue, 25 Nov 2014 22:23:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7867 In my generic linked list/scoreboard, pop when the list is empty is an assert failure. OTOH, if you are looking to return type'left, why not just declare a local variable: impure function pop return data_t is variable result : data_t ; -- defaults to left most value of type begin if not empty then result := top.value ; -- get -- remove top cell from list return result ; else report "FIFO_PKG: POP called when list empty" severity failure ; return result ; -- type'left by default end if ; end function pop ; I have the following already on the VHDL-201X list. Do you have any more? Cannot have arrays of protected types. Cannot have function/procedure arguments that are access types (or records that contain access types) in protected type member functions. Drop me a line as I have a package that you may like. From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? Newsgroups: comp.lang.vhdl User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 Nov 2014 11:21:15 GMT Lines: 66 Message-ID: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 2c4443a3.news.astraweb.com X-Trace: DXC=YlQQ`H0Snca1m]JSMD?cjjL?0kYOcDh@jSBc;\8ijUdkYRP3^H]h_dfAgmHV5@Nh Xref: mx02.eternal-september.org comp.lang.vhdl:7868 Hi, I'm trying to do something equivalent to the following: generic g : boolean; ... constant c : some_type := expression1 when g else expression2; This is something I want to do a lot in both synthesisable and non- synthesisable designs. Usually I end up writing an 8 line function to do something that I ought be able to do in a single line. For example, in Verilog 2001 I would write this as localparam c = g ? expression1 : expression2; (Questions below) I found this in the '08 standard: [§ 6.4.2.2] constant_declaration ::= constant identifier_list : subtype_indication [ := expression ] ; [§ 9.1] expression ::= condition_operator primary | logical_expression [§ 9.1] primary ::= name | literal | aggregate | function_call | qualified_expression | type_conversion | allocator | ( expression ) Unfortunately, "expression" doesn't ever lead to "conditional_expressions". [§ 10.5.3] conditional_expressions ::= expression when condition { else expression when condition } [ else expression ] Questions: Q1: Am I reading the standard correctly and we can't (in 2008) use conditional expressions in constant initialisers? Q2: Is there some simple and effective way of doing what I'm trying to do? Q3: If not, how do we go about fixing this? Thanks, Allan From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Mathias Weierganz Newsgroups: comp.lang.vhdl Subject: Xilinx ISE14: Problems with Sythesize Date: Wed, 26 Nov 2014 13:20:51 +0100 Organization: albasani.net Lines: 24 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.albasani.net xzta6jGovNTUmf+T8xqXsu/dRd9dkLx6EPI4Usf1/EqFNZCILgUrTPU4u/Kv7unWR5/FgC0qUQGJDFpQF82CR7UgwwgPT+xohv5wBr2+TbzJZf9tWCcY1zhb/CBYY0+v NNTP-Posting-Date: Wed, 26 Nov 2014 12:20:51 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="DOcd1ftLa4HeTD0s/qDe53ApTLP0dRANsJXWORpGYdaxB1QDxV3v7S96/BbZ/LWRX99OklXo2jmdbkDfxNfJdRn1kNz+7fj60qDXvg5e+IIzzvW51OFpmlCEPHuNeNUP"; mail-complaints-to="abuse@albasani.net" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 Cancel-Lock: sha1:7Tk6VV8xvCz3+/ozxvuyVga/1ZE= Xref: mx02.eternal-september.org comp.lang.vhdl:7869 I am using Xilinx ISE14.7 I have a project for Spartan6 which I can compile without problems. Now I try to compile it for a Virtex 5 and I run into problems already at the synthesis level. The first problem was easy to fix: The synthesis don't like the concatenation operator "&" in the instantiation bloc. But is there an easy solution for my second problem? The synthesis don't want to see this construct: databus_i => (others => '0'), and give me this error message: ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in unconstrained array aggregate. Let me say it again: I can compile the same project for Spartan-6 without any problems. Any hints? Thanks Mathias From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.182.111.164 with SMTP id ij4mr29995344obb.26.1417006272388; Wed, 26 Nov 2014 04:51:12 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr586843qgd.3.1417006272352; Wed, 26 Nov 2014 04:51:12 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7965634igd.0!news-out.google.com!m4ni578qag.1!nntp.google.com!s7no1994171qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 04:51:12 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: KJ Injection-Date: Wed, 26 Nov 2014 12:51:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7870 On Wednesday, November 26, 2014 6:21:16 AM UTC-5, Allan Herriman wrote: > Hi, >=20 > I'm trying to do something equivalent to the following: >=20 > generic g : boolean; > ... > constant c : some_type :=3D expression1 when g else expression2; >=20 >=20 > Q3: If not, how do we go about fixing this? >=20 >=20 Write a function that takes as input the condition and the two expressions = and returns the result. I called mine 'sel' (since 'select' is already a r= eserved keyword). Overload it for all of the basic types that you would us= e for an expression as well as for std_ulogic and boolean for the condition= . Works just fine for any version VHDL. function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer; function sel(Cond: BOOLEAN; If_True, If_False: real) return real; function sel(Cond: BOOLEAN; If_True, If_False: time) return time; function sel(Cond: BOOLEAN; If_True, If_False: BOOLEAN) return BOOLEAN; function sel(Cond: BOOLEAN; If_True, If_False: arr_integer) return arr_= integer; function sel(Cond: BOOLEAN; If_True, If_False: arr_natural) return arr_= natural; function sel(Cond: BOOLEAN; If_True, If_False: arr_real) return arr_rea= l; function sel(Cond: BOOLEAN; If_True, If_False: arr_time) return arr_tim= e; function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic) return std_u= logic; function sel(Cond: BOOLEAN; If_True, If_False: std_ulogic_vector) retur= n std_ulogic_vector; function sel(Cond: BOOLEAN; If_True, If_False: std_logic_vector) return= std_logic_vector; function sel(Cond: BOOLEAN; If_True, If_False: signed) return signed; function sel(Cond: BOOLEAN; If_True, If_False: unsigned) return unsigne= d; function sel(Cond: BOOLEAN; If_True, If_False: STRING) return STRING; function sel(Cond: BOOLEAN; If_True, If_False: Character) return Charac= ter; Then the usage is simply: constant c : some_type :=3D sel(g, expression1, expression2); Or for the more wordy constant c : some_type :=3D sel(Cond =3D> g, If_True =3D> expression1, If_F= alse =3D> expression2); Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.66.219.135 with SMTP id po7mr33035036pac.9.1417025296168; Wed, 26 Nov 2014 10:08:16 -0800 (PST) X-Received: by 10.182.216.202 with SMTP id os10mr25132obc.8.1417025295978; Wed, 26 Nov 2014 10:08:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8115957igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no704959igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:08:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2ecf2fab-174a-4654-970b-8779c82c17a5@googlegroups.com> Subject: Re: Xilinx ISE14: Problems with Sythesize From: Andy Injection-Date: Wed, 26 Nov 2014 18:08:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1516 X-Received-Body-CRC: 3595982537 Xref: mx02.eternal-september.org comp.lang.vhdl:7871 There are a lot of things that are non-compliant VHDL that are accepted by synthesis tools. And a lot of compliant VHDL is not accepted by synthesis tools either. Have you tried a simulator? They often have better error messages. Is the port formal of an unconstrained type (i.e. takes its size from that of the associated actual)? If so, there is no pre-defined port-width from which "others" can be determined, and vise versa. Andy From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.66.248.8 with SMTP id yi8mr32184430pac.26.1417025508772; Wed, 26 Nov 2014 10:11:48 -0800 (PST) X-Received: by 10.182.233.134 with SMTP id tw6mr166296obc.2.1417025508614; Wed, 26 Nov 2014 10:11:48 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8117709igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no706268igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:11:48 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.42 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <08e8e804-f755-4665-b4d0-3a32624466ca@googlegroups.com> Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: Andy Injection-Date: Wed, 26 Nov 2014 18:11:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1346 X-Received-Body-CRC: 1298250791 Xref: mx02.eternal-september.org comp.lang.vhdl:7872 There is no such thing in vhdl as "conditional expressions", only "conditional assignments". Since your statement is not an assignment statement, but a declaration statement, your code is non-compliant. Andy From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.70.19.201 with SMTP id h9mr31743341pde.3.1417027832824; Wed, 26 Nov 2014 10:50:32 -0800 (PST) X-Received: by 10.50.61.135 with SMTP id p7mr377293igr.9.1417027832719; Wed, 26 Nov 2014 10:50:32 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no722277igd.0!news-out.google.com!d20ni740igz.0!nntp.google.com!h15no8139262igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:50:32 -0800 (PST) In-Reply-To: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <5475b7aa$0$11091$c3e8da3@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008: Can I use conditional_expressions as an initialiser for a constant? From: Jim Lewis Injection-Date: Wed, 26 Nov 2014 18:50:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7873 Hi Allan, I worked on it for the VHDL-2008 phase. It is an interesting problem as to= how to add it as an expression given that signals assignments already have= existing conditional_waveforms. Also one of the members wanted to change = the else to a "," (in the name of conciseness) in the conditional assignmen= t. In the end that caused ambiguity which killed it. =20 During the LRM editing phase, I got busy with other items (had to work so I= could eat), and did not notice that the force statement required a separat= e BNF production that defined conditional_expression. Wish I had noticed a= s given that it was done there, it is very obvious to support that in at le= ast an initialization scenario as you asked for. =20 It is on the list again: =20 http://www.eda.org/twiki/bin/view.cgi/P1076/ConditionalExpressions I added a fail safe so that if the main proposal fails that we at least add= it to initialize constants, signals, and variables. Which seems to be a t= rivial addition at this point. =20 We are at the point where we are ranking proposals and welcome input from m= embers of the VHDL community - no one want to add and/or implement features= that are not wanted by the general community. Jim From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.182.65.232 with SMTP id a8mr33253210obt.5.1417028142084; Wed, 26 Nov 2014 10:55:42 -0800 (PST) X-Received: by 10.50.134.135 with SMTP id pk7mr375666igb.6.1417028141915; Wed, 26 Nov 2014 10:55:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no8141732igd.0!news-out.google.com!d20ni740igz.0!nntp.google.com!h15no8141725igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 26 Nov 2014 10:55:41 -0800 (PST) In-Reply-To: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <2326e3ef-907a-41d5-881d-756ced5009dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81079b61-a7b4-416b-a5f5-853d957fe904@googlegroups.com> Subject: Re: Floating point in VHDL From: Jim Lewis Injection-Date: Wed, 26 Nov 2014 18:55:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1627 X-Received-Body-CRC: 1768142744 Xref: mx02.eternal-september.org comp.lang.vhdl:7874 On Thursday, November 6, 2014 6:42:18 PM UTC-8, Dai Tran Van wrote: > Hi everyone. > I working with foating point, and i have problem with multipile maxtrix, vetor in foating.. > this i's my project to go out shool on time. help me. What have you done so far? VHDL-2008 added packages for floating point math. There is a tutorial on this part on my website at: http://www.synthworks.com/papers/index.htm If you look around some, you may find some packages that use this package that do what you want - they exist. From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Wed, 26 Nov 2014 14:23:11 -0500 Organization: Alacron, Inc. Lines: 38 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 26 Nov 2014 19:23:26 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="31024"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1958AGA5CNxhl9psk2gPwsGr2Gn3M0ha9g=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:BGx88lku/Vw796tuy/fZaC6TRo0= Xref: mx02.eternal-september.org comp.lang.vhdl:7875 Mathias Weierganz wrote: > I am using Xilinx ISE14.7 > I have a project for Spartan6 which I can compile without problems. Now > I try to compile it for a Virtex 5 and I run into problems already at > the synthesis level. > > The first problem was easy to fix: The synthesis don't like the > concatenation operator "&" in the instantiation bloc. > > But is there an easy solution for my second problem? The synthesis > don't want to see this construct: > databus_i => (others => '0'), > and give me this error message: > ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in > unconstrained array aggregate. > > Let me say it again: I can compile the same project for Spartan-6 > without any problems. > > > Any hints? > > Thanks > > Mathias Xilinx tools use a different front-end to synthesize 6-series and newer FPGA's by default. If your code works with the new front- end, you can try to use it on older parts. In the XST command line add the option: -use_new_parser yes If you use the Navigator GUI, you can apply this option under "Other XST Command Line Options" in the synthesis properties. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 26 Nov 2014 16:12:59 -0600 From: mazharchattha88 Subject: Re: VHDL code for Turbo Codes Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 9490c5c1-517d-4461-a749-5b3102ed76bc References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> Message-ID: Date: Wed, 26 Nov 2014 16:12:59 -0600 Lines: 6 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ssFfz3o5rhCRbopQZRCiHlc269IHZlgRbr0OMX9GEOssgbzgdyzpTD47unp0ahTqXsvXrfL69VnC7E1!FJndndIWObo1ZhNpGIaKpGCS4dO/PWHXE1xZGxwO8mUGy4qsQEAYewtjDK0f8zOiNoan2wT0wUbh!WKc= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1072 Xref: mx02.eternal-september.org comp.lang.vhdl:7876 hi i cant open this website for turbo code can u send me again From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Mathias Weierganz Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Thu, 27 Nov 2014 09:40:37 +0100 Organization: albasani.net Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.albasani.net cVUnQQPBxhqpSCBM8tQK3+RW8+7ty96JBqkNSWZaacdiXXj0zd+KA4dN0/jdiwuAyUUWxecq0gDlquuCu0iWKTX8n4UQhS/rdKsUVWTCjcz/0UVTu4y7v45NfQct3zTQ NNTP-Posting-Date: Thu, 27 Nov 2014 08:40:37 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="dZM1fkeRvpU4VugxlML3yk5X4VBak+gAjzdNTTLw9xzStNpyW9kPonUin3fiPUdHdid1MfLnysJKZMefyW0ycfO6XSmUQkvevgGVPzjg0EpNby0HDJKeP6OYdlbKG4KI"; mail-complaints-to="abuse@albasani.net" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:jelC626IdD4MCNOt/0uIYxqVnFc= Xref: mx02.eternal-september.org comp.lang.vhdl:7877 Am 26.11.2014 20:23, schrieb GaborSzakacs: > > Xilinx tools use a different front-end to synthesize 6-series and > newer FPGA's by default. If your code works with the new front- > end, you can try to use it on older parts. In the XST command > line add the option: > > -use_new_parser yes > > If you use the Navigator GUI, you can apply this option under > "Other XST Command Line Options" in the synthesis properties. > This works fine for me. Many thanks for this hint. Mathias From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Xilinx ISE14: Problems with Sythesize Date: Thu, 27 Nov 2014 11:26:55 +0000 (UTC) Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 27 Nov 2014 11:26:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="26475"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19OO3pYn2sU1/w9TetWPUL9XxlL6cJnx5k=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:v91n64F/2LPKx9k8fatygKVU9pc= Xref: mx02.eternal-september.org comp.lang.vhdl:7878 On Wed, 26 Nov 2014 13:20:51 +0100, Mathias Weierganz wrote: > But is there an easy solution for my second problem? The synthesis don't > want to see this construct: > databus_i => (others => '0'), > and give me this error message: > ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in > unconstrained array aggregate. Easily solved by constraining the array aggregate: databus_i => (databus_i'range => '0'), making the code more portable -- Brian From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.182.92.163 with SMTP id cn3mr5267392obb.49.1417141790936; Thu, 27 Nov 2014 18:29:50 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr952qgf.11.1417141790863; Thu, 27 Nov 2014 18:29:50 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no9014412igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2895006qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Nov 2014 18:29:50 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Subject: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 02:29:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1648 X-Received-Body-CRC: 2822916710 Xref: mx02.eternal-september.org comp.lang.vhdl:7879 http://goo.gl/ZgNnK4 Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff). I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00". The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working). Thank you in advanced. From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Thu, 27 Nov 2014 22:27:23 -0500 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 03:27:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="29976"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18k5+aG0oWCrqwoMBHCx2Id" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Cancel-Lock: sha1:yq0TM7kcNRgrmkJnDcTQJVrSZgE= Xref: mx02.eternal-september.org comp.lang.vhdl:7880 On 11/27/2014 9:29 PM, JB wrote: > http://goo.gl/ZgNnK4 > > Above is the VHDL code I've attached relating to a small "Baseball Scoreboard" project. I'm fairly new to VHDL (~2 months) so bare with me when it comes to common practices (real world type stuff). > > I'm trying to code this now so, for instance, when the baseball count is 3-BALLS and 1-STRIKE and when the next pitch is thrown is a BALL then both the balls and strikes get reset back to "000" and "00". > > The code attached is working but without this feature. I've tried numerous things without any luck. The reset on the top-level is for a "hits" button. When a hit is produced this button resets the count (currently working). > > Thank you in advanced. > The problem I see is that you are using the "button press" for each outcome as a clock. In real world applications, this has issues due to switch bouncing. However, supposing you had a "bounceless" button, you still get into trouble because you now *need* two processes (as you currently have) in order to use these two "clocks" but at the same time you can't assign balls (or strikes) in *both* of these processes, at least for synthesizable code. It might be possible to generate two signals when strike or ball happen on full count, and use each signal as an asynchronous reset to the other process. However this can get a bit messy. The usual way to handle this sort of problem is to use a free-running clock to sample the buttons. Then your state logic can all be in the same process driven by that clock's rising edge. You would use shift registers to synchronize and delay each button press and use bits from these shift registers to detect edges of the button synchronous to the clock. Now with one process, you can set or clear any number of signals on any button event (as detected by looking at the S/R bits). -- Gabor From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.52.1.103 with SMTP id 7mr40296873vdl.6.1417148476285; Thu, 27 Nov 2014 20:21:16 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr729199qgz.1.1417148476206; Thu, 27 Nov 2014 20:21:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no2411513qap.1!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2905056qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Nov 2014 20:21:16 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <653b4f7e-b556-48e0-bcab-fc7ecef4334e@googlegroups.com> Subject: Re: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 04:21:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1605 X-Received-Body-CRC: 3168534803 Xref: mx02.eternal-september.org comp.lang.vhdl:7881 This is funny you mention the "button press" as the clock because I know it's not the right method. I actually used a clock input and had changed it based on a friend's input, but knew it looked funny. Also, the fact I could not use both signal in my processes was another big issue and something I figured would have to be changed. Well, thank you very much Gabor. Glad I actually came to some solution (and had the same thoughts as you). I will implement what you suggested. Thanks again! From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: 28 Nov 2014 09:01:15 GMT Lines: 26 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> X-Trace: individual.net OjhmjEPXTg1rusa5h6CxWgMQ0m5tlmngyW4QroBkTloDPfew45 X-Orig-Path: not-for-mail Cancel-Lock: sha1:AfCEFoW2mM6vv4u5L8fx/oqKoUg= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7882 Hi Rick, rickman wrote: [] > I recommend that you fix your code to get rid of warnings. Otherwise > you become inured to them and eventually they will cause you to miss a > valid warning that you need to pay attention to. Just initialize the > full array to something that isn't a letter... ;) This is a sound suggestion, but I won't initialize those objects in the vhdl code since is error prone (you may suddenly forget to reset an added object and still get valid data). I usually get around this with the following lines in my .do file: set StdArithNoWarnings 1 set NumericStdNoWarnings 1 run 0 ns; set StdArithNoWarnings 0 set NumericStdNoWarnings 0 run -all HTH, Al From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.42.103.76 with SMTP id l12mr752661ico.8.1417172069952; Fri, 28 Nov 2014 02:54:29 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr4937qgd.27.1417172069861; Fri, 28 Nov 2014 02:54:29 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no9207703igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no2969339qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 02:54:29 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Fri, 28 Nov 2014 10:54:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7883 Makes a change from a traffic light controller. For full marks you need to read up on metastability, your simulator will always work but real D types can't cope with the button being pressed exactly when the clock edge occurs. Colin From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.182.245.162 with SMTP id xp2mr41498216obc.8.1417188283151; Fri, 28 Nov 2014 07:24:43 -0800 (PST) X-Received: by 10.140.38.197 with SMTP id t63mr4657qgt.31.1417188283126; Fri, 28 Nov 2014 07:24:43 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9351314igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2535997qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 07:24:43 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.176.197.14; posting-account=JQXykgoAAAB5c7UjCcMIJQGNoGxD60UO NNTP-Posting-Host: 88.176.197.14 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Subject: Generate find a good solution From: Olivier Dir Injection-Date: Fri, 28 Nov 2014 15:24:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7884 I have this process, pState : process(Clk) begin if Clk'event and Clk='1' then if SRst = '1' then State <= ST_IDLE; else case State is when ST_IDLE => if DspTrfAvb = '1' then State <= ST_TRF2DSP; elsif DataAbleRam(1) = '1' then State <= ST_WDATA1; elsif DataAbleRam(2) = '1' then State <= ST_WDATA2; elsif DataAbleRam(3) = '1' then State <= ST_WDATA3; elsif DataAbleRam(4) = '1' then State <= ST_WDATA4; elsif DataAbleRam(5) = '1' then State <= ST_WDATA5; elsif DataAbleRam(6) = '1' then State <= ST_WDATA6; elsif DataAbleRam(7) = '1' then State <= ST_WDATA7; elsif DataAbleRam(8) = '1' then State <= ST_WDATA8; else State <= ST_IDLE; end if; when ST_WDATA1 => if RdDataInRamRd(1) = '1' then State <= ST_DATA1; else State <= ST_WDATA1; end if; when ST_DATA1 => if DataAbleRamRd(1) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA1; end if; when ST_WDATA2 => if RdDataInRamRd(2) = '1' then State <= ST_DATA2; else State <= ST_WDATA2; end if; when ST_DATA2 => if DataAbleRamRd(2) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA2; end if; when ST_WDATA3 => if RdDataInRamRd(3) = '1' then State <= ST_DATA3; else State <= ST_WDATA3; end if; when ST_DATA3 => if DataAbleRamRd(3) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA3; end if; when ST_WDATA4 => if RdDataInRamRd(4) = '1' then State <= ST_DATA4; else State <= ST_WDATA4; end if; when ST_DATA4 => if DataAbleRamRd(4) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA4; end if; when ST_WDATA5 => if RdDataInRamRd(5) = '1' then State <= ST_DATA5; else State <= ST_WDATA5; end if; when ST_DATA5 => if DataAbleRamRd(5) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA5; end if; when ST_WDATA6 => if RdDataInRamRd(6) = '1' then State <= ST_DATA6; else State <= ST_WDATA6; end if; when ST_DATA6 => if DataAbleRamRd(6) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA6; end if; when ST_WDATA7 => if RdDataInRamRd(7) = '1' then State <= ST_DATA7; else State <= ST_WDATA7; end if; when ST_DATA7 => if DataAbleRamRd(7) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA7; end if; when ST_WDATA8 => if RdDataInRamRd(8) = '1' then State <= ST_DATA8; else State <= ST_WDATA8; end if; when ST_DATA8 => if DataAbleRamRd(8) = '0' then State <= ST_CHKTXAVB; else State <= ST_DATA8; end if; ---- end case; end if; end if; end process; what is the best syntax ? thank for advance Olivier From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Fri, 28 Nov 2014 10:43:35 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 15:43:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="1528"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jIT4vvd7IPRcSVUhiW63G" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:aYUBy0Km3ZvajUimtaKItcmMk/U= Xref: mx02.eternal-september.org comp.lang.vhdl:7885 On 11/28/2014 4:01 AM, alb wrote: > Hi Rick, > > rickman wrote: > [] >> I recommend that you fix your code to get rid of warnings. Otherwise >> you become inured to them and eventually they will cause you to miss a >> valid warning that you need to pay attention to. Just initialize the >> full array to something that isn't a letter... ;) > > This is a sound suggestion, but I won't initialize those objects in the > vhdl code since is error prone (you may suddenly forget to reset an > added object and still get valid data). I don't understand. If you forget to reset a signal, how will that create a problem? The type of warning the OP is talking about happens because the signal is *not* initialized and is a useful flag for that condition. It is not assured to catch all uninitialized signals, but how is intentionally not initializing them better? > I usually get around this with the following lines in my .do file: > > set StdArithNoWarnings 1 > set NumericStdNoWarnings 1 > run 0 ns; > set StdArithNoWarnings 0 > set NumericStdNoWarnings 0 > > run -all > > HTH, > > Al > -- Rick From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Generate find a good solution Date: Fri, 28 Nov 2014 10:45:44 -0500 Organization: A noiseless patient Spider Lines: 152 Message-ID: References: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Nov 2014 15:45:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="3001"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+FSusdbLVRqBceze5uo6pf" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: <70180598-daea-412f-b539-875d10ffbc3a@googlegroups.com> Cancel-Lock: sha1:wWQqF4so5s7PtuY/S9NSDXmd9Tc= Xref: mx02.eternal-september.org comp.lang.vhdl:7886 On 11/28/2014 10:24 AM, Olivier Dir wrote: > I have this process, > pState : process(Clk) > begin > if Clk'event and Clk='1' then > if SRst = '1' then > State <= ST_IDLE; > else > case State is > when ST_IDLE => > if DspTrfAvb = '1' then > State <= ST_TRF2DSP; > elsif DataAbleRam(1) = '1' then > State <= ST_WDATA1; > elsif DataAbleRam(2) = '1' then > State <= ST_WDATA2; > elsif DataAbleRam(3) = '1' then > State <= ST_WDATA3; > elsif DataAbleRam(4) = '1' then > State <= ST_WDATA4; > elsif DataAbleRam(5) = '1' then > State <= ST_WDATA5; > elsif DataAbleRam(6) = '1' then > State <= ST_WDATA6; > elsif DataAbleRam(7) = '1' then > State <= ST_WDATA7; > elsif DataAbleRam(8) = '1' then > State <= ST_WDATA8; > else > State <= ST_IDLE; > end if; > when ST_WDATA1 => > if RdDataInRamRd(1) = '1' then > State <= ST_DATA1; > else > State <= ST_WDATA1; > end if; > when ST_DATA1 => > if DataAbleRamRd(1) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA1; > end if; > when ST_WDATA2 => > if RdDataInRamRd(2) = '1' then > State <= ST_DATA2; > else > State <= ST_WDATA2; > end if; > when ST_DATA2 => > if DataAbleRamRd(2) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA2; > end if; > when ST_WDATA3 => > if RdDataInRamRd(3) = '1' then > State <= ST_DATA3; > else > State <= ST_WDATA3; > end if; > when ST_DATA3 => > if DataAbleRamRd(3) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA3; > end if; > when ST_WDATA4 => > if RdDataInRamRd(4) = '1' then > State <= ST_DATA4; > else > State <= ST_WDATA4; > end if; > when ST_DATA4 => > if DataAbleRamRd(4) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA4; > end if; > when ST_WDATA5 => > if RdDataInRamRd(5) = '1' then > State <= ST_DATA5; > else > State <= ST_WDATA5; > end if; > when ST_DATA5 => > if DataAbleRamRd(5) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA5; > end if; > when ST_WDATA6 => > if RdDataInRamRd(6) = '1' then > State <= ST_DATA6; > else > State <= ST_WDATA6; > end if; > when ST_DATA6 => > if DataAbleRamRd(6) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA6; > end if; > when ST_WDATA7 => > if RdDataInRamRd(7) = '1' then > State <= ST_DATA7; > else > State <= ST_WDATA7; > end if; > when ST_DATA7 => > if DataAbleRamRd(7) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA7; > end if; > when ST_WDATA8 => > if RdDataInRamRd(8) = '1' then > State <= ST_DATA8; > else > State <= ST_WDATA8; > end if; > when ST_DATA8 => > if DataAbleRamRd(8) = '0' then > State <= ST_CHKTXAVB; > else > State <= ST_DATA8; > end if; > ---- > end case; > end if; > end if; > end process; > > what is the best syntax ? > > thank for advance > Olivier > Not clear what you're asking. The only thing I notice is that your process has a lot of unnecessary else clauses that assign the state to its current value. This same action is implied by leaving out the else clause, and doing so makes the whole thing shorter, and in my opinion easier to read. The only other observation is that even if you have fully used all cases, it is often better to pick one and use "default" instead of the case name. Some synthesizers have an easier time to optimize code this way. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.42.246.66 with SMTP id lx2mr18881122icb.0.1417206881365; Fri, 28 Nov 2014 12:34:41 -0800 (PST) X-Received: by 10.140.104.145 with SMTP id a17mr2373qgf.16.1417206881294; Fri, 28 Nov 2014 12:34:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9528493igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2610805qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 12:34:41 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: JB Injection-Date: Fri, 28 Nov 2014 20:34:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7887 @Gabor I'm kind of stumped on this one. I understand the shift register approach b= ut don't see how I can get the correct outputs of "01" "11" and "001" "011"= "111". Whenever I place a '1' on the button press in put I get a constant = change of outputs either "00" "10" "11" "00" even if the button is not pres= sed. Hmm.. From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Fri, 28 Nov 2014 21:23:18 -0500 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 29 Nov 2014 02:23:14 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="83a31ac2c505da17ce863bed0f607c5d"; logging-data="13588"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SapKHwoUWWqfIbw8GsDEN" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 In-Reply-To: Cancel-Lock: sha1:D5vKksCepMxCVzpWNokgftM/0mU= Xref: mx02.eternal-september.org comp.lang.vhdl:7888 On 11/28/2014 3:34 PM, JB wrote: > @Gabor > > I'm kind of stumped on this one. I understand the shift register approach but don't see how I can get the correct outputs of "01" "11" and "001" "011" "111". Whenever I place a '1' on the button press in put I get a constant change of outputs either "00" "10" "11" "00" even if the button is not pressed. Hmm.. > OK, I have to say I have no idea what you're asking here. I looked back at your code and you haven't updated the paste.org page. So without seeing what you have now I really can't comment or help. By the way, you can always paste the VHDL code (at least the interesting bits) right into your post here instead of using an ad-sponsored site. After all VHDL is just text... -- Gabor From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.67.22.35 with SMTP id hp3mr13940655pad.11.1417231977527; Fri, 28 Nov 2014 19:32:57 -0800 (PST) X-Received: by 10.140.41.147 with SMTP id z19mr798713qgz.1.1417231977478; Fri, 28 Nov 2014 19:32:57 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no9704271igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2689922qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 19:32:57 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Subject: Re: Question pertaining to a project From: JB Injection-Date: Sat, 29 Nov 2014 03:32:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7889 --So this does exactly what I want it too without the feature I described to you prior. I was having a hard time implementing the shift registers. Here, I have the case statements but everything is now within one process block. My idea was something like: if tempstrikes <="11" then tempballs<="000"; type of thing, in order to clear the balls count if another strike is thrown and causes an out. But, it's not going to work based on the other assignments within the case statements. library IEEE; use ieee.std_logic_1164.all; entity Baseball_New is port (button_strikes : in std_logic; button_balls : in std_logic; clk : in std_logic; reset : in std_logic; led_strikes : out std_logic_vector (1 downto 0); led_balls : out std_logic_vector (2 downto 0) ); end entity; architecture Baseball_New_arch of Baseball_New is signal tempstrikes : std_logic_vector (1 downto 0); signal tempballs : std_logic_vector (2 downto 0); begin process (clk) begin if reset='1' then tempstrikes <="00"; elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then case ( tempstrikes) is when "00" => tempstrikes <="01"; when "01" => tempstrikes <="11"; when "10" => tempstrikes <="00"; when "11" => tempstrikes<="00"; when others => tempstrikes <="00"; end case; end if; end process; led_strikes <= tempstrikes; process (clk) is begin if reset='1' then tempballs<="000"; elsif clk'EVENT AND clk='1' AND button_balls ='1' then case (tempballs) is when "000" => tempballs <="001"; when "001" => tempballs <="011"; when "010" => tempballs <="000"; when "011" => tempballs<="111"; when others => tempballs <= "000"; end case; end if; end process; led_balls<=tempballs; end Baseball_New_arch; From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.50.88.10 with SMTP id bc10mr40014453igb.5.1417232318855; Fri, 28 Nov 2014 19:38:38 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr31qgd.6.1417232318775; Fri, 28 Nov 2014 19:38:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no9706029igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no2690897qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 28 Nov 2014 19:38:38 -0800 (PST) In-Reply-To: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.182.149.133; posting-account=NrqQLgoAAABQg-Vi8fsfQch46BvFR5iI NNTP-Posting-Host: 73.182.149.133 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: JB Injection-Date: Sat, 29 Nov 2014 03:38:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:7890 **Nevermind, this still has two processes. My apologies. From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Fri, 28 Nov 2014 23:34:36 -0500 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 29 Nov 2014 04:34:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4568"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+DhP4bYjY3yD0hRowXfzxZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:fqHA6dcu489pQtpMat3Lksy1m3c= Xref: mx02.eternal-september.org comp.lang.vhdl:7891 On 11/28/2014 10:38 PM, JB wrote: > **Nevermind, this still has two processes. My apologies. You need to change the sensitivity list to include reset. process (clk, reset) Also, if you want to post your code here, you should remove the tabs and replace with spaces. I believe you code is using something less than 8 spaces per tab while posting tabs here defaults to 8. -- Rick From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: 29 Nov 2014 23:31:52 GMT Lines: 45 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> X-Trace: individual.net XMYyK1BBx0YkgwPh6Qdh+wzEoNP6JKbJkr50U9Xd0e3WB+tcbo X-Orig-Path: not-for-mail Cancel-Lock: sha1:UxzeiRPXoMCqt7JyCBH6QeOBFxo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7892 Hi Rick, rickman wrote: [] >> This is a sound suggestion, but I won't initialize those objects in the >> vhdl code since is error prone (you may suddenly forget to reset an >> added object and still get valid data). > > I don't understand. If you forget to reset a signal, how will that > create a problem? The type of warning the OP is talking about happens > because the signal is *not* initialized and is a useful flag for that > condition. It is not assured to catch all uninitialized signals, but > how is intentionally not initializing them better? assume the following code: signal a: std_logic_vector := x"0123"; signal b: std_logic_vector := x"4567"; ... process (rst, clk) begin if rst = '1' then a <= '0000'; elsif rising_edge(clk) then -- do something comparing a and b end if; end process; The code above 'depends' on the initialization in the signals declaration and your simulation may differ from the behavior after synthesis, unless your target (and the toolchain) supports explicit initializations. My suggestion is to properly *reset* every register in your logic because this is how you control what is going to happen when your fpga will be doing *after* reset. You can safely disregard all signal initializations and handle those warnings at time 0 with the workaround posted. Al From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Warning interpretation ? Date: Sat, 29 Nov 2014 20:29:50 -0500 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <00f7a881-e23c-49a5-98ca-36cacf1a2a9c@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 30 Nov 2014 01:30:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25046"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+PO+peMpk8rn095LMHRsgI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:71zssctNc/+CkT6qTe28dOJTEWg= Xref: mx02.eternal-september.org comp.lang.vhdl:7893 On 11/29/2014 6:31 PM, alb wrote: > Hi Rick, > > rickman wrote: > [] >>> This is a sound suggestion, but I won't initialize those objects in the >>> vhdl code since is error prone (you may suddenly forget to reset an >>> added object and still get valid data). >> >> I don't understand. If you forget to reset a signal, how will that >> create a problem? The type of warning the OP is talking about happens >> because the signal is *not* initialized and is a useful flag for that >> condition. It is not assured to catch all uninitialized signals, but >> how is intentionally not initializing them better? > > assume the following code: > > > signal a: std_logic_vector := x"0123"; > signal b: std_logic_vector := x"4567"; > > .... > > process (rst, clk) > begin > if rst = '1' then > a <= '0000'; > elsif rising_edge(clk) then > -- do something comparing a and b > end if; > end process; > > > > The code above 'depends' on the initialization in the signals > declaration and your simulation may differ from the behavior after > synthesis, unless your target (and the toolchain) supports explicit > initializations. > > My suggestion is to properly *reset* every register in your logic > because this is how you control what is going to happen when your fpga > will be doing *after* reset. You can safely disregard all signal > initializations and handle those warnings at time 0 with the workaround > posted. If resetting a signal in your design is a requirement, it should have a way of verifying that it was reset. Every requirement should be verified. I would do that in the test bench. -- Rick From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.68.180.101 with SMTP id dn5mr2012770pbc.5.1417509046536; Tue, 02 Dec 2014 00:30:46 -0800 (PST) X-Received: by 10.50.30.202 with SMTP id u10mr35200igh.6.1417509046431; Tue, 02 Dec 2014 00:30:46 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no11810325igd.0!news-out.google.com!d20ni1426igz.0!nntp.google.com!h15no11810324igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 00:30:45 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=175.136.155.8; posting-account=5T8syQoAAADGHYRHO4dd1KbX_Ht4gcuF NNTP-Posting-Host: 175.136.155.8 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Subject: Local Controller for latch From: Mohd Zulkarnain Jaranee Injection-Date: Tue, 02 Dec 2014 08:30:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7894 Hi, I want to make a controller which will enable the latch.=20 As you can seen on my code below, the signal en will take the output from w= AND x to enable the latch. After that, w and x will fetch the en. For exam= ple, initially, let say the w and x values start at 1, the en will become 1= and cause the latch to fetch data from data_in to data_out. After that, en= will become the input of w and x and cause the latch to disable. However, = the circuit didn't work when I tested it using altera university waveform p= rogram. The data_out didnt take the value of data_in. I can't figure out wh= at is the problem still I'm new in VHDL. Hope you can assist/advice me on t= his :) Sorry for my bad english. library ieee; use ieee.std_logic_1164.all; entity gasp_ctrl is port( w,x : inout std_logic; --! bidirectional wire data_in : in std_logic; --! Data In when latch is enable data_out: out std_logic -- ); end gasp_ctrl; architecture ctrl of gasp_ctrl is signal en, ww, xx : std_logic; =09 begin en <=3D w and x; ------=20 ww <=3D en; xx <=3D not en; w <=3D ww; x <=3D xx; =09 -------- Latch ------ process(en) begin if(en =3D '1') then data_out <=3D data_in; end if; end process; end gasp_ctrl; From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.66.231.100 with SMTP id tf4mr60257300pac.48.1417513258924; Tue, 02 Dec 2014 01:40:58 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr19217qgf.11.1417513258608; Tue, 02 Dec 2014 01:40:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3474772igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no3548752qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:40:58 -0800 (PST) In-Reply-To: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29367b80-c99e-4872-883b-8f381472ba48@googlegroups.com> Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:40:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7895 Hi kwaj, i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.182.43.170 with SMTP id x10mr59171125obl.15.1417513289625; Tue, 02 Dec 2014 01:41:29 -0800 (PST) X-Received: by 10.140.48.69 with SMTP id n63mr1446qga.21.1417513289559; Tue, 02 Dec 2014 01:41:29 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no11844332igd.0!news-out.google.com!m4ni588qag.1!nntp.google.com!s7no3548799qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:41:29 -0800 (PST) In-Reply-To: <1105965927.803887.86760@f14g2000cwb.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> <1105965927.803887.86760@f14g2000cwb.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:41:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7896 Hi zinga i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.42.197.134 with SMTP id ek6mr2355345icb.6.1417513305153; Tue, 02 Dec 2014 01:41:45 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr110551qgj.7.1417513305085; Tue, 02 Dec 2014 01:41:45 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no11844429igd.0!news-out.google.com!m4ni576qag.1!nntp.google.com!w8no4042618qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:41:44 -0800 (PST) In-Reply-To: <91ca356bf018d3c2ea1e0c445b417d18@localhost.talkaboutprogramming.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <41ea5017$0$1041$5a62ac22@per-qv1-newsreader-01.iinet.net.au> <91ca356bf018d3c2ea1e0c445b417d18@localhost.talkaboutprogramming.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL code for Turbo Codes From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:41:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7897 Hi i need vhdl code for turbo codes .can u give me this.. i will be very thankful to you. best regards From newsfish@newsfish Tue Dec 29 16:43:37 2015 X-Received: by 10.70.44.161 with SMTP id f1mr33638081pdm.7.1417513452238; Tue, 02 Dec 2014 01:44:12 -0800 (PST) X-Received: by 10.182.241.135 with SMTP id wi7mr3356obc.29.1417513452059; Tue, 02 Dec 2014 01:44:12 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no11845056igd.0!news-out.google.com!d20ni730igz.0!nntp.google.com!h15no3475217igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 2 Dec 2014 01:44:11 -0800 (PST) In-Reply-To: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 References: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <74509e7f-214b-4eb7-ad79-9cdf201c3b09@googlegroups.com> Subject: Re: Looking for links to interleaver design for Turbo codes. From: Muhammad Injection-Date: Tue, 02 Dec 2014 09:44:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7898 On Monday, January 7, 2002 11:08:40 PM UTC+1, pacific ocean wrote: > Looking for links to interleaver design for Turbo codes. > > THX > Fredj hi, i need the code for interleaver can u give me plz.. thanks From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Local Controller for latch Date: Tue, 02 Dec 2014 04:51:04 -0500 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 Dec 2014 09:51:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5273"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+X59y627vMdGZL5OHERHS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <5471aa4c-ccf3-463d-a560-d48aa43207d5@googlegroups.com> Cancel-Lock: sha1:tNQ608Kt9+EKkRW7jEQf9q3hx10= Xref: mx02.eternal-september.org comp.lang.vhdl:7899 On 12/2/2014 3:30 AM, Mohd Zulkarnain Jaranee wrote: > Hi, I want to make a controller which will enable the latch. > > As you can seen on my code below, the signal en will take the output from w AND x to enable the latch. After that, w and x will fetch the en. For example, initially, let say the w and x values start at 1, the en will become 1 and cause the latch to fetch data from data_in to data_out. After that, en will become the input of w and x and cause the latch to disable. However, the circuit didn't work when I tested it using altera university waveform program. The data_out didnt take the value of data_in. I can't figure out what is the problem still I'm new in VHDL. Hope you can assist/advice me on this :) Sorry for my bad english. > > library ieee; > use ieee.std_logic_1164.all; > entity gasp_ctrl is > port( > w,x : inout std_logic; --! bidirectional wire > data_in : in std_logic; --! Data In when latch is enable > data_out: out std_logic -- > ); > end gasp_ctrl; > > architecture ctrl of gasp_ctrl is > signal en, ww, xx : std_logic; > > begin > en <= w and x; ------ > ww <= en; > xx <= not en; > w <= ww; > x <= xx; > > > -------- Latch ------ > process(en) > begin > if(en = '1') then > data_out <= data_in; > end if; > end process; > end gasp_ctrl; You have some fundamental misunderstandings of how logic and HTML work. I can identify two errors without trying. The really big one is that you seem to want X and W to be inputs, but also assign them in your code. Which are they, internal signals or inputs? Defining them as inout in your port doesn't make this synthesizeable. The next error is creating a feedback loop in the concurrent statements. By assigning values to X and W that depend on X and W you are creating unintentional latches. Do this. This is a simple circuit. Try drawing a logic schematic of what you think this should produce in the FPGA. Use AND and NOT functions and show what it should be. Finally, did you synthesize this or just load it into a chip and try running it? I'm surprised the tools didn't complain about this code. I guess maybe it just gave you warnings which you didn't pay attention to. Oh, there's a third error. You need to add data_in to your sensitivity list in the process... I don't think the simulation will work correctly without it. -- Rick From newsfish@newsfish Tue Dec 29 16:43:37 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Looking for links to interleaver design for Turbo codes. Date: Tue, 2 Dec 2014 12:45:03 +0000 (UTC) Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <1fb8ce7b.0201071408.2aeed3e7@posting.google.com> <74509e7f-214b-4eb7-ad79-9cdf201c3b09@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 2 Dec 2014 12:45:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+2rWK9gbGDpj7j/aHPKONSYPVXolpyHiQ=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:XN5g22paiQvPBwsdZ7KytpM3eyU= Xref: mx02.eternal-september.org comp.lang.vhdl:7900 On Tue, 02 Dec 2014 01:44:11 -0800, Muhammad wrote: > On Monday, January 7, 2002 11:08:40 PM UTC+1, pacific ocean wrote: >> Looking for links to interleaver design for Turbo codes. >> >> THX Fredj > > hi, > i need the code for interleaver can u give me plz.. > > thanks Well he's had 12 years to finish the assignment so maybe he'll give you teh codez. Good luck! From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: VHDL 2008 support in Modelsim? Date: Fri, 05 Dec 2014 14:48:03 +0200 Organization: An impatient and LOUD arachnid Lines: 35 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx02.eternal-september.org; posting-host="0d8432157885fb838356cc0832d33c8c"; logging-data="20586"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/k1vA4NoG0ax1Ut+7AwIkx" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:a4JYldoQu7RAXHYPh7ijxVwzuc8= sha1:Mlib5uZEurxo/OsnOSRoJ0QRRVc= Xref: mx02.eternal-september.org comp.lang.vhdl:7901 Is Modelsim still not implementing VHDL 2008? I have some code with the "new" if ... generate with else branch but Modelsim 10.1e doesn't seem to support that. Or is it just that the Altera's Starter Edition doesn't support that? I don't have a Modelsim PE or SE installed right now... I tried case in generate as well but it didn't work any better. Example code, vcom -2008 says ** Error: generate_prob.vhdl(20): near "else": syntax error (line 20 is the else generate line.) LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity dummy is generic ( some_boolean_generic : boolean := false); port( clk : in std_logic; reset_n : in std_logic; dout : out std_logic ); end dummy; architecture dummy_arch of dummy is begin some_label: if some_boolean_generic = false generate dout <= '0'; else generate dout <= '1'; end generate some_label; end dummy_arch; From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 support in Modelsim? Date: Fri, 05 Dec 2014 07:58:10 -0500 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 5 Dec 2014 12:57:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26753"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bbg16YLUGd+UiAW9n2lio" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:TzXowgniWHuomjGIV6hVFRPezAg= Xref: mx02.eternal-september.org comp.lang.vhdl:7902 I don't know specifically about Modelsim, but in many tools the VHDL 2008 features have to be turned on in the options. Try nosing around to see if you can find that. Rick On 12/5/2014 7:48 AM, Anssi Saari wrote: > > Is Modelsim still not implementing VHDL 2008? I have some code with the > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > to support that. Or is it just that the Altera's Starter Edition doesn't > support that? I don't have a Modelsim PE or SE installed right now... I > tried case in generate as well but it didn't work any better. > > Example code, vcom -2008 says > ** Error: generate_prob.vhdl(20): near "else": syntax error > (line 20 is the else generate line.) > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > entity dummy is > generic ( > some_boolean_generic : boolean := false); > port( > clk : in std_logic; > reset_n : in std_logic; > dout : out std_logic > ); > end dummy; > > architecture dummy_arch of dummy is > > begin > > some_label: if some_boolean_generic = false generate > dout <= '0'; > else generate > dout <= '1'; > end generate some_label; > > end dummy_arch; > -- Rick From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf04.am4!fx45.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 support in Modelsim? References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141204-1, 04/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 50 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1417789453 86.17.210.161 (Fri, 05 Dec 2014 14:24:13 UTC) NNTP-Posting-Date: Fri, 05 Dec 2014 14:24:13 UTC Organization: virginmedia.com Date: Fri, 05 Dec 2014 14:24:10 +0000 X-Received-Body-CRC: 2076097356 X-Received-Bytes: 2238 Xref: mx02.eternal-september.org comp.lang.vhdl:7903 On 05/12/2014 12:48, Anssi Saari wrote: > > Is Modelsim still not implementing VHDL 2008? I have some code with the > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > to support that. Or is it just that the Altera's Starter Edition doesn't > support that? I don't have a Modelsim PE or SE installed right now... I > tried case in generate as well but it didn't work any better. Modelsim 10.1e was released in June of 2013. Your code compiled OK in the latest 10.3d release. Modelsim SE is an obsolete product and replaced by Questa core. Regards, Hans www.ht-lab.com > > Example code, vcom -2008 says > ** Error: generate_prob.vhdl(20): near "else": syntax error > (line 20 is the else generate line.) > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > > entity dummy is > generic ( > some_boolean_generic : boolean := false); > port( > clk : in std_logic; > reset_n : in std_logic; > dout : out std_logic > ); > end dummy; > > architecture dummy_arch of dummy is > > begin > > some_label: if some_boolean_generic = false generate > dout <= '0'; > else generate > dout <= '1'; > end generate some_label; > > end dummy_arch; > From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.224.125.195 with SMTP id z3mr15143464qar.0.1417790813755; Fri, 05 Dec 2014 06:46:53 -0800 (PST) X-Received: by 10.140.18.178 with SMTP id 47mr31153qgf.9.1417790813695; Fri, 05 Dec 2014 06:46:53 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no4797805qac.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4306138qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 06:46:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:630:340:100b:0:0:f:97dc; posting-account=2g_UWgoAAADr5MhVMVTej8gzC_urYh2K NNTP-Posting-Host: 2001:630:340:100b:0:0:f:97dc User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> Subject: Design and Implementation of a PS/2 Receiver From: steverowedder@googlemail.com Injection-Date: Fri, 05 Dec 2014 14:46:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1472 X-Received-Body-CRC: 4086034508 Xref: mx02.eternal-september.org comp.lang.vhdl:7904 Hi There, Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. It was a year since I have completed any work in VHDL. If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd All files are below any help is greatly appreciated! Please assist, thanks in advance. Regards From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.182.87.39 with SMTP id u7mr15294608obz.4.1417790842769; Fri, 05 Dec 2014 06:47:22 -0800 (PST) X-Received: by 10.140.32.74 with SMTP id g68mr11658qgg.22.1417790842740; Fri, 05 Dec 2014 06:47:22 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no4807074igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no4797826qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 06:47:22 -0800 (PST) In-Reply-To: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:630:340:100b:0:0:f:97dc; posting-account=2g_UWgoAAADr5MhVMVTej8gzC_urYh2K NNTP-Posting-Host: 2001:630:340:100b:0:0:f:97dc References: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design and Implementation of a PS/2 Receiver From: steverowedder@googlemail.com Injection-Date: Fri, 05 Dec 2014 14:47:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 Xref: mx02.eternal-september.org comp.lang.vhdl:7905 On Friday, December 5, 2014 2:46:55 PM UTC, stever...@googlemail.com wrote: > Hi There, > > Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. > > It was a year since I have completed any work in VHDL. > > If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd > > All files are below any help is greatly appreciated! > > Please assist, thanks in advance. > > Regards Please ask for files and I can provide them From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.182.89.136 with SMTP id bo8mr15868034obb.7.1417793059644; Fri, 05 Dec 2014 07:24:19 -0800 (PST) X-Received: by 10.140.82.106 with SMTP id g97mr14781qgd.27.1417793059579; Fri, 05 Dec 2014 07:24:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no13818971igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no4809154qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 5 Dec 2014 07:24:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=5.55.108.200; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 5.55.108.200 References: <65a5299f-ca90-4542-8932-d10d29addcb7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Design and Implementation of a PS/2 Receiver From: Nikolaos Kavvadias Injection-Date: Fri, 05 Dec 2014 15:24:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1447 X-Received-Body-CRC: 1967781131 Xref: mx02.eternal-september.org comp.lang.vhdl:7906 Hi, can you set the context? 1) Which board do you target? (it's a Xilinx one since you use .ucf parlance) 2) Sharing the starting files will help. To sum this up, I can help you. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.236.4.106 with SMTP id 70mr20633640yhi.33.1417886784966; Sat, 06 Dec 2014 09:26:24 -0800 (PST) X-Received: by 10.140.17.82 with SMTP id 76mr424763qgc.5.1417886784909; Sat, 06 Dec 2014 09:26:24 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no4564444qap.1!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no5056142qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Dec 2014 09:26:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.231.168.41; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 37.231.168.41 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Subject: Throughput under Quartus II From: AA Injection-Date: Sat, 06 Dec 2014 17:26:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: mx02.eternal-september.org comp.lang.vhdl:7907 hi, How to calculate the throughput in Mbps of the design under Quartus II ? Thank you, From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.42.246.66 with SMTP id lx2mr26862614icb.0.1417915759083; Sat, 06 Dec 2014 17:29:19 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr485677qgd.3.1417915759010; Sat, 06 Dec 2014 17:29:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no14661457igd.0!news-out.google.com!n9ni21qai.0!nntp.google.com!w8no5139620qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 6 Dec 2014 17:29:18 -0800 (PST) In-Reply-To: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> Subject: Re: Throughput under Quartus II From: KJ Injection-Date: Sun, 07 Dec 2014 01:29:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 8 Xref: mx02.eternal-september.org comp.lang.vhdl:7908 On Saturday, December 6, 2014 12:26:26 PM UTC-5, AA wrote: > hi, > How to calculate the throughput in Mbps of the design under Quartus II ? > > Thank you, Quartus does not calculate Mbps. Use a spreadsheet. KJ From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.236.1.37 with SMTP id 25mr24322332yhc.25.1417961944349; Sun, 07 Dec 2014 06:19:04 -0800 (PST) X-Received: by 10.140.108.5 with SMTP id i5mr5908qgf.11.1417961944291; Sun, 07 Dec 2014 06:19:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no5236413qac.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4744906qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 06:19:04 -0800 (PST) In-Reply-To: <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.132.244.204; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 213.132.244.204 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> <8f92d3d3-2611-46df-8e36-44203df3f68a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0af828dc-255c-4798-ba33-0a0abf5cdb5f@googlegroups.com> Subject: Re: Throughput under Quartus II From: AA Injection-Date: Sun, 07 Dec 2014 14:19:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: mx02.eternal-september.org comp.lang.vhdl:7909 On Sunday, December 7, 2014 4:29:20 AM UTC+3, KJ wrote: > On Saturday, December 6, 2014 12:26:26 PM UTC-5, AA wrote: > > hi, > > How to calculate the throughput in Mbps of the design under Quartus II ? > > > > Thank you, > > Quartus does not calculate Mbps. Use a spreadsheet. > > KJ What do you mean by spreadsheet? May you please give me some details? From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!backlog3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 07 Dec 2014 08:24:51 -0600 From: "Andy Bartlett" Newsgroups: comp.lang.vhdl References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> Subject: Re: Throughput under Quartus II Date: Sun, 7 Dec 2014 14:24:33 -0000 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5512 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5512 Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-bVE4DSsD6TxvCfPA5aA075zryITftJjpAy0HN93H0UNyosCxgrw1KL3C6PnPhuVXKAq53E/XL3Kt6Rc!ElMqr0RLZ/ByTCPzBZnMIWTbx8GNlOy4pTiTTAYUWPgzz7t9Pz0hf5Vt1NEaXF70s/7z9/YawfPR!FiMQqERgWmluPMCEpMO7O+Z5OKw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1716 Xref: mx02.eternal-september.org comp.lang.vhdl:7910 "AA" wrote in message news:1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com... > hi, > How to calculate the throughput in Mbps of the design under Quartus II ? > > Thank you, Use the TimeQuest timing analyzer. This will give you the maximum internal clock rate you can run your design at. It will calculate the longest register-register prop. delay and include register setup and hold times. You can also get it to list all the internal props. starting at the longest of you want to sift through manually. As usual, RTFM. Andy From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.236.207.136 with SMTP id n8mr27517760yho.5.1417977181952; Sun, 07 Dec 2014 10:33:01 -0800 (PST) X-Received: by 10.50.79.197 with SMTP id l5mr173767igx.17.1417977181744; Sun, 07 Dec 2014 10:33:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w8no5289385qac.0!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15058834igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 10:33:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Sun, 07 Dec 2014 18:33:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:7911 I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. -Gandalf From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 17:19:09 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 7 Dec 2014 22:18:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="24681"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ZDtfTDH8hfYG8C7W0gzHa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:f+/oWkZs161chuaKL8SL2USCPs4= Xref: mx02.eternal-september.org comp.lang.vhdl:7912 On 12/7/2014 1:33 PM, Gandalf wrote: > I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. If you want to know what features to include in a processor design, pick a processor suitable for the job you want to do and use those. :) Before you consider rolling your own processor, take a look at the others out there. There are around 1000 of them so far. -- Rick From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Dave Higton Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 22:24:01 GMT Organization: Home Lines: 12 Message-ID: <76087c7254.DaveMeUK@my.inbox.com> References: X-Trace: individual.net KuyaAsU/Ot10+4pFCL7QEwPlXkZWKK2xk+AmIKUr1x9Y7pXMA= X-Orig-Path: my.inbox.com%DaveMeUK Cancel-Lock: sha1:GaQLf/RkzY209v0g771r5HOYi9k= User-Agent: Messenger-Pro/7.06 (MsgServe/7.06) (RISC-OS/5.20) NewsHound/v1.52-32 Xref: mx02.eternal-september.org comp.lang.vhdl:7913 In message Gandalf wrote: > I was studying VHDL, when this thought struck me. What features do you > think a new microprocessor written in VHDL must possess? If this is the > wrong place to ask, kindly redirect me to the relevant group if possible. Your question makes no sense at all. VHDL is a means to implement whatever features you wish. It has no limitations that would cause you to reduce the feature set. Dave From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.236.231.180 with SMTP id l50mr27615781yhq.4.1418006548132; Sun, 07 Dec 2014 18:42:28 -0800 (PST) X-Received: by 10.50.111.130 with SMTP id ii2mr187891igb.16.1418006547948; Sun, 07 Dec 2014 18:42:27 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!s7no4875999qap.1!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15265283igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 18:42:27 -0800 (PST) In-Reply-To: <76087c7254.DaveMeUK@my.inbox.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 References: <76087c7254.DaveMeUK@my.inbox.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Mon, 08 Dec 2014 02:42:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2018 X-Received-Body-CRC: 2965408117 Xref: mx02.eternal-september.org comp.lang.vhdl:7914 On Monday, December 8, 2014 3:54:11 AM UTC+5:30, Dave Higton wrote: > In message > Gandalf wrote: > > > I was studying VHDL, when this thought struck me. What features do you > > think a new microprocessor written in VHDL must possess? If this is the > > wrong place to ask, kindly redirect me to the relevant group if possible. > > Your question makes no sense at all. VHDL is a means to implement > whatever features you wish. It has no limitations that would cause > you to reduce the feature set. > > Dave Let me rephrase it- If you were to build a microprocessor today which is geared towards microcomputing platforms, what low level feature you would implement in addition to the standard PC,ALU, FPU etc. From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.236.26.5 with SMTP id b5mr26456353yha.15.1418006618619; Sun, 07 Dec 2014 18:43:38 -0800 (PST) X-Received: by 10.50.43.166 with SMTP id x6mr189404igl.5.1418006618429; Sun, 07 Dec 2014 18:43:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no5367479qac.0!news-out.google.com!jh1ni6649igb.0!nntp.google.com!h15no15265511igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 7 Dec 2014 18:43:37 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.42.153.228; posting-account=FkTdOgoAAAB7m3bkX-1LHzztiNf9oUhr NNTP-Posting-Host: 119.42.153.228 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Gandalf Injection-Date: Mon, 08 Dec 2014 02:43:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1930 X-Received-Body-CRC: 2495878504 Xref: mx02.eternal-september.org comp.lang.vhdl:7915 On Monday, December 8, 2014 3:49:08 AM UTC+5:30, rickman wrote: > On 12/7/2014 1:33 PM, Gandalf wrote: > > I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. > > If you want to know what features to include in a processor design, pick > a processor suitable for the job you want to do and use those. :) > > Before you consider rolling your own processor, take a look at the > others out there. There are around 1000 of them so far. > > -- > > Rick Hey thanks Rick, I already went through the MIPS documentation and the ARM documentation. Could you suggest me some more? From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL Date: Sun, 07 Dec 2014 23:25:43 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Dec 2014 04:25:24 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="24198"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hRVjne98BaYhLImzPu/MD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:0Pqb3Ldd0EJOualkZq60NqzLFBw= Xref: mx02.eternal-september.org comp.lang.vhdl:7916 On 12/7/2014 9:43 PM, Gandalf wrote: > On Monday, December 8, 2014 3:49:08 AM UTC+5:30, rickman wrote: >> On 12/7/2014 1:33 PM, Gandalf wrote: >>> I was studying VHDL, when this thought struck me. What features do you think a new microprocessor written in VHDL must possess? If this is the wrong place to ask, kindly redirect me to the relevant group if possible. >> >> If you want to know what features to include in a processor design, pick >> a processor suitable for the job you want to do and use those. :) >> >> Before you consider rolling your own processor, take a look at the >> others out there. There are around 1000 of them so far. >> >> -- >> >> Rick > > Hey thanks Rick, > I already went through the MIPS documentation and the ARM documentation. Could you suggest me some more? I meant that home grown CPU designs. If you are serious about this the question is "why"? I've been down this path myself designing some number of iterations of MISC type processors. In the end it was educational, but only moderately useful. The smallest practical processor I've seen is the picoBlaze from Xilinx, but it is not HDL, but rather done with Xilinx primitives. So in that sense my CPU was the smallest I have seen that wasn't also dog slow, but not by much. There are lots of CPUs of a wide range of sizes all designed with different goals in mind. The question is, what is your goal? -- Rick From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: vhdl code review Date: 8 Dec 2014 09:01:08 GMT Lines: 36 Message-ID: X-Trace: individual.net bCHgHHldyqfNEQ7QZSk3TAoSxWPWEjTrGVMTrvcyDFGitTUByX X-Orig-Path: not-for-mail Cancel-Lock: sha1:11/8n+V1qDMhOJofc70Lgfj8g0o= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7917 Hi everyone, inspired by a nice read (the art of designing embedded systems - Jack Ganssle) I've started wondering what's the best way to perform code reviews for vhdl. Our projects are on the scale of ~100 KLOC (including testbenches) and if the number of lines reviewed per hour presented in the book is correct (150) it will mean that we will need to spend ~85 days in code reviews (considering a day made out of 8 working hours)! Considering that best practices mandate 4 people per review (moderator, reader. recorder, author), only review would cost one and a half man/year! Am I missing something? In order to make reviews effective how can we organize them? I've also seen a presentation on klabs.org which talked about reviewing the netlist as well, since that is what ultimately goes in the hardware. This will complexify the process enormously, to the point where no one single manager would be on board. Any insight on this subject? If you happen to know any material (articles/books/presentations) which is worth reading I'll be happy to have a look. Thanks a lot, Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post01.fr7!fx39.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141208-0, 08/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1418031960 86.17.210.161 (Mon, 08 Dec 2014 09:46:00 UTC) NNTP-Posting-Date: Mon, 08 Dec 2014 09:46:00 UTC Organization: virginmedia.com Date: Mon, 08 Dec 2014 09:45:59 +0000 X-Received-Body-CRC: 2706193000 X-Received-Bytes: 2603 Xref: mx02.eternal-september.org comp.lang.vhdl:7918 Hi Al, On 08/12/2014 09:01, alb wrote: > Hi everyone, > > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. > > Our projects are on the scale of ~100 KLOC (including testbenches) and > if the number of lines reviewed per hour presented in the book is > correct (150) it will mean that we will need to spend ~85 days in code > reviews (considering a day made out of 8 working hours)! > > Considering that best practices mandate 4 people per review (moderator, > reader. recorder, author), only review would cost one and a half > man/year! > > Am I missing something? In order to make reviews effective how can we > organize them? > > I've also seen a presentation on klabs.org which talked about reviewing > the netlist as well, since that is what ultimately goes in the hardware. > This will complexify the process enormously, to the point where no one > single manager would be on board. > > Any insight on this subject? If you happen to know any material > (articles/books/presentations) which is worth reading I'll be happy to > have a look. > > Thanks a lot, > > Al I would suggest you look into linting tools as this is the only way to handle large amount of code. There are some really nice ones like Mentor's Design Checker, Atrenta's Spyclass, Aldec's Alint etc. Unfortunately these tools are not cheap but they are quit powerful and compared to the "old days" they do both static and dynamic linting (running synthesis in the background). Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.66.190.198 with SMTP id gs6mr29202357pac.4.1418044510027; Mon, 08 Dec 2014 05:15:10 -0800 (PST) X-Received: by 10.140.94.150 with SMTP id g22mr629115qge.0.1418044509978; Mon, 08 Dec 2014 05:15:09 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5942362igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4961893qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 05:15:09 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a005a45-c7a9-4443-a991-4471da18c678@googlegroups.com> Subject: Re: vhdl code review From: Chris Higgs Injection-Date: Mon, 08 Dec 2014 13:15:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7919 On Monday, December 8, 2014 9:01:11 AM UTC, alb wrote: > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. Great! It seems to have taken a while for code review to catch on for RTL development but done correctly you should find it beneficial. > Our projects are on the scale of ~100 KLOC (including testbenches) and > if the number of lines reviewed per hour presented in the book is > correct (150) it will mean that we will need to spend ~85 days in code > reviews (considering a day made out of 8 working hours)! If you view code review as a pure cost then it will never become ingrained in your process. Code review done correctly should *save* you time, though it's always difficult to quantify it should be noticeable. If you're trying to review 100 KLOC then you're very unlikely to succeed. Ideally code review should be done in parallel with development, reviewing small chunks at a time. It is probably better to focus on introducing a process for new development rather than trying to retrospectively review historical code. > Considering that best practices mandate 4 people per review (moderator, > reader. recorder, author), only review would cost one and a half > man/year! > > Am I missing something? In order to make reviews effective how can we > organize them? I think these best practices sound like they are from the 80s! It's generally accepted that review meetings generally don't work nearly so well as individual reviews. Group meetings are more suitable for architecture review where there is likely to be more discussion, but you should really try and separate the agreed architecture from the implementation review. Those reviewing the code should already be familiar with the agreed architecture. If you try putting 4 people in a room to perform a code review you it will not be very efficient (and most likely un-productive). Current software industry best-practice is for individuals to perform reviews at their own desks, using a software tool to track any discussion and actions. You asked for advice so here is mine: 1. Make code review part of the development process This is really important. Unless code review is "designed in" then it will always fall by the wayside because everybody is always too busy. The best way to achieve this is to engineer your development process. I would suggest the following: Use branches in your source control to enforce code review. Development happens on a branch, merges back onto stable are reviewed before they can be merged. You should also integrate this flow with your continuous integration such that your regression tests are run on the branch before it is merged too. Effectively you have a stable branch where to commit to it a review must have taken place and tests run. This can (and should) be enforced rather than optional. 2. Review small chunks of code If the cost of rewriting the entire chunk of code being reviewed is perceived as too high then it's too late to be doing the review. Ideally you want to keep reviews under ~500 LOC. 3. Use decent tools to assist There are plenty of free and non-free tools available (reviewboard, phabricator, crucible, even gitlab). These will track comments and discussions, report test results etc. At bare minimum you need something that ties into your source control, but there are significant benefits from integrating into your bug-tracking system and continuous integration / regression tests too. 4. Don't underestimate the cultural adjustment required Often introducing code reviews can cause difficulties. Some people don't like having flaws in their code pointed out, some people will become defensive, some people will be aggressively anal in the review. In my experience hardware engineers are more prone to rejecting the idea of code reviews than pure software engineers. The key thing to remember is that code review serves multiple purposes. It should improve the quality of your code-base. It should improve the teams familiarity with the code-base. It should improve the skill levels of all your engineers as they learn from each other. To achieve this however the code review needs to be viewed as beneficial by the engineers as well as the management! For further reading this paper has some real data and interesting commentary: http://smartbear.com/SmartBear/media/pdfs/best-kept-secrets-of-peer-code-review.pdf Pretty much everything written about software code-review will be relevant to you because at the end of the day RTL development is identical to software development... we just have much longer compile times ;) Thanks, Chris From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 8 Dec 2014 13:29:08 GMT Lines: 27 Message-ID: References: X-Trace: individual.net qrQ5Ugofz3+bVMfk4BqCnAGfb8bjVRJQQL9u0PcxlvClVQTPL5 X-Orig-Path: not-for-mail Cancel-Lock: sha1:KSVPTonggbVKgJ5RIWBr3P0piRA= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7920 Hi Hans, In article you wrote: [] > I would suggest you look into linting tools as this is the only way to > handle large amount of code. There are some really nice ones like > Mentor's Design Checker, Atrenta's Spyclass, Aldec's Alint etc. linting tools are essential in order to verify coding rules, but won't lack of synchronization, asynchronous logic complexity, race conditions, wrong initialization and all the assumptions the coder has chosen when writing the code. Moreover comments are seldom analyzed and they are an important part of the code quality. > Unfortunately these tools are not cheap but they are quit powerful and > compared to the "old days" they do both static and dynamic linting > (running synthesis in the background). I'll give a look at those since they certainly can provide a lot of useful checking that can be skimmed off the review table (essentially the build should be clean, no errors, no warnings unless justified), but there are other aspects that can't be covered with the tool and on top of my small list above I suspect there are even more. Al From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.42.52.208 with SMTP id k16mr32980711icg.23.1418048065299; Mon, 08 Dec 2014 06:14:25 -0800 (PST) X-Received: by 10.140.19.225 with SMTP id 88mr3315qgh.19.1418048065227; Mon, 08 Dec 2014 06:14:25 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no15523126igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no4972597qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 06:14:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <1ccdec9a-5f41-427e-928b-fd5297e11528@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Throughput under Quartus II From: KJ Injection-Date: Mon, 08 Dec 2014 14:14:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7921 On Sunday, December 7, 2014 9:24:53 AM UTC-5, Andy Bartlett wrote: > > "AA" > > hi, > > How to calculate the throughput in Mbps of the design under Quartus II ? > > > > Thank you, > > Use the TimeQuest timing analyzer. This will give you the maximum internal > clock rate you can run your design at. That will not give you "throughput in Mbps", it will only give you clock rate in MHz. Not at all the same thing. KJ From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 8 Dec 2014 23:32:52 GMT Lines: 251 Message-ID: References: <7a005a45-c7a9-4443-a991-4471da18c678@googlegroups.com> X-Trace: individual.net RRDuCX0/LCDqs6gEJ+6IhQPujKHo2CrBClJ5HrkWK6mUb4QhL/ X-Orig-Path: not-for-mail Cancel-Lock: sha1:6USE3KBLkqkQkKVuLxuFYCTkBU4= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7922 Hi Chris, Chris Higgs wrote: [] > Great! It seems to have taken a while for code review to catch on for RTL > development but done correctly you should find it beneficial. good to know that I'm not alone in my madness! >> Our projects are on the scale of ~100 KLOC (including testbenches) and >> if the number of lines reviewed per hour presented in the book is >> correct (150) it will mean that we will need to spend ~85 days in code >> reviews (considering a day made out of 8 working hours)! > > If you view code review as a pure cost then it will never become ingrained > in your process. Code review done correctly should *save* you time, > though it's always difficult to quantify it should be noticeable. to be ingrained in the process, management needs to be onboard, otherwise, by definition, it won't be ingrained. I'm certainly not wanting to reduce code review to a mere *cost*, but this is how some not really enlightened manager may perceive it. Moreover, technical staff as well should be the first driving force since they should see the immediate bbenefit of it and not just another burden on their shoulders. > > If you're trying to review 100 KLOC then you're very unlikely to succeed. > Ideally code review should be done in parallel with development, reviewing > small chunks at a time. It is probably better to focus on introducing a > process for new development rather than trying to retrospectively review > historical code. absolutely. The 100 KLOC is the size of a medium size project here in house and regardless of the way we integrate code review in our process at the end of the day we will still need to review it all, i.e. an extra amount of hours to budget in. >> Considering that best practices mandate 4 people per review (moderator, >> reader. recorder, author), only review would cost one and a half >> man/year! [] > It's generally accepted that review meetings generally don't work nearly > so well as individual reviews. Group meetings are more suitable for > architecture review where there is likely to be more discussion, but you > should really try and separate the agreed architecture from the > implementation review. Those reviewing the code should already be > familiar with the agreed architecture. Agreed, it is not uncommon indeed that people tend to discuss architectural choices instead of the implementation details, which invalidate the whole review and make them ineffective. A run down on the architecture should be preparatory for all the participants. We are trying to separate the verification effort completely from the development one, introducing at least two people, plus the technical coordinator who supervise the whole development, but rarely write any code. Both the verification engineer and the designer know the specifications as well as the architecture. The verification engineer could be part of the reviewers, but unfortunately his/her experience is more shaped around verification techniques. The same could be said for the RTL designer reviewing the testbench code. Asking people who are not part of the project to be educated on the architecture and the specs is a major drawback, it essentially would require the whole FPGA team to know everything about everything, which essentially is equivalent to knowing nothing about anything... :-/ [] > Current software industry best-practice is for individuals to perform > reviews at their own desks, using a software tool to track any discussion > and actions. I understand your point and I didn't think about having people sitting around a table and discussing hours about why the signal name has not been written in 'camel case'. We have formal round table reviews for hardware, with a checklist and the QA noting down any deviation, but the complexity you can get with 10M gates component is not comparable (at least in our designs the hardware is never driving the schedule) > 1. Make code review part of the development process > > This is really important. Unless code review is "designed in" then it > will always fall by the wayside because everybody is always too busy. The > best way to achieve this is to engineer your development process. I would > suggest the following: > > Use branches in your source control to enforce code review. Development > happens on a branch, merges back onto stable are reviewed before they can > be merged. By definition a ready to be integrated feature should be verified before the merging take place. If the code is already verified the code review may not be so attractive (the manager: the code is tested, why should we spend more time on it?). IMO instead, code review should take place before testing (but after elaboration *and* synthesis). IIRC effectiveness of code reviews are essentially due to the fact that a bug cost less if found early and there's no earlier than 'as soon as' the code is ready. Sometimes it costs more to run simulations that do not work because of simple bugs rather than having a pair of eyes reading the code. > You should also integrate this flow with your continuous > integration such that your regression tests are run on the branch before > it is merged too. Ok, this sentence by itself can start a whole new thread )on continuous integration), so I'll probably launch the discussion separately in the coming days. I think we've mildly talked about this in a not so distant past, but I'm still stuck where I was then (priorities are changing at a fast pace!). > Effectively you have a stable branch where to commit to it a review must > have taken place and tests run. This can (and should) be enforced rather > than optional. It's easy to enforce test runs with pre-hooks before merging onto mainstream, less evident how to force in the process the review. As said earlier the verification phase should not even start before code review is performed, but I'm asking myself if the review should be an iterative process not so different from the verification effort (test, modify, test). And when do we consider code review over? All lines of code have been reviewed, some where tagged as to be modified, some others will likely show bugs during simulation, should the code be reviewed after all the mods, along the mods? > 2. Review small chunks of code > > If the cost of rewriting the entire chunk of code being reviewed is > perceived as too high then it's too late to be doing the review. Ideally > you want to keep reviews under ~500 LOC. Divide and Conquer. The architectural phase is critical since is where we divide functions and establish their interconnections/interactions. Every functional block should also be divided in relatively manageable units which losely interact (micro architecture). Maybe we should envision multiple branches for each unit which all merge to a feature branch (that would eventually merge to the stable branch). It would be rather difficult though to break functionality with the number of lines of code as a delimiter, still I understand your idea and in practice most of our files (one entity per file) are around that number (with the exeception of testbenches which are usually longer and I believe wrongly structured!). > 3. Use decent tools to assist > > There are plenty of free and non-free tools available (reviewboard, > phabricator, crucible, even gitlab). These will track comments and > discussions, report test results etc. At bare minimum you need something > that ties into your source control, but there are significant benefits > from integrating into your bug-tracking system and continuous integration > / regression tests too. IIRC reviewboard should be easy to integrate with bugzilla, while I don't really see how to integrate it with the CI. Comments from reviewboard shall translate into bugs which should be treated before merging activities. This approach calls for somebody responsible for merging features in the trunk, verifying that no pending bugs are crawling under the carpet! > 4. Don't underestimate the cultural adjustment required > > Often introducing code reviews can cause difficulties. Some people don't > like having flaws in their code pointed out, some people will become > defensive, some people will be aggressively anal in the review. In my > experience hardware engineers are more prone to rejecting the idea of code > reviews than pure software engineers. Agreed. I see it frequently, everyone considering his/her domain the ultimate response to human struggles. I see lots of subjects which are common to both world, but even talented people often consider software practices like 'abstraction' as something to be rejected 'because I care about how many gates my code produces'. > The key thing to remember is that code review serves multiple purposes. Yet I've haven't found what should we focus on when reviewing the code. For what concerns coding rules maybe a fine tuned linting tool would solve the issue, but then? Here's my very small list off the top of my head (without no specific order): - entity interfaces types - wrongly initialized signals/variables - conditions for signals/states changes - clock domain transitions - resynchronization of asynchronous logic (if and when needed) - comments clarity - use of 'standard' functions/procedures - rewrite reused functional blocks into functions/procedures - do not discuss about architectural choices! - reasonable number of states for FSM, otherwise break in hierarchical FSM. Anything to add or to remove? > It should improve the quality of your code-base. It should improve the > teams familiarity with the code-base. It should improve the skill levels > of all your engineers as they learn from each other. To achieve this > however the code review needs to be viewed as beneficial by the engineers > as well as the management! Unfortunately too often management has rejected the idea to have a better quality code because 'it won't work better' (or at least is hard to prove). On top of it they often turn a blind eye on upfront efforts and prefers quick and dirty solution to ship in time. The lesser important argument is about skill level improvement, the answer would simply be 'not on my project'. No rational argument would be valid against such management. Still something needs to be done to improve our inability to tackle complexity at a larger scale. > For further reading this paper has some real data and interesting > commentary: http://smartbear.com/SmartBear/media/pdfs/best-kept-secrets-of-peer-code-review.pdf thanks for the link, someday I should start practice 'speed reading' to be more effective on the amount of stuff I *have to read* (it's piling up!). > Pretty much everything written about software code-review will be relevant > to you because at the end of the day RTL development is identical to > software development... we just have much longer compile times ;) Agreed and anyone rejecting the similarities because 'every flop counts' will not keep up with the increase of complexity. Even in a very conservative market like 'space', nowadays devices are monsters that allow complex SoC with multiple processors running and peripherals offloading the software stack. Willing to keep control over the register is IMO not affordable. In our house we are crazy about optimization in the very early phases, believing that if we can spare some gates on a functional block we have made the day. This approach is rather shortsighted since optimization should be looked at from a different perspective, often at system level, maybe moving functions from hardware to software, maybe rearchitecting the coupling between functions. On top of it, why optimizing a function whose impact is only 5% of the overall resource need? Donald Knuth wrote about 'premature optimization' as the 'root of all evil' and I could not agree more. Al From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.66.152.8 with SMTP id uu8mr31904758pab.24.1418093633893; Mon, 08 Dec 2014 18:53:53 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr82748qgj.7.1418093633548; Mon, 08 Dec 2014 18:53:53 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no6206544igd.0!news-out.google.com!n9ni43qai.0!nntp.google.com!w8no5594770qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 18:53:53 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> Subject: Re: vhdl code review From: Andy Injection-Date: Tue, 09 Dec 2014 02:53:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2863 X-Received-Body-CRC: 3553276090 Xref: mx02.eternal-september.org comp.lang.vhdl:7923 A couple of things we have found helpful for PL code reviews: 1. As already mentioned, a good (set of) linting tools with customized rule= s. The results from running these tools should be reviewed. This speeds up = verification of compliance to local design and coding standards.=20 2. A good IDE is immensely helpful especially when reviewing code I am not = familiar with (as an independent reviewer). They can make it easy to find o= bject definitions, etc. as well as extensive syntax highlighting (especiall= y Sigasi for VHDL). These often provide graphical and outline views, where-= used info, etc. 3. Code complexity analysis tools like SciTools Understand can help target = effective reviews commensurate with complexity/size of code. These tools al= so provide helpful graphical views of the code base. 4. Above all, invite younger, less experienced developers to reviews. This = is an excellent way for them to learn, and pays big dividends down the road= . 5. Don't forget to review constraints files, simulation/synthesis/place/rou= te logs, code/functional coverage results, etc.=20 6. Unless you have specific tools or items for which you wish to review net= lists, I don't recommend it. Reviewing log files is more cost effective. 7. Review issue tracking tool reports (types of issues found, how/when foun= d, how fixed, etc. This information is very useful for process improvement. As mentioned earlier, these are all pretty normal for experienced SW person= nel, but if your organization has not embraced the SW aspects of PL/ASIC de= velopment, much of this will seem foreign to participants and to management= . Additional training may be in order (how to prepare for and conduct code = reviews.) Andy From newsfish@newsfish Tue Dec 29 16:43:38 2015 X-Received: by 10.43.57.79 with SMTP id wf15mr1375865icb.24.1418111501692; Mon, 08 Dec 2014 23:51:41 -0800 (PST) X-Received: by 10.140.84.170 with SMTP id l39mr761qgd.33.1418111501660; Mon, 08 Dec 2014 23:51:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6279733igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no5144578qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Dec 2014 23:51:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.210.188.129; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 89.210.188.129 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL From: Nikolaos Kavvadias Injection-Date: Tue, 09 Dec 2014 07:51:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7924 Hi Gandalf and Rick, > >>> I was studying VHDL, when this thought struck me. What features do yo= u think a new microprocessor written in VHDL must possess? If this is the w= rong place to ask, kindly redirect me to the relevant group if possible. There are lots of new designs ranging from tiny micros, to DSP/VLIWs, vecto= r processors, embedded multicores etc. As a shameless plug, you can have a look at my processor, ByoRISC. ByoRISC = was conceived some ~8 years ago as a Nios-II or MIPS32 on steroids. Its des= ign is based around cheap, internal, multi-port storage for registers, the = kind of one that might be practical in FPGAs (and this depends). It is a sc= alable design (with full data forwarding from everywhere to everywhere) tha= t can be configured at compile/elaboration-time for a different maximum num= ber of read and write operands for the supported instructions. I was able t= o use it for at least up to 8 read and 8 write ports. For 8/8, MHz degradat= ion was 15-20% to a RISC-like with 2/1 read/write ports, but overall execut= ion time benefit was around 2.5x-4x for my application set (ByoRISC was bet= ter). ByoRISC is a good testbed for exercising custom instructions and stuf= fing it with additional tightly-coupled functional units. ByoRISC was also able to sustain better performance than some VLIWs, e.g. t= he HP Playdoh/VEX that I had used in experiments. Some readings:=20 http://www.nkavvadias.com/publications/kavvadias_vlsisoc08.pdf http://arxiv.org/abs/1403.6632 There was also its sister EDA tool, YARDstick for identifying custom instru= ctions (though not fully integrated into a single flow with ByoRISC develop= ment tools):=20 http://www.nkavvadias.com/yardstick/index.html The world has moved to embedded multicore of course and ByoRISC might not b= e too elemental as a brick, but it is a worthy experiment of a scalable ASI= P with performance at the 4/8-way VLIW range. Best regards Nikolaos Kavvadias http://www.nkavvadias.com > >> > >> If you want to know what features to include in a processor design, pi= ck > >> a processor suitable for the job you want to do and use those. :) > >> > >> Before you consider rolling your own processor, take a look at the > >> others out there. There are around 1000 of them so far. > >> > >> -- > >> > >> Rick > > > > Hey thanks Rick, > > I already went through the MIPS documentation and the ARM documentation= . Could you suggest me some more? >=20 > I meant that home grown CPU designs. >=20 > If you are serious about this the question is "why"? I've been down=20 > this path myself designing some number of iterations of MISC type=20 > processors. In the end it was educational, but only moderately useful.= =20 > The smallest practical processor I've seen is the picoBlaze from=20 > Xilinx, but it is not HDL, but rather done with Xilinx primitives. So=20 > in that sense my CPU was the smallest I have seen that wasn't also dog=20 > slow, but not by much. There are lots of CPUs of a wide range of sizes= =20 > all designed with different goals in mind. The question is, what is=20 > your goal? >=20 > --=20 >=20 > Rick From newsfish@newsfish Tue Dec 29 16:43:38 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 09 Dec 2014 02:51:35 -0600 Date: Tue, 09 Dec 2014 08:51:23 +0000 From: MK User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: What could be a complete redesign of a microprocessor if one wrote it in VHDL References: <76087c7254.DaveMeUK@my.inbox.com> <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> In-Reply-To: <45bec985-5545-4671-9310-6b522e4b5884@googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 27 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-q1CWcBmRsnHwZM+7YxNMNoIZNrH+NvxNBRLcaI8QF/EuYWjNfgkkQhVaPgbFULst9lyKlpzI5ySQmC1!btfc813XZWQa/wZZchN6qMe/cQnNjJG5gjegqz1fhnwDyXHyASh27qE9n8jO9Wg7Faw5c9ys9Nc= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2539 Xref: mx02.eternal-september.org comp.lang.vhdl:7925 On 08/12/2014 02:42, Gandalf wrote: > On Monday, December 8, 2014 3:54:11 AM UTC+5:30, Dave Higton wrote: >> In message >> Gandalf wrote: >> >>> I was studying VHDL, when this thought struck me. What features do you >>> think a new microprocessor written in VHDL must possess? If this is the >>> wrong place to ask, kindly redirect me to the relevant group if possible. >> >> Your question makes no sense at all. VHDL is a means to implement >> whatever features you wish. It has no limitations that would cause >> you to reduce the feature set. >> >> Dave > > Let me rephrase it- If you were to build a microprocessor today which is geared towards microcomputing platforms, what low level feature you would implement in addition to the standard PC,ALU, FPU etc. > The question still doesn't make much sense - the only two valid reasons I can imagine for developing yet another VHDL processor are: 1) because you want features that you can't get in anything else 2) for research/education In either case the required features are driving the project. Michael Kellett From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.66.142.226 with SMTP id rz2mr34138390pab.36.1418143163064; Tue, 09 Dec 2014 08:39:23 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr176260qgd.6.1418143162975; Tue, 09 Dec 2014 08:39:22 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no16217776igd.0!news-out.google.com!r1ni44qat.1!nntp.google.com!w8no5730575qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 9 Dec 2014 08:39:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.99.0.254; posting-account=sKIcugkAAADuN1jxTpi0uMTrPcQWONSB NNTP-Posting-Host: 195.99.0.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Does writeline consume the line? From: davehigton14@gmail.com Injection-Date: Tue, 09 Dec 2014 16:39:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 13 X-Received-Bytes: 1696 X-Received-Body-CRC: 1459603799 Xref: mx02.eternal-september.org comp.lang.vhdl:7926 The general process for writing to a file involves a write to a line, followed by a writeline to a file. But does the writeline consume the contents of the line? I think it does. I'm doing a multi-channel filter simulation. I'm writing the line to a Results.txt file if the channel is the active channel; then I'm writing the same line to one of eight Results.txt files according to the channel number. I was surprised to see that Results0.txt is empty when the active channel is channel 0. I infer that this means that writeline to the active channel consumes the contents of the line so that there is nothing left to write to Results0.txt. Dave From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: 9 Dec 2014 21:55:35 GMT Lines: 96 Message-ID: References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> X-Trace: individual.net zIBtDhhOuyNcSg0r3jAlownuyD8e8kEuQS9pqHl87toeRtSD/O X-Orig-Path: not-for-mail Cancel-Lock: sha1:AvjnOrcGg1P3E6axQNXp90z3pMo= User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-686 (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:7927 Hi Andy, Andy wrote: [] > 1. As already mentioned, a good (set of) linting tools with customized > rules. The results from running these tools should be reviewed. This > speeds up verification of compliance to local design and coding > standards. Having coding rules would be the first step toward a better code quality, I have always have hard time to understand why practices so well recognized are simply neglected in the name of 'lack of time'. > 2. A good IDE is immensely helpful especially when reviewing code I am > not familiar with (as an independent reviewer). They can make it easy > to find object definitions, etc. as well as extensive syntax > highlighting (especially Sigasi for VHDL). These often provide > graphical and outline views, where-used info, etc. I am pretty much accustomed with emacs and etags which help me browse the code base rather quickly. Amongst 8 people we have I guess 6 editors (moreover I'm not one of them) and each of them is religiously addicted to his preferred one (http://xkcd.com/378/). > 3. Code complexity analysis tools like SciTools Understand can help > target effective reviews commensurate with complexity/size of code. > These tools also provide helpful graphical views of the code base. Thanks for the hint, I'll give it a try on a large (and unstructured) code base to see how it can help. I heard several times that subcontracted code is a nightmare to maintain because of the lack of detailed knowledge of it. Tools like these may assist in the code analysis and in the familiarization process. Same happens when, due to workload and/or priorities, designers are brought in from nowhere and asked to *contribute* without even knowing where to start from. > 4. Above all, invite younger, less experienced developers to reviews. > This is an excellent way for them to learn, and pays big dividends > down the road. This is what's called investment...depending on the historical or emotional phases, management may be interfering a lot on this point. > 5. Don't forget to review constraints files, > simulation/synthesis/place/route logs, code/functional coverage > results, etc. To my understanding reports are already way down the road w.r.t. to code review. They certainly need to be reviewed and in our case they are also contractually required to appear in our documentation set (verification report, validation report, detailed design report...). While their importance is crucial in the intent to ship a sound project, IMO they are not part of the code itself. OTOH I do agree that constraint files need to be reviewed as code. I'd like to separate reviewing of what goes in, from what goes out. > 6. Unless you have specific tools or items for which you wish to > review net lists, I don't recommend it. Reviewing log files is more > cost effective. I've personally found netlist analysis a big PITA and I prefer to spend time in describing behavior at higher level and *verify* it works correctly. We have post-synth and post-layout sims [1] to make sure the generated netlist is behaving as expected. How could you possibly review a netlist on a 2M gates device with 92% occupancy? > 7. Review issue tracking tool reports (types of issues found, how/when > found, how fixed, etc. This information is very useful for process > improvement. Unfortunately our issue tracking tool is extremely losely configured and this type of information is extremely difficult to extract. I believe there's another whole area of improvement there. What we tend to do though is to review the bug fix ASAP in our corners and if somebody is not satisfied with the bug closure it will reopen it, asking for clarifications or additional mods. > As mentioned earlier, these are all pretty normal for experienced SW > personnel, but if your organization has not embraced the SW aspects of > PL/ASIC development, much of this will seem foreign to participants > and to management. Additional training may be in order (how to prepare > for and conduct code reviews.) Cultural inertia is certainly something that doesn't ease introduction of new philosophies and approaches. Training might be done in house and should not take too much efforts to bring people on board in small steps. If you have any extra suggestion directly related to aspects of the code beyond the ones I listed in a previous message in this thread I'd be happy to hear them. Al [1] ECSS-Q-60-02C requires full coverage of post-layout sims according to the verification plan which specifies which test covers which requirement and how. From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 09 Dec 2014 17:46:38 -0600 Date: Tue, 09 Dec 2014 23:46:38 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Does writeline consume the line? References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> Lines: 40 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-o4xbtk0BamOhVBgxMy9ORePB29VhTXzxm8gOUZNQ2AgON356Q68BjHLIEgYnBGV3NStjB2+cc1HgTpn!FoHEczghLUI0/aIPJhVIukmE2/fYN4vhoDUxgK5BJbPMqaPWPJcm2veUYxSlLqpH+G4lZJQ23Il0!w2BsvXQ5UvJFkcJDB67UW/55cVk= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2249 Xref: mx02.eternal-september.org comp.lang.vhdl:7928 On 09/12/14 16:39, davehigton14@gmail.com wrote: > The general process for writing to a file involves a write to a > line, followed by a writeline to a file. But does the writeline > consume the contents of the line? > > I think it does. I'm doing a multi-channel filter simulation. > I'm writing the line to a Results.txt file if the channel is the > active channel; then I'm writing the same line to one of eight > Results.txt files according to the channel number. I was > surprised to see that Results0.txt is empty when the active > channel is channel 0. I infer that this means that writeline > to the active channel consumes the contents of the line so that > there is nothing left to write to Results0.txt. > > Dave > Yes, writeline empties the line buffer. You can make a copy of the buffer if you know/realise that it is access string, e.g. process variable L1 : line; variable l2:: line; begin write(L1, fred); L2 := new string'(L1.all); writeline(F, L1); writeline(F2, L2); regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: vhdl code review Date: Tue, 09 Dec 2014 18:31:52 -0800 Organization: Aioe.org NNTP Server Lines: 13 Message-ID: References: NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:7929 > inspired by a nice read (the art of designing embedded systems - Jack > Ganssle) I've started wondering what's the best way to perform code > reviews for vhdl. Among the other suggestion this thread present you, I suggest you look up Fagan inspections. It's a formalized process for reviews. If your management supports allocating the resources (people) to participate, you're in a good position. We've used Fagan inspections with great results for circuit designs and C code reviews. It should work just fine for HDL inspections. JJS From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.42.52.208 with SMTP id k16mr6665092icg.23.1418199971039; Wed, 10 Dec 2014 00:26:11 -0800 (PST) X-Received: by 10.140.109.9 with SMTP id k9mr14425qgf.17.1418199970906; Wed, 10 Dec 2014 00:26:10 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6688376igd.0!news-out.google.com!r1ni15qat.1!nntp.google.com!s7no5383319qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 00:26:10 -0800 (PST) In-Reply-To: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.99.0.254; posting-account=sKIcugkAAADuN1jxTpi0uMTrPcQWONSB NNTP-Posting-Host: 195.99.0.254 References: <_dKdnQc5yqhDFBrJnZ2dnUVZ7rSdnZ2d@brightview.co.uk> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54577a10-7d42-43a2-9c3e-21d156aaef5f@googlegroups.com> Subject: Re: Does writeline consume the line? From: davehigton14@gmail.com Injection-Date: Wed, 10 Dec 2014 08:26:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7930 On Tuesday, December 9, 2014 11:46:41 PM UTC, Alan Fitch wrote: > On 09/12/14 16:39, Dave Higton wrote: > > The general process for writing to a file involves a write to a > > line, followed by a writeline to a file. But does the writeline > > consume the contents of the line? > > > > I think it does. I'm doing a multi-channel filter simulation. > > I'm writing the line to a Results.txt file if the channel is the > > active channel; then I'm writing the same line to one of eight > > Results.txt files according to the channel number. I was > > surprised to see that Results0.txt is empty when the active > > channel is channel 0. I infer that this means that writeline > > to the active channel consumes the contents of the line so that > > there is nothing left to write to Results0.txt. > > > > Dave > > > > Yes, writeline empties the line buffer. > > You can make a copy of the buffer if you know/realise that it is access > string, e.g. > > process > variable L1 : line; > variable l2:: line; > > begin > > write(L1, fred); > L2 := new string'(L1.all); > writeline(F, L1); > writeline(F2, L2); Thanks, Alan, for the confirmation, and for the simple solution. Dave From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.42.149.133 with SMTP id w5mr6614017icv.14.1418205484190; Wed, 10 Dec 2014 01:58:04 -0800 (PST) X-Received: by 10.140.101.247 with SMTP id u110mr16237qge.18.1418205484053; Wed, 10 Dec 2014 01:58:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!news.glorb.com!h15no16658782igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5396631qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 01:58:03 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=31.149.224.137; posting-account=F4r4WAoAAABE6olGH00oV5e4r70VrO8z NNTP-Posting-Host: 31.149.224.137 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Looking for expert VHDL books From: msteerefolk@gmail.com Injection-Date: Wed, 10 Dec 2014 09:58:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 14 Xref: mx02.eternal-september.org comp.lang.vhdl:7931 The past few weeks I'm often looking for information on very specific subje= cts. The more general books don't include these subjects, so I'm looking fo= r a list of specialised VHDL books. I'm currently looking specifically for books including the topics of bidire= ctional buses (most books skip this part because they're bad practice, but = they're essential for USB communication) optimizing LUTs, FPGAs and transmi= ssion protocols and more topics like that. Finding a list of beginner books is quite easy, but I'm specifically lookin= g for the higher-level reading. A few months ago I've studied Digital Signal Processing with Field Programm= able Gate Arrays (Uwe Meyer-Baese, ISBN 978-3-642-45308-3), which is exactl= y the type of book I'm looking for. Now I want more of those. From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.236.2.226 with SMTP id 62mr3047199yhf.1.1418207227338; Wed, 10 Dec 2014 02:27:07 -0800 (PST) X-Received: by 10.140.21.20 with SMTP id 20mr259qgk.30.1418207227283; Wed, 10 Dec 2014 02:27:07 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!s7no5401175qap.1!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5401172qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 02:27:07 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> Subject: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 10:27:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 24 Xref: mx02.eternal-september.org comp.lang.vhdl:7932 Good morning everyone, I am a newbie to VHDL without background in programming language. Library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Sorter IS Port ( C: IN std_logic_vector (3 downto 0); Sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; How do I declare the architecture given the condition that all the outputs of the sorter are set to Zero when Sel is different from 4 while the output = 1 if sel =4. I use Modelsim 10.3d version. Thanks From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.68.219.198 with SMTP id pq6mr3150433pbc.8.1418207427453; Wed, 10 Dec 2014 02:30:27 -0800 (PST) X-Received: by 10.140.85.134 with SMTP id n6mr16054qgd.20.1418207427405; Wed, 10 Dec 2014 02:30:27 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no16673136igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no5893592qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 02:30:27 -0800 (PST) In-Reply-To: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> Subject: Re: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 10:30:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7933 On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > Good morning everyone, > > I am a newbie to VHDL without background in programming language. > > Library ieee; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > entity Sorter IS > Port ( C: IN std_logic_vector (3 downto 0); > Sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); > out0: out std_logic; > out1: out std_logic; > out2: out std_logic; > out3: out std_logic > ); > end sorter; > > > How do I declare the architecture given the condition that all the outputs of the sorter are set to Zero when Sel is different from 4 while the output = 1 if sel =4. > > I use Modelsim 10.3d version. > > Thanks Books for beginners can also be recommended to aid my learning From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.182.92.163 with SMTP id cn3mr3669888obb.49.1418212627925; Wed, 10 Dec 2014 03:57:07 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr31390qgd.8.1418212627897; Wed, 10 Dec 2014 03:57:07 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no16724884igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no5912800qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 03:57:07 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.115.52.180; posting-account=RSDZnwoAAABlC_Dai9W9X1yTdgNRgfBu NNTP-Posting-Host: 85.115.52.180 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Subject: Is there still no elegant way to create a BFM with a transaction-level interface? From: Jon Skull Injection-Date: Wed, 10 Dec 2014 11:57:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7934 Hi VHDL fans, I've been slowly taking up the various enhancements provided in VHDL2008, a= nd I find some very useful for testbench construction, particularly generic= packages.=20 However, am I missing something, or is there still no elegant way to create= a pin-wiggling BFM driven by a transaction level (procedural) interface? Verilog has always supported this because it is possible to call a procedur= e from outside the module in which it is declared.=20 For years I've approximated this in VHDL by using an inout "transaction" re= cord port on the BFM, with some horrible bidirectional handshaking to trans= fer the transactions. I then define a package of procedures which take this= transaction record as an inout argument. I think other people use this app= roach too, but it's far from ideal as you are forced to use resolved signal= types for all of the record elements.=20 Has anyone found a better way using (supported!) VHDL2008 features? =20 Jon From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.67.14.232 with SMTP id fj8mr3654443pad.16.1418213883438; Wed, 10 Dec 2014 04:18:03 -0800 (PST) X-Received: by 10.140.84.21 with SMTP id k21mr85231qgd.6.1418213883387; Wed, 10 Dec 2014 04:18:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6770343igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5426880qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 04:18:03 -0800 (PST) In-Reply-To: <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> Subject: Re: Help with Architecture design From: Thomas Stanka Injection-Date: Wed, 10 Dec 2014 12:18:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7935 Am Mittwoch, 10. Dezember 2014 11:30:28 UTC+1 schrieb Olalekan Shittu: > On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > > Good morning everyone, > > > > I am a newbie to VHDL without background in programming language. Do you have a background in digital logic? Electronics? > > use IEEE.std_logic_arith.all; > > use IEEE.std_logic_unsigned.all; Those two libraries are not recomended to be used at all. BTW your code did not need them, you just copied without knowing why I guess. > Books for beginners can also be recommended to aid my learning I recommend to ignore in first step the fact that you could program software in VHDL (as soon as you program an compiler VHDL to executeable). You like to describe digital hardware and therefore I suggest reading in the basics of digital logic (design) unless you are familiar with descrete logic design. http://en.wikipedia.org/wiki/Register-transfer_level would be one easy point to start. Another often named (not necessary the best) is the "VHDL Cookbook" by Peter Ashden (google will find it for you). From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.66.167.231 with SMTP id zr7mr3515778pab.46.1418217532307; Wed, 10 Dec 2014 05:18:52 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr3271qgf.9.1418217532259; Wed, 10 Dec 2014 05:18:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no6799154igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5442109qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Dec 2014 05:18:52 -0800 (PST) In-Reply-To: <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.39.183.137; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 212.39.183.137 References: <7d661016-28b6-415a-ad2e-1959f9b67738@googlegroups.com> <6e168750-fc4c-4140-94fd-16cb55f3a337@googlegroups.com> <31955b00-b20a-4f30-a0a5-151e6c19752f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55e9804c-f6e1-4646-82c3-10e6de6b8844@googlegroups.com> Subject: Re: Help with Architecture design From: Olalekan Shittu Injection-Date: Wed, 10 Dec 2014 13:18:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 27 Xref: mx02.eternal-september.org comp.lang.vhdl:7936 On Wednesday, 10 December 2014 13:18:04 UTC+1, Thomas Stanka wrote: > Am Mittwoch, 10. Dezember 2014 11:30:28 UTC+1 schrieb Olalekan Shittu: > > On Wednesday, 10 December 2014 11:27:08 UTC+1, Olalekan Shittu wrote: > > > Good morning everyone, > > > > > > I am a newbie to VHDL without background in programming language. > > Do you have a background in digital logic? Electronics? Dont really have a srtong background in digital electronics > > > > use IEEE.std_logic_arith.all; > > > use IEEE.std_logic_unsigned.all; > > Those two libraries are not recomended to be used at all. BTW your code did not need them, you just copied without knowing why I guess. You are right > > > Books for beginners can also be recommended to aid my learning > > I recommend to ignore in first step the fact that you could program software in VHDL (as soon as you program an compiler VHDL to executeable). > > You like to describe digital hardware and therefore I suggest reading in the basics of digital logic (design) unless you are familiar with descrete logic design. > > http://en.wikipedia.org/wiki/Register-transfer_level > would be one easy point to start. > Another often named (not necessary the best) is the "VHDL Cookbook" by Peter Ashden (google will find it for you). From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.182.43.170 with SMTP id x10mr8472829obl.15.1418309880624; Thu, 11 Dec 2014 06:58:00 -0800 (PST) X-Received: by 10.140.106.229 with SMTP id e92mr8730qgf.29.1418309880597; Thu, 11 Dec 2014 06:58:00 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no17674921igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no5796250qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Dec 2014 06:58:00 -0800 (PST) In-Reply-To: <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Thu, 11 Dec 2014 14:58:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2523 X-Received-Body-CRC: 1789828018 Xref: mx02.eternal-september.org comp.lang.vhdl:7937 A few notes that will help you out. 1) You are trying to gate the clocks. Assuming you are expecting to learn t= o write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 = flip flops that all need a clock. Xilinx etc have put a lot of work into al= lowing a single clock to get to them all which is running at 100s of MHz. Y= ou can't put an AND gate (clock AND button press) on the clock input of a f= lip flop. The logic (LUT) in front of the flip flop will happily include fe= edback from the output of the same flip flop so that when it is clocked not= hing changes (except on the occasions when it should, of course). 2) As a result of 1) you need the button press to exist for exactly one clo= ck. VHDL code is always littered with=20 button1 <=3D button; if button1=3D'0' and button=3D'1' then --button has just been pressed and i= need to do something on this clock. 3) Someone said about having only one process, what they meant was probably= have only one clk'event although most would write "rising_edge" instead. W= ith the above in mind this is now possible. Colin (He's a beginner, lets not have a long discussion about whether synthesis w= ould unwrap the gated clock and put it where it should be(not that I have e= ver tried)). From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question pertaining to a project Date: Thu, 11 Dec 2014 23:21:51 -0500 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 04:21:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22660"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX192KTsp9GNSW0p90LX/0dAr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:jUdO1FRmpe1rcQC+g2DD/MyXgNU= Xref: mx02.eternal-september.org comp.lang.vhdl:7938 On 12/11/2014 9:58 AM, colin_toogood@yahoo.com wrote: > A few notes that will help you out. > > 1) You are trying to gate the clocks. Assuming you are expecting to learn to write code for an FPGA this is bad. Imagine you have an FPGA with 10,000 flip flops that all need a clock. Xilinx etc have put a lot of work into allowing a single clock to get to them all which is running at 100s of MHz. You can't put an AND gate (clock AND button press) on the clock input of a flip flop. The logic (LUT) in front of the flip flop will happily include feedback from the output of the same flip flop so that when it is clocked nothing changes (except on the occasions when it should, of course). I'm not sure this is true. Tell me how the synthesis tool will distinguish these two examples... 1) elsif clk'EVENT AND clk = '1' AND button_strikes ='1' then . . . end if; 2) elsif clk'EVENT AND clk = '1' then if button_strikes ='1' then . . . end if; end if; I am no expert at how the tools work, but my understanding is the logic is simplified (flattened) and then optimization happens. Is that wrong? > 2) As a result of 1) you need the button press to exist for exactly one clock. VHDL code is always littered with > button1 <= button; > if button1='0' and button='1' then --button has just been pressed and i need to do something on this clock. I believe you are describing edge detection, no? And in front of that he will need a debounce circuit. > 3) Someone said about having only one process, what they meant was probably have only one clk'event although most would write "rising_edge" instead. With the above in mind this is now possible. Yeah, one clocked process to handle the outputs. We all know what happens when you try to assign a single output from multiple processes. > Colin > (He's a beginner, lets not have a long discussion about whether synthesis would unwrap the gated clock and put it where it should be(not that I have ever tried)). Sure, I won't argue the style issue. I agree the separate IF condition for describing the edge sensitivity is best from a readability standpoint. I can't say for sure about the clock gating. I suspect the OP is gone, but perhaps he will return to glean a bit more from this topic. -- Rick From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Fri, 12 Dec 2014 00:43:52 -0500 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 05:43:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="2035"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19LAungJ7Gx2gU51U4NHrIB" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Cancel-Lock: sha1:jQbzWDh2lDji32oPrvEx1L4G98E= Xref: mx02.eternal-september.org comp.lang.vhdl:7939 On 12/10/2014 6:57 AM, Jon Skull wrote: > Hi VHDL fans, > > I've been slowly taking up the various enhancements provided in VHDL2008, and I find some very useful for testbench construction, particularly generic packages. > > However, am I missing something, or is there still no elegant way to create a pin-wiggling BFM driven by a transaction level (procedural) interface? > > Verilog has always supported this because it is possible to call a procedure from outside the module in which it is declared. > > For years I've approximated this in VHDL by using an inout "transaction" record port on the BFM, with some horrible bidirectional handshaking to transfer the transactions. I then define a package of procedures which take this transaction record as an inout argument. I think other people use this approach too, but it's far from ideal as you are forced to use resolved signal types for all of the record elements. > > Has anyone found a better way using (supported!) VHDL2008 features? Please educate me on what a BFM is? I know a BFS is a type of large screwdriver. I assume you mean some sort of an interface you wish to control via commands. I'm not sure what the problem is. I've done this many times in VHDL. I typically have a file with commands that define the action to take and the time to perform those actions. For example, an MCU interface has read and write transactions with address and data to be written on writes or verified on reads. I read a line from the file, parsed the information, waited for the time to match the simulation time and then passed the command to the function that handled bus transactions. Where is the problem? Oh, this was long before VHDL2008. -- Rick From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.236.1.201 with SMTP id 49mr11986630yhd.50.1418368525842; Thu, 11 Dec 2014 23:15:25 -0800 (PST) X-Received: by 10.140.92.176 with SMTP id b45mr9127qge.10.1418368525795; Thu, 11 Dec 2014 23:15:25 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s7no6054395qap.1!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no6054390qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 11 Dec 2014 23:15:25 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.210.188.129; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 89.210.188.129 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Nikolaos Kavvadias Injection-Date: Fri, 12 Dec 2014 07:15:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7940 Hi Rick and Jon, > Please educate me on what a BFM is? I know a BFS is a type of large=20 > screwdriver. @Rick: BFM stands for Bus Functional Model. It is an approach for modeling = .read() and .write() transactions from/to the system bus. SystemC/TLM is a = popular approach for developing BFMs and probably the right thing to do is = design a SystemC/TLM BFM and cosimulate with VHDL.=20 A BFM generation tool would be beneficial. On a second thought, ArchC (www.= archc.org) fits the bill at least partially, is open/free and has a tractab= le learning curve. It is an architecture description language for generatin= g SystemC simulators (functional and cycle-accurate) of processors, but als= o has been extended to generating models with TLM ports (e.g. for accessing= a memory via the bus), a binary utilities port, and even an LLVM compiler = backend [there is a prototype for that called accgen). So in this sense, ArchC is the closest thing to automating BFM generation s= ince you can include TLM ports in an ArchC model and generate a SystemC sim= ulator from it (and then you can tweak it according to your aim). @Jon: A VHDL package for easily designing BFM models would also be of inter= est. I don't think such thing exists, but again you can have a look at: htt= p://opencores.org/project,axi4_tlm_bfm This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Soluti= ons (www.tauhop.com). It is fairly well documented and maybe you could reus= e some of the code for your purpose. Best regards Nikolaos Kavvadias http://www.nkavvadias.com From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Fri, 12 Dec 2014 02:57:54 -0500 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 12 Dec 2014 07:57:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22794"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19l643qC3kwTS97CCLP6j88" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: <26ac7bc7-2170-4f23-b16e-753e7e0891de@googlegroups.com> Cancel-Lock: sha1:NQtH1F63mWXqqSrdGUXGadBVU1k= Xref: mx02.eternal-september.org comp.lang.vhdl:7941 On 12/12/2014 2:15 AM, Nikolaos Kavvadias wrote: > Hi Rick and Jon, > >> Please educate me on what a BFM is? I know a BFS is a type of large >> screwdriver. > > @Rick: BFM stands for Bus Functional Model. It is an approach for modeling ..read() and .write() transactions from/to the system bus. SystemC/TLM is a popular approach for developing BFMs and probably the right thing to do is design a SystemC/TLM BFM and cosimulate with VHDL. > > A BFM generation tool would be beneficial. On a second thought, ArchC (www.archc.org) fits the bill at least partially, is open/free and has a tractable learning curve. It is an architecture description language for generating SystemC simulators (functional and cycle-accurate) of processors, but also has been extended to generating models with TLM ports (e.g. for accessing a memory via the bus), a binary utilities port, and even an LLVM compiler backend [there is a prototype for that called accgen). > > So in this sense, ArchC is the closest thing to automating BFM generation since you can include TLM ports in an ArchC model and generate a SystemC simulator from it (and then you can tweak it according to your aim). > > @Jon: A VHDL package for easily designing BFM models would also be of interest. I don't think such thing exists, but again you can have a look at: http://opencores.org/project,axi4_tlm_bfm > > This is an AXI (AMBA 4.0) transactor and BFM by Daniel Kho of Tauhop Solutions (www.tauhop.com). It is fairly well documented and maybe you could reuse some of the code for your purpose. That is what I did some 15 years ago. I don't get why this is a big deal. It seems like a pretty straight forward thing to me. The only work involved was writing the code to parse the text file to drive the bus. Am I missing something? -- Rick From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.42.20.3 with SMTP id e3mr5551870icb.11.1418376880966; Fri, 12 Dec 2014 01:34:40 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr15515qgf.9.1418376880895; Fri, 12 Dec 2014 01:34:40 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no7987657igd.0!news-out.google.com!r1ni49qat.1!nntp.google.com!s7no6093483qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Dec 2014 01:34:40 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.154.109.115; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 78.154.109.115 References: <61716f60-e37e-465e-bef8-ff7a062bfd9e@googlegroups.com> <6fee568e-48de-4bf5-86be-c9b431d75102@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4f3267ee-b753-4291-b877-6266889133ea@googlegroups.com> Subject: Re: Question pertaining to a project From: "colin_toogood@yahoo.com" Injection-Date: Fri, 12 Dec 2014 09:34:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7942 Rick We will probably never know for certain, but from many years experience with new graduates it is my belief that he intended to gate the clock. I had already posted in this thread about metastability and others had already talked about debouncing. Colin From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.236.70.100 with SMTP id o64mr20491622yhd.9.1418487069077; Sat, 13 Dec 2014 08:11:09 -0800 (PST) X-Received: by 10.50.49.52 with SMTP id r20mr160369ign.8.1418487068977; Sat, 13 Dec 2014 08:11:08 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no7074832qac.0!news-out.google.com!jh1ni11954igb.0!nntp.google.com!h15no19592631igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Dec 2014 08:11:08 -0800 (PST) In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Jim Lewis Injection-Date: Sat, 13 Dec 2014 16:11:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2160 X-Received-Body-CRC: 2904953018 Xref: mx02.eternal-september.org comp.lang.vhdl:7943 Hi Jon, Still using records myself, however, ... VHDL 2008 introduces generic packages. Allows generic packages to be passe= d on entity interfaces. Allows generic instances within an architecture. = Has always allowed signals to be defined in packages. This would solve the= BFM connection, however, when calling the transaction subprogram, the subp= rogram still needs to pass the signals it needs to drive - for the time bei= ng, I plan on using a record reference for that.=20 When vendors support these features, it will offer us a feature similar to = SystemVerilog interfaces (without the concurrent region of the interface an= d modports (which allow constraint checking on who is allowed to drive whic= h signals and who is allowed to call which subprograms)).=20 I have prototypes and such. I have submitted bug reports. I need others t= o indicate they would like such features supported. =20 Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? Date: Sun, 14 Dec 2014 12:58:36 +0000 (UTC) Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sun, 14 Dec 2014 12:58:36 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="23392"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rsGHDeufa+50PaUyPZEHcmVxnIFU49Ac=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:48f21xpc3K0b1o07P6kQjxYl7Xg= Xref: mx02.eternal-september.org comp.lang.vhdl:7944 On Sat, 13 Dec 2014 08:11:08 -0800, Jim Lewis wrote: > Hi Jon, > Still using records myself, however, ... > > VHDL 2008 introduces generic packages. Allows generic packages to be > passed on entity interfaces. Allows generic instances within an > architecture. Has always allowed signals to be defined in packages. > This would solve the BFM connection, however, when calling the > transaction subprogram, the subprogram still needs to pass the signals > it needs to drive - for the time being, I plan on using a record > reference for that. > > When vendors support these features, it will offer us a feature similar > to SystemVerilog interfaces (without the concurrent region of the > interface and modports (which allow constraint checking on who is > allowed to drive which signals and who is allowed to call which > subprograms)). > > I have prototypes and such. I have submitted bug reports. I need > others to indicate they would like such features supported. > > Best Regards, > Jim If you have simple testcases ... I'd be interested to see them - or talk to Tristan. He seems to be on a roll these days. ghdl (not 0.31 but 0.32 which is in the pre-release stage, anyone can build it from source) supports enough VHDL-2008 to run OSVVM 2014.01 now. If you have a prototype or testcase requiring additional VHDL-2008 support beyond that, it would be great to get that into the next release. - Brian From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.43.78.198 with SMTP id zn6mr28826056icb.12.1418620399419; Sun, 14 Dec 2014 21:13:19 -0800 (PST) X-Received: by 10.140.27.197 with SMTP id 63mr132284qgx.6.1418620399284; Sun, 14 Dec 2014 21:13:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no10331969igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7310831qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Dec 2014 21:13:19 -0800 (PST) In-Reply-To: <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> <56fb9216-e895-4452-ae05-b80319b11823@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Andy Injection-Date: Mon, 15 Dec 2014 05:13:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2072 X-Received-Body-CRC: 1136280396 Xref: mx02.eternal-september.org comp.lang.vhdl:7945 Records work pretty well when you understand what the initializer does on a= signal or port declaration. It can be used to keep the signal benign until= /unless someone drives it. Another approach I have used is to declare a package procedure(s) with sepa= rate in/out/inout signal ports, that provides your procedural interface(s) = to the BFM.=20 Then in the process where you want to call the package procedure(s), you ca= n overload the package procedure(s) so that only pertinent, per-call info i= s passed to the local procedure(s). A procedure declared in a process can a= ccess/drive signals visible to the process without them having to be explic= itly passed to the local procedure. Just have the body of the local procedu= re call the package procedure with the full interface. Andy From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.66.155.230 with SMTP id vz6mr22496246pab.41.1418621803129; Sun, 14 Dec 2014 21:36:43 -0800 (PST) X-Received: by 10.140.95.182 with SMTP id i51mr6239qge.12.1418621802865; Sun, 14 Dec 2014 21:36:42 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no10349796igd.0!news-out.google.com!r1ni50qat.1!nntp.google.com!w8no7809830qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 14 Dec 2014 21:36:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> Subject: Re: vhdl code review From: Andy Injection-Date: Mon, 15 Dec 2014 05:36:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7946 Al, I don't recommend everyone has to use the same editor/ide, but regardless o= f the one(s) used by the developer(s), a good ide used by the reviewer is a= huge boost. I especially like sigasi, since it does not need a list of fil= es in compile order. Just point it at the directory(s) containing the sourc= e files, and it will figure it all out. Sigasi also can uniquely fontify di= fferent parts of speech (like ports, signals, variables, constants, functio= ns, types/subtypes etc.) making the code (that the reviewer did not write) = much easier to understand. IMHO, reviewing code that has not been compiled, or at least linted, is a w= aste of reviewers' time. If the code is only RTL unit level, the developer = should still synthesize it, at the unit level if necessary. It should also= be compiled into the simulator(s) to be used. The logs from these provide = useful information that can be quickly reviewed. Packages cannot be synthes= ized at the unit level, but maybe a simple test entity that uses the packag= e can be synthesized and the log files reviewed.=20 Andy From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.50.78.136 with SMTP id b8mr16756347igx.4.1418647159660; Mon, 15 Dec 2014 04:39:19 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr27146qgd.8.1418647159588; Mon, 15 Dec 2014 04:39:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no21737844igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7509460qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 04:39:19 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.178.200.133; posting-account=vuXUMwoAAADswfNzA5_BcjyTXE29RRxQ NNTP-Posting-Host: 212.178.200.133 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1582cdb4-87d7-4eb5-a35a-58fd20e5bd23@googlegroups.com> Subject: Re: Looking for expert VHDL books From: Simon Thijs de Feber Injection-Date: Mon, 15 Dec 2014 12:39:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7947 The following books I recommend : 1. The Designer's Guide to VHDL by Peter Ashenden 2. VHDL-2008, just the new stuff, by Peter Ashenden and Jim Lewis and my personal favorite 3. Embedded DSP Processor Design by Dake Liu and still very informative 4. The Design Warrior's Guide to FPGAs, by Clive Maxfield grtz ST From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.66.255.97 with SMTP id ap1mr26636911pad.1.1418667617530; Mon, 15 Dec 2014 10:20:17 -0800 (PST) X-Received: by 10.140.16.55 with SMTP id 52mr25413qga.31.1418667617437; Mon, 15 Dec 2014 10:20:17 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no22050917igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7641005qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 10:20:17 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> Subject: Total execution time in ModelSim From: AA Injection-Date: Mon, 15 Dec 2014 18:20:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: mx02.eternal-september.org comp.lang.vhdl:7948 hi, how to get the total execution time in ModelSim 14? Thank you From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!post02.fr7!fx05.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Total execution time in ModelSim References: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> In-Reply-To: <518bb7c6-80cf-458f-a70f-e296fdcbc652@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 141215-0, 15/12/2014), Outbound message X-Antivirus-Status: Clean Lines: 30 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1418669152 86.17.210.161 (Mon, 15 Dec 2014 18:45:52 UTC) NNTP-Posting-Date: Mon, 15 Dec 2014 18:45:52 UTC Organization: virginmedia.com Date: Mon, 15 Dec 2014 18:45:52 +0000 X-Received-Body-CRC: 2082777091 X-Received-Bytes: 1924 Xref: mx02.eternal-september.org comp.lang.vhdl:7949 On 15/12/2014 18:20, AA wrote: > hi, > how to get the total execution time in ModelSim 14? > > Thank you > Not sure what Modelsim 14 is but you can get all sorts of statistics using the simstats command. VSIM 2> simstats # Memory Statistics # mem: size after elab (VSZ) 106724.00 Kb # mem: size during sim (VSZ) 112988.00 Kb # Elaboration Time # elab: wall time 0.45 s # elab: cpu time 0.20 s # Simulation Time # sim: wall time 0.02 s # sim: cpu time 0.00 s # Tcl Command Time # cmd: wall time 9.24 s # cmd: cpu time 0.17 s # Total Time # total: wall time 9.70 s # total: cpu time 0.37 s # Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.182.81.74 with SMTP id y10mr30026916obx.22.1418689575735; Mon, 15 Dec 2014 16:26:15 -0800 (PST) X-Received: by 10.50.66.144 with SMTP id f16mr337895igt.1.1418689575606; Mon, 15 Dec 2014 16:26:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no11273002igd.0!news-out.google.com!jh1ni16719igb.0!nntp.google.com!h15no11272994igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 16:26:15 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.182.111.139; posting-account=W6w2ZAoAAAAeI1nFywA0Wk0a67aNeYkb NNTP-Posting-Host: 70.182.111.139 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f1687a7-5b6d-4eb0-b754-bb2839c367ec@googlegroups.com> Subject: Re: toggling an output From: weedenmatt@gmail.com Injection-Date: Tue, 16 Dec 2014 00:26:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:7950 Thank you for this answer. It was helpful to me. From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.68.95.228 with SMTP id dn4mr13062927pbb.7.1418710919442; Mon, 15 Dec 2014 22:21:59 -0800 (PST) X-Received: by 10.140.48.69 with SMTP id n63mr577qga.21.1418710919130; Mon, 15 Dec 2014 22:21:59 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no11453267igd.0!news-out.google.com!r1ni52qat.1!nntp.google.com!s7no7879428qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Dec 2014 22:21:59 -0800 (PST) In-Reply-To: <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <95b23918-ff71-4aac-856f-cdf155e87974@googlegroups.com> <28903359-06a3-4333-ba60-dec83a6fff30@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3cf36697-f932-4e61-919e-eba13a566210@googlegroups.com> Subject: Re: vhdl code review From: lars.anders.asplund@gmail.com Injection-Date: Tue, 16 Dec 2014 06:21:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:7951 I'm using unit testing when developing for VHDL and a nice side effect is t= hat it makes you review your own code in a way that you wouldn't do otherwi= se. I suspect that I find as many bugs writing these tests as I do running = them. We have released our unit testing framework for VHDL as open source o= n Github (https://github.com/LarsAsplund/vunit) and there are also other so= lutions for Verilog. Lars From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.42.88.81 with SMTP id b17mr35045260icm.2.1418724186226; Tue, 16 Dec 2014 02:03:06 -0800 (PST) X-Received: by 10.140.102.211 with SMTP id w77mr3683qge.28.1418724186153; Tue, 16 Dec 2014 02:03:06 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no22771025igd.0!news-out.google.com!r1ni53qat.1!nntp.google.com!w8no8429363qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 02:03:05 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.91.99.77; posting-account=RUFvCQoAAADIHDFMT_5SuWHKa8ch3_wO NNTP-Posting-Host: 134.91.99.77 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70bd1fec-20d2-424c-bf18-7d49bbcd6fe5@googlegroups.com> Subject: Recursive Systematic Convolution Encoder From: Muhammad Injection-Date: Tue, 16 Dec 2014 10:03:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:7952 Hi, i have to implement a turbo encoder and for that i need VHDL code of Recursive Systematic Convolution Encoder.Can any one help me thanks From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.70.140.206 with SMTP id ri14mr31206360pdb.9.1418748681116; Tue, 16 Dec 2014 08:51:21 -0800 (PST) X-Received: by 10.182.113.195 with SMTP id ja3mr9173obb.41.1418748681002; Tue, 16 Dec 2014 08:51:21 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no11865106igd.0!news-out.google.com!d20ni17812igz.0!nntp.google.com!h15no23139746igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 08:51:20 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.36 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Subject: automated converting records to std_logic_vector From: "V." Injection-Date: Tue, 16 Dec 2014 16:51:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1969 X-Received-Body-CRC: 1402634264 Xref: mx02.eternal-september.org comp.lang.vhdl:7953 Hello, First off, thank you everyone for contributing to this discussion group, it has been very helpful and informative to me as I progress with learning VHDL. I'm looking to convert a record that contains 16 std_logic types into a 16 bit std_logic_vector. I currently have a function call that manually assigns each element in the record to a specific bit location in the std_logic_vector : function rec2slv(x : rec_type) return std_logic_vector is variable result : std_logic_vector(15 downto 0) := (others => '0'); begin result(15) := x.element1; ... ... result(0) := x.element16; return result; end; === I have a large amount of records that I'd like to do this on, and it is very tedious to have to write a function for each of the record. Is there something similar to the following that could automate it? : for i in x'range loop result := x(i); end loop; Thank you all! From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.66.222.135 with SMTP id qm7mr33098697pac.20.1418758807879; Tue, 16 Dec 2014 11:40:07 -0800 (PST) X-Received: by 10.140.101.247 with SMTP id u110mr58153qge.18.1418758807825; Tue, 16 Dec 2014 11:40:07 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no12004458igd.0!news-out.google.com!r1ni57qat.1!nntp.google.com!s7no8162792qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 11:40:07 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d6e7531-768e-4f82-a6e5-569be41a115c@googlegroups.com> Subject: Re: automated converting records to std_logic_vector From: KJ Injection-Date: Tue, 16 Dec 2014 19:40:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3575 X-Received-Body-CRC: 1243375568 Xref: mx02.eternal-september.org comp.lang.vhdl:7954 On Tuesday, December 16, 2014 11:51:23 AM UTC-5, V. wrote: >=20 > I'm looking to convert a record that contains 16 std_logic types into a 1= 6=20 > bit std_logic_vector. I currently have a function call that manually assi= gns=20 > each element in the record to a specific bit location in the std_logic_ve= ctor :=20 There is no way to iterate through the elements of a record, so what you ar= e doing is basically the way it needs to be done. However, to decrease the= tedium a bit, if you define the record in the right fashion you can make i= t so an editor macro can munch on it and produce the functions quick enough= . What I do is to define the record like this... type t_IMG_DMA_IMG_SIZE is record Reserved1: std_ulogic_vector(31 downto 28); HSize: std_ulogic_vector(27 downto 16); Reserved2: std_ulogic_vector(15 downto 12); VSize: std_ulogic_vector(11 downto 0); end record t_IMG_DMA_IMG_SIZE; Then create functions that convert between the record and a std_ulogic_vect= or like this... function To_Std_ULogic_Vector(L: t_IMG_DMA_IMG_SIZE) return std_ulogic_= vector is variable RetVal: std_ulogic_vector(31 downto 0); begin RetVal(L.Reserved1'range) :=3D L.Reserved1; RetVal(L.HSize'range) :=3D L.HSize; RetVal(L.Reserved2'range) :=3D L.Reserved2; RetVal(L.VSize'range) :=3D L.VSize; return(RetVal); end function To_Std_ULogic_Vector; function From_Std_ULogic_Vector(L: std_ulogic_vector(31 downto 0)) retu= rn t_IMG_DMA_IMG_SIZE is variable RetVal: t_IMG_DMA_IMG_SIZE; begin RetVal :=3D ( Reserved1 =3D> L(RetVal.Reserved1'range), HSize =3D> L(RetVal.HSize'range), Reserved2 =3D> L(RetVal.Reserved2'range), VSize =3D> L(RetVal.VSize'range) ); return(RetVal); end function From_Std_ULogic_Vector; Note that the functions themselves do not need to be edited if all you do i= s change the bit positions. In that situation, you simply edit the record = definition. If you have one bit fields, you simply define them as one bit = vectors like this xyz: std_ulogic_vector(28 downto 28); Adding/removing a field from the record does require function editing. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:39 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: automated converting records to std_logic_vector Date: Tue, 16 Dec 2014 12:29:36 -0800 Organization: Highland Technology, Inc. Lines: 164 Message-ID: <20141216122936.1aaf935f@rg.highlandtechnology.com> References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="b789ea9a1fdbea3e4581bf19a1fd4beb"; logging-data="32208"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/yr1rVCsn0sdRl1BBDvS9S" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:DvPbzGUDY1vv5mWB7eOoyIyp7Lk= Xref: mx02.eternal-september.org comp.lang.vhdl:7955 On Tue, 16 Dec 2014 08:51:20 -0800 (PST) "V." wrote: > Hello, > > First off, thank you everyone for contributing to this discussion group, it has been very helpful and informative to me as I progress with learning VHDL. > > > I'm looking to convert a record that contains 16 std_logic types into a 16 bit std_logic_vector. I currently have a function call that manually assigns each element in the record to a specific bit location in the std_logic_vector : > > > function rec2slv(x : rec_type) return std_logic_vector is > variable result : std_logic_vector(15 downto 0) := (others => '0'); > begin > result(15) := x.element1; > ... > ... > result(0) := x.element16; > > return result; > end; > > > === > > > I have a large amount of records that I'd like to do this on, and it is very tedious to have to write a function for each of the record. > > Is there something similar to the following that could automate it? : > > for i in x'range loop > result := x(i); > end loop; > > > Thank you all! Not really. I wrote pack/unpack functions that I get a lot of use of when I have to cast a record type into an SLV, usually because I have to work with some generated core. Then I wind up writing functions for each direction as: function TO_SLV(rec : t_pvme_request) return t_pvme_request_slv is variable slv : t_pvme_request_slv; variable idx : integer; begin slv := (others => 'U'); idx := 0; pack(slv, idx, rec.data); pack(slv, idx, rec.address); pack(slv, idx, rec.timing); pack(slv, idx, rec.am); pack(slv, idx, rec.dm); pack(slv, idx, rec.req); return slv; end function TO_SLV; function TO_REQUEST (slv : t_pvme_request_slv) return t_pvme_request is variable rec : t_pvme_request; variable idx : integer; begin idx := 0; unpack(slv, idx, rec.data); unpack(slv, idx, rec.address); unpack(slv, idx, rec.timing); unpack(slv, idx, rec.am); unpack(slv, idx, rec.dm); unpack(slv, idx, rec.req); return rec; end function TO_REQUEST; I'll put all my overloads on the pack/unpack functions here in case anyone ever wants them. ----------------------------------------------------------------------- -- Record conversion functions ----------------------------------------------------------------------- procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in std_logic_vector ) is begin target(idx + nd'length - 1 downto idx) := nd; idx := idx + nd'length; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in std_logic ) is begin target(idx) := nd; idx := idx + 1; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in unsigned ) is begin target(idx + nd'length - 1 downto idx) := STD_LOGIC_VECTOR(nd); idx := idx + nd'length; end procedure pack; procedure pack( target : inout std_logic_vector; idx : inout integer; nd : in signed ) is begin target(idx + nd'length - 1 downto idx) := STD_LOGIC_VECTOR(nd); idx := idx + nd'length; end procedure pack; ---------------------------------------------------------------------- procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out std_logic_vector ) is begin dat := source(idx + dat'length - 1 downto idx); idx := idx + dat'length; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out std_logic ) is begin dat := source(idx); idx := idx + 1; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out unsigned ) is begin dat := UNSIGNED(source(idx + dat'length - 1 downto idx)); idx := idx + dat'length; end procedure unpack; procedure unpack ( source : in std_logic_vector; idx : inout integer; dat : out signed ) is begin dat := SIGNED(source(idx + dat'length - 1 downto idx)); idx := idx + dat'length; end procedure unpack; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.50.66.37 with SMTP id c5mr5150166igt.4.1418782955495; Tue, 16 Dec 2014 18:22:35 -0800 (PST) X-Received: by 10.140.93.17 with SMTP id c17mr286qge.26.1418782955338; Tue, 16 Dec 2014 18:22:35 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no23550387igd.0!news-out.google.com!r1ni59qat.1!nntp.google.com!n8no125118qaq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Dec 2014 18:22:35 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: automated converting records to std_logic_vector From: KJ Injection-Date: Wed, 17 Dec 2014 02:22:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 15 X-Received-Bytes: 1784 X-Received-Body-CRC: 1771948397 Xref: mx02.eternal-september.org comp.lang.vhdl:7956 Actually, there is another way for your particular case. Your case happens to have 16 named bits that you want to turn into a vector. Instead of a record then you can use an enumerated type. Type mytype is (element1, element2, ... element16); Type arr_mytype is array (mytype) of std_ulogic; Then you would refer to elements as x(element1) instead of x.element1. More important though you can iterate through the enumerations with For i in mytype loop Sulv(mytype'pos(i) := Inp(i); End loop; Where Inp is of type mytype, Sulv is the output std_ulogic_vector. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:39 2015 X-Received: by 10.68.68.173 with SMTP id x13mr35499441pbt.6.1418828182158; Wed, 17 Dec 2014 06:56:22 -0800 (PST) X-Received: by 10.140.81.169 with SMTP id f38mr871909qgd.3.1418828181902; Wed, 17 Dec 2014 06:56:21 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no24087401igd.0!news-out.google.com!r1ni62qat.1!nntp.google.com!s7no8490943qap.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Dec 2014 06:56:21 -0800 (PST) In-Reply-To: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: automated converting records to std_logic_vector From: Chris Higgs Injection-Date: Wed, 17 Dec 2014 14:56:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 19 Xref: mx02.eternal-september.org comp.lang.vhdl:7957 On Tuesday, December 16, 2014 4:51:23 PM UTC, V. wrote: > I'm looking to convert a record that contains 16 std_logic types > into a 16 bit std_logic_vector. I currently have a function call > that manually assigns each element in the record to a specific > bit location in the std_logic_vector Sadly as other contributors have mentioned there's no way to do this without explicitly rolling your own pack/unpack functions for each record type. There is however a proposal for the next VHDL revision to add functionality that would remove the need to write functions that are specific to each record: http://www.eda.org/twiki/bin/view.cgi/P1076/RecordIntrospection Thanks, Chris From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.224.46.7 with SMTP id h7mr3225967qaf.2.1418934896322; Thu, 18 Dec 2014 12:34:56 -0800 (PST) X-Received: by 10.50.143.102 with SMTP id sd6mr89170igb.13.1418934896222; Thu, 18 Dec 2014 12:34:56 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no347210qae.0!news-out.google.com!h6ni1784igv.0!nntp.google.com!h15no25331764igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Dec 2014 12:34:55 -0800 (PST) In-Reply-To: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.151.61; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.151.61 References: <8e81fec4-bf1d-47c1-a84c-02aa3b598178@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Is there still no elegant way to create a BFM with a transaction-level interface? From: Daniel Kho Injection-Date: Thu, 18 Dec 2014 20:34:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2891 X-Received-Body-CRC: 1044522406 Xref: mx02.eternal-september.org comp.lang.vhdl:7958 On Wednesday, 10 December 2014 19:57:11 UTC+8, Jon Skull wrote: > Hi VHDL fans, >=20 > I've been slowly taking up the various enhancements provided in VHDL2008,= and I find some very useful for testbench construction, particularly gener= ic packages.=20 >=20 > However, am I missing something, or is there still no elegant way to crea= te a pin-wiggling BFM driven by a transaction level (procedural) interface? >=20 > Verilog has always supported this because it is possible to call a proced= ure from outside the module in which it is declared.=20 >=20 > For years I've approximated this in VHDL by using an inout "transaction" = record port on the BFM, with some horrible bidirectional handshaking to tra= nsfer the transactions. I then define a package of procedures which take th= is transaction record as an inout argument. I think other people use this a= pproach too, but it's far from ideal as you are forced to use resolved sign= al types for all of the record elements.=20 >=20 > Has anyone found a better way using (supported!) VHDL2008 features? =20 >=20 > Jon As Nikolaos pointed out, do take a look at the AXI4 TLM/BFM project on Open= Cores. If you're not into AXI, you still can reuse some of the packages fro= m there. I've written it in a very reusable way - the pkg-tlm.vhdl generic = package can even be reused without any changes (possibly minor changes, if = you would) for any other protocol. The pkg-axi-tlm.vhdl is an instance of t= his generic package, so you can create other instances for other protocols. The project even uses OS-VVM to do coverage-driven constrained randomisatio= n of test vectors. Cheers, dan From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.68.112.66 with SMTP id io2mr3314450pbb.2.1418936699250; Thu, 18 Dec 2014 13:04:59 -0800 (PST) X-Received: by 10.50.43.199 with SMTP id y7mr91744igl.3.1418936698946; Thu, 18 Dec 2014 13:04:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no13632179igd.0!news-out.google.com!d20ni19676igz.0!nntp.google.com!h15no13632163igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 18 Dec 2014 13:04:58 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.106.151.61; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.106.151.61 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL 2008 support in Modelsim? From: Daniel Kho Injection-Date: Thu, 18 Dec 2014 21:04:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2672 X-Received-Body-CRC: 3044519012 Xref: mx02.eternal-september.org comp.lang.vhdl:7959 On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote: > On 05/12/2014 12:48, Anssi Saari wrote: > > > > Is Modelsim still not implementing VHDL 2008? I have some code with the > > "new" if ... generate with else branch but Modelsim 10.1e doesn't seem > > to support that. Or is it just that the Altera's Starter Edition doesn't > > support that? I don't have a Modelsim PE or SE installed right now... I > > tried case in generate as well but it didn't work any better. > > Modelsim 10.1e was released in June of 2013. Your code compiled OK in > the latest 10.3d release. > > Modelsim SE is an obsolete product and replaced by Questa core. > > Regards, > Hans > www.ht-lab.com > > > > > > > Example code, vcom -2008 says > > ** Error: generate_prob.vhdl(20): near "else": syntax error > > (line 20 is the else generate line.) > > > > LIBRARY ieee; > > USE ieee.std_logic_1164.ALL; > > > > entity dummy is > > generic ( > > some_boolean_generic : boolean := false); > > port( > > clk : in std_logic; > > reset_n : in std_logic; > > dout : out std_logic > > ); > > end dummy; > > > > architecture dummy_arch of dummy is > > > > begin > > > > some_label: if some_boolean_generic = false generate > > dout <= '0'; > > else generate > > dout <= '1'; > > end generate some_label; > > > > end dummy_arch; > > The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website. -dan From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Spectral Purity Measurement Date: Fri, 19 Dec 2014 10:06:50 -0500 Organization: A noiseless patient Spider Lines: 16 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 15:06:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d24b6b05896a8cf9cfa56f7a9e385806"; logging-data="4375"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XoiGiLmqGkKI69qEe99R3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 Cancel-Lock: sha1:9RNXTwzfxB9VvmzGNPwgHgwNgXo= Xref: mx02.eternal-september.org comp.dsp:52874 comp.lang.vhdl:7960 I want to analyze the output of a DDS circuit and am wondering if an FFT is the best way to do this. I'm mainly concerned with the "close in" spurs that are often generated by a DDS. My analysis of the errors involved in the sine generation is that they will be on the order of 1 ppm which I believe will be -240 dBc. Is that right? Sounds far too easy to get such good results. I guess I'm worried that it will be hard to measure such low levels. Any suggestions? I'll be coding both the implementation and the measurement code. The implementation will be synthesizable and the measurement code will not. I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating point. -- Rick From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 12:24:53 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 12:24:53 -0600 Lines: 56 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-XK3Ec4uWRHiQvww7P5yCDGVyCZK3V8F3XyNLI2IzjalJii9nACWyz6j/bE92Ssjv987RI3EYscXVQd0!ZprrZ6PfaFIZ0smxZWzLPV4jZrucn21PJyv9UoPwb63g1727rab6yxz9pWVdN04+zuVGuw/25rYd X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4026 X-Received-Bytes: 4138 X-Received-Body-CRC: 2151817098 Xref: mx02.eternal-september.org comp.dsp:52878 comp.lang.vhdl:7961 On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. If you mean a real circuit and not an FPGA configuration, and if you have any analog components in there, then you need to measure the thing with a spectrum analyzer. No spectrum analyzer in the world has a 240dB dynamic range, so you'd need to notch out the carrier with something absurdly deep and narrow-band, like a crystal filter. Measuring spurs down to that level would be a significant challenge for an experienced RF engineer -- I don't know that I could, or if I'd trust my results without double- checking from someone who did it every day. Even if you're measuring this numerically I think you need to do some careful and close analysis of whatever method you choose. An FFT that short will only be good to -240dBc if it collects an exact integer number of samples -- if it collects more or less, the artifacts from truncating the series will overwhelm any real effects. -240dBc implies 40 bits of precision, so you'll need to be sure that the error build-up in your FFT (or whatever) doesn't exceed that. You're talking a 12-stage FFT, and double-precision floating point has a 52-bit mantissa, so if everything stacks up wrong you've just blown your error budget. Such errors tend to be smeared out rather than to build up -- but you need to check with analysis to be sure. If you can, it may be best to generate a file of DDS outputs, and then do the analysis in some separate package like Scilab, Octave or Matlab. Even there, however, I would be concerned about the needed precision, and I'd seriously consider finding an FFT package that is, or can be compiled to, a quad-precision version. All of this really makes me want to ask _why_ -- if you're working in some application where you need to keep your DDS that spectrally pure, then chances are good that even with an absolutely perfect DDS, you're already screwed. You may want to review how well this thing is going to work when your input signal has noise, and has the inevitable distortion that comes from being measured by analog components. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.66.229.66 with SMTP id so2mr7106784pac.15.1419015877027; Fri, 19 Dec 2014 11:04:37 -0800 (PST) X-Received: by 10.140.33.229 with SMTP id j92mr59366qgj.7.1419015876978; Fri, 19 Dec 2014 11:04:36 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no26285714igd.0!news-out.google.com!r1ni76qat.1!nntp.google.com!dc16no333231qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 11:04:36 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.173.34 References: <7d8a83e9-b3fe-4c85-8eb7-121fb881e52f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9a8c82b3-6bbc-41c0-af8c-2549e721d77d@googlegroups.com> Subject: Re: automated converting records to std_logic_vector From: "V." Injection-Date: Fri, 19 Dec 2014 19:04:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2124 X-Received-Body-CRC: 3565825025 Xref: mx02.eternal-september.org comp.lang.vhdl:7962 On Tuesday, December 16, 2014 8:22:38 PM UTC-6, KJ wrote: > Actually, there is another way for your particular case. Your case happens to have 16 named bits that you want to turn into a vector. Instead of a record then you can use an enumerated type. > > Type mytype is (element1, element2, ... element16); > > Type arr_mytype is array (mytype) of std_ulogic; > > Then you would refer to elements as x(element1) instead of x.element1. > > More important though you can iterate through the enumerations with > For i in mytype loop > Sulv(mytype'pos(i) := Inp(i); > End loop; > > Where Inp is of type mytype, Sulv is the output std_ulogic_vector. > > Kevin Jennings Thanks Kevin ... Yes, that will work for about half of my records, which is good news! Unfortunately the other half contains a mix of logic types that won't play as nicely. Thank you Chris for the link, glad to know it's been brought up before. From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!not-for-mail Date: Fri, 19 Dec 2014 21:38:52 +0000 From: Andy Botterill User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Lines: 22 Message-ID: <54949aec$0$12285$bed64819@gradwell.net> NNTP-Posting-Host: 93d8898e.gradwell.net X-Trace: DXC=I7YdnIH]<00M:5lSP^d;@;aEW\3OJZ9Z3Po1k6Q\Tjc?NWPO_8o@]:>OT6Q0a]eYD2`mdDhe]3nh<5J0h1k;Ekc42;ZeR9iQSl0 X-Complaints-To: abuse@gradwell.net X-Received-Bytes: 1817 X-Received-Body-CRC: 87750330 Xref: mx02.eternal-september.org comp.dsp:52881 comp.lang.vhdl:7963 -240dbc is a very low signal level and will be below the noise floor of the environment being tested in. With a good spectrum analyser you may get down to -160dbm. Are you really sure about the power level. Compare with http://www.rohde-schwarz.co.uk/en/product/fsu-productstartpage_63493-7993.html On 19/12/14 15:06, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. > From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 19 Dec 2014 17:22:14 -0500 Organization: Alacron, Inc. Lines: 31 Message-ID: References: <54949aec$0$12285$bed64819@gradwell.net> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 22:23:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="18354"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ldMKpInUGy1sZuhnASOiAXEUBEtkAfm0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <54949aec$0$12285$bed64819@gradwell.net> Cancel-Lock: sha1:Da6CwU22INw+IrvhRFj0f8Vwuro= Xref: mx02.eternal-september.org comp.dsp:52882 comp.lang.vhdl:7964 Andy Botterill wrote: > -240dbc is a very low signal level and will be below the noise floor of > the environment being tested in. With a good spectrum analyser you may > get down to -160dbm. Are you really sure about the power level. > > Compare with > http://www.rohde-schwarz.co.uk/en/product/fsu-productstartpage_63493-7993.html > > > On 19/12/14 15:06, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. The implementation will be synthesizable and the >> measurement code will not. I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. >> > Are decibels used differently for dBc than for other usages? I would have thought that 6 orders of magnitude (1 ppm) was -120 dB not -240 dB 20 * log10 (10**-6) = 20 * -6 = -120 -- Gabor From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 17:10:32 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54949aec$0$12285$bed64819@gradwell.net> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 17:10:32 -0600 Lines: 47 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-SWXI3+HkivnzplC8Od11LuU4k2dsVIXh76YzxWKBrLDftgULpiKHzn0OiJv2lOs3nCuHIdvov28sV6J!P0CJLTv/dAI99vd4nrT/+vuCTZpohgKDwX5iabmHqzZv9W11W/5Za50Zk93ax6L30fzTcjGRCdhj X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3213 X-Received-Bytes: 3325 X-Received-Body-CRC: 3255967788 Xref: mx02.eternal-september.org comp.dsp:52883 comp.lang.vhdl:7965 On Fri, 19 Dec 2014 17:22:14 -0500, GaborSzakacs wrote: > Andy Botterill wrote: >> -240dbc is a very low signal level and will be below the noise floor of >> the environment being tested in. With a good spectrum analyser you may >> get down to -160dbm. Are you really sure about the power level. >> >> Compare with >> http://www.rohde-schwarz.co.uk/en/product/fsu- productstartpage_63493-7993.html >> >> >> On 19/12/14 15:06, rickman wrote: >>> I want to analyze the output of a DDS circuit and am wondering if an >>> FFT is the best way to do this. I'm mainly concerned with the "close >>> in" spurs that are often generated by a DDS. My analysis of the >>> errors involved in the sine generation is that they will be on the >>> order of 1 ppm which I believe will be -240 dBc. Is that right? >>> Sounds far too easy to get such good results. I guess I'm worried >>> that it will be hard to measure such low levels. >>> >>> Any suggestions? I'll be coding both the implementation and the >>> measurement code. The implementation will be synthesizable and the >>> measurement code will not. I'm thinking a fairly large FFT, 2048 or >>> maybe 4096 bins in floating point. >>> >>> >> > Are decibels used differently for dBc than for other usages? I would > have thought that 6 orders of magnitude (1 ppm) was -120 dB not -240 dB > 20 * log10 (10**-6) = 20 * -6 = -120 No, Rick made an arithmetic mistake, or he doubled his dB twice. And I didn't notice in my posting where I went on and on about the difficulty of verifying -240dBc, and the uselessness thereof. (-120dBc is still exceedingly hard to achieve in analog-land, and not necessarily useful in digital-land unless your goal is to be so damned good that you never have to worry about that being the source of your problems). dBc simply means "dB referenced to the carrier", so a signal that's -20dBc is 1/10th the amplitude, and 1/100th the power, of the carrier. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 19 Dec 2014 18:19:24 -0500 Organization: A noiseless patient Spider Lines: 51 Message-ID: References: Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 19 Dec 2014 23:19:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e1858bee1a7b8abf48ddd79e9de335b2"; logging-data="31810"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/LyonnfrUWzQrK3tpXIu+3" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:xD71z9TdmTmTK/20WByIsIIpfYE= Xref: mx02.eternal-september.org comp.dsp:52884 comp.lang.vhdl:7966 On 12/19/14 10:06 AM, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. i still get the concepts of DDS and NCO mixed up. what are the differences? is this a circuit with an analog output? or are you looking at the stream of samples before they get to the D/A converter? > My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too easy > to get such good results. I guess I'm worried that it will be hard to > measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. okay so you're at the samples before they're output to the D/A. instead of, i presume windowing with a decent window (like a Kaiser, but a Hamming might do in a pinch), using the FFT and looking for how clean the spike is, i would suggest a notch filter tuned to the frequency that you *know* is coming out of the NCO because you know the phase increment. or is this DDS generated differently than an NCO, like using some recursion equation? anyway, whatever comes out of that precisely-tuned, narrowband notch filter is the error signal. if there are spurs or whatever distortion, it will be in that notch filter output. > The implementation will be synthesizable and the > measurement code will not. i dunno what synthesizable code is. > I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. i wouldn't bother with the FFT unless you want to run it on the notch filter output. if you have an FFT in your toolbag, it sounds like your code is floating point. is that the case? because with "vhdl", that sounds like it might be a fixed-point architecture. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 19 Dec 2014 18:19:57 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Fri, 19 Dec 2014 18:19:58 -0600 Lines: 64 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-7QH/pWGcbnxd5UWQvCTN0EPZQhtWXMOtP91c8jnHCJ3z58KnIFfGJ39o3+aqO7p3jfhfaJXX0L+Aw6s!RXn+9siOTxRJK2jQvijpiX366FN0SX1l6iOtjjJHK+AQuyZChj+AMBVDMFtGE/Kp62f4hogA8JMH X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3844 X-Received-Bytes: 3956 X-Received-Body-CRC: 3173327248 Xref: mx02.eternal-september.org comp.dsp:52885 comp.lang.vhdl:7967 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: > On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. > > i still get the concepts of DDS and NCO mixed up. what are the > differences? > > is this a circuit with an analog output? or are you looking at the > stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > > okay so you're at the samples before they're output to the D/A. instead > of, i presume windowing with a decent window (like a Kaiser, but a > Hamming might do in a pinch), using the FFT and looking for how clean > the spike is, i would suggest a notch filter tuned to the frequency that > you *know* is coming out of the NCO because you know the phase > increment. or is this DDS generated differently than an NCO, like using > some recursion equation? anyway, whatever comes out of that > precisely-tuned, narrowband notch filter is the error signal. if there > are spurs or whatever distortion, it will be in that notch filter > output. > >> The implementation will be synthesizable and the measurement code will >> not. > > i dunno what synthesizable code is. Synthesizable code is code that the tool knows how to make into FPGA firmware. HDL projects generally have both a hardware description component which is synthesizable (or at least one fervently hopes) and a test component which generally is not. The tools will simulate the whole design under the control of the test component. >> I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating >> point. > > i wouldn't bother with the FFT unless you want to run it on the notch > filter output. if you have an FFT in your toolbag, it sounds like your > code is floating point. is that the case? because with "vhdl", that > sounds like it might be a fixed-point architecture. The test component can have floating point. For that matter, FPGAs are big enough to support code bloat these days; it's not unheard of to have floating-point math on them, although I think that fixed-point math is still the most common. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.236.63.6 with SMTP id z6mr8337536yhc.47.1419041798503; Fri, 19 Dec 2014 18:16:38 -0800 (PST) X-Received: by 10.140.87.68 with SMTP id q62mr1037qgd.8.1419041798486; Fri, 19 Dec 2014 18:16:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!dc16no413284qab.1!news-out.google.com!r1ni87qat.1!nntp.google.com!v10no12704qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 18:16:38 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 02:16:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2260 X-Received-Body-CRC: 620307632 Xref: mx02.eternal-september.org comp.lang.vhdl:7968 On Friday, December 19, 2014 10:07:02 AM UTC-5, rickman wrote: > > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. > I've posted some notes to comp.arch.fpga about this on occasion; the following post provides some analysis examples and links to modeling software: https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J > > I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating point. > Typically you'll need a much bigger FFT than that to see the close in stuff, the dds_oddities.pdf examples from the above links used variable sizes up to 2 Mpoints. Another difficulty in seeing these close in spurs with an FFT is that the "Grand Repetition Period" of a DDS with a large phase accumulator is so long that brute force FFT analysis of the whole truncation/quantization sequence is practically impossible. You can make some headway on this (for certain sequences) by precessing the phase of the DDS to near one of the truncation transients such that the transient occurs midway through the FFT input record. -Brian From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.66.179.140 with SMTP id dg12mr8727377pac.9.1419042412421; Fri, 19 Dec 2014 18:26:52 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr40qgf.9.1419042412368; Fri, 19 Dec 2014 18:26:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no26487250igd.0!news-out.google.com!r1ni76qat.1!nntp.google.com!dc16no414694qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Dec 2014 18:26:52 -0800 (PST) In-Reply-To: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 02:26:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 23 X-Received-Bytes: 2014 X-Received-Body-CRC: 81075505 Xref: mx02.eternal-september.org comp.lang.vhdl:7969 Earlier, I wrote: > > I've posted some notes to comp.arch.fpga about this > on occasion; the following post provides some analysis > examples and links to modeling software: > > https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J > Updated location of the broken link[2] from that old post: https://sites.google.com/site/fpgastuff/dds_oddities.pdf " "[1] close in DDS phase noise artifacts: " http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350 " "[2] plots of DDS spur pileups ( modeling numeical spurs only ) " http://members.aol.com/fpgastuff/dds_oddities.pdf " "[3] related posts about the pdf file in [2] " http://groups.yahoo.com/group/spectrumanalyzer/message/1027 " http://groups.yahoo.com/group/spectrumanalyzer/message/1038 " -Brian From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 04:04:06 GMT Organization: Anchor Hill Communications Lines: 67 Message-ID: <5494f4a1.456409145@news.eternal-september.org> References: Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="18383"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jWvDY9Z2Tv08UlwQ1bXiA2RsDAX6LGpI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141219-1, 12/19/2014), Outbound message Cancel-Lock: sha1:jmvzmeg1Yo3BWMV5/pyVM6ea1YU= Xref: mx02.eternal-september.org comp.dsp:52887 comp.lang.vhdl:7970 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: >On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences? One is spelled DDS and the other is spelled NCO. They're basically the same thing, like 4WD and AWD. The difference is mostly marketing. ;) >is this a circuit with an analog output? or are you looking at the >stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too easy >> to get such good results. I guess I'm worried that it will be hard to >> measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > >okay so you're at the samples before they're output to the D/A. instead >of, i presume windowing with a decent window (like a Kaiser, but a >Hamming might do in a pinch), using the FFT and looking for how clean >the spike is, i would suggest a notch filter tuned to the frequency that >you *know* is coming out of the NCO because you know the phase >increment. or is this DDS generated differently than an NCO, like using >some recursion equation? anyway, whatever comes out of that >precisely-tuned, narrowband notch filter is the error signal. if there >are spurs or whatever distortion, it will be in that notch filter output. > >> The implementation will be synthesizable and the >> measurement code will not. > >i dunno what synthesizable code is. Hardware Description Language that can be synthesized to gates or other hardware. >> I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > >i wouldn't bother with the FFT unless you want to run it on the notch >filter output. if you have an FFT in your toolbag, it sounds like your >code is floating point. is that the case? because with "vhdl", that >sounds like it might be a fixed-point architecture. > > >-- > >r b-j rbj@audioimagination.com > >"Imagination is more important than knowledge." > > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 01:54:52 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 20 Dec 2014 06:54:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14745"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18F4sgmw0MgDbooXlByH7+N" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:Z1xBZpsst788l902l6G6ShpgRcc= Xref: mx02.eternal-september.org comp.lang.vhdl:7971 On 12/19/2014 9:26 PM, Brian Davis wrote: > Earlier, I wrote: >> >> I've posted some notes to comp.arch.fpga about this >> on occasion; the following post provides some analysis >> examples and links to modeling software: >> >> https://groups.google.com/forum/#!msg/comp.arch.fpga/MAyeKC9SRDI/H9vE28kvuF0J >> > > Updated location of the broken link[2] from that old post: > https://sites.google.com/site/fpgastuff/dds_oddities.pdf > " > "[1] close in DDS phase noise artifacts: > " http://groups.google.com/group/comp.arch.fpga/msg/0b1a2f345aa1c350 > " > "[2] plots of DDS spur pileups ( modeling numeical spurs only ) > " http://members.aol.com/fpgastuff/dds_oddities.pdf > " > "[3] related posts about the pdf file in [2] > " http://groups.yahoo.com/group/spectrumanalyzer/message/1027 > " http://groups.yahoo.com/group/spectrumanalyzer/message/1038 > " Thank you for the references. The PDF file was especially interesting with all the plots of effects of PT and AQ. Just curious, what is up with the AOL thing? I couldn't view the link without joining. What good is posting content people can't view? -- Rick From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 11:05:54 +0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 20 Dec 2014 11:05:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="9827"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19MX9kUUo8XMUBZDUXgVtEstbpXI2mmbQM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:qsFCK9UIPj1wu338MNAPFMoWouY= Xref: mx02.eternal-september.org comp.dsp:52888 comp.lang.vhdl:7972 On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. 1ppm would be 120dBc, surely... (20 bits) I believe you can subtract an ideal signal, then FFT the remainder. You may also want to downconvert to a relatively low frequency so that you can get a decent bin spacing to examine close-in spurs. - Brian From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: N0Spam@daqarta.com (Bob Masta) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 13:29:15 GMT Organization: Interstellar Research Lines: 23 Message-ID: <549578bc.631514@news.eternal-september.org> References: Reply-To: NoSpam@daqarta.com Injection-Info: mx02.eternal-september.org; posting-host="1f489ea76e115f0420309a4a7252d84a"; logging-data="27293"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jFX9MmS70nMeiVZyMGq8Mxxil4OZVt18=" X-Newsreader: Forte Free Agent 1.11/32.235 Cancel-Lock: sha1:F8hXYGb+I3xs1JIHgU+nuLeIELc= Xref: mx02.eternal-september.org comp.dsp:52889 comp.lang.vhdl:7973 On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote: >On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences? According to Wikipedia (under "numerically controlled oscillator") the NCO is the digital part, which drives a DAC to make a DDS. Bob Masta DAQARTA v7.60 Data AcQuisition And Real-Time Analysis www.daqarta.com Scope, Spectrum, Spectrogram, Sound Level Meter Frequency Counter, Pitch Track, Pitch-to-MIDI FREE Signal Generator, DaqMusiq generator Science with your sound card! From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 20 Dec 2014 13:43:55 GMT Lines: 56 Message-ID: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: a55b373a.news.astraweb.com X-Trace: DXC=GIUoV^?kWc2Of6BS7?ncjjh_8]Unb> I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point. BTW, you are looking for spurs at -120dBc, not -240dBc. An FFT is part of the solution, but naively FFTing the DDS output waveform won't give you good results. Consider the difference between a regular Spectrum Analyser and a Phase Noise test set. The Phase Noise test set is really just a sort of spectrum analyser but it is designed for looking at low level phase noise. Keysight (used to be Agilent) claim to have a sensitivity of about -180 dBc/Hz on their top of the line model. That's an awful lot better than any regular SA. (It also claims to work to 110GHz.) The trick is to get rid of the carrier before calculating the spectrum. The FFT only needs to see the noise, rather than the signal + noise. May I suggest you do the following in your HDL simulation: 1. Generate an "ideal" reference waveform. Use floating point (but use it carefully). 2. Mix this ideal waveform with the waveform from your simulated DDS. You can use a real mixer (i.e. a multiplier). The ideal waveform and the DDS output must be close to pi/2 out of phase. The accuracy of this phase shift determines the amount of carrier cancellation. 3. Get rid of the 2F component at the output of the mixer, i.e. low pass filter. 4. FFT the output of the lpf. 5a Spend half an hour scratching your head trying to work out how to interpret the results. 5b. Decide that the maths is beyond human comprehension. At this point, you either refer to some HP system journal from last century, or determine the scale factors empirically by measuring a test signal with a known amount of phase or frequency modulation. Allan From newsfish@newsfish Tue Dec 29 16:43:40 2015 X-Received: by 10.66.182.7 with SMTP id ea7mr10439532pac.23.1419086258515; Sat, 20 Dec 2014 06:37:38 -0800 (PST) X-Received: by 10.140.18.173 with SMTP id 42mr28724qgf.9.1419086258468; Sat, 20 Dec 2014 06:37:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no14944034igd.0!news-out.google.com!r1ni87qat.1!nntp.google.com!v10no184820qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Dec 2014 06:37:38 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.64.6.79; posting-account=tpu9BAoAAAAZL2gZtrWqYIYAoMw9iVDq NNTP-Posting-Host: 72.64.6.79 References: <7d351cc9-2def-40ed-b6b3-1cd5e53963dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Spectral Purity Measurement From: Brian Davis Injection-Date: Sat, 20 Dec 2014 14:37:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2416 X-Received-Body-CRC: 4258892891 Xref: mx02.eternal-september.org comp.lang.vhdl:7975 On Saturday, December 20, 2014 1:55:06 AM UTC-5, rickman wrote: > >> Updated location of the broken link[2] from that old post: >> https://sites.google.com/site/fpgastuff/dds_oddities.pdf >=20 > Thank you for the references. The PDF file was especially interesting=20 > with all the plots of effects of PT and AQ. >=20 > Just curious, what is up with the AOL thing? I couldn't view the link=20 > without joining. What good is posting content people can't view? >=20 AOL used to provide free FTP space, but silently axed the service about 5 = years ago, so the files aren't there anymore; I moved all the stuff I'd pos= ted over the years to that new google sites page. I think that the login re= direct you're seeing is just some sort of broken link default for their sit= e. Allan wrote: > Consider the difference between a regular Spectrum Analyser=20 > and a Phase Noise test set. The Phase Noise test set is really=20 > just a sort of spectrum analyser but it is designed for looking > at low level phase noise. I first noticed these close-in spurious effects whilst measuring DDS phase= noise on a 3048A in the early 90's :) =20 -Brian From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 20 Dec 2014 15:06:41 GMT Lines: 67 Message-ID: <54959080$0$11124$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 43f189fd.news.astraweb.com X-Trace: DXC=kP2LRe3cEUF0UO2<>T]L;AL?0kYOcDh@JW\:Hm@YlDbJeDjgCTE@N;IAg3ieXVF9\HS8EWM:L2H[E Xref: mx02.eternal-september.org comp.dsp:52891 comp.lang.vhdl:7976 On Sat, 20 Dec 2014 13:43:55 +0000, Allan Herriman wrote: > On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be >> hard to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. The implementation will be synthesizable and the >> measurement code will not. I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > > > BTW, you are looking for spurs at -120dBc, not -240dBc. > > > An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results. > > Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.) > > The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise. > > May I suggest you do the following in your HDL simulation: > > 1. Generate an "ideal" reference waveform. Use floating point (but use > it carefully). > > 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and > the DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation. > > 3. Get rid of the 2F component at the output of the mixer, i.e. low > pass filter. > > 4. FFT the output of the lpf. > > 5a Spend half an hour scratching your head trying to work out how to > interpret the results. > > 5b. Decide that the maths is beyond human comprehension. At this > point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with > a known amount of phase or frequency modulation. > > Allan oops, forgot to mention that after you get rid of the carrier by mixing down to 0Hz (in step 2) and removing the 2F components (in step 3), you can decimate the signal to reduce the bandwidth. This allows you to avoid the need to calculate monster FFTs if you're only interested in the "close in" spurs. Allan From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 20 Dec 2014 19:43:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 71 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.dsp:52893 comp.lang.vhdl:7977 In comp.dsp Allan Herriman wrote: > On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. (snip) > BTW, you are looking for spurs at -120dBc, not -240dBc. > An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results. > Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.) > The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise. > May I suggest you do the following in your HDL simulation: > 1. Generate an "ideal" reference waveform. Use floating point (but use it carefully). My choice would be fixed point. With fixed point, you know exactly how the rounding is done, and it is done independent of the size of the values at any point in the computation. You could, for example, use 64 bit fixed point instead of 64 bit floating point. > 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and the > DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation. Pretty much you are computing, and then subtracting, one frequency (Fourier) component from the signal. You need enough bits (accuracy) to not have rounding contribute to the result (noise). > 3. Get rid of the 2F component at the output of the mixer, > i.e. low pass filter. > 4. FFT the output of the lpf. For fixed point FFT, the values can increase one bit at each stage of the FFT. On average they will increase by sqrt(2) (RMS), but if the orginal carrier is still there, you likely get an increase by a factor of 2 in some bin. If you have enough bits, original signal resolution plus log2(FFT length) seems to me you could just run it through the FFT. Well, that might work best if the carrier was in a single bin. > 5a Spend half an hour scratching your head trying to work out how to > interpret the results. > 5b. Decide that the maths is beyond human comprehension. At this point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with a > known amount of phase or frequency modulation. -- glen From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.albasani.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Dec 2014 04:33:28 GMT Lines: 38 Message-ID: <54964d98$0$21718$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 83f41704.news.astraweb.com X-Trace: DXC=GBbFdFZaRH2 In comp.dsp Allan Herriman wrote: >> 1. Generate an "ideal" reference waveform. Use floating point > (but use it carefully). > > My choice would be fixed point. > > With fixed point, you know exactly how the rounding is done, and it is > done independent of the size of the values at any point in the > computation. You could, for example, use 64 bit fixed point instead of > 64 bit floating point. Rickman appears to be writing a testbench in VHDL. If that is the case, he already has double precision floating point trig functions built in to his simulator (in package ieee.math_real). To use fixed point would be to reimplement and verify the trig functions from scratch - a task that is possibly harder than the original problem he is trying to solve. In general though, I do take your point about the rounding. I would also hazard a guess that Rickman is outputting samples from his testbench and then using a standalone FFT package (outside the VHDL simulation environment) instead of trying to code the FFT in VHDL. I guess this will probably only use floating point. I was thinking about the size of the FFT. The DDS is an FSM. The output is periodic. It's possible to match the number of points in the FFT to the number of states in the FSM, completely eliminating spectral leakage due to windowing. But I suspect he's using a 32 bit phase accumulator, which would rule out this approach. (How big can FFTs get these days? The largest I've ever done had 2**19 complex points, but that was last century on a Sparc.) Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 01:28:00 -0500 Organization: A noiseless patient Spider Lines: 55 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 06:27:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18609"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19wuxCOMuartm+KPoyt9vUa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <54964d98$0$21718$c3e8da3@news.astraweb.com> Cancel-Lock: sha1:iNhnttEGs2y1qD7ywcbbN3ai8l0= Xref: mx02.eternal-september.org comp.dsp:52897 comp.lang.vhdl:7979 On 12/20/2014 11:33 PM, Allan Herriman wrote: > On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: > >> In comp.dsp Allan Herriman wrote: > >>> 1. Generate an "ideal" reference waveform. Use floating point >> (but use it carefully). >> >> My choice would be fixed point. >> >> With fixed point, you know exactly how the rounding is done, and it is >> done independent of the size of the values at any point in the >> computation. You could, for example, use 64 bit fixed point instead of >> 64 bit floating point. > > Rickman appears to be writing a testbench in VHDL. If that is the case, > he already has double precision floating point trig functions built in to > his simulator (in package ieee.math_real). To use fixed point would be > to reimplement and verify the trig functions from scratch - a task that > is possibly harder than the original problem he is trying to solve. A reasonable assumption although I couldn't find info that said that reals were double precision (64 bit). In fact, the info I found said they are only assured to be 32 bit, single precision. Is that wrong? If the VHDL floating point only has a 24 bit mantissa the resolution is only slightly better than the signals I am attempting to measure. In that case I would consider writing out the NCO data to a file for processing in some other environment. In fact, maybe I should do that anyway for multiple reasons. I understand there are open source packages similar to Matlab. I may try using one of these. > In general though, I do take your point about the rounding. > > I would also hazard a guess that Rickman is outputting samples from his > testbench and then using a standalone FFT package (outside the VHDL > simulation environment) instead of trying to code the FFT in VHDL. I > guess this will probably only use floating point. > > > I was thinking about the size of the FFT. The DDS is an FSM. The output > is periodic. It's possible to match the number of points in the FFT to > the number of states in the FSM, completely eliminating spectral leakage > due to windowing. But I suspect he's using a 32 bit phase accumulator, > which would rule out this approach. (How big can FFTs get these days? > The largest I've ever done had 2**19 complex points, but that was last > century on a Sparc.) Once I find the spurs in an FFT, I can narrow down the search to selected bins and use a DFT. -- Rick From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 21 Dec 2014 11:03:38 GMT Lines: 21 Message-ID: <5496a90a$0$11117$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 5942ee25.news.astraweb.com X-Trace: DXC=`K6_UHb1b4VkR1VMS3E6>\L?0kYOcDh@ZW\:Hm@YlDbZ\Z=oIO[;=mTAg3ieXVF9\X5mUR5neNX1] Xref: mx02.eternal-september.org comp.dsp:52900 comp.lang.vhdl:7980 On Sun, 21 Dec 2014 01:28:00 -0500, rickman wrote: > A reasonable assumption although I couldn't find info that said that > reals were double precision (64 bit). In fact, the info I found said > they are only assured to be 32 bit, single precision. Is that wrong? That's a good point. It's implementation dependent. The old version of Modelsim that I have on this computer has this in the source for the std library: type real is range -1.0E308 to 1.0E308; which is equivalent to 64 bit "double". I don't imagine that any mainstream compiler would use less than 64 bits for real, but I could be wrong. OTOH, if you know that all the compilers you're using support 64 bit, it's probably safe to rely on that. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: HpW-Works Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 11:20:02 -0300 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 14:19:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="6c3e357dc38119382b92f62f4efda144"; logging-data="31865"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+NqSuX4Hc8BO9jkI+xAjA47RLEG/gb5MM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 In-Reply-To: Cancel-Lock: sha1:p+tXpAGX3I80mEtfFcxzq5p+kiY= Xref: mx02.eternal-september.org comp.dsp:52901 comp.lang.vhdl:7981 Am 19.12.2014 15:24, schrieb Tim Wescott: > No spectrum analyzer in the world has a 240dB dynamic > range Hmm, yes analog based on the todays ADC limitations O:( My PC based spectrum analyser supports more then an 240dB dynamic range, while internal calculations are done using double float and even 80 bit float O;) Hp www.hpw-works.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: chrisabele Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 09:49:42 -0500 Lines: 11 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net GlvMCPid4YrfgaqNQfhgrA15ANm+kC5reYEuWYR12B7LbpJcp4 Cancel-Lock: sha1:OgZ7yWM6B8XYYNNbO1jSPQETPek= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Xref: mx02.eternal-september.org comp.dsp:52902 comp.lang.vhdl:7982 On 12/21/2014 1:28 AM, rickman wrote: > > I understand there are open source > packages similar to Matlab. I may try using one of these. > I've found Scilab (http://www.scilab.org/) to be a very functional and well supported alternative to Matlab, at a compelling price point (free). From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Gerhard Hoffmann Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 17:11:03 +0100 Lines: 39 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Reply-To: ghf@hoffmann-hochfrequenz.de Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net AvVnyRpL1+CORgz++jTP0w6rXv9VGKPIavD0opRuZ8xjSzVJgW Cancel-Lock: sha1:ncf4EZFXeMJjLhOFawr8Jfzmmxc= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <54964d98$0$21718$c3e8da3@news.astraweb.com> Xref: mx02.eternal-september.org comp.dsp:52903 comp.lang.vhdl:7983 Am 21.12.2014 um 05:33 schrieb Allan Herriman: > On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: > >> In comp.dsp Allan Herriman wrote: > >>> 1. Generate an "ideal" reference waveform. Use floating point >> (but use it carefully). >> >> My choice would be fixed point. >> >> With fixed point, you know exactly how the rounding is done, and it is >> done independent of the size of the values at any point in the >> computation. You could, for example, use 64 bit fixed point instead of >> 64 bit floating point. > > Rickman appears to be writing a testbench in VHDL. If that is the case, > he already has double precision floating point trig functions built in to > his simulator (in package ieee.math_real). To use fixed point would be > to reimplement and verify the trig functions from scratch - a task that > is possibly harder than the original problem he is trying to solve. The test bed for my sine & cos functions on opencores can write the time series generated by a DDS to a file that could be used for further processing with matlab or whatever. There are also functions to convert between float and un/signed and fractional un/signed. They expect however, that the floats are higher resolution than the signed vectors, they will cease to work when one approaches 48 bit or whatever the size of the mantissa happens to be. Going via int/natural would be even more limiting (31 bit). regards, Gerhard < http://opencores.org/project,sincos > From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 12:05:39 -0500 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 17:05:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13365"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19pcslpI9BlDCUpFvHZk3VB" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:UfnZAn30K1ZCf5o1RVKx0Rzn/no= Xref: mx02.eternal-september.org comp.dsp:52904 comp.lang.vhdl:7984 On 12/21/2014 11:11 AM, Gerhard Hoffmann wrote: > Am 21.12.2014 um 05:33 schrieb Allan Herriman: >> On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: >> >>> In comp.dsp Allan Herriman wrote: >> >>>> 1. Generate an "ideal" reference waveform. Use floating point >>> (but use it carefully). >>> >>> My choice would be fixed point. >>> >>> With fixed point, you know exactly how the rounding is done, and it is >>> done independent of the size of the values at any point in the >>> computation. You could, for example, use 64 bit fixed point instead of >>> 64 bit floating point. >> >> Rickman appears to be writing a testbench in VHDL. If that is the case, >> he already has double precision floating point trig functions built in to >> his simulator (in package ieee.math_real). To use fixed point would be >> to reimplement and verify the trig functions from scratch - a task that >> is possibly harder than the original problem he is trying to solve. > > The test bed for my sine & cos functions on opencores can write > the time series generated by a DDS to a file that could be used > for further processing with matlab or whatever. > > There are also functions to convert between float and un/signed > and fractional un/signed. They expect however, that > the floats are higher resolution than the signed vectors, they > will cease to work when one approaches 48 bit or whatever the > size of the mantissa happens to be. > > Going via int/natural would be even more limiting (31 bit). > > regards, Gerhard > > < http://opencores.org/project,sincos > Thanks, I'll take a look. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 14:52:40 -0500 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 21 Dec 2014 19:52:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="23774"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++R87hlGqV/n+Y5V34yBZX" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: <5494f4a1.456409145@news.eternal-september.org> Cancel-Lock: sha1:VhULhLQqX06RjWOfluWLmaM5Wbk= Xref: mx02.eternal-september.org comp.dsp:52905 comp.lang.vhdl:7985 On 12/19/14 11:04 PM, Eric Jacobsen wrote: > On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 10:06 AM, rickman wrote: >>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>> is the best way to do this. I'm mainly concerned with the "close in" >>> spurs that are often generated by a DDS. >> >> i still get the concepts of DDS and NCO mixed up. what are the differences? > > One is spelled DDS and the other is spelled NCO. is the NCO the typical table-lookup kind (with phase accumulator)? or can it be algorithmic? like y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] where omega_0 is the normalized angular frequency of the sinusoid and with appropriate initial states, y[-1] and y[-2] to result in the amplitude and initial phase desired. is that an NCO that can be used in this DDS? or must it be LUT? anyway, in either case, the oscillator frequency is well defined and i don't understand why rickman would just put in a simple sharp notch filter tuned to the very same frequency and whack the sinusoid and analyze (however he does) what is residual. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 00:13:10 GMT Organization: Anchor Hill Communications Lines: 47 Message-ID: <549760f9.615217305@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="17843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+B0suBGDRsxQNlZ7/6H9USP4cBFfA+byw=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141221-1, 12/21/2014), Outbound message Cancel-Lock: sha1:exxRL9pSDUDqwezgUwkhYF5RWVI= Xref: mx02.eternal-september.org comp.dsp:52906 comp.lang.vhdl:7986 On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson wrote: >On 12/19/14 11:04 PM, Eric Jacobsen wrote: >> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 10:06 AM, rickman wrote: >>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>> is the best way to do this. I'm mainly concerned with the "close in" >>>> spurs that are often generated by a DDS. >>> >>> i still get the concepts of DDS and NCO mixed up. what are the differences? >> >> One is spelled DDS and the other is spelled NCO. > >is the NCO the typical table-lookup kind (with phase accumulator)? or >can it be algorithmic? like > > y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] > >where omega_0 is the normalized angular frequency of the sinusoid and >with appropriate initial states, y[-1] and y[-2] to result in the >amplitude and initial phase desired. > >is that an NCO that can be used in this DDS? or must it be LUT? Generally NCO or DDS refers to a phase accumulator with a LUT, since it is easily implemented in hardware. That's a general architecture that is well-known and can be adjusted to produce very clean local oscillators. If somebody tried to sell me a block of IP with an "NCO" built some other way I'd be asking a lot of questions. >anyway, in either case, the oscillator frequency is well defined and i >don't understand why rickman would just put in a simple sharp notch >filter tuned to the very same frequency and whack the sinusoid and >analyze (however he does) what is residual. It could be because the phase accumulator/LUT architecture is general and the range of operation of the output frequency is pretty broad. A more generalized test approach is more flexible to testing over a broader range of outputs. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sun, 21 Dec 2014 19:30:48 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 22 Dec 2014 00:30:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21463"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19groOp5Mdx+9Ej1Rylh7JX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549760f9.615217305@news.eternal-september.org> Cancel-Lock: sha1:C29TAPmyyRgvewU/M8WYyMHvrQc= Xref: mx02.eternal-september.org comp.dsp:52907 comp.lang.vhdl:7987 On 12/21/2014 7:13 PM, Eric Jacobsen wrote: > On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 10:06 AM, rickman wrote: >>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>> spurs that are often generated by a DDS. >>>> >>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>> >>> One is spelled DDS and the other is spelled NCO. >> >> is the NCO the typical table-lookup kind (with phase accumulator)? or >> can it be algorithmic? like >> >> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >> >> where omega_0 is the normalized angular frequency of the sinusoid and >> with appropriate initial states, y[-1] and y[-2] to result in the >> amplitude and initial phase desired. >> >> is that an NCO that can be used in this DDS? or must it be LUT? > > Generally NCO or DDS refers to a phase accumulator with a LUT, since > it is easily implemented in hardware. That's a general architecture > that is well-known and can be adjusted to produce very clean local > oscillators. If somebody tried to sell me a block of IP with an > "NCO" built some other way I'd be asking a lot of questions. Actually this started with a discussion is s.e.d about how bad the spurs are with a typical DDS and how to mitigate them. That made me dig up my memory of designing a DDS a few years back as part of a test set. It didn't need to be anything special, but for grins I took a look at what could be done in a rather small FPGA for audio frequencies. I considered linear interpolation which gets around the close in spurs from phase truncation (seems to be the major objection to using a DDS) and with even a smallish LUT of 256 entries I get about 18 bit accuracy in the sine values. With a 1024 entry table the accuracy is more than 10 times better or around 21 bits. Of course quantization error will add to that, but this allows the close in spurs to be *much* smaller than with straight LUTs. >> anyway, in either case, the oscillator frequency is well defined and i >> don't understand why rickman would just put in a simple sharp notch >> filter tuned to the very same frequency and whack the sinusoid and >> analyze (however he does) what is residual. > > It could be because the phase accumulator/LUT architecture is general > and the range of operation of the output frequency is pretty broad. > A more generalized test approach is more flexible to testing over a > broader range of outputs. I'm not sure I understand the question, notwithstanding the grammar error. I think Robert meant "i don't understand why rickman >>wouldn't<< just put in"... I don't know why I wouldn't do that either. I am here asking what would be the best way. I seem to remember something similar being done in a digital receiver test. A carrier is applied to the analog input and in the digital domain (somewhere) a notch filter is used to drop out the carrier leaving most of the artifacts. It's all very fuzzy at this point. I think they also used a two tone test which shows the effects of inter-modulation products, a real concern with real signals. -- Rick From newsfish@newsfish Tue Dec 29 16:43:40 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!Xl.tags.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 21 Dec 2014 16:44:33 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> <5496a90a$0$11117$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Sun, 21 Dec 2014 16:44:33 -0600 Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-tyjGmkV2gQeXYlSwkxdWq+SirL4hrYR78kBNijzR1QbRx8usQvUImNpfs1BvWgMAocfMVhyJcvy4WbV!sdq9ktP7Aqx6ThYJqZxYnq9tDrjPyNyBXMIPAEtQrp1Rz5PglvtWo+nrM0JTE57tkpgeZ4865tMs X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2594 Xref: mx02.eternal-september.org comp.dsp:52908 comp.lang.vhdl:7988 On Sun, 21 Dec 2014 11:03:38 +0000, Allan Herriman wrote: > On Sun, 21 Dec 2014 01:28:00 -0500, rickman wrote: > >> A reasonable assumption although I couldn't find info that said that >> reals were double precision (64 bit). In fact, the info I found said >> they are only assured to be 32 bit, single precision. Is that wrong? > > That's a good point. It's implementation dependent. > > The old version of Modelsim that I have on this computer has this in the > source for the std library: > > type real is range -1.0E308 to 1.0E308; > > which is equivalent to 64 bit "double". I don't imagine that any > mainstream compiler would use less than 64 bits for real, but I could be > wrong. > OTOH, if you know that all the compilers you're using support 64 bit, > it's probably safe to rely on that. If by "compiler" you mean VHDL, I can't speak to that. However, there are a distressingly large number of C compilers for 8- and 16-bit machines that use 32-bit floating point even when you call out "double". This just torques me. While there is every reason for making comprehensive libraries that work with 32-bit floating point numbers in resource-constrained machines, you don't have to make non-ANSI-compliant code to do it. -- www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!Xl.tags.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!buffer2.nntp.dca1.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 21 Dec 2014 16:46:42 -0600 From: Tim Wescott Subject: Re: Spectral Purity Measurement Newsgroups: comp.dsp,comp.lang.vhdl References: <54957d1b$0$12915$c3e8da3$5496439d@news.astraweb.com> <54964d98$0$21718$c3e8da3@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Sun, 21 Dec 2014 16:46:42 -0600 Lines: 21 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-TTIg4kEfVN43dlBV+99F/CScHoCzgzzp58Q/4wgUlkfRAsuoMv7pYQk+8RI3DuxDkc8ukIWew37Ehp8!ywNkRv6/WFQLum/c7/jei8sazA7/NeO454QWrRXgbZEbXvyJGtaS2cEHPn92KpNwdtamKuyAZeZN X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1958 Xref: mx02.eternal-september.org comp.dsp:52909 comp.lang.vhdl:7989 On Sun, 21 Dec 2014 09:49:42 -0500, chrisabele wrote: > On 12/21/2014 1:28 AM, rickman wrote: > >> >> I understand there are open source packages similar to Matlab. I may >> try using one of these. >> > > > I've found Scilab (http://www.scilab.org/) to be a very functional and > well supported alternative to Matlab, at a compelling price point > (free). +1 on using Scilab, at least if you were incorrect on your 240dBc calculation. At this point, I would prefer Scilab even if it were priced the same as Matlab. It doesn't have Matlab's bells and whistle's, but it does edge Matlab out in git-er-done utility. -- www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 19:10:27 GMT Organization: Anchor Hill Communications Lines: 110 Message-ID: <54986aaf.683238858@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="15146"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19tJRqhnNV1xo2/WsWSxT6WxK//0VwNqD8=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141222-0, 12/22/2014), Outbound message Cancel-Lock: sha1:7e5SyCEJX6ek1DzTh7GPx31U1pM= Xref: mx02.eternal-september.org comp.dsp:52911 comp.lang.vhdl:7990 On Sun, 21 Dec 2014 19:30:48 -0500, rickman wrote: >On 12/21/2014 7:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > >Actually this started with a discussion is s.e.d about how bad the spurs >are with a typical DDS and how to mitigate them. That made me dig up my >memory of designing a DDS a few years back as part of a test set. It >didn't need to be anything special, but for grins I took a look at what >could be done in a rather small FPGA for audio frequencies. I >considered linear interpolation which gets around the close in spurs >from phase truncation (seems to be the major objection to using a DDS) >and with even a smallish LUT of 256 entries I get about 18 bit accuracy >in the sine values. With a 1024 entry table the accuracy is more than >10 times better or around 21 bits. > >Of course quantization error will add to that, but this allows the close >in spurs to be *much* smaller than with straight LUTs. > > >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. > >I'm not sure I understand the question, notwithstanding the grammar >error. I think Robert meant "i don't understand why rickman > >>wouldn't<< just put in"... > >I don't know why I wouldn't do that either. I am here asking what would >be the best way. > >I seem to remember something similar being done in a digital receiver >test. A carrier is applied to the analog input and in the digital >domain (somewhere) a notch filter is used to drop out the carrier >leaving most of the artifacts. It's all very fuzzy at this point. I >think they also used a two tone test which shows the effects of >inter-modulation products, a real concern with real signals. > >-- > >Rick Do a web search on "Analog Devices DDS", and in the first few entries you should find links to some white papers that are good on details of DDS architecture and analysis. Also, Qualcomm's "Synthesizer Products Data Book" is also very good. Some of those documents are from the 90s, and there are other public docs out there that go into more detail on spur mitigation and analysis, but these are good references. BTW, Qualcomm was a leader in supplying stand-alone silicon DDS products, which were called by the name DDS, even though they didn't have an integrated DAC. Back then mixed-signal products weren't really available. For implementations where memory is very constrained, like potentially in an FPGA, the phase resolution in the LUT can be increased 4x by only storing a quarter of the wave. We've done this in the past with good results. DDS implementations can sometimes also benefit from dithering, at the outputs of both the phase accumulator and the LUT, although the usual tradeoffs apply. There are a number of tricks that have been learned over the years, and many are application dependent. e.g., different tricks may apply for generating a low-jitter clock than generating a local oscillator. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 15:17:23 -0700 Organization: Aioe.org NNTP Server Lines: 64 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.dsp:52914 comp.lang.vhdl:7991 On 12/21/2014 5:13 PM, Eric Jacobsen wrote: > On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson > wrote: > >> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 10:06 AM, rickman wrote: >>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>> spurs that are often generated by a DDS. >>>> >>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>> >>> One is spelled DDS and the other is spelled NCO. >> >> is the NCO the typical table-lookup kind (with phase accumulator)? or >> can it be algorithmic? like >> >> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >> >> where omega_0 is the normalized angular frequency of the sinusoid and >> with appropriate initial states, y[-1] and y[-2] to result in the >> amplitude and initial phase desired. >> >> is that an NCO that can be used in this DDS? or must it be LUT? > > Generally NCO or DDS refers to a phase accumulator with a LUT, since > it is easily implemented in hardware. That's a general architecture > that is well-known and can be adjusted to produce very clean local > oscillators. If somebody tried to sell me a block of IP with an > "NCO" built some other way I'd be asking a lot of questions. I have built NCOs using CORDIC rotators. No lookup tables. They pipeline nicely and are therefore very fast, they require no multipliers [1], they generate quadrature outputs for free, they can perform frequency translations for free (again no multipliers), and they are simple prove numerical accuracy. [1] Maybe not a huge issue these days. The LUT-based NCOs requires two multipliers to combine the coarse and fine LUTs (four multipliers if you need a complex NCO output) and perhaps another four multipliers if you need to do a frequency translation. Rob. >> anyway, in either case, the oscillator frequency is well defined and i >> don't understand why rickman would just put in a simple sharp notch >> filter tuned to the very same frequency and whack the sinusoid and >> analyze (however he does) what is residual. > > It could be because the phase accumulator/LUT architecture is general > and the range of operation of the output frequency is pretty broad. > A more generalized test approach is more flexible to testing over a > broader range of outputs. > > > Eric Jacobsen > Anchor Hill Communications > http://www.anchorhill.com > From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Mon, 22 Dec 2014 20:25:36 -0500 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 01:25:15 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="7516"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fR9Jqdyd7n6UoNynANu4E" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:oXQw9IY2E7SptBt9A9n/OiL98OE= Xref: mx02.eternal-september.org comp.dsp:52915 comp.lang.vhdl:7992 On 12/21/14 7:30 PM, rickman wrote: > On 12/21/2014 7:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> ... >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. > > I'm not sure I understand the question, notwithstanding the grammar > error. I think Robert meant "i don't understand why rickman >>wouldn't<< > just put in"... abstively correct. i often suffer from the "Wicked Bible" syndrome. > I don't know why I wouldn't do that either. I am here asking what would > be the best way. > > I seem to remember something similar being done in a digital receiver > test. A carrier is applied to the analog input and in the digital domain > (somewhere) a notch filter is used to drop out the carrier leaving most > of the artifacts. It's all very fuzzy at this point. I think they also > used a two tone test which shows the effects of inter-modulation > products, a real concern with real signals. okay, let's say that you have N points in your LUT. (if N is a power of two, the table wrap-around is trivial.) and let's say that there is a single cycle of a sine function in that LUT. and let's say your sample rate is Fs. the phase increment for a frequency of f0 would be phase_increment = N*(f0/Fs) every sample the phase is incremented: phase[n] = (phase[n-1] + phase_increment)modulo_N and phase[n] is divided into its integer part that tells you where to go in your LUT and a fractional part that tells you how you might interpolate. integer_part = floor(phase[n]) fractional_part = phase[n] - integer_part if you're doing no interpolation the waveform output is x[n] = LUT[integer_part] if you're doing linear interpolation the waveform output is x[n] = LUT[integer_part] + fractional_part*(LUT[integer_part+1] - LUT[integer_part]) just make sure you have an extra point at the end of your LUT that is the same as the zeroth point: LUT[N] = LUT[0] now, using that very same f0 and Fs and some Q or BW that you'll have to decide (make the BW sorta tight), then implement a very simple biquad notch filter: y[n] = b0*x[n] + b1*x[n-1] + b2*x[n-2] - a1*y[n-1] - a2*y[n-2] where b0 = b2 = 1/( 1 + sin(w0)/(2Q) ) b1 = a1 = -2*cos(w0)/(1 + sin(w0)/(2Q)) a2 = ( 1 - sin(w0)/(2Q) )/( 1 + sin(w0)/(2Q) ) and w0 = 2*pi*f0/Fs 1/Q = 2*sinh( ln(2)/2 * BW * w0/sin(w0) ) (BW in octaves) straight outa da cookbook. whatever comes out at y[n] is whatever is impure in your sinusoidal output. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 23 Dec 2014 09:23:35 -0600 From: techman Subject: Finding the difference between two numbers Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 513219d1-ac8c-4b5b-88e0-2ea8ad503715 Message-ID: Date: Tue, 23 Dec 2014 09:23:35 -0600 Lines: 10 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-NO0DROzUkjnb8OdBoXFIqlvFrs0KKPPUeeFu0huj5PJ3NVNmCLHLw1qnSJ6ZVprCLSHKz9bJIq2KzVP!BSnVMqdxywYlxcKzTarv87NvzNcQoj4NRrGShNRIMKx5uMLrS69Sft0C0v3KQZrLo3lFYsk6Kx9p!pKM= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1262 Xref: mx02.eternal-september.org comp.lang.vhdl:7993 Hi All, I would be grateful if someone can tell me the best way to find the difference between two std logic vectors which at any one time may or may not be signed. In simple terms if I was to use the integer equivalents then I would be looking for the following answers -2 -5 = 3 -2 +5 = 7 5 - 2 = 3 -5 -2 = 3 Thanks From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 15:35:13 GMT Organization: Anchor Hill Communications Lines: 83 Message-ID: <549989f6.756782253@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="20300"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+F2mFOyb8+L/fEc/6FEOa/oADKyWiGIK0=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141223-0, 12/23/2014), Outbound message Cancel-Lock: sha1:VqFEYr2PlleZMODyDoXLQDxKGOA= Xref: mx02.eternal-september.org comp.dsp:52920 comp.lang.vhdl:7994 On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle wrote: >On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > >I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >nicely and are therefore very fast, they require no multipliers [1], >they generate quadrature outputs for free, they can perform frequency >translations for free (again no multipliers), and they are simple prove >numerical accuracy. CORDICs are fine when and where they make sense, but they are often not the best tradeoff. If you have no memory, no multipliers, or gates are way cheaper than memory, and if the latency is tolerable, then a CORDIC may be a good option. >[1] Maybe not a huge issue these days. The LUT-based NCOs requires two >multipliers to combine the coarse and fine LUTs (four multipliers if you >need a complex NCO output) and perhaps another four multipliers if you >need to do a frequency translation. Many applications don't need separate LUTs to get the required performance, and even then, or even in the case of complex output, it can be done without multipliers. As is often the case, there are many ways to get the job done. Sometimes the complications aren't necessary, they're just convenient. >Rob. > >>> anyway, in either case, the oscillator frequency is well defined and i >>> don't understand why rickman would just put in a simple sharp notch >>> filter tuned to the very same frequency and whack the sinusoid and >>> analyze (however he does) what is residual. >> >> It could be because the phase accumulator/LUT architecture is general >> and the range of operation of the output frequency is pretty broad. >> A more generalized test approach is more flexible to testing over a >> broader range of outputs. >> >> >> Eric Jacobsen >> Anchor Hill Communications >> http://www.anchorhill.com >> > > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 11:06:39 -0500 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 16:06:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="28140"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ApYGY5oUR6nvd77yDUG6j" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549989f6.756782253@news.eternal-september.org> Cancel-Lock: sha1:TUheB/6RO1r6U7CWmVX+FSJrqSw= Xref: mx02.eternal-september.org comp.dsp:52922 comp.lang.vhdl:7995 On 12/23/2014 10:35 AM, Eric Jacobsen wrote: > On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle > wrote: > >> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>> spurs that are often generated by a DDS. >>>>>> >>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>> >>>>> One is spelled DDS and the other is spelled NCO. >>>> >>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>> can it be algorithmic? like >>>> >>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>> >>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>> amplitude and initial phase desired. >>>> >>>> is that an NCO that can be used in this DDS? or must it be LUT? >>> >>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>> it is easily implemented in hardware. That's a general architecture >>> that is well-known and can be adjusted to produce very clean local >>> oscillators. If somebody tried to sell me a block of IP with an >>> "NCO" built some other way I'd be asking a lot of questions. >> >> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >> nicely and are therefore very fast, they require no multipliers [1], >> they generate quadrature outputs for free, they can perform frequency >> translations for free (again no multipliers), and they are simple prove >> numerical accuracy. > > CORDICs are fine when and where they make sense, but they are often > not the best tradeoff. If you have no memory, no multipliers, or > gates are way cheaper than memory, and if the latency is tolerable, > then a CORDIC may be a good option. > >> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >> multipliers to combine the coarse and fine LUTs (four multipliers if you >> need a complex NCO output) and perhaps another four multipliers if you >> need to do a frequency translation. > > Many applications don't need separate LUTs to get the required > performance, and even then, or even in the case of complex output, it > can be done without multipliers. Care to elaborate on this? I'm not at all clear on how you make a LUT based NCO without LUTs and unless you are using a very coarse approximation, without multipliers. > As is often the case, there are many ways to get the job done. > Sometimes the complications aren't necessary, they're just convenient. Yes, there is more than one way to skin a goose. But they all have their issues. CORDIC for example, has no multiplier... but has an iteration that is essentially the same as multiplication by iteration. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed1.news.xs4all.nl!xs4all!usenetcore.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 23 Dec 2014 10:42:31 -0600 Date: Tue, 23 Dec 2014 16:42:24 +0000 From: Mike Perkins User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Finding the difference between two numbers References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 17 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-JLWur/p9kadO9VVSCdXu5UUeL+3Nkv+pCL6IS1EgL0lwy3QYiOuLyR7pn2P1bi40iZpcwxKEX5qw2OP!CpjgNSEX/7ybrMMZkilNewOG7/NW+/niiuggio4k4SlTJo1C/EYAii4hv25bhhGl7S1Kzjqt X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1745 Xref: mx02.eternal-september.org comp.lang.vhdl:7996 On 23/12/2014 15:23, techman wrote: > Hi All, > I would be grateful if someone can tell me the best way to find the difference between two std logic vectors which at any one time may or may not be signed. > In simple terms if I was to use the integer equivalents then I would be looking for the following answers > -2 -5 = 3 > -2 +5 = 7 > 5 - 2 = 3 > -5 -2 = 3 > Thanks I'm sorry but this is very basic. Can I suggest you google for arithmetic examples in VHDL? -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 21:48:22 GMT Organization: Anchor Hill Communications Lines: 89 Message-ID: <5499e27d.779445002@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="13553"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aLM+VNGzlXL6V6R5zRt3O2QAohukPQfE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141223-0, 12/23/2014), Outbound message Cancel-Lock: sha1:nUQafofgf71naVee71EYVAB4OC8= Xref: mx02.eternal-september.org comp.dsp:52924 comp.lang.vhdl:7997 On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >> wrote: >> >>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>> spurs that are often generated by a DDS. >>>>>>> >>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>> >>>>>> One is spelled DDS and the other is spelled NCO. >>>>> >>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>> can it be algorithmic? like >>>>> >>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>> >>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>> amplitude and initial phase desired. >>>>> >>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>> >>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>> it is easily implemented in hardware. That's a general architecture >>>> that is well-known and can be adjusted to produce very clean local >>>> oscillators. If somebody tried to sell me a block of IP with an >>>> "NCO" built some other way I'd be asking a lot of questions. >>> >>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>> nicely and are therefore very fast, they require no multipliers [1], >>> they generate quadrature outputs for free, they can perform frequency >>> translations for free (again no multipliers), and they are simple prove >>> numerical accuracy. >> >> CORDICs are fine when and where they make sense, but they are often >> not the best tradeoff. If you have no memory, no multipliers, or >> gates are way cheaper than memory, and if the latency is tolerable, >> then a CORDIC may be a good option. >> >>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>> need a complex NCO output) and perhaps another four multipliers if you >>> need to do a frequency translation. >> >> Many applications don't need separate LUTs to get the required >> performance, and even then, or even in the case of complex output, it >> can be done without multipliers. > >Care to elaborate on this? I'm not at all clear on how you make a LUT >based NCO without LUTs and unless you are using a very coarse >approximation, without multipliers. Not sure what you're asking. You a need a LUT, but just one in many cases. Having a dual-ported single LUT is easy in an FPGA and usually in silicon as well. What makes a multiplier necessary? I've never found the need, but my apps are limited to comm. >> As is often the case, there are many ways to get the job done. >> Sometimes the complications aren't necessary, they're just convenient. > >Yes, there is more than one way to skin a goose. But they all have >their issues. > >CORDIC for example, has no multiplier... but has an iteration that is >essentially the same as multiplication by iteration. Yup. >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 18:10:43 -0500 Organization: A noiseless patient Spider Lines: 80 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 23 Dec 2014 23:10:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="32437"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19dZGbVBA8OCtXd5nofPFRE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <5499e27d.779445002@news.eternal-september.org> Cancel-Lock: sha1:lDhLJ3J3hGrvhAtX6QJkogcaRNU= Xref: mx02.eternal-september.org comp.dsp:52926 comp.lang.vhdl:7998 On 12/23/2014 4:48 PM, Eric Jacobsen wrote: > On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: > >> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >>> wrote: >>> >>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>> wrote: >>>>>>> >>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>>> spurs that are often generated by a DDS. >>>>>>>> >>>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>>> >>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>> >>>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>>> can it be algorithmic? like >>>>>> >>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>> >>>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>>> amplitude and initial phase desired. >>>>>> >>>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>>> >>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>>> it is easily implemented in hardware. That's a general architecture >>>>> that is well-known and can be adjusted to produce very clean local >>>>> oscillators. If somebody tried to sell me a block of IP with an >>>>> "NCO" built some other way I'd be asking a lot of questions. >>>> >>>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>>> nicely and are therefore very fast, they require no multipliers [1], >>>> they generate quadrature outputs for free, they can perform frequency >>>> translations for free (again no multipliers), and they are simple prove >>>> numerical accuracy. >>> >>> CORDICs are fine when and where they make sense, but they are often >>> not the best tradeoff. If you have no memory, no multipliers, or >>> gates are way cheaper than memory, and if the latency is tolerable, >>> then a CORDIC may be a good option. >>> >>>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>>> need a complex NCO output) and perhaps another four multipliers if you >>>> need to do a frequency translation. >>> >>> Many applications don't need separate LUTs to get the required >>> performance, and even then, or even in the case of complex output, it >>> can be done without multipliers. >> >> Care to elaborate on this? I'm not at all clear on how you make a LUT >> based NCO without LUTs and unless you are using a very coarse >> approximation, without multipliers. > > Not sure what you're asking. You a need a LUT, but just one in many > cases. Having a dual-ported single LUT is easy in an FPGA and > usually in silicon as well. > > What makes a multiplier necessary? I've never found the need, but my > apps are limited to comm. Maybe we aren't on the same page. The multiplier is there for the fine adjustment. If you are happy with some -60 or -80 dB spurs one LUT is fine. But if you want better performance the single LUT approach requires *very* large tables. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 20:10:59 -0500 Organization: A noiseless patient Spider Lines: 82 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 01:10:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="93a28beffd6034b7478094f1f552d895"; logging-data="23049"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ZYdk01zJTgr76etvfwAYh" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:Jc4/Cbjss34eIRHEX797R2eo9Sg= Xref: mx02.eternal-september.org comp.dsp:52927 comp.lang.vhdl:7999 this did not seem to get posted so i am reposting. sorry for any repeated post. On 12/22/14 5:17 PM, Rob Doyle wrote: > On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >> wrote: >> >>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>> I want to analyze the output of a DDS circuit and am wondering if >>>>>> an FFT >>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>> spurs that are often generated by a DDS. >>>>> >>>>> i still get the concepts of DDS and NCO mixed up. what are the >>>>> differences? >>>> >>>> One is spelled DDS and the other is spelled NCO. >>> >>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>> can it be algorithmic? like >>> >>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>> >>> where omega_0 is the normalized angular frequency of the sinusoid and >>> with appropriate initial states, y[-1] and y[-2] to result in the >>> amplitude and initial phase desired. >>> >>> is that an NCO that can be used in this DDS? or must it be LUT? >> >> Generally NCO or DDS refers to a phase accumulator with a LUT, since >> it is easily implemented in hardware. That's a general architecture >> that is well-known and can be adjusted to produce very clean local >> oscillators. If somebody tried to sell me a block of IP with an >> "NCO" built some other way I'd be asking a lot of questions. > > I have built NCOs using CORDIC rotators. No lookup tables. They pipeline > nicely and are therefore very fast, they require no multipliers [1], ??? i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here a while back), but i always thought that CORDIC did essentially x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] or, as complex numbers: (x[n] + j*y[n]) = exp(j*2*pi*f0/Fs) * (x[n-1] + j*y[n-1]) doesn't that require a few multiplications? > they generate quadrature outputs for free, they can perform frequency > translations for free (again no multipliers), and they are simple prove > numerical accuracy. > > [1] Maybe not a huge issue these days. The LUT-based NCOs requires two > multipliers to combine the coarse and fine LUTs even for linear interpolation? i think one multiplier is enough. the higher order the interpolation, the more multipliers needed (and the fewer points int he LUT are needed). > (four multipliers if you need a complex NCO output) and perhaps another > four multipliers if you need to do a frequency translation. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 21:02:48 -0700 Organization: Aioe.org NNTP Server Lines: 149 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.dsp:52930 comp.lang.vhdl:8000 On 12/23/2014 6:10 PM, robert bristow-johnson wrote: > > this did not seem to get posted so i am reposting. sorry for any > repeated post. > > On 12/22/14 5:17 PM, Rob Doyle wrote: >> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>> wrote: >>> >>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>> mainly concerned with the "close > in" >>>>>>> spurs that are often generated by a DDS. >>>>>> >>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>> the differences? >>>>> >>>>> One is spelled DDS and the other is spelled NCO. >>>> >>>> is the NCO the typical table-lookup kind (with phase >>>> accumulator)? or can it be algorithmic? like >>>> >>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>> >>>> where omega_0 is the normalized angular frequency of the >>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>> to result in the amplitude and initial phase desired. >>>> >>>> is that an NCO that can be used in this DDS? or must it be >>>> LUT? >>> >>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>> since it is easily implemented in hardware. That's a general >>> architecture that is well-known and can be adjusted to produce >>> very clean local oscillators. If somebody tried to sell me a >>> block of IP with an "NCO" built some other way I'd be asking a >>> lot of questions. >> >> I have built NCOs using CORDIC rotators. No lookup tables. They >> pipeline nicely and are therefore very fast, they require no >> multipliers [1], > > ??? > > i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here > a while back), but i always thought that CORDIC did essentially > > x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] > y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] Yes. So far. So good. These are my notes if anyone is interested... [snip] Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase accumulator for an NCO application. Factor out the cos(theta): x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} At this point you might be thinking "Holy crap. That's one heck of a constraint!" Yeh... but keep reading anyway. You can drop the cos(theta) common term. It's just a gain term that rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. x[n] = x[n-1] - y[n-1] / 2**i y[n] = y[n-1] + x[n-1] / 2**i or (assuming twos complement math) - simply: x[n] = x[n-1] - y[n-1] >> i y[n] = y[n-1] + x[n-1] >> i where >> is a shift right operation [1] As this point it seems as if an *extreme* limitation has been placed on the selection of rotation angles. The equation above only describes how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of the following angles: atan(1) (45.000000000000000000000000000000 degrees) atan(1/2) (26.565051177077989351572193720453 degrees) atan(1/4) (14.036243467926478582892320159163 degrees) atan(1/8) (7.1250163489017975619533008412068 degrees) atan(1/16) (3.5763343749973510306847789144588 degrees) atan(1/32) (1.7899106082460693071502497760791 degrees) ...and so forth. The equation above does not describe how to rotate an input signal an arbitrary angle! Although this is true; all is not lost. Notice that in general that theta/2 < tan(theta). This truth allows the CORDIC to be used iteratively to rotate any input to any angle with any precision. IMO this is the genius of the CORDIC. I probably should have mentioned that you swap the rotation direction by flipping the additions and subtractions. The term z[n] is introduced to accumulate the angle as the CORDIC iterates. The term d[n] swaps the direction of rotation. Finally the familiar recursive CORDIC equation can be written as follows: x[n] = x[n-1] - d[n] y[n-1] >> i y[n] = y[n-1] + d[n] x[n-1] >> i z[n] = z[n-1] - d[n] tan(1/2**i) where: d[n] is +1 for z[n-1] < theta. Clockwise rotation next. d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. No multiplies here. The CORDIC simply does a successive approximation to the angle - rotating the angle clockwise or counter-clockwise by these limited selection of angles as necessary to converge on the desired angle. Each time the iteration occurs, the angle error is reduced by at least half. > doesn't that require a few multiplications? Nope. Just adds/subtracts - the sign of the angle error determines which direction to rotate on the next iteration. If this is pipelined, the shifts aren't real - they just select which bits of the previous iteration are used on the next iteration. The tan(1/2**i) term is a constant for each iteration. As an implementation detail, it saves hardware if you iterate from the angle toward zero instead of from zero toward the angle. If you do that, the sign of z[i] is the direction of rotation. It saves a magnitude compare for each iteration. Rob. From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Tue, 23 Dec 2014 23:40:20 -0500 Organization: A noiseless patient Spider Lines: 161 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 04:40:11 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18606"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18F882VOE0cNwur0H8ewn5r" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:DspwKTN75TEhFIQ8scai6tO9x3k= Xref: mx02.eternal-september.org comp.dsp:52931 comp.lang.vhdl:8001 On 12/23/2014 11:02 PM, Rob Doyle wrote: > On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >> >> this did not seem to get posted so i am reposting. sorry for any >> repeated post. >> >> On 12/22/14 5:17 PM, Rob Doyle wrote: >>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>> wrote: >>>> >>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>> mainly concerned with the "close >> in" >>>>>>>> spurs that are often generated by a DDS. >>>>>>> >>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>> the differences? >>>>>> >>>>>> One is spelled DDS and the other is spelled NCO. >>>>> >>>>> is the NCO the typical table-lookup kind (with phase >>>>> accumulator)? or can it be algorithmic? like >>>>> >>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>> >>>>> where omega_0 is the normalized angular frequency of the >>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>> to result in the amplitude and initial phase desired. >>>>> >>>>> is that an NCO that can be used in this DDS? or must it be >>>>> LUT? >>>> >>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>> since it is easily implemented in hardware. That's a general >>>> architecture that is well-known and can be adjusted to produce >>>> very clean local oscillators. If somebody tried to sell me a >>>> block of IP with an "NCO" built some other way I'd be asking a >>>> lot of questions. >>> >>> I have built NCOs using CORDIC rotators. No lookup tables. They >>> pipeline nicely and are therefore very fast, they require no >>> multipliers [1], >> >> ??? >> >> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >> a while back), but i always thought that CORDIC did essentially >> >> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] > > Yes. So far. So good. These are my notes if anyone is interested... > > [snip] > > Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase > accumulator for an NCO application. > > Factor out the cos(theta): > > x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} > y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} > > If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: > > x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} > y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} > > At this point you might be thinking "Holy crap. That's one heck of a > constraint!" Yeh... but keep reading anyway. > > You can drop the cos(theta) common term. It's just a gain term that > rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. > > x[n] = x[n-1] - y[n-1] / 2**i > y[n] = y[n-1] + x[n-1] / 2**i > > or (assuming twos complement math) - simply: > > x[n] = x[n-1] - y[n-1] >> i > y[n] = y[n-1] + x[n-1] >> i > > where >> is a shift right operation > > [1] As this point it seems as if an *extreme* limitation has been placed > on the selection of rotation angles. The equation above only describes > how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of > the following angles: > > atan(1) (45.000000000000000000000000000000 degrees) > atan(1/2) (26.565051177077989351572193720453 degrees) > atan(1/4) (14.036243467926478582892320159163 degrees) > atan(1/8) (7.1250163489017975619533008412068 degrees) > atan(1/16) (3.5763343749973510306847789144588 degrees) > atan(1/32) (1.7899106082460693071502497760791 degrees) > > ...and so forth. > > The equation above does not describe how to rotate an input signal an > arbitrary angle! Although this is true; all is not lost. > > Notice that in general that theta/2 < tan(theta). > > This truth allows the CORDIC to be used iteratively to rotate any input > to any angle with any precision. IMO this is the genius of the CORDIC. > > I probably should have mentioned that you swap the rotation direction by > flipping the additions and subtractions. > > The term z[n] is introduced to accumulate the angle as the CORDIC > iterates. The term d[n] swaps the direction of rotation. Finally the > familiar recursive CORDIC equation can be written as follows: > > x[n] = x[n-1] - d[n] y[n-1] >> i > y[n] = y[n-1] + d[n] x[n-1] >> i > z[n] = z[n-1] - d[n] tan(1/2**i) > > where: > > d[n] is +1 for z[n-1] < theta. Clockwise rotation next. > d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. > > No multiplies here. But this is the same as a multiply in terns of complexity, no? One large difference is that a multiply can be supported in commonly available hardware while this algorithm requires dedicated hardware or iterative software. > The CORDIC simply does a successive approximation to the angle - > rotating the angle clockwise or counter-clockwise by these limited > selection of angles as necessary to converge on the desired angle. Each > time the iteration occurs, the angle error is reduced by at least half. > >> doesn't that require a few multiplications? > > Nope. Just adds/subtracts - the sign of the angle error determines which > direction to rotate on the next iteration. If this is pipelined, the > shifts aren't real - they just select which bits of the previous > iteration are used on the next iteration. The tan(1/2**i) term is a > constant for each iteration. > > As an implementation detail, it saves hardware if you iterate from > the angle toward zero instead of from zero toward the angle. If you do > that, the sign of z[i] is the direction of rotation. It saves a > magnitude compare for each iteration. > > Rob. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Rob Doyle Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 01:24:42 -0700 Organization: Aioe.org NNTP Server Lines: 181 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: 670CkSRN2ntYFEZN8nXcjg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.dsp:52932 comp.lang.vhdl:8002 On 12/23/2014 9:40 PM, rickman wrote: > On 12/23/2014 11:02 PM, Rob Doyle wrote: >> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>> >>> this did not seem to get posted so i am reposting. sorry for any >>> repeated post. >>> >>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>> wrote: >>>>> >>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>> wrote: >>>>>>> >>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>> mainly concerned with the "close >>> in" >>>>>>>>> spurs that are often generated by a DDS. >>>>>>>> >>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>> the differences? >>>>>>> >>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>> >>>>>> is the NCO the typical table-lookup kind (with phase >>>>>> accumulator)? or can it be algorithmic? like >>>>>> >>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>> >>>>>> where omega_0 is the normalized angular frequency of the >>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>> to result in the amplitude and initial phase desired. >>>>>> >>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>> LUT? >>>>> >>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>> since it is easily implemented in hardware. That's a general >>>>> architecture that is well-known and can be adjusted to produce >>>>> very clean local oscillators. If somebody tried to sell me a >>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>> lot of questions. >>>> >>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>> pipeline nicely and are therefore very fast, they require no >>>> multipliers [1], >>> >>> ??? >>> >>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>> a while back), but i always thought that CORDIC did essentially >>> >>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >> >> Yes. So far. So good. These are my notes if anyone is interested... >> >> [snip] >> >> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >> accumulator for an NCO application. >> >> Factor out the cos(theta): >> >> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >> >> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >> >> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >> >> At this point you might be thinking "Holy crap. That's one heck of a >> constraint!" Yeh... but keep reading anyway. >> >> You can drop the cos(theta) common term. It's just a gain term that >> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >> >> x[n] = x[n-1] - y[n-1] / 2**i >> y[n] = y[n-1] + x[n-1] / 2**i >> >> or (assuming twos complement math) - simply: >> >> x[n] = x[n-1] - y[n-1] >> i >> y[n] = y[n-1] + x[n-1] >> i >> >> where >> is a shift right operation >> >> [1] As this point it seems as if an *extreme* limitation has been placed >> on the selection of rotation angles. The equation above only describes >> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >> the following angles: >> >> atan(1) (45.000000000000000000000000000000 degrees) >> atan(1/2) (26.565051177077989351572193720453 degrees) >> atan(1/4) (14.036243467926478582892320159163 degrees) >> atan(1/8) (7.1250163489017975619533008412068 degrees) >> atan(1/16) (3.5763343749973510306847789144588 degrees) >> atan(1/32) (1.7899106082460693071502497760791 degrees) >> >> ...and so forth. >> >> The equation above does not describe how to rotate an input signal an >> arbitrary angle! Although this is true; all is not lost. >> >> Notice that in general that theta/2 < tan(theta). >> >> This truth allows the CORDIC to be used iteratively to rotate any input >> to any angle with any precision. IMO this is the genius of the CORDIC. >> >> I probably should have mentioned that you swap the rotation direction by >> flipping the additions and subtractions. >> >> The term z[n] is introduced to accumulate the angle as the CORDIC >> iterates. The term d[n] swaps the direction of rotation. Finally the >> familiar recursive CORDIC equation can be written as follows: >> >> x[n] = x[n-1] - d[n] y[n-1] >> i >> y[n] = y[n-1] + d[n] x[n-1] >> i >> z[n] = z[n-1] - d[n] tan(1/2**i) >> >> where: >> >> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >> >> No multiplies here. > > But this is the same as a multiply in terns of complexity, no? One > large difference is that a multiply can be supported in commonly > available hardware while this algorithm requires dedicated hardware or > iterative software. I agree that the CORDIC has the same complexity as a multiply. I agree that table-based algorithms using multipliers use less FPGA fabric. I was simply pointing out that there might be places where a CORDIC has advantages over LUT-based NCOs. Especially if have ROM or multiplier limitations. I also wanted to point out that if you need to do a 20-bit (using your 120dB example) complex downconversion for example, the CORDIC still requires zero multipliers. If you want to do a 20-bit complex downconversion using a table-based NCO followed by a complex mixer, you might need a *lot* of multipliers. If you only have an 18-bit multiplier, each multiplication requires (maybe up to) 4 multiplier blocks and you need 8 multiplications. I also /suspect/ that for any given device technology the CORDIC will execute at higher speeds. Thats all... >> The CORDIC simply does a successive approximation to the angle - >> rotating the angle clockwise or counter-clockwise by these limited >> selection of angles as necessary to converge on the desired angle. Each >> time the iteration occurs, the angle error is reduced by at least half. >> >>> doesn't that require a few multiplications? >> >> Nope. Just adds/subtracts - the sign of the angle error determines which >> direction to rotate on the next iteration. If this is pipelined, the >> shifts aren't real - they just select which bits of the previous >> iteration are used on the next iteration. The tan(1/2**i) term is a >> constant for each iteration. >> >> As an implementation detail, it saves hardware if you iterate from >> the angle toward zero instead of from zero toward the angle. If you do >> that, the sign of z[i] is the direction of rotation. It saves a >> magnitude compare for each iteration. >> >> Rob. > > From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 04:13:38 -0500 Organization: A noiseless patient Spider Lines: 175 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 09:13:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="30468"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1821V7BIu20tFweYqCoMej8" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:P/as2fG1fn9eokc/e1/6HTAhnUc= Xref: mx02.eternal-september.org comp.dsp:52933 comp.lang.vhdl:8003 On 12/24/2014 3:24 AM, Rob Doyle wrote: > On 12/23/2014 9:40 PM, rickman wrote: >> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>> >>>> this did not seem to get posted so i am reposting. sorry for any >>>> repeated post. >>>> >>>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>>> mainly concerned with the "close >>>> in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>>> the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase >>>>>>> accumulator)? or can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the >>>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>>> to result in the amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>>> LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>>> since it is easily implemented in hardware. That's a general >>>>>> architecture that is well-known and can be adjusted to produce >>>>>> very clean local oscillators. If somebody tried to sell me a >>>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>>> lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>>> pipeline nicely and are therefore very fast, they require no >>>>> multipliers [1], >>>> >>>> ??? >>>> >>>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>>> a while back), but i always thought that CORDIC did essentially >>>> >>>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >>> >>> Yes. So far. So good. These are my notes if anyone is interested... >>> >>> [snip] >>> >>> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >>> accumulator for an NCO application. >>> >>> Factor out the cos(theta): >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >>> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >>> >>> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >>> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >>> >>> At this point you might be thinking "Holy crap. That's one heck of a >>> constraint!" Yeh... but keep reading anyway. >>> >>> You can drop the cos(theta) common term. It's just a gain term that >>> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >>> >>> x[n] = x[n-1] - y[n-1] / 2**i >>> y[n] = y[n-1] + x[n-1] / 2**i >>> >>> or (assuming twos complement math) - simply: >>> >>> x[n] = x[n-1] - y[n-1] >> i >>> y[n] = y[n-1] + x[n-1] >> i >>> >>> where >> is a shift right operation >>> >>> [1] As this point it seems as if an *extreme* limitation has been placed >>> on the selection of rotation angles. The equation above only describes >>> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >>> the following angles: >>> >>> atan(1) (45.000000000000000000000000000000 degrees) >>> atan(1/2) (26.565051177077989351572193720453 degrees) >>> atan(1/4) (14.036243467926478582892320159163 degrees) >>> atan(1/8) (7.1250163489017975619533008412068 degrees) >>> atan(1/16) (3.5763343749973510306847789144588 degrees) >>> atan(1/32) (1.7899106082460693071502497760791 degrees) >>> >>> ...and so forth. >>> >>> The equation above does not describe how to rotate an input signal an >>> arbitrary angle! Although this is true; all is not lost. >>> >>> Notice that in general that theta/2 < tan(theta). >>> >>> This truth allows the CORDIC to be used iteratively to rotate any input >>> to any angle with any precision. IMO this is the genius of the CORDIC. >>> >>> I probably should have mentioned that you swap the rotation direction by >>> flipping the additions and subtractions. >>> >>> The term z[n] is introduced to accumulate the angle as the CORDIC >>> iterates. The term d[n] swaps the direction of rotation. Finally the >>> familiar recursive CORDIC equation can be written as follows: >>> >>> x[n] = x[n-1] - d[n] y[n-1] >> i >>> y[n] = y[n-1] + d[n] x[n-1] >> i >>> z[n] = z[n-1] - d[n] tan(1/2**i) >>> >>> where: >>> >>> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >>> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >>> >>> No multiplies here. >> >> But this is the same as a multiply in terns of complexity, no? One >> large difference is that a multiply can be supported in commonly >> available hardware while this algorithm requires dedicated hardware or >> iterative software. > > I agree that the CORDIC has the same complexity as a multiply. I agree > that table-based algorithms using multipliers use less FPGA fabric. > > I was simply pointing out that there might be places where a CORDIC has > advantages over LUT-based NCOs. > > Especially if have ROM or multiplier limitations. > > I also wanted to point out that if you need to do a 20-bit (using your > 120dB example) complex downconversion for example, the CORDIC still > requires zero multipliers. > > If you want to do a 20-bit complex downconversion using a table-based > NCO followed by a complex mixer, you might need a *lot* of multipliers. > If you only have an 18-bit multiplier, each multiplication requires > (maybe up to) 4 multiplier blocks and you need 8 multiplications. > > I also /suspect/ that for any given device technology the CORDIC will > execute at higher speeds. > > Thats all... I understand, but the distinction between a multiplier and a CORDIC implementation is pretty pointless these days. If you have the space to implement a CORDIC wouldn't you have the space to implement an iterative multiply? I did a linear interpolation just because I could do the multiply iteratively while the previous sample was shifted out to the CODEC. One adder is the same as the CORDIC, no? I guess the difference is you only need one CORDIC while for a sine that is not an approximation you need two multipliers. I don't see how one would be faster than the other except for the case of a dedicated multiplier being much faster. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 15:19:50 -0500 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 24 Dec 2014 20:19:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="72f16bed1b42f4f6b518c584e62de743"; logging-data="385"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182oeis4qAwZOois8r+OuGa" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:ZataK4YgyypZSkH5p5V4+5noYzE= Xref: mx02.eternal-september.org comp.dsp:52940 comp.lang.vhdl:8004 On 12/24/14 4:13 AM, rickman wrote: > On 12/24/2014 3:24 AM, Rob Doyle wrote: >> On 12/23/2014 9:40 PM, rickman wrote: >>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>> >>>>> ..... (a whole bunch of stuff) > so, Rick, did that built-in notch filter make any sense to you? it's so cheap in software that i would think it would be cheap in VHDL or whatever your hardware language is. and i would just do LUT with linear interpolation. extend the table by one point so that LUT[N] = LUT[0] and you won't have to worry about an additional wrap-around in the linear interpolation. linear interpolation has a sinc^2 frequency response, so it puts zeros smack into the middle of images which reduces their amplitude a lot if the content frequency is much less than the sample rate. if your LUT length is decently long (like 512 or 1K or more), you'll do pretty good regarding the "purity" of your sinusoid. and with a perfectly tuned notch filter with, say, a 1/3 octave BW, you'll know exactly what your impurities are in either time domain or frequency domain (if you FFT it). -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 16:43:57 -0500 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Dec 2014 21:43:44 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17858"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18J+YcO/+5rlRpo2OPWva4E" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:KpXrkxSTr6aH3dMfYljKfLvQRXc= Xref: mx02.eternal-september.org comp.dsp:52942 comp.lang.vhdl:8005 On 12/24/2014 3:19 PM, robert bristow-johnson wrote: > On 12/24/14 4:13 AM, rickman wrote: >> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>> On 12/23/2014 9:40 PM, rickman wrote: >>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>> >>>>>> ..... (a whole bunch of stuff) >> > > so, Rick, did that built-in notch filter make any sense to you? it's so > cheap in software that i would think it would be cheap in VHDL or > whatever your hardware language is. > > and i would just do LUT with linear interpolation. extend the table by > one point so that LUT[N] = LUT[0] and you won't have to worry about an > additional wrap-around in the linear interpolation. linear > interpolation has a sinc^2 frequency response, so it puts zeros smack > into the middle of images which reduces their amplitude a lot if the > content frequency is much less than the sample rate. if your LUT length > is decently long (like 512 or 1K or more), you'll do pretty good > regarding the "purity" of your sinusoid. > > and with a perfectly tuned notch filter with, say, a 1/3 octave BW, > you'll know exactly what your impurities are in either time domain or > frequency domain (if you FFT it). I thought I replied about the notch filter. I"m not clear on what it buys me. If I FFT the data without the filter I get the same spectrum with the signal present which does not interfere with the spectrum. So what is the point? None of the analysis stuff will be implemented in hardware, so that is not an issue. BTW, in a sine table for linear interpolation, I don't use sine(0) as the value in LUT(0). I give the points a half step phase offset with the linear interp signed. I also offset the values to minimize the error over the step range which will be interpolated. BTW, LUT(N) won't equal LUT(0). Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. In my table each of the values are non-zero and not 1 although if the table is large enough, the value of LUT(N-1) is also 1. Having a table of 2^N+1 entries is a PITA in hardware. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: robert bristow-johnson Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 18:56:41 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: rbj@audioimagination.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 24 Dec 2014 23:56:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b1de198917c3b7d2f6897de3aaab5522"; logging-data="11560"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18CD1IerjYwWJqne/DaezVf" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.28) Gecko/20120306 Thunderbird/3.1.20 In-Reply-To: Cancel-Lock: sha1:R8Ec5PbsJX63G81RKzFVywfkmpA= Xref: mx02.eternal-september.org comp.dsp:52943 comp.lang.vhdl:8006 On 12/24/14 4:43 PM, rickman wrote: > On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >> On 12/24/14 4:13 AM, rickman wrote: >>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>> >>>>>>> ..... (a whole bunch of stuff) >>> >> ... >> >> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >> you'll know exactly what your impurities are in either time domain or >> frequency domain (if you FFT it). > > I thought I replied about the notch filter. I"m not clear on what it > buys me. If I FFT the data without the filter I get the same spectrum > with the signal present which does not interfere with the spectrum. do you know exactly what to subtract from the FFT to get whatever your residual nasty stuff is? is that bump a sidelobe of your windowed sinusoid or is it part of the "impurity" that you're measuring? > So > what is the point? None of the analysis stuff will be implemented in > hardware, so that is not an issue. > > BTW, in a sine table for linear interpolation, I don't use sine(0) as > the value in LUT(0). i don't think that matters. > I give the points a half step phase offset with the > linear interp signed. nor that. > I also offset the values to minimize the error > over the step range which will be interpolated. so it's kinda an optimal phase offset that gets your quantized sine values the least error (however the total error is defined). > BTW, LUT(N) won't equal LUT(0). it's N+1 points instead of N. so it's the same N points you would have had anyway, with one more added. > Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. okay. i guess i'm looking at resources more like a software guy would. if i were coding this for a DSP chip or something, i would just quadruple the number of entries and have a single cycle of the waveform, whatever it is. > In my table each of the values are non-zero and not 1 although if > the table is large enough, the value of LUT(N-1) is also 1. Having a > table of 2^N+1 entries is a PITA in hardware. i understand. ((2*pi)/N)/2 radians offset so the points are the same symmetry for each quadrant. and then it's sign manipulation that the hardware folk don't mind fiddling with. but you still know the frequency in advance and a notch filter can be tuned to that frequency. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge." From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 19:48:22 -0500 Organization: A noiseless patient Spider Lines: 91 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 25 Dec 2014 00:48:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QbRjf6u47Bdizo9m7oCxa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:MN1cx0prhuArNe+uz/SAIjHYcq0= Xref: mx02.eternal-september.org comp.dsp:52944 comp.lang.vhdl:8007 On 12/24/2014 6:56 PM, robert bristow-johnson wrote: > On 12/24/14 4:43 PM, rickman wrote: >> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>> On 12/24/14 4:13 AM, rickman wrote: >>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>> >>>>>>>> ..... (a whole bunch of stuff) >>>> >>> > ... >>> >>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>> you'll know exactly what your impurities are in either time domain or >>> frequency domain (if you FFT it). >> >> I thought I replied about the notch filter. I"m not clear on what it >> buys me. If I FFT the data without the filter I get the same spectrum >> with the signal present which does not interfere with the spectrum. > > do you know exactly what to subtract from the FFT to get whatever your > residual nasty stuff is? is that bump a sidelobe of your windowed > sinusoid or is it part of the "impurity" that you're measuring? I believe you are making this too complex. The measurement is a one time thing. I can use as large a transform as I am willing to wait for and therefore minimize the sidelobes. The measurement should be good enough that if I can't measure it, I won't really care about it. Check out these plots... https://sites.google.com/site/fpgastuff/dds_oddities.pdf The last page has some interesting data. >> So >> what is the point? None of the analysis stuff will be implemented in >> hardware, so that is not an issue. >> >> BTW, in a sine table for linear interpolation, I don't use sine(0) as >> the value in LUT(0). > > i don't think that matters. > >> I give the points a half step phase offset with the >> linear interp signed. > > nor that. > >> I also offset the values to minimize the error >> over the step range which will be interpolated. > > so it's kinda an optimal phase offset that gets your quantized sine > values the least error (however the total error is defined). > >> BTW, LUT(N) won't equal LUT(0). > > it's N+1 points instead of N. so it's the same N points you would have > had anyway, with one more added. > >> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. > > okay. i guess i'm looking at resources more like a software guy would. > if i were coding this for a DSP chip or something, i would just > quadruple the number of entries and have a single cycle of the waveform, > whatever it is. Even in software that can get expensive. The LUT is O(2^N) in size so you don't want N to get too large. *Much* better to use your N for storing useful data rather than duplicate info. >> In my table each of the values are non-zero and not 1 although if >> the table is large enough, the value of LUT(N-1) is also 1. Having a >> table of 2^N+1 entries is a PITA in hardware. > > i understand. ((2*pi)/N)/2 radians offset so the points are the same > symmetry for each quadrant. and then it's sign manipulation that the > hardware folk don't mind fiddling with. > > but you still know the frequency in advance and a notch filter can be > tuned to that frequency. If there is a purpose to it. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Wed, 24 Dec 2014 19:50:26 -0500 Organization: A noiseless patient Spider Lines: 98 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Thu, 25 Dec 2014 00:50:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Kj3ApprO2QhjL6EhWhlpN" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:wWXzFXhaVYDENtYU0lVsnV+JDpI= Xref: mx02.eternal-september.org comp.dsp:52945 comp.lang.vhdl:8008 On 12/24/2014 7:48 PM, rickman wrote: > On 12/24/2014 6:56 PM, robert bristow-johnson wrote: >> On 12/24/14 4:43 PM, rickman wrote: >>> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>>> On 12/24/14 4:13 AM, rickman wrote: >>>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>>> >>>>>>>>> ..... (a whole bunch of stuff) >>>>> >>>> >> ... >>>> >>>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>>> you'll know exactly what your impurities are in either time domain or >>>> frequency domain (if you FFT it). >>> >>> I thought I replied about the notch filter. I"m not clear on what it >>> buys me. If I FFT the data without the filter I get the same spectrum >>> with the signal present which does not interfere with the spectrum. >> >> do you know exactly what to subtract from the FFT to get whatever your >> residual nasty stuff is? is that bump a sidelobe of your windowed >> sinusoid or is it part of the "impurity" that you're measuring? > > I believe you are making this too complex. The measurement is a one > time thing. I can use as large a transform as I am willing to wait for > and therefore minimize the sidelobes. The measurement should be good > enough that if I can't measure it, I won't really care about it. > > Check out these plots... > > https://sites.google.com/site/fpgastuff/dds_oddities.pdf > > The last page has some interesting data. I hit send too quickly. I also meant to point out that the spurs of interest are the ones closer to the carrier. How well can I filter the carrier without filtering the side lobes? >>> So >>> what is the point? None of the analysis stuff will be implemented in >>> hardware, so that is not an issue. >>> >>> BTW, in a sine table for linear interpolation, I don't use sine(0) as >>> the value in LUT(0). >> >> i don't think that matters. >> >>> I give the points a half step phase offset with the >>> linear interp signed. >> >> nor that. >> >>> I also offset the values to minimize the error >>> over the step range which will be interpolated. >> >> so it's kinda an optimal phase offset that gets your quantized sine >> values the least error (however the total error is defined). >> >>> BTW, LUT(N) won't equal LUT(0). >> >> it's N+1 points instead of N. so it's the same N points you would have >> had anyway, with one more added. >> >>> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. >> >> okay. i guess i'm looking at resources more like a software guy would. >> if i were coding this for a DSP chip or something, i would just >> quadruple the number of entries and have a single cycle of the waveform, >> whatever it is. > > Even in software that can get expensive. The LUT is O(2^N) in size so > you don't want N to get too large. *Much* better to use your N for > storing useful data rather than duplicate info. > > >>> In my table each of the values are non-zero and not 1 although if >>> the table is large enough, the value of LUT(N-1) is also 1. Having a >>> table of 2^N+1 entries is a PITA in hardware. >> >> i understand. ((2*pi)/N)/2 radians offset so the points are the same >> symmetry for each quadrant. and then it's sign manipulation that the >> hardware folk don't mind fiddling with. >> >> but you still know the frequency in advance and a notch filter can be >> tuned to that frequency. > > If there is a purpose to it. > -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 10:41:28 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 65 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.dsp:52948 comp.lang.vhdl:8009 In comp.dsp Rob Doyle wrote: > On 12/23/2014 6:10 PM, robert bristow-johnson wrote: (snip) >> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >> a while back), but i always thought that CORDIC did essentially >> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] > Yes. So far. So good. These are my notes if anyone is interested... > [snip] > Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase > accumulator for an NCO application. > Factor out the cos(theta): > x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} > y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} > If you select tan(theta) from the set of 1/(2**i) > then [1] this becomes: Nice if you are doing it in binary, but many hand calculators do it in decimal. I believe I have seen the explanation once, but it is much harder to find than the binary version. This goes back to at least the beginning of HP hand calculators. > x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} > y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} > At this point you might be thinking "Holy crap. That's one heck of a > constraint!" Yeh... but keep reading anyway. > You can drop the cos(theta) common term. It's just a gain term that > rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. > x[n] = x[n-1] - y[n-1] / 2**i > y[n] = y[n-1] + x[n-1] / 2**i > or (assuming twos complement math) - simply: > x[n] = x[n-1] - y[n-1] >> i > y[n] = y[n-1] + x[n-1] >> i > where >> is a shift right operation > [1] As this point it seems as if an *extreme* limitation has been placed > on the selection of rotation angles. The equation above only describes > how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of > the following angles: > atan(1) (45.000000000000000000000000000000 degrees) > atan(1/2) (26.565051177077989351572193720453 degrees) > atan(1/4) (14.036243467926478582892320159163 degrees) > atan(1/8) (7.1250163489017975619533008412068 degrees) > atan(1/16) (3.5763343749973510306847789144588 degrees) > atan(1/32) (1.7899106082460693071502497760791 degrees) (snip) -- glen From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 15:52:36 GMT Organization: Anchor Hill Communications Lines: 86 Message-ID: <549c32a9.931041360@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JUCXvqegKro0z4wjz806vlvYkJnMMvGI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:rwBPf1kU6NIK9QE9QjgrxcMgCac= Xref: mx02.eternal-september.org comp.dsp:52949 comp.lang.vhdl:8010 On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >> >>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>> On Mon, 22 Dec 2014 15:17:23 -0700, Rob Doyle >>>> wrote: >>>> >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am wondering if an FFT >>>>>>>>>> is the best way to do this. I'm mainly concerned with the "close in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase accumulator)? or >>>>>>> can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the sinusoid and >>>>>>> with appropriate initial states, y[-1] and y[-2] to result in the >>>>>>> amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, since >>>>>> it is easily implemented in hardware. That's a general architecture >>>>>> that is well-known and can be adjusted to produce very clean local >>>>>> oscillators. If somebody tried to sell me a block of IP with an >>>>>> "NCO" built some other way I'd be asking a lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They pipeline >>>>> nicely and are therefore very fast, they require no multipliers [1], >>>>> they generate quadrature outputs for free, they can perform frequency >>>>> translations for free (again no multipliers), and they are simple prove >>>>> numerical accuracy. >>>> >>>> CORDICs are fine when and where they make sense, but they are often >>>> not the best tradeoff. If you have no memory, no multipliers, or >>>> gates are way cheaper than memory, and if the latency is tolerable, >>>> then a CORDIC may be a good option. >>>> >>>>> [1] Maybe not a huge issue these days. The LUT-based NCOs requires two >>>>> multipliers to combine the coarse and fine LUTs (four multipliers if you >>>>> need a complex NCO output) and perhaps another four multipliers if you >>>>> need to do a frequency translation. >>>> >>>> Many applications don't need separate LUTs to get the required >>>> performance, and even then, or even in the case of complex output, it >>>> can be done without multipliers. >>> >>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>> based NCO without LUTs and unless you are using a very coarse >>> approximation, without multipliers. >> >> Not sure what you're asking. You a need a LUT, but just one in many >> cases. Having a dual-ported single LUT is easy in an FPGA and >> usually in silicon as well. >> >> What makes a multiplier necessary? I've never found the need, but my >> apps are limited to comm. > >Maybe we aren't on the same page. The multiplier is there for the fine >adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >fine. But if you want better performance the single LUT approach >requires *very* large tables. There are a lot of tricks that can be used to keep the table size down. I've mentioned one already. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 15:55:24 GMT Organization: Anchor Hill Communications Lines: 199 Message-ID: <549c32f5.931117005@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190mCWuptpvbRsy0aXutr6ti+bYUqXzdOs=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:daVWJ/sri8nhZ+dA/rh0VMoMOug= Xref: mx02.eternal-september.org comp.dsp:52950 comp.lang.vhdl:8011 On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle wrote: >On 12/23/2014 9:40 PM, rickman wrote: >> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>> >>>> this did not seem to get posted so i am reposting. sorry for any >>>> repeated post. >>>> >>>> On 12/22/14 5:17 PM, Rob Doyle wrote: >>>>> On 12/21/2014 5:13 PM, Eric Jacobsen wrote: >>>>>> On Sun, 21 Dec 2014 14:52:40 -0500, robert bristow-johnson >>>>>> wrote: >>>>>> >>>>>>> On 12/19/14 11:04 PM, Eric Jacobsen wrote: >>>>>>>> On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson >>>>>>>> wrote: >>>>>>>> >>>>>>>>> On 12/19/14 10:06 AM, rickman wrote: >>>>>>>>>> I want to analyze the output of a DDS circuit and am >>>>>>>>>> wondering if an FFT is the best way to do this. I'm >>>>>>>>>> mainly concerned with the "close >>>> in" >>>>>>>>>> spurs that are often generated by a DDS. >>>>>>>>> >>>>>>>>> i still get the concepts of DDS and NCO mixed up. what are >>>>>>>>> the differences? >>>>>>>> >>>>>>>> One is spelled DDS and the other is spelled NCO. >>>>>>> >>>>>>> is the NCO the typical table-lookup kind (with phase >>>>>>> accumulator)? or can it be algorithmic? like >>>>>>> >>>>>>> y[n] = (2*cos(omega_0))*y[n-1] - y[n-2] >>>>>>> >>>>>>> where omega_0 is the normalized angular frequency of the >>>>>>> sinusoid and with appropriate initial states, y[-1] and y[-2] >>>>>>> to result in the amplitude and initial phase desired. >>>>>>> >>>>>>> is that an NCO that can be used in this DDS? or must it be >>>>>>> LUT? >>>>>> >>>>>> Generally NCO or DDS refers to a phase accumulator with a LUT, >>>>>> since it is easily implemented in hardware. That's a general >>>>>> architecture that is well-known and can be adjusted to produce >>>>>> very clean local oscillators. If somebody tried to sell me a >>>>>> block of IP with an "NCO" built some other way I'd be asking a >>>>>> lot of questions. >>>>> >>>>> I have built NCOs using CORDIC rotators. No lookup tables. They >>>>> pipeline nicely and are therefore very fast, they require no >>>>> multipliers [1], >>>> >>>> ??? >>>> >>>> i don't s'pose Ray Andraka is hanging around (he was Dr. CORDIC here >>>> a while back), but i always thought that CORDIC did essentially >>>> >>>> x[n] = cos(2*pi*f0/Fs) * x[n-1] - sin(2*pi*f0/Fs) * y[n-1] >>>> y[n] = sin(2*pi*f0/Fs) * x[n-1] + cos(2*pi*f0/Fs) * y[n-1] >>> >>> Yes. So far. So good. These are my notes if anyone is interested... >>> >>> [snip] >>> >>> Assume theta = 2*pi*f0*t/fs, i.e., theta is the output of a phase >>> accumulator for an NCO application. >>> >>> Factor out the cos(theta): >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] tan(theta)} >>> y[n] = cos(theta) {y[n-1] + x[n-1] tan(theta)} >>> >>> If you select tan(theta) from the set of 1/(2**i) then [1] this becomes: >>> >>> x[n] = cos(theta) {x[n-1] - y[n-1] / 2**i} >>> y[n] = cos(theta) {y[n-1] + x[n-1] / 2**i} >>> >>> At this point you might be thinking "Holy crap. That's one heck of a >>> constraint!" Yeh... but keep reading anyway. >>> >>> You can drop the cos(theta) common term. It's just a gain term that >>> rapidly converges to 1.647. Therefore the gain of a CORDIC is not 0 dB. >>> >>> x[n] = x[n-1] - y[n-1] / 2**i >>> y[n] = y[n-1] + x[n-1] / 2**i >>> >>> or (assuming twos complement math) - simply: >>> >>> x[n] = x[n-1] - y[n-1] >> i >>> y[n] = y[n-1] + x[n-1] >> i >>> >>> where >> is a shift right operation >>> >>> [1] As this point it seems as if an *extreme* limitation has been placed >>> on the selection of rotation angles. The equation above only describes >>> how to rotate an input signal by tan(theta) = 1/(2**i) - or by one of >>> the following angles: >>> >>> atan(1) (45.000000000000000000000000000000 degrees) >>> atan(1/2) (26.565051177077989351572193720453 degrees) >>> atan(1/4) (14.036243467926478582892320159163 degrees) >>> atan(1/8) (7.1250163489017975619533008412068 degrees) >>> atan(1/16) (3.5763343749973510306847789144588 degrees) >>> atan(1/32) (1.7899106082460693071502497760791 degrees) >>> >>> ...and so forth. >>> >>> The equation above does not describe how to rotate an input signal an >>> arbitrary angle! Although this is true; all is not lost. >>> >>> Notice that in general that theta/2 < tan(theta). >>> >>> This truth allows the CORDIC to be used iteratively to rotate any input >>> to any angle with any precision. IMO this is the genius of the CORDIC. >>> >>> I probably should have mentioned that you swap the rotation direction by >>> flipping the additions and subtractions. >>> >>> The term z[n] is introduced to accumulate the angle as the CORDIC >>> iterates. The term d[n] swaps the direction of rotation. Finally the >>> familiar recursive CORDIC equation can be written as follows: >>> >>> x[n] = x[n-1] - d[n] y[n-1] >> i >>> y[n] = y[n-1] + d[n] x[n-1] >> i >>> z[n] = z[n-1] - d[n] tan(1/2**i) >>> >>> where: >>> >>> d[n] is +1 for z[n-1] < theta. Clockwise rotation next. >>> d[n] is -1 for z[n-1] > theta. Counter-clockwise rotation next. >>> >>> No multiplies here. >> >> But this is the same as a multiply in terns of complexity, no? One >> large difference is that a multiply can be supported in commonly >> available hardware while this algorithm requires dedicated hardware or >> iterative software. > >I agree that the CORDIC has the same complexity as a multiply. I agree >that table-based algorithms using multipliers use less FPGA fabric. > >I was simply pointing out that there might be places where a CORDIC has >advantages over LUT-based NCOs. > >Especially if have ROM or multiplier limitations. > >I also wanted to point out that if you need to do a 20-bit (using your >120dB example) complex downconversion for example, the CORDIC still >requires zero multipliers. > >If you want to do a 20-bit complex downconversion using a table-based >NCO followed by a complex mixer, you might need a *lot* of multipliers. >If you only have an 18-bit multiplier, each multiplication requires >(maybe up to) 4 multiplier blocks and you need 8 multiplications. > >I also /suspect/ that for any given device technology the CORDIC will >execute at higher speeds. > >Thats all... That's been my experience; that if multipliers are scarce or too expensive, or memory is scarce or too expensive, then a CORDIC is a nice back-up option. These days multipliers and memory are both plentiful in most platforms, so CORDICs just aren't as useful as they used to be. The latency is sometimes an issue as well. There are still some places where they make sense, though. >>> The CORDIC simply does a successive approximation to the angle - >>> rotating the angle clockwise or counter-clockwise by these limited >>> selection of angles as necessary to converge on the desired angle. Each >>> time the iteration occurs, the angle error is reduced by at least half. >>> >>>> doesn't that require a few multiplications? >>> >>> Nope. Just adds/subtracts - the sign of the angle error determines which >>> direction to rotate on the next iteration. If this is pipelined, the >>> shifts aren't real - they just select which bits of the previous >>> iteration are used on the next iteration. The tan(1/2**i) term is a >>> constant for each iteration. >>> >>> As an implementation detail, it saves hardware if you iterate from >>> the angle toward zero instead of from zero toward the angle. If you do >>> that, the sign of z[i] is the direction of rotation. It saves a >>> magnitude compare for each iteration. >>> >>> Rob. >> >> > Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:03:54 GMT Organization: Anchor Hill Communications Lines: 95 Message-ID: <549c338c.931268482@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="7868"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mIaCruTz3sORVPFa9lRaYd7p3u3mptWw=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-0, 12/25/2014), Outbound message Cancel-Lock: sha1:P6Gew+S8yRUFDrUvI6zQOwer59Y= Xref: mx02.eternal-september.org comp.dsp:52951 comp.lang.vhdl:8012 On Wed, 24 Dec 2014 18:56:41 -0500, robert bristow-johnson wrote: >On 12/24/14 4:43 PM, rickman wrote: >> On 12/24/2014 3:19 PM, robert bristow-johnson wrote: >>> On 12/24/14 4:13 AM, rickman wrote: >>>> On 12/24/2014 3:24 AM, Rob Doyle wrote: >>>>> On 12/23/2014 9:40 PM, rickman wrote: >>>>>> On 12/23/2014 11:02 PM, Rob Doyle wrote: >>>>>>> On 12/23/2014 6:10 PM, robert bristow-johnson wrote: >>>>>>>> >>>>>>>> ..... (a whole bunch of stuff) >>>> >>> >... >>> >>> and with a perfectly tuned notch filter with, say, a 1/3 octave BW, >>> you'll know exactly what your impurities are in either time domain or >>> frequency domain (if you FFT it). >> >> I thought I replied about the notch filter. I"m not clear on what it >> buys me. If I FFT the data without the filter I get the same spectrum >> with the signal present which does not interfere with the spectrum. > >do you know exactly what to subtract from the FFT to get whatever your >residual nasty stuff is? is that bump a sidelobe of your windowed >sinusoid or is it part of the "impurity" that you're measuring? > >> So >> what is the point? None of the analysis stuff will be implemented in >> hardware, so that is not an issue. >> >> BTW, in a sine table for linear interpolation, I don't use sine(0) as >> the value in LUT(0). > >i don't think that matters. > >> I give the points a half step phase offset with the >> linear interp signed. > >nor that. Actually, not having a zero entries in the table for the zero crossings can help solve some common problems with artifacts like spurs (for oscillators) and jitter (for clock generators). The case for the clock output is easy to explain, since the MSB duty cycle is not symmetric when there are two zero entries. Just offsetting the phase a tiny bit, even to just one LSB present in the table output near the zero crossing, makes the MSB duty cycle 50% in the table. >> I also offset the values to minimize the error >> over the step range which will be interpolated. > >so it's kinda an optimal phase offset that gets your quantized sine >values the least error (however the total error is defined). > >> BTW, LUT(N) won't equal LUT(0). > >it's N+1 points instead of N. so it's the same N points you would have >had anyway, with one more added. Which means you just doubled the size of the memory. >> Only 90° is stored so that in your table LUT(0) = 0 and LUT(256) = 1. > >okay. i guess i'm looking at resources more like a software guy would. > if i were coding this for a DSP chip or something, i would just >quadruple the number of entries and have a single cycle of the waveform, >whatever it is. A quarter cycle is all that's really needed. >> In my table each of the values are non-zero and not 1 although if >> the table is large enough, the value of LUT(N-1) is also 1. Having a >> table of 2^N+1 entries is a PITA in hardware. > >i understand. ((2*pi)/N)/2 radians offset so the points are the same >symmetry for each quadrant. and then it's sign manipulation that the >hardware folk don't mind fiddling with. > >but you still know the frequency in advance and a notch filter can be >tuned to that frequency. If there's only one frequency needed and it's known in advance, you may not need a DDS/NCO. Usually an NCO is used because it needs to vary a bit either for tracking or tuning or other adjustments. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 11:56:15 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 16:56:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="18965"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1//txFjuZhulgC6NjCXP50j" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c32a9.931041360@news.eternal-september.org> Cancel-Lock: sha1:HHsWOqKZ+J41Hb6+vg2LvtHqMkA= Xref: mx02.eternal-september.org comp.dsp:52954 comp.lang.vhdl:8013 On 12/25/2014 10:52 AM, Eric Jacobsen wrote: > On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: > >> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>> >>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>> >>>>> Many applications don't need separate LUTs to get the required >>>>> performance, and even then, or even in the case of complex output, it >>>>> can be done without multipliers. >>>> >>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>> based NCO without LUTs and unless you are using a very coarse >>>> approximation, without multipliers. >>> >>> Not sure what you're asking. You a need a LUT, but just one in many >>> cases. Having a dual-ported single LUT is easy in an FPGA and >>> usually in silicon as well. >>> >>> What makes a multiplier necessary? I've never found the need, but my >>> apps are limited to comm. >> >> Maybe we aren't on the same page. The multiplier is there for the fine >> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >> fine. But if you want better performance the single LUT approach >> requires *very* large tables. > > There are a lot of tricks that can be used to keep the table size > down. I've mentioned one already. And what was that? You have made some 20 or more posts in this thread, I don't feel like weeding through all of them to find this. Reading back through this thread it seems like your posts are intended to be mysterious rather than informative. Every one leaves enough unsaid that more questions are needed. -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 12:02:57 -0500 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 17:02:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20241"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZRRLmOa10SL4+tI+FiJ1Y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c32f5.931117005@news.eternal-september.org> Cancel-Lock: sha1:fsVGX/iCPD+mUCkWc5oOPIXSswU= Xref: mx02.eternal-september.org comp.dsp:52955 comp.lang.vhdl:8014 On 12/25/2014 10:55 AM, Eric Jacobsen wrote: > On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle > wrote: > >> I agree that the CORDIC has the same complexity as a multiply. I agree >> that table-based algorithms using multipliers use less FPGA fabric. >> >> I was simply pointing out that there might be places where a CORDIC has >> advantages over LUT-based NCOs. >> >> Especially if have ROM or multiplier limitations. >> >> I also wanted to point out that if you need to do a 20-bit (using your >> 120dB example) complex downconversion for example, the CORDIC still >> requires zero multipliers. >> >> If you want to do a 20-bit complex downconversion using a table-based >> NCO followed by a complex mixer, you might need a *lot* of multipliers. >> If you only have an 18-bit multiplier, each multiplication requires >> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >> >> I also /suspect/ that for any given device technology the CORDIC will >> execute at higher speeds. >> >> Thats all... > > That's been my experience; that if multipliers are scarce or too > expensive, or memory is scarce or too expensive, then a CORDIC is a > nice back-up option. These days multipliers and memory are both > plentiful in most platforms, so CORDICs just aren't as useful as they > used to be. I think the distinction between a multiply and the CORDIC technique is bogus. CORDIC is an iterative process including all the operations that make up a multiply. The only difference is that in many cases there is hardware available that facilitates execution of generic multiplies while the CORDIC must be implemented in detail in every case. > The latency is sometimes an issue as well. > > There are still some places where they make sense, though. Care to explain? -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 20:56:47 GMT Organization: Anchor Hill Communications Lines: 47 Message-ID: <549c79aa.949218051@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/eSWyXSi9amODB2mcpd4YZttdMnQ3zPHE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:m4VIPaWKBbbGrb3nnC2Ua4W0mPI= Xref: mx02.eternal-september.org comp.dsp:52958 comp.lang.vhdl:8015 On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >> >>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>> >>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>> >>>>>> Many applications don't need separate LUTs to get the required >>>>>> performance, and even then, or even in the case of complex output, it >>>>>> can be done without multipliers. >>>>> >>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>> based NCO without LUTs and unless you are using a very coarse >>>>> approximation, without multipliers. >>>> >>>> Not sure what you're asking. You a need a LUT, but just one in many >>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>> usually in silicon as well. >>>> >>>> What makes a multiplier necessary? I've never found the need, but my >>>> apps are limited to comm. >>> >>> Maybe we aren't on the same page. The multiplier is there for the fine >>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>> fine. But if you want better performance the single LUT approach >>> requires *very* large tables. >> >> There are a lot of tricks that can be used to keep the table size >> down. I've mentioned one already. > >And what was that? You have made some 20 or more posts in this thread, >I don't feel like weeding through all of them to find this. Reading >back through this thread it seems like your posts are intended to be >mysterious rather than informative. Every one leaves enough unsaid that >more questions are needed. I can't divulge trade secrets or proprietary information that doesn't belong to me. I can, however, hint in directions of benefit. Take it or leave it. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:01:22 GMT Organization: Anchor Hill Communications Lines: 66 Message-ID: <549c7a34.949356689@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="4724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+xL7Evvl68wG2VReWB+HLbcTiXY25TGro=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:WYaaooCe/YOXdw/V5MOZzl5rURA= Xref: mx02.eternal-september.org comp.dsp:52959 comp.lang.vhdl:8016 On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: >On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >> wrote: >> >>> I agree that the CORDIC has the same complexity as a multiply. I agree >>> that table-based algorithms using multipliers use less FPGA fabric. >>> >>> I was simply pointing out that there might be places where a CORDIC has >>> advantages over LUT-based NCOs. >>> >>> Especially if have ROM or multiplier limitations. >>> >>> I also wanted to point out that if you need to do a 20-bit (using your >>> 120dB example) complex downconversion for example, the CORDIC still >>> requires zero multipliers. >>> >>> If you want to do a 20-bit complex downconversion using a table-based >>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>> If you only have an 18-bit multiplier, each multiplication requires >>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>> >>> I also /suspect/ that for any given device technology the CORDIC will >>> execute at higher speeds. >>> >>> Thats all... >> >> That's been my experience; that if multipliers are scarce or too >> expensive, or memory is scarce or too expensive, then a CORDIC is a >> nice back-up option. These days multipliers and memory are both >> plentiful in most platforms, so CORDICs just aren't as useful as they >> used to be. > >I think the distinction between a multiply and the CORDIC technique is >bogus. CORDIC is an iterative process including all the operations that >make up a multiply. The only difference is that in many cases there is >hardware available that facilitates execution of generic multiplies >while the CORDIC must be implemented in detail in every case. In the past (some of it long ago) when we did tradeoffs on using a CORDIC or an NCO, or a CORDIC or a complex mix implemented with multipliers, it comes down to resource availability. If multipliers are available (either in FPGA fabric or as a module in silicon), then a mixer is generally much more efficient with multipliers. If the memory is available, then a LUT with a phase accumulator is hard to beat for a numeric oscillator. The latency may also tilt the tradeoff further away from the CORDIC. They certainly have their place, but those places have gotten more limited as silicon resources get cheaper. > >> The latency is sometimes an issue as well. >> >> There are still some places where they make sense, though. > >Care to explain? > >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:08:45 -0500 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 21:08:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6442"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183pkh0RhB/DOGBIktewO2o" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c79aa.949218051@news.eternal-september.org> Cancel-Lock: sha1:Dgq4sOvRQm1CT+fNmnnm3WvILqw= Xref: mx02.eternal-september.org comp.dsp:52960 comp.lang.vhdl:8017 On 12/25/2014 3:56 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: > >> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>> >>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>> >>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>> >>>>>>> Many applications don't need separate LUTs to get the required >>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>> can be done without multipliers. >>>>>> >>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>> approximation, without multipliers. >>>>> >>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>> usually in silicon as well. >>>>> >>>>> What makes a multiplier necessary? I've never found the need, but my >>>>> apps are limited to comm. >>>> >>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>> fine. But if you want better performance the single LUT approach >>>> requires *very* large tables. >>> >>> There are a lot of tricks that can be used to keep the table size >>> down. I've mentioned one already. >> >> And what was that? You have made some 20 or more posts in this thread, >> I don't feel like weeding through all of them to find this. Reading >> back through this thread it seems like your posts are intended to be >> mysterious rather than informative. Every one leaves enough unsaid that >> more questions are needed. > > I can't divulge trade secrets or proprietary information that doesn't > belong to me. I can, however, hint in directions of benefit. Take > it or leave it. I have no idea what you are talking about. If you don't have anything to say, why are you bothering to post? I don't even recall the hints. Or are you forbidden from pointing out what those are? You said you had already mentioned a way to reduce table size. What was that? -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 16:13:15 -0500 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 21:13:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8834"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/I1uClhzeKwBRRh1O80df5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c7a34.949356689@news.eternal-september.org> Cancel-Lock: sha1:p2xkTMrovFmYMYpmQWZIKTMZ6eI= Xref: mx02.eternal-september.org comp.dsp:52961 comp.lang.vhdl:8018 On 12/25/2014 4:01 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: > >> On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >>> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >>> wrote: >>> >>>> I agree that the CORDIC has the same complexity as a multiply. I agree >>>> that table-based algorithms using multipliers use less FPGA fabric. >>>> >>>> I was simply pointing out that there might be places where a CORDIC has >>>> advantages over LUT-based NCOs. >>>> >>>> Especially if have ROM or multiplier limitations. >>>> >>>> I also wanted to point out that if you need to do a 20-bit (using your >>>> 120dB example) complex downconversion for example, the CORDIC still >>>> requires zero multipliers. >>>> >>>> If you want to do a 20-bit complex downconversion using a table-based >>>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>>> If you only have an 18-bit multiplier, each multiplication requires >>>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>>> >>>> I also /suspect/ that for any given device technology the CORDIC will >>>> execute at higher speeds. >>>> >>>> Thats all... >>> >>> That's been my experience; that if multipliers are scarce or too >>> expensive, or memory is scarce or too expensive, then a CORDIC is a >>> nice back-up option. These days multipliers and memory are both >>> plentiful in most platforms, so CORDICs just aren't as useful as they >>> used to be. >> >> I think the distinction between a multiply and the CORDIC technique is >> bogus. CORDIC is an iterative process including all the operations that >> make up a multiply. The only difference is that in many cases there is >> hardware available that facilitates execution of generic multiplies >> while the CORDIC must be implemented in detail in every case. > > In the past (some of it long ago) when we did tradeoffs on using a > CORDIC or an NCO, or a CORDIC or a complex mix implemented with > multipliers, it comes down to resource availability. If multipliers > are available (either in FPGA fabric or as a module in silicon), then > a mixer is generally much more efficient with multipliers. If the > memory is available, then a LUT with a phase accumulator is hard to > beat for a numeric oscillator. The latency may also tilt the > tradeoff further away from the CORDIC. > > They certainly have their place, but those places have gotten more > limited as silicon resources get cheaper. Let's assume there is no multiplier blocks and no LUTs. Now how is the CORDIC better than using a multiplies? Just like the CORDIC the multiplies can be done iteratively using virtually the same logic. Speed, in most cases, will be determined by the carry chain in the adder so speed should be about the same. >>> The latency is sometimes an issue as well. >>> >>> There are still some places where they make sense, though. >> >> Care to explain? So where are the places where the CORDIC makes sense? -- Rick From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:32:55 GMT Organization: Anchor Hill Communications Lines: 72 Message-ID: <549c8171.951208826@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="11567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dNbYLZL1qZquayIakBuok9mApxf6vzrE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:dOjJGWvgkcUWyKhh/yldaYgqV0E= Xref: mx02.eternal-september.org comp.dsp:52964 comp.lang.vhdl:8019 On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >> >>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>> >>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>> >>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>> >>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>> can be done without multipliers. >>>>>>> >>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>> approximation, without multipliers. >>>>>> >>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>> usually in silicon as well. >>>>>> >>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>> apps are limited to comm. >>>>> >>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>> fine. But if you want better performance the single LUT approach >>>>> requires *very* large tables. >>>> >>>> There are a lot of tricks that can be used to keep the table size >>>> down. I've mentioned one already. >>> >>> And what was that? You have made some 20 or more posts in this thread, >>> I don't feel like weeding through all of them to find this. Reading >>> back through this thread it seems like your posts are intended to be >>> mysterious rather than informative. Every one leaves enough unsaid that >>> more questions are needed. >> >> I can't divulge trade secrets or proprietary information that doesn't >> belong to me. I can, however, hint in directions of benefit. Take >> it or leave it. > >I have no idea what you are talking about. If you don't have anything >to say, why are you bothering to post? Why do you care whether I post or not? Feel free to put me in your kill file if you don't like my posts. > I don't even recall the hints. >Or are you forbidden from pointing out what those are? No, but it seems to me like unnecessary duplication. There are lots of hints from multiple people scattered throughout the thread, as well as in some of the literature mentioned previously. >You said you had already mentioned a way to reduce table size. What was >that? One way is to store a quarter wave instead of a full cycle. I think that was mentioned more than once, but here it is again just for you. >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 21:34:41 GMT Organization: Anchor Hill Communications Lines: 79 Message-ID: <549c82a3.951515306@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="11567"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Z4lbMEFUCX77+P4QjZF4618iu/0dpjE0=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141225-1, 12/25/2014), Outbound message Cancel-Lock: sha1:SjQl0a5ESQu0Oysef3o/OxhSHJs= Xref: mx02.eternal-september.org comp.dsp:52965 comp.lang.vhdl:8020 On Thu, 25 Dec 2014 16:13:15 -0500, rickman wrote: >On 12/25/2014 4:01 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 12:02:57 -0500, rickman wrote: >> >>> On 12/25/2014 10:55 AM, Eric Jacobsen wrote: >>>> On Wed, 24 Dec 2014 01:24:42 -0700, Rob Doyle >>>> wrote: >>>> >>>>> I agree that the CORDIC has the same complexity as a multiply. I agree >>>>> that table-based algorithms using multipliers use less FPGA fabric. >>>>> >>>>> I was simply pointing out that there might be places where a CORDIC has >>>>> advantages over LUT-based NCOs. >>>>> >>>>> Especially if have ROM or multiplier limitations. >>>>> >>>>> I also wanted to point out that if you need to do a 20-bit (using your >>>>> 120dB example) complex downconversion for example, the CORDIC still >>>>> requires zero multipliers. >>>>> >>>>> If you want to do a 20-bit complex downconversion using a table-based >>>>> NCO followed by a complex mixer, you might need a *lot* of multipliers. >>>>> If you only have an 18-bit multiplier, each multiplication requires >>>>> (maybe up to) 4 multiplier blocks and you need 8 multiplications. >>>>> >>>>> I also /suspect/ that for any given device technology the CORDIC will >>>>> execute at higher speeds. >>>>> >>>>> Thats all... >>>> >>>> That's been my experience; that if multipliers are scarce or too >>>> expensive, or memory is scarce or too expensive, then a CORDIC is a >>>> nice back-up option. These days multipliers and memory are both >>>> plentiful in most platforms, so CORDICs just aren't as useful as they >>>> used to be. >>> >>> I think the distinction between a multiply and the CORDIC technique is >>> bogus. CORDIC is an iterative process including all the operations that >>> make up a multiply. The only difference is that in many cases there is >>> hardware available that facilitates execution of generic multiplies >>> while the CORDIC must be implemented in detail in every case. >> >> In the past (some of it long ago) when we did tradeoffs on using a >> CORDIC or an NCO, or a CORDIC or a complex mix implemented with >> multipliers, it comes down to resource availability. If multipliers >> are available (either in FPGA fabric or as a module in silicon), then >> a mixer is generally much more efficient with multipliers. If the >> memory is available, then a LUT with a phase accumulator is hard to >> beat for a numeric oscillator. The latency may also tilt the >> tradeoff further away from the CORDIC. >> >> They certainly have their place, but those places have gotten more >> limited as silicon resources get cheaper. > >Let's assume there is no multiplier blocks and no LUTs. Now how is the >CORDIC better than using a multiplies? Just like the CORDIC the >multiplies can be done iteratively using virtually the same logic. >Speed, in most cases, will be determined by the carry chain in the adder >so speed should be about the same. It could be there isn't much difference, which means if you have a CORDIC laying around, there may not be a reason to not use it. >>>> The latency is sometimes an issue as well. >>>> >>>> There are still some places where they make sense, though. >>> >>> Care to explain? > >So where are the places where the CORDIC makes sense? > >-- > >Rick Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:41 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Thu, 25 Dec 2014 18:08:54 -0500 Organization: A noiseless patient Spider Lines: 92 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 25 Dec 2014 23:08:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="32014"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xhEulFRZPIe7juyE0p0A6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549c8171.951208826@news.eternal-september.org> Cancel-Lock: sha1:KqwWcax4DryqH5aJju+eB0YIoUY= Xref: mx02.eternal-september.org comp.dsp:52967 comp.lang.vhdl:8021 On 12/25/2014 4:32 PM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: > >> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>> >>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>> >>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>> >>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>> can be done without multipliers. >>>>>>>> >>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>> approximation, without multipliers. >>>>>>> >>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>> usually in silicon as well. >>>>>>> >>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>> apps are limited to comm. >>>>>> >>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>> fine. But if you want better performance the single LUT approach >>>>>> requires *very* large tables. >>>>> >>>>> There are a lot of tricks that can be used to keep the table size >>>>> down. I've mentioned one already. >>>> >>>> And what was that? You have made some 20 or more posts in this thread, >>>> I don't feel like weeding through all of them to find this. Reading >>>> back through this thread it seems like your posts are intended to be >>>> mysterious rather than informative. Every one leaves enough unsaid that >>>> more questions are needed. >>> >>> I can't divulge trade secrets or proprietary information that doesn't >>> belong to me. I can, however, hint in directions of benefit. Take >>> it or leave it. >> >> I have no idea what you are talking about. If you don't have anything >> to say, why are you bothering to post? > > Why do you care whether I post or not? Feel free to put me in your > kill file if you don't like my posts. If you aren't interested in having a conversation, why do you bother to type? Above you said you had already mentioned "one" method already. Clearly that one is not a trade secret. Care to explain what method you are referring to? >> I don't even recall the hints. >> Or are you forbidden from pointing out what those are? > > No, but it seems to me like unnecessary duplication. There are lots > of hints from multiple people scattered throughout the thread, as well > as in some of the literature mentioned previously. Exactly, scattered in some 50 or so messages. If you have something to say, why no say it instead of being so vague? Just tell me which message you are referring to. >> You said you had already mentioned a way to reduce table size. What was >> that? > > One way is to store a quarter wave instead of a full cycle. I think > that was mentioned more than once, but here it is again just for you. Thank you for the response. Yes, that is table reduction 101. Anyone other than a newbie is aware of that. I believe *I* was the one who in this thread pointed it out to someone who said memory is cheap not fully appreciating that memory is order 2^N is size. Even so it is just a factor of four and does nothing to change the fact that memory is anything but cheap if you are looking for high resolution and low distortion. Using MBs of memory to store a LUT is usually not a good trade off. What was the technique *you* mentioned as you indicate above? -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 16:45:35 GMT Organization: Anchor Hill Communications Lines: 107 Message-ID: <549d8ef7.1020206758@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="17051"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1//YAYVSojgLLizsEWQbKRJh1Kzb6jcaZI=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141226-0, 12/26/2014), Outbound message Cancel-Lock: sha1:cEBmjhHQEJnK73pIXHZlNDnjrg4= Xref: mx02.eternal-september.org comp.dsp:52976 comp.lang.vhdl:8022 On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >> >>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>> >>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>> >>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>> can be done without multipliers. >>>>>>>>> >>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>> approximation, without multipliers. >>>>>>>> >>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>> usually in silicon as well. >>>>>>>> >>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>> apps are limited to comm. >>>>>>> >>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>> fine. But if you want better performance the single LUT approach >>>>>>> requires *very* large tables. >>>>>> >>>>>> There are a lot of tricks that can be used to keep the table size >>>>>> down. I've mentioned one already. >>>>> >>>>> And what was that? You have made some 20 or more posts in this thread, >>>>> I don't feel like weeding through all of them to find this. Reading >>>>> back through this thread it seems like your posts are intended to be >>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>> more questions are needed. >>>> >>>> I can't divulge trade secrets or proprietary information that doesn't >>>> belong to me. I can, however, hint in directions of benefit. Take >>>> it or leave it. >>> >>> I have no idea what you are talking about. If you don't have anything >>> to say, why are you bothering to post? >> >> Why do you care whether I post or not? Feel free to put me in your >> kill file if you don't like my posts. > >If you aren't interested in having a conversation, why do you bother to >type? Above you said you had already mentioned "one" method already. >Clearly that one is not a trade secret. Care to explain what method you >are referring to? I did later in the same post. >>> I don't even recall the hints. >>> Or are you forbidden from pointing out what those are? >> >> No, but it seems to me like unnecessary duplication. There are lots >> of hints from multiple people scattered throughout the thread, as well >> as in some of the literature mentioned previously. > >Exactly, scattered in some 50 or so messages. If you have something to >say, why no say it instead of being so vague? Just tell me which >message you are referring to. So you want me to go back and search through the thread for you? Are you not capable of doing that? I'm not at all clear why you think that I should do the search if you're the one that wants the information. >>> You said you had already mentioned a way to reduce table size. What was >>> that? >> >> One way is to store a quarter wave instead of a full cycle. I think >> that was mentioned more than once, but here it is again just for you. > >Thank you for the response. > >Yes, that is table reduction 101. Anyone other than a newbie is aware >of that. I believe *I* was the one who in this thread pointed it out to >someone who said memory is cheap not fully appreciating that memory is >order 2^N is size. Even so it is just a factor of four and does nothing >to change the fact that memory is anything but cheap if you are looking >for high resolution and low distortion. Using MBs of memory to store a >LUT is usually not a good trade off. > >What was the technique *you* mentioned as you indicate above? That was one of them. I mentioned it more than once. In my experience a 4x reduction in memory can be significant, and the quarter-wave trick isn't obvious to some people so I didn't make the assumption that it was. You're welcome. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 12:05:24 -0500 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 26 Dec 2014 17:05:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21348"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Nb4gR7FvRS2mN1oRFyQ+e" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549d8ef7.1020206758@news.eternal-september.org> Cancel-Lock: sha1:AB0al25NbOBt5tFON+ctJ4QnSh4= Xref: mx02.eternal-september.org comp.dsp:52977 comp.lang.vhdl:8023 On 12/26/2014 11:45 AM, Eric Jacobsen wrote: > On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: > >> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>> >>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>> >>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>> can be done without multipliers. >>>>>>>>>> >>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>> approximation, without multipliers. >>>>>>>>> >>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>> usually in silicon as well. >>>>>>>>> >>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>> apps are limited to comm. >>>>>>>> >>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>> requires *very* large tables. >>>>>>> >>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>> down. I've mentioned one already. >>>>>> >>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>> back through this thread it seems like your posts are intended to be >>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>> more questions are needed. >>>>> >>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>> it or leave it. >>>> >>>> I have no idea what you are talking about. If you don't have anything >>>> to say, why are you bothering to post? >>> >>> Why do you care whether I post or not? Feel free to put me in your >>> kill file if you don't like my posts. >> >> If you aren't interested in having a conversation, why do you bother to >> type? Above you said you had already mentioned "one" method already. >> Clearly that one is not a trade secret. Care to explain what method you >> are referring to? > > I did later in the same post. What same post would that be? I'm not sure what "same" means since the context is not clear. >>>> I don't even recall the hints. >>>> Or are you forbidden from pointing out what those are? >>> >>> No, but it seems to me like unnecessary duplication. There are lots >>> of hints from multiple people scattered throughout the thread, as well >>> as in some of the literature mentioned previously. >> >> Exactly, scattered in some 50 or so messages. If you have something to >> say, why no say it instead of being so vague? Just tell me which >> message you are referring to. > > So you want me to go back and search through the thread for you? Are > you not capable of doing that? I'm not at all clear why you think > that I should do the search if you're the one that wants the > information. I'm assuming that you might have more recollection of having made a post than I do of reading it. I did a scan and I never saw any useful comments on table reduction. Everything you posted seems to allude to things but always shies away from actually giving any info. >>>> You said you had already mentioned a way to reduce table size. What was >>>> that? >>> >>> One way is to store a quarter wave instead of a full cycle. I think >>> that was mentioned more than once, but here it is again just for you. >> >> Thank you for the response. >> >> Yes, that is table reduction 101. Anyone other than a newbie is aware >> of that. I believe *I* was the one who in this thread pointed it out to >> someone who said memory is cheap not fully appreciating that memory is >> order 2^N is size. Even so it is just a factor of four and does nothing >> to change the fact that memory is anything but cheap if you are looking >> for high resolution and low distortion. Using MBs of memory to store a >> LUT is usually not a good trade off. >> >> What was the technique *you* mentioned as you indicate above? > > That was one of them. I mentioned it more than once. In my > experience a 4x reduction in memory can be significant, and the > quarter-wave trick isn't obvious to some people so I didn't make the > assumption that it was. > > You're welcome. Yes, a four fold reduction in size can be useful, but like I said, this is sine table 101. Was there anything else of value you have to offer on the topic? -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Fri, 26 Dec 2014 18:15:24 GMT Organization: Anchor Hill Communications Lines: 135 Message-ID: <549da465.1025693142@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="7009"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y05Qsu8LlJfIjxxbwuZLT3M/6hiGRbRk=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141226-0, 12/26/2014), Outbound message Cancel-Lock: sha1:TwBj2udw7cpwt7GQXeeIXhRPJDU= Xref: mx02.eternal-september.org comp.dsp:52979 comp.lang.vhdl:8024 On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >> >>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>> >>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>> >>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>> >>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>> >>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>> approximation, without multipliers. >>>>>>>>>> >>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>> usually in silicon as well. >>>>>>>>>> >>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>> apps are limited to comm. >>>>>>>>> >>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>> requires *very* large tables. >>>>>>>> >>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>> down. I've mentioned one already. >>>>>>> >>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>> back through this thread it seems like your posts are intended to be >>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>> more questions are needed. >>>>>> >>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>> it or leave it. >>>>> >>>>> I have no idea what you are talking about. If you don't have anything >>>>> to say, why are you bothering to post? >>>> >>>> Why do you care whether I post or not? Feel free to put me in your >>>> kill file if you don't like my posts. >>> >>> If you aren't interested in having a conversation, why do you bother to >>> type? Above you said you had already mentioned "one" method already. >>> Clearly that one is not a trade secret. Care to explain what method you >>> are referring to? >> >> I did later in the same post. > >What same post would that be? I'm not sure what "same" means since the >context is not clear. The same one you were responding to at the time. >>>>> I don't even recall the hints. >>>>> Or are you forbidden from pointing out what those are? >>>> >>>> No, but it seems to me like unnecessary duplication. There are lots >>>> of hints from multiple people scattered throughout the thread, as well >>>> as in some of the literature mentioned previously. >>> >>> Exactly, scattered in some 50 or so messages. If you have something to >>> say, why no say it instead of being so vague? Just tell me which >>> message you are referring to. >> >> So you want me to go back and search through the thread for you? Are >> you not capable of doing that? I'm not at all clear why you think >> that I should do the search if you're the one that wants the >> information. > >I'm assuming that you might have more recollection of having made a >post than I do of reading it. I did a scan and I never saw any useful >comments on table reduction. Everything you posted seems to allude to >things but always shies away from actually giving any info. I mentioned the quarter-wave reduction specifically multiple times. Sorry you weren't able to glean anything. Not everybody does. >>>>> You said you had already mentioned a way to reduce table size. What was >>>>> that? >>>> >>>> One way is to store a quarter wave instead of a full cycle. I think >>>> that was mentioned more than once, but here it is again just for you. >>> >>> Thank you for the response. >>> >>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>> of that. I believe *I* was the one who in this thread pointed it out to >>> someone who said memory is cheap not fully appreciating that memory is >>> order 2^N is size. Even so it is just a factor of four and does nothing >>> to change the fact that memory is anything but cheap if you are looking >>> for high resolution and low distortion. Using MBs of memory to store a >>> LUT is usually not a good trade off. >>> >>> What was the technique *you* mentioned as you indicate above? >> >> That was one of them. I mentioned it more than once. In my >> experience a 4x reduction in memory can be significant, and the >> quarter-wave trick isn't obvious to some people so I didn't make the >> assumption that it was. >> >> You're welcome. > >Yes, a four fold reduction in size can be useful, but like I said, this >is sine table 101. > >Was there anything else of value you have to offer on the topic? You can go back and see what's valuable to you, and I can't anticipate what will or won't be. You seem to resent having the quarter-wave trick pointed out to you, so I'm not going to try to guess what you might or might not find obvious. One of the nice things about usenet is that the posts a pretty sticky, so you can go back and review if you want to and take or leave things as you see fit. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 01:35:55 -0500 Organization: A noiseless patient Spider Lines: 150 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 06:35:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9797"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/JO59OGUJ9Mz6tFhC99LiH" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549da465.1025693142@news.eternal-september.org> Cancel-Lock: sha1:fcfVhLGF1c6IuhWkpCm/fg1dOEU= Xref: mx02.eternal-september.org comp.dsp:52984 comp.lang.vhdl:8025 On 12/26/2014 1:15 PM, Eric Jacobsen wrote: > On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: > >> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>> >>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>> >>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>> >>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>> >>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>> >>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>> usually in silicon as well. >>>>>>>>>>> >>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>> apps are limited to comm. >>>>>>>>>> >>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>> requires *very* large tables. >>>>>>>>> >>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>> down. I've mentioned one already. >>>>>>>> >>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>> more questions are needed. >>>>>>> >>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>> it or leave it. >>>>>> >>>>>> I have no idea what you are talking about. If you don't have anything >>>>>> to say, why are you bothering to post? >>>>> >>>>> Why do you care whether I post or not? Feel free to put me in your >>>>> kill file if you don't like my posts. >>>> >>>> If you aren't interested in having a conversation, why do you bother to >>>> type? Above you said you had already mentioned "one" method already. >>>> Clearly that one is not a trade secret. Care to explain what method you >>>> are referring to? >>> >>> I did later in the same post. >> >> What same post would that be? I'm not sure what "same" means since the >> context is not clear. > > The same one you were responding to at the time. At this point it is pretty clear you are just playing with me and have nothing to say. >>>>>> I don't even recall the hints. >>>>>> Or are you forbidden from pointing out what those are? >>>>> >>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>> of hints from multiple people scattered throughout the thread, as well >>>>> as in some of the literature mentioned previously. >>>> >>>> Exactly, scattered in some 50 or so messages. If you have something to >>>> say, why no say it instead of being so vague? Just tell me which >>>> message you are referring to. >>> >>> So you want me to go back and search through the thread for you? Are >>> you not capable of doing that? I'm not at all clear why you think >>> that I should do the search if you're the one that wants the >>> information. >> >> I'm assuming that you might have more recollection of having made a >> post than I do of reading it. I did a scan and I never saw any useful >> comments on table reduction. Everything you posted seems to allude to >> things but always shies away from actually giving any info. > > I mentioned the quarter-wave reduction specifically multiple times. > Sorry you weren't able to glean anything. Not everybody does. I just never read your post in this thread where you mentioned that. That's why I pointed it out to someone who spoke of using the full wave. >>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>> that? >>>>> >>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>> that was mentioned more than once, but here it is again just for you. >>>> >>>> Thank you for the response. >>>> >>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>> of that. I believe *I* was the one who in this thread pointed it out to >>>> someone who said memory is cheap not fully appreciating that memory is >>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>> to change the fact that memory is anything but cheap if you are looking >>>> for high resolution and low distortion. Using MBs of memory to store a >>>> LUT is usually not a good trade off. >>>> >>>> What was the technique *you* mentioned as you indicate above? >>> >>> That was one of them. I mentioned it more than once. In my >>> experience a 4x reduction in memory can be significant, and the >>> quarter-wave trick isn't obvious to some people so I didn't make the >>> assumption that it was. >>> >>> You're welcome. >> >> Yes, a four fold reduction in size can be useful, but like I said, this >> is sine table 101. >> >> Was there anything else of value you have to offer on the topic? > > You can go back and see what's valuable to you, and I can't anticipate > what will or won't be. You seem to resent having the quarter-wave > trick pointed out to you, so I'm not going to try to guess what you > might or might not find obvious. One of the nice things about usenet > is that the posts a pretty sticky, so you can go back and review if > you want to and take or leave things as you see fit. I have read your posts here and I didn't see you mention the quarter wave table or anything else specific. Rather you gave thin references to the fact that "significant" reductions are possible. That's why I asked and so far you have not been able to explain what you meant or point to a post. You just keep repeating that you have already said things. Ok, nuff said. -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 10:33:15 +0100 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 09:32:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b4bd7f96a7efdaa1b5fa87721b3547c4"; logging-data="5537"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rbPECLYBzcG0KWNczR0he" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 In-Reply-To: Cancel-Lock: sha1:SPk3QStB5D7+glkliL8w9O9M4VE= Xref: mx02.eternal-september.org comp.lang.vhdl:8026 > So where are the places where the CORDIC makes sense? rickman, You are annoying with your posts. Use your imagination. Nearly every calculator use cordic instead of LUT for trigonometric functions. Why? (Please don't answer, it's a rhetorical question.) Bart From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 05:25:07 -0500 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549c32f5.931117005@news.eternal-september.org> <549c7a34.949356689@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 10:24:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14277"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tfZnZvVzfHNl+l2LEPclz" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Cancel-Lock: sha1:ao/JFKvXBxuPBhDnAOBg9T7hBjE= Xref: mx02.eternal-september.org comp.lang.vhdl:8027 On 12/27/2014 4:33 AM, Bart Fox wrote: >> So where are the places where the CORDIC makes sense? > rickman, > You are annoying with your posts. > > Use your imagination. > Nearly every calculator use cordic instead of LUT for trigonometric > functions. Why? > (Please don't answer, it's a rhetorical question.) I don't get your post. You say my questions are annoying, and then you ask a "rhetorical" question as if I am supposed to know the answer. If I knew the answer, I wouldn't be asking the question myself. -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: eric.jacobsen@ieee.org (Eric Jacobsen) Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 16:33:10 GMT Organization: Anchor Hill Communications Lines: 165 Message-ID: <549edda8.1105888388@news.eternal-september.org> References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> Reply-To: eric.jacobsen@ieee.org Injection-Info: mx02.eternal-september.org; posting-host="2fa9bbb0ed4892a570792958bf77f0f2"; logging-data="25843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qBPNzii2Cjfu57S7RFdIC3dxvB9xzvwE=" X-Antivirus-Status: Clean X-Newsreader: Forte Free Agent 1.21/32.243 X-Antivirus: avast! (VPS 141227-0, 12/27/2014), Outbound message Cancel-Lock: sha1:jh3dgQKWeaq0tviQNtTyrgX3BdE= Xref: mx02.eternal-september.org comp.dsp:52985 comp.lang.vhdl:8028 On Sat, 27 Dec 2014 01:35:55 -0500, rickman wrote: >On 12/26/2014 1:15 PM, Eric Jacobsen wrote: >> On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >> >>> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>>> >>>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>>> >>>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>>> >>>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>>> >>>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>>> >>>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>>> >>>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>>> >>>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>>> >>>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>>> usually in silicon as well. >>>>>>>>>>>> >>>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>>> apps are limited to comm. >>>>>>>>>>> >>>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>>> requires *very* large tables. >>>>>>>>>> >>>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>>> down. I've mentioned one already. >>>>>>>>> >>>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>>> more questions are needed. >>>>>>>> >>>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>>> it or leave it. >>>>>>> >>>>>>> I have no idea what you are talking about. If you don't have anything >>>>>>> to say, why are you bothering to post? >>>>>> >>>>>> Why do you care whether I post or not? Feel free to put me in your >>>>>> kill file if you don't like my posts. >>>>> >>>>> If you aren't interested in having a conversation, why do you bother to >>>>> type? Above you said you had already mentioned "one" method already. >>>>> Clearly that one is not a trade secret. Care to explain what method you >>>>> are referring to? >>>> >>>> I did later in the same post. >>> >>> What same post would that be? I'm not sure what "same" means since the >>> context is not clear. >> >> The same one you were responding to at the time. > >At this point it is pretty clear you are just playing with me and have >nothing to say. No, seriously, it was in the same post. I found it ironic that you were asking me to explain the method I was referring to, and I had explained in the post you were responding to at the time. >>>>>>> I don't even recall the hints. >>>>>>> Or are you forbidden from pointing out what those are? >>>>>> >>>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>>> of hints from multiple people scattered throughout the thread, as well >>>>>> as in some of the literature mentioned previously. >>>>> >>>>> Exactly, scattered in some 50 or so messages. If you have something to >>>>> say, why no say it instead of being so vague? Just tell me which >>>>> message you are referring to. >>>> >>>> So you want me to go back and search through the thread for you? Are >>>> you not capable of doing that? I'm not at all clear why you think >>>> that I should do the search if you're the one that wants the >>>> information. >>> >>> I'm assuming that you might have more recollection of having made a >>> post than I do of reading it. I did a scan and I never saw any useful >>> comments on table reduction. Everything you posted seems to allude to >>> things but always shies away from actually giving any info. >> >> I mentioned the quarter-wave reduction specifically multiple times. >> Sorry you weren't able to glean anything. Not everybody does. > >I just never read your post in this thread where you mentioned that. >That's why I pointed it out to someone who spoke of using the full wave. > >>>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>>> that? >>>>>> >>>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>>> that was mentioned more than once, but here it is again just for you. >>>>> >>>>> Thank you for the response. >>>>> >>>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>>> of that. I believe *I* was the one who in this thread pointed it out to >>>>> someone who said memory is cheap not fully appreciating that memory is >>>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>>> to change the fact that memory is anything but cheap if you are looking >>>>> for high resolution and low distortion. Using MBs of memory to store a >>>>> LUT is usually not a good trade off. >>>>> >>>>> What was the technique *you* mentioned as you indicate above? >>>> >>>> That was one of them. I mentioned it more than once. In my >>>> experience a 4x reduction in memory can be significant, and the >>>> quarter-wave trick isn't obvious to some people so I didn't make the >>>> assumption that it was. >>>> >>>> You're welcome. >>> >>> Yes, a four fold reduction in size can be useful, but like I said, this >>> is sine table 101. >>> >>> Was there anything else of value you have to offer on the topic? >> >> You can go back and see what's valuable to you, and I can't anticipate >> what will or won't be. You seem to resent having the quarter-wave >> trick pointed out to you, so I'm not going to try to guess what you >> might or might not find obvious. One of the nice things about usenet >> is that the posts a pretty sticky, so you can go back and review if >> you want to and take or leave things as you see fit. > >I have read your posts here and I didn't see you mention the quarter >wave table or anything else specific. Rather you gave thin references >to the fact that "significant" reductions are possible. That's why I >asked and so far you have not been able to explain what you meant or >point to a post. You just keep repeating that you have already said >things. Ok, nuff said. I've mentioned several techniques for improving DDS performance specifically. I didn't go into a lot of detail, but I mentioned a number of things pretty unambiguously, both before and after the thread started cross-posting. Maybe you just didn't see them. I use Forte newsreader, and there's not a simple way to go back and search which posts in a thread contained what, even if I posted it. I'm not inclined to do that for you. Sorry. It's there if you, or anybody, want to look, though. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.dsp,comp.lang.vhdl Subject: Re: Spectral Purity Measurement Date: Sat, 27 Dec 2014 14:49:33 -0500 Organization: A noiseless patient Spider Lines: 171 Message-ID: References: <5494f4a1.456409145@news.eternal-september.org> <549760f9.615217305@news.eternal-september.org> <549989f6.756782253@news.eternal-september.org> <5499e27d.779445002@news.eternal-september.org> <549c32a9.931041360@news.eternal-september.org> <549c79aa.949218051@news.eternal-september.org> <549c8171.951208826@news.eternal-september.org> <549d8ef7.1020206758@news.eternal-september.org> <549da465.1025693142@news.eternal-september.org> <549edda8.1105888388@news.eternal-september.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 27 Dec 2014 19:49:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4217"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EG/qoSE/U+tTxpKzqnR6P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <549edda8.1105888388@news.eternal-september.org> Cancel-Lock: sha1:Pj6OIDFOtpL3WB8PIoG4oE39IJM= Xref: mx02.eternal-september.org comp.dsp:52987 comp.lang.vhdl:8029 On 12/27/2014 11:33 AM, Eric Jacobsen wrote: > On Sat, 27 Dec 2014 01:35:55 -0500, rickman wrote: > >> On 12/26/2014 1:15 PM, Eric Jacobsen wrote: >>> On Fri, 26 Dec 2014 12:05:24 -0500, rickman wrote: >>> >>>> On 12/26/2014 11:45 AM, Eric Jacobsen wrote: >>>>> On Thu, 25 Dec 2014 18:08:54 -0500, rickman wrote: >>>>> >>>>>> On 12/25/2014 4:32 PM, Eric Jacobsen wrote: >>>>>>> On Thu, 25 Dec 2014 16:08:45 -0500, rickman wrote: >>>>>>> >>>>>>>> On 12/25/2014 3:56 PM, Eric Jacobsen wrote: >>>>>>>>> On Thu, 25 Dec 2014 11:56:15 -0500, rickman wrote: >>>>>>>>> >>>>>>>>>> On 12/25/2014 10:52 AM, Eric Jacobsen wrote: >>>>>>>>>>> On Tue, 23 Dec 2014 18:10:43 -0500, rickman wrote: >>>>>>>>>>> >>>>>>>>>>>> On 12/23/2014 4:48 PM, Eric Jacobsen wrote: >>>>>>>>>>>>> On Tue, 23 Dec 2014 11:06:39 -0500, rickman wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>> On 12/23/2014 10:35 AM, Eric Jacobsen wrote: >>>>>>>>>>>>>>> >>>>>>>>>>>>>>> Many applications don't need separate LUTs to get the required >>>>>>>>>>>>>>> performance, and even then, or even in the case of complex output, it >>>>>>>>>>>>>>> can be done without multipliers. >>>>>>>>>>>>>> >>>>>>>>>>>>>> Care to elaborate on this? I'm not at all clear on how you make a LUT >>>>>>>>>>>>>> based NCO without LUTs and unless you are using a very coarse >>>>>>>>>>>>>> approximation, without multipliers. >>>>>>>>>>>>> >>>>>>>>>>>>> Not sure what you're asking. You a need a LUT, but just one in many >>>>>>>>>>>>> cases. Having a dual-ported single LUT is easy in an FPGA and >>>>>>>>>>>>> usually in silicon as well. >>>>>>>>>>>>> >>>>>>>>>>>>> What makes a multiplier necessary? I've never found the need, but my >>>>>>>>>>>>> apps are limited to comm. >>>>>>>>>>>> >>>>>>>>>>>> Maybe we aren't on the same page. The multiplier is there for the fine >>>>>>>>>>>> adjustment. If you are happy with some -60 or -80 dB spurs one LUT is >>>>>>>>>>>> fine. But if you want better performance the single LUT approach >>>>>>>>>>>> requires *very* large tables. >>>>>>>>>>> >>>>>>>>>>> There are a lot of tricks that can be used to keep the table size >>>>>>>>>>> down. I've mentioned one already. >>>>>>>>>> >>>>>>>>>> And what was that? You have made some 20 or more posts in this thread, >>>>>>>>>> I don't feel like weeding through all of them to find this. Reading >>>>>>>>>> back through this thread it seems like your posts are intended to be >>>>>>>>>> mysterious rather than informative. Every one leaves enough unsaid that >>>>>>>>>> more questions are needed. >>>>>>>>> >>>>>>>>> I can't divulge trade secrets or proprietary information that doesn't >>>>>>>>> belong to me. I can, however, hint in directions of benefit. Take >>>>>>>>> it or leave it. >>>>>>>> >>>>>>>> I have no idea what you are talking about. If you don't have anything >>>>>>>> to say, why are you bothering to post? >>>>>>> >>>>>>> Why do you care whether I post or not? Feel free to put me in your >>>>>>> kill file if you don't like my posts. >>>>>> >>>>>> If you aren't interested in having a conversation, why do you bother to >>>>>> type? Above you said you had already mentioned "one" method already. >>>>>> Clearly that one is not a trade secret. Care to explain what method you >>>>>> are referring to? >>>>> >>>>> I did later in the same post. >>>> >>>> What same post would that be? I'm not sure what "same" means since the >>>> context is not clear. >>> >>> The same one you were responding to at the time. >> >> At this point it is pretty clear you are just playing with me and have >> nothing to say. > > No, seriously, it was in the same post. I found it ironic that you > were asking me to explain the method I was referring to, and I had > explained in the post you were responding to at the time. I have no idea which post you are referring to. Context is long lost and you keep saying the "same post". >>>>>>>> I don't even recall the hints. >>>>>>>> Or are you forbidden from pointing out what those are? >>>>>>> >>>>>>> No, but it seems to me like unnecessary duplication. There are lots >>>>>>> of hints from multiple people scattered throughout the thread, as well >>>>>>> as in some of the literature mentioned previously. >>>>>> >>>>>> Exactly, scattered in some 50 or so messages. If you have something to >>>>>> say, why no say it instead of being so vague? Just tell me which >>>>>> message you are referring to. >>>>> >>>>> So you want me to go back and search through the thread for you? Are >>>>> you not capable of doing that? I'm not at all clear why you think >>>>> that I should do the search if you're the one that wants the >>>>> information. >>>> >>>> I'm assuming that you might have more recollection of having made a >>>> post than I do of reading it. I did a scan and I never saw any useful >>>> comments on table reduction. Everything you posted seems to allude to >>>> things but always shies away from actually giving any info. >>> >>> I mentioned the quarter-wave reduction specifically multiple times. >>> Sorry you weren't able to glean anything. Not everybody does. >> >> I just never read your post in this thread where you mentioned that. >> That's why I pointed it out to someone who spoke of using the full wave. >> >>>>>>>> You said you had already mentioned a way to reduce table size. What was >>>>>>>> that? >>>>>>> >>>>>>> One way is to store a quarter wave instead of a full cycle. I think >>>>>>> that was mentioned more than once, but here it is again just for you. >>>>>> >>>>>> Thank you for the response. >>>>>> >>>>>> Yes, that is table reduction 101. Anyone other than a newbie is aware >>>>>> of that. I believe *I* was the one who in this thread pointed it out to >>>>>> someone who said memory is cheap not fully appreciating that memory is >>>>>> order 2^N is size. Even so it is just a factor of four and does nothing >>>>>> to change the fact that memory is anything but cheap if you are looking >>>>>> for high resolution and low distortion. Using MBs of memory to store a >>>>>> LUT is usually not a good trade off. >>>>>> >>>>>> What was the technique *you* mentioned as you indicate above? >>>>> >>>>> That was one of them. I mentioned it more than once. In my >>>>> experience a 4x reduction in memory can be significant, and the >>>>> quarter-wave trick isn't obvious to some people so I didn't make the >>>>> assumption that it was. >>>>> >>>>> You're welcome. >>>> >>>> Yes, a four fold reduction in size can be useful, but like I said, this >>>> is sine table 101. >>>> >>>> Was there anything else of value you have to offer on the topic? >>> >>> You can go back and see what's valuable to you, and I can't anticipate >>> what will or won't be. You seem to resent having the quarter-wave >>> trick pointed out to you, so I'm not going to try to guess what you >>> might or might not find obvious. One of the nice things about usenet >>> is that the posts a pretty sticky, so you can go back and review if >>> you want to and take or leave things as you see fit. >> >> I have read your posts here and I didn't see you mention the quarter >> wave table or anything else specific. Rather you gave thin references >> to the fact that "significant" reductions are possible. That's why I >> asked and so far you have not been able to explain what you meant or >> point to a post. You just keep repeating that you have already said >> things. Ok, nuff said. > > I've mentioned several techniques for improving DDS performance > specifically. I didn't go into a lot of detail, but I mentioned a > number of things pretty unambiguously, both before and after the > thread started cross-posting. Maybe you just didn't see them. > > I use Forte newsreader, and there's not a simple way to go back and > search which posts in a thread contained what, even if I posted it. > I'm not inclined to do that for you. Sorry. It's there if you, or > anybody, want to look, though. Yes, it's there... on the Internet. Anyone can find that! -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.236.11.70 with SMTP id 46mr57640017yhw.22.1420188953915; Fri, 02 Jan 2015 00:55:53 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr5528qgp.16.1420188953874; Fri, 02 Jan 2015 00:55:53 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!bm13no2717196qab.0!news-out.google.com!n9ni77qai.0!nntp.google.com!bm13no2717191qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Jan 2015 00:55:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.11.95.114; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 84.11.95.114 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Subject: Help with VHDL architecture From: Olalekan Shittu Injection-Date: Fri, 02 Jan 2015 08:55:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8030 Hello everyone. I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. Below is my entity declaration from the system Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Jan 2015 03:16:47 -0600 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> In-Reply-To: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Subject: Re: Help with VHDL architecture Date: Fri, 2 Jan 2015 09:16:23 -0000 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 76 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-wgusDPkBGHgxpeOlzM8knku5Z4k+qsf/aD5cGZV8bCU8trjEKeM7OlNCWu2DtOidmJXyB81SoKmLyoW!6tPlbJWgPBbpaYQkPfkZc7a4BlusjrenqgzgnK5bi8zkS5A/opL8ewkE/oJslA2OZpTailB7LASZ!5qaxsCfsMbt+I6fnoCvO5cNahWI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2636 Xref: mx02.eternal-september.org comp.lang.vhdl:8031 "Olalekan Shittu" wrote in message news:622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com... Hello everyone. I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. Below is my entity declaration from the system Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks Something like:- Defaults:- Out[3..0] = 0 End defaults If C >= 0 or C < 4 then out0 = 1 end if If C >= 4 or C < 8 then out1 = 1 end if If C >= 8 or C < 12end if out2 = 1 end if If C >= 12 or C < 16 then out3 = 1 end if From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Jan 2015 03:19:39 -0600 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> In-Reply-To: Subject: Re: Help with VHDL architecture Date: Fri, 2 Jan 2015 09:19:39 -0000 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 48 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-6k7zh6VNplCoReRDFP3+mypcBqrittFW2J7/x02Rf4/8z4HyPtVFo6KjY12wi4rcOFDoj+z5odAuFrZ!TXw42VRwBwJysiggdRdnfF0foqBrqUVJ4+EICBKm6d5EMVnS2hGbyNzMCxHANSSMpYnRPH/KxVPF!Kzv5lvGn1zIvFOK/sVJObncXaVw= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1844 Xref: mx02.eternal-september.org comp.lang.vhdl:8032 "Andy Bennett" wrote in message news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... Forgot to add sel ... so Something like:- Defaults:- Out[3..0] = 0 End defaults If sel = 4 then If C >= 0 or C < 4 then out0 = 1 end if If C >= 4 or C < 8 then out1 = 1 end if If C >= 8 or C < 12end if out2 = 1 end if If C >= 12 or C < 16 then out3 = 1 end if end if The student can add/correct the syntax Andy From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.182.68.10 with SMTP id r10mr68008390obt.13.1420281497360; Sat, 03 Jan 2015 02:38:17 -0800 (PST) X-Received: by 10.140.104.166 with SMTP id a35mr1540qgf.20.1420281497336; Sat, 03 Jan 2015 02:38:17 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no20632480igd.0!news-out.google.com!n9ni76qai.0!nntp.google.com!dc16no3798361qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Jan 2015 02:38:17 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=105.112.8.4; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 105.112.8.4 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> Subject: Re: Help with VHDL architecture From: Olalekan Shittu Injection-Date: Sat, 03 Jan 2015 10:38:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8033 On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote: > "Andy Bennett" wrote in message > news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... > > Forgot to add sel ... so > > > > > > > > Something like:- > > Defaults:- > > Out[3..0] = 0 > > End defaults > > > If sel = 4 then > If C >= 0 or C < 4 then > out0 = 1 > end if > > If C >= 4 or C < 8 then > out1 = 1 > end if > > If C >= 8 or C < 12end if > out2 = 1 > end if > > If C >= 12 or C < 16 then > out3 = 1 > end if > end if > > > The student can add/correct the syntax > > > Andy Thanks Andy, trying to work on the syntax for now. Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email. From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.236.22.71 with SMTP id s47mr1280331yhs.7.1420296652079; Sat, 03 Jan 2015 06:50:52 -0800 (PST) X-Received: by 10.140.84.103 with SMTP id k94mr667880qgd.3.1420296652035; Sat, 03 Jan 2015 06:50:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!dc16no3840180qab.1!news-out.google.com!n9ni77qai.0!nntp.google.com!bm13no2982635qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Jan 2015 06:50:51 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=196.46.245.126; posting-account=K0gblgoAAADsltVFNuj1FkZP2N0fuWaj NNTP-Posting-Host: 196.46.245.126 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1948d48f-320b-4111-828c-bf2fa62229cf@googlegroups.com> Subject: Re: Finding the difference between two numbers From: Olalekan Shittu Injection-Date: Sat, 03 Jan 2015 14:50:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8034 Hello Mike, Can you help with an architecture for the below entity and conditions. Thanks Library ieee; use IEEE.std_logic_1164.all; entity Sorter IS Port ( C: IN std_logic_vector (0 to 3); Sel: IN STD_LOGIC_VECTOR(0 to 2); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic ); end sorter; I am to write an architecture for the above with condition that: When Sel equal 4, the resulting output as shown in the table below is generated out0 out1 out2 out3 0 <= C < 4 1 0 0 0 4 <= C < 8 0 1 0 0 8 <= C < 12 0 0 1 0 12 <= C < 16 0 0 0 1 otherwise out0,out1,out2,out3 are all equal to zero. Thanks From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Initializing Large Arrays Date: Mon, 05 Jan 2015 12:11:27 -0500 Organization: A noiseless patient Spider Lines: 12 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Jan 2015 17:11:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17667"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qD1wwzp/KBzqX1OC/zioj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 Cancel-Lock: sha1:TxKXwqqhpZSEq0q3gLPjP6iLFT0= Xref: mx02.eternal-september.org comp.lang.vhdl:8035 I have some large arrays to initialize from a function call. This is a ROM table containing integer values derived from trig functions. I'm thinking the best way is to use a process on startup that will step through the table elements invoking the function to generate the data. The only variable input to the function is the index although there may be scaling constants as well to make the function more general purpose. Any other suggestions? -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.50.78.136 with SMTP id b8mr11322877igx.4.1420479865061; Mon, 05 Jan 2015 09:44:25 -0800 (PST) X-Received: by 10.140.23.50 with SMTP id 47mr19717qgo.27.1420479865024; Mon, 05 Jan 2015 09:44:25 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no36699607igd.0!news-out.google.com!n9ni76qai.0!nntp.google.com!dc16no4280903qab.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Jan 2015 09:44:24 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fe83954-e8b5-40e7-9fd1-8bf636ff51c9@googlegroups.com> Subject: Re: Initializing Large Arrays From: KJ Injection-Date: Mon, 05 Jan 2015 17:44:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8036 On Monday, January 5, 2015 12:11:46 PM UTC-5, rickman wrote: > I have some large arrays to initialize from a function call. This is a= =20 > ROM table containing integer values derived from trig functions. I'm=20 > thinking the best way is to use a process on startup that will step=20 > through the table elements invoking the function to generate the data.=20 > The only variable input to the function is the index although there may= =20 > be scaling constants as well to make the function more general purpose. >=20 > Any other suggestions? >=20 If this is meant to be synthesizable, then you will also need another funct= ion that loops through the entire index range to generate the entire table = so that the whole thing can then be assigned to a constant integer array. = Even if it does not need to be synthesized, I still tend to like this metho= d of having a function generate the entire table. A function(s) can simply= be reused directly, whereas using a process to call a function involves co= py/paste when reusing. Kevin From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Initializing Large Arrays Date: Mon, 5 Jan 2015 10:04:22 -0800 Organization: Highland Technology, Inc. Lines: 43 Message-ID: <20150105100422.267aa57d@rg.highlandtechnology.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="22628"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18scETh5Fzo8uesG1wof6gX" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:gF9VZ3kaLwGOyNWsHKIdf2a7GaM= Xref: mx02.eternal-september.org comp.lang.vhdl:8037 On Mon, 05 Jan 2015 12:11:27 -0500 rickman wrote: > I have some large arrays to initialize from a function call. This is a > ROM table containing integer values derived from trig functions. I'm > thinking the best way is to use a process on startup that will step > through the table elements invoking the function to generate the data. > The only variable input to the function is the index although there may > be scaling constants as well to make the function more general purpose. > > Any other suggestions? > > -- > > Rick Something like the following? (Note, this is all in the architecture declaration bit, not the bit with the processes). type RAM is array (INT_MAX_ADDR downto 0) of std_logic_vector(15 downto 0); -- Function to initialize the RAM to a sinewave impure function SetTable return RAM is variable count : integer; variable phase : real; variable sinx : real; variable nextval : integer; variable data : RAM; begin for count in 0 to INT_MAX_ADDR loop phase := REAL(count * 2) * MATH_PI / REAL(INT_MAX_ADDR); sinx := SIN(phase) * 32767.0; nextval := INTEGER(ROUND(sinx)); data(count) := STD_LOGIC_VECTOR(TO_SIGNED(nextval, 16)); end loop; return data; end function; signal internal_data : RAM := SetTable; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.182.65.227 with SMTP id a3mr9648412obt.2.1420517163844; Mon, 05 Jan 2015 20:06:03 -0800 (PST) X-Received: by 10.50.110.101 with SMTP id hz5mr208189igb.6.1420517163762; Mon, 05 Jan 2015 20:06:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no161916igd.0!news-out.google.com!h6ni6igv.0!nntp.google.com!h15no84983igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Jan 2015 20:06:03 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=163.180.171.34; posting-account=4Z7noQoAAACvo8dN9s9CMQogvE7lEACd NNTP-Posting-Host: 163.180.171.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> Subject: what is the reason of this error?? From: Youjung Hong Injection-Date: Tue, 06 Jan 2015 04:06:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8038 I am making eeprom on Actel A3PE3000 board. when I place and route ports, I got this errors. I don't know what is the reason. Here is the error report. ***** Layout Variables ********************************************* Mode: TIMING_DRIVEN Power-driven Layout: OFF Incremental Placement: OFF Incremental Route: OFF Running I/O Bank Assigner. I/O Bank Assigner completed successfully. Planning global net placement... Error: PLC004: No legal global assignment could be found. Some global nets have shared instances, requiring them to be assigned to overlapping global regions. Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations: |--------------------------------------------| |Global Net |Valid Driver Locations | |--------------------------------------------| |CLK_c |(None) |--------------------------------------------| |RST_c |(None) |--------------------------------------------| Info: Consider relaxing the constraints for these nets by removing region constraints, unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input buffers without hardwired pad connections. Error: PLC003: No legal global assignment could be found because of complex region and/or IO technology constraints. Error: PLC005: Automatic global net placement failed. INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about the global assignment. The Layout command failed ( 00:00:01 ) The Layout command failed ( 00:00:02 ) Error: Failure when executing Tcl script. [ Line 18 ] The Execute Script command failed ( 00:00:05 ) Warning: The database was closed without a save, modifications are lost Design closed. From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: what is the reason of this error?? Date: Tue, 6 Jan 2015 13:48:34 +0000 (UTC) Organization: A noiseless patient Spider Lines: 60 Message-ID: References: <18ea7387-fb8b-4cf0-9ff6-2923c7f3982a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 6 Jan 2015 13:48:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="4557"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YrU3r09PlF62eb+0TyAkVKyh4uJ5BHVc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:DWO/FopdOEINci8inJwSPhTx/PE= Xref: mx02.eternal-september.org comp.lang.vhdl:8039 On Mon, 05 Jan 2015 20:06:03 -0800, Youjung Hong wrote: > I am making eeprom on Actel A3PE3000 board. > when I place and route ports, I got this errors. > I don't know what is the reason. > > Here is the error report. > > ***** Layout Variables ********************************************* > > Mode: TIMING_DRIVEN Power-driven Layout: OFF Incremental Placement: OFF > Incremental Route: OFF > > > > Running I/O Bank Assigner. > > I/O Bank Assigner completed successfully. > > > Planning global net placement... > Error: PLC004: No legal global assignment could be found. I hope you haven't laid out the PCB yet. > > |--------------------------------------------| > |Global Net |Valid Driver Locations | > |--------------------------------------------| > |CLK_c |(None) > |--------------------------------------------| > |RST_c |(None) > |--------------------------------------------| > Your pin assignment is incorrect. While you have apparently assigned CLK_c and RST_c to "global" pins, that is not good enough, because, incredibly, "global" pins are not actually global. You need "chip global" pins as opposed to the "quadrant global" pins you are apparently using now (which the name implies can only access 1/4 of the device). This unique interpretation of the word "global" nearly caught me out too ... fortunately I mistrust the tools enough to have insisted on a PAR run before board layout... The data sheet I'm looking at says (section 3-2), User Pins "All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. " and "All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals" Unfortunately this seems to contradict itself, probably a cut&paste error, and I can't be bothered to find another datasheet. But it means you have to select pins named (probably) GCnn or GFnn to get truly global clock and reset signals. - Brian From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.236.45.68 with SMTP id o44mr11335749yhb.51.1420808941766; Fri, 09 Jan 2015 05:09:01 -0800 (PST) X-Received: by 10.140.109.162 with SMTP id l31mr4546qgf.22.1420808941649; Fri, 09 Jan 2015 05:09:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1984933igd.0!news-out.google.com!qk8ni1868igc.0!nntp.google.com!h15no1984925igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 05:09:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.176.1.84; posting-account=-qULwgoAAADJOPTEj_v8bQ7RHRQyCpyP NNTP-Posting-Host: 192.176.1.84 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Subject: Learning VHDL beyond basics From: johan.falkenstrom@gmail.com Injection-Date: Fri, 09 Jan 2015 13:09:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8040 a month ago I decided that I was lacking FPGA knowhow, said and done I orde= red an experiment board (beeing an opensource aficionado I ordered the Logi= cStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "= The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exampl= es: Spartan 3". My reasoning behind these two books is that I start with As= henden to learn the whole language then go to Pong to learn how to write sy= ntezisable VHDL, since both contain exercises they make for really good sel= f teaching material. I know Pong is targeting another experiment board but = it's the same FPGA and im very confident I can myself make adjustments, exc= ept for e.g. the PS2 port which my papilio thankfully does not have. I have now started to search for what to do after these books, how do I get= more advanced in my FPGA knowledge. I'm a software guy and if I got the qu= estion "I want to start programming" from someone new to programming I woul= d recomend a good starting book in python, then a good book on how to do te= st driven design, then a book about patterns, then moving to C followed by = a book about object oriented design, then perhaps going for a best practice= book and so on, by level of complexity and relevance. I have scoured the i= nternet (or feels like it) to find such a list regarding FPGA, but at no lu= ck so far, so thinking of posting the question here. I have looked at three books for continued learning after I'm finished with= Pong Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed= at explaining deeper the differences beetwen syntezisable and simulated VH= DL. Though it seem to go through the VHDL language constructs yet again per= haps it is too much overlapping with Pong and Ashenden Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seem= s a good continuation, I understand that FSM is a very important topic in H= W world and that they are completely different from SW FSM, also it seem to= have excersises after each chapter which is good. Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabili= ty, and Scalability ; seems good, no more comments. Thats my thinking, any suggestions or comments? Have not come about any boo= ks regarding FPGA testing? Perhaps I should look outside the more hands on = book to one of the "meta" books out there? From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 09 Jan 2015 12:43:17 -0500 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Jan 2015 17:43:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="131d71abdca206f852e85f753b3a8167"; logging-data="29838"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CGhm/9sHRQwyd6iJ8HX7i" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Cancel-Lock: sha1:8FIYzB72hp+Gtlx183kpxai7Jhg= Xref: mx02.eternal-september.org comp.lang.vhdl:8041 On 1/9/2015 8:09 AM, johan.falkenstrom@gmail.com wrote: > a month ago I decided that I was lacking FPGA knowhow, said and done I ordered an experiment board (beeing an opensource aficionado I ordered the LogicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Examples: Spartan 3". My reasoning behind these two books is that I start with Ashenden to learn the whole language then go to Pong to learn how to write syntezisable VHDL, since both contain exercises they make for really good self teaching material. I know Pong is targeting another experiment board but it's the same FPGA and im very confident I can myself make adjustments, except for e.g. the PS2 port which my papilio thankfully does not have. > > I have now started to search for what to do after these books, how do I get more advanced in my FPGA knowledge. I'm a software guy and if I got the question "I want to start programming" from someone new to programming I would recomend a good starting book in python, then a good book on how to do test driven design, then a book about patterns, then moving to C followed by a book about object oriented design, then perhaps going for a best practice book and so on, by level of complexity and relevance. I have scoured the internet (or feels like it) to find such a list regarding FPGA, but at no luck so far, so thinking of posting the question here. > > I have looked at three books for continued learning after I'm finished with Pong > > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aimed at explaining deeper the differences beetwen syntezisable and simulated VHDL. Though it seem to go through the VHDL language constructs yet again perhaps it is too much overlapping with Pong and Ashenden > > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; seems a good continuation, I understand that FSM is a very important topic in HW world and that they are completely different from SW FSM, also it seem to have excersises after each chapter which is good. > > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability ; seems good, no more comments. > > Thats my thinking, any suggestions or comments? Have not come about any books regarding FPGA testing? Perhaps I should look outside the more hands on book to one of the "meta" books out there? I don't think I ever read HDL books to learn higher level ideas. I read them to learn the basics. Oddly enough every one had a rather different approach to teaching what I think is very simple and straightforward really. Still, they got me over the hump and on the road to teaching myself. I learned FSMs in school and never felt the need to worry with how others write FSM code. I also tossed most of what I learned about FSMs actually. The whole Mealy/Moore thing is not so valuable when coding them up in HDL. I don't think any of my FSM designs are purely either now. It was a useful concept to learn about FSMs, but not so useful in practice. The Pong Chu book may be useful, at least it sounds good. I have to wonder if it is better than reading the app notes from the FPGA vendors. All HDL compilers are a little different and of course the chip architectures are also different. So how can one book be applicable to all? There is a standard for synthesis which I suppose is what he covers. I suggest you look more toward the vendors for info on how to use their tools. To me that is the bottom line. After all, in FPGAland there is no way to completely avoid the vendor tools. -- Rick From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.66.150.33 with SMTP id uf1mr568377pab.33.1420828763212; Fri, 09 Jan 2015 10:39:23 -0800 (PST) X-Received: by 10.140.96.202 with SMTP id k68mr26852qge.24.1420828763012; Fri, 09 Jan 2015 10:39:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no1648916igd.0!news-out.google.com!qk8ni2672igc.0!nntp.google.com!f12no32649qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 10:39:22 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2e3c382c-eba0-4c5e-9a4e-4d29d7893231@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Lars Asplund Injection-Date: Fri, 09 Jan 2015 18:39:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 9 Xref: mx02.eternal-september.org comp.lang.vhdl:8042 If you have a software and TDD background I would recommend a look at VUnit= , an open-source unit testing framework for VHDL, which we just released on= GitHub (https://github.com/LarsAsplund/vunit). It will let you work with T= DD in a way that you are used to. I'm just about to add more introduction material on YouTube so make sure to= follow the project and sign up for the referenced YouTube channel if you'r= e interested. Lars From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.236.4.194 with SMTP id 42mr12717242yhj.24.1420836787845; Fri, 09 Jan 2015 12:53:07 -0800 (PST) X-Received: by 10.182.219.13 with SMTP id pk13mr16645obc.39.1420836787387; Fri, 09 Jan 2015 12:53:07 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f12no60083qad.0!news-out.google.com!qk8ni2634igc.0!nntp.google.com!h15no2306664igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 12:53:07 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=12.251.154.34; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 12.251.154.34 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KKoorndyk Injection-Date: Fri, 09 Jan 2015 20:53:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2979 X-Received-Body-CRC: 1123848707 Xref: mx02.eternal-september.org comp.lang.vhdl:8043 The Ashenden book is a great reference but may be a bit difficult to sit an= d read cover to cover to learn the language. I assume you bought the 3rd e= dition, right? A lot of examples early in the book are fine for models and= learning the language, but are not synthesizable. Pay particular attentio= n to the new Design for Synthesis chapter (21). =20 Along the lines of rickman's suggestion, I would *HIGHLY* recommend that yo= u read the synthesis guides for Altera Quartus II and Xilinx's XST and Viva= do Synthesis. They'll provide guidance on what constructs are supported. = =20 http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.= pdf http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-v= ivado-synthesis.pdf I would also recommend reading Xilinx's UltraFast Design Methodology Guide.= It is obviously heavily geared towards the Vivado tool suite, but it also= contains a lot of best practices. http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-= methodology.pdf You might also consider an on-demand college course like the one mentioned = on this page: http://dangerousprototypes.com/2013/03/09/cornell-online-courses-designing-= with-microcontrollers-and-fpgas/ Altera also offers quite a few free, on-demand training "courses", but they= 're a little light on quality content. Xilinx also has several videos: http://www.xilinx.com/training/free-video-courses.htm#FPGA Doulos has some good, free material on their site: http://www.doulos.com/kn= owhow/vhdl_designers_guide/ Check out OpenCores.org. There are a ton of open modules that you can lear= n from reviewing, but be careful - some are garbage. There's also some material on the EETimes Programmable Logic Designline blo= g. From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.182.143.34 with SMTP id sb2mr13071421obb.27.1420836961761; Fri, 09 Jan 2015 12:56:01 -0800 (PST) X-Received: by 10.140.30.118 with SMTP id c109mr50671qgc.15.1420836961536; Fri, 09 Jan 2015 12:56:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no1699392igd.0!news-out.google.com!qk8ni2672igc.0!nntp.google.com!f12no60952qad.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 9 Jan 2015 12:56:01 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07812bd8-20af-4ce5-9f7a-7bd9ca8caa94@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Leonardo Capossio Injection-Date: Fri, 09 Jan 2015 20:56:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2547 X-Received-Body-CRC: 3881391190 Xref: mx02.eternal-september.org comp.lang.vhdl:8044 It is difficult to say, since advanced stuff this days is mostly done by ex= perience and reading other peoples code/papers. Also...remember that actually VHDL is a low level language, and what you ac= tually have to get knowledge about is hardware architectures (or digital de= sign in general). Get into some project, set some goal, when the need arise= s search for more specific knowledge. There is possible exception, if you only want to do verification (usually a= ttributed to be a pure-software task), then I would advise to get some veri= fication book I don't know about, but I do know that if you are going to be= using VHDL the most advanced verification can be done with OSVVM (search i= t). Otherwise SystemVerilog is what you are looking for. But advanced verif= ication is most well suited to ASICs, in FPGA sometimes it doesn't make sen= s because you can prototype quickly. I could recommend Altera Cookbook for learning a couple of synthesis tricks= (search, it is free downloadable, but it is mostly in Verilog). Then for D= igital Design I recommend Wakerly (Digital Design: Principles and Practices= ), it is one the most comprehensible and cool books that I have found (and = also detailed). Also I recommend a The Design Warrior's Guide to FPGA, as a= general FPGA knowledge book. Good luck and welcome to the FPGA world! From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 9 Jan 2015 15:22:03 -0800 Organization: Highland Technology, Inc. Lines: 19 Message-ID: <20150109152203.61d253d8@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="18267"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+9H5cCEhZmPZFsm6g1Q8al" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Xviv774AJjpSg0PB9F+2VBY5VjE= Xref: mx02.eternal-september.org comp.lang.vhdl:8045 On Fri, 9 Jan 2015 12:53:07 -0800 (PST) KKoorndyk wrote: > The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21). > > Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported. > http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf > Wow. Just flipped through the Vivado Synthesis guide. It's all still recommending you use std_logic_arith/std_logic_unsigned. There's no mention of numeric_std at all, let along the VHDL-2008 packages. This is why we can't have nice things. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Fri, 9 Jan 2015 15:39:09 -0800 Organization: Highland Technology, Inc. Lines: 29 Message-ID: <20150109153909.0a7f8ef9@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="18267"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Qaap5N4s5lCDJjbe76UgA" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:bp7wTaJEVu3E8ZoAYTgg2CJzepg= Xref: mx02.eternal-september.org comp.lang.vhdl:8046 On Fri, 9 Jan 2015 15:22:03 -0800 Rob Gaddi wrote: > On Fri, 9 Jan 2015 12:53:07 -0800 (PST) > KKoorndyk wrote: > > > The Ashenden book is a great reference but may be a bit difficult to sit and read cover to cover to learn the language. I assume you bought the 3rd edition, right? A lot of examples early in the book are fine for models and learning the language, but are not synthesizable. Pay particular attention to the new Design for Synthesis chapter (21). > > > > Along the lines of rickman's suggestion, I would *HIGHLY* recommend that you read the synthesis guides for Altera Quartus II and Xilinx's XST and Vivado Synthesis. They'll provide guidance on what constructs are supported. > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf > > > > Wow. Just flipped through the Vivado Synthesis guide. It's all still > recommending you use std_logic_arith/std_logic_unsigned. There's no > mention of numeric_std at all, let along the VHDL-2008 packages. > > This is why we can't have nice things. Never mind. Finally made it all the way to the section on the IEEE packages for VHDL, where they do mention support for numeric_std, fixed_pkg, and float_pkg. The latter two are just shunted off into ieee_proposed. Good to see support for such things, even if all their design examples are still recommending packages that were deprecated in 1992. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 12 Jan 2015 11:31:44 +0100 Lines: 32 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net RNm6W7HgwDPIZ2Qw53T3WAMuanBQ23Oo33q3PGS9ahyt92wvIz Cancel-Lock: sha1:0AUCGYYpsr4f8aVubziCxVW2ykw= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: <20150109152203.61d253d8@rg.highlandtechnology.com> Xref: mx02.eternal-september.org comp.lang.vhdl:8047 Rob Gaddi wrote: > Wow. Just flipped through the Vivado Synthesis guide. It's all still > recommending you use std_logic_arith/std_logic_unsigned. There's no > mention of numeric_std at all, let along the VHDL-2008 packages. > > This is why we can't have nice things. Not only that, but all their examples and all of their cores use std_logic and std_logic_vector almost exclusively, instead of std_ulogic/std_ulogic_vector. That is not only useless, because the hardware doesn't really support it (what does a FF do with an 'X' input?), but more importantly it prevents detecting multiple driver errors early in the process (like right at the beginning during VHDL elaboration). I'd like to stick to std_ulogic in my designs, but it's a hassle to have to convert to std_logic every time I connect to a core or code snippet from them, sometimes needing intermediate signals just for the conversion (because no type conversions allowed in instantiations...). So in the end you can either have readable code or "safe" code. At the moment (at least up to Vivdao 2014.3) they have an issue in Vivado that causes them sometimes to not detect multiple drivers at all; but even if they do, you sometimes only get a "critical warning" that does not stop the flow and can be easily missed when you don't search the logs for it (or you can configure synthesis to promote that warning to an error). The only time you really get a multiple drivers error is at the very end during bitfile generation, so they let you waste hours with a completely useless synthesis/map/pnr run before issuing an error that should really occur before it starts synthesizing... Greetings, Sean From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.182.78.69 with SMTP id z5mr9604912obw.4.1421069035568; Mon, 12 Jan 2015 05:23:55 -0800 (PST) X-Received: by 10.182.219.200 with SMTP id pq8mr35384obc.6.1421069035283; Mon, 12 Jan 2015 05:23:55 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no3844874igd.0!news-out.google.com!qk8ni2634igc.0!nntp.google.com!h15no3844844igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Jan 2015 05:23:55 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KJ Injection-Date: Mon, 12 Jan 2015 13:23:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8048 On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote: > I'd like to stick to std_ulogic in my designs, but it's a hassle to have > to convert to std_logic every time I connect to a core or code snippet > from them, sometimes needing intermediate signals just for the > conversion (because no type conversions allowed in instantiations...). > So in the end you can either have readable code or "safe" code. >=20 No conversion is necessary between std_logic and std_ulogic; only between s= td_logic_vector and std_ulogic_vector. If your tools support VHDL-2008, yo= u don't even need to convert the vectors. If your tools do not support VHD= L-2008, you can put the type conversion right in the port map (both for inp= uts and outputs) so there is no need for intermediate signals. Example: My_Entity port map( std_logic_vector(some_slv) =3D> some_sulv, some_other_slv =3D> std_ulogic_vector(some_other_sulv)); Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:42 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 12 Jan 2015 16:25:31 +0100 Lines: 67 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net Y4613/vfBqQkyKqaVLqfNAiMSLpyZMv2Uz28i1Kd6DPjUQrnyF Cancel-Lock: sha1:VEjgb/t2zhjtOCY7R7FSTm9QvtU= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 In-Reply-To: Xref: mx02.eternal-september.org comp.lang.vhdl:8049 KJ wrote: > On Monday, January 12, 2015 at 5:31:48 AM UTC-5, Sean Durkin wrote: > >> I'd like to stick to std_ulogic in my designs, but it's a hassle to >> have to convert to std_logic every time I connect to a core or code >> snippet from them, sometimes needing intermediate signals just for >> the conversion (because no type conversions allowed in >> instantiations...). So in the end you can either have readable code >> or "safe" code. >> > No conversion is necessary between std_logic and std_ulogic; only > between std_logic_vector and std_ulogic_vector. Correct, but that only messes things up further: you need a conversion for one signal and not for the other... Again, sucks for readability IMHO. > If your tools support VHDL-2008, you don't even need to convert the vectors. Well, Vivado has some very rudimentary support vor VHDL-2008, but not for that AFAIK. > If your tools do not support VHDL-2008, you can put the type conversion > right in the port map (both for inputs and outputs) so there is no > need for intermediate signals. > Example: My_Entity port map( > std_logic_vector(some_slv) => some_sulv, > some_other_slv => std_ulogic_vector(some_other_sulv)); Ah, OK, didn't know about the type conversion of the port (the second line in your example). I only tried converting the actual, which does not work for entity outputs (Vivado quits saying "output designator some_slv cannot contain an actual type-conversion"). Now that you say it, kinda makes sense to put the conversion at the "source", I just never had dared to use type conversions on the ports themselves, only on signals connected to ports. The entire std_ulogic-thing just seems to be utterly broken in Vivado. Even if there wasn't added hassle for conversions, it wouldn't help any, since Vivado synthesis doesn't catch multiple drivers in some cases, which for me is the main reason to use std_ulogic in the first place. Concurrent assignments like: sig <= some_other_sig; ... sig <= '0'; ... with "sig" being a std_ulogic do not produce an error; this produces a bitfile that simply does not work as expected, no warnings or errors in any of the logfiles. Modelsim or any other synthesis tool do not even compile that, which is what I'd expect. Interesting enough, the simulation tool that comes with Vivado does also not compile that, but the synthesis tool by the same vendor integrated in the same IDE does not seem to have a problem with it. It took a lot of complaining and week-long discussions until Xilinx even acknowledged that this is indeed a bug, and there's a CR for it now. Don't know when it will be fixed... I haven't tried the latest Vivado release though; it might be fixed now, but at least there's nothing in the release notes about this issue being addressed. I'm in release-freeze now and don't have half a day to spare to install and try out the new release. Anyway, to cut a long story short: - Xilinx still use std_logic_arith in almost all of their code - Xilinx still use std_logic in almost any case, even if std_ulogic would make a lot more sense IMHO Old habits really die hard... From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.236.202.207 with SMTP id d55mr1280703yho.4.1421197035085; Tue, 13 Jan 2015 16:57:15 -0800 (PST) X-Received: by 10.140.39.39 with SMTP id u36mr16208qgu.17.1421197035003; Tue, 13 Jan 2015 16:57:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!v8no809938qal.1!news-out.google.com!n9ni488qai.0!nntp.google.com!bm13no292047qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Jan 2015 16:57:14 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=94.4.87.209; posting-account=Uk0pMgoAAADu6ZbtaHLSUFljg_8C_HaD NNTP-Posting-Host: 94.4.87.209 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Subject: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: KM23 Injection-Date: Wed, 14 Jan 2015 00:57:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 15 Xref: mx02.eternal-september.org comp.lang.vhdl:8050 Hi, I use the following package only in my vhdl file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; In the code, i compare an std_logic_vector signal : A with a constant value= , e.g ...if A<=3D"00001011" then yet the code was checked correctly by Xilinx ISE. My understanding is that = STD_LOGIC_1164 package does not include an implementation of inequalities h= aving as an operand std_logic_vector so why the above code statement was ac= cepted and will the above comparison treat A as signed or unsigned number? Cheers From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.68.224.5 with SMTP id qy5mr3534024pbc.7.1421249584172; Wed, 14 Jan 2015 07:33:04 -0800 (PST) X-Received: by 10.140.95.182 with SMTP id i51mr18246qge.12.1421249583912; Wed, 14 Jan 2015 07:33:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h15no5141849igd.0!news-out.google.com!ik4ni254qab.1!nntp.google.com!v8no928309qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Jan 2015 07:33:03 -0800 (PST) In-Reply-To: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7576a42f-3a97-406a-a67e-a0cafb8c5779@googlegroups.com> Subject: Re: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: Thomas Stanka Injection-Date: Wed, 14 Jan 2015 15:33:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2110 X-Received-Body-CRC: 1904466646 Xref: mx02.eternal-september.org comp.lang.vhdl:8052 Am Mittwoch, 14. Januar 2015 01:57:16 UTC+1 schrieb KM23: > use IEEE.STD_LOGIC_1164.ALL; [..] > ...if A<=3D"00001011" then Std_ulogic_vector means your signal A is an arbitrary collection of single = bits without further meaning, than beeing a collection of 8 bits (eg. the s= tatus signals of 8 one bit inputs collected). If you like to compare a collection of bits with an string containing bits = the operation "=3D" is well defined. The operation ">" and "<" can only mea= n has more or less bits.=20 If you want to compare if A <=3D "101" you need to define if "101" is a col= lection of bits and you like to know if A has no more than 3 bits, or if y= ou like to see if A<=3D5 or A<=3D-3. This can only be achieved by declaring= explicite, that A is signed or unsigned instead of arbitrary bit collectio= n. This is usually done with numeric_std package. From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.43.99.202 with SMTP id ct10mr5763276icc.29.1421268637144; Wed, 14 Jan 2015 12:50:37 -0800 (PST) X-Received: by 10.50.7.100 with SMTP id i4mr126279iga.11.1421268637064; Wed, 14 Jan 2015 12:50:37 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!h15no3401587igd.0!news-out.google.com!qk8ni6628igc.0!nntp.google.com!h15no5313653igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 14 Jan 2015 12:50:36 -0800 (PST) In-Reply-To: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.83.214; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.83.214 References: <1caf4b3d-c75d-42a8-b606-a65774e3d27b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: compare std_logic_vector to a constant using std_logic_vector package ONLY,possible? From: Jim Lewis Injection-Date: Wed, 14 Jan 2015 20:50:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8053 > ...if A<=3D"00001011" then All enumerated types and arrays of enumerated types implicitly define the r= egular ordering relational operators (>, >=3D, <, <=3D). Unfortunately it = is not numerically ordered, so the results may not be as expected. Instead= it is dictionary ordered.=20 First you have to look at the element type, which is std_logic whose base t= ype is std_ulogic. For an enumerated type, such as std_ulogic, left values= are less than right values, hence, for std_ulogic (and std_logic): 'U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-' For equal length arrays whose element base type is std_ulogic (such as std_= logic_vector or std_ulogic_vector) whose values are only 0 or 1, things wor= k out fine: "1010" > "0101" Note that dictionary comparisons always compare the left element first. He= nce, for string, something that starts with 'S' is always less than somethi= ng that starts with 'T' independent of length. This is great for sorting s= trings into a dictionary and is the only practical default - if we are goin= g to provide such as thing. OTOH, this is not so great if you are thinking things are numeric. For exa= mple, if the arrays are not equal length, then the following is true becaus= e the leading '1'on the left parameter is > the leading '0' of the right pa= rameter. =20 "100" > "0111" Hence, with only "use ieee.std_logic_1164.all", you have potential exposure= to bad coding practices that mistakenly think of std_logic_vector as numer= ic (such as unsigned). =20 Many will argue, never use std_logic_vector for math and ">" is math. I ge= nerally agree. So what do I do? How do I protect my design and design team from this. Fi= rst you have to decide a policy and how to implement it.=20 1) Forbid use of regular ordering relational operators (>, >=3D, <, <=3D) w= ith std_logic_vector and enforce it with a lint tool. However this means y= ou have to buy and require the use of a lint tool. 2) Forbid use of regular ordering relational operators (>, >=3D, <, <=3D) w= ith std_logic_vector and enforce it by using the both of the following pack= age references. Note that this generates errors by referencing two definit= ions for each of the operators, and hence, when used the expression becomes= ambiguous. Note this may be problematic since numeric_std_unsigned was in= troduced in 1076-2008 and it may not yet be supported by your synthesis too= ls. =20 library ieee ;=20 use ieee.numeric_std_unsigned.all ;=20 use ieee.std_logic_unsigned.all ; 3) Relax the rules some. Our biggest concern is design correctness. Allow= std_logic_vector to be interpreted as an unsigned value and either referen= ce numeric_std_unsigned (preferred, but it is VHDL-2008 and may not be impl= emented by your synthesis tool yet - but if it is not be sure to submit a b= ug report) or std_logic_unsigned (not preferred - this is an old shareware = package that is not an IEEE standard and perhaps does not belong in the IEE= E library - OTOH, it is well supported and it plays nice with other package= s - such as numeric_std). =20 The nice result of this is that it also allows comparisons that include int= egers: if A <=3D 11 then=20 Note, some suggest that the overloading of ">" and friends in numeric_std_u= nsigned/std_logic_unsigned is illegal. This was a very conservative interp= retation of 1076 prior to VHDL-2008. It was fixed for all revisions of VHD= L with an ISAC resolution prior to VHDL-2008 that determined that explicitl= y defined operators always overload implicitly defined operators without cr= eating any ambiguity. I note that even the VHDL FAQ is out of date on this = issue.=20 4) Be formal, but practical. Never use std_logic_vector. Only use numeric= types, such as unsigned and signed from package ieee.numeric_std. Types s= igned and unsigned also support comparisons with integers. There are probably a few strategies I left out. =20 Note that VHDL-2008 introduces matching operators which also address this i= ssue by not defining them for types that do not have a numeric interpretati= on. These operators are: ?=3D, ?/=3D, ?>, ?>=3D, ?<, ?<=3D Best Regards, Jim Lewis IEEE 1076 WG Member (among other things) From newsfish@newsfish Tue Dec 29 16:43:42 2015 X-Received: by 10.70.13.161 with SMTP id i1mr8694752pdc.3.1421347743306; Thu, 15 Jan 2015 10:49:03 -0800 (PST) X-Received: by 10.182.230.133 with SMTP id sy5mr97997obc.1.1421347743173; Thu, 15 Jan 2015 10:49:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5925470igd.0!news-out.google.com!db6ni86igc.0!nntp.google.com!h15no3804604igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 15 Jan 2015 10:49:03 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: Andy Injection-Date: Thu, 15 Jan 2015 18:49:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8054 VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_ve= ctor, using a new syntax that effectively applies the scalar resolution fun= ction to each bit (meaning each bit is also resolved), so they are now inte= rchangeable.=20 Whether or not multiple drivers are allowed is dependent on the type/subtyp= e of the object being driven. So now, you can declare your signals/ports as= SULV and connect to IP with SLV ports just fine, with no port conversions = or any other syntactic gymnastics. I do not know whether Xilinx Vivado supports this yet. If not, open a bug f= or it. This is how we get what we want. There are other (better) synthesis = tools available (Synplify & Precision are two), and it doesn't hurt to remi= nd Xilinx of that fact. Andy From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Thu, 15 Jan 2015 10:54:45 -0800 Organization: Highland Technology, Inc. Lines: 23 Message-ID: <20150115105445.75ba3f19@rg.highlandtechnology.com> References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="00c0529b11392f77bf1ca106a3de87ed"; logging-data="23176"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IbbcfoPdbOP3CcSxt2l9k" X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) Cancel-Lock: sha1:TRIY+hUrQhCisOHWacEExkrPEiY= Xref: mx02.eternal-september.org comp.lang.vhdl:8055 On Thu, 15 Jan 2015 10:49:03 -0800 (PST) Andy wrote: > VHDL-2008 redefines std_logic_vector as a resolved subtype of std_ulogic_vector, using a new syntax that effectively applies the scalar resolution function to each bit (meaning each bit is also resolved), so they are now interchangeable. > > Whether or not multiple drivers are allowed is dependent on the type/subtype of the object being driven. So now, you can declare your signals/ports as SULV and connect to IP with SLV ports just fine, with no port conversions or any other syntactic gymnastics. > > I do not know whether Xilinx Vivado supports this yet. If not, open a bug for it. This is how we get what we want. There are other (better) synthesis tools available (Synplify & Precision are two), and it doesn't hurt to remind Xilinx of that fact. > > Andy The problem is that threat lacks credibility. Xilinx doesn't give a damn whether you don't want to use their software to do synthesis so long as you're going to buy their silicon to put it on. The software is almost certainly a money loser, even with their preposterous and short-sighted efforts to squeeze money out of you for the right to use their chips. Not that Altera's more than fractionally better, mind. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.lang.vhdl Subject: Re: Learning VHDL beyond basics Date: Mon, 19 Jan 2015 11:52:09 +0100 Lines: 23 Message-ID: References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net aWZrqIGeC1xPGAYKpGGxFQKKVvlkEXvw/cBlkb370ofpdeVuBX Cancel-Lock: sha1:DSBkj1ULzfMKs01imx048ZDaU5w= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 In-Reply-To: Xref: mx02.eternal-september.org comp.lang.vhdl:8056 Andy wrote: > I do not know whether Xilinx Vivado supports this yet. If not, open a > bug for it. This is how we get what we want. There are other (better) > synthesis tools available (Synplify & Precision are two), and it > doesn't hurt to remind Xilinx of that fact. Well, it's getting increasingly difficult to open bugs. They used to have this WebCase thing on their website you could use, but that is now only available to premium customers. The rest has to go through the Xilinx user support forums and/or through the FAE that is usually totally swamped already. And, as I said before, going through the forum for me resulted in week-long discussions before they even ackowledged that there was indeed a problem there (A SULV with multiple drivers should result in an error no matter which VHDL standard is chosen...). So if it's that hard to get them recognize something that very clearly is a bug, how interested do you think they are in adding "nice to have" features that the majority of FPGA developers still doesn't even know about (sadly)? AFAIK, the rudimentary VHDL-2008-support they do have was requested by one of the big customers, the rest they don't really seem to care about... From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.236.28.102 with SMTP id f66mr2245541yha.31.1421815313883; Tue, 20 Jan 2015 20:41:53 -0800 (PST) X-Received: by 10.140.39.39 with SMTP id u36mr3859qgu.17.1421815313825; Tue, 20 Jan 2015 20:41:53 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!v8no2472845qal.1!news-out.google.com!l7ni0qai.0!nntp.google.com!bm13no1955319qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Jan 2015 20:41:53 -0800 (PST) In-Reply-To: <20150115105445.75ba3f19@rg.highlandtechnology.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.36 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> <20150115105445.75ba3f19@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: Andy Injection-Date: Wed, 21 Jan 2015 04:41:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:8057 Does anyone know that Vivado does not support this 2008 feature? Or do we simply assume not, and accept it like sheep? Vote with your next design-in. Andy From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.236.28.230 with SMTP id g66mr4922007yha.2.1421849663389; Wed, 21 Jan 2015 06:14:23 -0800 (PST) X-Received: by 10.182.153.66 with SMTP id ve2mr2167obb.40.1421849663148; Wed, 21 Jan 2015 06:14:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!bm13no2048278qab.0!news-out.google.com!db6ni4746igc.0!nntp.google.com!hl2no745460igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jan 2015 06:14:22 -0800 (PST) In-Reply-To: <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=12.251.154.34; posting-account=w728HAoAAAAF2xrMb6mkfbhZUlYwqJjV NNTP-Posting-Host: 12.251.154.34 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> <20150109152203.61d253d8@rg.highlandtechnology.com> <20150115105445.75ba3f19@rg.highlandtechnology.com> <63571c7d-10e7-47d5-86a9-28fded86747f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: KKoorndyk Injection-Date: Wed, 21 Jan 2015 14:14:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3068 X-Received-Body-CRC: 3538559653 Xref: mx02.eternal-september.org comp.lang.vhdl:8058 On Tuesday, January 20, 2015 at 11:41:55 PM UTC-5, Andy wrote: > Does anyone know that Vivado does not support this 2008 feature? > > Or do we simply assume not, and accept it like sheep? > > Vote with your next design-in. > > Andy http://www.xilinx.com/support/answers/62005.html The supported language constructs are as follows: Feature Vivado Release Unconstrained Element Types 2014.3 Relational operators: ??, ?=, ?/=, ?>, ?>=, ?<, ?<= 2014.3 Maximum and Minimum 2014.3 shift operators 2014.3 bit_vector, boolean_vector, integer_vector and the predefined operators 2014.3 Strength Reduction Functions 2014.3 Unary reduction Operators (and,or,nand,nor,xor,xnor) 2014.3 Array Logic Operators 2014.3 Scalar Logic Operators 2014.3 If-else-if & Case Generate 2014.3 Sequential Signal Assignments 2014.3 Matching Select for Variables 2014.3 Matching Case for Variables 2014.3 Matching Select for Signals 2014.3 Matching Case for Signals 2014.3 Case? Statement 2014.3 Select? Statement 2014.3 Slices in aggregates 2014.3 Sized Bit String Literals 2014.3 Reading Output Ports 2014.3 Expressions in Port Maps 2014.3 Process(all) 2014.3 Referencing Generics in Generic Lists 2014.3 Relaxed return rules for Function Return Values 2014.3 Relaxed Qualified Expressions 2014.3 Type Conversions 2014.3 Extensions to globally static and locally static expressions 2014.3 Static Ranges and Integer expressions in range bounds 2014.3 Block Comments 2014.3 std_logic_1164/Numeric_bit/Numeric_std updates 2014.3 From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.236.11.193 with SMTP id 41mr1787545yhx.53.1421907304948; Wed, 21 Jan 2015 22:15:04 -0800 (PST) X-Received: by 10.51.15.133 with SMTP id fo5mr556276igd.3.1421907304738; Wed, 21 Jan 2015 22:15:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!bm13no2200035qab.0!news-out.google.com!db6ni5834igc.0!nntp.google.com!h15no1699509igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Jan 2015 22:15:04 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:7:1780:4ef:b9a0:bdba:7dfc:be59; posting-account=6q9j7QoAAABb1svNDLq2pkeRwQoxnxfP NNTP-Posting-Host: 2601:7:1780:4ef:b9a0:bdba:7dfc:be59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Pulse Width detection in verilog? From: redgar@pdx.edu Injection-Date: Thu, 22 Jan 2015 06:15:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8059 I'm working on a project that requires me to detect the frequency and duty cycle of the PWM signal this is what i have so far but i have couple errors that i don't know how to fix: module low_high_count( input clk, input pwm0_signal, input reset_n, output [31:0] frequency, //embsus GPIO outputs count output [31:0] duty_cycle); //inter variables wire sysclk; wire sysreset_n; wire axi_timer_0_pwm0; wire [31:0] axi_gpio_1_duty_cycle; wire [31:0] axi_gpio_1_frequency; //local variables used for calcuation reg [31:0] hightime_count; reg [31:0] lowtime_count; reg [31:0] duty_cycle_calculation; reg [31:0] frequency_calculation; reg [31:0] period_calculation; reg [31:0] old_frequency; reg [31:0] old_duty_cycle; assign old_frequency =0; assign old_duty_cycle=0; //connect the ports-wires ("wire" = "verilog input/output") assign axi_timer_0_pwm0 = pwm0_signal; assign sysclk=clk; assign sysreset_n=reset_n; assign axi_gpio_1_frequency = frequency; assign axi_gpio_1_duty_cycle = duty_cycle; //counts, starting at the first positive edge, the hight time always @(posedge pwm0_signal ) if(!reset_n) begin hightime_count <= 32'd0 ; //resets positive clock count end else begin hightime_count <= hightime_count + 32'd1; //increment the count by 1 end always @(negedge pwm0_signal) if(!reset_n) begin lowtime_count <= 32'd0; //resets negative clock count end else begin lowtime_count <= lowtime_count + 32'd1; //increment the count by 1 end //duty cycle and frequency calculation assign period_calculation = (hightime_count + lowtime_count)/100000000; assign frequency_calculation = (1/period_calculation); assign duty_cycle_calculation = (hightime_count/(hightime_count + lowtime_count))*100; assign old_frequency = frequency_calculation; assign old_duty_cycle = duty_cycle_calculation; assign frequency = frequency_calculation; assign duty_cycle = duty_cycle_calculation; endmodule thank you so much edgar From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.236.17.197 with SMTP id j45mr763741yhj.35.1421930688228; Thu, 22 Jan 2015 04:44:48 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr17150qgp.16.1421930688210; Thu, 22 Jan 2015 04:44:48 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!bm13no2259689qab.0!news-out.google.com!l7ni0qai.0!nntp.google.com!bm13no2259687qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Jan 2015 04:44:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77bbd3f3-50db-4dcd-83bc-b6287d8ebc75@googlegroups.com> Subject: Re: Pulse Width detection in verilog? From: Thomas Stanka Injection-Date: Thu, 22 Jan 2015 12:44:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 45 X-Received-Bytes: 2743 X-Received-Body-CRC: 2884996525 Xref: mx02.eternal-september.org comp.lang.vhdl:8060 Hello, there exists a group for verilog. YOu might get some answers concerning ver= ilog there. But the principle is the same in VHDL, so this post should stil= l help you. BTW your topic is somehow a FAQ, Google provides several sollut= ions to this problem. > module low_high_count( > input clk, > input pwm0_signal, > input reset_n, > output [31:0] frequency, //embsus GPIO outputs count > output [31:0] duty_cycle); > //counts, starting at the first positive edge, the hight time > always @(posedge pwm0_signal ) It is usually the wrong way to use the signal you like to measure as clock = signal in a process. What you like to do is to oversample the pwm signal with clk and measure ho= w many cycles of clk the signal pwm is high after a rising edge. Therefore you use best a two rank FF to bring the signal PWM stable in cloc= k domain of signal "clk" (avoid problems with clock domain crossing), use a= third ff for edge detection and measure the number of clock cycles the sig= nal in clk-clock domain is set high. In VHDL this would be: signal pwm_clk : std_ulogic_vector(1 downto 0); signal counter : integer range 0 to .....; process (clk, reset) if reset=3DACTIVE then pwm_clk <=3D (others=3D>'0'); counter <=3D 0; elsif rising_edge(clk) pwm_clk <=3D pwm_clk(1) & pwm0_signal; if pwm_clk(2 downto 1) =3D "01" then counter <=3D 0; elsif pwm_clk(2)=3D'1' then counter <=3D counter+1; end if; end if; From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx37.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: UVM for VHDL Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150128-0, 28/01/2015), Outbound message X-Antivirus-Status: Clean Lines: 13 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1422440924 86.17.210.161 (Wed, 28 Jan 2015 10:28:44 UTC) NNTP-Posting-Date: Wed, 28 Jan 2015 10:28:44 UTC Organization: virginmedia.com Date: Wed, 28 Jan 2015 10:28:43 +0000 X-Received-Body-CRC: 240998217 X-Received-Bytes: 1252 Xref: mx02.eternal-september.org comp.lang.vhdl:8061 For those who haven't seen it: http://bitvis.no/resources/presentations/uvvm/ Looks promising and IMHO hugely important for the VHDL community (even if you don't need it). With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to tackle complex verification jobs. Regards, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.66.65.202 with SMTP id z10mr1212394pas.29.1422551944992; Thu, 29 Jan 2015 09:19:04 -0800 (PST) X-Received: by 10.140.108.166 with SMTP id j35mr27362qgf.18.1422551944940; Thu, 29 Jan 2015 09:19:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no4395453igb.0!news-out.google.com!q4ni24qan.0!nntp.google.com!v8no4342399qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Jan 2015 09:19:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=84.212.255.208; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 84.212.255.208 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: UVM for VHDL From: espen.tallaksen@bitvis.no Injection-Date: Thu, 29 Jan 2015 17:19:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2215 X-Received-Body-CRC: 744020633 Xref: mx02.eternal-september.org comp.lang.vhdl:8062 onsdag 28. januar 2015 11.28.48 UTC+1 skrev HT-Lab f=F8lgende: > For those who haven't seen it: >=20 > http://bitvis.no/resources/presentations/uvvm/ >=20 > Looks promising and IMHO hugely important for the VHDL community (even=20 > if you don't need it). >=20 > With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to= =20 > tackle complex verification jobs. >=20 > Regards, > Hans > www.ht-lab.com Thanks Hans, for the nice feedback. We plan to do the UVVM release in Q2 (May?) with a beta release in March. We will present an introduction to UVVM at FPGA-forum in February, and prob= ably publish the presentation not long after that. This will show what we w= ill implement in the first version that is focused on making a good verific= ation component system with a structured distribution of commands from the = sequencer to the verification components. This will allow both direct comma= nds and local sequencers - and an easily understandable way of controlling = the test cases. After that we will continue with more advanced features.=20 Best regards Espen www.bitvis.no From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!eu.feeder.erje.net!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 29 Jan 2015 11:35:56 -0600 From: friendsa17 Subject: Re: Carry Save Adder (CSA) Verilog code Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 41488da0-fe9c-4b8d-ab6b-06cf7dcbe2b2 References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> Message-ID: <8PKdnaDTBfnh8lfJnZ2dnUU7-VednZ2d@giganews.com> Date: Thu, 29 Jan 2015 11:35:56 -0600 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-8zpaGya4FHmSlzIxey4qTzkNulz5735BeGzoNJC5liesHu1QWvYORZimhMuadsPY3xlbegIiDaOzCTA!y4wRKGdR70s/PXjct44E1aMrFVQcIgJi3jf+M0su/AA6b/JPwMdKUdIH/c7EAVidO9SImnD3jvXm!Y0Y= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1051 Xref: mx02.eternal-september.org comp.lang.vhdl:8063 sir, i need verilog coding for 16pt dif computation From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.67.1.100 with SMTP id bf4mr5349749pad.4.1422627570891; Fri, 30 Jan 2015 06:19:30 -0800 (PST) X-Received: by 10.140.16.55 with SMTP id 52mr81884qga.31.1422627570846; Fri, 30 Jan 2015 06:19:30 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no3745894igb.0!news-out.google.com!q4ni22qan.0!nntp.google.com!bm13no3998950qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 06:19:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.164.136.112; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 146.164.136.112 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: FSM recurring state technique From: revkarol Injection-Date: Fri, 30 Jan 2015 14:19:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8064 Let's say I have an FSM such as the example on the Altera website. =20 This is a typical 4-state FSM in the Moore style.=20 Now, let's say I want a state where the inputs don't change but I want the = outputs to change (say, a counter output). For example, I want to get to s= tate s2 and when I do, I'll stay in state s2 for say 10 cycles and then exi= t to state s3. I'm not sure how to do this. Using the format of the examp= le below, because the state doesn't change, the output is latched. This seems like a standard problem, but I don't know the standard solution. Advance thanks, Karol. -- A Moore machine's outputs are dependent only on the current state. -- The output is written only when the state changes. (State -- transitions are synchronous.) library ieee; use ieee.std_logic_1164.all; entity moore_4s is port( clk : in std_logic; data_in : in std_logic; reset : in std_logic; data_out : out std_logic_vector(1 downto 0) ); =09 end entity; architecture rtl of moore_4s is -- Build an enumerated type for the state machine type state_type is (s0, s1, s2, s3); =09 -- Register to hold the current state signal state : state_type; begin -- Logic to advance to the next state process (clk, reset) begin if reset =3D '1' then state <=3D s0; elsif (rising_edge(clk)) then case state is when s0=3D> if data_in =3D '1' then state <=3D s1; else state <=3D s0; end if; when s1=3D> if data_in =3D '1' then state <=3D s2; =20 else state <=3D s1; end if; when s2=3D> if data_in =3D '1' then -- here I would have something like -- if counter > 10 then state <=3D s3; else state <=3D s2; end if; when s3 =3D> if data_in =3D '1' then state <=3D s0; else state <=3D s3; end if; end case; end if; end process; =09 -- Output depends solely on the current state process (state) begin =09 case state is when s0 =3D> data_out <=3D "00"; when s1 =3D> data_out <=3D "01"; when s2 =3D> data_out <=3D "10"; -- here I would have=20 data_out <=3D value depending on counter; when s3 =3D> data_out <=3D "11"; end case; end process; =09 end rtl; From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Fri, 30 Jan 2015 11:10:41 -0500 Organization: Alacron, Inc. Lines: 126 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Jan 2015 16:12:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="27944"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+XCwOfMxMJSa3/xEY4K7DZASDEsdtblM=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:MFWG3Xs6sfSraEHofF2utUfLAmQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8065 revkarol wrote: > Let's say I have an FSM such as the example on the Altera website. > This is a typical 4-state FSM in the Moore style. > > Now, let's say I want a state where the inputs don't change but I want the outputs to change (say, a counter output). For example, I want to get to state s2 and when I do, I'll stay in state s2 for say 10 cycles and then exit to state s3. I'm not sure how to do this. Using the format of the example below, because the state doesn't change, the output is latched. > > This seems like a standard problem, but I don't know the standard solution. > > > > Advance thanks, > Karol. > > > > > > -- A Moore machine's outputs are dependent only on the current state. > -- The output is written only when the state changes. (State > -- transitions are synchronous.) > > library ieee; > use ieee.std_logic_1164.all; > > entity moore_4s is > > port( > clk : in std_logic; > data_in : in std_logic; > reset : in std_logic; > data_out : out std_logic_vector(1 downto 0) > ); > > end entity; > > architecture rtl of moore_4s is > > -- Build an enumerated type for the state machine > type state_type is (s0, s1, s2, s3); > > -- Register to hold the current state > signal state : state_type; > > begin > -- Logic to advance to the next state > process (clk, reset) > begin > if reset = '1' then > state <= s0; > elsif (rising_edge(clk)) then > case state is > when s0=> > if data_in = '1' then > state <= s1; > else > state <= s0; > end if; > when s1=> > if data_in = '1' then > state <= s2; > > else > state <= s1; > end if; > when s2=> > if data_in = '1' then > -- here I would have something like > -- if counter > 10 then > state <= s3; > else > state <= s2; > end if; > when s3 => > if data_in = '1' then > state <= s0; > else > state <= s3; > end if; > end case; > end if; > end process; > > -- Output depends solely on the current state > process (state) > begin > > case state is > when s0 => > data_out <= "00"; > when s1 => > data_out <= "01"; > when s2 => > data_out <= "10"; > -- here I would have > data_out <= value depending on counter; > when s3 => > data_out <= "11"; > end case; > end process; > > end rtl; It's not hard to add "counter" as a ranged integer and then increment it while in state s2. Then the only other thing you need is to reset the counter before entering state s2. You can do this in several ways: 1) reset "counter" in all other states. 2) reset "counter" in states that can lead to s2. 3) reset "counter" in the transition terms (when assigning state <= s2 from another state). There are other ways to do this including building a timer "subroutine." I've used this is more complex FSM's where I needed a variable amount of time spent in a number of different states. In this case I have a state that just counts down on a counter until it reaches 0. States that need the delay will set up their outputs as required, set the delay value into the counter, store the "return state" in another signal of the same type as "state" and then set "state" to the wait state. When the counter is decremented to zero, the wait state then just assigns state to the return state. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.68.57.175 with SMTP id j15mr5788169pbq.1.1422638538567; Fri, 30 Jan 2015 09:22:18 -0800 (PST) X-Received: by 10.140.19.193 with SMTP id 59mr95937qgh.23.1422638538306; Fri, 30 Jan 2015 09:22:18 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!bloom-beacon.mit.edu!bloom-beacon.mit.edu!newsswitch.lcs.mit.edu!ottix-news.ottix.net!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4965751igb.0!news-out.google.com!q4ni24qan.0!nntp.google.com!v8no4552866qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 09:22:18 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.164.136.112; posting-account=r2yQngoAAABH6wHUUUDXnfZDWZunMbzu NNTP-Posting-Host: 146.164.136.112 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Subject: Re: FSM recurring state technique From: revkarol Injection-Date: Fri, 30 Jan 2015 17:22:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 145 Xref: mx02.eternal-september.org comp.lang.vhdl:8066 On Friday, 30 January 2015 14:12:42 UTC-2, Gabor Sz wrote: > revkarol wrote: > > Let's say I have an FSM such as the example on the Altera website. =20 > > This is a typical 4-state FSM in the Moore style.=20 > >=20 > > Now, let's say I want a state where the inputs don't change but I want = the outputs to change (say, a counter output). For example, I want to get = to state s2 and when I do, I'll stay in state s2 for say 10 cycles and then= exit to state s3. I'm not sure how to do this. Using the format of the e= xample below, because the state doesn't change, the output is latched. > >=20 > > This seems like a standard problem, but I don't know the standard solut= ion. > >=20 > >=20 > >=20 > > Advance thanks, > > Karol. > >=20 > >=20 > >=20 > >=20 > >=20 > > -- A Moore machine's outputs are dependent only on the current state. > > -- The output is written only when the state changes. (State > > -- transitions are synchronous.) > >=20 > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity moore_4s is > >=20 > > port( > > clk : in std_logic; > > data_in : in std_logic; > > reset : in std_logic; > > data_out : out std_logic_vector(1 downto 0) > > ); > > =09 > > end entity; > >=20 > > architecture rtl of moore_4s is > >=20 > > -- Build an enumerated type for the state machine > > type state_type is (s0, s1, s2, s3); > > =09 > > -- Register to hold the current state > > signal state : state_type; > >=20 > > begin > > -- Logic to advance to the next state > > process (clk, reset) > > begin > > if reset =3D '1' then > > state <=3D s0; > > elsif (rising_edge(clk)) then > > case state is > > when s0=3D> > > if data_in =3D '1' then > > state <=3D s1; > > else > > state <=3D s0; > > end if; > > when s1=3D> > > if data_in =3D '1' then > > state <=3D s2; > > =20 > > else > > state <=3D s1; > > end if; > > when s2=3D> > > if data_in =3D '1' then > > -- here I would have something = like > > -- if counter > 10 then > > state <=3D s3; > > else > > state <=3D s2; > > end if; > > when s3 =3D> > > if data_in =3D '1' then > > state <=3D s0; > > else > > state <=3D s3; > > end if; > > end case; > > end if; > > end process; > > =09 > > -- Output depends solely on the current state > > process (state) > > begin > > =09 > > case state is > > when s0 =3D> > > data_out <=3D "00"; > > when s1 =3D> > > data_out <=3D "01"; > > when s2 =3D> > > data_out <=3D "10"; > > -- here I would have=20 > > data_out <=3D value depending on counte= r; > > when s3 =3D> > > data_out <=3D "11"; > > end case; > > end process; > > =09 > > end rtl; >=20 > It's not hard to add "counter" as a ranged integer and > then increment it while in state s2. Then the only > other thing you need is to reset the counter before > entering state s2. You can do this in several ways: >=20 > 1) reset "counter" in all other states. > 2) reset "counter" in states that can lead to s2. > 3) reset "counter" in the transition terms (when assigning > state <=3D s2 from another state). >=20 > There are other ways to do this including building a timer > "subroutine." I've used this is more complex FSM's where > I needed a variable amount of time spent in a number of > different states. In this case I have a state that just > counts down on a counter until it reaches 0. States that > need the delay will set up their outputs as required, set > the delay value into the counter, store the "return state" > in another signal of the same type as "state" and then > set "state" to the wait state. When the counter is decremented > to zero, the wait state then just assigns state to the return > state. >=20 > --=20 > Gabor Hi Gabor, I think I follow you. So what I think I should do is create another clocke= d process that deals with the counting (and the special output based on the= counting). When I enter the correct state in the FSM, I set an enable for= this clocked process. Without the enable the process does essentially not= hing. Then when I'm done I set a "finished" flag, and that in turn trigger= s the FSM to exit the current state and de-asserts the enable flag. Many thanks, Karol. From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Supersedes: Date: Fri, 30 Jan 2015 17:55:38 +0000 (UTC) Organization: A noiseless patient Spider Lines: 69 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 30 Jan 2015 17:55:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="3096"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mw49u9j3d0cNr5LkWJRgD" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Key: sha1:7atxe9c+fZEObzTk+RugA5eQacI= Cancel-Lock: sha1:CWZ/fYmbZtZDd/9Xd1cj/GUWctI= Xref: mx02.eternal-september.org comp.lang.vhdl:8068 On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: > > Hi Gabor, > > I think I follow you. So what I think I should do is create another > clocked process that deals with the counting (and the special output > based on the counting). When I enter the correct state in the FSM, I > set an enable for this clocked process. Without the enable the process > does essentially nothing. Then when I'm done I set a "finished" flag, > and that in turn triggers the FSM to exit the current state and > de-asserts the enable flag. > > Many thanks, > Karol. More processes = more problems. I've frequently done things like below (untested, so beware the syntax). Note two important things. 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to use two process state machines, even for simple Moore ones. They're wrong, it just adds confusion to your world. 2) The states have real people names, not S0, S1, S2. signal go : boolean; signal count : integer range 0 to 15; signal lamp : boolean; type t_state is (IDLE, LAMPOFF, LAMPON); signal state : t_state; ... FSM: process(clk) begin if rising_edge(clk) then lamp <= false; case state is when IDLE => count <= 0; if go then state <= LAMPOFF; end if; when LAMPOFF => if count = 15 then count <= 0; state <= LAMPON; else count <= count + 1; end if; when LAMPON => lamp <= true; if count = 15 then count <= 0; state <= IDLE; else count <= count + 1; end if; end case; end if; end process FSM; -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Fri, 30 Jan 2015 14:02:18 -0500 Organization: Alacron, Inc. Lines: 117 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 30 Jan 2015 19:03:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9899"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vy5VAmI6oKD6uEk37LrJRiB8bWEOaNAY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:2MWcg8jgy6EbFx11Zd6/LT/ZAU0= Xref: mx02.eternal-september.org comp.lang.vhdl:8069 Rob Gaddi wrote: > On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >> Hi Gabor, >> >> I think I follow you. So what I think I should do is create another >> clocked process that deals with the counting (and the special output >> based on the counting). When I enter the correct state in the FSM, I >> set an enable for this clocked process. Without the enable the process >> does essentially nothing. Then when I'm done I set a "finished" flag, >> and that in turn triggers the FSM to exit the current state and >> de-asserts the enable flag. >> >> Many thanks, >> Karol. > > More processes = more problems. > > I've frequently done things like below (untested, so beware the syntax). > Note two important things. > > 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to > use two process state machines, even for simple Moore ones. They're > wrong, it just adds confusion to your world. > > 2) The states have real people names, not S0, S1, S2. > > signal go : boolean; > signal count : integer range 0 to 15; > signal lamp : boolean; > type t_state is (IDLE, LAMPOFF, LAMPON); > signal state : t_state; > > ... > > FSM: process(clk) > begin > if rising_edge(clk) then > lamp <= false; > > case state is > when IDLE => > count <= 0; > if go then > state <= LAMPOFF; > end if; > > when LAMPOFF => > if count = 15 then > count <= 0; > state <= LAMPON; > else > count <= count + 1; > end if; > > when LAMPON => > lamp <= true; > if count = 15 then > count <= 0; > state <= IDLE; > else > count <= count + 1; > end if; > end case; > end if; > end process FSM; > That is in fact what I was suggesting. There is no need to count in a separate process, since your FSM was already a clocked process. Similarly, here's the "subroutine" approach: signal go : boolean; signal count : integer range 0 to 15; signal lamp : boolean; type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); signal state : t_state; signal rtn_state : t_state; ... FSM: process(clk) begin if rising_edge(clk) then case state is when IDLE => count <= 0; if go then state <= LAMPOFF; end if; when LAMPOFF => lamp <= false; count <= 15; rtn_state <= LAMPON; state <= SPIN; when LAMPON => lamp <= true; count <= 15; rtn_state <= IDLE; state <= SPIN; when SPIN => if count = 0 then state <= rtn_state; else count <= count - 1; end if; end case; end if; end process FSM; -- Gabor From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Proposed additions to std.env Date: Fri, 30 Jan 2015 19:26:51 +0000 (UTC) Organization: A noiseless patient Spider Lines: 51 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 30 Jan 2015 19:26:51 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="3096"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19RVfS89m8m3CHVqo6j2bwZ" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:muBxycJSNXxSqyFd8kbULpy2oQw= Xref: mx02.eternal-september.org comp.lang.vhdl:8070 A couple things that might be really nice to have, probably in std.env *** function simulation return bool; This would allow the use of if/else/endif blocks to get around one of my least favorite VHDL anti-patterns, the use of --synthesis translate_on/off Pragmas are awful. They're error-prone kludges that can lead to accidentally and silently knocking huge chunks of your code out, because a misformed pragma is just a comment. Additionally, while most vendors support knocking code out for synthesis, support for putting some back in for synthesis such as Altera's comment_as_hdl is limited. Another way around this would be to pass SIMULATION down as a generic, but this a) doesn't work for functions in packages and b) requires that you manually pass the generic all the way down the hierarchy. You could also put it into a package, but then you're responsible for manually changing it back and forth in the code. Now, an argument could be made that this is all awful because you shouldn't be doing it anyhow; that synthesizing code that is different than what you simulate is inherently dangerous. I wouldn't disagree. But at the end of the day, sometimes it's the only way to get it to actually work; the vendor synthesis tools are pretty dumb and get confused by things like assigning 'X' values so that you can trace invalid states through your simulation. Or debugging log file writes. And if there has to be a knock-out mechanism, it should at least be linguistically sound. *** function file_path return string; Provides the path to the current VHDL file. Not sure if there's a better implementation option than that, but some way of enforcing relative paths for files that is better than "Hope the tool has the same understanding of the root directory than I do." would be great. Again, there are workarounds with generics or packages, but again they're a pain for all the same reasons; who wants to have to hard code absolute paths into a VHDL package that you may need to move to another machine? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.42.10.206 with SMTP id r14mr7216247icr.15.1422654821285; Fri, 30 Jan 2015 13:53:41 -0800 (PST) X-Received: by 10.140.98.198 with SMTP id o64mr110839qge.41.1422654821205; Fri, 30 Jan 2015 13:53:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3885278igb.0!news-out.google.com!q4ni22qan.0!nntp.google.com!bm13no4084909qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 30 Jan 2015 13:53:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7ea7cdab-fac3-46c9-8f2c-3283b1803088@googlegroups.com> Subject: Re: Proposed additions to std.env From: Lars Asplund Injection-Date: Fri, 30 Jan 2015 21:53:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1430 X-Received-Body-CRC: 3399345164 Xref: mx02.eternal-september.org comp.lang.vhdl:8071 A way to get the current line number would also be great. Together with file path and the now function you have a solid foundation for logging. It can be achieved with preprocessing like we do in VUnit (https://github.com/LarsAsplund/vunit): 86810000 ps: DEBUG in traffic_logger (uart_rx.vhd:39): Received 77 but language support would be better. /Lars From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.42.111.201 with SMTP id v9mr5530056icp.1.1422903643097; Mon, 02 Feb 2015 11:00:43 -0800 (PST) X-Received: by 10.50.128.202 with SMTP id nq10mr174779igb.12.1422903642979; Mon, 02 Feb 2015 11:00:42 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no5954098igb.0!news-out.google.com!qk8ni19963igc.0!nntp.google.com!hl2no7899364igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Feb 2015 11:00:42 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.235.165.203; posting-account=jeyu9goAAAADG4d2_eLFCWm4Vp6N4Svn NNTP-Posting-Host: 117.235.165.203 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> Subject: vhdl coding for image centroid From: ann.140190@gmail.com Injection-Date: Mon, 02 Feb 2015 19:00:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1398 X-Received-Body-CRC: 2118766271 Xref: mx02.eternal-september.org comp.lang.vhdl:8072 hello, how to write the vhdl coding for finding the image centroid using following eqaution scalar (greyscale) image with pixel intensities I(x,y) http://en.wikipedia.org/wiki/Image_moment#Raw_moments M{ij} = sum_x sum_y x^i y^j I(x,y) Centroid: { x, y } = {M10/M00, M01/M00 } the pixel value have to be taken/read such that they are stored in the bram.my fpga have 8 bram of 18kb.kindly share the code thank you. From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.42.240.132 with SMTP id la4mr956411icb.15.1422967262031; Tue, 03 Feb 2015 04:41:02 -0800 (PST) X-Received: by 10.140.48.97 with SMTP id n88mr275943qga.35.1422967261995; Tue, 03 Feb 2015 04:41:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no8756143igb.0!news-out.google.com!q4ni25qan.0!nntp.google.com!v8no6263181qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 04:41:01 -0800 (PST) In-Reply-To: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <656dc9f9-79b1-4102-807c-c385e27af83f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: vhdl coding for image centroid From: KJ Injection-Date: Tue, 03 Feb 2015 12:41:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8073 On Monday, February 2, 2015 at 2:00:45 PM UTC-5, ann.1...@gmail.com wrote: > hello, > > how to write the vhdl coding for finding the image centroid using following eqaution > > scalar (greyscale) image with pixel intensities I(x,y) > http://en.wikipedia.org/wiki/Image_moment#Raw_moments > > M{ij} = sum_x sum_y x^i y^j I(x,y) > Centroid: { x, y } = {M10/M00, M01/M00 } > > the pixel value have to be taken/read such that they are stored in the bram.my fpga have 8 bram of 18kb.kindly share the code > > thank you. Perhaps you can post the code that you've written over the past two weeks, that will give us a better idea of where you're having trouble http://www.edaboard.com/thread330375.html Don't ask people to do your work unless you're paying them to do so. KJ From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.182.251.231 with SMTP id zn7mr3406998obc.24.1422980272161; Tue, 03 Feb 2015 08:17:52 -0800 (PST) X-Received: by 10.140.92.146 with SMTP id b18mr315276qge.36.1422980272127; Tue, 03 Feb 2015 08:17:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no6767203igb.0!news-out.google.com!q4ni25qan.0!nntp.google.com!v8no6334535qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 08:17:51 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.78.170.74; posting-account=7akUhQoAAABcu0ph5ZANULxKC3yW8kb5 NNTP-Posting-Host: 194.78.170.74 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0c4ad78c-03b3-4dcd-ae8f-fff345880be1@googlegroups.com> Subject: PADRE E FIGLIO DI PUTTANA, PIERLUIGI BOSCHI DI AREZZO E BANCA ETRURIA, SU INPUT DI BATTONA BERLUSCONICCHIA MARIA ELENA BOSCHI, HA PASSATO INSIDER SU BANCHE POPOLARI A VERME DAVIDE SERRA DI ALGEBRIS E TWITTER ED HA BECCATO STECCA DI 1.000.000 EURO A? From: "MICHELE RAGAZZI. ODEY GIANO." Injection-Date: Tue, 03 Feb 2015 16:17:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 14426 X-Received-Body-CRC: 3613499520 Xref: mx02.eternal-september.org comp.lang.vhdl:8074 PADRE E FIGLIO DI PUTTANA, PIERLUIGI BOSCHI DI AREZZO E BANCA ETRURIA, SU I= NPUT DI BATTONA BERLUSCONICCHIA MARIA ELENA BOSCHI, HA PASSATO INSIDER SU B= ANCHE POPOLARI A VERME DAVIDE SERRA DI ALGEBRIS E TWITTER ED HA BECCATO ST= ECCA DI 1.000.000 EURO A? =20 STO BASTARDO NAZINDRANGHETISTA DI DAVIDE SERRA DI ALGEBRIS E TWITTER HA RIC= EVUTO L'INSIDER TRADING SULLE BANCHE POPOLARI DA NOTO LAVA SOLDI MAFIOSI PI= ER LUIGI BOSCHI DI AREZZO E BANCA ETRURIA. HA PURE RAGLIATO CHE COMPRA BANC= HE POPOLARI DAL MARZO 2014. SPUTTANANDOSI ANCORA DI PIU', COME UN IMBECILLE= , PEDERASTA SODOMIZZA BAMBINI E MEGA COCAINOMANE, QUALE DA SEMPRE E'. IL SU= O POR-CO-RROTTISSIMO MATTEO RENZI (CHE VIA "SS", SPINTA E STECCHE DI SILVIO= BERLUSCONI, HA SCIPPATO SEGRETERIA PD E PALAZZO CHIGI, NEL SECONDO CASO CO= L FEBBRAIO 2014), GLI HA PASSATO, ATTRAVERSO "A ZOCCOLONA BERLUSCONICCHIA, = STECCATISSIMA E CELLULITOSA" MARIA ELENA BOSCHI http://www.dagospia.com/im= g/foto/08-2014/maria-elena-boschi-bikini-rosa-in-spiaggia-a-marina-di-pietr= asanta-581617_tn.jpg E IL VERME MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI = DI BANCA ETRURIA, L'INSIDER SULLE BANCHE POPOLARI. E PER QUESTO, STO ESCREM= ENTO HITLERIANO DI DAVIDE SERRA DI TWITTER E ALGEBRIS, SI E' MESSO A COMPRA= RE BANCHE POPOLARI DAL MARZO 2014. UN MESE DOPO (ULLALA CHE COINCIDENZA, UL= LALA). SEMPRE INSIDER E'. TRATTASI DI MANDRIA DI PORCI FASCIOCAMORRISTI, T= IPO, ANCHE, NOTO AVANZO DI GALERA PAOLO BARRAI (DI CRIMINALISSIME WMO, BSI = ITALIA SRL DI VIA SOCRATE 26 MILANO E BLOG "MERDATO"LIBERO), CHE SI FINGONO= DEL PD, X... DISTRUGGERLO, INFILTRARLO A MORTE, RENDERLO DIARREA BERLUSCON= ICCHIA! VOGLIAMO UNA ACCESISSIMA E VINCENTISSIMA REVOLUCIOOOOOON! VOGLIAMO = IL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, FALLITO ED IN GALERA! = SUBITO! PLS, DOTTOR SERGIO MATTARELLA, CI DIA UNA MANO. IN ONORE A SUO FRAT= ELLO UCCISO DALLA MAFIA ( MAFIA CHE QUANDO SI METTE LA FASCISTISSIMA CRAVAT= TA DOLCE E GABBANA, SIGNIFICA SILVIO BERLUSCONI E DAVIDE SERRA). IN ONORE A= D ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO, FATTI SPAPPOLARE, SICURISSIMA= MENTE, DA SILVIO BERLUSCONI, VIA, A SUA VOLTA, BERLUSCONIANISSIMA COSA NOST= RA! ED OLTRE A VOLER SILVIO BERLUSCONI FALLITO ED IN GALERA, VOGLIAMO VEDER= E IL SUO PICCIOTTO INCRAVATTATO, IL FACCENDIERE DI BERLUSCONAZISTI, PADANAZ= ISTI, E CRIMINALITA' ORGANIZZATE DI MEZZO MONDO, PAOLO BARRAI DI MALAVITOSA= WMO, PURE, IN GALERA! VOGLIAMO IL NUOVO GIANCARLO LANDE, IL NUOVO BERNARD = MADOFF, IL NUOVO MICHELE SINDONA, VERME CRIMINALISSIMO DAVIDE SERRA DI TWIT= TER ED ALGEBRIS, FALLITO, E PER LO MENO, PER QUALCHE MESE, IN GALERA! CHE S= IA ETICISSSIMA E VINCENTISSIMA REVOLUCIOOOOON! COME DA OTTIMO SITO INFORMARE X RESISTERE: http://www.informarexresistere.fr/2015/01/27/qualcuno-sapeva-in-anticipo-ch= e-il-governo-avrebbe-varato-un-provvedimento-sulle-banche-popolari-enormi-s= peculazioni/ COME DA CORRIERE DELLA SERA, DI, OTTIMAMENTE, ANTIRENZUSCONIANO FERRUCCIO = DE BORTOLI, DA NON TOCCARE E A TUTTI I COSTI: http://www.corriere.it/economia/15_gennaio_24/quei-movimenti-un-po-sospetti= -popolari-f59ffb1c-a3a5-11e4-808e-442fa7f91611.shtml Acquisti consistenti prima della riforma che ha abolito il voto capitario.= La famiglia Boschi ha sicurissimamente passato insider trading a Londra, t= ramite noto ladro, truffatore, nazifascista, immensamente ricicla soldi maf= iosi, che affatto va' in Tanzania a fare del bene, in quanto vi va' a ricic= lare cash di (sua) LL Lega Ladrona, come per suoi gusti sessuali di tipo de= pravatissimo: avanzo di galera Davide Serra di Algebris e Twitter. Dove pre= nderanno, le mazzette, ora, i vermi nazifascisti Pier Luigi Boschi di Banca= Etruria e sua zoccolona ( di fatto) Berlusconicchia Maria Elena Boschi ( b= astarda puttanazista che vuole sgozzare la giustizia via estremissimamente = ingiusta salvaberlusconi http://www.blitzquotidiano.it/rassegna-stampa/libe= ro-renzi-per-fare-la-pace-offre-la-salva-berlusconi-che-fara-mattarella-209= 0491/ .... che qui, non per niente, slingua un topo di fogna corrotto, ndra= nghetista, fascista, estortore di soldi alla Banca Popolare di Lodihttp://w= ww.repubblica.it/2005/l/sezioni/economia/banche21/ipolitici/ipolitici.html = .. pezzo di merda criminalissimo Paolo Romani http://www.corriere.it/methode_image/2014/08/08/Politica/Foto%20Politica%20= -%20Trattate/6ebdfe07bdd8cb1fe88af8343f8a5b1c-012-kXsC-U43030145012273wcB-5= 93x443@Corriere-Web-Sezioni.jpg?v=3D20140808175213 )? A) Alle Bahamas B) Alle Bermuda C) A Panama D) Ad Hong Kong E) A Singapore F) Alle Mauritius ( "roba" tipo Svizzera e' da anni 70, 80: stile nazimafi= oso pedofilo Silvio Berlusconi e suo B-o-ttino Craxi, dai, please) Lauti premi a chi azzecca per primo. --- BRAVO, BRAVO, DAVVERO BRAVISSIMO ELIO LANNUTTI A QUERELARE STO VERME BERLUS= -CORROTTTISSIMO DI MATTEO RENZI: http://www.ilfattoquotidiano.it/2015/01/21/denuncia-per-renzi/1357263/ CHE SBEFFEGGIA PM PER BENE, EROICI, SALVA NAZIONE ( SPESSO FATTI ESPLODERE= , COME IL NAZIMAFIOSO PEDOFILO STRAGISTA SILVIO BERLUSCONI FECE FARE CON GL= I ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO). TIPO QUELLI DI PALERMO, BARI= , MILANO, NAPOLI, DICENDO, ANZI, RAGLIANDO LORO: "'OOOO OO CHE PAURA, MI FA= NNO, OO OO" http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-pau= ra-sciopero-sindacati-polizia-illegale/295911/ CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE FRA= POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO REN= ZI! https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-di-= me-il-2-febbraio-carmelo-lopapa/ "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERLUSC= ONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA BL= OCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGLI U= LTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNER, = FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVREBB= ERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU METTI AL QUIRI= NALE UN FANTOCCIO DI MIA PROPRIETA' CHE COMPRO QUANDO VOGLIO QUALE GIULIANO= AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... O MEGLIO ANCORA, SE PARLIAMO= DI MIEI FASCIOBAMBOCCI ALLA PIERFERDINANDO CASINI O GIANNI LETTA... TUTTI = MIEI PUPAZZI CHE MI HAN GIA' GARANTITO CHE CON SEI EURO E MEZZO CASH, MI FI= RMEREBBERO TUTTE LE GRAZIE CHE VOGLIO IN NOME DELLA MIA.... PACIFICAZIONE A= LLA VASELLINA... E ... SPECIALMENTE ...GIUSTO PER ANDARE SUL SICURO.... MI = FAI ANCHE E SUBITO UNA NORMINA DECAPITANTE NOIOSISSIMI CONCETTI COME DEMOCR= AZIA E GIUSTIZIA CHE IMPONGA IL MIO TORNARE IN POLITICA, COSI' CHE POSSA FO= TTERE IL POPOLO CIUCCIO, LE LEGGI, DOZZINE DI (GRANDISSIMI) MAGISTRATI COME= ILDA BOCASSINI, EDMONDO BRUTI LIBERATI, NINO DI MATTEO, ROBERTO SCARPINATO= , FABIO DE PASQUALE, HENRY WOODCOCK, PASQUALE DRAGO, ATTRAVERSO LA ( BASTAR= DAMENTE VIGLIACCHISSIMA) IMMUNITA' EVITA GALERA, CHE MI RI RITROVEREI"! http://www.ilfattoquotidiano.it/2015/01/18/salva-berlusconi-alessandro-pace= -manina-renzi-reato-falso/1349562/ http://www.ilfattoquotidiano.it/2015/01/08/salva-berlusconi-mucchetti-renzi= -venga-senato-spiegare-successo/1322595/ http://www.ilfattoquotidiano.it/2015/01/06/salva-berlusconi-coppi-ammette-q= uella-norma-segnale-per-quirinale/1318110/ ECCO DOVE CI PORTANO BASTARDI LAVA CASH MAFIOSO A GO GO COME I MALAVITOSIN= CRAVATTATI DAVIDE SERRA DI ALGEBRIS E TWITTER INSIEME AL RENATO VALLANZASCA= UNITO AD UGO FANTOZZI DELLA FINANZA, NOTO AVANZO DI GALERA PAOLO BARRAI NA= TO A MILANO IL 28.6.1965, DI CRIMINALISSIMO WMO, CRIMINALISSIMA BSI ITALIA = SRL DI VIA SOCRATE 26 MILANO E CRIMINALISSIMO BLOG MERCATO "MERDATO" LIBERO= ( DUE VERMI REPELLENTI CHE RICICLANO ALL'ESTERO VAGONI DI SOLDI DI COSA NO= STRA, CAMORRA, NDRANGHETA O LADRATI SE NON PURE FRUTTO DI MEGA MAZZETTE IN = DIREZIONE LL LEGA LADRONA ED EX PDL POPOLO DI LADRONI; IN CONGIUNZIONE CON = BANCHIERI DELINQUENTISSIMI, SPESSO PURE MANDANTI DI OMICIDI O "SUICIDATE", = COME FATTO CON DAVID ROSSI DI MONTE PASCHI, QUALI GLI ASSASSINI ENNIO DORIS= E MASSIMO DORIS DI BANCA MEDIOLANUM; O QUALE "O MASSONE CAMORRISTA" GIUSEP= PE SABATO DI BANCA ESPERIA http://www.gruppoesperia.it/chi-siamo/giuseppe-sabato.html https://books.google.it/books?id=3DB1mEj0GtktIC&pg=3DPT304&lpg=3DPT304&dq= =3DGIUSEPPE+SABATO+LICIO+GELLI&source=3Dbl&ots=3DGqtu0KYRmD&sig=3Dd2TOz9sZD= Y6563zIPxwnNYcbxb4&hl=3Dit&sa=3DX&ei=3DI-i_VOOsBMLlUonCgZgI&ved=3D0CFMQ6AEw= CA#v=3Donepage&q=3DGIUSEPPE%20SABATO%20LICIO%20GELLI&f=3Dfalse TUTTI DEL GRUPPO MA-F-INIVEST DI " STEFANO BONTATE, MARCELLO DELL'UTRI, TO= TO RIINA, LICIO GELLI, BERNARDO PROVENZANO E SILVIO BERLUSCONI: " OO CHE CA= SO, OO")! E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STECCAT= ISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE MIC= HELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER PRO= TEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROTTIE= RE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA SOD= OMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOLO C= IUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE MATTEO RENZI! http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_ren= zie.html https://www.youtube.com/watch?v=3DA7Ngp6JrK9A http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-paga= ti-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375 VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE, Q= UELLO ANTI MAFIA FASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E SEL= ! A FARE IL SUO VERO LAVORO, OSSIA LA ZOCCOLA DI STRADA, STA BATTONA HITLER= IANA, CHE SI CREDE MODELLA MA E' CESSO STRA COLMO DI CELLULITE, DI MARIA EL= ENA BOSCHI http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-biki= ni-rosa-in-spiaggia-a-marina-di-pietrasanta-581617_tn.jpg FIGLIA DI ALTRO = VERME CRIMINALISSIMO: MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA ET= RURIA (DOPO AVER PASSATO TUTTA UNA VITA A TRAFFICARE CON COOP VICINISSIME A= MAFIA, CAMORRA E NDRANGHETA, NON PER NIENTE, STILE "RENZUSCONIANISSIMI" SA= LVATORE BUZZI E MASSIMO CARMINATI)! AL QUIRINALE UN UOMO O DONNA VERA, ALLA= NINO DI MATTEO O ILDA BOCASSINI, CHE FACCIA TRASLOCARE IL CANCROMICIDA DEL= MONDO INTERO, SILVIO BERLUSCONI, DA PALAZZO GRAZIOLI A PALAZZO UCCIARDONE = E SUBITO. O VERA RIVOLUZIONE SARA'! RIVOLUZIONE RIPRISTINANTE VERA DEMOCRAC= IA Y LIBERTAD! PS SEMPRE VINCENTISSIMI I GENI BORSISTICI GEORGE SOROS E MIC= HELE NISTA A PUNTARE SULLA SPAGNA. PARREBBE CHE DOPO AVER SAPUTO CHE IL MIG= LIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NISTA, VEDA NON MALE LA SP= AGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO, MANCO FOSSERO NOCCIOLIN= E, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI BANCO SANTANDER. NON SA= RA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON LO E' ALCUN PAESE DEL P= IANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE NON MANCANO ( MA SONO A= L MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA DI RENZUSCONIA)! PERO',= NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI VI E' DEMOCRAZIA VERA. SI= A AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMETTENTISSIMO PABLO IGLESIA= S DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRONA DI MADRID, VERMI STRA= GISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERLUSCONI, CHE SI FAN LE LE= GGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLTRE CHE PER SGOZZARE A MO= RTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. E QUESTO, O IN PROPRIO, O COMPRAND= OSI RAGAZZINI CORROTTISSIMI CHIAMANTISI MATTEO, COME MATTEO RENZI (OGGI). O= IL NUOVO ADOLF HITLER: MATTEO SALVINI (DOMANI). MENTRE L'UNICO PADRONE, L'= UNICO VERO BOSS DEL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, UN AL= TRO MATTEO, MATTEO MESSINA DENARO, SORRIDE E DICE " BRAVO MIO PRESTANOME BE= DDU SILVIO BERLUSCONI, HAI TRASFORMATO L'ITALIA IN RENZUSCONIA, CHE IN REAL= TA' SEMPRE BERLUSCONIA E', AAAAAAA... COME PIACE A MMMIA, AAAA.... E' TUTTO= UNA COSA NOSTRA, SILVIUZZEDDU BEDDU ..... CONTINUA COSI' CHE TI TROVIAMO Q= UALCHE ALTRA BEDDA PROSTITUTA DI 12-14 ANNI PELLU TEMPU LIBERO, AAAAA.... Q= UESTA VOLTA CAMBIAMO, AAAA... TE LA TROVIAMO FILIPPINA E LA FACCIAMO PASSAR= E PER LA NIPOTE DEL RE DELLA THAILANDIA, BHUMIBOL ADULYADEJ, IL RE PIU' RIC= CO DEL MONDO... CHE SPESSO E VOLENTIERI "ABOLISCE UFFICIALISSIMAMENTE LA DE= MOCRAZIA"... SI... SILVIUZZEDDU BEDDU DA COSA NOSTRA, TI TROVIAMO UNA BAMBI= NA FILIPPINA DI 12 ANNI DA SBAVARE E TOCCARE QUANTO VUOI... E LA FACCIAMO P= ASSARE PER LA NIPOTE THAILANDESE DI BHUMIBOL ADULYADEJ, AAAA.... COSI' VEDR= AI CHE QUANDO TELEFONI, PREOCCUPATISSIMO, DA PARIGI ( TANTO, FRA POCO, NELL= A TUA DITTATURA DELLE BANANAS DI RENZUSCONIA, SUBITO, IL PASSAPORTO, TI RID= ARANNO), I POLIZIOTTI O QUESTORI, SOLO E SEMPRE LA TUA VOLONTA', FARANNO, A= AA"!!! From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.50.85.18 with SMTP id d18mr15363665igz.3.1422981698258; Tue, 03 Feb 2015 08:41:38 -0800 (PST) X-Received: by 10.50.40.9 with SMTP id t9mr262027igk.7.1422981698180; Tue, 03 Feb 2015 08:41:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no8938880igb.0!news-out.google.com!qk8ni19963igc.0!nntp.google.com!hl2no8938877igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 08:41:37 -0800 (PST) In-Reply-To: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=216.65.182.66; posting-account=JlXAlwoAAACzvkJ2IoEBs0mddSuKa3cg NNTP-Posting-Host: 216.65.182.66 References: <530204a0$0$29889$c3e8da3$5496439d@news.astraweb.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: LeRoss Calnek Injection-Date: Tue, 03 Feb 2015 16:41:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3478 X-Received-Body-CRC: 493813554 Xref: mx02.eternal-september.org comp.lang.vhdl:8075 very helpful thanks On Monday, 17 February 2014 06:46:24 UTC-6, Allan Herriman wrote: > On Mon, 17 Feb 2014 01:03:27 -0800, thunder wrote: > > > Hello > > > > > > My design consists of VHDL blocks. Now i need to instantiate a verilog > > block inside my VHDL block. > > > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > > QS: If the answer to the above question is yes, how to achieve this? > > > > Thanks in advance > > My experience is that it is possible to instantiate a verilog module > inside a VHDL architecture, both using component instantiation and entity > instantiation, in most tools, for both synthesis and simulation. > > Significantly, Altera Quartus does not allow entity instantiation, which > means if you want Altera compatibility you will need to write a component > declaration for each Verilog module. > > Things that don't work the way you'd want: > - heirarchical references typically can't go across a VHDL/Verilog > boundary. > > Things to avoid for portability: > - (for ports) types other than std_logic, std_logic_vector > - (for generics/parameters) types other than integer and string > - in some tools (e.g. older Modelsim), port mappings can only be to > signals. It is not possible to map a port to a constant, for example. > > > Example: > > module foo > #( > parameter bar = 1 > ) > ( > input wire bletch, > output reg baz = 1'b0 > ); > > You could instantiate this as an entity, provided that it has already > been compiled into the work library: > > some_label : entity work.foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Or if you really like typing you could instantiate module foo as a > component: > > component foo is > generic ( > bar : integer := 1 > ); > port ( > bletch : in std_logic; > baz : out std_logic > ); > end component foo; > > ... > > some_label : component foo > generic map ( > bar => 2 > ) > port map ( > bletch => signal1, > baz => signal2 > ); > > Note that the keyword "component" is optional in a component > instantiation. Most people leave it out. > > Regards, > Allan From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.70.32.129 with SMTP id j1mr21081112pdi.8.1423000284905; Tue, 03 Feb 2015 13:51:24 -0800 (PST) X-Received: by 10.140.40.242 with SMTP id x105mr320476qgx.14.1423000284803; Tue, 03 Feb 2015 13:51:24 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!hl2no6937465igb.0!news-out.google.com!q4ni26qan.0!nntp.google.com!bm13no5903476qab.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Feb 2015 13:51:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.241.194.161; posting-account=RzNB3QoAAACErfT8OnroBxxwx7Ka-eQH NNTP-Posting-Host: 50.241.194.161 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Subject: Digital Design / Hardware Simulation From: jknight@metamorphsoftware.com Injection-Date: Tue, 03 Feb 2015 21:51:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8076 Hello, I am looking for a digital design engineer to come work for us, MetaMorph, on Google's Project Ara. Our tools use SystemC for digital simulation and we're looking for someone to help guide this area. I'm sorry if this is spamming, but I'm offering a legit well paying and permanent job. I'm open to all types of arrangements for the right person. Have a look or drop me a line. metamorphsoftware.com/careers/ projectara.com Thank you, Justin Knight CEO, MetaMorph jknight@metamorphsoftware.com From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Tue, 03 Feb 2015 16:54:16 -0500 Organization: A noiseless patient Spider Lines: 129 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 3 Feb 2015 21:53:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21303"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX185ucjLpvnuVZDta9gyGPyU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 In-Reply-To: Cancel-Lock: sha1:Ny5HNCgq4rZQ1uHI61GZkKrvy9s= Xref: mx02.eternal-september.org comp.lang.vhdl:8077 On 1/30/2015 2:02 PM, GaborSzakacs wrote: > Rob Gaddi wrote: >> On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >>> Hi Gabor, >>> >>> I think I follow you. So what I think I should do is create another >>> clocked process that deals with the counting (and the special output >>> based on the counting). When I enter the correct state in the FSM, I >>> set an enable for this clocked process. Without the enable the process >>> does essentially nothing. Then when I'm done I set a "finished" flag, >>> and that in turn triggers the FSM to exit the current state and >>> de-asserts the enable flag. >>> >>> Many thanks, >>> Karol. >> >> More processes = more problems. >> >> I've frequently done things like below (untested, so beware the syntax). >> Note two important things. >> >> 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to >> use two process state machines, even for simple Moore ones. They're >> wrong, it just adds confusion to your world. >> >> 2) The states have real people names, not S0, S1, S2. >> >> signal go : boolean; >> signal count : integer range 0 to 15; >> signal lamp : boolean; >> type t_state is (IDLE, LAMPOFF, LAMPON); >> signal state : t_state; >> >> ... >> >> FSM: process(clk) >> begin >> if rising_edge(clk) then >> lamp <= false; >> case state is >> when IDLE => >> count <= 0; >> if go then >> state <= LAMPOFF; >> end if; >> when LAMPOFF => >> if count = 15 then >> count <= 0; >> state <= LAMPON; >> else >> count <= count + 1; >> end if; >> when LAMPON => >> lamp <= true; >> if count = 15 then >> count <= 0; >> state <= IDLE; >> else >> count <= count + 1; >> end if; >> end case; >> end if; >> end process FSM; >> > > That is in fact what I was suggesting. There is no need to count > in a separate process, since your FSM was already a clocked process. > > Similarly, here's the "subroutine" approach: > > signal go : boolean; > signal count : integer range 0 to 15; > signal lamp : boolean; > type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); > signal state : t_state; > signal rtn_state : t_state; > > .... > > FSM: process(clk) > begin > if rising_edge(clk) then > > case state is > when IDLE => > count <= 0; > if go then > state <= LAMPOFF; > end if; > > when LAMPOFF => > lamp <= false; > count <= 15; > rtn_state <= LAMPON; > state <= SPIN; > > when LAMPON => > lamp <= true; > count <= 15; > rtn_state <= IDLE; > state <= SPIN; > > when SPIN => > if count = 0 then > state <= rtn_state; > else > count <= count - 1; > end if; > > end case; > end if; > end process FSM; Just my two cents worth... Rather than assign 0 to count in the idle state I would simply ignore count which will leave it unchanged at its present value. In other words the counter would have an enable rather than a reset. Not sure if it is more complex in the logic or not, but if the FSM is otherwise not enabled, there should be a "free" enable input to each of the FFs which likely would be used for this. Also, and I realize this is not finished code, but an initialization should be considered for all of this logic including the counter. Since the counter is only used in the SPIN state and set before entering the SPIN state, the counter likely doesn't need initialization although it can make simulations more readable. -- Rick From newsfish@newsfish Tue Dec 29 16:43:43 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: FSM recurring state technique Date: Tue, 03 Feb 2015 18:03:30 -0500 Organization: Alacron, Inc. Lines: 139 Message-ID: References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 3 Feb 2015 23:04:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="9892"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+SlKmZCJhIsO9M+2ch0CCZcyc7LESGGQQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ARD0XF98VQJ6zNpqbNpYs0aNE2E= Xref: mx02.eternal-september.org comp.lang.vhdl:8078 rickman wrote: > On 1/30/2015 2:02 PM, GaborSzakacs wrote: >> Rob Gaddi wrote: >>> On Fri, 30 Jan 2015 09:22:18 -0800, revkarol wrote: >>>> Hi Gabor, >>>> >>>> I think I follow you. So what I think I should do is create another >>>> clocked process that deals with the counting (and the special output >>>> based on the counting). When I enter the correct state in the FSM, I >>>> set an enable for this clocked process. Without the enable the process >>>> does essentially nothing. Then when I'm done I set a "finished" flag, >>>> and that in turn triggers the FSM to exit the current state and >>>> de-asserts the enable flag. >>>> >>>> Many thanks, >>>> Karol. >>> >>> More processes = more problems. >>> >>> I've frequently done things like below (untested, so beware the syntax). >>> Note two important things. >>> >>> 1) The entire FSM is one process. The FPGA vendors LOVE to tell you to >>> use two process state machines, even for simple Moore ones. They're >>> wrong, it just adds confusion to your world. >>> >>> 2) The states have real people names, not S0, S1, S2. >>> >>> signal go : boolean; >>> signal count : integer range 0 to 15; >>> signal lamp : boolean; >>> type t_state is (IDLE, LAMPOFF, LAMPON); >>> signal state : t_state; >>> >>> ... >>> >>> FSM: process(clk) >>> begin >>> if rising_edge(clk) then >>> lamp <= false; >>> case state is >>> when IDLE => >>> count <= 0; >>> if go then >>> state <= LAMPOFF; >>> end if; >>> when LAMPOFF => >>> if count = 15 then >>> count <= 0; >>> state <= LAMPON; >>> else >>> count <= count + 1; >>> end if; >>> when LAMPON => >>> lamp <= true; >>> if count = 15 then >>> count <= 0; >>> state <= IDLE; >>> else >>> count <= count + 1; >>> end if; >>> end case; >>> end if; >>> end process FSM; >>> >> >> That is in fact what I was suggesting. There is no need to count >> in a separate process, since your FSM was already a clocked process. >> >> Similarly, here's the "subroutine" approach: >> >> signal go : boolean; >> signal count : integer range 0 to 15; >> signal lamp : boolean; >> type t_state is (IDLE, LAMPOFF, LAMPON, SPIN); >> signal state : t_state; >> signal rtn_state : t_state; >> >> .... >> >> FSM: process(clk) >> begin >> if rising_edge(clk) then >> >> case state is >> when IDLE => >> count <= 0; >> if go then >> state <= LAMPOFF; >> end if; >> >> when LAMPOFF => >> lamp <= false; >> count <= 15; >> rtn_state <= LAMPON; >> state <= SPIN; >> >> when LAMPON => >> lamp <= true; >> count <= 15; >> rtn_state <= IDLE; >> state <= SPIN; >> >> when SPIN => >> if count = 0 then >> state <= rtn_state; >> else >> count <= count - 1; >> end if; >> >> end case; >> end if; >> end process FSM; > > Just my two cents worth... Rather than assign 0 to count in the idle > state I would simply ignore count which will leave it unchanged at its > present value. In other words the counter would have an enable rather > than a reset. Not sure if it is more complex in the logic or not, but > if the FSM is otherwise not enabled, there should be a "free" enable > input to each of the FFs which likely would be used for this. > > Also, and I realize this is not finished code, but an initialization > should be considered for all of this logic including the counter. Since > the counter is only used in the SPIN state and set before entering the > SPIN state, the counter likely doesn't need initialization although it > can make simulations more readable. > You're right. I think the count <= 0 came from the old code and I just left it there. If anything it would best be initialized to 15 since no other value is ever loaded in parallel. However the point of the "subroutine" method is that you could load different values into the counter depending on the time required by each state. Even if the count was allowed to start up "U" there would be no issue with simulation since it is always loaded before it is used. The "state" variable would need an initial value for simulation, though. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.66.155.3 with SMTP id vs3mr27154776pab.20.1423051986613; Wed, 04 Feb 2015 04:13:06 -0800 (PST) X-Received: by 10.140.94.172 with SMTP id g41mr364453qge.34.1423051986565; Wed, 04 Feb 2015 04:13:06 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!hl2no9488854igb.0!news-out.google.com!q4ni11068qan.0!nntp.google.com!v8no6545054qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 04:13:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.64.248.202; posting-account=WhTRKAoAAAAYALbNZHGsh5N_3Jfy6d8U NNTP-Posting-Host: 217.64.248.202 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3ca4c308-54e9-4314-95fc-db8f888dc46a@googlegroups.com> Subject: SCHIFOSA BERLUS-CORROTTA PUTTANA MARIA ELENA BOSCHI, NON PAGA DI SUE RIFORME BASTARDAMENTE NAZISTE, NON PAGA DEGLI INSIDER TRADING CHE PASSA AL CRIMINALE VERME DAVIDE SERRA DI ALGEBRIS, ORA VUOLE SGOZZARE LA GIUSTIZIA VIA SALVABERLUSCONI. REVOLUCION! From: "CHE SIA REVOLUCIOOON!!!" Injection-Date: Wed, 04 Feb 2015 12:13:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8079 SCHIFOSA BERLUS-CORROTTA PUTTANA MARIA ELENA BOSCHI, NON PAGA DI SUE RIFORM= E BASTARDAMENTE NAZISTE, NON PAGA DEGLI INSIDER TRADING CHE PASSA AL CRIMIN= ALE VERME DAVIDE SERRA DI ALGEBRIS, ORA VUOLE SGOZZARE LA GIUSTIZIA VIA SAL= VABERLUSCONI. REVOLUCION!=20 =20 STO LURIDO NAZINDRANGHETISTA DI DAVIDE SERRA DI ALGEBRIS E TWITTER HA RICEV= UTO L'INSIDER TRADING SULLE BANCHE POPOLARI DA NOTO LAVA SOLDI MAFIOSI PIER= LUIGI BOSCHI DI AREZZO E BANCA ETRURIA. HA PURE RAGLIATO CHE COMPRA BANCHE= POPOLARI DAL MARZO 2014. SPUTTANANDOSI ANCORA DI PIU', COME UN IMBECILLE, = PEDERASTA SODOMIZZA BAMBINI E MEGA COCAINOMANE, QUALE DA SEMPRE E'. IL SUO = POR-CO-RROTTISSIMO MATTEO RENZI (CHE VIA "SS", SPINTA E STECCHE DI SILVIO B= ERLUSCONI, HA SCIPPATO SEGRETERIA PD E PALAZZO CHIGI, NEL SECONDO CASO COL = FEBBRAIO 2014), GLI HA PASSATO, ATTRAVERSO "A ZOCCOLONA BERLUSCONICCHIA, ST= ECCATISSIMA E CELLULITOSA" MARIA ELENA BOSCHI http://www.dagospia.com/img/= foto/08-2014/maria-elena-boschi-bikini-rosa-in-spiaggia-a-marina-di-pietras= anta-581617_tn.jpg E IL VERME MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI= BANCA ETRURIA, L'INSIDER SULLE BANCHE POPOLARI. E PER QUESTO, STO ESCREMEN= TO HITLERIANO DI DAVIDE SERRA DI TWITTER E ALGEBRIS, SI E' MESSO A COMPRARE= BANCHE POPOLARI DAL MARZO 2014. UN MESE DOPO (ULLALA CHE COINCIDENZA, ULLA= LA). SEMPRE INSIDER E'. TRATTASI DI MANDRIA DI PORCI FASCIOCAMORRISTI, TIP= O, ANCHE, NOTO AVANZO DI GALERA PAOLO BARRAI (DI CRIMINALISSIME WMO, BSI IT= ALIA SRL DI VIA SOCRATE 26 MILANO E BLOG "MERDATO"LIBERO), CHE SI FINGONO D= EL PD, X... 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TIPO QUELLI DI PALERMO, BARI= , MILANO, NAPOLI, DICENDO, ANZI, RAGLIANDO LORO: "'OOOO OO CHE PAURA, MI FA= NNO, OO OO" http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-pau= ra-sciopero-sindacati-polizia-illegale/295911/ CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE FRA= POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO REN= ZI! https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-di-= me-il-2-febbraio-carmelo-lopapa/ "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERLUSC= ONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA BL= OCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGLI U= LTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNER, = FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVREBB= ERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU METTI AL QUIRI= NALE UN FANTOCCIO DI MIA PROPRIETA' CHE COMPRO QUANDO VOGLIO QUALE GIULIANO= AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... 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E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STECCAT= ISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE MIC= HELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER PRO= TEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROTTIE= RE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA SOD= OMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOLO C= IUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE MATTEO RENZI! http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_ren= zie.html https://www.youtube.com/watch?v=3DA7Ngp6JrK9A http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-paga= ti-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375 VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE, Q= UELLO ANTI MAFIA FASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E SEL= ! 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PARREBBE CHE DOPO AVER SAPUTO CHE IL MI= GLIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NISTA, VEDA NON MALE LA S= PAGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO, MANCO FOSSERO NOCCIOLI= NE, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI BANCO SANTANDER. NON S= ARA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON LO E' ALCUN PAESE DEL = PIANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE NON MANCANO ( MA SONO = AL MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA DI RENZUSCONIA)! PERO'= , NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI VI E' DEMOCRAZIA VERA. S= IA AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMETTENTISSIMO PABLO IGLESI= AS DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRONA DI MADRID, VERMI STR= AGISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERLUSCONI, CHE SI FAN LE L= EGGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLTRE CHE PER SGOZZARE A M= ORTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. E QUESTO, O IN PROPRIO, O COMPRAN= DOSI RAGAZZINI CORROTTISSIMI CHIAMANTISI MATTEO, COME MATTEO RENZI (OGGI). = O IL NUOVO ADOLF HITLER: MATTEO SALVINI (DOMANI). MENTRE L'UNICO PADRONE, L= 'UNICO VERO BOSS DEL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, UN A= LTRO MATTEO, MATTEO MESSINA DENARO, SORRIDE E DICE " BRAVO MIO PRESTANOME B= EDDU SILVIO BERLUSCONI, HAI TRASFORMATO L'ITALIA IN RENZUSCONIA, CHE IN REA= LTA' SEMPRE BERLUSCONIA E', AAAAAAA... COME PIACE A MMMIA, AAAA.... E' TUTT= O UNA COSA NOSTRA, SILVIUZZEDDU BEDDU .. CONTINUA COSI' CHE TI TROVIAMO QUA= LCHE ALTRA BEDDA PROSTITUTA DI 12-14 ANNI PELLU TEMPU LIBERO, AAAAA.... QUE= STA VOLTA CAMBIAMO, AAAA... TE LA TROVIAMO FILIPPINA E LA FACCIAMO PASSARE = PER LA NIPOTE DEL RE DELLA THAILANDIA, BHUMIBOL ADULYADEJ, IL RE PIU' RICCO= DEL MONDO... CHE SPESSO E VOLENTIERI "ABOLISCE UFFICIALISSIMAMENTE LA DEMO= CRAZIA"... SI... SILVIUZZEDDU BEDDU DA COSA NOSTRA, TI TROVIAMO UNA BAMBINA= FILIPPINA DI 12 ANNI DA SBAVARE E TOCCARE QUANTO VUOI... E LA FACCIAMO PAS= SARE PER LA NIPOTE THAILANDESE DI BHUMIBOL ADULYADEJ, AAAA.... COSI' VEDRAI= CHE QUANDO TELEFONI, PREOCCUPATISSIMO, DA PARIGI ( TANTO, FRA POCO, NELLA = TUA DITTATURA DELLE BANANAS DI RENZUSCONIA, SUBITO, IL PASSAPORTO, TI RIDAR= ANNO), I POLIZIOTTI O QUESTORI, SOLO E SEMPRE LA TUA VOLONTA', FARANNO, AAA= "!!! From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.182.143.34 with SMTP id sb2mr1552408obb.27.1423104347417; Wed, 04 Feb 2015 18:45:47 -0800 (PST) X-Received: by 10.182.106.233 with SMTP id gx9mr12989obb.0.1423104347330; Wed, 04 Feb 2015 18:45:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no9844513igb.0!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7347955igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 18:45:45 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: <983c6d4e-d086-4a28-b1ee-472a813b1679@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f703a14-f0c1-4fdb-9141-32b27c8fe79c@googlegroups.com> Subject: Re: FSM recurring state technique From: Andy Injection-Date: Thu, 05 Feb 2015 02:45:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1957 X-Received-Body-CRC: 3015286656 Xref: mx02.eternal-september.org comp.lang.vhdl:8080 Beware that saving/restoring the state to/from a separate register may prev= ent the synthesis tool from recognizing and optimizing/augmenting the FSM (= many require reading and writing state only from/to one register.) Be sure = to check it out before you use this method if that is important to your app= lication. An alternative method would be to use separate register(s) with flag(s) or = a separate enumerated type to determine where to go from the subroutine. An= if/then/else tree or case statement in the subroutine state could be used = to assign the state register based on the flags/enum, without preventing FS= M synthesis optimization/augmentation. Andy From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.236.26.108 with SMTP id b72mr1484502yha.33.1423104954860; Wed, 04 Feb 2015 18:55:54 -0800 (PST) X-Received: by 10.182.252.232 with SMTP id zv8mr12326obc.37.1423104954746; Wed, 04 Feb 2015 18:55:54 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v8no6677928qal.1!news-out.google.com!qk8ni25600igc.0!nntp.google.com!hl2no9846036igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 18:55:54 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Proposed additions to std.env From: Andy Injection-Date: Thu, 05 Feb 2015 02:55:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8081 I've used a deferred constant for detection of simulation. Just compile a different package body for simulation, after compiling the RTL. constant simulation: Boolean; -- package constant simulation: Boolean := false; -- rtl package body constant simulation: Boolean := true; -- simulation package body Andy On Friday, January 30, 2015 at 1:27:26 PM UTC-6, Rob Gaddi wrote: > A couple things that might be really nice to have, probably in std.env > > *** > > function simulation return bool; > > This would allow the use of if/else/endif blocks to get around one of my > least favorite VHDL anti-patterns, the use of > --synthesis translate_on/off > > Pragmas are awful. They're error-prone kludges that can lead to > accidentally and silently knocking huge chunks of your code out, because > a misformed pragma is just a comment. Additionally, while most vendors > support knocking code out for synthesis, support for putting some back in > for synthesis such as Altera's comment_as_hdl is limited. > > Another way around this would be to pass SIMULATION down as a generic, > but this a) doesn't work for functions in packages and b) requires that > you manually pass the generic all the way down the hierarchy. > > You could also put it into a package, but then you're responsible for > manually changing it back and forth in the code. > > Now, an argument could be made that this is all awful because you > shouldn't be doing it anyhow; that synthesizing code that is different > than what you simulate is inherently dangerous. I wouldn't disagree. > But at the end of the day, sometimes it's the only way to get it to > actually work; the vendor synthesis tools are pretty dumb and get > confused by things like assigning 'X' values so that you can trace > invalid states through your simulation. Or debugging log file writes. > And if there has to be a knock-out mechanism, it should at least be > linguistically sound. > > *** > > function file_path return string; > > Provides the path to the current VHDL file. Not sure if there's a better > implementation option than that, but some way of enforcing relative paths > for files that is better than "Hope the tool has the same understanding > of the root directory than I do." would be great. > > Again, there are workarounds with generics or packages, but again they're > a pain for all the same reasons; who wants to have to hard code absolute > paths into a VHDL package that you may need to move to another machine? > > > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.66.66.108 with SMTP id e12mr2008813pat.30.1423115994237; Wed, 04 Feb 2015 21:59:54 -0800 (PST) X-Received: by 10.50.66.141 with SMTP id f13mr439530igt.17.1423115994046; Wed, 04 Feb 2015 21:59:54 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no9886851igb.0!news-out.google.com!qk8ni25600igc.0!nntp.google.com!hl2no9886849igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Feb 2015 21:59:53 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.176.99.126; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 98.176.99.126 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> Subject: Split package - package body with deferred type definitions? From: David Rogoff Injection-Date: Thu, 05 Feb 2015 05:59:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8082 Hi all. Getting back into some VHDL verification after many years of SystemVerilog.= Question about packages and deferred definitions. Test environment has main test split into separate entity and architecture = files so that 1) entity can be compiled once with RTL and only architecture= file needs to be recompiled when changes, and 2) multiple architecture fil= es can be configured to the single entity. This works great. I'm now trying to extend this concept with a package to = be used by this test file. Again, I'm setting up the package and package b= ody in separate files so the test entity can "use" the package file and mul= tiple package body files (each corresponding to the test architecture files= ) would have the local definitions of things. This is fine for constants and procedures since I can put the prototype in = the package file and then the deferred constant assignment and procedure bo= dies in the package body files. So far, so good. However, it all dies for the type definitions. Each package body needs to = define its own version of the types. It doesn't look like there's such a t= hing as deferred type declarations. Am I missing something? Another way to implement this concept? I can brut= e-force a Verilog/C-like `define by using the compile script to concatenate= the package body file (minus the package body/end package body lines) and = the architecture file into one (inserting the "package" after the "architec= ture xx of yy is" line) and compiling that. Ugly, but it should work. Help! Thanks, David From newsfish@newsfish Tue Dec 29 16:43:43 2015 X-Received: by 10.66.123.16 with SMTP id lw16mr3913433pab.37.1423154020430; Thu, 05 Feb 2015 08:33:40 -0800 (PST) X-Received: by 10.182.236.74 with SMTP id us10mr37299obc.32.1423154020276; Thu, 05 Feb 2015 08:33:40 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no10157436igb.0!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7535272igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Feb 2015 08:33:40 -0800 (PST) In-Reply-To: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.69.57; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.69.57 References: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> Subject: Re: Split package - package body with deferred type definitions? From: Jim Lewis Injection-Date: Thu, 05 Feb 2015 16:33:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2261 X-Received-Body-CRC: 3164425204 Xref: mx02.eternal-september.org comp.lang.vhdl:8083 Hi David, Have you considered using generics on packages? This is a VHDL-2008 feature. With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages. The following shows a simple sketch of a package with type and subprogram generics: package ScoreBoardPkg is generic ( type BaseType ; function check(A, E : BaseType) return boolean ) ; -- remaining part of package goes here end ScoreBoardPkg ; To use the generic package you must create a package instance. This is done as follows: library IEEE ; use ieee.std_logic_1164.all ; package ScoreBoardPkg_slv8 is new work.ScoreBoardPkg generic map ( BaseType => std_logic_vector(7 downto 0), check => std_match ) ; If you are looking for features such as randomization and functional coverage, be sure to check out the Open Source VHDL Verification Methodology page at http://www.osvvm.org If you are looking for training on OSVVM and Advanced VHDL Verification techniques, see http://synthworks.com/vhdl_testbench_verification.htm Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.15.69 with SMTP id e45mr4575220yhe.5.1423156874701; Thu, 05 Feb 2015 09:21:14 -0800 (PST) X-Received: by 10.182.73.170 with SMTP id m10mr40273obv.27.1423156874545; Thu, 05 Feb 2015 09:21:14 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v8no6802861qal.1!news-out.google.com!qk8ni25140igc.0!nntp.google.com!hl2no7548265igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Feb 2015 09:21:14 -0800 (PST) In-Reply-To: <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 References: <4cde06d0-a565-4a11-bfb4-8643a9490bae@googlegroups.com> <47f2ce6e-b363-41f1-8d6a-e56585c4b9c5@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ddc6974-7554-4389-9a39-95124d471c10@googlegroups.com> Subject: Re: Split package - package body with deferred type definitions? From: David Rogoff Injection-Date: Thu, 05 Feb 2015 17:21:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1792 X-Received-Body-CRC: 3924499039 Xref: mx02.eternal-september.org comp.lang.vhdl:8084 On Thursday, February 5, 2015 at 8:33:43 AM UTC-8, Jim Lewis wrote: > Hi David, > Have you considered using generics on packages? This is a VHDL-2008 feature. > > With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages. > > Best Regards, > Jim Thanks Jim. I briefly thought about generics but didn't look into the details. I'll have to take some time with that. I think it could work but might be really messy given the number and size of some type enums I need to deal with. David From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.233.198 with SMTP id ty6mr11267549pac.24.1423396905407; Sun, 08 Feb 2015 04:01:45 -0800 (PST) X-Received: by 10.140.28.131 with SMTP id 3mr55758qgz.16.1423396905133; Sun, 08 Feb 2015 04:01:45 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no11886775igb.0!news-out.google.com!q4ni11076qan.0!nntp.google.com!v8no7398292qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Feb 2015 04:01:45 -0800 (PST) In-Reply-To: <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.55.215.39; posting-account=sQsPdgoAAACgOMKaiBi8koqnE3-a4hm- NNTP-Posting-Host: 78.55.215.39 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> <8aa2903c-12b4-4784-8a69-8eb7349ef645@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help with VHDL architecture From: saadriazqazi@gmail.com Injection-Date: Sun, 08 Feb 2015 12:01:45 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2422 X-Received-Body-CRC: 688637370 Xref: mx02.eternal-september.org comp.lang.vhdl:8085 On Saturday, 3 January 2015 11:38:20 UTC+1, Olalekan Shittu wrote: > On Friday, 2 January 2015 10:19:42 UTC+1, Andy Bennett wrote: > > "Andy Bennett" wrote in message > > news:O_2dnY2_V4Fi_DvJnZ2dnUVZ8nWdnZ2d@brightview.co.uk... > > > > Forgot to add sel ... so > > > > > > > > > > > > > > > > Something like:- > > > > Defaults:- > > > > Out[3..0] = 0 > > > > End defaults > > > > > > If sel = 4 then > > If C >= 0 or C < 4 then > > out0 = 1 > > end if > > > > If C >= 4 or C < 8 then > > out1 = 1 > > end if > > > > If C >= 8 or C < 12end if > > out2 = 1 > > end if > > > > If C >= 12 or C < 16 then > > out3 = 1 > > end if > > end if > > > > > > The student can add/correct the syntax > > > > > > Andy > > Thanks Andy, trying to work on the syntax for now. > > Is there a way I can combine this system with another system before writing a test bench for it. If you dont mind, I can send you a personal email. What do you want to combine this with? It is a very simple if statement logic and can be combined easily i think. From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.224.22.77 with SMTP id m13mr5294268qab.7.1423404595720; Sun, 08 Feb 2015 06:09:55 -0800 (PST) X-Received: by 10.140.109.181 with SMTP id l50mr30347qgf.3.1423404595703; Sun, 08 Feb 2015 06:09:55 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v8no7422370qal.1!news-out.google.com!q4ni11076qan.0!nntp.google.com!v8no7422368qal.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Feb 2015 06:09:55 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.143.74.212; posting-account=FV5KWwoAAABWbmoeB-F7wz-j4xEKw8x5 NNTP-Posting-Host: 82.143.74.212 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8f890076-5350-48df-9392-6869bae881ca@googlegroups.com> Subject: CRIMINALISSIMO PEZZO DI MERDA DAVIDE SERRA (ALGEBRIS E TWITTER) HA BECCATO L'INSIDER SULLE BANCHE POPOLARI DAL MEGALAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA ETRURIA. SON TUTTI NAZINDRANGHETISTI, TIPO PAOLO BARRAI DI WMO, CHE SI FINGONO DEL PD X.. From: ALFREDO PIACENTINI DECALIA GENEVE Injection-Date: Sun, 08 Feb 2015 14:09:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 14576 X-Received-Body-CRC: 1995175423 Xref: mx02.eternal-september.org comp.lang.vhdl:8086 CRIMINALISSIMO PEZZO DI MERDA DAVIDE SERRA (ALGEBRIS E TWITTER) HA BECCATO = L'INSIDER SULLE BANCHE POPOLARI DAL MEGALAVA SOLDI MAFIOSI PIER LUIGI BOSCH= I DI BANCA ETRURIA. SON TUTTI NAZINDRANGHETISTI, TIPO PAOLO BARRAI DI WMO, = CHE SI FINGONO DEL PD X.. STO CRIMINALISSIMO PEZZO DI MER-A DI DAVIDE SERRA DI ALGEBRIS E TWITTER H= A RICEVUTO L'INSIDER TRADING SULLE BANCHE POPOLARI DA NOTO MEGA LAVA SOLDI = MAFIOSI PIER LUIGI BOSCHI DI AREZZO E BANCA ETRURIA. HA PURE RAGLIATO CHE C= OMPRA BANCHE POPOLARI DAL MARZO 2014. SPUTTANANDOSI ANCORA DI PIU', COME UN= IMBECILLE, COME UN PEDERASTA SODOMIZZA BAMBINI IN TANZANIA, COME UN MEGA = COCAINOMANE, QUALE DA SEMPRE E'. IL SUO POR-CO-RROTTISSIMO MATTEO RENZI (CH= E VIA "SS", SPINTA E STECCHE DI SILVIO BERLUSCONI, HA SCIPPATO SEGRETERIA P= D E PALAZZO CHIGI, NEL SECONDO CASO COL FEBBRAIO 2014), GLI HA PASSATO, ATT= RAVERSO "A ZOCCOLONA BERLUSCONICCHIA, STECCATISSIMA E CELLULITOSA" MARIA EL= ENA BOSCHI http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-bik= ini-rosa-in-spiaggia-a-marina-di-pietrasanta-581617_tn.jpg E IL VERME MEGA= LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA ETRURIA, L'INSIDER SULLE BAN= CHE POPOLARI. E PER QUESTO, STO ESCREMENTO HITLERIANO DI DAVIDE SERRA DI TW= ITTER ED ALGEBRIS, SI E' MESSO A COMPRARE BANCHE POPOLARI DAL MARZO 2014. U= N MESE DOPO LO SCIPPO NAZISTA DI MATTEO RENZI, DI PALAZZO CHIGI (ULLALA' CH= E COINCIDENZA, ULLALA'). SEMPRE INSIDER E'. TRATTASI DI MANDRIA DI PORCI F= ASCIOCAMORRISTI, TIPO, ANCHE, NOTO AVANZO DI GALERA PAOLO BARRAI (DI CRIMIN= ALISSIME WMO, BSI ITALIA SRL DI VIA SOCRATE 26 MILANO E BLOG "MERDATO"LIBER= O), CHE SI FINGONO DEL PD, X... DISTRUGGERLO, INFILTRARLO A MORTE, RENDERLO= DIARREA BERLUSCONICCHIA! VOGLIAMO UNA ACCESISSIMA E VINCENTISSIMA REVOLUCI= OOOOOON! VOGLIAMO IL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, FALL= ITO ED IN GALERA! SUBITO! PLS, DOTTOR SERGIO MATTARELLA, CI DIA UNA MANO. I= N ONORE A SUO FRATELLO UCCISO DALLA MAFIA ( MAFIA CHE QUANDO SI METTE LA FA= SCISTISSIMA CRAVATTA DOLCE E GABBANA, SIGNIFICA SILVIO BERLUSCONI E DAVIDE = SERRA). IN ONORE AD ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO, FATTI SPAPP= OLARE, SICURISSIMAMENTE, DA SILVIO BERLUSCONI, VIA, A SUA VOLTA, BERLUSCONI= ANISSIMA COSA NOSTRA! ED OLTRE A VOLER SILVIO BERLUSCONI FALLITO ED IN GALE= RA, VOGLIAMO VEDERE IL SUO PICCIOTTO INCRAVATTATO, IL FACCENDIERE DI BERLUS= CONAZISTI, PADANAZISTI, E CRIMINALITA' ORGANIZZATE DI MEZZO MONDO, PAOLO BA= RRAI DI MALAVITOSA WMO, PURE, IN GALERA! VOGLIAMO IL NUOVO GIANCARLO LANDE,= IL NUOVO BERNARD MADOFF, IL NUOVO MICHELE SINDONA, VERME CRIMINALISSIMO DA= VIDE SERRA DI TWITTER ED ALGEBRIS, FALLITO, E PER LO MENO, PER QUALCHE MESE= , IN GALERA! CHE SIA ETICISSSIMA E VINCENTISSIMA REVOLUCIOOOOON! COME DA OTTIMO SITO INFORMARE X RESISTERE: http://www.informarexresistere.fr/2015/01/27/qualcuno-sapeva-in-anticipo-ch= e-il-governo-avrebbe-varato-un-provvedimento-sulle-banche-popolari-enormi-s= peculazioni/ =20 COME DA CORRIERE DELLA SERA, DI, OTTIMAMENTE, ANTIRENZUSCONIANO FERRUCCI= O DE BORTOLI, DA NON TOCCARE E A TUTTI I COSTI: http://www.corriere.it/economia/15_gennaio_24/quei-movimenti-un-po-sospetti= -popolari-f59ffb1c-a3a5-11e4-808e-442fa7f91611.shtml =20 Acquisti consistenti prima della riforma che ha abolito il voto capitari= o. La famiglia Boschi ha sicurissimamente passato insider trading a Londra,= tramite noto ladro, truffatore, nazifascista, immensamente ricicla soldi m= afiosi, che affatto va' in Tanzania a fare del bene, in quanto vi va' a ric= iclare cash di (sua) LL Lega Ladrona, come per suoi gusti sessuali di tipo = depravatissimo: avanzo di galera Davide Serra di Algebris e Twitter. Dove p= renderanno, le mazzette, ora, i vermi nazifascisti Pier Luigi Boschi di Ban= ca Etruria e sua zoccolona ( di fatto) Berlusconicchia Maria Elena Boschi (= bastarda puttanazista che vuole sgozzare la giustizia via estremissimament= e ingiusta salvaberlusconi http://www.blitzquotidiano.it/rassegna-stampa/li= bero-renzi-per-fare-la-pace-offre-la-salva-berlusconi-che-fara-mattarella-2= 090491/ .... che qui, non per niente, slingua un topo di fogna corrotto, nd= ranghetista, fascista, estortore di soldi alla Banca Popolare di Lodihttp:/= /www.repubblica.it/2005/l/sezioni/economia/banche21/ipolitici/ipolitici.htm= l .. pezzo di merda criminalissimo Paolo Romani http://www.corriere.it/methode_image/2014/08/08/Politica/Foto%20Politica%20= -%20Trattate/6ebdfe07bdd8cb1fe88af8343f8a5b1c-012-kXsC-U43030145012273wcB-5= 93x443@Corriere-Web-Sezioni.jpg?v=3D20140808175213 )? A) Alle Bahamas B) Alle Bermuda C) A Panama D) Ad Hong Kong E) A Singapore F) Alle Mauritius ( "roba" tipo Svizzera e' da anni 70, 80: stile nazim= afioso pedofilo Silvio Berlusconi e suo B-o-ttino Craxi.. dai.. please) Lauti premi a chi azzecca per primo. --- BRAVO, BRAVO, DAVVERO BRAVISSIMO ELIO LANNUTTI A QUERELARE STO VERME BERL= US-CORROTTTISSIMO DI MATTEO RENZI: http://www.ilfattoquotidiano.it/2015/01/21/denuncia-per-renzi/1357263/ CHE SBEFFEGGIA PM PER BENE, EROICI, SALVA NAZIONE ( SPESSO FATTI ESPLOD= ERE, COME IL NAZIMAFIOSO PEDOFILO STRAGISTA SILVIO BERLUSCONI FECE FARE CON= GLI ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO). TIPO QUELLI DI PALERMO, B= ARI, MILANO, NAPOLI, DICENDO, ANZI, RAGLIANDO LORO: "'OOOO OO CHE PAURA, MI= FANNO, OO OO" http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-pau= ra-sciopero-sindacati-polizia-illegale/295911/ CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE = FRA POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO = RENZI! https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-di-= me-il-2-febbraio-carmelo-lopapa/ "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERL= USCONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA= BLOCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGL= I ULTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNE= R, FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVR= EBBERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU METTI AL QU= IRINALE UN FANTOCCIO DI MIA PROPRIETA' CHE COMPRO QUANDO VOGLIO QUALE GIULI= ANO AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... O MEGLIO ANCORA, SE PARLI= AMO DI MIEI FASCIOBAMBOCCI ALLA PIERFERDINANDO CASINI O GIANNI LETTA... TUT= TI MIEI PUPAZZI CHE MI HAN GIA' GARANTITO CHE CON SEI EURO E MEZZO CASH, MI= FIRMEREBBERO TUTTE LE GRAZIE CHE VOGLIO IN NOME DELLA MIA.... PACIFICAZION= E ALLA VASELLINA... E ... SPECIALMENTE ...GIUSTO PER ANDARE SUL SICURO.... = MI FAI ANCHE E SUBITO UNA NORMINA DECAPITANTE NOIOSISSIMI CONCETTI COME DEM= OCRAZIA E GIUSTIZIA CHE IMPONGA IL MIO TORNARE IN POLITICA, COSI' CHE POSSA= FOTTERE IL POPOLO CIUCCIO, LE LEGGI, DOZZINE DI (GRANDISSIMI) MAGISTRATI C= OME ILDA BOCASSINI, EDMONDO BRUTI LIBERATI, NINO DI MATTEO, ROBERTO SCARPIN= ATO, FABIO DE PASQUALE, HENRY WOODCOCK, PASQUALE DRAGO, ATTRAVERSO LA ( BAS= TARDAMENTE VIGLIACCHISSIMA) IMMUNITA' EVITA GALERA, CHE MI RI RITROVEREI"! http://www.ilfattoquotidiano.it/2015/01/18/salva-berlusconi-alessandro-pace= -manina-renzi-reato-falso/1349562/ http://www.ilfattoquotidiano.it/2015/01/08/salva-berlusconi-mucchetti-renzi= -venga-senato-spiegare-successo/1322595/ http://www.ilfattoquotidiano.it/2015/01/06/salva-berlusconi-coppi-ammette-q= uella-norma-segnale-per-quirinale/1318110/ ECCO DOVE CI PORTANO BASTARDI LAVA CASH MAFIOSO A GO GO COME I MALAVITO= SINCRAVATTATI DAVIDE SERRA DI ALGEBRIS E TWITTER INSIEME AL RENATO VALLANZA= SCA UNITO AD UGO FANTOZZI DELLA FINANZA, NOTO AVANZO DI GALERA PAOLO BARRAI= NATO A MILANO IL 28.6.1965, DI CRIMINALISSIMO WMO, CRIMINALISSIMA BSI ITAL= IA SRL DI VIA SOCRATE 26 MILANO E CRIMINALISSIMO BLOG MERCATO "MERDATO" LIB= ERO ( DUE VERMI REPELLENTI CHE RICICLANO ALL'ESTERO VAGONI DI SOLDI DI COSA= NOSTRA, CAMORRA, NDRANGHETA O LADRATI SE NON PURE FRUTTO DI MEGA MAZZETTE = IN DIREZIONE LL LEGA LADRONA ED EX PDL POPOLO DI LADRONI; IN CONGIUNZIONE C= ON BANCHIERI DELINQUENTISSIMI, SPESSO PURE MANDANTI DI OMICIDI O "SUICIDATE= ", COME FATTO CON DAVID ROSSI DI MONTE PASCHI, QUALI GLI ASSASSINI ENNIO DO= RIS E MASSIMO DORIS DI BANCA MEDIOLANUM; O QUALE "O MASSONE CAMORRISTA" GIU= SEPPE SABATO DI BANCA ESPERIA http://www.gruppoesperia.it/chi-siamo/giuseppe-sabato.html https://books.google.it/books?id=3DB1mEj0GtktIC&pg=3DPT304&lpg=3DPT304&dq= =3DGIUSEPPE+SABATO+LICIO+GELLI&source=3Dbl&ots=3DGqtu0KYRmD&sig=3Dd2TOz9sZD= Y6563zIPxwnNYcbxb4&hl=3Dit&sa=3DX&ei=3DI-i_VOOsBMLlUonCgZgI&ved=3D0CFMQ6AEw= CA#v=3Donepage&q=3DGIUSEPPE%20SABATO%20LICIO%20GELLI&f=3Dfalse TUTTI DEL GRUPPO MA-F-INIVEST DI " STEFANO BONTATE, MARCELLO DELL'UTRI,= TOTO RIINA, LICIO GELLI, BERNARDO PROVENZANO E SILVIO BERLUSCONI: " OO CHE= CASO, OO")! E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STEC= CATISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE = MICHELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER = PROTEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROT= TIERE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA = SODOMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOL= O CIUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE MATTEO RENZ= I! http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_ren= zie.html https://www.youtube.com/watch?v=3DA7Ngp6JrK9A http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-paga= ti-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375 VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE= , QUELLO ANTI MAFIA FASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E = SEL! A FARE IL SUO VERO LAVORO, OSSIA LA ZOCCOLA DI STRADA, STA BATTONA HIT= LERIANA, CHE SI CREDE MODELLA MA E' CESSO STRA COLMO DI CELLULITE, DI MARIA= ELENA BOSCHI http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-b= ikini-rosa-in-spiaggia-a-marina-di-pietrasanta-581617_tn.jpg FIGLIA DI ALT= RO VERME CRIMINALISSIMO: MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA= ETRURIA (DOPO AVER PASSATO TUTTA UNA VITA A TRAFFICARE CON COOP VICINISSIM= E A MAFIA, CAMORRA E NDRANGHETA, NON PER NIENTE, STILE "RENZUSCONIANISSIMI"= SALVATORE BUZZI E MASSIMO CARMINATI)! AL QUIRINALE UN UOMO O DONNA VERA, A= LLA NINO DI MATTEO O ILDA BOCASSINI, CHE FACCIA TRASLOCARE IL CANCROMICIDA = DEL MONDO INTERO, SILVIO BERLUSCONI, DA PALAZZO GRAZIOLI A PALAZZO UCCIARDO= NE E SUBITO. O VERA RIVOLUZIONE SARA'! RIVOLUZIONE RIPRISTINANTE VERA DEMOC= RACIA Y LIBERTAD! PS SEMPRE VINCENTISSIMI I GENI BORSISTICI GEORGE SOROS E = MICHELE NISTA A PUNTARE SULLA SPAGNA. PARREBBE CHE DOPO AVER SAPUTO CHE IL = MIGLIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NISTA, VEDA NON MALE LA= SPAGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO, MANCO FOSSERO NOCCIO= LINE, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI BANCO SANTANDER. NON= SARA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON LO E' ALCUN PAESE DE= L PIANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE NON MANCANO ( MA SON= O AL MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA DI RENZUSCONIA)! PER= O', NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI VI E' DEMOCRAZIA VERA!= SIA AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMETTENTISSIMO PABLO IGLE= SIAS DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRONA DI MADRID, VERMI S= TRAGISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERLUSCONI, CHE SI FAN LE= LEGGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLTRE CHE PER SGOZZARE A= MORTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. 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From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.47.170 with SMTP id t30mr6087958yhb.19.1423781087320; Thu, 12 Feb 2015 14:44:47 -0800 (PST) X-Received: by 10.140.37.113 with SMTP id q104mr97915qgq.0.1423781087276; Thu, 12 Feb 2015 14:44:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no859048qae.0!news-out.google.com!n6ni6qar.0!nntp.google.com!j7no184942qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Feb 2015 14:44:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Overloading procedures with parameters of different size? From: David Rogoff Injection-Date: Thu, 12 Feb 2015 22:44:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2070 X-Received-Body-CRC: 3185681635 Xref: mx02.eternal-september.org comp.lang.vhdl:8087 Hi all. More VHDL headaches. I've been using a lot of overloaded procedur= es - mostly to deal with optional arguments / default values that VHDL does= not support. So far, so good. However, I need multiple versions of a pro= cedure that take an std_logic_vector as an input but with different widths.= I have something like the following: subtype shortdata_t is std_logic_vector (7 downto 0); subtype meddata_t is std_logic_vector (15 downto 0); procedure a (d_in : in shortdata_t; .....); procedure a (d_in : in meddata_t; .....); This just gets me illegal redeclaration errors from the compiler. I think = it's because they're different subtypes, not different types. I could use = a generic and pass the size but that's a big headache. Is there a way to d= o this? Also, is there a way (or upcoming standard) to have optional inputs with de= fault values like SystemVerilog so I don't have to have multiple, overloade= d versions of subprograms just to deal with that? Thanks, David From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? Date: Thu, 12 Feb 2015 22:59:12 +0000 (UTC) Organization: A noiseless patient Spider Lines: 42 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 12 Feb 2015 22:59:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="22466"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Y3ACFaWFBz+4N80VXywiC" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:j9IW4r1ZCxVzW2v65+B2F1+naxk= Xref: mx02.eternal-september.org comp.lang.vhdl:8088 On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote: > Hi all. More VHDL headaches. I've been using a lot of overloaded > procedures - mostly to deal with optional arguments / default values > that VHDL does not support. So far, so good. However, I need multiple > versions of a procedure that take an std_logic_vector as an input but > with different widths. I have something like the following: > > subtype shortdata_t is std_logic_vector (7 downto 0); > subtype meddata_t is std_logic_vector (15 downto 0); > > > procedure a (d_in : in shortdata_t; .....); > > procedure a (d_in : in meddata_t; .....); > > This just gets me illegal redeclaration errors from the compiler. I > think it's because they're different subtypes, not different types. I > could use a generic and pass the size but that's a big headache. Is > there a way to do this? > > Also, is there a way (or upcoming standard) to have optional inputs with > default values like SystemVerilog so I don't have to have multiple, > overloaded versions of subprograms just to deal with that? > > Thanks, > > David There's always procedure a (d_in : std_logic_vector; .....) is begin if d_in'length = shortdata_t'length then .... Inelegant, but it would get the job done. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Colin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: Digital Design / Hardware Simulation Date: Fri, 13 Feb 2015 12:51:14 +0100 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="20508"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+4h0LCp3rm93DQ3gdLeWzMRnO7Ra8mtLVKPS5Vw7lIFg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <12e20410-787b-4dcc-bcd9-b55d0036848d@googlegroups.com> Cancel-Lock: sha1:sa86APQfraVho3Of/GGHUwowT+M= X-X-Sender: gloster@anapnea.net Xref: mx02.eternal-september.org comp.lang.vhdl:8089 Justin Knight sent: |-------------------------------------------------------------------| |"Hello, | | | |I am looking for a digital design engineer to come work for us, | |MetaMorph, on Google's Project Ara. | | | |Our tools use SystemC for digital simulation and we're looking for | |someone to help guide this area. | | | |I'm sorry if this is spamming, but I'm offering a legit well paying| |and permanent job. I'm open to all types of arrangements for the | |right person. Have a look or drop me a line. | | | |metamorphsoftware.com/careers/ | |projectara.com | | | |Thank you, | | | |Justin Knight | |CEO, MetaMorph" | |-------------------------------------------------------------------| Hello, This is a VHDL (i.e.) engineering newsgroup, therefore this advertisement for a SystemC(R) is not appropriate for this newsgroup. I hope that you will see sense and use a language which is fit for purpose. Yours sincerely, Colin Paul de Gloucester From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.255.68 with SMTP id ao4mr8190242pad.1.1423828370593; Fri, 13 Feb 2015 03:52:50 -0800 (PST) X-Received: by 10.140.109.66 with SMTP id k60mr118479qgf.36.1423828370504; Fri, 13 Feb 2015 03:52:50 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no10910822igb.0!news-out.google.com!c1ni5qar.1!nntp.google.com!i13no951297qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Feb 2015 03:52:50 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=99.184.243.36; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 99.184.243.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> Subject: Re: Overloading procedures with parameters of different size? From: KJ Injection-Date: Fri, 13 Feb 2015 11:52:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8090 On Thursday, February 12, 2015 at 5:44:48 PM UTC-5, David Rogoff wrote: > > Also, is there a way (or upcoming standard) to have optional inputs with default values like SystemVerilog so I don't have to have multiple, overloaded versions of subprograms just to deal with that? > Yes, you just put the default value in the procedure declaration: The following defaults the value of 'd_in' to "00000000" procedure a (d_in : std_logic_vector "= x"00"; .....) Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? Date: Fri, 13 Feb 2015 13:39:34 +0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 13 Feb 2015 13:39:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="6184"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Gks+ndl/41Wv9hg62LbbL8VkXu4S11L8=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:rns8Wa3/68iWvlen2ZtHIZFhKbQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8091 On Thu, 12 Feb 2015 14:44:47 -0800, David Rogoff wrote: > Hi all. More VHDL headaches. I've been using a lot of overloaded > procedures - mostly to deal with optional arguments / default values > that VHDL does not support. So far, so good. However, I need multiple > versions of a procedure that take an std_logic_vector as an input but > with different widths. I have something like the following: > > subtype shortdata_t is std_logic_vector (7 downto 0); > subtype meddata_t is std_logic_vector (15 downto 0); > > > procedure a (d_in : in shortdata_t; .....); procedure a (d_in : in std_logic_vector; .....); Make the body of "a" agnostic about d_in's actual length, using attributes where necessary, "for i in d_in'range loop ..." etc. If you need to identify the actual subtype, Rob's trick of testing d_in'length in an if or case statement will work. -- Brian From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.182.135.197 with SMTP id pu5mr9760978obb.32.1423854951797; Fri, 13 Feb 2015 11:15:51 -0800 (PST) X-Received: by 10.140.89.84 with SMTP id u78mr142968qgd.10.1423854951731; Fri, 13 Feb 2015 11:15:51 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no15755610igb.0!news-out.google.com!c1ni5qar.1!nntp.google.com!i13no1034993qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Feb 2015 11:15:51 -0800 (PST) In-Reply-To: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.163.20.52; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 64.163.20.52 References: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> Subject: Re: Overloading procedures with parameters of different size? From: David Rogoff Injection-Date: Fri, 13 Feb 2015 19:15:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:8092 Thanks - Unfortunately, this will only work with named associations in the= procedure/function call. In general, I'm in favor of this, but when you h= ave hundreds of calls of the same procedure that each have long lists of ar= guments, it can be get really messy. Does it work for positional associati= ons if the optional argument is the last one? David From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe002.ams.xsnews.nl!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 13 Feb 2015 18:16:13 -0600 Date: Sat, 14 Feb 2015 00:16:13 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Overloading procedures with parameters of different size? References: <8233b7c0-98a0-4129-b11b-cf891ccc6435@googlegroups.com> <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> In-Reply-To: <13df3cc1-8121-4404-a285-a291304eaee8@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Message-ID: Lines: 14 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-exsMftOUZW9yaK8oy4cPA7MtkMODFxWgaeMk2MCsKlZ8ZVdG6gupcRIMdnkHtzlVaRHmLjnIgGnN8Z8!taK6sEIGvuHya8pnDoAA6wTKnW9B0o9zUWd2hdAeGh6ARFjJV2/dXffmgE8FEx7skf+C2XoThVTq!ZX+0H7iHDH2JekIKlswDe/gB X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1918 Xref: mx02.eternal-september.org comp.lang.vhdl:8093 On 13/02/15 19:15, David Rogoff wrote: > Thanks - Unfortunately, this will only work with named associations in the procedure/function call. In general, I'm in favor of this, but when you have hundreds of calls of the same procedure that each have long lists of arguments, it can be get really messy. Does it work for positional associations if the optional argument is the last one? > > David > Yes, you can mix positional and named association, as long as positional association comes first. You can't change back to positional association after you've started named assocation. regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.52.142.141 with SMTP id rw13mr13818276vdb.6.1423941101768; Sat, 14 Feb 2015 11:11:41 -0800 (PST) X-Received: by 10.50.85.17 with SMTP id d17mr285287igz.7.1423941101662; Sat, 14 Feb 2015 11:11:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j7no589219qaq.1!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16345823igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Feb 2015 11:11:41 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Weng Tianxiang Injection-Date: Sat, 14 Feb 2015 19:11:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8094 Hi Jim, I published a paper "HDL code efficiency sources and its solutions" in the publication of the 11th annual international HDL conference & exhibition in 2002. The conference, as I knew, was held by VHDL committee chaired by Jim Lewis. In the paper I introduced two groups of total 5 new keywords: Group A: orif, elsor and errels. Group B: machine and exclusive. I used Google and Microsoft tools to search the paper and found nothing in the searching results. As Jim indicated before, some or all of new keywords are introduced into Verilog-2008, VHDL-2008 and VHDL2009. I tried another paper "Fault simulation with dynamic model abstraction switching" and it wasn't found either. I don't know why the articles in the conference cannot be found by Google and Microsoft searching tools. Is the conference's academic level so low that all papers published in the conference are not considered as scientific papers? Jim, you should pay attention to it! Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.221.5 with SMTP id qa5mr16129952pac.16.1423967930284; Sat, 14 Feb 2015 18:38:50 -0800 (PST) X-Received: by 10.50.79.131 with SMTP id j3mr301073igx.16.1423967930002; Sat, 14 Feb 2015 18:38:50 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no16516385igb.0!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16516384igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 14 Feb 2015 18:38:49 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.69.57; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.69.57 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13e73df5-e334-42bd-8297-712b6da3d24b@googlegroups.com> Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Jim Lewis Injection-Date: Sun, 15 Feb 2015 02:38:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: mx02.eternal-september.org comp.lang.vhdl:8095 Hi Weng, > I published a paper "HDL code efficiency sources and its solutions" in the publication of the 11th annual international HDL conference & exhibition in 2002. The conference, as I knew, was held by VHDL committee chaired by Jim Lewis. Sure I remember your paper. OTOH, VASG which I currently chair (but not back then) was not the conference organizer. > Is the conference's academic level so low that all papers published in the conference are not considered as scientific papers? > > Jim, you should pay attention to it! While I was on the program committee at that time, I did not organize the conference. I suspect that you may have received the proceedings on a CD. Did you search your resources for it? What you are searching for is papers from the International HDL Conference - in 2003, it changed names to DVCon. I looked on the DVCon site and only found papers back to 2008. I looked on my computer to see if I might have a copy of the conference papers and I do not. Looked around my office to see if I could find my disk but did not see it. Best Regards, Jim From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.136.79 with SMTP id py15mr17519053pab.40.1424020626320; Sun, 15 Feb 2015 09:17:06 -0800 (PST) X-Received: by 10.50.178.180 with SMTP id cz20mr326090igc.14.1424020626207; Sun, 15 Feb 2015 09:17:06 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no16836394igb.0!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no16836385igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Feb 2015 09:17:05 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? From: Weng Tianxiang Injection-Date: Sun, 15 Feb 2015 17:17:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 50 Xref: mx02.eternal-september.org comp.lang.vhdl:8096 On Saturday, February 14, 2015 at 11:11:43 AM UTC-8, Weng Tianxiang wrote: > Hi Jim, > I published a paper "HDL code efficiency sources and its solutions" in th= e publication of the 11th annual international HDL conference & exhibition = in 2002. The conference, as I knew, was held by VHDL committee chaired by J= im Lewis. >=20 > In the paper I introduced two groups of total 5 new keywords:=20 > Group A: orif, elsor and errels.=20 > Group B: machine and exclusive. >=20 > I used Google and Microsoft tools to search the paper and found nothing i= n the searching results. >=20 > As Jim indicated before, some or all of new keywords are introduced into = Verilog-2008, VHDL-2008 and VHDL2009. >=20 > I tried another paper "Fault simulation with dynamic model abstraction sw= itching"=20 > and it wasn't found either.=20 >=20 > I don't know why the articles in the conference cannot be found by Google= and Microsoft searching tools. >=20 > Is the conference's academic level so low that all papers published in th= e conference are not considered as scientific papers? >=20 > Jim, you should pay attention to it! >=20 > Thank you. >=20 > Weng Hi Jim, Thank you for your reply. As the present VHDL committee chairman, you should do something to make sur= e that every paper published in the conferences held by VHDL committee shou= ld go into some data base so that it will be searchable through web. If you= couldn't do that it certainly would do deep harms to any future conference= held by your VHDL committee.=20 If your committee doesn't require any payment I think any digital paper lib= rary would like to freely accept your offer to register all papers which ha= ve been published in any conferences held by VHDL committee even though you= are not responsible for such blunder. Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Colin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: A searching miss for all papers published in the 11th annual international HDL conference & exhibition? Date: Mon, 16 Feb 2015 12:24:07 +0100 Organization: A noiseless patient Spider Lines: 92 Message-ID: References: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="1269e88b772369679a1c60bd0bac220f"; logging-data="26186"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18tVpyh8pz1IkSYbi1ELFGgus57AIHKFxGDz2tzURKSkg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <9985ada7-3730-4c75-91c5-b9d4ffbbfb58@googlegroups.com> Cancel-Lock: sha1:6zKXqUWuAO3Bg8/vMuKsGq3LKas= X-X-Sender: gloster@anapnea.net Xref: mx02.eternal-september.org comp.lang.vhdl:8097 On February 15th, 2015, Weng Tianxiang posted: |---------------------------------------------------------------------------| |"On Saturday, February 14, 2015 at 11:11:43 AM UTC-8, Weng Tianxiang wrote:| |> Hi Jim, | |> I published a paper "HDL code efficiency sources and its solutions" | |> in the publication of the 11th annual international HDL conference & | |> exhibition in 2002. The conference, as I knew, was held by VHDL | |> committee chaired by Jim Lewis. | |> | |> In the paper I introduced two groups of total 5 new keywords: | |> Group A: orif, elsor and errels. | |> Group B: machine and exclusive. | |> | |> I used Google and Microsoft tools to search the paper and found | |> nothing in the searching results. | |> | |> As Jim indicated before, some or all of new keywords are introduced | |> into Verilog-2008, VHDL-2008 and VHDL2009. | |> | |> I tried another paper "Fault simulation with dynamic model | |> abstraction switching" | |> and it wasn't found either." | |---------------------------------------------------------------------------| Dear Weng: Unfortunately I did not find "HDL code efficiency sources and its solutions". Google Scholar claimed today that "Fault simulation with dynamic model abstraction switching" was cited two times. |---------------------------------------------------------------------------| |"> I don't know why the articles in the conference cannot be found by | |> Google and Microsoft searching tools." | |---------------------------------------------------------------------------| What criteria are utilized by Google Scholar are subject to much speculation. See for example ListServ messages archived by HTTP://web.UTK.edu/~gwhitney/sigmetrics.html |---------------------------------------------------------------------------| |"> Is the conference's academic level so low that all papers published | |> in the conference are not considered as scientific papers?" | |---------------------------------------------------------------------------| Maybe the reason these search engines did not find them is because these papers are archived on C.D.s instead of being freely available on the Internet. They search the Internet instead of C.D.s. |---------------------------------------------------------------------------| |"> Jim, you should pay attention to it! | |> | |> Thank you. | |> | |> Weng | | | |Hi Jim, | |Thank you for your reply. | | | |As the present VHDL committee chairman, you should do something to | |make sure that every paper published in the conferences held by VHDL | |committee should go into some data base so that it will be searchable | |through web. If you couldn't do that it certainly would do deep harms | |to any future conference held by your VHDL committee. | | | |If your committee doesn't require any payment I think any digital | |paper library would like to freely accept your offer to register all | |papers which have been published in any conferences held by VHDL | |committee even though you are not responsible for such blunder. | | | |Thank you. | | | |Weng" | |---------------------------------------------------------------------------| Information should be available. Absurdly HDLCon.org obstructed making its information available. HTTPS://web.Archive.org/web/*/http://www.hdlcon.org reported: "Page cannot be crawled or displayed due to robots.txt. See www.hdlcon.org robots.txt page. Learn more about robots.txt." Archive.org can help to find some old files, e.g. HTTPS://web.Archive.org/web/20070212200049/http://www.dvcon.org/archive.html but I did not find files from this 2002 conference. HTTPS://web.Archive.org/web/20100127041856/http://dvcon.org/archive.html even had hyperlinks for 2001 and 2003, but not for 2002. Good luck, Colin Paul de Gloucester From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.40.112 with SMTP id e76mr23395715yhb.5.1424195428626; Tue, 17 Feb 2015 09:50:28 -0800 (PST) X-Received: by 10.140.109.181 with SMTP id l50mr356210qgf.3.1424195428584; Tue, 17 Feb 2015 09:50:28 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no1826457qae.0!news-out.google.com!n6ni8qar.0!nntp.google.com!j7no1152123qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Feb 2015 09:50:28 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> Subject: Open source unit testing framework release From: Lars Asplund Injection-Date: Tue, 17 Feb 2015 17:50:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3127 X-Received-Body-CRC: 2362345869 Xref: mx02.eternal-september.org comp.lang.vhdl:8098 Hi, VUnit, an unit testing framework for VHDL, is now freely available on githu= b (https://github.com/LarsAsplund/vunit). It is released under the business= -friendly Mozilla Public License, v. 2.0 and features the functionality nee= ded to realize continuous and automated testing of your VHDL code. VUnit do= esn't replace but rather complements traditional testing methodologies by s= upporting a "test early and often" approach through automation. A quick 6 minute introduction to unit testing can be found at https://www.y= outube.com/watch?v=3DPZuBqcxS8t4 and a short (12 min) introduction to VUnit= can be found at https://www.youtube.com/watch?v=3DD8s_VLD91tw. Some of the VUnit highlights are - Python test runner that enables powerful test administration, can handle = VHDL fatal run-time errors (e.g. division by zero), and ensures test case i= ndependence. - Scanners for identifying files, tests, file dependencies, and file change= s enable for automatic (re)compilation and execution of test suites. - Scripting as well as command line support. - Support for running same test suite with different generics. - VHDL test runner which enables test execution for not fully supported sim= ulators. We currently have full support for ModelSim but Aldec support is c= oming soon. - Assertion checker library that extends VHDL built-in support (assert). - Logging framework supporting display and file output, different log level= s, filtering on level and design hierarchy, output formatting and multiple = loggers. Spreadsheet tool integration. - Location preprocessor that traces log and check calls back to file and li= ne number. - JUnit report files for better Jenkins integration. We are an active and responsive community but want to grow to benefit furth= er development. You can participate by adding questions on Github, suggesti= ng enhancement, reporting bugs, and contributing code. If you like what you= see click "star" and if you want to get notified of the progress you shoul= d click "follow". Regards, Lars Asplund From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Wed, 18 Feb 2015 13:28:21 +0000 (UTC) Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 18 Feb 2015 13:28:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="31819"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18auCIgHIWZHSO6A3wz0LBBc2Ls5KZ+3Ok=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:pxphUnkRe1USmTIf887dZq24P4w= Xref: mx02.eternal-september.org comp.lang.vhdl:8099 On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: > Hi, > > VUnit, an unit testing framework for VHDL, is now freely available on > github (https://github.com/LarsAsplund/vunit). It is released under the > business-friendly Mozilla Public License, v. 2.0 and features the > functionality needed to realize continuous and automated testing of your > VHDL code. VUnit doesn't replace but rather complements traditional > testing methodologies by supporting a "test early and often" approach > through automation. Interesting - another user of OSVVM too... You may be interested to know that as of ghdl-0.32 (not yet released but buildable from source for most systems : Mac OSX is giving a little trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be easy to integrate into Vunit... https://sourceforge.net/projects/ghdl-updates/?source=navbar -- Brian From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.50.176.202 with SMTP id ck10mr183152igc.5.1424267996593; Wed, 18 Feb 2015 05:59:56 -0800 (PST) X-Received: by 10.140.92.226 with SMTP id b89mr3981qge.29.1424267996424; Wed, 18 Feb 2015 05:59:56 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no18387490igb.0!news-out.google.com!n6ni9qar.0!nntp.google.com!j7no1332388qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Feb 2015 05:59:56 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1659df2a-9c50-4095-a689-a62d5bb57789@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Wed, 18 Feb 2015 13:59:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8100 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: >=20 > > Hi, > >=20 > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of you= r > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. >=20 > Interesting - another user of OSVVM too... >=20 > You may be interested to know that as of ghdl-0.32 (not yet released but= =20 > buildable from source for most systems : Mac OSX is giving a little=20 > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be= =20 > easy to integrate into Vunit... >=20 > https://sourceforge.net/projects/ghdl-updates/?source=3Dnavbar >=20 > -- Brian Hi Brian, We redistribute OSVVM because it's commonly used and it's convenient for Gi= t users to only do git pull to have the latest version instead of relying o= n the version provided with your simulator or manually download and unzip f= rom osvvm.org. VUnit doesn't require OSVVM to work and it also supports, in addition to VH= DL 2008, the older VHDL 93 and 2002. Our acceptance tests run all these ver= sions of VHDL. We haven't tried VUnit under GHDL (maybe someone else did?) but there is a = question on github (https://github.com/LarsAsplund/vunit/issues/10) regardi= ng what simulator support people would like to see. As I said in my first p= ost I'd like an active community so that we can put our development efforts= where they are best needed. You should place your vote! Regards, Lars From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.237.140 with SMTP id vc12mr1718109pac.44.1424299631249; Wed, 18 Feb 2015 14:47:11 -0800 (PST) X-Received: by 10.140.108.9 with SMTP id i9mr54961qgf.1.1424299631202; Wed, 18 Feb 2015 14:47:11 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no12707543igb.0!news-out.google.com!n6ni11qar.0!nntp.google.com!j7no1457663qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Feb 2015 14:47:11 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <39eefd4a-d2b8-44f8-aedd-8f1f3f2f0d86@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Wed, 18 Feb 2015 22:47:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 36 Xref: mx02.eternal-september.org comp.lang.vhdl:8101 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: >=20 > > Hi, > >=20 > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of you= r > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. >=20 > Interesting - another user of OSVVM too... >=20 > You may be interested to know that as of ghdl-0.32 (not yet released but= =20 > buildable from source for most systems : Mac OSX is giving a little=20 > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be= =20 > easy to integrate into Vunit... >=20 > https://sourceforge.net/projects/ghdl-updates/?source=3Dnavbar >=20 > -- Brian An addition to my previous post. VUnit is designed to integrate nicely with= Jenkins (https://www.youtube.com/watch?v=3DD8s_VLD91tw) which enables you = to distribute your simulations on several machines. This is never an option= for many due to license costs so a free option would certainly make a diff= erence in that area. However, the majority of our audience sits with Models= im or Aldec so we've focused our initial efforts there. After that I would = like to look into the free alternatives unless someone is willing to make t= hat effort in parallel ;-) /Lars From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.202.207 with SMTP id d55mr5046798yho.4.1424361844696; Thu, 19 Feb 2015 08:04:04 -0800 (PST) X-Received: by 10.140.104.174 with SMTP id a43mr106489qgf.2.1424361844679; Thu, 19 Feb 2015 08:04:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j7no1681772qaq.1!news-out.google.com!n6ni12qar.0!nntp.google.com!i13no2355320qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 19 Feb 2015 08:04:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Thu, 19 Feb 2015 16:04:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 24 Xref: mx02.eternal-september.org comp.lang.vhdl:8102 Den onsdag 18 februari 2015 kl. 14:29:02 UTC+1 skrev Brian Drummond: > On Tue, 17 Feb 2015 09:50:28 -0800, Lars Asplund wrote: > > > Hi, > > > > VUnit, an unit testing framework for VHDL, is now freely available on > > github (https://github.com/LarsAsplund/vunit). It is released under the > > business-friendly Mozilla Public License, v. 2.0 and features the > > functionality needed to realize continuous and automated testing of your > > VHDL code. VUnit doesn't replace but rather complements traditional > > testing methodologies by supporting a "test early and often" approach > > through automation. > > Interesting - another user of OSVVM too... > > You may be interested to know that as of ghdl-0.32 (not yet released but > buildable from source for most systems : Mac OSX is giving a little > trouble), ghdl understands enough VHDL-2008 to support OSVVM. Should be > easy to integrate into Vunit... > > https://sourceforge.net/projects/ghdl-updates/?source=navbar > > -- Brian @Brian Please join the VUnit with GHDL discussion on this thread: https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL are being discussed From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Fri, 20 Feb 2015 10:47:04 +0000 (UTC) Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 20 Feb 2015 10:47:04 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="18148"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18a8hZgo88L0EUtu9jRNrJFWx7pGsMW5X0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/4ENvPn5FWlpGima6nRzCch3Bos= Xref: mx02.eternal-september.org comp.lang.vhdl:8103 On Thu, 19 Feb 2015 08:04:04 -0800, Lars Asplund wrote: > > @Brian Please join the VUnit with GHDL discussion on this thread: > https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL > are being discussed I'll have to subscribe to Github before I respond there. Probably the best thing would be to file a ticket - enhancement request - at https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar It sounds like a reasonable facility to add. Thanks From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.182.94.204 with SMTP id de12mr9658171obb.13.1424433114503; Fri, 20 Feb 2015 03:51:54 -0800 (PST) X-Received: by 10.140.31.134 with SMTP id f6mr175068qgf.33.1424433114472; Fri, 20 Feb 2015 03:51:54 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no13439487igb.0!news-out.google.com!n6ni12qar.0!nntp.google.com!i13no2540938qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Feb 2015 03:51:54 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Fri, 20 Feb 2015 11:51:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8104 Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: > On Thu, 19 Feb 2015 08:04:04 -0800, Lars Asplund wrote: > > > > > @Brian Please join the VUnit with GHDL discussion on this thread: > > https://github.com/LarsAsplund/vunit/issues/10 Some requirements on GHDL > > are being discussed > > I'll have to subscribe to Github before I respond there. > > Probably the best thing would be to file a ticket - enhancement request - > at > https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar > > It sounds like a reasonable facility to add. > > Thanks Just my thought. I will do that. /Lars From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Open source unit testing framework release Date: Sat, 21 Feb 2015 12:32:17 +0000 (UTC) Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 21 Feb 2015 12:32:17 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="7839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19OIeeuVbATQbHQuP8syqyv7FN7hZmOSs0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:hFe+Rojj2XJapDx6HnSMr1sndeI= Xref: mx02.eternal-september.org comp.lang.vhdl:8105 On Fri, 20 Feb 2015 03:51:54 -0800, Lars Asplund wrote: > Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: >> Probably the best thing would be to file a ticket - enhancement request >> It sounds like a reasonable facility to add. > Just my thought. I will do that. and Tristan has agreed to add it... -- Brian From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.182.246.73 with SMTP id xu9mr2424898obc.17.1424523541780; Sat, 21 Feb 2015 04:59:01 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr5045qgp.26.1424523541671; Sat, 21 Feb 2015 04:59:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no14595753igb.0!news-out.google.com!c1ni8qar.1!nntp.google.com!i13no3093732qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 21 Feb 2015 04:59:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6de78f57-a634-4773-926b-05bc7a220cc5@googlegroups.com> Subject: Re: Open source unit testing framework release From: Lars Asplund Injection-Date: Sat, 21 Feb 2015 12:59:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 16 Xref: mx02.eternal-september.org comp.lang.vhdl:8106 Den l=F6rdag 21 februari 2015 kl. 13:33:03 UTC+1 skrev Brian Drummond: > On Fri, 20 Feb 2015 03:51:54 -0800, Lars Asplund wrote: >=20 > > Den fredag 20 februari 2015 kl. 11:47:46 UTC+1 skrev Brian Drummond: >=20 > >> Probably the best thing would be to file a ticket - enhancement reques= t > >> It sounds like a reasonable facility to add. > > Just my thought. I will do that. >=20 > and Tristan has agreed to add it... >=20 > -- Brian Great! Thanks.=20 Lars From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.182.111.132 with SMTP id ii4mr17402168obb.2.1424797777671; Tue, 24 Feb 2015 09:09:37 -0800 (PST) X-Received: by 10.50.110.101 with SMTP id hz5mr281842igb.6.1424797777498; Tue, 24 Feb 2015 09:09:37 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no27765940igb.0!news-out.google.com!db6ni36953igc.0!nntp.google.com!hl2no27765930igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Feb 2015 09:09:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Subject: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 24 Feb 2015 17:09:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3156 X-Received-Body-CRC: 1810898056 Xref: mx02.eternal-september.org comp.lang.vhdl:8107 Hi Jim, glen, JK, rickman, Mike, Andy,=20 I have filed a provisional patent application: "Systematic method of coding= wave pipelined circuits in HDL". If it is proved correct, the patent will = introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four= source code modules for a new library in HDL and thoroughly resolve a pend= ing problem so that every digital designer can code wave-pipelined circuits= in HDL. Here is the abstract of the invention: The present invention classifies all critical paths into two basic type= s: a series critical path and a feedback critical path, and divides each of= wave-pipelined circuits into two components: a static logic part, called c= ritical path component (CPC), and a dynamic logic part, formalized into fou= r wave-pipelining components (WPC) shared by all wave-pipelined circuits. E= ach wave-pipelining ready code in HDL comprises two components: a WPC insta= ntiation and a CPC instantiation wire-connected and linked by a new link st= atement. Each WPC has new wave constants which play the same role as generi= c constants do, but whose initial values are determined and assigned by a s= ynthesizer after code analysis, so designers can use after-synthesization i= nformation in their code before synthesization for wave-pipelining technolo= gy. The responsibility of analyzing and manipulating wave-pipelining ready = code, generating and implementing wave-pipelined circuits on a design-wide = or chip-wide scale in HDL is shifted from designers to synthesizers. Anyone who are interested in its content is welcome to send a email request= to the following email address: wtx wtx @ gmail . com with title "Systemat= ic" and he will receive the full documents: one specification, 9 drawings a= nd one text file in VHDL. If one reviews the files and feels that it would be a good thing to recomme= nd the application to his company to buy it, the first person to do it afte= r his recommended company does so will receive $10,000 commission fee. Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:44 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Svenn Newsgroups: comp.lang.vhdl Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL Date: Thu, 26 Feb 2015 12:37:34 +0100 Organization: Aioe.org NNTP Server Lines: 10 Message-ID: References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> NNTP-Posting-Host: tDMmuv6iTFrCTcEz1T/Pnw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.3.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8108 On 24/02/15 18:09, Weng Tianxiang wrote: > If one reviews the files and feels that it would be a good thing to recommend the application > to his company to buy it, the first person to do it after his recommended company does so > will receive $10,000 commission fee. In my country, I would go to jail for doing so. -- Svenn From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.222.103 with SMTP id s97mr8710686yhp.19.1424970309516; Thu, 26 Feb 2015 09:05:09 -0800 (PST) X-Received: by 10.50.129.98 with SMTP id nv2mr230272igb.1.1424970309333; Thu, 26 Feb 2015 09:05:09 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i13no8367616qae.0!news-out.google.com!qk8ni43839igc.0!nntp.google.com!hl2no32071864igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Feb 2015 09:05:08 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <99da35c2-083f-49e5-a2ea-0f88688f7409@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 26 Feb 2015 17:05:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1910 X-Received-Body-CRC: 423788661 Xref: mx02.eternal-september.org comp.lang.vhdl:8109 On Thursday, February 26, 2015 at 3:37:37 AM UTC-8, Svenn Are Bjerkem wrote: > On 24/02/15 18:09, Weng Tianxiang wrote: > > If one reviews the files and feels that it would be a good thing to recommend the application > > to his company to buy it, the first person to do it after his > recommended company does so > > will receive $10,000 commission fee. > > In my country, I would go to jail for doing so. > > -- > Svenn Svenn, Do it following your company bylaw: 1. The recommendation does benefit your company. 2. Tell your company the commission fee. If your company agree you can accept it; if not abandon it. 3. Pay due tax properly. I am not generate a crime scene for you to do the wrong thing. Weng From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.4.134 with SMTP id 6mr10611812yhj.35.1425002593664; Thu, 26 Feb 2015 18:03:13 -0800 (PST) X-Received: by 10.50.222.75 with SMTP id qk11mr34293igc.0.1425002593372; Thu, 26 Feb 2015 18:03:13 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j7no8048387qaq.1!news-out.google.com!qk8ni43055igc.0!nntp.google.com!hl2no26478065igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Feb 2015 18:03:12 -0800 (PST) In-Reply-To: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 27 Feb 2015 02:03:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8179 X-Received-Body-CRC: 642128293 Xref: mx02.eternal-september.org comp.lang.vhdl:8110 On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote: > Hi Jim, glen, JK, rickman, Mike, Andy,=20 >=20 > I have filed a provisional patent application: "Systematic method of codi= ng wave pipelined circuits in HDL". If it is proved correct, the patent wil= l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo= ur source code modules for a new library in HDL and thoroughly resolve a pe= nding problem so that every digital designer can code wave-pipelined circui= ts in HDL. >=20 > Here is the abstract of the invention: >=20 > The present invention classifies all critical paths into two basic ty= pes: a series critical path and a feedback critical path, and divides each = of wave-pipelined circuits into two components: a static logic part, called= critical path component (CPC), and a dynamic logic part, formalized into f= our wave-pipelining components (WPC) shared by all wave-pipelined circuits.= Each wave-pipelining ready code in HDL comprises two components: a WPC ins= tantiation and a CPC instantiation wire-connected and linked by a new link = statement. Each WPC has new wave constants which play the same role as gene= ric constants do, but whose initial values are determined and assigned by a= synthesizer after code analysis, so designers can use after-synthesization= information in their code before synthesization for wave-pipelining techno= logy. The responsibility of analyzing and manipulating wave-pipelining read= y code, generating and implementing wave-pipelined circuits on a design-wid= e or chip-wide scale in HDL is shifted from designers to synthesizers. >=20 > Anyone who are interested in its content is welcome to send a email reque= st to the following email address: wtx wtx @ gmail . com with title "System= atic" and he will receive the full documents: one specification, 9 drawings= and one text file in VHDL. >=20 > If one reviews the files and feels that it would be a good thing to recom= mend the application to his company to buy it, the first person to do it af= ter his recommended company does so will receive $10,000 commission fee. >=20 > Thank you. >=20 > Weng Hi, I want to add some introductions to what the wave-pipelined circuits are an= d their status. [0003] A synchronous digital system contains a lot of registers. Valid d= ata flow through successive registers from system input registers to system= output registers. All data flows are synchronous with triggering edges of = a chip clock. For example, data flow from registers A to registers B, from = registers B to registers C and so on in a successive order on the same cloc= k cycle. [0004] A path in a synchronous digital system is a route between any nei= ghboring registers connected by combinational logic. If the target running = frequency for a digital design is predetermined, the upper limit of propaga= ting time for any paths is determined and has the inverse value of the targ= et running frequency. A path is called a critical path if the time signals = take to propagate through it is beyond the predetermined propagating time, = and the time is called the path's critical time. If there are any critical = paths, digital designers must spend time reducing all critical times by all= means and eliminating all critical paths to meet the target running freque= ncy. [0005] Wave-pipelining is a technology which completes an operation that= needs several clock cycles to propagate without intermediate registers and= with input data acceptable on every clock cycle. For example, in a convent= ional pipelining operation, data flow from registers A to registers D throu= gh registers B and C to divide the critical path time into multiple smaller= intervals to meet the critical time: A to B to C to D; with wave-pipelinin= g, data flow through registers A and D without intermediate registers B and= C. Absolutely, wave-pipelining will reduce logic resource usage and is sup= erior to the conventional pipelining technology if it can be used. Here are the most important inequalities involving wave-pipelining from pap= er "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burleson e= t al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no. 3, = pp. 464-474, Sep. 1998. [0018] Currently many memory chip manufacturers successfully use wave-pi= pelining in their memory chip products with higher rate outputs, reduced po= wer consumption and logic resources; and a few scientists use FPGA chips as= a base to show some circuits can be done with wave-pipelining in isolated = environments. Their works prove that the wave-pipelining is a very powerful= tool to reduce power consumption and logic resources. Now there are two ma= jor existing obstacles preventing any ordinary digital designers from using= the wave-pipelining in HDL: * The software algorithms making wave-pipelining successful, like Wong and = Klass algorithms and others, have already been developed and matured, but o= rdinary digital designers have no means or resources to access to the techn= ology, because there are no international HDL standards on how synthesizer = manufacturers incorporate those capabilities into their products. * HDL needs the capabilities for digital designers to write wave-pipelining= ready code for any number of critical paths on a design-wide or chip-wide = scale instead of in an isolated environment and the written code can be ide= ntified, synthesized and used to generate wave-pipelined circuits by any sy= nthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 [0019] The target of the present invention is: * Invent a wave-pipelining coding system as new part of HDL standards for d= esigners to write wave-pipelining ready code which can be identified, synth= esized and used to generate wave-pipelined circuits by any synthesizer in A= SIC or FPGA. * Make wave-pipelining ready code written based on the coding system workin= g with no extra logic generated, compared with independently written wave-p= ipelined circuits, and with no code changes when switching from non-wave-pi= pelined mode to wave-pipelined mode or vice verse if all of wave-pipelining= ready code meet wave-pipelining requirements.=20 * Shift burdens of analyzing and manipulating wave-pipelining ready code, g= enerating and implementing wave-pipelined circuits on a design-wide or chip= -wide scale in HDL from individual designers to synthesizer manufacturers. [0020] If the coding system becomes new part of HDL standards all synthe= sizer manufactures will automatically be forced to implement all well-known= wave-pipelining algorithms and techniques within their products, a competi= tion will start for better implementations, making wave-pipelining techniqu= e available to every digital designer in HDL. Weng From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.66.224.42 with SMTP id qz10mr14844184pac.0.1425066693234; Fri, 27 Feb 2015 11:51:33 -0800 (PST) X-Received: by 10.140.33.202 with SMTP id j68mr241019qgj.27.1425066692965; Fri, 27 Feb 2015 11:51:32 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no28029101igb.0!news-out.google.com!n6ni190qar.0!nntp.google.com!j7no8768170qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Feb 2015 11:51:32 -0800 (PST) In-Reply-To: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Fri, 27 Feb 2015 19:51:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 23 Xref: mx02.eternal-september.org comp.lang.vhdl:8111 On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > [0020] If the coding system becomes new part of HDL standards all > synthesizer manufactures will automatically be forced to implement all we= ll- > known wave-pipelining algorithms and techniques within their products, a= =20 > competition will start for better implementations, making wave-pipelining= =20 > technique available to every digital designer in HDL. >=20 A couple of problems with your assumptions: - No standard body will accept a patent burdened idea to incorporate into a= new revision of a standard. You would likely have to effectively surrende= r your patent rights (should they be granted in the first place) in order t= o get this to happen. - If you think that simply being part of a standard will force synthesis ve= ndors to do anything at all, you're very mistaken. - Wave pipelining has not caught on with FPGA suppliers in the 45 years sin= ce the concept was first introduced nor in the 16 years since Burleson's pa= per was published so uptake on the technique has not been very quick. That= doesn't imply that it will never catch on, but it does suggest the wait wi= ll be significant. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.50.29.6 with SMTP id f6mr5146616igh.2.1425073598081; Fri, 27 Feb 2015 13:46:38 -0800 (PST) X-Received: by 10.50.72.37 with SMTP id a5mr120782igv.9.1425073598004; Fri, 27 Feb 2015 13:46:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!hl2no34595309igb.0!news-out.google.com!qk8ni43055igc.0!nntp.google.com!hl2no28217588igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Feb 2015 13:46:37 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 27 Feb 2015 21:46:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: mx02.eternal-september.org comp.lang.vhdl:8112 On Friday, February 27, 2015 at 11:51:37 AM UTC-8, KJ wrote: > On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > > [0020] If the coding system becomes new part of HDL standards all > > synthesizer manufactures will automatically be forced to implement all = well- > > known wave-pipelining algorithms and techniques within their products, = a=20 > > competition will start for better implementations, making wave-pipelini= ng=20 > > technique available to every digital designer in HDL. > >=20 > A couple of problems with your assumptions: > - No standard body will accept a patent burdened idea to incorporate into= a new revision of a standard. You would likely have to effectively surren= der your patent rights (should they be granted in the first place) in order= to get this to happen. I don't have experience with it and will do some research on it. > - If you think that simply being part of a standard will force synthesis = vendors to do anything at all, you're very mistaken. It's not my business. I invent something and let others do their part. As I= often see Jim calling for help to do something with new standard implement= ations from manufacturers. > - Wave pipelining has not caught on with FPGA suppliers in the 45 years s= ince the concept was first introduced nor in the 16 years since Burleson's = paper was published so uptake on the technique has not been very quick. Th= at doesn't imply that it will never catch on, but it does suggest the wait = will be significant. You are right. In 2002 I published a paper "HDL code inefficient sourses an= d its solutions", introducing 5 keywords "orif, elsor, errels, machine and = exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/2009,= according to Jim's comment, that takes 6 years to become standards. Weng >=20 > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.236.4.100 with SMTP id 64mr17298047yhi.43.1425119004342; Sat, 28 Feb 2015 02:23:24 -0800 (PST) X-Received: by 10.140.86.85 with SMTP id o79mr79996qgd.36.1425119004296; Sat, 28 Feb 2015 02:23:24 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i13no9993769qae.0!news-out.google.com!c1ni203qar.1!nntp.google.com!i13no9993767qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Feb 2015 02:23:24 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Subject: PSL help please From: niv Injection-Date: Sat, 28 Feb 2015 10:23:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 90 Xref: mx02.eternal-september.org comp.lang.vhdl:8113 How do I write PSL assertion for the following code? The idea is that if I/p sig is active for a certain time (number of clock cycles), an o/p is permanently set: Here's some noddy code for the idea: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.NUMERIC_STD.ALL; ENTITY limit_resp IS PORT( clk : IN STD_LOGIC; rst : IN STD_LOGIC; stim_1 : IN STD_LOGIC; resp_1 : OUT STD_LOGIC ); END ENTITY limit_resp ; -- ARCHITECTURE rtl OF limit_resp IS SIGNAL clk_enable : STD_LOGIC; SIGNAL clk_en_cntr : UNSIGNED(3 DOWNTO 0); SIGNAL counter : UNSIGNED(7 DOWNTO 0); BEGIN -------------------------------------------------------------------------------- -- Generate a clock enable signal at 1/10 clock rate. -------------------------------------------------------------------------------- clk_en_gen:PROCESS(rst, clk) BEGIN IF rst = '1' THEN clk_enable <= '0'; clk_en_cntr <= TO_UNSIGNED(0,4); ELSIF rising_edge(clk) THEN IF clk_en_cntr = TO_UNSIGNED(9,4) THEN clk_enable <= '1'; clk_en_cntr <= TO_UNSIGNED(0,4); ELSE clk_enable <= '0'; clk_en_cntr <= clk_en_cntr + 1; END IF; END IF; END PROCESS clk_en_gen; -------------------------------------------------------------------------------- -- Count up to some arbitrary value (for this test) -------------------------------------------------------------------------------- count_up:PROCESS(rst, clk) BEGIN IF rst = '1' THEN counter <= TO_UNSIGNED(0,8); ELSIF rising_edge(clk) THEN IF clk_enable = '1' THEN IF stim_1 = '1' THEN IF counter < 200 THEN counter <= counter + 1; END IF; ELSE counter <= TO_UNSIGNED(0,8); END IF; END IF; END IF; END PROCESS count_up; -------------------------------------------------------------------------------- -- If counter has maxed out, set the output high (forever, unless master reset) -- i.e. if the counter ever reaches its max (200) then the output is set, -- regardless of whether the input stim subsequently is removed. -------------------------------------------------------------------------------- set_output:PROCESS(rst, clk) BEGIN IF rst = '1' THEN resp_1 <= '0'; ELSIF rising_edge(clk) THEN IF counter = 200 THEN resp_1 <= '1'; END IF; END IF; END PROCESS set_output; -------------------------------------------------------------------------------- -- Now include a PSL assertion to test the following; -- -- If stim is set for "N" clock cycles (or more) (2000 in this example), -- then the "resp" output is set. -- HELP REQUIRED FOR THE BELOW PLEASE! -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- psl begin -- default clock is rising_edge(clk); -- -- -- end -------------------------------------------------------------------------------- END ARCHITECTURE rtl; Regards, Niv From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.70.42.170 with SMTP id p10mr21456252pdl.3.1425209556057; Sun, 01 Mar 2015 03:32:36 -0800 (PST) X-Received: by 10.50.25.202 with SMTP id e10mr210949igg.4.1425209555915; Sun, 01 Mar 2015 03:32:35 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no1775695igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no1775692igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 03:32:35 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=14.139.181.229; posting-account=KO-KNwkAAADC2mbnvzGpph7FQxwtXLlX NNTP-Posting-Host: 14.139.181.229 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> Subject: How different is the synthesized results of for loop and for generate? From: Deepak kumar Singhaniya Injection-Date: Sun, 01 Mar 2015 11:32:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8114 Hi, Why is it that only concurrent statements are allowed to use within for generate? I want to understand the difference between for loop and for generate so that I can be aware of what I will synthesizing. From newsfish@newsfish Tue Dec 29 16:43:44 2015 X-Received: by 10.182.96.131 with SMTP id ds3mr21611232obb.35.1425233151288; Sun, 01 Mar 2015 10:05:51 -0800 (PST) X-Received: by 10.140.36.134 with SMTP id p6mr309308qgp.26.1425233151140; Sun, 01 Mar 2015 10:05:51 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no2006950igb.0!news-out.google.com!c1ni203qar.1!nntp.google.com!i13no10668394qae.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 10:05:50 -0800 (PST) In-Reply-To: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL help please From: Leonardo Capossio Injection-Date: Sun, 01 Mar 2015 18:05:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: mx02.eternal-september.org comp.lang.vhdl:8115 Using ModelSim embedded PSL syntax: --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; then assert the property: --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.66.252.138 with SMTP id zs10mr24656691pac.3.1425255767427; Sun, 01 Mar 2015 16:22:47 -0800 (PST) X-Received: by 10.50.239.165 with SMTP id vt5mr232847igc.5.1425255767224; Sun, 01 Mar 2015 16:22:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no1921480igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2216357igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 16:22:46 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 02 Mar 2015 00:22:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2802 X-Received-Body-CRC: 822894985 Xref: mx02.eternal-september.org comp.lang.vhdl:8116 On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wrote: > You are right. In 2002 I published a paper "HDL code inefficient sourses = and its solutions", introducing 5 keywords "orif, elsor, errels, machine an= d exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/200= 9, according to Jim's comment, that takes 6 years to become standards. None of those are reserved words in IEEE Std 1076-2008 (published in 2009). See Issue Report 2012 http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt VASG-ISAC Recommendation for IEEE Std 1076-2002 ----------------------------------------------- No change. VASG-ISAC Recommendation for Future Revisions --------------------------------------------- Forward the submitter's request to the VHDL-200x Modeling and Productivity group for consideration. You'd be hard pressed to find any record that a 'VHDL-200x Modeling and Productivity group' considered your issue. This would have been under the = auspices of Accellera's VHDL activities and all those records are not avail= able today. There is a Unique Condition proposal encompassing IR2012: http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition It doesn't appear to be currently gaining a lot of traction. Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords the= re either. (Note there is unique and unique0). (See Annex B Keywords) From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.66.171.9 with SMTP id aq9mr25902721pac.20.1425273093824; Sun, 01 Mar 2015 21:11:33 -0800 (PST) X-Received: by 10.50.1.113 with SMTP id 17mr244657igl.8.1425273093622; Sun, 01 Mar 2015 21:11:33 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no1964410igb.0!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2317018igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 1 Mar 2015 21:11:33 -0800 (PST) In-Reply-To: <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 05:11:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8117 On Sunday, March 1, 2015 at 4:22:50 PM UTC-8, diog...@gmail.com wrote: > On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wrot= e: >=20 > > You are right. In 2002 I published a paper "HDL code inefficient sourse= s and its solutions", introducing 5 keywords "orif, elsor, errels, machine = and exclusive", and they are incorporated into Verilog-2008 and VHDL-2008/2= 009, according to Jim's comment, that takes 6 years to become standards. >=20 > None of those are reserved words in IEEE Std 1076-2008 (published in 2009= ). >=20 > See Issue Report 2012 > http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt >=20 > VASG-ISAC Recommendation for IEEE Std 1076-2002 > ----------------------------------------------- >=20 > No change. >=20 >=20 > VASG-ISAC Recommendation for Future Revisions > --------------------------------------------- >=20 > Forward the submitter's request to the VHDL-200x Modeling and > Productivity group for consideration. >=20 > You'd be hard pressed to find any record that a 'VHDL-200x Modeling and > Productivity group' considered your issue. This would have been under th= e auspices of Accellera's VHDL activities and all those records are not ava= ilable today. >=20 > There is a Unique Condition proposal encompassing IR2012: > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition >=20 > It doesn't appear to be currently gaining a lot of traction. >=20 > Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords t= here either. (Note there is unique and unique0). (See Annex B Keywords) Thank you for your valuable comment. Jim, the current chairman of VHDL committee, told me the information. I will response to you comment a few days later and hope to make some contr= ibutions to SystemVerilog-2012. Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.182.29.3 with SMTP id f3mr29214254obh.16.1425325757767; Mon, 02 Mar 2015 11:49:17 -0800 (PST) X-Received: by 10.50.127.232 with SMTP id nj8mr316724igb.0.1425325757566; Mon, 02 Mar 2015 11:49:17 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2305321igb.0!news-out.google.com!db6ni40239igc.0!nntp.google.com!hl2no2305319igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 11:49:16 -0800 (PST) In-Reply-To: <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 19:49:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 15459 X-Received-Body-CRC: 1550594812 Xref: mx02.eternal-september.org comp.lang.vhdl:8118 On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: > On Sunday, March 1, 2015 at 4:22:50 PM UTC-8, diog...@gmail.com wrote: > > On Saturday, February 28, 2015 at 10:46:43 AM UTC+13, Weng Tianxiang wr= ote: > >=20 > > > You are right. In 2002 I published a paper "HDL code inefficient sour= ses and its solutions", introducing 5 keywords "orif, elsor, errels, machin= e and exclusive", and they are incorporated into Verilog-2008 and VHDL-2008= /2009, according to Jim's comment, that takes 6 years to become standards. > >=20 > > None of those are reserved words in IEEE Std 1076-2008 (published in 20= 09). > >=20 > > See Issue Report 2012 > > http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > >=20 > > VASG-ISAC Recommendation for IEEE Std 1076-2002 > > ----------------------------------------------- > >=20 > > No change. > >=20 > >=20 > > VASG-ISAC Recommendation for Future Revisions > > --------------------------------------------- > >=20 > > Forward the submitter's request to the VHDL-200x Modeling and > > Productivity group for consideration. > >=20 > > You'd be hard pressed to find any record that a 'VHDL-200x Modeling and > > Productivity group' considered your issue. This would have been under = the auspices of Accellera's VHDL activities and all those records are not a= vailable today. > >=20 > > There is a Unique Condition proposal encompassing IR2012: > > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > >=20 > > It doesn't appear to be currently gaining a lot of traction. > >=20 > > Searching IEEE std 1800-2012 (SystemVerilog) shows they aren't keywords= there either. (Note there is unique and unique0). (See Annex B Keywords) >=20 > Thank you for your valuable comment. >=20 > Jim, the current chairman of VHDL committee, told me the information. >=20 > I will response to you comment a few days later and hope to make some con= tributions to SystemVerilog-2012. >=20 > Weng Thank you very much for your comment. 0. I don't have any written versions of Verilog-2008 or VHDL-2008/2009. The information I listed in my comment was based on Jim Lewis's comment, th= e chairman of current VHDL committee.=20 His comment happened in about 2010 and I cannot find it again now. But you = may see the following comments: https://groups.google.com/forum/#!topic/comp.lang.vhdl/V1ZeRkQ-El4 1. "This would have been under the auspices of Accellera's VHDL activities = and all those records are not available today.? You are right. Jim Lewis is the current chairman of Accellera's VHDL and th= e first man mentioned reserved word "errels". 2. "None of those are reserved words in IEEE Std 1076-2008 (published in 20= 09)." It must be the situation that those reserved words mentioned in my paper we= re incorporated into IEEE Std 1076-2008 (published in 2009) using different= names. I was not contacted in their incorporation activities. Jim Lewis wi= ll clear that later. 3. "See Issue Report 2012 http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt" This request was made by me in 2001. It doesn't mean anything now, because = it occurred in 2002 and we are talking about Verilog-2008 and VHDL-2008/200= 9. 4. In http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition=20 Current Situation section clearly describes the situation and what the targ= et is, but the application range is narrowed unintentionally: "In those above 3 situations, a superfluous condition is posed on the equat= ion; it means a priority tree is implied in all three situations. Actually = most of time when dealing with main data flow, all above conditions are mut= ually exclusive, so there is no need to pose the extra conditions on the fi= nal equation." The above situation occurs not only in main data flow, but also occurs when= dealing with logic flow in a non-clocked state machine process. 5. There are two errors in section of Implementation:=20 "The proposed solution is to introduce a new keyword 'elsor', which implies= that the conditions are mutually exclusive. The keyword would have to be u= sed throughout the statement, and imply that all the conditions are mutuall= y exclusive. The question of checking whether none of the conditions have b= een met can be handled by an assertion.? 5.1. New keyword "elsor" can be nested, and has not to be used throughou= t the statement. In page 169 of The 11th Annual International HDL Conference, the paper "HDL= Code Inefficiency Sources and its Solutions" describes: "To make HDL code efficient, we should have a way to let HDL compilers know= if there are any partially or totally mutually exclusive conditions contai= ned in "if...elsif...else" statement. The solution is to include two new keywords"orif" and "elsor" in the next H= DL version. "orif" is used in sequential environments and "elsor" in concur= rent environments. Proposal 1: In sequential situations, any "elsif" keyword in "if...elsif...= else" statement may be replaced by new keyword "orif", specifying that cond= itions at any contiguous block of "orif(...)" lines and the condition at "i= f(...)" or "elsif(...) line that is located above the contiguous block of "= orif(...)" lines are mutually exclusive.=20 And a new keyword "errels" can be added after last "orif(...)" line of any = contiguous "orif(...)" blocks to specify what action should be taken when v= iolations of expecting mutually exclusive conditions occur during simulatio= n. All other rules appled to "if...elsif...else" don't change. Example: A : process(clk, nreset) begin if nreset =3D '0' then=20 Outbus <=3D (others=3D>'0'); =20 elsif clk'event and clk =3D '1' then if C1 then -- C1 and C2 are mutually exclusive Outbus <=3D Bus1; orif C2 then Outbus <=3D Bus2; errels -- if both C1 and C2 are true, an error oc= curs Outbus <=3D Outbus ; assert false report "1: mutually exclusive is violated" severity note; elsif C3 then -- C3 and C4 are mutually exclusive Outbus <=3D Bus3; orif C4 then Outbus <=3D Bus4; errels -- if both C3 and C4 are true, an error oc= curs Outbus <=3D Outbus ; assert false report "2: mutually exclusive is violated" severity note; else Outbus <=3D (others=3D>'0'); end if; end if; end process; The above equation tells that (C1 and C2), (C3 and C4) are mutually exclusi= ve. The following equation in AHDL is expected: Outbus <=3D (C1 * Bus1 + C2 * Bus2) + !(C1 + C2) (C3 * Bus3 + C4 * Bus4)= ; The new keyword "orif" is to emphasize that "or" operations are involved to= save logic.=20 Statements following "errels" are skipped in synthesis, but are involved in= simulation. 5.2 =E6=8F=9Fhe question of checking whether none of the conditions have be= en met can be handled by an assertion.? I don=E6=8A=B0 know SystemVerilog, but the above question can be handled= without any additional rules and it can be handled as an usual =E6=90=83f= =E5=8D=90lsif=E5=8D=90lse?does. If one contiguous block of "orif" and its above "if(...)" or "elsif(...)= " is treated as one if-level in a "if...elsif...else" statement, nothing sh= ould have changed. Please see following examples. 5.3. In the above conetext "The 'unique' keyword implies an error if none o= f the conditions is met and there is no 'else', whereas the 'unique0' keywo= rd does not imply this additional check." When no conditions are true in the mutually exclusive group, the situati= on is treated in the same way as how a usual "if...elsif...else" is treated= , but when more than one condition in a mutually exclusive group of conditi= ons is true, an error occurs, that can be detected using "elserr".=20 OneHot0(...) really has the bad effects as the recommendation indicated. 6. Here I give a very useful example showing how the new keyword "orif" is = used and how it would save logic in my unpublished code: If an idle state in a state machine State_2 is monitoring a data bus to = see if the command target address appeared in the bus falls into a designat= ed address space, the code would be: case State_2 is when Idle_s =3D> if Address =3D Area1 then State_2_NS <=3D S1; elsif Address =3D Area2 then State_2_NS <=3D S2; elsif Address =3D Area3 then State_2_NS <=3D S3; elsif Address =3D Area4 then State_2_NS <=3D S4; elsif Address =3D Area5 then State_2_NS <=3D S5; else State_2_NS <=3D Idle_s; end if; =20 end if; ... No experienced designers would write the above dumb code. Because each o= f area addresses can be written as a 32-bits address or so and rewrite the = equation to make them do no more logic comparison than needed. case State_2 is when Idle_s =3D> if Address_H8 =3D Common_address_H8 then case Address_L24 is when Address_L24_1 =3D> State_2_NS <=3D S1; when Address_L24_2 =3D> State_2_NS <=3D S2; when Address_L24_3 =3D> State_2_NS <=3D S3; when Address_L24_4 =3D> State_2_NS <=3D S4; when Address_L24_5 =3D> State_2_NS <=3D S5; when others =3D> State_2_NS <=3D Idle_s; end case; end if; ... =20 Now my problem comes here due to the jump conditions which are mutually exc= lusive and cannot be divided as above example shows. In one state machine State_1 it generates 7 situations which are generated = in one if-statement and mutually exclusive and very complex. In another state machine State_2 it is waiting in idle state to monitor the= progress of State_1 and acts when one of 7 situations occurs. The situations are very common in complex designs. case State_2 is when Idle_S =3D> If situation_1 then State_2_NS <=3D S2_1; elsif situation_2 then State_2_NS <=3D S2_2; elsif situation_3 then State_2_NS <=3D S2_3; elsif situation_4 then State_2_NS <=3D S2_4; elsif situation_5 then State_2_NS <=3D S2_5; elsif situation_6 then State_2_NS <=3D S2_6; elsif situation_7 then State_2_NS <=3D S2_7; else State_2_NS <=3D Idle_S; end if; The above code is unacceptable because all situation_x are mutually exclusi= vely generated in one if-statement in State_1 state machine. What I can do now in State_1 is as follows: code <=3D "000"; -- no action if A1 then code<=3D "001"; -- situation_1 else A2 then -- situation_2 code<=3D "010"; elsif A3 then if A4 then -- situation_3 code<=3D "011"; else A5 then -- situation_4 code<=3D "101"; ... In State_2 I have to use a case statement to simplify the situations as fol= lowing code shows: case State_2 is when Idle_s =3D> case code is when "001" =3D> ...; -- situation_1 when "010" =3D> ...; -- situation_2 when "011" =3D> ...; -- situation_3 when others =3D>Idle_s;-- no action If new keyword "orif" is introduced as my specification tells, the new code= in State_1 would be: situation_1 <=3D '0"; -- situation_1 situation_2 <=3D '0"; -- situation_2 situation_3 <=3D '0"; -- situation_3 situation_4 <=3D '0"; -- situation_4 situation_5 <=3D '0"; -- situation_5 situation_6 <=3D '0"; -- situation_6 situation_7 <=3D '0"; -- situation_7 =20 if A1 then situation_1 <=3D '1"; -- situation_1 else A2 then =20 situation_2 <=3D '1"; -- situation_2 elsif A3 then if A4 then =20 situation_3 <=3D '1"; -- situation_3 else A5 then =20 situation_4 <=3D '1"; -- situation_4 ... =20 the code in State_2 would be: case State_2 is when Idle_s =3D> if situatino_1 =3D '1' then State_2_NS <=3D S1; -- situation_1 orif situatino_2 =3D '1' then State_2_NS <=3D S2; -- situation_2 orif situatino_3 =3D '1' then State_2_NS <=3D S3; -- situation_3 orif situatino_4 =3D '1' then State_2_NS <=3D S4; -- situation_4 orif situatino_5 =3D '1' then State_2_NS <=3D S5; -- situation_5 orif situatino_6 =3D '1' then State_2_NS <=3D S6; -- situation_6 orif situatino_7 =3D '1' then State_2_NS <=3D S7; -- situation_7 errels -- if more than one wire is assert= ed State_2_NS <=3D Idle_s; -- keep State_2 unchanged assert false =20 report "Violation of mutually exclusiveness occurs" severity failure; -- that is what should be done if no condition is true in a contiguous bloc= k of "orif" else =20 State_2_NS <=3D Idle_s; -- keep State_2 unchanged end if; ... =20 =20 Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.68.104.5 with SMTP id ga5mr27953996pbb.2.1425327469331; Mon, 02 Mar 2015 12:17:49 -0800 (PST) X-Received: by 10.140.32.34 with SMTP id g31mr43610qgg.21.1425327469053; Mon, 02 Mar 2015 12:17:49 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2858256igb.0!news-out.google.com!n6ni190qar.0!nntp.google.com!j7no10324956qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 12:17:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Mon, 02 Mar 2015 20:17:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2236 X-Received-Body-CRC: 2996557782 Xref: mx02.eternal-september.org comp.lang.vhdl:8119 On Monday, March 2, 2015 at 2:49:26 PM UTC-5, Weng Tianxiang wrote: > On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: It looks like you submitted this back in 2001 but the suggestion was not re= commended for a change to VHDL-2002 (http://www.eda.org/isac/IRs-VHDL-2002/= IR2012.txt). It did not make the cut in VHDL-2008 either. Along with any other open proposals, it has been ported over to the current= working group for consideration (http://www.eda.org/twiki/bin/view.cgi/P10= 76/UniqueCondition). That working group has been together for just about 3= years, it's not clear if there is any particular target date that they are= working toward. Kevin From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.140.231.139 with SMTP id b133mr28881090qhc.1.1425340120421; Mon, 02 Mar 2015 15:48:40 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr336696igb.10.1425340120129; Mon, 02 Mar 2015 15:48:40 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!j7no10369646qaq.1!news-out.google.com!qk8ni45613igc.0!nntp.google.com!hl2no2976871igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Mar 2015 15:48:39 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <2143d8be-196b-4474-a9d0-168b0179e6bc@googlegroups.com> <70c1ed92-0ff2-47dc-85e4-8f02d8b46fbc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <97ac969d-1424-44ad-9635-00a15bb055cc@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 02 Mar 2015 23:48:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 37 Xref: mx02.eternal-september.org comp.lang.vhdl:8120 On Monday, March 2, 2015 at 12:17:52 PM UTC-8, KJ wrote: > On Monday, March 2, 2015 at 2:49:26 PM UTC-5, Weng Tianxiang wrote: > > On Sunday, March 1, 2015 at 9:11:36 PM UTC-8, Weng Tianxiang wrote: >=20 > It looks like you submitted this back in 2001 but the suggestion was not = recommended for a change to VHDL-2002 (http://www.eda.org/isac/IRs-VHDL-200= 2/IR2012.txt). You are right. >=20 > It did not make the cut in VHDL-2008 either. No, it did make the cut in Verilog-2008 for both groups of new keywords and= in VHDL-2008/2009 for either. Jim Lewis provided me with the info in 2010 or 2011, but I couldn't find hi= s record. I will try again.=20 =20 >=20 > Along with any other open proposals, it has been ported over to the curre= nt working group for consideration (http://www.eda.org/twiki/bin/view.cgi/P= 1076/UniqueCondition). That working group has been together for just about= 3 years, it's not clear if there is any particular target date that they a= re working toward. You are right. I am very thankful for this SystemVerilog-1012 group. I will= try to publish a paper that will definitely confirm using schematics diagr= ams that "orif" saves logic in such a dramatic way as I claimed. >=20 > Kevin Hi KJ, Thank you for your comment. Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!lightspeed.eweka.nl!lightspeed.eweka.nl!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!npeersf04.am4!fx34.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150302-2, 02/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 23 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425376487 86.17.210.161 (Tue, 03 Mar 2015 09:54:47 UTC) NNTP-Posting-Date: Tue, 03 Mar 2015 09:54:47 UTC Organization: virginmedia.com Date: Tue, 03 Mar 2015 09:54:46 +0000 X-Received-Body-CRC: 2688360251 X-Received-Bytes: 2114 Xref: mx02.eternal-september.org comp.lang.vhdl:8121 On 01/03/2015 18:05, Leonardo Capossio wrote: > Using ModelSim embedded PSL syntax: > > --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; > > then assert the property: > > --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; > > If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. > > Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. > I think the lecturer wants the student to learn about writing bad assertions hence he specifically asked to check for 2000 clock cycles. The counter is the obvious choice but you might not always be aware of what is available in the code. I am not going to give the answer as this is clearly homework. I give kudos to the University (tech college?) for teaching PSL, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.42.163.8 with SMTP id a8mr2498509icy.2.1425407911901; Tue, 03 Mar 2015 10:38:31 -0800 (PST) X-Received: by 10.140.37.113 with SMTP id q104mr7646qgq.0.1425407911731; Tue, 03 Mar 2015 10:38:31 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3521917igb.0!news-out.google.com!c1ni204qar.1!nntp.google.com!j7no10581444qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 10:38:31 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Subject: Re: PSL help please From: niv Injection-Date: Tue, 03 Mar 2015 18:38:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2902 X-Received-Body-CRC: 2513481031 Xref: mx02.eternal-september.org comp.lang.vhdl:8122 On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: > On 01/03/2015 18:05, Leonardo Capossio wrote: > > Using ModelSim embedded PSL syntax: > > > > --PSL property resp_check is always( {counter = 200} |=> {resp_1} ) abort rst; > > > > then assert the property: > > > > --PSL assert_resp_check: assert resp_check report "resp_1 is not working!!!"; > > > > If you are using VHDL-2008 PSL probably syntax would be a little different, never investigated this. > > > > Use this as a starting point, I haven't used PSL in a while, and even if I have, verification also needs debugging. > > > I think the lecturer wants the student to learn about writing bad > assertions hence he specifically asked to check for 2000 clock cycles. > The counter is the obvious choice but you might not always be aware of > what is available in the code. I am not going to give the answer as > this is clearly homework. > > I give kudos to the University (tech college?) for teaching PSL, > > Hans > www.ht-lab.com Not homework (other than self imposed)! I've been VHDL coding for ~25 years, but just started to grapple with PSL. Bought Cindy Eisner book, which I've started to read & creating my own examples to test myself. So, Leonardo answer worked, sort of, but I've changed the code so the resp_1 o/p is also clocked when clk_enable is '1', so this has caused a set of 9(?) assertion failures between counter = 200 & resp_1 going high. I tried this, which worked, but seems a bit too like the source code? -- property RESP_01 is -- ({counter = 200 AND clk_enable = '1'} |=> {resp_1} abort rst); -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at count max"; -- Any suggestions welcome! From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.66.119.132 with SMTP id ku4mr372723pab.7.1425408892712; Tue, 03 Mar 2015 10:54:52 -0800 (PST) X-Received: by 10.140.84.213 with SMTP id l79mr6777qgd.41.1425408892591; Tue, 03 Mar 2015 10:54:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no3534394igb.0!news-out.google.com!n6ni192qar.0!nntp.google.com!w8no195147qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 10:54:52 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.244.219.43; posting-account=EoIP4wkAAAChC0vnU72BDebYgCW_Wydn NNTP-Posting-Host: 195.244.219.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55b616fb-0f1b-4d15-aed9-add49c8552b6@googlegroups.com> Subject: PEZZO DI MERDA SCHIFOSO TIZIANO RENZI (WIKI, IL FATTO QUOTIDIANO ECT)! FA DA TRAMITE FRA STRAGISTA NAZIMAFIOSO PEDOFILO SILVIO BERLUSCONI, FASCIOLESBICA MARINA BERLUSCONI E FIGLIO BERLUS-CO-RROTTO MATTEO RENZI PER FAR SI CHE RENZUSCONIA WD NEVER DIE! From: Dieffe Ventitre Injection-Date: Tue, 03 Mar 2015 18:54:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 240 Xref: mx02.eternal-september.org comp.lang.vhdl:8123 PEZZO DI MERDA SCHIFOSO TIZIANO RENZI (WIKI, IL FATTO QUOTIDIANO ECT)! FA D= A TRAMITE FRA STRAGISTA NAZIMAFIOSO PEDOFILO SILVIO BERLUSCONI, FASCIOLESBI= CA MARINA BERLUSCONI E FIGLIO BERLUS-CO-RROTTO MATTEO RENZI PER FAR SI CHE = RENZUSCONIA WD NEVER DIE! =20 COLERICISSIMO TOPO DI FOGNA DAVIDE SERRA DI ALGEBRIS E TWITTER HA RICEVUTO,= ANZI, HA LUI STESSO ARCHITETTATO ( COSA MOLTISSIMO PIU=B4 GRAVE) L'INSIDER= TRADING SULLE BANCHE POPOLARI BECCATO DAL BASTARDO DITTATORE BERLUS-CO-RRO= TTISSIMO MATTEO RENZI ( UNITO ALLA BAGASCIONA BERLUS-CO-RROTTISSIMA MARIA E= LENA BOSCHI, ED IL, DI QUEST=B4ULTIMA, DELINQUENTE PADRE, NOTO MEGA RICICLA= SOLDI MAFIOSI: PIER LUIGI BOSCHI DI AREZZO E BANCA ETRURIA). ED HA PURE RA= GLIATO CHE COMPRA BANCHE POPOLARI " BEN" DAL MARZO 2014. SPUTTANANDOSI ANCO= RA DI PIU', COME UN IMBECILLE, COME UN PEDERASTA SODOMIZZA BAMBINI IN TANZA= NIA, COME UN MEGA COCAINOMANE, QUALE DA SEMPRE, STO LERCISSIMO COLLETTO DI = DAVIDE SERRA, DA SEMPRE, E'. NON PER NIENTE... IL SUO CESSO STECCATISSIMO M= ATTEO RENZI (CHE VIA "SS", SPINTA E STECCHE DI SILVIO BERLUSCONI E DAVIDE S= ERRA, HA SCIPPATO SEGRETERIA PD E PALAZZO CHIGI, NEL SECONDO CASO COL FEBBR= AIO 2014), HA RICEVUTO DA STO PORCO HITLERIANO DI ALGEBRIS, INDICAZIONI, AN= ZI, ASSOLUTISSIMI ORDINI, SU COME RIFORMARE LE POPOLARI. NEL FEBBRAIO 2014 = STESSO. "OVVISSIMAMENTE", DETTO IMMENSO PAPPA TANGENTI DI MATTEO RENZI HA O= BBEDITO AGLI ORDINI ( IMMENSO PAPPA TANGENTI DI MATTEO RENZI, FIGLIO DI MOS= TRUOSISSIMAMENTE BASTARDO, LADRO, TRUFFATORE TIZIANO RENZI, NOTO IN TUTTA T= OSCANA COME " IL BANCAROTTIERE FRAUDOLENTO DI SATANA"). E PER QUESTO, STO T= OPASTRO DI FOGNA NAZISTA, ANZI, STO TOPASTRO DI FOG-NA-ZISTA DI DAVIDE SER= RA DI TWITTER ED ALGEBRIS, SI E' MESSO A COMPRARE BANCHE POPOLARI, OHIBO', = GUARDA CASO, DAL MARZO 2014. UN MESE DOPO LO SCIPPO FASCIOCAMORRISTA DI MAT= TEO RENZI DI PALAZZO CHIGI (ULLALA' CHE COINCIDENZA, ULLALA'). INSIDER ARCH= ITETTATO DAL NUOVO BERNARD MADOFF, OSSIA DAVIDE SERRA, IN PIENISSIMO, E'!!!= TRATTASI DI MANDRIA DI PORCI FASCIOCAMORRISTI, TIPO, ANCHE, NOTO AVANZO D= I GALERA PAOLO BARRAI (DI CRIMINALISSIMA WMO, CRIMINALISSIMA BSI ITALIA SRL= DI VIA SOCRATE 26 MILANO E CRIMINALISSIMA BLOG MERCATO "MERDATO"LIBERO), C= HE SI FINGONO DEL PD, X... DISTRUGGERLO, INFILTRARLO A MORTE, RENDERLO DIAR= REA BERLUSCONICCHIA! VOGLIAMO UNA ACCESISSIMA E VINCENTISSIMA REVOLUCIOOOOO= ON! VOGLIAMO IL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, FALLITO E= D IN GALERA! SUBITO! PLS, DOTTOR SERGIO MATTARELLA, CI DIA UNA MANO! IN ONO= RE A SUO FRATELLO UCCISO DA COSA NOSTRA ( COSA NOSTRA CHE QUANDO SI METTE L= A FASCISTISSIMA CRAVATTA DOLCE E GABBANA, SIGNIFICA SILVIO BERLUSCONI, DAVI= DE SERRA E PAOLO BARRAI, GLIELO POSSO, NON SOLO ASSICURARE, MA ANCHE PROVAR= E). IN ONORE AD ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO, FATTI SPAPPOLAR= E, SICURISSIMAMENTE, DA SILVIO BERLUSCONI, VIA, A SUA VOLTA, BERLUSCONIANIS= SIMA MAFIA! ED OLTRE A VOLER SILVIO BERLUSCONI FALLITO ED IN GALERA, VOGLIA= MO VEDERE IL SUO PICCIOTTO INCRAVATTATO, IL FACCENDIERE DI BERLUSCONAZISTI,= PADANAZISTI, E CRIMINALITA' ORGANIZZATE DI MEZZO MONDO, PAOLO BARRAI DI MA= LAVITOSA WMO, PURE, IN GALERA! VOGLIAMO IL NUOVO GIANCARLO LANDE, IL NUOVO = BERNARD MADOFF, IL NUOVO MICHELE SINDONA, VERME CRIMINALISSIMO DAVIDE SERRA= DI TWITTER ED ALGEBRIS, FALLITO, E PER LO MENO, PER QUALCHE MESE, IN GALER= A! CHE SIA ETICISSSIMA E VINCENTISSIMA REVOLUCIOOOOON! COME DA OTTIMO SITO INFORMARE X RESISTERE: http://www.informarexresistere.fr/2015/01/27/qualcuno-sapeva-in-anticipo-ch= e-il-governo-avrebbe-varato-un-provvedimento-sulle-banche-popolari-enormi-s= peculazioni/ =20 COME DA CORRIERE DELLA SERA, DI, OTTIMAMENTE, ANTIRENZUSCONIANO FERRUCCI= O DE BORTOLI, UOMO DA NON TOCCARE E A TUTTI I COSTI: http://www.corriere.it/economia/15_gennaio_24/quei-movimenti-un-po-sospetti= -popolari-f59ffb1c-a3a5-11e4-808e-442fa7f91611.shtml =20 Acquisti consistenti prima della riforma che ha abolito il voto capitari= o. La famiglia Boschi ha sicurissimamente passato insider trading a Londra,= tramite noto ladro, truffatore, nazifascista, immensamente ricicla soldi m= afiosi, che affatto va' in Tanzania a fare del bene, in quanto vi va' a ric= iclare cash di (sua) LL Lega Ladrona, come per suoi gusti sessuali di tipo = depravatissimo: avanzo di galera Davide Serra di Algebris e Twitter ( che a= nzi, di stra certo, ha architettato la suddetta "mafia sulle Banche Popolar= i", gia=B4dal Febbraio 2014, dall=B4inizio della topaia a Palazzo Chigi, ch= iamata, non Governo Renzi, ma Governo Renzusconi). Ci chiediamo ora: dove p= renderanno, le mazzette, i vermi nazifascisti Pier Luigi Boschi di Banca Et= ruria e sua zoccolona ( di fatto) Berlusconicchia Maria Elena Boschi ( bast= arda puttanazista che vuole sgozzare la giustizia via estremissimamente ing= iusta salvaberlusconi http://www.blitzquotidiano.it/rassegna-stampa/libero-= renzi-per-fare-la-pace-offre-la-salva-berlusconi-che-fara-mattarella-209049= 1/ .... che qui, non per niente, slingua=20 http://www.corriere.it/methode_image/2014/08/08/Politica/Foto%20Politica%20= -%20Trattate/6ebdfe07bdd8cb1fe88af8343f8a5b1c-012-kXsC-U43030145012273wcB-5= 93x443@Corriere-Web-Sezioni.jpg?v=3D20140808175213 un topo di fogna corrotto, ndranghetista, fascista, estortore di soldi alla= Banca Popolare di Lodi .. pezzo di merda criminalissimo Paolo Romani: http://www.repubblica.it/2005/l/sezioni/economia/banche21/ipolitici/ipoliti= ci.html )? A) Alle Bahamas B) Alle Bermuda C) A Panama D) Ad Hong Kong E) A Singapore F) Alle Mauritius ( "roba" tipo Svizzera e' da anni 70, 80: stile nazim= afioso pedofilo Silvio Berlusconi e suo B-o-ttino Craxi.. dai.. please) Lauti premi a chi azzecca per primo!!! --- BRAVO, BRAVO, DAVVERO BRAVISSIMO ELIO LANNUTTI A QUERELARE STO VERME BERLU= S-CORROTTTISSIMO DI MATTEO RENZI: http://www.ilfattoquotidiano.it/2015/01/21/denuncia-per-renzi/1357263/ CHE SBEFFEGGIA PM PER BENE, EROICI, SALVA NAZIONE ( SPESSO SPAPPOLATI, = COME IL NAZIMAFIOSO PEDOFILO STRAGISTA SILVIO BERLUSCONI FECE FARE CON GLI = ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO.. SILVIO BERLUSCONI, PROPRIO IL = POR-CO-RRUTTORE MAXIMO DI MATTEO RENZI... ULLALA=B4CHE COINCIDENZINA, ULLAL= A=B4). TIPO QUELLI DI PALERMO, BARI, MILANO, NAPOLI, DICENDO, ANZI, RAGLIAN= DO LORO: "'OOOO OO CHE PAURA, MI FANNO, OO OO" http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-pau= ra-sciopero-sindacati-polizia-illegale/295911/ CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE = FRA POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO = RENZI! https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-di-= me-il-2-febbraio-carmelo-lopapa/ "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERL= USCONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA= BLOCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGL= I ULTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNE= R, FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVR= EBBERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU MI ASSICURI= LA NOCCIOLINA DI BEN 50 MILIONI DI EURO DI SCONTO, VIA MILLE-STECCATISSIME= -PROROGHE" http://www.affaritaliani.it/economia/milleproroghe-sfratti-frequ= enze-tv170215.html "IO TI VOTO LE RIFORME DI AUGUSTO PINOCHET CHE VUOI IMPO= RRE, TU METTI AL QUIRINALE UN FANTOCCIO DI MIA PROPRIETA', CHE COMPRO QUAND= O VOGLIO QUALE GIULIANO AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... O MEG= LIO ANCORA, SE PARLIAMO DI MIEI FASCIOBAMBOCCI ALLA PIERFERDINANDO CASINI O= GIANNI LETTA... TUTTI MIEI PUPAZZI CHE MI HAN GIA' GARANTITO CHE CON SEI E= URO E MEZZO CASH, MI FIRMEREBBERO TUTTE LE GRAZIE CHE VOGLIO IN NOME DELLA = MIA.... PACIFICAZIONE ALLA VASELLINA... E ... SPECIALMENTE ...GIUSTO PER AN= DARE SUL SICURO.... MI FAI ANCHE E SUBITO UNA NORMINA DECAPITANTE NOIOSISSI= MI CONCETTI COME DEMOCRAZIA E GIUSTIZIA CHE IMPONGA IL MIO TORNARE IN POLIT= ICA, COSI' CHE POSSA FOTTERE IL POPOLO CIUCCIO, LE LEGGI, DOZZINE DI (GRAND= ISSIMI) MAGISTRATI COME ILDA BOCASSINI, EDMONDO BRUTI LIBERATI, NINO DI MAT= TEO, ROBERTO SCARPINATO, FABIO DE PASQUALE, HENRY WOODCOCK, PASQUALE DRAGO,= ATTRAVERSO LA ( BASTARDAMENTE VIGLIACCHISSIMA) IMMUNITA' EVITA GALERA, CHE= MI RI RITROVEREI"! http://www.ilfattoquotidiano.it/2015/01/18/salva-berlusconi-alessandro-pace= -manina-renzi-reato-falso/1349562/ http://www.ilfattoquotidiano.it/2015/01/08/salva-berlusconi-mucchetti-renzi= -venga-senato-spiegare-successo/1322595/ http://www.ilfattoquotidiano.it/2015/01/06/salva-berlusconi-coppi-ammette-q= uella-norma-segnale-per-quirinale/1318110/ IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERLUSCON= IANISSIME) CHE STAI APPRONTANDO, TU MI FAI PAPPARE RAI WAY E TELECOM, COSI= =B4CHE POSSA CONTROLLARE CHIUNQUE NON MI LECCHI IL DI DIETRO, DISTRUGGENDOG= LI LA VITA ( VEDI DISARTICOLAZIONI CON MEZZI TRAMAUTICI, ALIAS, SPESSO, ASS= ASSINI http://comuni.it/servizi/forumbb/viewtopic.php?p=3D539677 http://www.antimafiaduemila.com/200712201537/terzo-millennio/terzo-millenni= o-anno-vid-numero-5-2006-nd51/pezzi-eversivi-di-uno-stato-a-pezzi.html http://freeforumzone.leonardo.it/lofi/SERVIZIETTI-POCO-SEGRETI-MARCO-TRAVAG= LIO-/D5676425.html ) E SPECIALMENTE, POSSA CONTROLLARE TUTTE LE INTERCETTAZIONI AMBIENTALI E TEL= EFONICHE DEI PM, E QUINDI, SGOZZARE, STILE BERLUSCONIANISSIME ISIS ED AL QA= EDA, LA GIUSTIZIA. INFATTI, GIA=B4AI TEMPI, I PORCORROTTI GIULIANO TAVAROLI= ED EMANUELE CIPRIANI, STUPRAVANO A MORTE, LA DEMOCRAZIA, PER ME, SILVIO BE= RLUSCONI, PIU=B4CHE PER MARCO TRONCHETTI PROVERA. CHI CONTROLLA LE TELEFONA= TE, E=B4DA SEMPRE, IL NUOVO DUCE, E IO, SILVIO BERLUSCONI, LO SONO, NEL MIO= PAESE, ED ORMAI, DA QUASI MEZZO SECOLO"!!! ECCO DOVE CI PORTANO BASTARDI LAVA CASH MAFIOSO A GO GO COME I MALAVITO= SINCRAVATTATI DAVIDE SERRA DI ALGEBRIS E TWITTER INSIEME AL RENATO VALLANZA= SCA UNITO AD UGO FANTOZZI DELLA FINANZA, NOTO AVANZO DI GALERA, GIA=B4VARIE= VOLTE IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965, DI CRIMINALISSI= MO WMO, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO E CRIMINALIS= SIMO BLOG MERCATO "MERDATO" LIBERO ( DUE VERMI REPELLENTI CHE RICICLANO ALL= 'ESTERO VAGONI DI SOLDI DI COSA NOSTRA, CAMORRA, NDRANGHETA O LADRATI SE NO= N PURE FRUTTO DI MEGA MAZZETTE IN DIREZIONE LL LEGA LADRONA ED EX PDL POPOL= O DI LADRONI; IN CONGIUNZIONE CON BANCHIERI DELINQUENTISSIMI, SPESSO PURE M= ANDANTI DI OMICIDI O "SUICIDATE", COME FATTO CON DAVID ROSSI DI MONTE PASCH= I, QUALI GLI ASSASSINI ENNIO DORIS E MASSIMO DORIS DI BANCA MEDIOLANUM; O Q= UALE "O MASSONE CAMORRISTA" GIUSEPPE SABATO DI BANCA ESPERIA E GRAN LOGGIA = MASSONICA ITALIANA http://www.gruppoesperia.it/chi-siamo/giuseppe-sabato.html https://books.google.it/books?id=3DB1mEj0GtktIC&pg=3DPT304&lpg=3DPT304&dq= =3DGIUSEPPE+SABATO+LICIO+GELLI&source=3Dbl&ots=3DGqtu0KYRmD&sig=3Dd2TOz9sZD= Y6563zIPxwnNYcbxb4&hl=3Dit&sa=3DX&ei=3DI-i_VOOsBMLlUonCgZgI&ved=3D0CFMQ6AEw= CA#v=3Donepage&q=3DGIUSEPPE%20SABATO%20LICIO%20GELLI&f=3Dfalse TUTTI DEL GRUPPO MA-F-INIVEST DI " STEFANO BONTATE, MARCELLO DELL'UTRI,= TOTO RIINA, LICIO GELLI, BERNARDO PROVENZANO E SILVIO BERLUSCONI: " OO CHE= CASO, OO")! E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STEC= CATISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE = MICHELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER = PROTEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROT= TIERE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA = SODOMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOL= O CIUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE CON LATTE A= LLA BOCCA: MATTEO RENZI! http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_ren= zie.html https://www.youtube.com/watch?v=3DA7Ngp6JrK9A http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-paga= ti-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375 CHE VIA ASSASSINE MASSONERIE NAZIFASCISTE, VER E PROPRIE MASSONAZISTERIE,= =20 FA DA TRAMITE FRA LO STRAGISTA NAZIMAFIOSO PEDOFILO SILVIO BERLUSCONI, LA F= ASCIOLESBICA MARINA BERLUSCONI E SUO FIGLIO BERLUS-CO-RROTTISSIMO MATTEO RE= NZI, PER FAR SI CHE BERLUSCONIA WOULD NEVER DIE! http://www.dagospia.com/rubrica-3/politica/mascherina-ti-conosco-dopo-aver-= fatto-contro-pelu-renzi-76510.htm http://www.laretenonperdona.it/2013/06/16/cause-e-fallimenti-aziendali-i-da= nni-di-papa-renzi/ http://www.huffingtonpost.it/news/renzi-boy-scout-licio-gelli/ http://www.ilfattoquotidiano.it/2014/12/21/tiziano-renzi-i-pm-interrogano-p= adre-premier-indagato-per-bancarotta/1285579/ http://micheledisalvo.com/tutti-gli-amici-di-matteo-renzi.html http://www.affaritaliani.it/cronache/renzi-e-i-legami-con-la-massoneria0210= 14.html =20 VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE, QU= ELLO ANTI MAFIA NAZIFASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E = SEL! A FARE IL SUO VERO LAVORO, OSSIA LA ZOCCOLA DI STRADA, STA BATTONA HIT= LERIANA, CHE SI CREDE MODELLA MA E' CESSO STRA COLMO DI CELLULITE, DI MARIA= ELENA BOSCHI http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-b= ikini-rosa-in-spiaggia-a-marina-di-pietrasanta-581617_tn.jpg FIGLIA DI ALT= RO VERME CRIMINALISSIMO: MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA= ETRURIA (DOPO AVER PASSATO TUTTA UNA VITA A TRAFFICARE CON COOP VICINISSIM= E A MAFIA, CAMORRA E NDRANGHETA, NON PER NIENTE, STILE "RENZUSCONIANISSIMI"= SALVATORE BUZZI E MASSIMO CARMINATI). PS SEMPRE VINCENTISSIMI I GENI BORSI= STICI GEORGE SOROS E MICHELE NISTA A PUNTARE SULLA SPAGNA. PARREBBE CHE DOP= O AVER SAPUTO CHE IL MIGLIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NI= STA, VEDA NON MALE LA SPAGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO,= MANCO FOSSERO NOCCIOLINE, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI= BANCO SANTANDER. NON SARA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON= LO E' ALCUN PAESE DEL PIANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE= NON MANCANO ( MA SONO AL MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA= DI RENZUSCONIA)! PERO', NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI V= I E' DEMOCRAZIA VERA. SIA AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMET= TENTISSIMO PABLO IGLESIAS DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRO= NA DI MADRID, VERMI STRAGISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERL= USCONI, CHE SI FAN LE LEGGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLT= RE CHE PER SGOZZARE A MORTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. E QUESTO, = O IN PROPRIO, O COMPRANDOSI RAGAZZINI CORROTTISSIMI CHIAMANTISI MATTEO, COM= E MATTEO RENZI (OGGI). O IL NUOVO ADOLF HITLER: MATTEO SALVINI (DOMANI). ME= NTRE L'UNICO PADRONE, L'UNICO VERO BOSS DEL CANCROMICIDA DEL MONDO INTERO, = SILVIO BERLUSCONI, UN ALTRO MATTEO, MATTEO MESSINA DENARO, SORRIDE E DICE "= BRAVO MIO PRESTANOME BEDDU SILVIO BERLUSCONI, HAI TRASFORMATO L'ITALIA IN = RENZUSCONIA, CHE IN REALTA' SEMPRE BERLUSCONIA E', AAAAAAA... COME PIACE A = MMMIA, AAAA.... E' TUTTO UNA COSA NOSTRA, SILVIUZZEDDU BEDDU .. CONTINUA CO= SI' CHE TI TROVIAMO QUALCHE ALTRA BEDDA PROSTITUTA DI 12-14 ANNI PELLU TEMP= U LIBERO, AAAAA.... QUESTA VOLTA CAMBIAMO, AAAA... TE LA TROVIAMO FILIPPINA= E LA FACCIAMO PASSARE PER LA NIPOTE DEL RE DELLA THAILANDIA, BHUMIBOL ADUL= YADEJ, IL RE PIU' RICCO DEL MONDO ... CHE SPESSO E VOLENTIERI "ABOLISCE UFF= ICIALISSIMAMENTE LA DEMOCRAZIA"... SI... SILVIUZZEDDU BEDDU DA COSA NOSTRA,= TI TROVIAMO UNA BAMBINA FILIPPINA DI 12 ANNI DA SBAVARE E TOCCARE QUANTO V= UOI... E LA FACCIAMO PASSARE PER LA NIPOTE THAILANDESE DI BHUMIBOL ADULYADE= J, AAAA.... COSI' VEDRAI CHE QUANDO TELEFONI, PREOCCUPATISSIMO, DA PARIGI (= TANTO, FRA POCO, NELLA TUA DITTATURA DELLE BANANAS DI RENZUSCONIA, SUBITO,= IL PASSAPORTO, TI RIDARANNO), I POLIZIOTTI O QUESTORI, SOLO E SEMPRE LA TU= A VOLONTA', FARANNO, AAA"!!! From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.182.96.131 with SMTP id ds3mr1735944obb.35.1425428068354; Tue, 03 Mar 2015 16:14:28 -0800 (PST) X-Received: by 10.140.81.229 with SMTP id f92mr32218qgd.28.1425428068250; Tue, 03 Mar 2015 16:14:28 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no3700892igb.0!news-out.google.com!c1ni204qar.1!nntp.google.com!j7no10666969qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 16:14:28 -0800 (PST) In-Reply-To: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.150.32.12; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 83.150.32.12 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL help please From: Leonardo Capossio Injection-Date: Wed, 04 Mar 2015 00:14:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8124 El martes, 3 de marzo de 2015, 15:38:35 (UTC-3), niv escribi=F3: > On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: > > On 01/03/2015 18:05, Leonardo Capossio wrote: > > > Using ModelSim embedded PSL syntax: > > > > > > --PSL property resp_check is always( {counter =3D 200} |=3D> {resp_1}= ) abort rst; > > > > > > then assert the property: > > > > > > --PSL assert_resp_check: assert resp_check report "resp_1 is not work= ing!!!"; > > > > > > If you are using VHDL-2008 PSL probably syntax would be a little diff= erent, never investigated this. > > > > > > Use this as a starting point, I haven't used PSL in a while, and even= if I have, verification also needs debugging. > > > > > I think the lecturer wants the student to learn about writing bad=20 > > assertions hence he specifically asked to check for 2000 clock cycles.= =20 > > The counter is the obvious choice but you might not always be aware of= =20 > > what is available in the code. I am not going to give the answer as=20 > > this is clearly homework. > >=20 > > I give kudos to the University (tech college?) for teaching PSL, > >=20 > > Hans > > www.ht-lab.com >=20 > Not homework (other than self imposed)! > I've been VHDL coding for ~25 years, but just started to grapple with PSL= . > Bought Cindy Eisner book, which I've started to read & creating my own ex= amples to test myself. >=20 > So, Leonardo answer worked, sort of,=20 > but I've changed the code so the resp_1 o/p is also clocked when clk_enab= le is '1', so this has caused a set of 9(?) assertion failures between coun= ter =3D 200 & resp_1 going high. >=20 > I tried this, which worked, but seems a bit too like the source code? >=20 > -- property RESP_01 is > -- ({counter =3D 200 AND clk_enable =3D '1'} |=3D> {resp_1} abort rst= ); > -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at coun= t max"; > -- >=20 >=20 > Any suggestions welcome! Well, you can use that, it is simple, but PSL has many ways of doing the sa= me thing, and in this case some may be more 'correct' than others. Following Hans suggestion, you might not be able to access the counter (you= might want to do this PSL stuff from outside, hence only being able to acc= ess ports), so PSL provides a way for you to check for a condition that may= run in continuous clock cycles or not, for example you could do: --PSL property resp_check is always( {clk_enable[=3D200]} |=3D> {clk_enable= [=3D1]} |-> {resp_1} ) abort rst; The condition part of the implication is that the clock enable is sampled h= igh exactly 200 times every rising edge, and this times CAN be non-consecut= ive (in non-consecutive clock cycles, for them to be consecutive use [*200]= ). Then on the next clock cycle if clk_enable is HIGH exactly one cycle, th= en resp_1 must go HIGH, IN THE SAME CLOCK CYCLE. Try if it works, see this tutorial for more help: http://www.project-veripa= ge.com/psl_tutorial_6.php From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.182.33.97 with SMTP id q1mr2199389obi.42.1425432306863; Tue, 03 Mar 2015 17:25:06 -0800 (PST) X-Received: by 10.50.112.194 with SMTP id is2mr477497igb.2.1425432306768; Tue, 03 Mar 2015 17:25:06 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no3727889igb.0!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3727886igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 17:25:06 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=208.13.76.142; posting-account=S61AnQkAAADt4_PSYpI-Tm-z1E4cd7xa NNTP-Posting-Host: 208.13.76.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cfc5822-d51b-456a-8a5d-1669c22b6fad@googlegroups.com> Subject: run-time path instance attribute? From: David Rogoff Injection-Date: Wed, 04 Mar 2015 01:25:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 X-Received-Bytes: 2194 X-Received-Body-CRC: 1839135175 Xref: mx02.eternal-september.org comp.lang.vhdl:8125 Hi all. More VHDL learning curve. I'm trying to copy some SystemVerilog verificati= on code I did a couple of years ago but I'm stuck. I want to report and/or= act based on the hierarchical instance of a procedure. I thought I could = use the 'instance_name attribute but that only statically determined and ju= st tells me the package name where I defined the procedure - not what I wan= t. How do I extra the hierarchical path during run-time? I thought of a way t= o do it using generics but I'd have to rewrite dozens of nested procedures = and functions to plumb a path string down. Not gonna happen. Thanks! David ps - I did find some handy string manipulation in VHDL 2008 (e.g. to_string= (time:) ). I also wrote an slv to string function that adds underscores ev= ery 4 digits to make long numbers readable. I'm working on a similar func= tion that takes a real and outputs a string with commas every 3 digits to t= he left and right of the decimal point. Don't suppose someone already has = this? Extra points for Euro input to swap "." and "," :) From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.182.248.227 with SMTP id yp3mr2880495obc.22.1425442012840; Tue, 03 Mar 2015 20:06:52 -0800 (PST) X-Received: by 10.182.97.200 with SMTP id ec8mr22353obb.20.1425442012744; Tue, 03 Mar 2015 20:06:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no2912083igb.0!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3780135igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 20:06:52 -0800 (PST) In-Reply-To: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <722555e0-c905-4a95-ae89-7fdba680a470@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76619e15-8eed-4ea8-959d-0bf62201d63a@googlegroups.com> Subject: Re: How different is the synthesized results of for loop and for generate? From: Andy Injection-Date: Wed, 04 Mar 2015 04:06:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1971 X-Received-Body-CRC: 3882658202 Xref: mx02.eternal-september.org comp.lang.vhdl:8126 A generate is statically bound. A for loop is dynamically bound. They are different structures for different purposes than the sequential if/loop statements, though similar logic can be described using either one. You can use a variable in a for-loop for iterative behavior (updating the same variable over multiple iterations of the loop, such as when calculating parity of an SLV). In synthesis, both are "unrolled" and therefore the loop/generate index is treated as static (i.e. a constant) for each iteration. Note also that a generate statement can contain a declarative region where signals, types, constants, etc. unique to each iteration can be declared. I tend to use for-generate in structural code (e.g. instantiating N copies of an entity), and for-loop in behavioral code (TB or RTL). Andy From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.28.230 with SMTP id g66mr3003659yha.2.1425446804277; Tue, 03 Mar 2015 21:26:44 -0800 (PST) X-Received: by 10.50.118.42 with SMTP id kj10mr130743igb.9.1425446804091; Tue, 03 Mar 2015 21:26:44 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no23147qaq.1!news-out.google.com!qk8ni48798igc.0!nntp.google.com!hl2no3807233igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 21:26:42 -0800 (PST) In-Reply-To: <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Wed, 04 Mar 2015 05:26:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 13061 X-Received-Body-CRC: 659939989 Xref: mx02.eternal-september.org comp.lang.vhdl:8127 On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrote: > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote: > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > >=20 > > I have filed a provisional patent application: "Systematic method of co= ding wave pipelined circuits in HDL". If it is proved correct, the patent w= ill introduce 1 keyword, 3 permanent constants, 1 concurrent statement and = four source code modules for a new library in HDL and thoroughly resolve a = pending problem so that every digital designer can code wave-pipelined circ= uits in HDL. > >=20 > > Here is the abstract of the invention: > >=20 > > The present invention classifies all critical paths into two basic = types: a series critical path and a feedback critical path, and divides eac= h of wave-pipelined circuits into two components: a static logic part, call= ed critical path component (CPC), and a dynamic logic part, formalized into= four wave-pipelining components (WPC) shared by all wave-pipelined circuit= s. Each wave-pipelining ready code in HDL comprises two components: a WPC i= nstantiation and a CPC instantiation wire-connected and linked by a new lin= k statement. Each WPC has new wave constants which play the same role as ge= neric constants do, but whose initial values are determined and assigned by= a synthesizer after code analysis, so designers can use after-synthesizati= on information in their code before synthesization for wave-pipelining tech= nology. The responsibility of analyzing and manipulating wave-pipelining re= ady code, generating and implementing wave-pipelined circuits on a design-w= ide or chip-wide scale in HDL is shifted from designers to synthesizers. > >=20 > > Anyone who are interested in its content is welcome to send a email req= uest to the following email address: wtx wtx @ gmail . com with title "Syst= ematic" and he will receive the full documents: one specification, 9 drawin= gs and one text file in VHDL. > >=20 > > If one reviews the files and feels that it would be a good thing to rec= ommend the application to his company to buy it, the first person to do it = after his recommended company does so will receive $10,000 commission fee. > >=20 > > Thank you. > >=20 > > Weng >=20 > Hi, > I want to add some introductions to what the wave-pipelined circuits are = and their status. >=20 > [0003] A synchronous digital system contains a lot of registers. Valid= data flow through successive registers from system input registers to syst= em output registers. All data flows are synchronous with triggering edges o= f a chip clock. For example, data flow from registers A to registers B, fro= m registers B to registers C and so on in a successive order on the same cl= ock cycle. > [0004] A path in a synchronous digital system is a route between any n= eighboring registers connected by combinational logic. If the target runnin= g frequency for a digital design is predetermined, the upper limit of propa= gating time for any paths is determined and has the inverse value of the ta= rget running frequency. A path is called a critical path if the time signal= s take to propagate through it is beyond the predetermined propagating time= , and the time is called the path's critical time. If there are any critica= l paths, digital designers must spend time reducing all critical times by a= ll means and eliminating all critical paths to meet the target running freq= uency. > [0005] Wave-pipelining is a technology which completes an operation th= at needs several clock cycles to propagate without intermediate registers a= nd with input data acceptable on every clock cycle. For example, in a conve= ntional pipelining operation, data flow from registers A to registers D thr= ough registers B and C to divide the critical path time into multiple small= er intervals to meet the critical time: A to B to C to D; with wave-pipelin= ing, data flow through registers A and D without intermediate registers B a= nd C. Absolutely, wave-pipelining will reduce logic resource usage and is s= uperior to the conventional pipelining technology if it can be used. >=20 > Here are the most important inequalities involving wave-pipelining from p= aper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burleson= et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no. 3= , pp. 464-474, Sep. 1998. >=20 > [0018] Currently many memory chip manufacturers successfully use wave-= pipelining in their memory chip products with higher rate outputs, reduced = power consumption and logic resources; and a few scientists use FPGA chips = as a base to show some circuits can be done with wave-pipelining in isolate= d environments. Their works prove that the wave-pipelining is a very powerf= ul tool to reduce power consumption and logic resources. Now there are two = major existing obstacles preventing any ordinary digital designers from usi= ng the wave-pipelining in HDL: > * The software algorithms making wave-pipelining successful, like Wong an= d Klass algorithms and others, have already been developed and matured, but= ordinary digital designers have no means or resources to access to the tec= hnology, because there are no international HDL standards on how synthesize= r manufacturers incorporate those capabilities into their products. > * HDL needs the capabilities for digital designers to write wave-pipelini= ng ready code for any number of critical paths on a design-wide or chip-wid= e scale instead of in an isolated environment and the written code can be i= dentified, synthesized and used to generate wave-pipelined circuits by any = synthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 > [0019] The target of the present invention is: > * Invent a wave-pipelining coding system as new part of HDL standards for= designers to write wave-pipelining ready code which can be identified, syn= thesized and used to generate wave-pipelined circuits by any synthesizer in= ASIC or FPGA. > * Make wave-pipelining ready code written based on the coding system work= ing with no extra logic generated, compared with independently written wave= -pipelined circuits, and with no code changes when switching from non-wave-= pipelined mode to wave-pipelined mode or vice verse if all of wave-pipelini= ng ready code meet wave-pipelining requirements.=20 > * Shift burdens of analyzing and manipulating wave-pipelining ready code,= generating and implementing wave-pipelined circuits on a design-wide or ch= ip-wide scale in HDL from individual designers to synthesizer manufacturers= . > [0020] If the coding system becomes new part of HDL standards all synt= hesizer manufactures will automatically be forced to implement all well-kno= wn wave-pipelining algorithms and techniques within their products, a compe= tition will start for better implementations, making wave-pipelining techni= que available to every digital designer in HDL. >=20 > Weng Here I add some contents of the invention: Main idea behind the present invention [0057] The most difficult part coding all types of wave-pipelined circui= ts on a design-wide scale in HDL is that a wave-pipelined circuit code alwa= ys comprises two logic parts:=20 * A static logic part: it doesn't change if the number of series clock cycl= es through the circuit changes and is unique for each of wave-pipelined cir= cuits. * A dynamic logic part: it does change if the number of series clock cycles= through the circuit changes and is the same for one of groups of wave-pipe= lined circuits. [0058] Every wave-pipelined circuit has its own change rules and those c= hanges are unknown to designers when they are writing code and will be know= n to a synthesizer only after it has analyzed the circuit. [0059] The present invention classifies all critical paths into two basi= c types: a series critical path and a feedback critical path, and divides e= ach of wave-pipelined circuits into two components: one is static logic par= t and called critical path component (CPC); another is dynamic logic part a= nd formalized into four wave-pipelining components (WPC) shared by all wave= -pipelined circuits. Under the present invention each of standard wave-pipe= lining ready code in HDL comprises two components: a WPC instantiation and = a CPC instantiation which are wire-connected and linked by a new concurrent= link statement. Each of four WPC embodiments has a group of new type wave = constant, which plays the same role as a generic constant does, but whose i= nitial value is determined and assigned by a synthesizer after it has analy= zed the linked CPC component under slow mode and target mode, respectively,= so designers can use after-synthesization information in their code before= synthesization in HDL for wave-pipelining technology. Following the instru= ctions of the present invention creates a situation that digital designers = can write wave-pipelining ready code in HDL and the responsibility of analy= zing and manipulating wave-pipelining ready code, generating and implementi= ng wave-pipelined circuits on a design-wide or chip-wide scale in HDL is sh= ifted from individual designers to synthesizer manufacturers. How the method works [0060] The systematic method of coding wave-pipelined circuits in HDL co= mprises following ten parts: 1. Define five signals, one counter, one switch and one table that will be = used when generating wave-pipelined circuits on a design-wide or chip-wide = scale in HDL. 2. Define the interfaces of a CPC each of which encapsulates a critical pat= h's static logic part. 3. Define and implement four WPC embodiments in HDL each of which is a crit= ical path's dynamic logic part: a series_module, an input_delay_module, a m= ultiple_copy_module1 and a multiple_copy_module2. 4. Define one new keyword wave and three new wave constants which provide a= means to dynamically transfer after-synthesization information to designer= s' code before synthesization. 5. Define the methods of determining and searching for wave constant values= of a known WPC instantiation under slow mode and target mode, respectively= . 6. Define three versions of a concurrent link statement: link1, link2 and l= ink3, and rules on how they are used. 7. Define the pairing rules between a WPC and a CPC. 8. Define how a digital designer prepares wave-pipelining ready code system= atically. 9. Shift the responsibility of analyzing and manipulating wave-pipelining r= eady code, generating and implementing wave-pipelined circuits on a design-= wide or chip-wide scale in HDL from individual designers to synthesizer man= ufacturers. 10. Define how four WPC embodiments are simulated and debugged under any of= current versions of a synthesizer in HDL. [0061] It is fair to put the burden of successfully generating wave-pipe= lined circuits based on wave-pipelining ready code squarely on synthesizer = manufacturers' shoulder if all necessary information is passed to a synthes= izer. For example, with tens of papers claiming that successful wave-pipeli= ned circuits are implemented in FPGA chips in an isolated environment, it i= s the responsibility of FPGA synthesizers to be capable of generating those= wave-pipelined circuits in a design-wide environment without designers' fu= rther involvements, a process similar for them to the task of generating a = circuit with the highest running frequency and minimum used resources if po= ssible for any normal digital design code. Thank you for your reading. From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.26.179 with SMTP id c39mr3313167yha.27.1425455260336; Tue, 03 Mar 2015 23:47:40 -0800 (PST) X-Received: by 10.140.84.213 with SMTP id l79mr43543qgd.41.1425455260258; Tue, 03 Mar 2015 23:47:40 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no49377qaq.1!news-out.google.com!c1ni205qar.1!nntp.google.com!k15no49373qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Mar 2015 23:47:40 -0800 (PST) In-Reply-To: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: hssig Injection-Date: Wed, 04 Mar 2015 07:47:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8128 Aaah, the "VHDL hater" is back ;-) From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.63.42 with SMTP id z30mr3373226yhc.37.1425458317384; Wed, 04 Mar 2015 00:38:37 -0800 (PST) X-Received: by 10.50.43.234 with SMTP id z10mr140235igl.8.1425458317254; Wed, 04 Mar 2015 00:38:37 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no62007qaq.1!news-out.google.com!db6ni40239igc.0!nntp.google.com!hl2no2981511igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 00:38:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=202.62.65.48; posting-account=x4WE3QoAAACvybfiq0gf93gqOYCxol97 NNTP-Posting-Host: 202.62.65.48 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Subject: c-language to VHDL converter From: Sai Jaswanth Injection-Date: Wed, 04 Mar 2015 08:38:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8129 hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.50.23.75 with SMTP id k11mr5765097igf.3.1425460518093; Wed, 04 Mar 2015 01:15:18 -0800 (PST) X-Received: by 10.140.108.182 with SMTP id j51mr52994qgf.24.1425460517920; Wed, 04 Mar 2015 01:15:17 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no2992477igb.0!news-out.google.com!n6ni192qar.0!nntp.google.com!w8no375585qac.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 01:15:17 -0800 (PST) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a37e343-8d49-4394-8de3-23e18a676e59@googlegroups.com> Subject: Re: c-language to VHDL converter From: hssig Injection-Date: Wed, 04 Mar 2015 09:15:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8130 In Vivado you can (HLS) From newsfish@newsfish Tue Dec 29 16:43:45 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx46.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: c-language to VHDL converter References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150303-1, 03/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425467364 86.17.210.161 (Wed, 04 Mar 2015 11:09:24 UTC) NNTP-Posting-Date: Wed, 04 Mar 2015 11:09:24 UTC Organization: virginmedia.com Date: Wed, 04 Mar 2015 11:09:23 +0000 X-Received-Body-CRC: 747208525 X-Received-Bytes: 1394 Xref: mx02.eternal-september.org comp.lang.vhdl:8131 On 04/03/2015 08:38, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? > Hi Sai, Check out Hercules: http://www.nkavvadias.com/hercules/ You could also try Xilinx HLS, Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:45 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx04.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PSL help please References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> In-Reply-To: <1d0c613e-b660-44a9-b7ae-f2386ea4ebcd@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150303-1, 03/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 51 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1425468423 86.17.210.161 (Wed, 04 Mar 2015 11:27:03 UTC) NNTP-Posting-Date: Wed, 04 Mar 2015 11:27:03 UTC Organization: virginmedia.com Date: Wed, 04 Mar 2015 11:27:02 +0000 X-Received-Body-CRC: 1238012365 X-Received-Bytes: 2996 Xref: mx02.eternal-september.org comp.lang.vhdl:8132 On 03/03/2015 18:38, niv wrote: Hi Niv, > On Tuesday, March 3, 2015 at 9:54:53 AM UTC, HT-Lab wrote: ..snip > > Not homework (other than self imposed)! That is good! PSL is amazingly powerful language especially on a formal tool. > I've been VHDL coding for ~25 years, but just started to grapple with PSL. > Bought Cindy Eisner book, which I've started to read & creating my own examples to test myself. > > So, Leonardo answer worked, sort of, > but I've changed the code so the resp_1 o/p is also clocked when clk_enable is '1', so this has caused a set of 9(?) assertion failures between counter = 200 & resp_1 going high. > > I tried this, which worked, but seems a bit too like the source code? > > -- property RESP_01 is > -- ({counter = 200 AND clk_enable = '1'} |=> {resp_1} abort rst); > -- assert always RESP_01 report "ERROR: resp_1 did not go to '1' at count max"; > -- > > > Any suggestions welcome! Leonardo already gave you some good advice, however, watch out for the consecutive repeat [*n] operator as you could end up with a lot of assertion threads (when part of the LHS becomes valid your simulator will spawn a new thread, in Modelsim these are the blue blocks). A possible (but untested) better solution could be the goto repetition [->] operator. Some general comments, watch out were you put your () brackets, the abort operator takes precedence. In your code you are aborting the RHS of your property. I would have aborted the whole property or directive to avoid wasting simulation cycles, example: always (..) abort rst; (always ..) abort rst; I would also use {resp_1='1'} just in case your variable goes to 'X'/'Z' etc. Good luck, Regards, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.140.151.75 with SMTP id 72mr4919705qhx.3.1425481563824; Wed, 04 Mar 2015 07:06:03 -0800 (PST) X-Received: by 10.50.112.194 with SMTP id is2mr534212igb.2.1425481563638; Wed, 04 Mar 2015 07:06:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!au2pb.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!k15no148671qaq.1!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4104656igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 07:06:03 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Wed, 04 Mar 2015 15:06:03 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3382 X-Received-Body-CRC: 1278390142 Xref: mx02.eternal-september.org comp.lang.vhdl:8133 On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > Aaah, the "VHDL hater" is back ;-) Hi HSSIG, Ha, Ha, Ha, Ha, you have a really good memory!!! The story happened 13 year= s ago!!! You must have attended the 11th International HDL conference held in Double= Tree hotel, San Jose=EF=BC=8CCA=EF=BC=8Cin March, 2002, and listened to my= presentation! When I was doing my presentation, a big laugh was burst when I said "I hate= VHDL, because it lacks the data grammar structure which can nicely handle = the mutually exclusive cases."=20 During the period I met great pressure to increase the running frequency fo= r a 66MHz PCI DMA board. How could I do it to increase the running frequenc= y to meet 66MHz requirement in VHDL from 23 MHz running frequency achieved = from an Altera chip? I hoped to get experts' help, but none touched and ans= wered my question. Finally I successfully finished the job and my design go= t 480 MByte/s on a maximum 528 MByte/s 66MHz PCI bus achieved through a Xil= inx chip.=20 Thank you for giving me the nickname "VHDL hater."=20 After my distributions of my paper in this and FPGA group, I received more = than 150 paper requests to get the article within 3 month period. Now I gladly know that even SystemVerilog, a HDL language Intel uses, lacks= the function, even SystemVerilog-2012 "doesn't appear to be currently gain= ing a lot of traction." =E2=80=9COne person's medicine, another one's fortune."=20 Now it give me a chance to make a fortune to publish another group of inven= tion-patents which had been finished at least 4 years ago and would schemat= ically and definitely show that new keyword "orif" and its data structure r= eally saves logic and it is really indispensable=EF=BC=8Cessential, necessa= ry, all-important, of the utmost importance, of the essence, vital, must-ha= ve, crucial, key, needed, required, requisite, imperative and invaluable. Thank you for your comment. Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.70.92.103 with SMTP id cl7mr7512252pdb.0.1425513283662; Wed, 04 Mar 2015 15:54:43 -0800 (PST) X-Received: by 10.182.65.169 with SMTP id y9mr75035obs.17.1425513283257; Wed, 04 Mar 2015 15:54:43 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!hl2no4416540igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416513igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:54:43 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Learn VHDL and FPGA! From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:54:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8134 Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.222.103 with SMTP id s97mr7478241yhp.19.1425513307916; Wed, 04 Mar 2015 15:55:07 -0800 (PST) X-Received: by 10.182.142.66 with SMTP id ru2mr73172obb.5.1425513307702; Wed, 04 Mar 2015 15:55:07 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!k15no294255qaq.1!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416746igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:07 -0800 (PST) In-Reply-To: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <7c89e56e-9caa-434a-a87e-78a40c011071@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <508dd711-754c-4ed7-bc7f-539b54dbeaab@googlegroups.com> Subject: Re: PSL help please From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8135 On Saturday, February 28, 2015 at 5:23:26 AM UTC-5, niv wrote: > How do I write PSL assertion for the following code? > The idea is that if I/p sig is active for a certain time (number of clock cycles), an o/p is permanently set: > > Here's some noddy code for the idea: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.NUMERIC_STD.ALL; > ENTITY limit_resp IS > PORT( > clk : IN STD_LOGIC; > rst : IN STD_LOGIC; > stim_1 : IN STD_LOGIC; > resp_1 : OUT STD_LOGIC > ); > END ENTITY limit_resp ; > -- > ARCHITECTURE rtl OF limit_resp IS > SIGNAL clk_enable : STD_LOGIC; > SIGNAL clk_en_cntr : UNSIGNED(3 DOWNTO 0); > SIGNAL counter : UNSIGNED(7 DOWNTO 0); > BEGIN > -------------------------------------------------------------------------------- > -- Generate a clock enable signal at 1/10 clock rate. > -------------------------------------------------------------------------------- > clk_en_gen:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > clk_enable <= '0'; > clk_en_cntr <= TO_UNSIGNED(0,4); > ELSIF rising_edge(clk) THEN > IF clk_en_cntr = TO_UNSIGNED(9,4) THEN > clk_enable <= '1'; > clk_en_cntr <= TO_UNSIGNED(0,4); > ELSE > clk_enable <= '0'; > clk_en_cntr <= clk_en_cntr + 1; > END IF; > END IF; > END PROCESS clk_en_gen; > -------------------------------------------------------------------------------- > -- Count up to some arbitrary value (for this test) > -------------------------------------------------------------------------------- > count_up:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > counter <= TO_UNSIGNED(0,8); > ELSIF rising_edge(clk) THEN > IF clk_enable = '1' THEN > IF stim_1 = '1' THEN > IF counter < 200 THEN > counter <= counter + 1; > END IF; > ELSE > counter <= TO_UNSIGNED(0,8); > END IF; > END IF; > END IF; > END PROCESS count_up; > -------------------------------------------------------------------------------- > -- If counter has maxed out, set the output high (forever, unless master reset) > -- i.e. if the counter ever reaches its max (200) then the output is set, > -- regardless of whether the input stim subsequently is removed. > -------------------------------------------------------------------------------- > set_output:PROCESS(rst, clk) > BEGIN > IF rst = '1' THEN > resp_1 <= '0'; > ELSIF rising_edge(clk) THEN > IF counter = 200 THEN > resp_1 <= '1'; > END IF; > END IF; > END PROCESS set_output; > -------------------------------------------------------------------------------- > -- Now include a PSL assertion to test the following; > -- > -- If stim is set for "N" clock cycles (or more) (2000 in this example), > -- then the "resp" output is set. > -- HELP REQUIRED FOR THE BELOW PLEASE! > -------------------------------------------------------------------------------- > -------------------------------------------------------------------------------- > -- psl begin > -- default clock is rising_edge(clk); > -- > -- > -- end > -------------------------------------------------------------------------------- > END ARCHITECTURE rtl; > > Regards, Niv Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.66.140.66 with SMTP id re2mr7522901pab.29.1425513327227; Wed, 04 Mar 2015 15:55:27 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76506obc.34.1425513326981; Wed, 04 Mar 2015 15:55:26 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4416825igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416819igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:26 -0800 (PST) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: c-language to VHDL converter From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8136 On Wednesday, March 4, 2015 at 3:38:38 AM UTC-5, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VHDL directly by any software. (or) can we compile C-code in xilinx IDE? Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.140.151.75 with SMTP id 72mr7453741qhx.3.1425513357322; Wed, 04 Mar 2015 15:55:57 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76519obc.34.1425513357120; Wed, 04 Mar 2015 15:55:57 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!w8no598045qac.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4416974igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:55:57 -0800 (PST) In-Reply-To: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43d0c6d9-716d-43ee-b3d2-8447950dea9a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:55:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8137 On Tuesday, February 24, 2015 at 12:09:40 PM UTC-5, Weng Tianxiang wrote: > Hi Jim, glen, JK, rickman, Mike, Andy,=20 >=20 > I have filed a provisional patent application: "Systematic method of codi= ng wave pipelined circuits in HDL". If it is proved correct, the patent wil= l introduce 1 keyword, 3 permanent constants, 1 concurrent statement and fo= ur source code modules for a new library in HDL and thoroughly resolve a pe= nding problem so that every digital designer can code wave-pipelined circui= ts in HDL. >=20 > Here is the abstract of the invention: >=20 > The present invention classifies all critical paths into two basic ty= pes: a series critical path and a feedback critical path, and divides each = of wave-pipelined circuits into two components: a static logic part, called= critical path component (CPC), and a dynamic logic part, formalized into f= our wave-pipelining components (WPC) shared by all wave-pipelined circuits.= Each wave-pipelining ready code in HDL comprises two components: a WPC ins= tantiation and a CPC instantiation wire-connected and linked by a new link = statement. Each WPC has new wave constants which play the same role as gene= ric constants do, but whose initial values are determined and assigned by a= synthesizer after code analysis, so designers can use after-synthesization= information in their code before synthesization for wave-pipelining techno= logy. The responsibility of analyzing and manipulating wave-pipelining read= y code, generating and implementing wave-pipelined circuits on a design-wid= e or chip-wide scale in HDL is shifted from designers to synthesizers. >=20 > Anyone who are interested in its content is welcome to send a email reque= st to the following email address: wtx wtx @ gmail . com with title "System= atic" and he will receive the full documents: one specification, 9 drawings= and one text file in VHDL. >=20 > If one reviews the files and feels that it would be a good thing to recom= mend the application to his company to buy it, the first person to do it af= ter his recommended company does so will receive $10,000 commission fee. >=20 > Thank you. >=20 > Weng Want to learn more in engineering? If you are interested in learning=20 VHDL programming and FPGA development take my course today! This coupon=20 is good till April 6th, 2015 for $60 - 40% off the cost of the class at=20 regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermedi= ates/?couponCode=3DMarch60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.70.131.81 with SMTP id ok17mr7496288pdb.6.1425513379889; Wed, 04 Mar 2015 15:56:19 -0800 (PST) X-Received: by 10.182.89.198 with SMTP id bq6mr76563obb.28.1425513379562; Wed, 04 Mar 2015 15:56:19 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no4417080igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4417076igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:56:19 -0800 (PST) In-Reply-To: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <622c3fc8-8a1c-46ae-9cc4-db0d9c842739@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Help with VHDL architecture From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:56:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2601 X-Received-Body-CRC: 4146377143 Xref: mx02.eternal-september.org comp.lang.vhdl:8138 On Friday, January 2, 2015 at 3:55:55 AM UTC-5, Olalekan Shittu wrote: > Hello everyone. > > I have been trying to write a VHDL architecture for the circuit below but doesn't seem to be making headway, can anyone be of help. > > Below is my entity declaration from the system > > Library ieee; > use IEEE.std_logic_1164.all; > > entity Sorter IS > Port ( C: IN std_logic_vector (0 to 3); > Sel: IN STD_LOGIC_VECTOR(0 to 2); > out0: out std_logic; > out1: out std_logic; > out2: out std_logic; > out3: out std_logic > ); > end sorter; > > I am to write an architecture for the above with condition that: > > When Sel equal 4, the resulting output as shown in the table below is generated > > out0 out1 out2 out3 > 0 <= C < 4 1 0 0 0 > > 4 <= C < 8 0 1 0 0 > > 8 <= C < 12 0 0 1 0 > > 12 <= C < 16 0 0 0 1 > > otherwise out0,out1,out2,out3 are all equal to zero. > > Thanks Want to learn more in engineering? If you are interested in learning VHDL programming and FPGA development take my course today! This coupon is good till April 6th, 2015 for $60 - 40% off the cost of the class at regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=March60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.42.209.135 with SMTP id gg7mr365865icb.9.1425513399206; Wed, 04 Mar 2015 15:56:39 -0800 (PST) X-Received: by 10.182.220.229 with SMTP id pz5mr76551obc.34.1425513398947; Wed, 04 Mar 2015 15:56:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4417279igb.0!news-out.google.com!db6ni44004igc.0!nntp.google.com!hl2no4417275igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 15:56:38 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cb65708-e019-48cb-9b10-bdc121c39877@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: jjchristman13@gmail.com Injection-Date: Wed, 04 Mar 2015 23:56:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8139 On Friday, January 9, 2015 at 8:09:03 AM UTC-5, johan.fa...@gmail.com wrote= : > a month ago I decided that I was lacking FPGA knowhow, said and done I or= dered an experiment board (beeing an opensource aficionado I ordered the Lo= gicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's= "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exam= ples: Spartan 3". My reasoning behind these two books is that I start with = Ashenden to learn the whole language then go to Pong to learn how to write = syntezisable VHDL, since both contain exercises they make for really good s= elf teaching material. I know Pong is targeting another experiment board bu= t it's the same FPGA and im very confident I can myself make adjustments, e= xcept for e.g. the PS2 port which my papilio thankfully does not have. >=20 > I have now started to search for what to do after these books, how do I g= et more advanced in my FPGA knowledge. I'm a software guy and if I got the = question "I want to start programming" from someone new to programming I wo= uld recomend a good starting book in python, then a good book on how to do = test driven design, then a book about patterns, then moving to C followed b= y a book about object oriented design, then perhaps going for a best practi= ce book and so on, by level of complexity and relevance. I have scoured the= internet (or feels like it) to find such a list regarding FPGA, but at no = luck so far, so thinking of posting the question here. >=20 > I have looked at three books for continued learning after I'm finished wi= th Pong >=20 > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aim= ed at explaining deeper the differences beetwen syntezisable and simulated = VHDL. Though it seem to go through the VHDL language constructs yet again p= erhaps it is too much overlapping with Pong and Ashenden >=20 > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; se= ems a good continuation, I understand that FSM is a very important topic in= HW world and that they are completely different from SW FSM, also it seem = to have excersises after each chapter which is good. >=20 > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabi= lity, and Scalability ; seems good, no more comments. >=20 > Thats my thinking, any suggestions or comments? Have not come about any b= ooks regarding FPGA testing? Perhaps I should look outside the more hands o= n book to one of the "meta" books out there? Want to learn more in engineering? If you are interested in learning=20 VHDL programming and FPGA development take my course today! This coupon=20 is good till April 6th, 2015 for $60 - 40% off the cost of the class at=20 regular price! Join now! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermedi= ates/?couponCode=3DMarch60#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.18.232 with SMTP id l68mr8177704yhl.16.1425528315295; Wed, 04 Mar 2015 20:05:15 -0800 (PST) X-Received: by 10.140.101.51 with SMTP id t48mr140681qge.10.1425528315249; Wed, 04 Mar 2015 20:05:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!k15no317895qaq.1!news-out.google.com!c1ni208qar.1!nntp.google.com!k15no317892qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 20:05:15 -0800 (PST) In-Reply-To: <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f19d:6431:41a6:faec; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f19d:6431:41a6:faec References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 04:05:15 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 127 Xref: mx02.eternal-september.org comp.lang.vhdl:8140 On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: >=20 > Now it give me a chance to make a fortune to publish another group of=20 > invention-patents which had been finished at least 4 years ago and would= =20 > schematically and definitely show that new keyword "orif" and its data=20 > structure really saves logic and it is really indispensable=EF=BC=8Cessen= tial,=20 > necessary, all-important, of the utmost importance, of the essence, vital= ,=20 > must-have, crucial, key, needed, required, requisite, imperative and=20 > invaluable. >=20 You might want to save some of those superlatives for a different invention= , they do not apply to 'orif'. Back when you first proposed it, you used the keyword 'elsor' [1] which is = also how it is currently reflected in the proposal presented on the 1076 TW= IKI page [2]. However, the real problem is that if the control signals rea= lly are mutually exclusive, all of the different forms that you presented w= ill produce exactly the same result today. In your proposal, you presented= three different alternative forms (if/elsif...endif; sequential if/endif a= nd concurrent 'when/else') and you declared but presented no actual evidenc= e that these three will have 'superfluous condition is posed on the equatio= n' and that a 'priority tree' will be created which will in turn create ext= ra logic over the preferred form of a simple 'and/or' structure. You're mi= staken. All three of the alternatives will produce the exact same logic as= the preferred 'and/or' form. [3]. In order for their to be any actual utility to 'orif', you would first have= to come up with a scenario where the input control signals a, b, c, d, e t= ruly are mutually exclusive but the synthesis tool generates different resu= lts. One possible approach would be to say that a-e are top level inputs t= o the design and that those inputs are supposed to come from the output of = a decoder so therefore they are mutually exclusive. Besides limiting 'orif= ' to only be applicable to the scenario where the controls come only from d= evice input pins, this ignores the real world possibility that those input = pins have been shorted together so a-e are not absolutely guaranteed to be = mutually exclusive. But I'll leave it to you to: - Come up with the scenario where a-e are provably mutually exclusive but a= real synthesis tool produces different results for the four approaches tha= t you have defined and I have implemented in [3]. - Show how that scenario is of actual widespread benefit to anyone Kevin Jennings 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition 3. Using brand 'Q' synthesis tool, and the code below, you will get exactly= the same result no matter what value you set the generic 'Method'. =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D library ieee; use ieee.std_logic_1164.all; entity Orif_Example is generic(Method: in natural range 0 to 3); port( Address: in natural range 0 to 5; Abus: in std_ulogic; Bbus: in std_ulogic; Cbus: in std_ulogic; Dbus: in std_ulogic; Ebus: in std_ulogic; Outbus: out std_ulogic ); end Orif_Example; architecture RTL of Orif_Example is signal a: std_ulogic; signal b: std_ulogic; signal c: std_ulogic; signal d: std_ulogic; signal e: std_ulogic; begin a <=3D '1' when (Address =3D 1) else '0'; b <=3D '1' when (Address =3D 2) else '0'; c <=3D '1' when (Address =3D 3) else '0'; d <=3D '1' when (Address =3D 4) else '0'; e <=3D '1' when (Address =3D 5) else '0'; GEN_METHOD_0 : if (Method =3D 0) generate Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and = DBus) or (e and EBus);=20 end generate GEN_METHOD_0; GEN_METHOD_1 : if (Method =3D 1) generate -- One statement structure in serial mode:=20 process(all) begin if(a =3D '1') then OutBus <=3D ABus; elsif(b =3D '1') then Outbus <=3D BBus; elsif(c =3D '1') then Outbus <=3D CBus; elsif(d =3D '1') then Outbus <=3D DBus; elsif(e =3D '1') then Outbus <=3D EBus; else Outbus <=3D '0'; end if;=20 end process; end generate GEN_METHOD_1; GEN_METHOD_2 : if (Method =3D 2) generate -- or in another equal form:=20 process(all) begin Outbus <=3D '0';=20 if(a =3D '1') then OutBus <=3D ABus; end if; if(b =3D '1') then OutBus <=3D BBus; end if; if(c =3D '1') then OutBus <=3D CBus; end if; if(d =3D '1') then OutBus <=3D DBus; end if; if(e =3D '1') then OutBus <=3D EBus; end if; end process; end generate GEN_METHOD_2; GEN_METHOD_3 : if (Method =3D 3) generate -- In concurrent mode: OutBus <=3D ABus when a =3D '1' else BBus when b =3D '1' else CBus when c =3D '1' else DBus when d =3D '1' else EBus when e =3D '1' else '0'; end generate GEN_METHOD_3; end RTL; =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.70.42.170 with SMTP id p10mr8638838pdl.3.1425535152113; Wed, 04 Mar 2015 21:59:12 -0800 (PST) X-Received: by 10.50.129.98 with SMTP id nv2mr126247igb.1.1425535151991; Wed, 04 Mar 2015 21:59:11 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4538348igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4538330igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Mar 2015 21:59:11 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 05:59:12 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8141 On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: > On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > >=20 > > Now it give me a chance to make a fortune to publish another group of= =20 > > invention-patents which had been finished at least 4 years ago and woul= d=20 > > schematically and definitely show that new keyword "orif" and its data= =20 > > structure really saves logic and it is really indispensable=EF=BC=8Cess= ential,=20 > > necessary, all-important, of the utmost importance, of the essence, vit= al,=20 > > must-have, crucial, key, needed, required, requisite, imperative and=20 > > invaluable. > >=20 >=20 > You might want to save some of those superlatives for a different inventi= on, they do not apply to 'orif'. >=20 > Back when you first proposed it, you used the keyword 'elsor' [1] which i= s also how it is currently reflected in the proposal presented on the 1076 = TWIKI page [2]. However, the real problem is that if the control signals r= eally are mutually exclusive, all of the different forms that you presented= will produce exactly the same result today. In your proposal, you present= ed three different alternative forms (if/elsif...endif; sequential if/endif= and concurrent 'when/else') and you declared but presented no actual evide= nce that these three will have 'superfluous condition is posed on the equat= ion' and that a 'priority tree' will be created which will in turn create e= xtra logic over the preferred form of a simple 'and/or' structure. You're = mistaken. All three of the alternatives will produce the exact same logic = as the preferred 'and/or' form. [3]. >=20 > In order for their to be any actual utility to 'orif', you would first ha= ve to come up with a scenario where the input control signals a, b, c, d, e= truly are mutually exclusive but the synthesis tool generates different re= sults. One possible approach would be to say that a-e are top level inputs= to the design and that those inputs are supposed to come from the output o= f a decoder so therefore they are mutually exclusive. Besides limiting 'or= if' to only be applicable to the scenario where the controls come only from= device input pins, this ignores the real world possibility that those inpu= t pins have been shorted together so a-e are not absolutely guaranteed to b= e mutually exclusive. >=20 > But I'll leave it to you to: > - Come up with the scenario where a-e are provably mutually exclusive but= a real synthesis tool produces different results for the four approaches t= hat you have defined and I have implemented in [3]. > - Show how that scenario is of actual widespread benefit to anyone >=20 > Kevin Jennings >=20 > 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > 3. Using brand 'Q' synthesis tool, and the code below, you will get exact= ly the same result no matter what value you set the generic 'Method'. > =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D > library ieee; > use ieee.std_logic_1164.all; >=20 > entity Orif_Example is > generic(Method: in natural range 0 to 3); > port( > Address: in natural range 0 to 5; > Abus: in std_ulogic; > Bbus: in std_ulogic; > Cbus: in std_ulogic; > Dbus: in std_ulogic; > Ebus: in std_ulogic; > Outbus: out std_ulogic > ); > end Orif_Example; >=20 > architecture RTL of Orif_Example is > signal a: std_ulogic; > signal b: std_ulogic; > signal c: std_ulogic; > signal d: std_ulogic; > signal e: std_ulogic; > begin > a <=3D '1' when (Address =3D 1) else '0'; > b <=3D '1' when (Address =3D 2) else '0'; > c <=3D '1' when (Address =3D 3) else '0'; > d <=3D '1' when (Address =3D 4) else '0'; > e <=3D '1' when (Address =3D 5) else '0'; >=20 > GEN_METHOD_0 : if (Method =3D 0) generate > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d an= d DBus) or (e and EBus);=20 > end generate GEN_METHOD_0; >=20 > GEN_METHOD_1 : if (Method =3D 1) generate > -- One statement structure in serial mode:=20 > process(all) > begin > if(a =3D '1') then OutBus <=3D ABus; > elsif(b =3D '1') then Outbus <=3D BBus; > elsif(c =3D '1') then Outbus <=3D CBus; > elsif(d =3D '1') then Outbus <=3D DBus; > elsif(e =3D '1') then Outbus <=3D EBus; > else Outbus <=3D '0'; > end if;=20 > end process; > end generate GEN_METHOD_1; >=20 > GEN_METHOD_2 : if (Method =3D 2) generate > -- or in another equal form:=20 > process(all) > begin > Outbus <=3D '0';=20 > if(a =3D '1') then OutBus <=3D ABus; end if; > if(b =3D '1') then OutBus <=3D BBus; end if; > if(c =3D '1') then OutBus <=3D CBus; end if; > if(d =3D '1') then OutBus <=3D DBus; end if; > if(e =3D '1') then OutBus <=3D EBus; end if; > end process; >=20 > end generate GEN_METHOD_2; >=20 > GEN_METHOD_3 : if (Method =3D 3) generate > -- In concurrent mode: > OutBus <=3D ABus when a =3D '1' > else BBus when b =3D '1' > else CBus when c =3D '1' > else DBus when d =3D '1' > else EBus when e =3D '1' > else '0'; > end generate GEN_METHOD_3; > end RTL; > =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D Hi KJ, Thank you for taking time to discuss the keyword "orif". I don't have to generate other example and just use your example with follo= wing changes: Generate a, b, c, d, e in two different state machines with t= he two state machines being mutually exclusive, so that a-e are mutually ex= clusive.=20 The two state machine may be a read state machine and a write state machine= of a bus. And a-e are used to drive the 2nd bus. Now please generate your code to see how a compiler knows if a-e are mutual= ly exclusive. The generated code must be different!!! What your example provides is the simplest one and a compiler can do it ver= y easily!!! Nature and coding in complex situations are more complex than your example = provides. 1. You must acknowledge that there are situations that only the code writer= knows which conditions are mutually exclusive. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition#Arguments_FOR Current Situation Consider a basic equation in hardware design:=20 -- no priority tree is implied Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and DBus) or= (e and EBus); One statement structure in serial mode: -- a priority tree is implied if(a =3D '1') then OutBus <=3D ABus; elsif(b =3D '1') then Outbus <=3D BBus; elsif(c =3D '1') then Outbus <=3D CBus; elsif(d =3D '1') then Outbus <=3D DBus; elsif(e =3D '1') then Outbus <=3D EBus; else Outbus <=3D '0'; end if; or in another equal form: -- a priority tree is implied Outbus <=3D '0'; if(a =3D '1') then OutBus <=3D ABus; end if; if(b =3D '1') then OutBus <=3D BBus; end if; if(c =3D '1') then OutBus <=3D CBus; end if; if(d =3D '1') then OutBus <=3D DBus; end if; if(e =3D '1') then OutBus <=3D EBus; end if; In concurrent mode: -- a priority tree is implied OutBus <=3D ABus when a =3D '1' else BBus when b =3D '1' else CBus when c =3D '1' else DBus when d =3D '1' else EBus when e =3D '1' else '0'; In those above 3 situations, a superfluous condition is posed on the equati= on, it means a priority tree is implied in all three situations. Actually m= ost of time when dealing with main data flow, all above conditions are mutu= ally exclusive, so there is no need to pose the extra conditions on the fin= al equation. Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.140.216.150 with SMTP id m144mr9411177qhb.9.1425553138925; Thu, 05 Mar 2015 02:58:58 -0800 (PST) X-Received: by 10.50.79.170 with SMTP id k10mr634651igx.5.1425553138650; Thu, 05 Mar 2015 02:58:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!w8no691677qac.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no3485066igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 02:58:57 -0800 (PST) In-Reply-To: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 10:58:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 10921 X-Received-Body-CRC: 2877488998 Xref: mx02.eternal-september.org comp.lang.vhdl:8142 On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: > > On Wednesday, March 4, 2015 at 10:06:05 AM UTC-5, Weng Tianxiang wrote: > > > On Tuesday, March 3, 2015 at 11:47:41 PM UTC-8, hssig wrote: > > >=20 > > > Now it give me a chance to make a fortune to publish another group of= =20 > > > invention-patents which had been finished at least 4 years ago and wo= uld=20 > > > schematically and definitely show that new keyword "orif" and its dat= a=20 > > > structure really saves logic and it is really indispensable=EF=BC=8Ce= ssential,=20 > > > necessary, all-important, of the utmost importance, of the essence, v= ital,=20 > > > must-have, crucial, key, needed, required, requisite, imperative and= =20 > > > invaluable. > > >=20 > >=20 > > You might want to save some of those superlatives for a different inven= tion, they do not apply to 'orif'. > >=20 > > Back when you first proposed it, you used the keyword 'elsor' [1] which= is also how it is currently reflected in the proposal presented on the 107= 6 TWIKI page [2]. However, the real problem is that if the control signals= really are mutually exclusive, all of the different forms that you present= ed will produce exactly the same result today. In your proposal, you prese= nted three different alternative forms (if/elsif...endif; sequential if/end= if and concurrent 'when/else') and you declared but presented no actual evi= dence that these three will have 'superfluous condition is posed on the equ= ation' and that a 'priority tree' will be created which will in turn create= extra logic over the preferred form of a simple 'and/or' structure. You'r= e mistaken. All three of the alternatives will produce the exact same logi= c as the preferred 'and/or' form. [3]. > >=20 > > In order for their to be any actual utility to 'orif', you would first = have to come up with a scenario where the input control signals a, b, c, d,= e truly are mutually exclusive but the synthesis tool generates different = results. One possible approach would be to say that a-e are top level inpu= ts to the design and that those inputs are supposed to come from the output= of a decoder so therefore they are mutually exclusive. Besides limiting '= orif' to only be applicable to the scenario where the controls come only fr= om device input pins, this ignores the real world possibility that those in= put pins have been shorted together so a-e are not absolutely guaranteed to= be mutually exclusive. > >=20 > > But I'll leave it to you to: > > - Come up with the scenario where a-e are provably mutually exclusive b= ut a real synthesis tool produces different results for the four approaches= that you have defined and I have implemented in [3]. > > - Show how that scenario is of actual widespread benefit to anyone > >=20 > > Kevin Jennings > >=20 > > 1. http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt > > 2. http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition > > 3. Using brand 'Q' synthesis tool, and the code below, you will get exa= ctly the same result no matter what value you set the generic 'Method'. > > =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity Orif_Example is > > generic(Method: in natural range 0 to 3); > > port( > > Address: in natural range 0 to 5; > > Abus: in std_ulogic; > > Bbus: in std_ulogic; > > Cbus: in std_ulogic; > > Dbus: in std_ulogic; > > Ebus: in std_ulogic; > > Outbus: out std_ulogic > > ); > > end Orif_Example; > >=20 > > architecture RTL of Orif_Example is > > signal a: std_ulogic; > > signal b: std_ulogic; > > signal c: std_ulogic; > > signal d: std_ulogic; > > signal e: std_ulogic; > > begin > > a <=3D '1' when (Address =3D 1) else '0'; > > b <=3D '1' when (Address =3D 2) else '0'; > > c <=3D '1' when (Address =3D 3) else '0'; > > d <=3D '1' when (Address =3D 4) else '0'; > > e <=3D '1' when (Address =3D 5) else '0'; > >=20 > > GEN_METHOD_0 : if (Method =3D 0) generate > > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d = and DBus) or (e and EBus);=20 > > end generate GEN_METHOD_0; > >=20 > > GEN_METHOD_1 : if (Method =3D 1) generate > > -- One statement structure in serial mode:=20 > > process(all) > > begin > > if(a =3D '1') then OutBus <=3D ABus; > > elsif(b =3D '1') then Outbus <=3D BBus; > > elsif(c =3D '1') then Outbus <=3D CBus; > > elsif(d =3D '1') then Outbus <=3D DBus; > > elsif(e =3D '1') then Outbus <=3D EBus; > > else Outbus <=3D '0'; > > end if;=20 > > end process; > > end generate GEN_METHOD_1; > >=20 > > GEN_METHOD_2 : if (Method =3D 2) generate > > -- or in another equal form:=20 > > process(all) > > begin > > Outbus <=3D '0';=20 > > if(a =3D '1') then OutBus <=3D ABus; end if; > > if(b =3D '1') then OutBus <=3D BBus; end if; > > if(c =3D '1') then OutBus <=3D CBus; end if; > > if(d =3D '1') then OutBus <=3D DBus; end if; > > if(e =3D '1') then OutBus <=3D EBus; end if; > > end process; > >=20 > > end generate GEN_METHOD_2; > >=20 > > GEN_METHOD_3 : if (Method =3D 3) generate > > -- In concurrent mode: > > OutBus <=3D ABus when a =3D '1' > > else BBus when b =3D '1' > > else CBus when c =3D '1' > > else DBus when d =3D '1' > > else EBus when e =3D '1' > > else '0'; > > end generate GEN_METHOD_3; > > end RTL; > > =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D >=20 > Hi KJ, > Thank you for taking time to discuss the keyword "orif". >=20 > I don't have to generate other example and just use your example with fol= lowing changes: Generate a, b, c, d, e in two different state machines with= the two state machines being mutually exclusive, so that a-e are mutually = exclusive.=20 >=20 > The two state machine may be a read state machine and a write state machi= ne of a bus. And a-e are used to drive the 2nd bus. >=20 > Now please generate your code to see how a compiler knows if a-e are mutu= ally exclusive. The generated code must be different!!! >=20 > What your example provides is the simplest one and a compiler can do it v= ery easily!!! >=20 > Nature and coding in complex situations are more complex than your exampl= e provides. >=20 > 1. You must acknowledge that there are situations that only the code writ= er knows which conditions are mutually exclusive. >=20 > http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition#Arguments_FOR >=20 > Current Situation > Consider a basic equation in hardware design:=20 > -- no priority tree is implied > Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and DBus) = or (e and EBus); >=20 > One statement structure in serial mode: -- a priority tree is implied > if(a =3D '1') then OutBus <=3D ABus; > elsif(b =3D '1') then Outbus <=3D BBus; > elsif(c =3D '1') then Outbus <=3D CBus; > elsif(d =3D '1') then Outbus <=3D DBus; > elsif(e =3D '1') then Outbus <=3D EBus; > else Outbus <=3D '0'; > end if; >=20 > or in another equal form: -- a priority tree is implied > Outbus <=3D '0'; > if(a =3D '1') then OutBus <=3D ABus; end if; > if(b =3D '1') then OutBus <=3D BBus; end if; > if(c =3D '1') then OutBus <=3D CBus; end if; > if(d =3D '1') then OutBus <=3D DBus; end if; > if(e =3D '1') then OutBus <=3D EBus; end if; >=20 > In concurrent mode: -- a priority tree is implied > OutBus <=3D ABus when a =3D '1' > else BBus when b =3D '1' > else CBus when c =3D '1' > else DBus when d =3D '1' > else EBus when e =3D '1' > else '0'; >=20 > In those above 3 situations, a superfluous condition is posed on the equa= tion, it means a priority tree is implied in all three situations. Actually= most of time when dealing with main data flow, all above conditions are mu= tually exclusive, so there is no need to pose the extra conditions on the f= inal equation. >=20 > Weng Hi KJ, You don't have to look for mutually exclusive conditions in any artificial = examples. Just look at any of your successful projects, check any of complex if-state= ments to see if there are any contiguous conditions which are mutually excl= usive in an if-statement. If you find some, change related "elsif" to "orif= ", then this part of logic would run faster than the original one without e= ffecting other logic.=20 No matter it is a partial or a full if-statement. No matter it is a data bus or a state machine logic. No matter it is a top level if-statement or a deeply nested if-statement. That is the real magic the keyword "orif" plays: you provide more info and = the compiler should generate more efficient logic accordingly. Please remember that a compiler cannot know more than what you understand a= s a code writer. Thank you. Weng From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.66.232.133 with SMTP id to5mr10831767pac.27.1425577381655; Thu, 05 Mar 2015 09:43:01 -0800 (PST) X-Received: by 10.140.81.229 with SMTP id f92mr201270qgd.28.1425577381565; Thu, 05 Mar 2015 09:43:01 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4954564igb.0!news-out.google.com!c1ni208qar.1!nntp.google.com!k15no489770qaq.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 09:43:01 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.125.175.43; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 64.125.175.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7a9948cf-f0fd-440e-9756-f63dd6b4908f@googlegroups.com> Subject: Want to learn VHDL and FPGA programming? From: jjchristman13@gmail.com Injection-Date: Thu, 05 Mar 2015 17:43:01 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: mx02.eternal-september.org comp.lang.vhdl:8143 Hi, if you or anyone you know is interested in training or need additional learning material for VHDL and FPGA programming check out my course! I'm offering a special for $10 with lifetime access!! This coupon is valid till 4/7/15! www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=VHDL10#/ From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.182.191.65 with SMTP id gw1mr11468354obc.40.1425579242635; Thu, 05 Mar 2015 10:14:02 -0800 (PST) X-Received: by 10.50.60.71 with SMTP id f7mr688061igr.10.1425579242553; Thu, 05 Mar 2015 10:14:02 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no4975979igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4975976igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:14:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Thu, 05 Mar 2015 18:14:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8144 On Friday, February 27, 2015 at 11:51:37 AM UTC-8, KJ wrote: > On Thursday, February 26, 2015 at 9:03:15 PM UTC-5, Weng Tianxiang wrote: > > [0020] If the coding system becomes new part of HDL standards all > > synthesizer manufactures will automatically be forced to implement all = well- > > known wave-pipelining algorithms and techniques within their products, = a=20 > > competition will start for better implementations, making wave-pipelini= ng=20 > > technique available to every digital designer in HDL. > >=20 > A couple of problems with your assumptions: > - No standard body will accept a patent burdened idea to incorporate into= a new revision of a standard. You would likely have to effectively surren= der your patent rights (should they be granted in the first place) in order= to get this to happen. Hi KJ, Here is an example that MIT has 4 patents for HDTV and now it is suing a Ja= panese HDTV manufacturer. MIT Sues Funai Over 4 HDTV Patents http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents Weng > - If you think that simply being part of a standard will force synthesis = vendors to do anything at all, you're very mistaken. > - Wave pipelining has not caught on with FPGA suppliers in the 45 years s= ince the concept was first introduced nor in the 16 years since Burleson's = paper was published so uptake on the technique has not been very quick. Th= at doesn't imply that it will never catch on, but it does suggest the wait = will be significant. >=20 > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.42.63.10 with SMTP id a10mr3950159ici.25.1425579617322; Thu, 05 Mar 2015 10:20:17 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr334734igb.10.1425579617226; Thu, 05 Mar 2015 10:20:17 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!hl2no3685768igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no3685758igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:20:16 -0800 (PST) In-Reply-To: <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6407dd22-922b-4abb-a1e0-34a434343e6f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 18:20:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 9808 X-Received-Body-CRC: 774136007 Xref: mx02.eternal-september.org comp.lang.vhdl:8145 On Thursday, March 5, 2015 at 12:59:17 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 8:05:16 PM UTC-8, KJ wrote: >=20 > I don't have to generate other example and just use your example with=20 > following changes: Generate a, b, c, d, e in two different state machines= =20 > with the two state machines being mutually exclusive, so that a-e are=20 > mutually exclusive.=20 >=20 You're the one making the unsubstantiated claim, so you should generate the= example. But I did make up one as you said [1]. Two state machines. One= generates a, b, c. The other generates d, e. Which state machine is acti= ve at any given time is controlled by an external device I/O pin. The result is exactly the same as I previously stated. Regardless of the m= ethod chosen to implement the data bus muxing, the synthesized output files= are identical. >=20 > Now please generate your code to see how a compiler knows if a-e are=20 > mutually exclusive. The generated code must be different!!! >=20 They are not different. > What your example provides is the simplest one and a compiler can do it= =20 > very easily!!! You provided no example of how a-e would be generated and probably mutually= exclusive which is more than you provided. You simply made claims based o= n the appearance of the source code and an incorrect assumption of how synt= hesis tools would create logic >=20 > Nature and coding in complex situations are more complex than your exampl= e=20 > provides. Don't try to hide behind 'complex situations'. In a good design you would = not code something that is intended to be mutually exclusive in a way that = makes it possibly not exclusive (i.e. the generation of a-e). So there wou= ld be no a-e, but simply an enumeration or an integer that might get decode= d into a-e at some point in a manner essentially identical to what I showed= . What I'm showing here on this post is that even if you try to make it 'more= complex', the described logic still resulted in absolutely no difference i= n the synthesized logic output so the 'orif' still would provide no benefit= . You're presenting 'orif' as if is somehow widely applicable to any numbe= r of situations. While there might be niches where 'orif' does have use, I= 've shown here in these two posts that it is not nearly as universal as you= seem to think. So the scope of where it is useful is quite a bit smaller.= In fact, to this point, you have not provided a single scenario where it = can actually be shown to result in less logic as you claim. What you shoul= d focus on is what types of situations would 'orif' actually be beneficial = instead of making a claim, not testing it and then be called on it. I'm no= t saying 'orif' isn't useful, but the scope of where it would be useful has= not been shown. >=20 > 1. You must acknowledge that there are situations that only the code writ= er knows which conditions are mutually exclusive. >=20 You have not presented actual working sample of such code to demonstrate a = single situation. I'll accept that maybe you could, but just have not. On= the other side, I've put forth two examples of situations where 'orif' wou= ld have no benefit even though you claimed that it would. For me though, these situations would not arise because I wouldn't be writi= ng code where something that is mutually exclusive is not explicitly coded = in that way as well. There would be no need for "only the code writer know= s..." =20 > In those above 3 situations, a superfluous condition is posed on the=20 > equation, it means a priority tree is implied in all three situations.=20 > Actually most of time when dealing with main data flow, all above=20 > conditions are mutually exclusive, so there is no need to pose the extra= =20 > conditions on the final equation. >=20 I've shown that to not be the case. Kevin [1] Modified code that demonstrates a 'more complex' version of creating a-= e that still results in identical implementation of the logic =3D=3D=3D=3D=3D=3D=3D START OF CODE =3D=3D=3D=3D=3D=3D=3D library ieee;=20 use ieee.std_logic_1164.all;=20 entity Orif_Example is=20 generic( Excl_Method:in natural range 0 to 1; Method: in natural range 0 to 3);=20 port( Clock: in std_ulogic; Selector: in std_ulogic; Address: in natural range 0 to 5;=20 Abus: in std_ulogic;=20 Bbus: in std_ulogic;=20 Cbus: in std_ulogic;=20 Dbus: in std_ulogic;=20 Ebus: in std_ulogic;=20 Outbus: out std_ulogic=20 );=20 end Orif_Example;=20 architecture RTL of Orif_Example is=20 signal a: std_ulogic;=20 signal b: std_ulogic;=20 signal c: std_ulogic;=20 signal d: std_ulogic;=20 signal e: std_ulogic;=20 begin=20 GEN_EXCL_METHOD_0 : if (Excl_Method =3D 0) generate a <=3D '1' when (Address =3D 1) else '0';=20 b <=3D '1' when (Address =3D 2) else '0';=20 c <=3D '1' when (Address =3D 3) else '0';=20 d <=3D '1' when (Address =3D 4) else '0';=20 e <=3D '1' when (Address =3D 5) else '0';=20 end generate GEN_EXCL_METHOD_0; GEN_EXCL_METHOD_1 : if (Excl_Method =3D 1) generate type t_STATES1 is (Idle, St_a, St_b, St_c); type t_STATES2 is (Idle, St_d, St_e); signal State1: t_STATES1; signal State2: t_STATES2; begin process(Clock) begin if rising_edge(Clock) then a <=3D '0'; b <=3D '0'; c <=3D '0'; d <=3D '0'; e <=3D '0'; case State1 is when Idle =3D> null; when St_a =3D> a <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_b; end if; when St_b =3D> b <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_c; end if; when St_c =3D> c <=3D '1'; if (Selector =3D '1') th= en State1 <=3D St_a; end if; end case; case State2 is when Idle =3D> null; when St_d =3D> d <=3D '1'; if (Selector =3D '0') th= en State2 <=3D St_e; end if; when St_e =3D> e <=3D '1'; if (Selector =3D '0') th= en State2 <=3D St_d; end if; end case; end if; end process; end generate GEN_EXCL_METHOD_1; GEN_METHOD_0 : if (Method =3D 0) generate=20 Outbus <=3D (a and ABus) or (b and BBus) or (c and CBus) or (d and = DBus) or (e and EBus);=20 end generate GEN_METHOD_0;=20 GEN_METHOD_1 : if (Method =3D 1) generate=20 -- One statement structure in serial mode:=20 process(all)=20 begin=20 if(a =3D '1') then OutBus <=3D ABus;=20 elsif(b =3D '1') then Outbus <=3D BBus;=20 elsif(c =3D '1') then Outbus <=3D CBus;=20 elsif(d =3D '1') then Outbus <=3D DBus;=20 elsif(e =3D '1') then Outbus <=3D EBus;=20 else Outbus <=3D '0';=20 end if;=20 end process;=20 end generate GEN_METHOD_1;=20 GEN_METHOD_2 : if (Method =3D 2) generate=20 -- or in another equal form:=20 process(all)=20 begin=20 Outbus <=3D '0';=20 if(a =3D '1') then OutBus <=3D ABus; end if;=20 if(b =3D '1') then OutBus <=3D BBus; end if;=20 if(c =3D '1') then OutBus <=3D CBus; end if;=20 if(d =3D '1') then OutBus <=3D DBus; end if;=20 if(e =3D '1') then OutBus <=3D EBus; end if;=20 end process;=20 end generate GEN_METHOD_2;=20 GEN_METHOD_3 : if (Method =3D 3) generate=20 -- In concurrent mode:=20 OutBus <=3D ABus when a =3D '1'=20 else BBus when b =3D '1'=20 else CBus when c =3D '1'=20 else DBus when d =3D '1'=20 else EBus when e =3D '1'=20 else '0';=20 end generate GEN_METHOD_3;=20 end RTL;=20 =3D=3D=3D=3D=3D=3D=3D END OF CODE =3D=3D=3D=3D=3D=3D=3D From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.42.76.145 with SMTP id e17mr4122680ick.34.1425579874086; Thu, 05 Mar 2015 10:24:34 -0800 (PST) X-Received: by 10.50.107.4 with SMTP id gy4mr335120igb.10.1425579873979; Thu, 05 Mar 2015 10:24:33 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no4985410igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no4985399igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 5 Mar 2015 10:24:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Thu, 05 Mar 2015 18:24:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 33 Xref: mx02.eternal-september.org comp.lang.vhdl:8146 On Thursday, March 5, 2015 at 5:59:00 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > You don't have to look for mutually exclusive conditions in any artificia= l=20 > examples. You provided the examples. >=20 > Just look at any of your successful projects, check any of complex if- > statements to see if there are any contiguous conditions which are=20 > mutually exclusive in an if-statement. If you find some, change related= =20 > "elsif" to "orif", then this part of logic would run faster than the=20 > original one without effecting other logic.=20 I've already shown that it would not under common situations. >=20 > No matter it is a partial or a full if-statement. > No matter it is a data bus or a state machine logic. > No matter it is a top level if-statement or a deeply nested if-statement. >=20 > That is the real magic the keyword "orif" plays: you provide more info an= d=20 > the compiler should generate more efficient logic accordingly. The only 'more info' that is needed is to code properly. If something is m= utually exclusive, then it should be coded as a single signal that has mult= iple values, not as separate signals. Although as I've demonstrated, separ= ate signals can still be properly analyzed by synthesis and the optimum sol= ution obtained without 'orif'. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:45 2015 X-Received: by 10.236.28.44 with SMTP id f32mr14623093yha.11.1425681947327; Fri, 06 Mar 2015 14:45:47 -0800 (PST) X-Received: by 10.182.46.199 with SMTP id x7mr157993obm.13.1425681947243; Fri, 06 Mar 2015 14:45:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no6044387igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no6044381igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 6 Mar 2015 14:45:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Subject: MODELSIM: Switch between two package libraries depending on environment From: "V." Injection-Date: Fri, 06 Mar 2015 22:45:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: mx02.eternal-september.org comp.lang.vhdl:8147 I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. I was trying to do the following in order to switch between them: use work.intf_defn -- synthesis translate_off _sim -- synthesis translate_on .all; ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. Is there a smarter way to do this? The following compiles without issue, but not quite what I want. use work -- synthesis translate_off .intf_defn -- synthesis translate_on .all; From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.78.69 with SMTP id z5mr18337148obw.4.1425730014674; Sat, 07 Mar 2015 04:06:54 -0800 (PST) X-Received: by 10.140.34.168 with SMTP id l37mr298660qgl.20.1425730014531; Sat, 07 Mar 2015 04:06:54 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!hl2no4612134igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no4612133igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 04:06:54 -0800 (PST) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:c073:c0e0:28cf:f653; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:c073:c0e0:28cf:f653 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <02cac647-df24-45b0-bdff-b3f72bfdbf98@googlegroups.com> Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: KJ Injection-Date: Sat, 07 Mar 2015 12:06:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8148 On Friday, March 6, 2015 at 5:45:49 PM UTC-5, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical > defines, but different values. > > Is there a smarter way to do this? > - Put the two packages into separate files - Use the same package name - Include the file with the 'sim' package in Modelsim; include the file with the 'synthesis' package into your synthesis tool. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.236.53.10 with SMTP id f10mr18579320yhc.17.1425744699556; Sat, 07 Mar 2015 08:11:39 -0800 (PST) X-Received: by 10.182.233.202 with SMTP id ty10mr170935obc.31.1425744699460; Sat, 07 Mar 2015 08:11:39 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.ripco.com!news.glorb.com!hl2no4710652igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no6561347igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 08:11:39 -0800 (PST) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=206.51.178.164; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 206.51.178.164 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5629b3d6-7633-4d10-a75f-da2afc3583d0@googlegroups.com> Subject: Re: Learning VHDL beyond basics From: jjchristman13@gmail.com Injection-Date: Sat, 07 Mar 2015 16:11:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8149 Hi, if you or anyone you know is interested in training or need additional learning material for VHDL and FPGA programming check out my course! I'm offering a special for $10 with lifetime access!! This coupon is valid till 4/7/15! www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=VHDL10#/ From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.102.100 with SMTP id fn4mr19209481pab.19.1425749927036; Sat, 07 Mar 2015 09:38:47 -0800 (PST) X-Received: by 10.50.30.202 with SMTP id u10mr516659igh.6.1425749927003; Sat, 07 Mar 2015 09:38:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no6613545igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no4744860igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 7 Mar 2015 09:38:46 -0800 (PST) In-Reply-To: <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 07 Mar 2015 17:38:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8150 On Thursday, March 5, 2015 at 10:24:35 AM UTC-8, KJ wrote: > On Thursday, March 5, 2015 at 5:59:00 AM UTC-5, Weng Tianxiang wrote: > > On Wednesday, March 4, 2015 at 9:59:17 PM UTC-8, Weng Tianxiang wrote: > > You don't have to look for mutually exclusive conditions in any artific= ial=20 > > examples. >=20 > You provided the examples. >=20 > >=20 > > Just look at any of your successful projects, check any of complex if- > > statements to see if there are any contiguous conditions which are=20 > > mutually exclusive in an if-statement. If you find some, change related= =20 > > "elsif" to "orif", then this part of logic would run faster than the=20 > > original one without effecting other logic.=20 >=20 > I've already shown that it would not under common situations. >=20 > >=20 > > No matter it is a partial or a full if-statement. > > No matter it is a data bus or a state machine logic. > > No matter it is a top level if-statement or a deeply nested if-statemen= t. > >=20 > > That is the real magic the keyword "orif" plays: you provide more info = and=20 > > the compiler should generate more efficient logic accordingly. >=20 > The only 'more info' that is needed is to code properly. If something is= mutually exclusive, then it should be coded as a single signal that has mu= ltiple values, not as separate signals. Although as I've demonstrated, sep= arate signals can still be properly analyzed by synthesis and the optimum s= olution obtained without 'orif'. >=20 > Kevin Jennings Hi KJ, "If something is mutually exclusive, then it should be coded as a single si= gnal that has multiple values, not as separate signals. " How can a compiler know that a group of signals coming from two different s= tate machines are mutually exclusive unless you give more info? Those situations are common in my coding. As my example has shown, there is no better way than using a case statement= to tell a compiler that those signals are mutually exclusive. Please let me know if there is a better way than using case statement to do= so. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp6-1.free.fr!not-for-mail Date: Sun, 08 Mar 2015 11:40:32 +0100 From: manu User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: MODELSIM: Switch between two package libraries depending on environment References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Lines: 41 Message-ID: <54fc2731$0$3354$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 08 Mar 2015 11:40:49 CET NNTP-Posting-Host: 82.229.198.7 X-Trace: 1425811249 news-2.free.fr 3354 82.229.198.7:43635 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8151 Hello, this is not a modelsim but a VHDL issue. I had the same problem in a mixed-signal design as "_sig" syntax is widely used among analog designers to reflect active low signals. Identifiers must start with letter. Special characters and even ciphers are not allowed. Some tools mays accept this but most will fail to compile your code. Regards, Manu On 06/03/2015 23:45, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; > From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.18.102 with SMTP id v6mr25299962obd.11.1425850834042; Sun, 08 Mar 2015 14:40:34 -0700 (PDT) X-Received: by 10.140.32.34 with SMTP id g31mr399086qgg.21.1425850834007; Sun, 08 Mar 2015 14:40:34 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no7421039igb.0!news-out.google.com!db6ni44597igc.0!nntp.google.com!hl2no7421036igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 8 Mar 2015 14:40:33 -0700 (PDT) In-Reply-To: <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2963:5d3a:e919:6aaf; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2963:5d3a:e919:6aaf References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <7b19ea4b-bdd7-4227-b7e6-7fd28f6bb00e@googlegroups.com> <15b8812b-4e00-4761-ae44-c2610a5d2417@googlegroups.com> <4efc6b8d-837a-4a56-a029-6df96667c6d9@googlegroups.com> <227db440-0de6-45b7-9a5b-c207b931811f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <02bce619-0d24-4649-890f-0354b1238ec4@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Sun, 08 Mar 2015 21:40:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8152 On Saturday, March 7, 2015 at 12:38:52 PM UTC-5, Weng Tianxiang wrote: > On Thursday, March 5, 2015 at 10:24:35 AM UTC-8, KJ wrote: > >=20 > > "If something is mutually exclusive, then it should be coded as a singl= e > > signal that has multiple values, not as separate signals. " >=20 > How can a compiler know that a group of signals coming from two different= =20 > state machines are mutually exclusive unless you give more info? >=20 Synthesis tool don't give a hoot about whether you think something is mutua= lly exclusive or not. They implement Boolean logic from a hardware descrip= tion. I've already shown you two examples where you seem to believe it to = not be possible that synthesis tools do the proper thing, and apparently yo= u can't accept it. > Those situations are common in my coding. >=20 OK...so what? > As my example has shown, there is no better way than using a case stateme= nt=20 > to tell a compiler that those signals are mutually exclusive. >=20 A case statement does not "tell a compiler that those signals are mutually = exclusive". It is a enumeration of all of the states possible and what is = to be done under those conditions. Nothing more, nothing less. > Please let me know if there is a better way than using case statement to = do=20 > so. >=20 I already did, you don't accept it so I'm done. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.148.40 with SMTP id tp8mr9239662pab.35.1425895362991; Mon, 09 Mar 2015 03:02:42 -0700 (PDT) X-Received: by 10.50.22.3 with SMTP id z3mr644614ige.3.1425895362951; Mon, 09 Mar 2015 03:02:42 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!hl2no7694821igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no5343908igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Mar 2015 03:02:42 -0700 (PDT) In-Reply-To: <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Mon, 09 Mar 2015 10:02:42 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 303 X-Received-Bytes: 19720 X-Received-Body-CRC: 2508480071 Xref: mx02.eternal-september.org comp.lang.vhdl:8153 On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrote: > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wrote= : > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > >=20 > > > I have filed a provisional patent application: "Systematic method of = coding wave pipelined circuits in HDL". If it is proved correct, the patent= will introduce 1 keyword, 3 permanent constants, 1 concurrent statement an= d four source code modules for a new library in HDL and thoroughly resolve = a pending problem so that every digital designer can code wave-pipelined ci= rcuits in HDL. > > >=20 > > > Here is the abstract of the invention: > > >=20 > > > The present invention classifies all critical paths into two basi= c types: a series critical path and a feedback critical path, and divides e= ach of wave-pipelined circuits into two components: a static logic part, ca= lled critical path component (CPC), and a dynamic logic part, formalized in= to four wave-pipelining components (WPC) shared by all wave-pipelined circu= its. Each wave-pipelining ready code in HDL comprises two components: a WPC= instantiation and a CPC instantiation wire-connected and linked by a new l= ink statement. Each WPC has new wave constants which play the same role as = generic constants do, but whose initial values are determined and assigned = by a synthesizer after code analysis, so designers can use after-synthesiza= tion information in their code before synthesization for wave-pipelining te= chnology. The responsibility of analyzing and manipulating wave-pipelining = ready code, generating and implementing wave-pipelined circuits on a design= -wide or chip-wide scale in HDL is shifted from designers to synthesizers. > > >=20 > > > Anyone who are interested in its content is welcome to send a email r= equest to the following email address: wtx wtx @ gmail . com with title "Sy= stematic" and he will receive the full documents: one specification, 9 draw= ings and one text file in VHDL. > > >=20 > > > If one reviews the files and feels that it would be a good thing to r= ecommend the application to his company to buy it, the first person to do i= t after his recommended company does so will receive $10,000 commission fee= . > > >=20 > > > Thank you. > > >=20 > > > Weng > >=20 > > Hi, > > I want to add some introductions to what the wave-pipelined circuits ar= e and their status. > >=20 > > [0003] A synchronous digital system contains a lot of registers. Val= id data flow through successive registers from system input registers to sy= stem output registers. All data flows are synchronous with triggering edges= of a chip clock. For example, data flow from registers A to registers B, f= rom registers B to registers C and so on in a successive order on the same = clock cycle. > > [0004] A path in a synchronous digital system is a route between any= neighboring registers connected by combinational logic. If the target runn= ing frequency for a digital design is predetermined, the upper limit of pro= pagating time for any paths is determined and has the inverse value of the = target running frequency. A path is called a critical path if the time sign= als take to propagate through it is beyond the predetermined propagating ti= me, and the time is called the path's critical time. If there are any criti= cal paths, digital designers must spend time reducing all critical times by= all means and eliminating all critical paths to meet the target running fr= equency. > > [0005] Wave-pipelining is a technology which completes an operation = that needs several clock cycles to propagate without intermediate registers= and with input data acceptable on every clock cycle. For example, in a con= ventional pipelining operation, data flow from registers A to registers D t= hrough registers B and C to divide the critical path time into multiple sma= ller intervals to meet the critical time: A to B to C to D; with wave-pipel= ining, data flow through registers A and D without intermediate registers B= and C. Absolutely, wave-pipelining will reduce logic resource usage and is= superior to the conventional pipelining technology if it can be used. > >=20 > > Here are the most important inequalities involving wave-pipelining from= paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burles= on et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, no.= 3, pp. 464-474, Sep. 1998. > >=20 > > [0018] Currently many memory chip manufacturers successfully use wav= e-pipelining in their memory chip products with higher rate outputs, reduce= d power consumption and logic resources; and a few scientists use FPGA chip= s as a base to show some circuits can be done with wave-pipelining in isola= ted environments. Their works prove that the wave-pipelining is a very powe= rful tool to reduce power consumption and logic resources. Now there are tw= o major existing obstacles preventing any ordinary digital designers from u= sing the wave-pipelining in HDL: > > * The software algorithms making wave-pipelining successful, like Wong = and Klass algorithms and others, have already been developed and matured, b= ut ordinary digital designers have no means or resources to access to the t= echnology, because there are no international HDL standards on how synthesi= zer manufacturers incorporate those capabilities into their products. > > * HDL needs the capabilities for digital designers to write wave-pipeli= ning ready code for any number of critical paths on a design-wide or chip-w= ide scale instead of in an isolated environment and the written code can be= identified, synthesized and used to generate wave-pipelined circuits by an= y synthesizer in ASIC or FPGA, and they should be part of HDL standards.=20 > > [0019] The target of the present invention is: > > * Invent a wave-pipelining coding system as new part of HDL standards f= or designers to write wave-pipelining ready code which can be identified, s= ynthesized and used to generate wave-pipelined circuits by any synthesizer = in ASIC or FPGA. > > * Make wave-pipelining ready code written based on the coding system wo= rking with no extra logic generated, compared with independently written wa= ve-pipelined circuits, and with no code changes when switching from non-wav= e-pipelined mode to wave-pipelined mode or vice verse if all of wave-pipeli= ning ready code meet wave-pipelining requirements.=20 > > * Shift burdens of analyzing and manipulating wave-pipelining ready cod= e, generating and implementing wave-pipelined circuits on a design-wide or = chip-wide scale in HDL from individual designers to synthesizer manufacture= rs. > > [0020] If the coding system becomes new part of HDL standards all sy= nthesizer manufactures will automatically be forced to implement all well-k= nown wave-pipelining algorithms and techniques within their products, a com= petition will start for better implementations, making wave-pipelining tech= nique available to every digital designer in HDL. > >=20 > > Weng >=20 > Here I add some contents of the invention: >=20 > Main idea behind the present invention >=20 > [0057] The most difficult part coding all types of wave-pipelined circ= uits on a design-wide scale in HDL is that a wave-pipelined circuit code al= ways comprises two logic parts:=20 > * A static logic part: it doesn't change if the number of series clock cy= cles through the circuit changes and is unique for each of wave-pipelined c= ircuits. > * A dynamic logic part: it does change if the number of series clock cycl= es through the circuit changes and is the same for one of groups of wave-pi= pelined circuits. > [0058] Every wave-pipelined circuit has its own change rules and those= changes are unknown to designers when they are writing code and will be kn= own to a synthesizer only after it has analyzed the circuit. > [0059] The present invention classifies all critical paths into two ba= sic types: a series critical path and a feedback critical path, and divides= each of wave-pipelined circuits into two components: one is static logic p= art and called critical path component (CPC); another is dynamic logic part= and formalized into four wave-pipelining components (WPC) shared by all wa= ve-pipelined circuits. Under the present invention each of standard wave-pi= pelining ready code in HDL comprises two components: a WPC instantiation an= d a CPC instantiation which are wire-connected and linked by a new concurre= nt link statement. Each of four WPC embodiments has a group of new type wav= e constant, which plays the same role as a generic constant does, but whose= initial value is determined and assigned by a synthesizer after it has ana= lyzed the linked CPC component under slow mode and target mode, respectivel= y, so designers can use after-synthesization information in their code befo= re synthesization in HDL for wave-pipelining technology. Following the inst= ructions of the present invention creates a situation that digital designer= s can write wave-pipelining ready code in HDL and the responsibility of ana= lyzing and manipulating wave-pipelining ready code, generating and implemen= ting wave-pipelined circuits on a design-wide or chip-wide scale in HDL is = shifted from individual designers to synthesizer manufacturers. >=20 > How the method works >=20 > [0060] The systematic method of coding wave-pipelined circuits in HDL = comprises following ten parts: > 1. Define five signals, one counter, one switch and one table that will b= e used when generating wave-pipelined circuits on a design-wide or chip-wid= e scale in HDL. > 2. Define the interfaces of a CPC each of which encapsulates a critical p= ath's static logic part. > 3. Define and implement four WPC embodiments in HDL each of which is a cr= itical path's dynamic logic part: a series_module, an input_delay_module, a= multiple_copy_module1 and a multiple_copy_module2. > 4. Define one new keyword wave and three new wave constants which provide= a means to dynamically transfer after-synthesization information to design= ers' code before synthesization. > 5. Define the methods of determining and searching for wave constant valu= es of a known WPC instantiation under slow mode and target mode, respective= ly. > 6. Define three versions of a concurrent link statement: link1, link2 and= link3, and rules on how they are used. > 7. Define the pairing rules between a WPC and a CPC. > 8. Define how a digital designer prepares wave-pipelining ready code syst= ematically. > 9. Shift the responsibility of analyzing and manipulating wave-pipelining= ready code, generating and implementing wave-pipelined circuits on a desig= n-wide or chip-wide scale in HDL from individual designers to synthesizer m= anufacturers. > 10. Define how four WPC embodiments are simulated and debugged under any = of current versions of a synthesizer in HDL. > [0061] It is fair to put the burden of successfully generating wave-pi= pelined circuits based on wave-pipelining ready code squarely on synthesize= r manufacturers' shoulder if all necessary information is passed to a synth= esizer. For example, with tens of papers claiming that successful wave-pipe= lined circuits are implemented in FPGA chips in an isolated environment, it= is the responsibility of FPGA synthesizers to be capable of generating tho= se wave-pipelined circuits in a design-wide environment without designers' = further involvements, a process similar for them to the task of generating = a circuit with the highest running frequency and minimum used resources if = possible for any normal digital design code. >=20 > Thank you for your reading. Here are more contents. Definitions of wave-pipelining component and critical path component [0062] A design component is called a critical path component (CPC) if i= t is an entity (a term in VHDL-2002) in HDL and encapsulates the static log= ic part of a critical path which is to be wave-pipelined circuit. There are= two types of CPCs:=20 =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99s st= atic logic part. =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2=80=99= s static logic part.=20 [0063] A CPC also refers to a CPC instantiation when it will not be misu= nderstood. The required interfaces of both a series CPC and a feedback CPC = are always the same. The combinational logic of a CPC may be located within= or outside of the component and there is no limit on it.=20 [0064] A design component is called a wave-pipelining component (WPC) if= it is an entity in HDL, provided by HDL in a new wave-pipelining system li= brary and used to generate a critical path=E2=80=99s dynamic logic part, i.= e., to generate output data valid signal and write enable signals to the in= put and output registers of a critical path.=20 [0065] There are three types of WPC:=20 =E2=80=A2 A series_module is used to connect to a series CPC with input dat= a acceptable on every clock cycle. =E2=80=A2 An input_delay_module is used to connect to a series or feedback = CPC with input data acceptable on every one or more clock cycle. =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to con= nect to multiple copied series or feedback CPCs with input data acceptable = on every clock cycle. [0066] A WPC also refers to a WPC instantiation when it will not be misu= nderstood. Later multiple_copy_module refers to either of multiple_copy_mod= ule1 and multiple_copy_module2. A synthesizer=E2=80=99s new signals, switch and table [0067] A synthesizer that is able of handling wave-pipelining needs six = signals, one switch, one table and the table=E2=80=99s row index to help fi= nish its job: =E2=80=A2 A floating signal target_running_frequency: it is set up by a des= igner and the target running frequency under which a design finally runs. =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and its= initial value is deasserted. A synthesizer will generate related circuit f= iles for a design under slow mode for slow mode hardware testing if generat= e_circuit is asserted and no errors are detected after a synthesization, or= will not otherwise. A synthesizer will always generate related circuit fil= es for a design under target mode for target mode hardware testing if no er= rors are detected after a synthesization. =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and its = initial value is deasserted. Assert the bit if a CPC is being analyzed and = determined to have feedbacks, and deassert it after the analysis is finishe= d. =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer and = its initial value is deasserted. Assert the bit if a designer wants to keep= all CPC new circuits automatically and successfully modified by a synthesi= zer under target mode unchanged under slow mode when he is switching to syn= thesize the same design from under target mode to under slow mode and the r= elated code doesn=E2=80=99t change, or deassert it otherwise. The bit provi= des a method for a designer to check if the new automatically and successfu= lly modified circuits by a synthesizer don=E2=80=99t change basic logic.=20 =E2=80=A2 An integer signal parent_series_clock_number: it is set up by a s= ynthesizer and Its initial value is zero. When the instantiation of a WPC d= elay_input_module or multiple_copy_module is being analyzed and executed it= s series_clock_number value is stored in parent_series_clock_number, and it= is cleared to zero when the execution is finished. =E2=80=A2 An integer signal start_number: it is set up by a synthesizer and= used when the synthesizer determines that a CPC cannot meet the wave-pipel= ining requirements with input data acceptable on every clock cycle and the = CPC is linked with a WPC input_delay_module or multiple_copy_module. The st= art_number is made equal to 2 if a WPC multiple_copy_module is linked or to= feedback_clock_number if a WPC input_delay_module is linked as the startin= g value of wave constant input_clock_number or multiple_copy_number. =E2=80=A2 A bit switch running_mode: it is set up by a designer and it has = two valid values with slow mode being its initial value: o Slow mode: under slow mode a digital designer designs his code, a design = is synthesized, simulated, and hardware tested under the following assumpti= ons: =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs und= er slow running frequency. =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. =EF=82=A7 No multiple copied CPCs are generated. o Target mode: under target mode a design is synthesized, simulated, hardwa= re tested and finally runs under predetermined target running frequency, an= d its implementation is determined and generated by a synthesizer under the= following assumptions: =EF=82=A7 Signals take one or more clock cycle to propagate through any of = CPCs as designed. =EF=82=A7 Each of CPCs has input data acceptable on every one or more clock= cycle as wave-pipelining ready code indicates and it is necessary. =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready code = indicates and it is necessary. =E2=80=A2 A wave constant signal table: it is generated and manipulated by = a synthesizer and stores information about each linked pair of a CPC and a = WPC; all wave constant values and alias wave constant values can be accesse= d from the table. =E2=80=A2 An integer row_index to the wave constant signal table: it is set= up by a synthesizer and its initial value is 1. It is used as a row index = for a new link statement in the wave constant signal table and will be incr= eased by 1 after a synthesizer finishes the filling of the row during the s= ource code scanning.=20 Thank you for your reading. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.42.33.134 with SMTP id i6mr25953212icd.22.1425993436750; Tue, 10 Mar 2015 06:17:16 -0700 (PDT) X-Received: by 10.182.107.228 with SMTP id hf4mr276418obb.6.1425993436405; Tue, 10 Mar 2015 06:17:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!ecngs!feeder2.ecngs.de!news.glorb.com!hl2no8681962igb.0!news-out.google.com!db6ni44602igc.0!nntp.google.com!hl2no6025916igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 10 Mar 2015 06:17:16 -0700 (PDT) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4625ee40-c5a1-4d8b-9206-baebb356ffc2@googlegroups.com> Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: Andy Injection-Date: Tue, 10 Mar 2015 13:17:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8154 VHDL 2008 includes generics for packages. Check your tool documentation to see if it is supported yet (many do because generics are used for the fixed and floating point packages). Define a generic on your package that alters the values of the constants. You may need to initialize the constants with functions that uses the generic to select which value to return. If that generic value is passed down from a top-level generic, then you can override the default value in the tool command line. I usually set the default to the value for synthesis, and let the simulation scripts override it. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.97.2 with SMTP id dw2mr40008929obb.0.1426100451771; Wed, 11 Mar 2015 12:00:51 -0700 (PDT) X-Received: by 10.182.149.235 with SMTP id ud11mr348515obb.42.1426100451650; Wed, 11 Mar 2015 12:00:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no6844709igb.0!news-out.google.com!db6ni50310igc.0!nntp.google.com!hl2no6844700igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Mar 2015 12:00:51 -0700 (PDT) In-Reply-To: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.42; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.91.173.42 References: <13020785-c887-4a2d-ad58-64ee33061bbd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MODELSIM: Switch between two package libraries depending on environment From: "V." Injection-Date: Wed, 11 Mar 2015 19:00:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8155 On Friday, March 6, 2015 at 4:45:49 PM UTC-6, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; On Friday, March 6, 2015 at 4:45:49 PM UTC-6, V. wrote: > I am trying to switch between a simulation library and synthesis only library depending on my environment using Modelsim's predefined pragmas. > > I made two packages called intf_defn_sim and intf_defn . They have identical defines, but different values. > > > I was trying to do the following in order to switch between them: > > use work.intf_defn > -- synthesis translate_off > _sim > -- synthesis translate_on > .all; > > > ModelSim compile currently fails out of this as I think it doesn't recognize the "_" in front of the keyword sim. > > Is there a smarter way to do this? > > > > The following compiles without issue, but not quite what I want. > > use work > -- synthesis translate_off > .intf_defn > -- synthesis translate_on > .all; Gents, Appreciate all the great feedback. I should clarify that the main reason I'm trying to do this is because of some pretty long (and numerous) delays I've setup in my design (hundreds of milliseconds), and did not want to bog down my simulation. I seem to have some success by redefining these delays within the modules that use them using the synthesis pragma. So the shorter delays should only take affect in simulation, and for synthesis, it will use the longer delays defined in my package file. -- these defines override the longer delays -- synthesis translate_off constant DELAY : integer := 10; -- 10clk cycles instead of 10ms constant DELAY2 : integer := 50; .. .. constant DELAY30 : integer := 20; -- synthesis translate_on Is this is a viable approach? From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.43.135.194 with SMTP id ih2mr44529010icc.7.1426311907233; Fri, 13 Mar 2015 22:45:07 -0700 (PDT) X-Received: by 10.50.35.162 with SMTP id i2mr600710igj.4.1426311907186; Fri, 13 Mar 2015 22:45:07 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no11763263igb.0!news-out.google.com!db6ni50316igc.0!nntp.google.com!hl2no11763261igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 13 Mar 2015 22:45:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 14 Mar 2015 05:45:07 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8156 On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wrot= e: > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang wro= te: > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > >=20 > > > > I have filed a provisional patent application: "Systematic method o= f coding wave pipelined circuits in HDL". If it is proved correct, the pate= nt will introduce 1 keyword, 3 permanent constants, 1 concurrent statement = and four source code modules for a new library in HDL and thoroughly resolv= e a pending problem so that every digital designer can code wave-pipelined = circuits in HDL. > > > >=20 > > > > Here is the abstract of the invention: > > > >=20 > > > > The present invention classifies all critical paths into two ba= sic types: a series critical path and a feedback critical path, and divides= each of wave-pipelined circuits into two components: a static logic part, = called critical path component (CPC), and a dynamic logic part, formalized = into four wave-pipelining components (WPC) shared by all wave-pipelined cir= cuits. Each wave-pipelining ready code in HDL comprises two components: a W= PC instantiation and a CPC instantiation wire-connected and linked by a new= link statement. Each WPC has new wave constants which play the same role a= s generic constants do, but whose initial values are determined and assigne= d by a synthesizer after code analysis, so designers can use after-synthesi= zation information in their code before synthesization for wave-pipelining = technology. The responsibility of analyzing and manipulating wave-pipelinin= g ready code, generating and implementing wave-pipelined circuits on a desi= gn-wide or chip-wide scale in HDL is shifted from designers to synthesizers= . > > > >=20 > > > > Anyone who are interested in its content is welcome to send a email= request to the following email address: wtx wtx @ gmail . com with title "= Systematic" and he will receive the full documents: one specification, 9 dr= awings and one text file in VHDL. > > > >=20 > > > > If one reviews the files and feels that it would be a good thing to= recommend the application to his company to buy it, the first person to do= it after his recommended company does so will receive $10,000 commission f= ee. > > > >=20 > > > > Thank you. > > > >=20 > > > > Weng > > >=20 > > > Hi, > > > I want to add some introductions to what the wave-pipelined circuits = are and their status. > > >=20 > > > [0003] A synchronous digital system contains a lot of registers. V= alid data flow through successive registers from system input registers to = system output registers. All data flows are synchronous with triggering edg= es of a chip clock. For example, data flow from registers A to registers B,= from registers B to registers C and so on in a successive order on the sam= e clock cycle. > > > [0004] A path in a synchronous digital system is a route between a= ny neighboring registers connected by combinational logic. If the target ru= nning frequency for a digital design is predetermined, the upper limit of p= ropagating time for any paths is determined and has the inverse value of th= e target running frequency. A path is called a critical path if the time si= gnals take to propagate through it is beyond the predetermined propagating = time, and the time is called the path's critical time. If there are any cri= tical paths, digital designers must spend time reducing all critical times = by all means and eliminating all critical paths to meet the target running = frequency. > > > [0005] Wave-pipelining is a technology which completes an operatio= n that needs several clock cycles to propagate without intermediate registe= rs and with input data acceptable on every clock cycle. For example, in a c= onventional pipelining operation, data flow from registers A to registers D= through registers B and C to divide the critical path time into multiple s= maller intervals to meet the critical time: A to B to C to D; with wave-pip= elining, data flow through registers A and D without intermediate registers= B and C. Absolutely, wave-pipelining will reduce logic resource usage and = is superior to the conventional pipelining technology if it can be used. > > >=20 > > > Here are the most important inequalities involving wave-pipelining fr= om paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Burl= eson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6, n= o. 3, pp. 464-474, Sep. 1998. > > >=20 > > > [0018] Currently many memory chip manufacturers successfully use w= ave-pipelining in their memory chip products with higher rate outputs, redu= ced power consumption and logic resources; and a few scientists use FPGA ch= ips as a base to show some circuits can be done with wave-pipelining in iso= lated environments. Their works prove that the wave-pipelining is a very po= werful tool to reduce power consumption and logic resources. Now there are = two major existing obstacles preventing any ordinary digital designers from= using the wave-pipelining in HDL: > > > * The software algorithms making wave-pipelining successful, like Won= g and Klass algorithms and others, have already been developed and matured,= but ordinary digital designers have no means or resources to access to the= technology, because there are no international HDL standards on how synthe= sizer manufacturers incorporate those capabilities into their products. > > > * HDL needs the capabilities for digital designers to write wave-pipe= lining ready code for any number of critical paths on a design-wide or chip= -wide scale instead of in an isolated environment and the written code can = be identified, synthesized and used to generate wave-pipelined circuits by = any synthesizer in ASIC or FPGA, and they should be part of HDL standards.= =20 > > > [0019] The target of the present invention is: > > > * Invent a wave-pipelining coding system as new part of HDL standards= for designers to write wave-pipelining ready code which can be identified,= synthesized and used to generate wave-pipelined circuits by any synthesize= r in ASIC or FPGA. > > > * Make wave-pipelining ready code written based on the coding system = working with no extra logic generated, compared with independently written = wave-pipelined circuits, and with no code changes when switching from non-w= ave-pipelined mode to wave-pipelined mode or vice verse if all of wave-pipe= lining ready code meet wave-pipelining requirements.=20 > > > * Shift burdens of analyzing and manipulating wave-pipelining ready c= ode, generating and implementing wave-pipelined circuits on a design-wide o= r chip-wide scale in HDL from individual designers to synthesizer manufactu= rers. > > > [0020] If the coding system becomes new part of HDL standards all = synthesizer manufactures will automatically be forced to implement all well= -known wave-pipelining algorithms and techniques within their products, a c= ompetition will start for better implementations, making wave-pipelining te= chnique available to every digital designer in HDL. > > >=20 > > > Weng > >=20 > > Here I add some contents of the invention: > >=20 > > Main idea behind the present invention > >=20 > > [0057] The most difficult part coding all types of wave-pipelined ci= rcuits on a design-wide scale in HDL is that a wave-pipelined circuit code = always comprises two logic parts:=20 > > * A static logic part: it doesn't change if the number of series clock = cycles through the circuit changes and is unique for each of wave-pipelined= circuits. > > * A dynamic logic part: it does change if the number of series clock cy= cles through the circuit changes and is the same for one of groups of wave-= pipelined circuits. > > [0058] Every wave-pipelined circuit has its own change rules and tho= se changes are unknown to designers when they are writing code and will be = known to a synthesizer only after it has analyzed the circuit. > > [0059] The present invention classifies all critical paths into two = basic types: a series critical path and a feedback critical path, and divid= es each of wave-pipelined circuits into two components: one is static logic= part and called critical path component (CPC); another is dynamic logic pa= rt and formalized into four wave-pipelining components (WPC) shared by all = wave-pipelined circuits. Under the present invention each of standard wave-= pipelining ready code in HDL comprises two components: a WPC instantiation = and a CPC instantiation which are wire-connected and linked by a new concur= rent link statement. Each of four WPC embodiments has a group of new type w= ave constant, which plays the same role as a generic constant does, but who= se initial value is determined and assigned by a synthesizer after it has a= nalyzed the linked CPC component under slow mode and target mode, respectiv= ely, so designers can use after-synthesization information in their code be= fore synthesization in HDL for wave-pipelining technology. Following the in= structions of the present invention creates a situation that digital design= ers can write wave-pipelining ready code in HDL and the responsibility of a= nalyzing and manipulating wave-pipelining ready code, generating and implem= enting wave-pipelined circuits on a design-wide or chip-wide scale in HDL i= s shifted from individual designers to synthesizer manufacturers. > >=20 > > How the method works > >=20 > > [0060] The systematic method of coding wave-pipelined circuits in HD= L comprises following ten parts: > > 1. Define five signals, one counter, one switch and one table that will= be used when generating wave-pipelined circuits on a design-wide or chip-w= ide scale in HDL. > > 2. Define the interfaces of a CPC each of which encapsulates a critical= path's static logic part. > > 3. Define and implement four WPC embodiments in HDL each of which is a = critical path's dynamic logic part: a series_module, an input_delay_module,= a multiple_copy_module1 and a multiple_copy_module2. > > 4. Define one new keyword wave and three new wave constants which provi= de a means to dynamically transfer after-synthesization information to desi= gners' code before synthesization. > > 5. Define the methods of determining and searching for wave constant va= lues of a known WPC instantiation under slow mode and target mode, respecti= vely. > > 6. Define three versions of a concurrent link statement: link1, link2 a= nd link3, and rules on how they are used. > > 7. Define the pairing rules between a WPC and a CPC. > > 8. Define how a digital designer prepares wave-pipelining ready code sy= stematically. > > 9. Shift the responsibility of analyzing and manipulating wave-pipelini= ng ready code, generating and implementing wave-pipelined circuits on a des= ign-wide or chip-wide scale in HDL from individual designers to synthesizer= manufacturers. > > 10. Define how four WPC embodiments are simulated and debugged under an= y of current versions of a synthesizer in HDL. > > [0061] It is fair to put the burden of successfully generating wave-= pipelined circuits based on wave-pipelining ready code squarely on synthesi= zer manufacturers' shoulder if all necessary information is passed to a syn= thesizer. For example, with tens of papers claiming that successful wave-pi= pelined circuits are implemented in FPGA chips in an isolated environment, = it is the responsibility of FPGA synthesizers to be capable of generating t= hose wave-pipelined circuits in a design-wide environment without designers= ' further involvements, a process similar for them to the task of generatin= g a circuit with the highest running frequency and minimum used resources i= f possible for any normal digital design code. > >=20 > > Thank you for your reading. >=20 > Here are more contents. >=20 > Definitions of wave-pipelining component and critical path component >=20 > [0062] A design component is called a critical path component (CPC) if= it is an entity (a term in VHDL-2002) in HDL and encapsulates the static l= ogic part of a critical path which is to be wave-pipelined circuit. There a= re two types of CPCs:=20 > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99s = static logic part. > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2=80= =99s static logic part.=20 >=20 > [0063] A CPC also refers to a CPC instantiation when it will not be mi= sunderstood. The required interfaces of both a series CPC and a feedback CP= C are always the same. The combinational logic of a CPC may be located with= in or outside of the component and there is no limit on it.=20 >=20 > [0064] A design component is called a wave-pipelining component (WPC) = if it is an entity in HDL, provided by HDL in a new wave-pipelining system = library and used to generate a critical path=E2=80=99s dynamic logic part, = i.e., to generate output data valid signal and write enable signals to the = input and output registers of a critical path.=20 >=20 > [0065] There are three types of WPC:=20 > =E2=80=A2 A series_module is used to connect to a series CPC with input d= ata acceptable on every clock cycle. > =E2=80=A2 An input_delay_module is used to connect to a series or feedbac= k CPC with input data acceptable on every one or more clock cycle. > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to c= onnect to multiple copied series or feedback CPCs with input data acceptabl= e on every clock cycle. >=20 > [0066] A WPC also refers to a WPC instantiation when it will not be mi= sunderstood. Later multiple_copy_module refers to either of multiple_copy_m= odule1 and multiple_copy_module2. >=20 > A synthesizer=E2=80=99s new signals, switch and table >=20 > [0067] A synthesizer that is able of handling wave-pipelining needs si= x signals, one switch, one table and the table=E2=80=99s row index to help = finish its job: > =E2=80=A2 A floating signal target_running_frequency: it is set up by a d= esigner and the target running frequency under which a design finally runs. > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and i= ts initial value is deasserted. A synthesizer will generate related circuit= files for a design under slow mode for slow mode hardware testing if gener= ate_circuit is asserted and no errors are detected after a synthesization, = or will not otherwise. A synthesizer will always generate related circuit f= iles for a design under target mode for target mode hardware testing if no = errors are detected after a synthesization. > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and it= s initial value is deasserted. Assert the bit if a CPC is being analyzed an= d determined to have feedbacks, and deassert it after the analysis is finis= hed. > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer an= d its initial value is deasserted. Assert the bit if a designer wants to ke= ep all CPC new circuits automatically and successfully modified by a synthe= sizer under target mode unchanged under slow mode when he is switching to s= ynthesize the same design from under target mode to under slow mode and the= related code doesn=E2=80=99t change, or deassert it otherwise. The bit pro= vides a method for a designer to check if the new automatically and success= fully modified circuits by a synthesizer don=E2=80=99t change basic logic.= =20 > =E2=80=A2 An integer signal parent_series_clock_number: it is set up by a= synthesizer and Its initial value is zero. When the instantiation of a WPC= delay_input_module or multiple_copy_module is being analyzed and executed = its series_clock_number value is stored in parent_series_clock_number, and = it is cleared to zero when the execution is finished. > =E2=80=A2 An integer signal start_number: it is set up by a synthesizer a= nd used when the synthesizer determines that a CPC cannot meet the wave-pip= elining requirements with input data acceptable on every clock cycle and th= e CPC is linked with a WPC input_delay_module or multiple_copy_module. The = start_number is made equal to 2 if a WPC multiple_copy_module is linked or = to feedback_clock_number if a WPC input_delay_module is linked as the start= ing value of wave constant input_clock_number or multiple_copy_number. > =E2=80=A2 A bit switch running_mode: it is set up by a designer and it ha= s two valid values with slow mode being its initial value: > o Slow mode: under slow mode a digital designer designs his code, a desig= n is synthesized, simulated, and hardware tested under the following assump= tions: > =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs u= nder slow running frequency. > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > =EF=82=A7 No multiple copied CPCs are generated. > o Target mode: under target mode a design is synthesized, simulated, hard= ware tested and finally runs under predetermined target running frequency, = and its implementation is determined and generated by a synthesizer under t= he following assumptions: > =EF=82=A7 Signals take one or more clock cycle to propagate through any o= f CPCs as designed. > =EF=82=A7 Each of CPCs has input data acceptable on every one or more clo= ck cycle as wave-pipelining ready code indicates and it is necessary. > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready cod= e indicates and it is necessary. > =E2=80=A2 A wave constant signal table: it is generated and manipulated b= y a synthesizer and stores information about each linked pair of a CPC and = a WPC; all wave constant values and alias wave constant values can be acces= sed from the table. > =E2=80=A2 An integer row_index to the wave constant signal table: it is s= et up by a synthesizer and its initial value is 1. It is used as a row inde= x for a new link statement in the wave constant signal table and will be in= creased by 1 after a synthesizer finishes the filling of the row during the= source code scanning.=20 >=20 > Thank you for your reading. >=20 > Weng Here are more contents. It shows how a complicated problem is resolved by c= reative ideas. New keyword wave and wave constant in HDL [0068] When writing wave-pipelining code, digital designers don=E2=80=99= t know how many clock cycles signals need to propagate through a critical p= ath, and to finish their jobs, it may take several working cycles for them = manually to adjust their code to make a wave-pipelined circuit working. Thi= s method is not feasible on a design-wide or chip-wide scale, because a des= ign may have 100 or more critical paths to be wave-pipelined circuits and t= here is no guarantee for designers to perfectly remember which is finished = and which is not, and most importantly, synthesizers are left aside of the = business of wave-pipelining, giving no help at all. One of obstacles using = wave-pipelining in HDL is how to establish a communication channel between = a synthesizer and digital designers to provide the following essential func= tions: =E2=80=A2 How a designer can use after-synthesization information to write = code for wave-pipelined circuits before they have been synthesized in HDL f= or wave-pipelining technology. This function is not necessary for successfu= lly generating a wave-pipelined circuit, but beneficial to implement a comp= lex one. =E2=80=A2 If all pieces of wave-pipelining ready code are written, a design= has passed simulations and/or hardware testing under slow mode perfectly, = and a synthesizer certifies that all wave-pipelining requirements are met w= ith input data acceptable on every one or more clock cycle and no errors ar= e detected after a synthesization, then correct full design circuits can be= generated under target mode and work as designed with no code change durin= g the switching from slow mode to target mode or vice verse on a design-wid= e or chip-wide scale. This function is critical and essential for successf= ully generating all wave-pipelined circuits on a design-wide or chip-wide s= cale in HDL. [0069] New keyword wave and three wave constants are introduced to resol= ve the problem. In the following listing characters in bold type are new su= ggested definitions based on VHDL-2002. entity_declaration ::=3D=20 entity identifier is entity_header entity_declarative_part [begin entity_statement_part ] end [ entity ] [ entity_simple_name ] ; entity_header ::=3D [formal_generic_clause ] [formal_port_clause ] generic_clause ::=3D generic ( generic_list ) ; generic_list ::=3D generic_interface_list interface_list ::=3D interface_element { ; interface_element } interface_element ::=3D interface_declaration interface_declaration ::=3D interface_constant_declaration |interface_wave_constant_declaration | interface_signal_declaration | interface_variable_declaration | interface_file_declaration interface_constant_declaration ::=3D [constant] identifier_list : [ in] subtype_indication [ :=3D static_express= ion ] interface_wave_constant_declaration ::=3D wave [constant] wave_constant_list : [ in ] subtype_indication [ :=3D static_expression ] wave_constant_list ::=3D=20 wave_constant_element { , wave_constant_element } wave_constant_element ::=3D=20 wave_constant |internal_wave_constant wave_constant ::=3D series_clock_number | input_clock_number | multiple_copy_number internal_wave_constant ::=3D one_hot entity_declarative_part ::=3D { entity_declarative_item } entity_declarative_item ::=3D subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | alias_wave_constant_declaration | signal_declaration |shared_variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration architecture_body ::=3D architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end[ architecture ] [ architecture_simple_name ] ; architecture_declarative_part ::=3D { block_declarative_item } block_declarative_item ::=3D subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | alias_wave_constant_declaration | signal_declaration | shared_variable_declaration | file_declaration | alias_declaration | component_declaration | attribute_declaration | attribute_specification | configuration_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration constant_declaration ::=3D constant identifier_list : subtype_indication [ :=3D expression ] ; alias_wave_constant_declaration ::=3D wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 wave_constant ; alias_wave_constant_list ::=3D alias_wave_constant { , alias_wave_constant } alias_wave_constant ::=3D identifier [0070] The set of following rules is called wave constant mechanism: =E2=80=A2 There are three wave constants related to wave-pipelining techniq= ue: series_clock_number, input_clock_number and multiple_copy_number.=20 =E2=80=A2 A wave constant can only be declared in the generic_clause of the= entity definition of a WPC embodiment, plays the same role as a generic co= nstant declared in the same place does except that it has actual initial va= lue 1 under slow mode, and actual initial value equal to or greater than 1 = determined and assigned by a synthesizer under target mode, and the static = expression in an interface wave constant declaration is always ignored. =E2=80=A2 A WPC instantiation must not include corresponding association el= ement with a formal wave constant in the generic map aspect.=20 =E2=80=A2 Any wave constant declared in a WPC definition is accessible by d= esigners through an alias wave constant declaration. =E2=80=A2 An alias wave constant declaration identifies a list of alias wav= e constants which are assigned a wave constant. Each alias wave constant mu= st be linked with a WPC instantiation through a link statement and shares t= he wave constant value of the linked WPC instantiation for testing, debuggi= ng or implementing purpose. An alias wave constant plays the same role as a= normal constant declared in the same place does.=20 =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants and= output signals as its own input signal, but must have no input signals whi= ch are related to any unrelated WPC instantiation=E2=80=99s wave constants. =E2=80=A2 The internal wave constant one_hot is used internally by a synthe= sizer to optimize the implementation of a WPC and not accessible by designe= rs.=20 =E2=80=A2 A synthesizer has its discretion to determine internal wave const= ant one_hot value based on the environment and the consideration of its pro= duction technique used unless a WPC input_delay_module has its R_O output c= onnected in which case one_hot will be =E2=80=981=E2=80=99 in order to gene= rate valid R_O output signal.=20 Thank you for your reading. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.125.100 with SMTP id mp4mr25503409obb.21.1426503171890; Mon, 16 Mar 2015 03:52:51 -0700 (PDT) X-Received: by 10.140.21.113 with SMTP id 104mr901685qgk.11.1426503171771; Mon, 16 Mar 2015 03:52:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!hl2no12940477igb.0!news-out.google.com!q90ni145qgd.1!nntp.google.com!z107no1944170qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Mar 2015 03:52:51 -0700 (PDT) In-Reply-To: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:9c80:85be:2c27:3b39; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:9c80:85be:2c27:3b39 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Mon, 16 Mar 2015 10:52:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8157 On Saturday, March 14, 2015 at 1:45:11 AM UTC-4, Weng Tianxiang wrote: > Here are more contents. It shows how a complicated problem is resolved by > creative ideas. > > [0069] New keyword wave and three wave constants are introduced to resolve > the problem. In the following listing characters in bold type are new suggested > definitions based on VHDL-2002. > Do you have any data to support your contention that your solution actually solves the problem of designer productivity in implementing wave-pipeline code? Kevin From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.224.42 with SMTP id qz10mr71582980pac.0.1426616123525; Tue, 17 Mar 2015 11:15:23 -0700 (PDT) X-Received: by 10.50.49.2 with SMTP id q2mr1822ign.12.1426616123485; Tue, 17 Mar 2015 11:15:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no478095igj.0!news-out.google.com!qk8ni59857igc.0!nntp.google.com!z20no478086igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Mar 2015 11:15:22 -0700 (PDT) In-Reply-To: <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 17 Mar 2015 18:15:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8158 On Monday, March 16, 2015 at 3:52:56 AM UTC-7, KJ wrote: > On Saturday, March 14, 2015 at 1:45:11 AM UTC-4, Weng Tianxiang wrote: >=20 > > Here are more contents. It shows how a complicated problem is resolved = by=20 > > creative ideas. > >=20 > =20 > > [0069] New keyword wave and three wave constants are introduced to r= esolve=20 > > the problem. In the following listing characters in bold type are new s= uggested=20 > > definitions based on VHDL-2002. > >=20 >=20 > Do you have any data to support your contention that your solution actual= ly solves the problem of designer productivity in implementing wave-pipelin= e code? >=20 > Kevin KJ, I didn't invent any method to generate correct wave pipelined circuits, wha= t I did is I invented a systematic method for all digital designers to be a= ble to write any types of wave pipelined circuits in HDL and shifted the re= sponsibility to generate such circuits from individual designers to compile= rs!!!=20 So your question is pointless. Here is a historical example: Before HDL introduction, everyone had to write logic to make 32-bit*32-bit = multiplication if he needed to do it. After HDL and multiple sign "*' introduction, everyone now can do 32*32 mul= tiplication using multiple sign "*'. What difference between my invention and multiple sign "*' introduction is = that the idea behind my method is very complex, non-obvious so that after 1= 967 first paper published on wave pipelined circuits, no one had figured ou= t how it can be done in HDL. The invention is 65 pages long, a jumbo invention according to USPTO standa= rds, and describes all rules for designers and compilers to observe to make= such things happening harmoniously without any defects. The results of my invention are: 1. Every digital designer can write wave pipelined circuits in HDL if the i= nvention is adopted by HDL. 2. Every wave pipelined circuit published publicly, implemented or non-impl= emented, ASIC or FPGA, can be implemented by any compiler without any doubt= . 3. The method to write the circuit for digital designers is both very simpl= e and comprehensive. The method will not generate any extra logic, compared= to the original method. 4. What a designer needs to do is very simple: tell compiler that this is a= wave pipelined circuit design and generate it for me, and I have tools to = check if you do a correct thing and if you cannot do it, let me know what I= should do to improve the successful rate. Please be patient to see my posting which will finally publish all related = source code for public to check if my claims are correct.=20 After that you may have more rights to comment and I will welcome any comme= nts. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.236.8.69 with SMTP id 45mr56522974yhq.39.1426642008035; Tue, 17 Mar 2015 18:26:48 -0700 (PDT) X-Received: by 10.140.98.7 with SMTP id n7mr1067261qge.13.1426642007994; Tue, 17 Mar 2015 18:26:47 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h3no3128604qgf.1!news-out.google.com!f74ni149qge.0!nntp.google.com!h3no3128603qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 17 Mar 2015 18:26:47 -0700 (PDT) In-Reply-To: <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:7510:8352:f8d2:dfbc; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:7510:8352:f8d2:dfbc References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Wed, 18 Mar 2015 01:26:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5436 X-Received-Body-CRC: 1854744208 Xref: mx02.eternal-september.org comp.lang.vhdl:8159 On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: >=20 > KJ, > I didn't invent any method to generate correct wave pipelined circuits,= =20 I never said or implied that you did > what I did is I invented a systematic method for all digital designers to= be=20 > able to write any types of wave pipelined circuits in HDL and shifted the= =20 > responsibility to generate such circuits from individual designers to > compilers!!!=20 >=20 And my question was simply: "Do you have any data to support your contentio= n that your solution actually solves the problem of designer productivity i= n implementing wave-pipeline code?"=20 >=20 > So your question is pointless. >=20 Sure...if you have nothing to support your position, try to blame it on the= question. So I'll have to assume at this point that this you have nothing= to back up your claims, just like you had nothing to backup your claims wi= th 'orif' which I showed to be incorrect. >=20 > What difference between my invention and multiple sign "*' introduction i= s=20 > that the idea behind my method is very complex, non-obvious so that after= =20 > 1967 first paper published on wave pipelined circuits, no one had figured= out=20 > how it can be done in HDL. >=20 But does your method have any practical utility? You say it does, and mayb= e you're right, but you haven't demonstrated that with any of your posting = here. To get a patent you may not need to show this, but since you're post= ing here to an open forum you should consider that without practical utilit= y what you're posting isn't interesting reading. =20 Maybe you haven't gotten to that part of showing the utility even after all= of the postings in this newsgroup, or maybe it's because this idea is like= your idea for 'orif' which has little or no real utility as I demonstrated= on one of the sidebars of this thread. > The invention is 65 pages long, a jumbo invention according to USPTO=20 > standards, and describes all rules for designers and compilers to observe= to=20 > make such things happening harmoniously without any defects. >=20 > The results of my invention are: > 1. Every digital designer can write wave pipelined circuits in HDL if the= =20 > invention is adopted by HDL. >=20 Without any data to backup what you say...it becomes easy to claim most any= thing > 2. Every wave pipelined circuit published publicly, implemented or non- > implemented, ASIC or FPGA, can be implemented by any compiler without any= =20 > doubt. >=20 Can you provide evidence of this? > 3. The method to write the circuit for digital designers is both very sim= ple=20 > and comprehensive. The method will not generate any extra logic, compared= to=20 > the original method. >=20 You're contradicting yourself. A few lines up you said "no one had figured= out how it can be done in HDL" and yet now you say that there is some "ori= ginal method". And again...can you demonstrate it or can you only claim th= at it must be? > 4. What a designer needs to do is very simple: tell compiler that this is= a=20 > wave pipelined circuit design and generate it for me, and I have tools to= =20 > check if you do a correct thing and if you cannot do it, let me know what= I=20 > should do to improve the successful rate. >=20 What if I tell it that it is a wave pipelined circuit when in fact it is no= t? > Please be patient to see my posting which will finally publish all relate= d=20 > source code for public to check if my claims are correct.=20 >=20 OK > After that you may have more rights to comment and I will welcome any=20 > comments. I have the same 'rights' to post and comment here as you do. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.157.194 with SMTP id wo2mr77352548pab.17.1426714288191; Wed, 18 Mar 2015 14:31:28 -0700 (PDT) X-Received: by 10.50.40.9 with SMTP id t9mr156176igk.7.1426714288144; Wed, 18 Mar 2015 14:31:28 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no1315655igj.0!news-out.google.com!qk8ni61499igc.0!nntp.google.com!z20no1315651igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 18 Mar 2015 14:31:27 -0700 (PDT) In-Reply-To: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <52b3490c-3579-4716-aa9f-c54001dc1137@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Wed, 18 Mar 2015 21:31:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8160 On Wednesday, March 18, 2015 at 2:26:49 PM UTC+13, KJ wrote: > On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: > > After that you may have more rights to comment and I will welcome any > > comments. > > I have the same 'rights' to post and comment here as you do. > > Kevin Jennings I'd echo Kevin's sentiments. If you want to control the story do your own blog or website. In the mean time your comportment in this thread doesn't portray you nor your questionable-yet-not-to-be-questioned ideas in a particularly good light. From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.236.220.74 with SMTP id n70mr89581169yhp.40.1426862976166; Fri, 20 Mar 2015 07:49:36 -0700 (PDT) X-Received: by 10.50.85.17 with SMTP id d17mr66214igz.7.1426862976139; Fri, 20 Mar 2015 07:49:36 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!h3no3707624qgf.1!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2156043igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 07:49:35 -0700 (PDT) In-Reply-To: <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <2b48b9b7-ce04-4c38-9b58-c8d0b6c0b70a@googlegroups.com> <2c3f6d18-b4e8-4bd1-9213-b5b24c7439ef@googlegroups.com> <411022ce-f2b6-49e9-8a32-eb5f55fc0c79@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Fri, 20 Mar 2015 14:49:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 7160 X-Received-Body-CRC: 424211717 Xref: mx02.eternal-september.org comp.lang.vhdl:8161 On Tuesday, March 17, 2015 at 6:26:49 PM UTC-7, KJ wrote: > On Tuesday, March 17, 2015 at 2:15:26 PM UTC-4, Weng Tianxiang wrote: > >=20 > > KJ, > > I didn't invent any method to generate correct wave pipelined circuits,= =20 >=20 > I never said or implied that you did >=20 > > what I did is I invented a systematic method for all digital designers = to be=20 > > able to write any types of wave pipelined circuits in HDL and shifted t= he=20 > > responsibility to generate such circuits from individual designers to > > compilers!!!=20 > >=20 >=20 > And my question was simply: "Do you have any data to support your content= ion that your solution actually solves the problem of designer productivity= in implementing wave-pipeline code?"=20 >=20 > >=20 > > So your question is pointless. > >=20 > Sure...if you have nothing to support your position, try to blame it on t= he question. So I'll have to assume at this point that this you have nothi= ng to back up your claims, just like you had nothing to backup your claims = with 'orif' which I showed to be incorrect. >=20 > > >=20 > > What difference between my invention and multiple sign "*' introduction= is=20 > > that the idea behind my method is very complex, non-obvious so that aft= er=20 > > 1967 first paper published on wave pipelined circuits, no one had figur= ed out=20 > > how it can be done in HDL. > >=20 >=20 > But does your method have any practical utility? You say it does, and ma= ybe you're right, but you haven't demonstrated that with any of your postin= g here. To get a patent you may not need to show this, but since you're po= sting here to an open forum you should consider that without practical util= ity what you're posting isn't interesting reading. > =20 > Maybe you haven't gotten to that part of showing the utility even after a= ll of the postings in this newsgroup, or maybe it's because this idea is li= ke your idea for 'orif' which has little or no real utility as I demonstrat= ed on one of the sidebars of this thread. >=20 > > The invention is 65 pages long, a jumbo invention according to USPTO=20 > > standards, and describes all rules for designers and compilers to obser= ve to=20 > > make such things happening harmoniously without any defects. > >=20 > > The results of my invention are: > > 1. Every digital designer can write wave pipelined circuits in HDL if t= he=20 > > invention is adopted by HDL. > >=20 >=20 > Without any data to backup what you say...it becomes easy to claim most a= nything >=20 > > 2. Every wave pipelined circuit published publicly, implemented or non- > > implemented, ASIC or FPGA, can be implemented by any compiler without a= ny=20 > > doubt. > >=20 >=20 > Can you provide evidence of this? >=20 > > 3. The method to write the circuit for digital designers is both very s= imple=20 > > and comprehensive. The method will not generate any extra logic, compar= ed to=20 > > the original method. > >=20 >=20 > You're contradicting yourself. A few lines up you said "no one had figur= ed out how it can be done in HDL" and yet now you say that there is some "o= riginal method". And again...can you demonstrate it or can you only claim = that it must be? >=20 > > 4. What a designer needs to do is very simple: tell compiler that this = is a=20 > > wave pipelined circuit design and generate it for me, and I have tools = to=20 > > check if you do a correct thing and if you cannot do it, let me know wh= at I=20 > > should do to improve the successful rate. > >=20 >=20 > What if I tell it that it is a wave pipelined circuit when in fact it is = not? >=20 > > Please be patient to see my posting which will finally publish all rela= ted=20 > > source code for public to check if my claims are correct.=20 > >=20 >=20 > OK >=20 > > After that you may have more rights to comment and I will welcome any= =20 > > comments. >=20 > I have the same 'rights' to post and comment here as you do. >=20 > Kevin Jennings KJ, "Critical questions are inventions' mother." Einstein Thank you for your critical comments.=20 The reason is that your comments are driving me to file another patent appl= ication on the same wave-pipelined circuits theory to fully support my theo= ry and meet your curiosity:=20 1. It will provide an example implementation used for a 4-core processor en= vironment with source code included. The included source code is not necess= ary, but will certainly accelerate the process of understanding, distributi= ng, helping and correct assessing my patent applications. 2. It will fully describe using the implementable example why my invented m= ethod really resolves the 50-year pending problem and makes it successful w= ithout failure with sharp-point targeting and answering all questionable-ye= t-not-to-be-questioned ideas. I will continue publishing all remaining part of my patent application when= I am available, including all related source code of 52,089 bytes, about 1= ,100 lines, for public verification, because that invention is targeted and= assumed to be incorporated into all HDL language, and public has the right= s to know it. If any readers find any questionable-yet-not-to-be-questioned ideas while r= eading my application text, you may immediately ask me the questions after = my posting and I will immediately answer your doubts without any delay. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.248.227 with SMTP id yp3mr93320030obc.22.1426867957839; Fri, 20 Mar 2015 09:12:37 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr80409igb.1.1426867957814; Fri, 20 Mar 2015 09:12:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z20no1543177igj.0!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2193647igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 09:12:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Need: DevOps Engineer in EI Segundo, CA From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 16:12:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3371 X-Received-Body-CRC: 2892403991 Xref: mx02.eternal-september.org comp.lang.vhdl:8162 Hi, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: DevOps Engineer Location: EI Segundo, CA Duration: 12 Months Required Qualifications: 5-7 years DevOps, IT, and/or software engineering work experience Experienced in the installation, configuration and administration of Red Hat Enterprise and its derivatives Rich DevOps skills across SCM, Static Code Analyzer, Build and Release, Continuous Integration tools and frameworks such as, SVN, GIT, ANT, MVN, Sonar etc Deep understanding and practical working knowledge of Puppet, Chef, Jenkins Ability to use a wide variety of open source technologies and cloud services (particularly Amazon Web Services and OpenStack) Working understanding of code and script (Bash, Python, Perl and/or Ruby) Knowledge of IP networking, VPN's, DNS, load balancing and firewalling Familiar with implementing Continuous Integration, Delivery and Deployment practices Experience with automated testing tools Familiarity with some of the Big Data tools like Hadoop, Splunk Experience with relational & NoSQL data stores, such as MongoDB, CouchDB etc Excellent verbal and written communication skills, with the ability to work effectively across internal and external organizations Bachelor's degree in computer science or related field or equivalent experience DevOps engineer responsibilities/activities : Automating software deployment and configuration management Release (with tools such as jenkins, travis, teamcity) Configuration management and infrastructure provisioning (with tools such as puppet, chef, ansible, cfengine) Orchestration (with tools such as zookeeper, noah, mesos) Revision control source code repositories (such as Git, SVN, Perforce) Developing and supporting deployment and rollback tools and processes Monitoring (with tools such as Nagios, Incinga, SiteScope) Virtualization and containerization (with tools such as AWS, OpenStack, vagrant, docker) Participate in capacity planning, provisioning and scaling of the application infrastructure Ability to develop High-Level Design interaction diagrams, system functionality changes, data model, data flow, high-level interface specifications Thanks & Regards, Lalitha.K ksivalalitha@sageitinc.net panand@sageitinc.net From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.246.37 with SMTP id xt5mr89161034obc.25.1426879011175; Fri, 20 Mar 2015 12:16:51 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr386447igt.17.1426879011124; Fri, 20 Mar 2015 12:16:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!z20no2276746igj.0!news-out.google.com!qk8ni62932igc.0!nntp.google.com!z20no1607034igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 12:16:50 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e143f7e-38f5-4799-88c8-dc1735460274@googlegroups.com> Subject: AWS Administrator - Lexington, Kentucky - 12 Months From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 19:16:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8163 Hi , This is Lalitha from SAGE IT INC. Hope you are doing great. Please send me your updated resume if you're interested for this position. AWS Administrator Lexington, Kentucky 6 to 12 Months Client : Wipro / Lexmark Job Description: * Experience: 8-10 yrs * End to end Amazon Web Service knowledge & experience * Must have experience as AWS Admin * Must Have skills - AWS (VPC, EC2, Redshift, RDS, S3, SWF, SQS), Python/Java * Good to have Skills - Hadoop/EMR Thanks Lalitha Reddy K ksivalalitha@sageitinc.net From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.50.43.229 with SMTP id z5mr5951436igl.3.1426885536199; Fri, 20 Mar 2015 14:05:36 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr401902igl.8.1426885536182; Fri, 20 Mar 2015 14:05:36 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z20no1636505igj.0!news-out.google.com!db6ni58136igc.0!nntp.google.com!z20no2317749igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Mar 2015 14:05:35 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Need: Unix Admin in EI Segundo, CA From: latha.karnti@gmail.com Injection-Date: Fri, 20 Mar 2015 21:05:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 39 Xref: mx02.eternal-september.org comp.lang.vhdl:8164 Hi, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: Unix Admin Location: EI Segundo,CA Duration: 6+ Months Responsibilities will include: Analysis of the organization's business needs with the capability to translate LoB requirements for automation use cases into design and implementation plans Engineering and architectural development of robust Operating system, middleware and application configuration solution. Proactive review of environment to suggest/develop new configuration management policies Qualifications: Experience in medium to large enterprise or service provider of a distributed platform Experience implementing highly automated data driven automation. Minimum of 6+ years' experience of Redhat in a large, mission critical global production enterprise(5000+ servers). Minimum of 2+ years professional experience working with CFEngine or equivalent (Puppet, Chef) Experience of one or both of Solaris or AIX Strong understanding of Unix Security and LDAP Understanding of security best practices for multi-tiered operating systems Advanced scripting abilities with Shell and Perl Programming development skills with C, C++ Ability to adapt to a dynamic work environment and must be able to multi-task and work with minimal guidance Effective written and verbal communication skills Results driven, ensuring short-term goals are achieved while supporting long-term initiatives with an appropriate sense of urgency Desired Skills/Product Skills: Configuration Management: CFEngine 3, Chef or Puppet Operating System: Redhat 5/6/7, AIX 5/6/7 Solaris 10 Experience in database technologies Experience in scripting and automation such as: PERL, Shell (Bourne, Korn, C-Shell), JAVA, JavaScript, HTML and PHP Thanks & Regards, Anand Executive-Talent Acquisition Direct: 972-996-0650 Ext: 339 panand@sageitinc.net www.sageitinc.com From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.68.209.164 with SMTP id mn4mr5185222pbc.8.1426976610715; Sat, 21 Mar 2015 15:23:30 -0700 (PDT) X-Received: by 10.50.110.101 with SMTP id hz5mr56046igb.6.1426976610658; Sat, 21 Mar 2015 15:23:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!z20no2855641igj.0!news-out.google.com!qk8ni62932igc.0!nntp.google.com!z20no1972833igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 21 Mar 2015 15:23:29 -0700 (PDT) In-Reply-To: <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 21 Mar 2015 22:23:30 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8165 On Friday, March 13, 2015 at 10:45:11 PM UTC-7, Weng Tianxiang wrote: > On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang wr= ote: > > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang w= rote: > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > >=20 > > > > > I have filed a provisional patent application: "Systematic method= of coding wave pipelined circuits in HDL". If it is proved correct, the pa= tent will introduce 1 keyword, 3 permanent constants, 1 concurrent statemen= t and four source code modules for a new library in HDL and thoroughly reso= lve a pending problem so that every digital designer can code wave-pipeline= d circuits in HDL. > > > > >=20 > > > > > Here is the abstract of the invention: > > > > >=20 > > > > > The present invention classifies all critical paths into two = basic types: a series critical path and a feedback critical path, and divid= es each of wave-pipelined circuits into two components: a static logic part= , called critical path component (CPC), and a dynamic logic part, formalize= d into four wave-pipelining components (WPC) shared by all wave-pipelined c= ircuits. Each wave-pipelining ready code in HDL comprises two components: a= WPC instantiation and a CPC instantiation wire-connected and linked by a n= ew link statement. Each WPC has new wave constants which play the same role= as generic constants do, but whose initial values are determined and assig= ned by a synthesizer after code analysis, so designers can use after-synthe= sization information in their code before synthesization for wave-pipelinin= g technology. The responsibility of analyzing and manipulating wave-pipelin= ing ready code, generating and implementing wave-pipelined circuits on a de= sign-wide or chip-wide scale in HDL is shifted from designers to synthesize= rs. > > > > >=20 > > > > > Anyone who are interested in its content is welcome to send a ema= il request to the following email address: wtx wtx @ gmail . com with title= "Systematic" and he will receive the full documents: one specification, 9 = drawings and one text file in VHDL. > > > > >=20 > > > > > If one reviews the files and feels that it would be a good thing = to recommend the application to his company to buy it, the first person to = do it after his recommended company does so will receive $10,000 commission= fee. > > > > >=20 > > > > > Thank you. > > > > >=20 > > > > > Weng > > > >=20 > > > > Hi, > > > > I want to add some introductions to what the wave-pipelined circuit= s are and their status. > > > >=20 > > > > [0003] A synchronous digital system contains a lot of registers.= Valid data flow through successive registers from system input registers t= o system output registers. All data flows are synchronous with triggering e= dges of a chip clock. For example, data flow from registers A to registers = B, from registers B to registers C and so on in a successive order on the s= ame clock cycle. > > > > [0004] A path in a synchronous digital system is a route between= any neighboring registers connected by combinational logic. If the target = running frequency for a digital design is predetermined, the upper limit of= propagating time for any paths is determined and has the inverse value of = the target running frequency. A path is called a critical path if the time = signals take to propagate through it is beyond the predetermined propagatin= g time, and the time is called the path's critical time. If there are any c= ritical paths, digital designers must spend time reducing all critical time= s by all means and eliminating all critical paths to meet the target runnin= g frequency. > > > > [0005] Wave-pipelining is a technology which completes an operat= ion that needs several clock cycles to propagate without intermediate regis= ters and with input data acceptable on every clock cycle. For example, in a= conventional pipelining operation, data flow from registers A to registers= D through registers B and C to divide the critical path time into multiple= smaller intervals to meet the critical time: A to B to C to D; with wave-p= ipelining, data flow through registers A and D without intermediate registe= rs B and C. Absolutely, wave-pipelining will reduce logic resource usage an= d is superior to the conventional pipelining technology if it can be used. > > > >=20 > > > > Here are the most important inequalities involving wave-pipelining = from paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. Bu= rleson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. 6,= no. 3, pp. 464-474, Sep. 1998. > > > >=20 > > > > [0018] Currently many memory chip manufacturers successfully use= wave-pipelining in their memory chip products with higher rate outputs, re= duced power consumption and logic resources; and a few scientists use FPGA = chips as a base to show some circuits can be done with wave-pipelining in i= solated environments. Their works prove that the wave-pipelining is a very = powerful tool to reduce power consumption and logic resources. Now there ar= e two major existing obstacles preventing any ordinary digital designers fr= om using the wave-pipelining in HDL: > > > > * The software algorithms making wave-pipelining successful, like W= ong and Klass algorithms and others, have already been developed and mature= d, but ordinary digital designers have no means or resources to access to t= he technology, because there are no international HDL standards on how synt= hesizer manufacturers incorporate those capabilities into their products. > > > > * HDL needs the capabilities for digital designers to write wave-pi= pelining ready code for any number of critical paths on a design-wide or ch= ip-wide scale instead of in an isolated environment and the written code ca= n be identified, synthesized and used to generate wave-pipelined circuits b= y any synthesizer in ASIC or FPGA, and they should be part of HDL standards= .=20 > > > > [0019] The target of the present invention is: > > > > * Invent a wave-pipelining coding system as new part of HDL standar= ds for designers to write wave-pipelining ready code which can be identifie= d, synthesized and used to generate wave-pipelined circuits by any synthesi= zer in ASIC or FPGA. > > > > * Make wave-pipelining ready code written based on the coding syste= m working with no extra logic generated, compared with independently writte= n wave-pipelined circuits, and with no code changes when switching from non= -wave-pipelined mode to wave-pipelined mode or vice verse if all of wave-pi= pelining ready code meet wave-pipelining requirements.=20 > > > > * Shift burdens of analyzing and manipulating wave-pipelining ready= code, generating and implementing wave-pipelined circuits on a design-wide= or chip-wide scale in HDL from individual designers to synthesizer manufac= turers. > > > > [0020] If the coding system becomes new part of HDL standards al= l synthesizer manufactures will automatically be forced to implement all we= ll-known wave-pipelining algorithms and techniques within their products, a= competition will start for better implementations, making wave-pipelining = technique available to every digital designer in HDL. > > > >=20 > > > > Weng > > >=20 > > > Here I add some contents of the invention: > > >=20 > > > Main idea behind the present invention > > >=20 > > > [0057] The most difficult part coding all types of wave-pipelined = circuits on a design-wide scale in HDL is that a wave-pipelined circuit cod= e always comprises two logic parts:=20 > > > * A static logic part: it doesn't change if the number of series cloc= k cycles through the circuit changes and is unique for each of wave-pipelin= ed circuits. > > > * A dynamic logic part: it does change if the number of series clock = cycles through the circuit changes and is the same for one of groups of wav= e-pipelined circuits. > > > [0058] Every wave-pipelined circuit has its own change rules and t= hose changes are unknown to designers when they are writing code and will b= e known to a synthesizer only after it has analyzed the circuit. > > > [0059] The present invention classifies all critical paths into tw= o basic types: a series critical path and a feedback critical path, and div= ides each of wave-pipelined circuits into two components: one is static log= ic part and called critical path component (CPC); another is dynamic logic = part and formalized into four wave-pipelining components (WPC) shared by al= l wave-pipelined circuits. Under the present invention each of standard wav= e-pipelining ready code in HDL comprises two components: a WPC instantiatio= n and a CPC instantiation which are wire-connected and linked by a new conc= urrent link statement. Each of four WPC embodiments has a group of new type= wave constant, which plays the same role as a generic constant does, but w= hose initial value is determined and assigned by a synthesizer after it has= analyzed the linked CPC component under slow mode and target mode, respect= ively, so designers can use after-synthesization information in their code = before synthesization in HDL for wave-pipelining technology. Following the = instructions of the present invention creates a situation that digital desi= gners can write wave-pipelining ready code in HDL and the responsibility of= analyzing and manipulating wave-pipelining ready code, generating and impl= ementing wave-pipelined circuits on a design-wide or chip-wide scale in HDL= is shifted from individual designers to synthesizer manufacturers. > > >=20 > > > How the method works > > >=20 > > > [0060] The systematic method of coding wave-pipelined circuits in = HDL comprises following ten parts: > > > 1. Define five signals, one counter, one switch and one table that wi= ll be used when generating wave-pipelined circuits on a design-wide or chip= -wide scale in HDL. > > > 2. Define the interfaces of a CPC each of which encapsulates a critic= al path's static logic part. > > > 3. Define and implement four WPC embodiments in HDL each of which is = a critical path's dynamic logic part: a series_module, an input_delay_modul= e, a multiple_copy_module1 and a multiple_copy_module2. > > > 4. Define one new keyword wave and three new wave constants which pro= vide a means to dynamically transfer after-synthesization information to de= signers' code before synthesization. > > > 5. Define the methods of determining and searching for wave constant = values of a known WPC instantiation under slow mode and target mode, respec= tively. > > > 6. Define three versions of a concurrent link statement: link1, link2= and link3, and rules on how they are used. > > > 7. Define the pairing rules between a WPC and a CPC. > > > 8. Define how a digital designer prepares wave-pipelining ready code = systematically. > > > 9. Shift the responsibility of analyzing and manipulating wave-pipeli= ning ready code, generating and implementing wave-pipelined circuits on a d= esign-wide or chip-wide scale in HDL from individual designers to synthesiz= er manufacturers. > > > 10. Define how four WPC embodiments are simulated and debugged under = any of current versions of a synthesizer in HDL. > > > [0061] It is fair to put the burden of successfully generating wav= e-pipelined circuits based on wave-pipelining ready code squarely on synthe= sizer manufacturers' shoulder if all necessary information is passed to a s= ynthesizer. For example, with tens of papers claiming that successful wave-= pipelined circuits are implemented in FPGA chips in an isolated environment= , it is the responsibility of FPGA synthesizers to be capable of generating= those wave-pipelined circuits in a design-wide environment without designe= rs' further involvements, a process similar for them to the task of generat= ing a circuit with the highest running frequency and minimum used resources= if possible for any normal digital design code. > > >=20 > > > Thank you for your reading. > >=20 > > Here are more contents. > >=20 > > Definitions of wave-pipelining component and critical path component > >=20 > > [0062] A design component is called a critical path component (CPC) = if it is an entity (a term in VHDL-2002) in HDL and encapsulates the static= logic part of a critical path which is to be wave-pipelined circuit. There= are two types of CPCs:=20 > > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80=99= s static logic part. > > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2= =80=99s static logic part.=20 > >=20 > > [0063] A CPC also refers to a CPC instantiation when it will not be = misunderstood. The required interfaces of both a series CPC and a feedback = CPC are always the same. The combinational logic of a CPC may be located wi= thin or outside of the component and there is no limit on it.=20 > >=20 > > [0064] A design component is called a wave-pipelining component (WPC= ) if it is an entity in HDL, provided by HDL in a new wave-pipelining syste= m library and used to generate a critical path=E2=80=99s dynamic logic part= , i.e., to generate output data valid signal and write enable signals to th= e input and output registers of a critical path.=20 > >=20 > > [0065] There are three types of WPC:=20 > > =E2=80=A2 A series_module is used to connect to a series CPC with input= data acceptable on every clock cycle. > > =E2=80=A2 An input_delay_module is used to connect to a series or feedb= ack CPC with input data acceptable on every one or more clock cycle. > > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used to= connect to multiple copied series or feedback CPCs with input data accepta= ble on every clock cycle. > >=20 > > [0066] A WPC also refers to a WPC instantiation when it will not be = misunderstood. Later multiple_copy_module refers to either of multiple_copy= _module1 and multiple_copy_module2. > >=20 > > A synthesizer=E2=80=99s new signals, switch and table > >=20 > > [0067] A synthesizer that is able of handling wave-pipelining needs = six signals, one switch, one table and the table=E2=80=99s row index to hel= p finish its job: > > =E2=80=A2 A floating signal target_running_frequency: it is set up by a= designer and the target running frequency under which a design finally run= s. > > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer and= its initial value is deasserted. A synthesizer will generate related circu= it files for a design under slow mode for slow mode hardware testing if gen= erate_circuit is asserted and no errors are detected after a synthesization= , or will not otherwise. A synthesizer will always generate related circuit= files for a design under target mode for target mode hardware testing if n= o errors are detected after a synthesization. > > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer and = its initial value is deasserted. Assert the bit if a CPC is being analyzed = and determined to have feedbacks, and deassert it after the analysis is fin= ished. > > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designer = and its initial value is deasserted. Assert the bit if a designer wants to = keep all CPC new circuits automatically and successfully modified by a synt= hesizer under target mode unchanged under slow mode when he is switching to= synthesize the same design from under target mode to under slow mode and t= he related code doesn=E2=80=99t change, or deassert it otherwise. The bit p= rovides a method for a designer to check if the new automatically and succe= ssfully modified circuits by a synthesizer don=E2=80=99t change basic logic= .=20 > > =E2=80=A2 An integer signal parent_series_clock_number: it is set up by= a synthesizer and Its initial value is zero. When the instantiation of a W= PC delay_input_module or multiple_copy_module is being analyzed and execute= d its series_clock_number value is stored in parent_series_clock_number, an= d it is cleared to zero when the execution is finished. > > =E2=80=A2 An integer signal start_number: it is set up by a synthesizer= and used when the synthesizer determines that a CPC cannot meet the wave-p= ipelining requirements with input data acceptable on every clock cycle and = the CPC is linked with a WPC input_delay_module or multiple_copy_module. Th= e start_number is made equal to 2 if a WPC multiple_copy_module is linked o= r to feedback_clock_number if a WPC input_delay_module is linked as the sta= rting value of wave constant input_clock_number or multiple_copy_number. > > =E2=80=A2 A bit switch running_mode: it is set up by a designer and it = has two valid values with slow mode being its initial value: > > o Slow mode: under slow mode a digital designer designs his code, a des= ign is synthesized, simulated, and hardware tested under the following assu= mptions: > > =EF=82=A7 Signals take one clock cycle to propagate through any of CPCs= under slow running frequency. > > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > > =EF=82=A7 No multiple copied CPCs are generated. > > o Target mode: under target mode a design is synthesized, simulated, ha= rdware tested and finally runs under predetermined target running frequency= , and its implementation is determined and generated by a synthesizer under= the following assumptions: > > =EF=82=A7 Signals take one or more clock cycle to propagate through any= of CPCs as designed. > > =EF=82=A7 Each of CPCs has input data acceptable on every one or more c= lock cycle as wave-pipelining ready code indicates and it is necessary. > > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready c= ode indicates and it is necessary. > > =E2=80=A2 A wave constant signal table: it is generated and manipulated= by a synthesizer and stores information about each linked pair of a CPC an= d a WPC; all wave constant values and alias wave constant values can be acc= essed from the table. > > =E2=80=A2 An integer row_index to the wave constant signal table: it is= set up by a synthesizer and its initial value is 1. It is used as a row in= dex for a new link statement in the wave constant signal table and will be = increased by 1 after a synthesizer finishes the filling of the row during t= he source code scanning.=20 > >=20 > > Thank you for your reading. > >=20 > > Weng >=20 > Here are more contents. It shows how a complicated problem is resolved by= creative ideas. >=20 >=20 > New keyword wave and wave constant in HDL >=20 > [0068] When writing wave-pipelining code, digital designers don=E2=80= =99t know how many clock cycles signals need to propagate through a critica= l path, and to finish their jobs, it may take several working cycles for th= em manually to adjust their code to make a wave-pipelined circuit working. = This method is not feasible on a design-wide or chip-wide scale, because a = design may have 100 or more critical paths to be wave-pipelined circuits an= d there is no guarantee for designers to perfectly remember which is finish= ed and which is not, and most importantly, synthesizers are left aside of t= he business of wave-pipelining, giving no help at all. One of obstacles usi= ng wave-pipelining in HDL is how to establish a communication channel betwe= en a synthesizer and digital designers to provide the following essential f= unctions: >=20 > =E2=80=A2 How a designer can use after-synthesization information to writ= e code for wave-pipelined circuits before they have been synthesized in HDL= for wave-pipelining technology. This function is not necessary for success= fully generating a wave-pipelined circuit, but beneficial to implement a co= mplex one. >=20 > =E2=80=A2 If all pieces of wave-pipelining ready code are written, a desi= gn has passed simulations and/or hardware testing under slow mode perfectly= , and a synthesizer certifies that all wave-pipelining requirements are met= with input data acceptable on every one or more clock cycle and no errors = are detected after a synthesization, then correct full design circuits can = be generated under target mode and work as designed with no code change dur= ing the switching from slow mode to target mode or vice verse on a design-w= ide or chip-wide scale. This function is critical and essential for succes= sfully generating all wave-pipelined circuits on a design-wide or chip-wide= scale in HDL. >=20 > [0069] New keyword wave and three wave constants are introduced to res= olve the problem. In the following listing characters in bold type are new = suggested definitions based on VHDL-2002. >=20 > entity_declaration ::=3D=20 > entity identifier is > entity_header > entity_declarative_part > [begin > entity_statement_part ] > end [ entity ] [ entity_simple_name ] ; >=20 > entity_header ::=3D > [formal_generic_clause ] > [formal_port_clause ] >=20 > generic_clause ::=3D generic ( generic_list ) ; > generic_list ::=3D generic_interface_list > interface_list ::=3D interface_element { ; interface_element } > interface_element ::=3D interface_declaration >=20 > interface_declaration ::=3D > interface_constant_declaration > |interface_wave_constant_declaration > | interface_signal_declaration > | interface_variable_declaration > | interface_file_declaration >=20 > interface_constant_declaration ::=3D > [constant] identifier_list : [ in] subtype_indication [ :=3D static_expre= ssion ] >=20 > interface_wave_constant_declaration ::=3D > wave [constant] wave_constant_list : [ in ] subtype_indication > [ :=3D static_expression ] >=20 > wave_constant_list ::=3D=20 > wave_constant_element { , wave_constant_element } >=20 > wave_constant_element ::=3D=20 > wave_constant > |internal_wave_constant >=20 > wave_constant ::=3D > series_clock_number > | input_clock_number > | multiple_copy_number >=20 > internal_wave_constant ::=3D one_hot >=20 > entity_declarative_part ::=3D > { entity_declarative_item } >=20 > entity_declarative_item ::=3D > subprogram_declaration > | subprogram_body > | type_declaration > | subtype_declaration > | constant_declaration > | alias_wave_constant_declaration > | signal_declaration > |shared_variable_declaration > | file_declaration > | alias_declaration > | attribute_declaration > | attribute_specification > | disconnection_specification > | use_clause > | group_template_declaration > | group_declaration >=20 > architecture_body ::=3D > architecture identifier of entity_name is > architecture_declarative_part > begin > architecture_statement_part > end[ architecture ] [ architecture_simple_name ] ; >=20 > architecture_declarative_part ::=3D > { block_declarative_item } >=20 > block_declarative_item ::=3D > subprogram_declaration > | subprogram_body > | type_declaration > | subtype_declaration > | constant_declaration > | alias_wave_constant_declaration > | signal_declaration > | shared_variable_declaration > | file_declaration > | alias_declaration > | component_declaration > | attribute_declaration > | attribute_specification > | configuration_specification > | disconnection_specification > | use_clause > | group_template_declaration > | group_declaration >=20 > constant_declaration ::=3D > constant identifier_list : subtype_indication [ :=3D expression ] ; >=20 > alias_wave_constant_declaration ::=3D > wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 > wave_constant ; >=20 > alias_wave_constant_list ::=3D > alias_wave_constant { , alias_wave_constant } >=20 > alias_wave_constant ::=3D identifier >=20 > [0070] The set of following rules is called wave constant mechanism: >=20 > =E2=80=A2 There are three wave constants related to wave-pipelining techn= ique: series_clock_number, input_clock_number and multiple_copy_number.=20 >=20 > =E2=80=A2 A wave constant can only be declared in the generic_clause of t= he entity definition of a WPC embodiment, plays the same role as a generic = constant declared in the same place does except that it has actual initial = value 1 under slow mode, and actual initial value equal to or greater than = 1 determined and assigned by a synthesizer under target mode, and the stati= c expression in an interface wave constant declaration is always ignored. >=20 > =E2=80=A2 A WPC instantiation must not include corresponding association = element with a formal wave constant in the generic map aspect.=20 >=20 > =E2=80=A2 Any wave constant declared in a WPC definition is accessible by= designers through an alias wave constant declaration. >=20 > =E2=80=A2 An alias wave constant declaration identifies a list of alias w= ave constants which are assigned a wave constant. Each alias wave constant = must be linked with a WPC instantiation through a link statement and shares= the wave constant value of the linked WPC instantiation for testing, debug= ging or implementing purpose. An alias wave constant plays the same role as= a normal constant declared in the same place does.=20 >=20 > =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants a= nd output signals as its own input signal, but must have no input signals w= hich are related to any unrelated WPC instantiation=E2=80=99s wave constant= s. >=20 > =E2=80=A2 The internal wave constant one_hot is used internally by a synt= hesizer to optimize the implementation of a WPC and not accessible by desig= ners.=20 >=20 > =E2=80=A2 A synthesizer has its discretion to determine internal wave con= stant one_hot value based on the environment and the consideration of its p= roduction technique used unless a WPC input_delay_module has its R_O output= connected in which case one_hot will be =E2=80=981=E2=80=99 in order to ge= nerate valid R_O output signal.=20 >=20 >=20 > Thank you for your reading. >=20 > Weng Wave-pipelining component series_module (SM) in HDL [0071] FIG. 3 is the interface of a WPC embodiment series_module (SM) li= nked with a series CPC in FIG. 3A. CLK, RESET and SINI are three standard i= nput signals for a synchronous component and the same for each of four WPCs= , and play the same roles. CLK is clock source of the CPC. RESET is a globa= l asynchronous initialization input signal. SINI is a global synchronous in= itialization input signal. Either of RESET/SINI is used to initialize a SM = and one of them must be asserted once to keep SM in initial working status = before it is used. One of RESET/SINI is necessary and another is optional, = and if one of RESET/SINI is not used, it must be connected to =E2=80=980=E2= =80=99 to make it optimized out. [0072] FIG. 3 has two additional input signals and three output signals: =E2=80=A2 Input signal INI is designed to load initialization data into the= linked series CPC. Input data at D_I for the linked CPC is initialization = data if INI is asserted, or working input data otherwise. The assertion of = input signal INI may last as long as needed. Input INI must be connected to= =E2=80=980=E2=80=99 or left opened with default value being =E2=80=980=E2= =80=99 if the linked CPC doesn=E2=80=99t need initialization data. Input si= gnal INI must be asserted after one of RESET/SINI is asserted to make sure = that SM is at the initial state, or wait for the series_clock_number of clo= ck cycles to let the CPC go empty. =E2=80=A2 Input signal WE_I drives write enable signal to the input registe= rs of the linked CPC; input data at D_I of the linked CPC will be latched i= nto the input registers of the CPC on the next clock cycle if WE_I is asser= ted on the current clock cycle, or will not otherwise.=20 =E2=80=A2 Output signal WE_O drives write enable signal to the output regis= ters of the linked CPC; current arriving wave of combinational logic data w= ill be latched into the output registers on the next clock cycle if WE_O is= asserted on the current clock cycle, or will not otherwise.=20 =E2=80=A2 Output signal Valid_O is a data valid output signal; data at D_O = of the linked CPC is valid if Valid_O is asserted or invalid otherwise.=20 =E2=80=A2 Output signal S_O is the Q outputs of each of internal right shif= t registers and may be useful when debugging or implementing a wave-pipelin= ing ready code and optional. No extra logic will be generated if it is left= opened without connection. [0073] The assertion of each of WE_I, WE_O and Valid_O lasts one clock c= ycle for each valid input or output data, respectively.=20 [0074] FIG. 3A is the interface of a series CPC linked with a WPC series= _module in FIG. 3. In addition to the global input signal CLK, the interfac= e has four input signals and one output signal that are essential to wave-p= ipelining: =E2=80=A2 Input signal INI is optional. If it exists, input data at D_I for= the CPC is initialization data when INI is asserted, or working input data= otherwise. The INI assertion may last as long as needed.=20 =E2=80=A2 Input signal WE_I is shared with the linked SM as write enable si= gnal to the input registers. =E2=80=A2 Input signal D_I is data input bus to the CPC.=20 =E2=80=A2 Input signal WE_O_I is write enable signal to the output register= s of the CPC. It comes from the linked SM output signal WE_O and is used to= latch current arriving wave of combinational logic data into output regist= ers.=20 =E2=80=A2 Output signal D_O is output data bus. Output data at D_O is valid= if output signal Valid_O of the linked SM is asserted, or invalid otherwis= e.=20 [0075] A CPC in FIG. 3A may have any number of additional input and outp= ut signals to assist the component and those signals are not drawn here. Th= e dashed lines between FIG. 3 and FIG. 3A show how input and output signals= of two components, a WPC SM and a series CPC, are connected. In addition t= o the connection of global clock signal CLK there are three connections bet= ween the two connected components:=20 =E2=80=A2 Input signals INI of both WPC and CPC are connected together if t= he CPC needs to load initialization data into it before working normally. =E2=80=A2 Input signals WE_I of both components are connected. =E2=80=A2 Output signal WE_O of SM in FIG. 3 drives write enable signal WE_= O_I of its linked series CPC in FIG. 3A. [0076] FIG. 4 is the schematics of a WPC embodiment series_module (SM) l= inked with a series CPC and with input data acceptable on every clock cycle= . 400 is a series CPC; 410 is the input registers of input data bus width; = 420 is its combinational logic circuit; 430 is the output registers of outp= ut data width and input data bus width may be different from output data w= idth. 440 is a SM linked with a series CPC 400 and comprises two sub-compon= ents: 450 is right shift registers with two or more bits; 460 is the right = shift register controller and its schematics are shown in FIG. 4A. In FIG. = 4 dotted line 470 represents the situations when signals take one clock cyc= le to propagate through the series CPC 400 under either slow mode or target= mode; dashed lines represent the situations where the design runs under ta= rget mode and signals take X clock cycles to propagate through the series C= PC 400 with X > 1. The dotted line 470 and dashed lines are mutually exclus= ive. [0077] A SM is essentially right shift registers 450 with a variable len= gth and its controller 460. The right shift registers have X+1 bits, where = X is the number of series clock cycles for CPC 400. When a designer designs= a series CPC or it runs under slow mode, signals are assumed to take one c= lock cycle to propagate through the component, X =3D 1 and the right shift = registers have 2 bits; when the CPC runs under target mode, its number of s= eries clock cycles is X, determined by a synthesizer, and the right shift r= egisters have X+1 bits. S_O output signal is Q outputs of each bit register= of the right shift registers 450 for possible debugging or implementing us= e and optional. [0078] After either RESET or SINI input signal is asserted, the right sh= ift registers are cleared immediately for RESET or on the next clock cycle = for SINI. Each bit register of the right shift registers is connected toget= her one after another with its Q output driving D input of next bit registe= r with following exceptions:=20 =E2=80=A2 A 2-input and-gate A0 has one input coupled to input signal WE_I,= another inversely coupled to input signal INI, and its output driving node= W, D input of the most left bit register FFx and input W of controller 460= .=20 =E2=80=A2 The Q output of second most right bit register drives output sign= al WE_O. =E2=80=A2 The Q output of the most right bit register FF0 drives output sig= nal Valid_O.=20 [0079] A linked pair of a SM and a CPC has two states based on input sig= nal INI value if the CPC has INI input: =E2=80=A2 Initial data loading state: When INI is asserted, node W is deass= erted, leaving right shift registers 450 in an idle state. There will be no= output data latched into the output registers FFo and output signal Valid_= O will be deasserted. Initialization data will be latched into the input re= gisters FFi through D_I on the next clock cycle if input signal WE_I is ass= erted on the current clock cycle. =E2=80=A2 Working state: When INI is deasserted, working data will be latch= ed into the input registers FFi through D_I on the next clock cycle if inpu= t signal WE_I is asserted on the current clock cycle; right shift registers= 450 and its controller 460 are active, output signals WE_O, D_O and Valid_= O work as designed. [0080] In both situations input data will be acceptable on every clock c= ycle. Clock signal is not drawn in the present invention for clarity and si= mplicity. [0081] FIG. 4A is the schematics of the right shift register controller = 460 of a WPC series_module (SM). Or-gate OR1 has (X+2) input signals, where= X is the number of series clock cycles, and under slow mode X =3D 1. =E2=80=A2 Each of input signals Q0-Qx is driven by Q output of one bit regi= ster of the right shift registers, respectively, and the series CPC has val= id data if one of Q0-Qx is asserted or invalid data otherwise. =E2=80=A2 Input signal W is working input data ready signal. If input signa= l INI of a SM is asserted, W is deasserted; when input signal INI is deasse= rted, input signal W is equal to input signal WE_I of the SM.=20 [0082] Or-gate OR1 output signal E drives enable signal E to each bit re= gister of the right shift registers 450. The right shift registers 450 will= right shift one bit on next clock cycle if E is asserted on the current cl= ock cycle or will not otherwise. Right shift registers 450 will right shift= one bit on next clock cycle in either of two situations: =E2=80=A2 There are valid data in the linked CPC. =E2=80=A2 There is a working input data to enter the linked CPC. [0083] Care must be taken before input signal INI is asserted if its CPC= still contains valid data in it. In the situation the linked SM will conti= nue to work to output internal valid data until it is empty, but the CPC ma= y change its internal data flow if input signal INI to the CPC is asserted,= contaminating the outgoing data. Of course, to people in the art the embod= iment of right shift registers can be replaced by embodiment of left shift = registers. [0084] Based on connections of FIG. 3 and FIG. 3A a WPC series_module ha= s nothing to do with input data at D_I and output data at D_O of its linked= CPC, so series_module can handle any types of input data and output data o= f a series CPC and doesn=E2=80=99t have any overloading type. Weng From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.52.5.169 with SMTP id t9mr99399224vdt.7.1427070154412; Sun, 22 Mar 2015 17:22:34 -0700 (PDT) X-Received: by 10.50.119.131 with SMTP id ku3mr108994igb.2.1427070154370; Sun, 22 Mar 2015 17:22:34 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h3no4186892qgf.1!news-out.google.com!qk8ni62932igc.0!nntp.google.com!z20no2275168igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 22 Mar 2015 17:22:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=209.200.192.122; posting-account=0C4O8AoAAABSBpnL-C_4yHc2eT3qQe-d NNTP-Posting-Host: 209.200.192.122 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <54c55154-9a7a-4150-b66d-f47ea3d519f9@googlegroups.com> Subject: How to make $100,000 in 20-90 days From: "Kristina C." Injection-Date: Mon, 23 Mar 2015 00:22:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 94 X-Received-Bytes: 8435 X-Received-Body-CRC: 2150511876 Xref: mx02.eternal-september.org comp.lang.vhdl:8166 HOW TO MAKE 100000 DOLLARS IN 20 -90 DAYS!=20 Send $1.00 to each of the 6 names and addresses stated in the article. You = then place your own name and address in the bottom of the list at #6, and p= ost the article in at least 200 newsgroups. No catch, that was it. So after= thinking it over, and talking to a few people first, I thought about tryin= g it. I figured: "what have I got to lose except 6 stamps and $6.00, right?= " Then I invested the measly $6.00. Well GUESS WHAT!?... within 7 days, I s= tarted getting money in the mail! I was shocked! I figured it would end soo= n, but the money just kept coming in. In my first week, I made about $25.00= . By the end of the second week I had made a total of over $1,000.00! In th= e third week I had over $10,000.00 and it's still growing. This is now my f= ourth week and I have made a total of just over $42,000.00 and it's still c= oming in rapidly. It's certainly worth $6.00, and 6 stamps, I have spent mo= re than that on the lottery!! Let me tell you how this works and most impor= tantly, WHY it works... Also, make sure you print a copy of this article NO= W, so you can get the information off of it as you need it. I promise you t= hat if you follow the directions exactly, that you will start making more m= oney than you thought possible by doing something so easy! Suggestion: Read= this entire message carefully! (print it out or download it.) Follow the s= imple directions and watch the money come in! It's easy. It's legal. And yo= ur investment is only $6.00 (Plus postage) IMPORTANT: This is not a rip-off= ; it is not indecent; it is not illegal; and it is 99% no risk - it really = works! If all of the following instructions are adhered to, you will receiv= e extraordinary dividends. PLEASE NOTE: Follow these directions EXACTLY, an= d $50,000.00 or more can be yours in 20 to 60 days. This program remains su= ccessful because of the honesty and integrity of the participants. Please c= ontinue its success by carefully adhering to the instructions. You will now= become part of the Mail Order business. In this business your product is n= ot solid and tangible, it's a service. You are in the business of developin= g Mailing Lists. Many large corporations are happy to pay big bucks for qua= lity lists. However, the money made from the mailing lists is secondary to = the income which is made from people like you and me asking to be included = in that list. Here are the 4 easy steps to success: STEP 1: Get 6 separate = pieces of paper and write down your name and address followed by the words = "PLEASE ADD ME TO YOUR MAILING LIST" on each of them. Now get 6 US $1.00 bi= lls and place ONE inside EACH of the 6 pieces of paper so the bill will not= be visible through the envelope (to prevent thievery). Next, place one pap= er in each of the 6 envelopes and seal them. You should now have 6 sealed e= nvelopes, each with a piece of paper stating the above phrase, your name an= d address, and a $1.00 bill. What you are doing is creating a service. THIS= IS ABSOLUTELY LEGAL! You are requesting a legitimate service and you are p= aying for it! Like most of us I was a little skeptical and a little worried= about the legal aspects of it all. So I checked it out with the U.S. Post = Office (1- 800-725-2161) and they confirmed that it is indeed legal. Mail t= he 6 envelopes to the following addresses: 1.) Kyle P. 1325 Tonti St. LaSa= lle, IL.USA 61301 2.) Rucci 418 Wilcox Street Carnegie, Pa. 15106 3. St= efan B. 2903 Marquette Rd. Peru, IL. USA 61354 4.) Cody Neely, P.O. box 47= 2, Sylvania Ga. USA 30467 5.) Sarah Mccully, 8818 w 88th st overland park= , ks, USA 66212 6.) Kristie C. P.O. Box 3034 Kalispell MT 59903 STEP 2: Now= take the #1 name off the list that you see above, move the other names up = (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as number 6 on the lis= t. STEP 3: Change anything you need to, but try to keep this article as clo= se to original as possible. Now, post your amended article to at least 200 = newsgroups. (I think there are close to 24,000 groups) All you need is 200,= but remember, the more you post, the more money you make! You won't get ve= ry much unless you post like crazy. This is perfectly legal! If you have an= y doubts, refer to Title 18 Sec. 1302 & 1341 of the Postal lottery laws. Ke= ep a copy of these steps for yourself and, whenever you need money, you can= use it again, and again. PLEASE REMEMBER that this program remains success= ful because of the honesty and integrity of the participants and by their c= arefully adhering to the directions. Look at it this way. If you are of int= egrity, the program will continue and the money that so many others have re= ceived will come your way. NOTE: You may want to retain every name and addr= ess sent to you, either on a computer or hard copy and keeps the notes peop= le send you. This VERIFIES that you are truly providing a service. (Also, i= t might be a good idea to wrap the $1 bill in dark paper to reduce the risk= of mail theft.) So, as each post is downloaded and the directions carefull= y followed, six members will be reimbursed for their participation as a Lis= t Developer with one dollar each. Your name will move up the list geometric= ally so that when your name reaches the #1 position you will be receiving t= housands of dollars in CASH!!! What an opportunity for only $6.00 ($1.00 fo= r each of the first six people listed above) Send it now, add your own name= to the list and you're in business! ---DIRECTIONS ----- FOR HOW TO POST TO= NEWSGROUPS---------- Step 1) You do not need to re-type this entire letter= to do your own posting. Simply put your cursor at the beginning of this le= tter and drag your cursor to the bottom of this document, and select 'copy'= from the edit menu. This will copy the entire letter into the computer's m= emory. Step 2) Open a blank 'notepad' file and places your cursor at the to= p of the blank page. From the 'edit' menu select 'paste'. This will paste a= copy of the letter into notepad so that you can add your name to the list.= Step 3) Save your new notepad file as a .txt file. If you want to do your = postings in different settings, you'll away, after you get the hang of it, = it will take about 30 seconds for each newsgroup! **REMEMBER, THE MORE NEWS= GROUPS YOU POST IN, THE MORE MONEY YOU WILL MAKE! BUT: YOU HAVE TO POST A M= INIMUM OF 200** That's it! You will begin receiving money from around the w= orld within days! You may eventually want to rent a P.O. Box due to the lar= ge amount of mail you will receive. To find newsgroups type in a topic and= newsgroup list into google and you should be able to find some. If you pu= t the newsgroup into the search engine it will pull it up and likely it wil= l say google groups if it is free to post. Google lets you post about 15 p= osts and then you have to wait for a little while, an hour is usually good.= You may have to post less adds more frequently. Can also post to facebook= groups, youtube, craigslist (don't post more than one or two a day or you = will be flagged). Unless you are part of the group already you cannot post= to moderated groups.=20 From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.80.7 with SMTP id n7mr2568662obx.10.1427162442489; Mon, 23 Mar 2015 19:00:42 -0700 (PDT) X-Received: by 10.140.34.56 with SMTP id k53mr29349qgk.19.1427162442367; Mon, 23 Mar 2015 19:00:42 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed1a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z20no3967514igj.0!news-out.google.com!q90ni527qgd.1!nntp.google.com!h3no4425160qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Mar 2015 19:00:42 -0700 (PDT) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.49.104.28; posting-account=9GnU7goAAAAHU53ujXD8Ejd5wZPBXz8p NNTP-Posting-Host: 50.49.104.28 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <06a2a4ed-38e1-42bb-9ceb-619ec784bc8a@googlegroups.com> Subject: Re: c-language to VHDL converter From: Derek Simmons Injection-Date: Tue, 24 Mar 2015 02:00:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 27 Xref: mx02.eternal-september.org comp.lang.vhdl:8167 On Wednesday, March 4, 2015 at 3:38:38 AM UTC-5, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VH= DL directly by any software. (or) can we compile C-code in xilinx IDE? I tried out Impulse C it had its pluses and minuses.=20 Pluses:=20 In an image processing environment the FPGA engineers created that was shar= ed between the FPGA engineers and the imaging scientist. The imaging scient= ist didn't understand what we did but worked within the framework we create= d for them. They would develop their algorithms is Visual Studio and demo a= pplications. We would make sure the projects would translate from C to VHDL= . Minuses: You were limited to do things that would translate 'nicely' to VHDL and usi= ng constructs that would convert to VHDL.=20 My advice is get a copy of Pong Chu's, "RTL Hardware Design Using VHDL" and= read chapters 11 and 12 on Register Transfer Methodology. We had a plain t= ext license and under the hood this is kind of what the C to VHDL compiler = was doing.=20 What we decided to do was create a design standard and write it by hand bec= ause it was easier for us to support. You can't beat a good VHDL designer. From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.52.29.4 with SMTP id f4mr6203249vdh.3.1427221371762; Tue, 24 Mar 2015 11:22:51 -0700 (PDT) X-Received: by 10.50.51.67 with SMTP id i3mr303507igo.15.1427221371700; Tue, 24 Mar 2015 11:22:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!border2.nntp.ams2.giganews.com!backlog4.nntp.ams3.giganews.com!buffer2.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h3no4567023qgf.1!news-out.google.com!db6ni61707igc.0!nntp.google.com!z20no2876875igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 11:22:50 -0700 (PDT) In-Reply-To: <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 24 Mar 2015 18:22:51 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Lines: 2094 X-Original-Bytes: 93234 Xref: mx02.eternal-september.org comp.lang.vhdl:8168 On Saturday, March 21, 2015 at 3:23:34 PM UTC-7, Weng Tianxiang wrote: > On Friday, March 13, 2015 at 10:45:11 PM UTC-7, Weng Tianxiang wrote: > > On Monday, March 9, 2015 at 3:02:48 AM UTC-7, Weng Tianxiang wrote: > > > On Tuesday, March 3, 2015 at 9:26:46 PM UTC-8, Weng Tianxiang wrote: > > > > On Thursday, February 26, 2015 at 6:03:15 PM UTC-8, Weng Tianxiang = wrote: > > > > > On Tuesday, February 24, 2015 at 9:09:40 AM UTC-8, Weng Tianxiang= wrote: > > > > > > Hi Jim, glen, JK, rickman, Mike, Andy,=20 > > > > > >=20 > > > > > > I have filed a provisional patent application: "Systematic meth= od of coding wave pipelined circuits in HDL". If it is proved correct, the = patent will introduce 1 keyword, 3 permanent constants, 1 concurrent statem= ent and four source code modules for a new library in HDL and thoroughly re= solve a pending problem so that every digital designer can code wave-pipeli= ned circuits in HDL. > > > > > >=20 > > > > > > Here is the abstract of the invention: > > > > > >=20 > > > > > > The present invention classifies all critical paths into tw= o basic types: a series critical path and a feedback critical path, and div= ides each of wave-pipelined circuits into two components: a static logic pa= rt, called critical path component (CPC), and a dynamic logic part, formali= zed into four wave-pipelining components (WPC) shared by all wave-pipelined= circuits. Each wave-pipelining ready code in HDL comprises two components:= a WPC instantiation and a CPC instantiation wire-connected and linked by a= new link statement. Each WPC has new wave constants which play the same ro= le as generic constants do, but whose initial values are determined and ass= igned by a synthesizer after code analysis, so designers can use after-synt= hesization information in their code before synthesization for wave-pipelin= ing technology. The responsibility of analyzing and manipulating wave-pipel= ining ready code, generating and implementing wave-pipelined circuits on a = design-wide or chip-wide scale in HDL is shifted from designers to synthesi= zers. > > > > > >=20 > > > > > > Anyone who are interested in its content is welcome to send a e= mail request to the following email address: wtx wtx @ gmail . com with tit= le "Systematic" and he will receive the full documents: one specification, = 9 drawings and one text file in VHDL. > > > > > >=20 > > > > > > If one reviews the files and feels that it would be a good thin= g to recommend the application to his company to buy it, the first person t= o do it after his recommended company does so will receive $10,000 commissi= on fee. > > > > > >=20 > > > > > > Thank you. > > > > > >=20 > > > > > > Weng > > > > >=20 > > > > > Hi, > > > > > I want to add some introductions to what the wave-pipelined circu= its are and their status. > > > > >=20 > > > > > [0003] A synchronous digital system contains a lot of register= s. Valid data flow through successive registers from system input registers= to system output registers. All data flows are synchronous with triggering= edges of a chip clock. For example, data flow from registers A to register= s B, from registers B to registers C and so on in a successive order on the= same clock cycle. > > > > > [0004] A path in a synchronous digital system is a route betwe= en any neighboring registers connected by combinational logic. If the targe= t running frequency for a digital design is predetermined, the upper limit = of propagating time for any paths is determined and has the inverse value o= f the target running frequency. A path is called a critical path if the tim= e signals take to propagate through it is beyond the predetermined propagat= ing time, and the time is called the path's critical time. If there are any= critical paths, digital designers must spend time reducing all critical ti= mes by all means and eliminating all critical paths to meet the target runn= ing frequency. > > > > > [0005] Wave-pipelining is a technology which completes an oper= ation that needs several clock cycles to propagate without intermediate reg= isters and with input data acceptable on every clock cycle. For example, in= a conventional pipelining operation, data flow from registers A to registe= rs D through registers B and C to divide the critical path time into multip= le smaller intervals to meet the critical time: A to B to C to D; with wave= -pipelining, data flow through registers A and D without intermediate regis= ters B and C. Absolutely, wave-pipelining will reduce logic resource usage = and is superior to the conventional pipelining technology if it can be used= . > > > > >=20 > > > > > Here are the most important inequalities involving wave-pipelinin= g from paper "Wave-Pipelining: A Tutorial and Research Survey" by Wayne P. = Burleson et al in IEEE Trans. Very Large Scale Integra. (VLSI) Syst., vol. = 6, no. 3, pp. 464-474, Sep. 1998. > > > > >=20 > > > > > [0018] Currently many memory chip manufacturers successfully u= se wave-pipelining in their memory chip products with higher rate outputs, = reduced power consumption and logic resources; and a few scientists use FPG= A chips as a base to show some circuits can be done with wave-pipelining in= isolated environments. Their works prove that the wave-pipelining is a ver= y powerful tool to reduce power consumption and logic resources. Now there = are two major existing obstacles preventing any ordinary digital designers = from using the wave-pipelining in HDL: > > > > > * The software algorithms making wave-pipelining successful, like= Wong and Klass algorithms and others, have already been developed and matu= red, but ordinary digital designers have no means or resources to access to= the technology, because there are no international HDL standards on how sy= nthesizer manufacturers incorporate those capabilities into their products. > > > > > * HDL needs the capabilities for digital designers to write wave-= pipelining ready code for any number of critical paths on a design-wide or = chip-wide scale instead of in an isolated environment and the written code = can be identified, synthesized and used to generate wave-pipelined circuits= by any synthesizer in ASIC or FPGA, and they should be part of HDL standar= ds.=20 > > > > > [0019] The target of the present invention is: > > > > > * Invent a wave-pipelining coding system as new part of HDL stand= ards for designers to write wave-pipelining ready code which can be identif= ied, synthesized and used to generate wave-pipelined circuits by any synthe= sizer in ASIC or FPGA. > > > > > * Make wave-pipelining ready code written based on the coding sys= tem working with no extra logic generated, compared with independently writ= ten wave-pipelined circuits, and with no code changes when switching from n= on-wave-pipelined mode to wave-pipelined mode or vice verse if all of wave-= pipelining ready code meet wave-pipelining requirements.=20 > > > > > * Shift burdens of analyzing and manipulating wave-pipelining rea= dy code, generating and implementing wave-pipelined circuits on a design-wi= de or chip-wide scale in HDL from individual designers to synthesizer manuf= acturers. > > > > > [0020] If the coding system becomes new part of HDL standards = all synthesizer manufactures will automatically be forced to implement all = well-known wave-pipelining algorithms and techniques within their products,= a competition will start for better implementations, making wave-pipelinin= g technique available to every digital designer in HDL. > > > > >=20 > > > > > Weng > > > >=20 > > > > Here I add some contents of the invention: > > > >=20 > > > > Main idea behind the present invention > > > >=20 > > > > [0057] The most difficult part coding all types of wave-pipeline= d circuits on a design-wide scale in HDL is that a wave-pipelined circuit c= ode always comprises two logic parts:=20 > > > > * A static logic part: it doesn't change if the number of series cl= ock cycles through the circuit changes and is unique for each of wave-pipel= ined circuits. > > > > * A dynamic logic part: it does change if the number of series cloc= k cycles through the circuit changes and is the same for one of groups of w= ave-pipelined circuits. > > > > [0058] Every wave-pipelined circuit has its own change rules and= those changes are unknown to designers when they are writing code and will= be known to a synthesizer only after it has analyzed the circuit. > > > > [0059] The present invention classifies all critical paths into = two basic types: a series critical path and a feedback critical path, and d= ivides each of wave-pipelined circuits into two components: one is static l= ogic part and called critical path component (CPC); another is dynamic logi= c part and formalized into four wave-pipelining components (WPC) shared by = all wave-pipelined circuits. Under the present invention each of standard w= ave-pipelining ready code in HDL comprises two components: a WPC instantiat= ion and a CPC instantiation which are wire-connected and linked by a new co= ncurrent link statement. Each of four WPC embodiments has a group of new ty= pe wave constant, which plays the same role as a generic constant does, but= whose initial value is determined and assigned by a synthesizer after it h= as analyzed the linked CPC component under slow mode and target mode, respe= ctively, so designers can use after-synthesization information in their cod= e before synthesization in HDL for wave-pipelining technology. Following th= e instructions of the present invention creates a situation that digital de= signers can write wave-pipelining ready code in HDL and the responsibility = of analyzing and manipulating wave-pipelining ready code, generating and im= plementing wave-pipelined circuits on a design-wide or chip-wide scale in H= DL is shifted from individual designers to synthesizer manufacturers. > > > >=20 > > > > How the method works > > > >=20 > > > > [0060] The systematic method of coding wave-pipelined circuits i= n HDL comprises following ten parts: > > > > 1. Define five signals, one counter, one switch and one table that = will be used when generating wave-pipelined circuits on a design-wide or ch= ip-wide scale in HDL. > > > > 2. Define the interfaces of a CPC each of which encapsulates a crit= ical path's static logic part. > > > > 3. Define and implement four WPC embodiments in HDL each of which i= s a critical path's dynamic logic part: a series_module, an input_delay_mod= ule, a multiple_copy_module1 and a multiple_copy_module2. > > > > 4. Define one new keyword wave and three new wave constants which p= rovide a means to dynamically transfer after-synthesization information to = designers' code before synthesization. > > > > 5. Define the methods of determining and searching for wave constan= t values of a known WPC instantiation under slow mode and target mode, resp= ectively. > > > > 6. Define three versions of a concurrent link statement: link1, lin= k2 and link3, and rules on how they are used. > > > > 7. Define the pairing rules between a WPC and a CPC. > > > > 8. Define how a digital designer prepares wave-pipelining ready cod= e systematically. > > > > 9. Shift the responsibility of analyzing and manipulating wave-pipe= lining ready code, generating and implementing wave-pipelined circuits on a= design-wide or chip-wide scale in HDL from individual designers to synthes= izer manufacturers. > > > > 10. Define how four WPC embodiments are simulated and debugged unde= r any of current versions of a synthesizer in HDL. > > > > [0061] It is fair to put the burden of successfully generating w= ave-pipelined circuits based on wave-pipelining ready code squarely on synt= hesizer manufacturers' shoulder if all necessary information is passed to a= synthesizer. For example, with tens of papers claiming that successful wav= e-pipelined circuits are implemented in FPGA chips in an isolated environme= nt, it is the responsibility of FPGA synthesizers to be capable of generati= ng those wave-pipelined circuits in a design-wide environment without desig= ners' further involvements, a process similar for them to the task of gener= ating a circuit with the highest running frequency and minimum used resourc= es if possible for any normal digital design code. > > > >=20 > > > > Thank you for your reading. > > >=20 > > > Here are more contents. > > >=20 > > > Definitions of wave-pipelining component and critical path component > > >=20 > > > [0062] A design component is called a critical path component (CPC= ) if it is an entity (a term in VHDL-2002) in HDL and encapsulates the stat= ic logic part of a critical path which is to be wave-pipelined circuit. The= re are two types of CPCs:=20 > > > =E2=80=A2 A series CPC: it encapsulates a series critical path=E2=80= =99s static logic part. > > > =E2=80=A2 A feedback CPC: it encapsulates a feedback critical path=E2= =80=99s static logic part.=20 > > >=20 > > > [0063] A CPC also refers to a CPC instantiation when it will not b= e misunderstood. The required interfaces of both a series CPC and a feedbac= k CPC are always the same. The combinational logic of a CPC may be located = within or outside of the component and there is no limit on it.=20 > > >=20 > > > [0064] A design component is called a wave-pipelining component (W= PC) if it is an entity in HDL, provided by HDL in a new wave-pipelining sys= tem library and used to generate a critical path=E2=80=99s dynamic logic pa= rt, i.e., to generate output data valid signal and write enable signals to = the input and output registers of a critical path.=20 > > >=20 > > > [0065] There are three types of WPC:=20 > > > =E2=80=A2 A series_module is used to connect to a series CPC with inp= ut data acceptable on every clock cycle. > > > =E2=80=A2 An input_delay_module is used to connect to a series or fee= dback CPC with input data acceptable on every one or more clock cycle. > > > =E2=80=A2 A multiple_copy_module1 or a multiple_copy_module2 is used = to connect to multiple copied series or feedback CPCs with input data accep= table on every clock cycle. > > >=20 > > > [0066] A WPC also refers to a WPC instantiation when it will not b= e misunderstood. Later multiple_copy_module refers to either of multiple_co= py_module1 and multiple_copy_module2. > > >=20 > > > A synthesizer=E2=80=99s new signals, switch and table > > >=20 > > > [0067] A synthesizer that is able of handling wave-pipelining need= s six signals, one switch, one table and the table=E2=80=99s row index to h= elp finish its job: > > > =E2=80=A2 A floating signal target_running_frequency: it is set up by= a designer and the target running frequency under which a design finally r= uns. > > > =E2=80=A2 A bit signal generate_circuit: it is set up by a designer a= nd its initial value is deasserted. A synthesizer will generate related cir= cuit files for a design under slow mode for slow mode hardware testing if g= enerate_circuit is asserted and no errors are detected after a synthesizati= on, or will not otherwise. A synthesizer will always generate related circu= it files for a design under target mode for target mode hardware testing if= no errors are detected after a synthesization. > > > =E2=80=A2 A bit signal feedback_bit: it is set up by a synthesizer an= d its initial value is deasserted. Assert the bit if a CPC is being analyze= d and determined to have feedbacks, and deassert it after the analysis is f= inished. > > > =E2=80=A2 A bit signal keep_target_circuit: it is set up by a designe= r and its initial value is deasserted. Assert the bit if a designer wants t= o keep all CPC new circuits automatically and successfully modified by a sy= nthesizer under target mode unchanged under slow mode when he is switching = to synthesize the same design from under target mode to under slow mode and= the related code doesn=E2=80=99t change, or deassert it otherwise. The bit= provides a method for a designer to check if the new automatically and suc= cessfully modified circuits by a synthesizer don=E2=80=99t change basic log= ic.=20 > > > =E2=80=A2 An integer signal parent_series_clock_number: it is set up = by a synthesizer and Its initial value is zero. When the instantiation of a= WPC delay_input_module or multiple_copy_module is being analyzed and execu= ted its series_clock_number value is stored in parent_series_clock_number, = and it is cleared to zero when the execution is finished. > > > =E2=80=A2 An integer signal start_number: it is set up by a synthesiz= er and used when the synthesizer determines that a CPC cannot meet the wave= -pipelining requirements with input data acceptable on every clock cycle an= d the CPC is linked with a WPC input_delay_module or multiple_copy_module. = The start_number is made equal to 2 if a WPC multiple_copy_module is linked= or to feedback_clock_number if a WPC input_delay_module is linked as the s= tarting value of wave constant input_clock_number or multiple_copy_number. > > > =E2=80=A2 A bit switch running_mode: it is set up by a designer and i= t has two valid values with slow mode being its initial value: > > > o Slow mode: under slow mode a digital designer designs his code, a d= esign is synthesized, simulated, and hardware tested under the following as= sumptions: > > > =EF=82=A7 Signals take one clock cycle to propagate through any of CP= Cs under slow running frequency. > > > =EF=82=A7 Any of CPCs has input data acceptable on every clock cycle. > > > =EF=82=A7 No multiple copied CPCs are generated. > > > o Target mode: under target mode a design is synthesized, simulated, = hardware tested and finally runs under predetermined target running frequen= cy, and its implementation is determined and generated by a synthesizer und= er the following assumptions: > > > =EF=82=A7 Signals take one or more clock cycle to propagate through a= ny of CPCs as designed. > > > =EF=82=A7 Each of CPCs has input data acceptable on every one or more= clock cycle as wave-pipelining ready code indicates and it is necessary. > > > =EF=82=A7 Multiple copied CPCs are generated as wave-pipelining ready= code indicates and it is necessary. > > > =E2=80=A2 A wave constant signal table: it is generated and manipulat= ed by a synthesizer and stores information about each linked pair of a CPC = and a WPC; all wave constant values and alias wave constant values can be a= ccessed from the table. > > > =E2=80=A2 An integer row_index to the wave constant signal table: it = is set up by a synthesizer and its initial value is 1. It is used as a row = index for a new link statement in the wave constant signal table and will b= e increased by 1 after a synthesizer finishes the filling of the row during= the source code scanning.=20 > > >=20 > > > Thank you for your reading. > > >=20 > > > Weng > >=20 > > Here are more contents. It shows how a complicated problem is resolved = by creative ideas. > >=20 > >=20 > > New keyword wave and wave constant in HDL > >=20 > > [0068] When writing wave-pipelining code, digital designers don=E2= =80=99t know how many clock cycles signals need to propagate through a crit= ical path, and to finish their jobs, it may take several working cycles for= them manually to adjust their code to make a wave-pipelined circuit workin= g. This method is not feasible on a design-wide or chip-wide scale, because= a design may have 100 or more critical paths to be wave-pipelined circuits= and there is no guarantee for designers to perfectly remember which is fin= ished and which is not, and most importantly, synthesizers are left aside o= f the business of wave-pipelining, giving no help at all. One of obstacles = using wave-pipelining in HDL is how to establish a communication channel be= tween a synthesizer and digital designers to provide the following essentia= l functions: > >=20 > > =E2=80=A2 How a designer can use after-synthesization information to wr= ite code for wave-pipelined circuits before they have been synthesized in H= DL for wave-pipelining technology. This function is not necessary for succe= ssfully generating a wave-pipelined circuit, but beneficial to implement a = complex one. > >=20 > > =E2=80=A2 If all pieces of wave-pipelining ready code are written, a de= sign has passed simulations and/or hardware testing under slow mode perfect= ly, and a synthesizer certifies that all wave-pipelining requirements are m= et with input data acceptable on every one or more clock cycle and no error= s are detected after a synthesization, then correct full design circuits ca= n be generated under target mode and work as designed with no code change d= uring the switching from slow mode to target mode or vice verse on a design= -wide or chip-wide scale. This function is critical and essential for succ= essfully generating all wave-pipelined circuits on a design-wide or chip-wi= de scale in HDL. > >=20 > > [0069] New keyword wave and three wave constants are introduced to r= esolve the problem. In the following listing characters in bold type are ne= w suggested definitions based on VHDL-2002. > >=20 > > entity_declaration ::=3D=20 > > entity identifier is > > entity_header > > entity_declarative_part > > [begin > > entity_statement_part ] > > end [ entity ] [ entity_simple_name ] ; > >=20 > > entity_header ::=3D > > [formal_generic_clause ] > > [formal_port_clause ] > >=20 > > generic_clause ::=3D generic ( generic_list ) ; > > generic_list ::=3D generic_interface_list > > interface_list ::=3D interface_element { ; interface_element } > > interface_element ::=3D interface_declaration > >=20 > > interface_declaration ::=3D > > interface_constant_declaration > > |interface_wave_constant_declaration > > | interface_signal_declaration > > | interface_variable_declaration > > | interface_file_declaration > >=20 > > interface_constant_declaration ::=3D > > [constant] identifier_list : [ in] subtype_indication [ :=3D static_exp= ression ] > >=20 > > interface_wave_constant_declaration ::=3D > > wave [constant] wave_constant_list : [ in ] subtype_indication > > [ :=3D static_expression ] > >=20 > > wave_constant_list ::=3D=20 > > wave_constant_element { , wave_constant_element } > >=20 > > wave_constant_element ::=3D=20 > > wave_constant > > |internal_wave_constant > >=20 > > wave_constant ::=3D > > series_clock_number > > | input_clock_number > > | multiple_copy_number > >=20 > > internal_wave_constant ::=3D one_hot > >=20 > > entity_declarative_part ::=3D > > { entity_declarative_item } > >=20 > > entity_declarative_item ::=3D > > subprogram_declaration > > | subprogram_body > > | type_declaration > > | subtype_declaration > > | constant_declaration > > | alias_wave_constant_declaration > > | signal_declaration > > |shared_variable_declaration > > | file_declaration > > | alias_declaration > > | attribute_declaration > > | attribute_specification > > | disconnection_specification > > | use_clause > > | group_template_declaration > > | group_declaration > >=20 > > architecture_body ::=3D > > architecture identifier of entity_name is > > architecture_declarative_part > > begin > > architecture_statement_part > > end[ architecture ] [ architecture_simple_name ] ; > >=20 > > architecture_declarative_part ::=3D > > { block_declarative_item } > >=20 > > block_declarative_item ::=3D > > subprogram_declaration > > | subprogram_body > > | type_declaration > > | subtype_declaration > > | constant_declaration > > | alias_wave_constant_declaration > > | signal_declaration > > | shared_variable_declaration > > | file_declaration > > | alias_declaration > > | component_declaration > > | attribute_declaration > > | attribute_specification > > | configuration_specification > > | disconnection_specification > > | use_clause > > | group_template_declaration > > | group_declaration > >=20 > > constant_declaration ::=3D > > constant identifier_list : subtype_indication [ :=3D expression ] ; > >=20 > > alias_wave_constant_declaration ::=3D > > wave [ constant ] alias_wave_constant_list : subtype_indication :=3D=20 > > wave_constant ; > >=20 > > alias_wave_constant_list ::=3D > > alias_wave_constant { , alias_wave_constant } > >=20 > > alias_wave_constant ::=3D identifier > >=20 > > [0070] The set of following rules is called wave constant mechanism: > >=20 > > =E2=80=A2 There are three wave constants related to wave-pipelining tec= hnique: series_clock_number, input_clock_number and multiple_copy_number.= =20 > >=20 > > =E2=80=A2 A wave constant can only be declared in the generic_clause of= the entity definition of a WPC embodiment, plays the same role as a generi= c constant declared in the same place does except that it has actual initia= l value 1 under slow mode, and actual initial value equal to or greater tha= n 1 determined and assigned by a synthesizer under target mode, and the sta= tic expression in an interface wave constant declaration is always ignored. > >=20 > > =E2=80=A2 A WPC instantiation must not include corresponding associatio= n element with a formal wave constant in the generic map aspect.=20 > >=20 > > =E2=80=A2 Any wave constant declared in a WPC definition is accessible = by designers through an alias wave constant declaration. > >=20 > > =E2=80=A2 An alias wave constant declaration identifies a list of alias= wave constants which are assigned a wave constant. Each alias wave constan= t must be linked with a WPC instantiation through a link statement and shar= es the wave constant value of the linked WPC instantiation for testing, deb= ugging or implementing purpose. An alias wave constant plays the same role = as a normal constant declared in the same place does.=20 > >=20 > > =E2=80=A2 A CPC may have any of its linked WPC=E2=80=99s wave constants= and output signals as its own input signal, but must have no input signals= which are related to any unrelated WPC instantiation=E2=80=99s wave consta= nts. > >=20 > > =E2=80=A2 The internal wave constant one_hot is used internally by a sy= nthesizer to optimize the implementation of a WPC and not accessible by des= igners.=20 > >=20 > > =E2=80=A2 A synthesizer has its discretion to determine internal wave c= onstant one_hot value based on the environment and the consideration of its= production technique used unless a WPC input_delay_module has its R_O outp= ut connected in which case one_hot will be =E2=80=981=E2=80=99 in order to = generate valid R_O output signal.=20 > >=20 > >=20 > > Thank you for your reading. > >=20 > > Weng >=20 > Wave-pipelining component series_module (SM) in HDL >=20 > [0071] FIG. 3 is the interface of a WPC embodiment series_module (SM) = linked with a series CPC in FIG. 3A. CLK, RESET and SINI are three standard= input signals for a synchronous component and the same for each of four WP= Cs, and play the same roles. CLK is clock source of the CPC. RESET is a glo= bal asynchronous initialization input signal. SINI is a global synchronous = initialization input signal. Either of RESET/SINI is used to initialize a S= M and one of them must be asserted once to keep SM in initial working statu= s before it is used. One of RESET/SINI is necessary and another is optional= , and if one of RESET/SINI is not used, it must be connected to =E2=80=980= =E2=80=99 to make it optimized out. >=20 > [0072] FIG. 3 has two additional input signals and three output signal= s: > =E2=80=A2 Input signal INI is designed to load initialization data into t= he linked series CPC. Input data at D_I for the linked CPC is initializatio= n data if INI is asserted, or working input data otherwise. The assertion o= f input signal INI may last as long as needed. Input INI must be connected = to =E2=80=980=E2=80=99 or left opened with default value being =E2=80=980= =E2=80=99 if the linked CPC doesn=E2=80=99t need initialization data. Input= signal INI must be asserted after one of RESET/SINI is asserted to make su= re that SM is at the initial state, or wait for the series_clock_number of = clock cycles to let the CPC go empty. > =E2=80=A2 Input signal WE_I drives write enable signal to the input regis= ters of the linked CPC; input data at D_I of the linked CPC will be latched= into the input registers of the CPC on the next clock cycle if WE_I is ass= erted on the current clock cycle, or will not otherwise.=20 > =E2=80=A2 Output signal WE_O drives write enable signal to the output reg= isters of the linked CPC; current arriving wave of combinational logic data= will be latched into the output registers on the next clock cycle if WE_O = is asserted on the current clock cycle, or will not otherwise.=20 > =E2=80=A2 Output signal Valid_O is a data valid output signal; data at D_= O of the linked CPC is valid if Valid_O is asserted or invalid otherwise.= =20 > =E2=80=A2 Output signal S_O is the Q outputs of each of internal right sh= ift registers and may be useful when debugging or implementing a wave-pipel= ining ready code and optional. No extra logic will be generated if it is le= ft opened without connection. >=20 > [0073] The assertion of each of WE_I, WE_O and Valid_O lasts one clock= cycle for each valid input or output data, respectively.=20 >=20 > [0074] FIG. 3A is the interface of a series CPC linked with a WPC seri= es_module in FIG. 3. In addition to the global input signal CLK, the interf= ace has four input signals and one output signal that are essential to wave= -pipelining: > =E2=80=A2 Input signal INI is optional. If it exists, input data at D_I f= or the CPC is initialization data when INI is asserted, or working input da= ta otherwise. The INI assertion may last as long as needed.=20 > =E2=80=A2 Input signal WE_I is shared with the linked SM as write enable = signal to the input registers. > =E2=80=A2 Input signal D_I is data input bus to the CPC.=20 > =E2=80=A2 Input signal WE_O_I is write enable signal to the output regist= ers of the CPC. It comes from the linked SM output signal WE_O and is used = to latch current arriving wave of combinational logic data into output regi= sters.=20 > =E2=80=A2 Output signal D_O is output data bus. Output data at D_O is val= id if output signal Valid_O of the linked SM is asserted, or invalid otherw= ise.=20 >=20 > [0075] A CPC in FIG. 3A may have any number of additional input and ou= tput signals to assist the component and those signals are not drawn here. = The dashed lines between FIG. 3 and FIG. 3A show how input and output signa= ls of two components, a WPC SM and a series CPC, are connected. In addition= to the connection of global clock signal CLK there are three connections b= etween the two connected components:=20 > =E2=80=A2 Input signals INI of both WPC and CPC are connected together if= the CPC needs to load initialization data into it before working normally. > =E2=80=A2 Input signals WE_I of both components are connected. > =E2=80=A2 Output signal WE_O of SM in FIG. 3 drives write enable signal W= E_O_I of its linked series CPC in FIG. 3A. >=20 > [0076] FIG. 4 is the schematics of a WPC embodiment series_module (SM)= linked with a series CPC and with input data acceptable on every clock cyc= le. 400 is a series CPC; 410 is the input registers of input data bus width= ; 420 is its combinational logic circuit; 430 is the output registers of ou= tput data width and input data bus width may be different from output data= width. 440 is a SM linked with a series CPC 400 and comprises two sub-comp= onents: 450 is right shift registers with two or more bits; 460 is the righ= t shift register controller and its schematics are shown in FIG. 4A. In FIG= . 4 dotted line 470 represents the situations when signals take one clock c= ycle to propagate through the series CPC 400 under either slow mode or targ= et mode; dashed lines represent the situations where the design runs under = target mode and signals take X clock cycles to propagate through the series= CPC 400 with X > 1. The dotted line 470 and dashed lines are mutually excl= usive. >=20 > [0077] A SM is essentially right shift registers 450 with a variable l= ength and its controller 460. The right shift registers have X+1 bits, wher= e X is the number of series clock cycles for CPC 400. When a designer desig= ns a series CPC or it runs under slow mode, signals are assumed to take one= clock cycle to propagate through the component, X =3D 1 and the right shif= t registers have 2 bits; when the CPC runs under target mode, its number of= series clock cycles is X, determined by a synthesizer, and the right shift= registers have X+1 bits. S_O output signal is Q outputs of each bit regist= er of the right shift registers 450 for possible debugging or implementing = use and optional. >=20 > [0078] After either RESET or SINI input signal is asserted, the right = shift registers are cleared immediately for RESET or on the next clock cycl= e for SINI. Each bit register of the right shift registers is connected tog= ether one after another with its Q output driving D input of next bit regis= ter with following exceptions:=20 > =E2=80=A2 A 2-input and-gate A0 has one input coupled to input signal WE_= I, another inversely coupled to input signal INI, and its output driving no= de W, D input of the most left bit register FFx and input W of controller 4= 60.=20 > =E2=80=A2 The Q output of second most right bit register drives output si= gnal WE_O. > =E2=80=A2 The Q output of the most right bit register FF0 drives output s= ignal Valid_O.=20 >=20 > [0079] A linked pair of a SM and a CPC has two states based on input s= ignal INI value if the CPC has INI input: > =E2=80=A2 Initial data loading state: When INI is asserted, node W is dea= sserted, leaving right shift registers 450 in an idle state. There will be = no output data latched into the output registers FFo and output signal Vali= d_O will be deasserted. Initialization data will be latched into the input = registers FFi through D_I on the next clock cycle if input signal WE_I is a= sserted on the current clock cycle. > =E2=80=A2 Working state: When INI is deasserted, working data will be lat= ched into the input registers FFi through D_I on the next clock cycle if in= put signal WE_I is asserted on the current clock cycle; right shift registe= rs 450 and its controller 460 are active, output signals WE_O, D_O and Vali= d_O work as designed. >=20 > [0080] In both situations input data will be acceptable on every clock= cycle. Clock signal is not drawn in the present invention for clarity and = simplicity. >=20 > [0081] FIG. 4A is the schematics of the right shift register controlle= r 460 of a WPC series_module (SM). Or-gate OR1 has (X+2) input signals, whe= re X is the number of series clock cycles, and under slow mode X =3D 1. > =E2=80=A2 Each of input signals Q0-Qx is driven by Q output of one bit re= gister of the right shift registers, respectively, and the series CPC has v= alid data if one of Q0-Qx is asserted or invalid data otherwise. > =E2=80=A2 Input signal W is working input data ready signal. If input sig= nal INI of a SM is asserted, W is deasserted; when input signal INI is deas= serted, input signal W is equal to input signal WE_I of the SM.=20 >=20 > [0082] Or-gate OR1 output signal E drives enable signal E to each bit = register of the right shift registers 450. The right shift registers 450 wi= ll right shift one bit on next clock cycle if E is asserted on the current = clock cycle or will not otherwise. Right shift registers 450 will right shi= ft one bit on next clock cycle in either of two situations: > =E2=80=A2 There are valid data in the linked CPC. > =E2=80=A2 There is a working input data to enter the linked CPC. >=20 > [0083] Care must be taken before input signal INI is asserted if its C= PC still contains valid data in it. In the situation the linked SM will con= tinue to work to output internal valid data until it is empty, but the CPC = may change its internal data flow if input signal INI to the CPC is asserte= d, contaminating the outgoing data. Of course, to people in the art the emb= odiment of right shift registers can be replaced by embodiment of left shif= t registers. >=20 > [0084] Based on connections of FIG. 3 and FIG. 3A a WPC series_module = has nothing to do with input data at D_I and output data at D_O of its link= ed CPC, so series_module can handle any types of input data and output data= of a series CPC and doesn=E2=80=99t have any overloading type. >=20 > Weng Here I publish all source code for public confirmation. There must be some = misunderstanding because only part of my application document was published= . You may copy this part of code to do simulation by yourself. The line maxim= um width is 95 char. -- Author: Weng Tianxiang -- Diamond Bar, CA 91705 -- USA -- Email: wtxwtx@gmail.com -- Date: 2014/09/14 -- 2015/01/29 -- Project: Systematic method of coding wave-pipelined circuits in HDL -- File name: WPC-CPC.vhd -- this design is written and works using VHDL-2002 synthsizer -- all changes using VHDL-2008 are noted properly. -- critical path coding is based on the assumption:=20 -- signals take 1 clock cycle to propagate thru any critical path under slo= w_mode=20 -- signals take N clock cycle to propagate thru a critical path under targe= t_mode ---------------------------------------------------------------------------= ---- -- it must do following sets of simulations under different parameter combi= nations -- INI =3D '1', '0' and following conbinations -- ONE_HOT =3D '1', '0' and following conbinations -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1; it generates slow mode -- constant SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- constant INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- for target mode simulation,=20 -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER; -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER; -- it must do 6*2 sets of simulations and it generates target mode -- constant SERIES_CLOCK_NUMBER : positive :=3D 6; =20 -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1.. <=3D SERIES_CLOCK_NUMB= ER -- constant INPUT_CLOCK_NUMBER : positive :=3D 1.. <=3D SERIES_CLOCK_NUMB= ER=20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- used only for this simulation package wave_pipeline_package is=20 -- for target mode simulation,=20 -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER; -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER; -- the number of clock cycles signals takes thru a serial critical path constant SERIES_CLOCK_NUMBER : positive :=3D 6; -- for target mode sim= ulation -- the number of multiple copied CPCs constant MULTIPLE_COPY_NUMBER : positive :=3D 4; -- the number of clock cycles to accept next input data constant INPUT_CLOCK_NUMBER : positive :=3D 3; =20 -- constant MULTIPLE_COPY_NUMBER : positive :=3D 1; -- for slow mode simula= tion -- constant SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- constant INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- '1': use Left_rotator; '0' : use Counter constant ONE_HOT : std_logic :=3D '1'; -- '1': initializaton data; '0': working data=20 constant INI : std_logic :=3D '0'; =20 -- in this simulation, DATA_IN_WIDTH =3D DATA_OUT_WIDTH for simplicity constant DATA_IN_WIDTH : positive :=3D 8; -- data in width constant DATA_OUT_WIDTH : positive :=3D 8; -- data out width -- VHDL-2002 type OUT_DATA_ARRAY is array(natural range <>) of unsigned(DATA_OUT_WIDT= H-1 downto 0); type OUT_SHIFT_ARRAY is array(natural range <>) of unsigned(SERIES_CLOCK= _NUMBER downto 0); -- VHDL-2008 -- type OUT_DATA_ARRAY_8 is array(natural range <>) of unsigned(natural ran= ge <>); end wave_pipeline_package; ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---------------------------------------------------------------------------= ---- -- a wave-pipelining component (WPC) to be linked with a series CPC (CPC) entity series_module is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falling_e= dge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1');-- SINI assertion data port ( =20 -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, an= other is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0':= working data WE_I : in std_logic; -- '1': write enable to input registe= rs WE_O : out std_logic; -- '1': write enable to output regist= ers Valid_O : out std_logic; -- '1': data in output registers is v= alid -- info of right shift registers for assistant use=20 S_O : out unsigned(SERIES_CLOCK_NUMBER downto 0) ); end series_module; ---------------------------------------------------------------------------= ---- architecture A of series_module is signal Right_shift : unsigned(SERIES_CLOCK_NUMBER downto 0);=20 constant C_RS : unsigned(SERIES_CLOCK_NUMBER downto 0) :=3D (othe= rs=3D>'0');=20 signal Working_WE_I: std_logic; -- '1': working input data is ready =20 ---------------------------------------------------------------------------= ---- begin WE_O <=3D Right_shift(1); -- '1': latch output registers Valid_O <=3D Right_shift(0); -- '1': data at output registers is valid S_O <=3D Right_shift; -- output use is optional -- INI =3D '0': Working_WE_I <=3D WE_I; INI =3D'1': Working_WE_I <=3D '0= ' -- '1': working input data is ready Working_WE_I <=3D (not INI) and WE_I; =20 =20 ---------------------------------------------------------------------------= ---- R_With_SINI : process(CLK, RESET) begin if RESET =3D RESET_DATA then Right_shift <=3D (others =3D> '0'); =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Right_shift <=3D (others =3D> '0'); =20 -- right shift 1 position only when: -- 1. Working_WE_I =3D '1': working input data is ready -- 2. Right_shift /=3D C_RS: there is a data in wave-pipeline elsif Working_WE_I =3D '1' or Right_shift /=3D C_RS then Right_shift <=3D Working_WE_I & Right_shift(SERIES_CLOCK_NUMBER= downto 1); end if; end if; end process; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---------------------------------------------------------------------------= ---- -- a WPC input_delay_module is linked with a series or a feedback CPC -- using this module can generate write enable signal to input registers on= every one or=20 -- more clock cycle to relaxe wave-pipelining requirements or meet feedback= requirements -- it also has series critical path and a series_module is used to latch ou= tput registers=20 entity input_delay_module is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- the number of clock cycles to accept next input data -- 1 <=3D INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER -- wave INPUT_CLOCK_NUMBER : positive :=3D 1; =20 INPUT_CLOCK_NUMBER : positive :=3D 1; =20 -- wave ONE_HOT: std_logic :=3D '0'; -- '1': use a rotator; '0': use a = counter ONE_HOT : std_logic :=3D '0'; CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falling_= edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1');-- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, a= nother is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0': = working data Ready_I : in std_logic; -- input data is ready -- advance input data properly if WE_I_O =3D '1' WE_I_O : out std_logic; -- '1': write enable to input regist= ers WE_O : out std_logic; -- '1': write enable to output regis= ters Valid_O : out std_logic; -- '1': data in output registers is = valid -- assistant info S_O : out unsigned(SERIES_CLOCK_NUMBER downto 0);--right shift= registers' output R_O : out unsigned(INPUT_CLOCK_NUMBER-1 downto 0)-- left rotat= or's output ); end input_delay_module; ---------------------------------------------------------------------------= ---- =20 architecture A of input_delay_module is -- ONE_HOT =3D '1': Left_rotator(0) =3D '1': input data is acceptable signal Left_rotator : unsigned(INPUT_CLOCK_NUMBER-1 downto 0); constant Left_rotator_Zero : unsigned(INPUT_CLOCK_NUMBER-1 downto 0) := =3D (others=3D>'0'); -- ONE_HOT =3D '0': Counter =3D 0: input data is acceptable signal Counter : integer range 0 to INPUT_CLOCK_NUMBER-1; -- '1': write enable to input registers, internal use signal WE_I : std_logic; signal Woring_Ready_I : std_logic; -- '1': new working input data= is ready =20 ---------------------------------------------------------------------------= ---- begin -- WE_I =3D '1': write enable to input registers of the linked CPC -- 1. INPUT_CLOCK_NUMBER =3D 1: there is neither rotator nor Counter, WE= _I_O <=3D Ready_I -- 2. INI =3D '1': WE_I_O <=3D Ready_I WE_I <=3D Ready_I when INPUT_CLOCK_NUMBER =3D 1 or INI =3D '1' else = =20 -- ONE_HOT =3D '1': use a left rotator -- 1. Ready_I =3D '1': input data is ready -- 2. Left_rotator(0) =3D 1: indicates that next input data is = acceptable Ready_I and Left_rotator(0) when ONE_HOT =3D '1' else -- ONE_HOT =3D '0': use a counter -- 1. Ready_I =3D '1': input data is ready -- 2. Counter =3D 0: indicates that next input data is acceptab= le Ready_I when Counter =3D 0 else '0'; =20 =20 WE_I_O<=3D WE_I; =20 -- when R_O is connected, ONE_HOT must be '1' R_O <=3D Left_rotator when ONE_HOT =3D '1' else Left_rotator_Zero; =20 -- 1. if INI =3D '1', Woring_Ready_I =3D '0'; no working input data; -- if INI =3D '0', Woring_Ready_I <=3D Ready_I, working input data is= ready Woring_Ready_I <=3D (not INI) and Ready_I; -- '1': working input data = is ready =20 ---------------------------------------------------------------------------= ---- -- the instantiation of series_module is not at the top level, needs spe= cial handling SM_1 : entity work.series_module generic map ( -- wave constant SERIES_CLOCK_NUMBER will inherit SERIES_CLOCK_NUMBER= value at top level -- for this simulation only and skip if "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working d= ata WE_I =3D> WE_I, -- '1': write enable to input registers WE_O =3D> WE_O, -- '1': write enable to output registers Valid_O =3D> Valid_O, -- '1': data in output registers is valid S_O =3D> S_O -- right right shift registers' output ); =20 ---------------------------------------------------------------------------= ---- Register_With_SINI : process(CLK, RESET) begin if INPUT_CLOCK_NUMBER =3D 1 then -- there is neither Left_rotator nor= Counter -- it is empty elsif ONE_HOT =3D '1' then -- use a rotator if RESET =3D RESET_DATA then -- Left_rotator <=3D (0=3D>'1', others=3D>'0'); for J in 0 to INPUT_CLOCK_NUMBER-1 loop Left_rotator(J) <=3D '0'; end loop; Left_rotator(0) <=3D '1'; elsif CLK'event and CLK =3D CLK_EDGE then -- for input registers if SINI =3D SINI_DATA then -- Left_rotator <=3D (0=3D>'1', others=3D>'0'); for J in 0 to INPUT_CLOCK_NUMBER-1 loop Left_rotator(J) <=3D '0'; end loop; Left_rotator(0) <=3D '1'; else -- 1. Left_rotator(0) =3D '0': there is a data in feedback path -- 2. Woring_Ready_I =3D '1': working input data is ready if Left_rotator(0) =3D '0' or Woring_Ready_I =3D '1' then -- left rotate 1 bit Left_rotator <=3D Left_rotator(INPUT_CLOCK_NUMBER-2 downt= o 0) & Left_rotator(INPUT_CLOCK_NUMBER-1); end if; end if; end if; else -- use a counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; else -- 1: Counter /=3D 0: there is a data in feedback path -- 2: Woring_Ready_I =3D '1': working input data is ready if Counter /=3D 0 or Woring_Ready_I =3D '1' then -- Counter =3D (INPUT_CLOCK_NUMBER-1): Counter reaches it= s range limit if Counter =3D (INPUT_CLOCK_NUMBER-1) then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; end if; end if; =20 end process; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- -- a WPC to be linked with multiple copied CPCs=20 -- suffix "_m" of a signal: it is a signal which has multiple sets of input= or output signals -- each of which either comes from or goes to one of multiple copied CPCs. entity multiple_copy_module1 is generic ( -- the number of clock cycles for signals to propagate through a CPC -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- wave MULTIPLE_COPY_NUMBER: positive :=3D 1; -- the number of CPCs c= opied MULTIPLE_COPY_NUMBER : positive :=3D 1; =20 -- wave ONE_HOT : std_logic:=3D '0'; -- '1': use left rotator; '0': u= se counter ONE_HOT : std_logic:=3D '0'; DATA_OUT_WIDTH: positive :=3D 8; CLK_EDGE : std_logic:=3D '1'; -- '1': rising_edge; '0': fallin= g_edge RESET_DATA : std_logic:=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic:=3D '1'); -- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, ano= ther is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0';-- '1': initialization data; '0= ': working data -- on every clock cycle on both s= ituations -- each assertion of following inputs/outputs lasts one clock cycle f= or each valid data Ready_I : in std_logic; -- '1': input data is ready -- VHDL-2002 : input data from each set of output registers=20 Dr_I_m : in OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- VHDL-2008 -- Dr_I_m : in OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); =20 -- '1': write enable to one set of input registers=20 WE_I_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': write enable to one set of output registers WE_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0); -- final o= utput data Valid_O : out std_logic; -- '1': da= ta at D_O is valid -- VHDL-2002, output S_O of each SM S_O_m : out OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0) -- VHDL-2008 -- S_O_m :out OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(SERIES_CLO= CK_NUMBER downto 0) ); end multiple_copy_module1; ---------------------------------------------------------------------------= ---- architecture A of multiple_copy_module1 is -- ONE_HOT =3D '1': determine which CPC is to accept input data signal Left_rotator : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- ONE_HOT =3D '0': determine which CPC is to accept input data signal Counter : integer range 0 to MULTIPLE_COPY_NUMBER-1; -- internal use, =3D WE_I_O_m signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': output registers is valid signal Valid_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 =20 ---------------------------------------------------------------------------= ---- begin WE_I_O_m <=3D WE_I_m; =20 ---------------------------------------------------------------------------= ---- P0 : process(Ready_I, Counter, Left_rotator, Valid_m, Dr_I_m) variable V : std_logic; variable D : unsigned(DATA_OUT_WIDTH-1 downto 0); begin if MULTIPLE_COPY_NUMBER =3D 1 then -- neither Left_rotator, nor Count= er WE_I_m(0) <=3D Ready_I; -- WE_I =3D Ready_I else -- determine which of multiple copied critical paths is to accept = input data for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if ONE_HOT =3D '1' then -- use Left_rotator -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Left_rotator(J) =3D '1': it's its turn to accept input= data WE_I_m(J) <=3D Ready_I and Left_rotator(J); =20 else -- use Counter -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Counter =3D J: it's its turn to accept input data if Ready_I =3D '1' and Counter =3D J then WE_I_m(J) <=3D '1'; -- '1': latch input registers else =20 WE_I_m(J) <=3D '0'; end if; =20 end if; =20 end loop; end if; =20 =20 -- Valid_O <=3D Valid_m(0) or Valid_m(1) or ... V :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then V :=3D V or '1'; end if; =20 end loop; =20 Valid_O <=3D V; =20 -- D_O <=3D (Valid_m(0) and D_I(0)) or (Valid_m(1) and D_I(1)) or ... D :=3D (others=3D>'0'); for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then D :=3D Dr_I_m(J) or D; end if; =20 end loop; D_O <=3D D; end process; =20 ---------------------------------------------------------------------------= ---- -- change the turn bit properly P1 : process(CLK, RESET) begin if MULTIPLE_COPY_NUMBER =3D 1 then -- neither Left_rotator, nor Count= er -- empty elsif ONE_HOT =3D '1' then -- use Left_rotator if RESET =3D RESET_DATA then -- Left_rotator <=3D (Left_rotator(0) =3D> '1', others =3D> '= 0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then -- Left_rotator <=3D (Left_rotator(0) =3D> '1', others =3D= > '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; -- Ready_I =3D '1': there is a valid input data and do left rot= ation once elsif Ready_I =3D '1' then -- left rotate 1 position Left_rotator <=3D Left_rotator(MULTIPLE_COPY_NUMBER-2 downto= 0) & Left_rotator(MULTIPLE_COPY_NUMBER-1); end if; end if; =20 else -- use Counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; -- Ready_I =3D '1': there is a valid input data and increase Co= unter by 1 elsif Ready_I =3D '1' then -- Counter =3D MULTIPLE_COPY_NUMBER-1: it is time for Counte= r to turn around if Counter =3D MULTIPLE_COPY_NUMBER-1 then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; end if; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- call series_module for each of CPCs G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate -- the instantiation of series_module is not at the top level E0 : entity work.series_module generic map ( -- SERIES_CLOCK_NUMBER will inherit data from SERIES_CLOCK_NUMB= ER value at top level=20 -- for this simulation only and skip if "wave" is accepted in H= DL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': = working data WE_I =3D> WE_I_m(J), -- write enabl to each set of inpu= t registers WE_O =3D> WE_O_m(J), -- write enable to each set of out= put registers Valid_O =3D> Valid_m(J), -- '1': data at one set of outut r= egisters is valid S_O =3D> S_O_m(J) -- SM right shift register's info ); end generate; =20 end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- -- a WPC to be linked with multiple copied CPCs entity multiple_copy_module2 is generic ( -- wave SERIES_CLOCK_NUMBER : positive :=3D 1; =20 SERIES_CLOCK_NUMBER : positive :=3D 1; =20 -- wave MULTIPLE_COPY_NUMBER: positive :=3D 1; MULTIPLE_COPY_NUMBER : positive :=3D 1; -- wave ONE_HOT : std_logic :=3D '0'; -- '1': use left rotator; '0':= use counter ONE_HOT : std_logic :=3D '0'; DATA_OUT_WIDTH : positive :=3D 8; -- user must define his output= data width CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': fall= ing_edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1'); -- SINI assertion data port ( -- 3 clock related signals CLK : in std_logic; RESET : in std_logic; -- one of RESET/SINI is necessary, an= other is optional SINI : in std_logic; -- connect the optional to '0' INI : in std_logic :=3D '0'; -- '1': initialization data; = '0': working data -- on every clock cycle on both= situations -- each of following inputs/outputs lasts only one clock cycle for ea= ch valid data Ready_I : in std_logic; -- '1': input data is ready -- VHDL-2002, input from each set of combinational logic outputs Dc_I_m : in OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0);= =20 -- VHDL-2008 -- Dc_I_m : in OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); =20 -- '1': write enable to each set of input registers WE_I_O_m : out unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0); -- final = data output Valid_O : out std_logic; -- '1': data at D_O is valid -- VHDL-2002, output S_O of each SM S_O_m : out OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0) -- VHDL-2008 -- S_O_m: out OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(SERIES_CLO= CK_NUMBER downto 0) ); end multiple_copy_module2; ---------------------------------------------------------------------------= ---- architecture A of multiple_copy_module2 is -- ONE_HOT =3D '1': determine which is to accept input data signal Left_rotator : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- ONE_HOT =3D '0': determine which is to accept input data signal Counter: integer range 0 to MULTIPLE_COPY_NUMBER-1; signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); -- internal= use, =3D WE_I_O_m -- write enable to each set of output registers signal WE_O_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': output registers is valid signal Valid_m: unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 signal D_O_in : unsigned(DATA_OUT_WIDTH-1 downto 0); -- data to output= registers signal WE_Out : std_logic; -- write enable to output registers ---------------------------------------------------------------------------= ---- begin WE_I_O_m <=3D WE_I_m; =20 ---------------------------------------------------------------------------= ---- P0 : process(Ready_I, Counter, Left_rotator, Valid_m) variable V : std_logic; begin if MULTIPLE_COPY_NUMBER =3D 1 then -- there is neither Left_rotator n= or Counter WE_I_m(0) <=3D Ready_I; -- WE_I <=3D Ready_I else -- determine which of multiple copied CPCs is to accept input data for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if ONE_HOT =3D '1' then -- use Left_rotator -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Left_rotator(J) =3D '1': it's its turn to accept input= data WE_I_m(J) <=3D Ready_I and Left_rotator(J); else -- use Counter -- 1. Ready_I =3D '1': a valid input data is ready -- 2. Counter =3D J: it's its turn to accept input data if Ready_I =3D '1' and Counter =3D J then WE_I_m(J) <=3D '1'; -- '1': latch one set of input regis= ters else =20 WE_I_m(J) <=3D '0'; end if; =20 end if; =20 end loop; =20 end if; =20 =20 -- Valid_O <=3D Valid_m(0) or Valid_m(1) or ... V :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if Valid_m(J) =3D '1' then V :=3D '1'; end if; =20 end loop; =20 Valid_O <=3D V; end process; =20 ---------------------------------------------------------------------------= ---- -- call series_module for each of CPCs G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate -- the instantiation of series_module is not at the top level E0 : entity work.series_module generic map ( -- SERIES_CLOCK_NUMBER inherits from SERIES_CLOCK_NUMBER value = at top level=20 -- for this simulation only and skip if "wave" is accepted in H= DL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, CLK_EDGE =3D> CLK_EDGE, RESET_DATA =3D> RESET_DATA, SINI_DATA =3D> SINI_DATA) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': = working data WE_I =3D> WE_I_m(J), -- '1': write enable to input regi= sters WE_O =3D> WE_O_m(J), -- '1': write enable to output reg= isters Valid_O =3D> Valid_m(J), -- '1': data at output registers i= s valid S_O =3D> S_O_m(J) -- SM right shift register's info ); end generate; =20 ---------------------------------------------------------------------------= ---- -- turn bit is updated if Ready_I =3D '1' P1 : process(CLK, RESET) begin if MULTIPLE_COPY_NUMBER =3D 1 then -- there is neither Left_rotator n= or Counter -- it is empty elsif ONE_HOT =3D '1' then -- use Left_rotator if RESET =3D RESET_DATA then -- Left_rotate <=3D (0 =3D> '1', others =3D> '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; =20 elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then -- Right_rotate <=3D (MULTIPLE_COPY_NUMBER-1 =3D> '1', oth= ers =3D> '0'); for J in Left_rotator'range loop Left_rotator(J) <=3D '0'; end loop; =20 Left_rotator(0) <=3D '1'; -- Ready_I =3D '1': there is a valid input data and do left rot= ation once elsif Ready_I =3D '1' then -- left rotate 1 position Left_rotator <=3D Left_rotator(MULTIPLE_COPY_NUMBER-2 downto= 0)=20 & Left_rotator(MULTIPLE_COPY_NUMBER-1); end if; end if; =20 else -- use Counter if RESET =3D RESET_DATA then Counter <=3D 0; elsif CLK'event and CLK =3D CLK_EDGE then if SINI =3D SINI_DATA then Counter <=3D 0; -- Ready_I =3D '1': there is a valid input data and increase Co= unter by 1 elsif Ready_I =3D '1' then -- Counter =3D MULTIPLE_COPY_NUMBER-1: it is time for Counte= r to turn around if Counter =3D MULTIPLE_COPY_NUMBER-1 then Counter <=3D 0; else Counter <=3D Counter+1; end if; end if; end if; =20 end if; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- select circuit for combinational data to output registers is optimize= d for each case P2 : process(WE_O_m, Dc_I_m) variable W : std_logic; variable Out_in: unsigned(DATA_OUT_WIDTH-1 downto 0);=20 begin W :=3D '0'; for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if WE_O_m(J) =3D '1' then W :=3D '1'; end if; =20 end loop; -- WE_Out: write enable to output registers WE_Out <=3D W; =20 case MULTIPLE_COPY_NUMBER is when 1 =3D> D_O_in <=3D Dc_I_m(0); when 2 =3D> if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; when 3 =3D> if WE_O_m(2) =3D '1' then D_O_in <=3D Dc_I_m(2); else =20 if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; end if; =20 when 4 =3D> if WE_O_m(1) =3D '1' or WE_O_m(0) =3D '1' then if WE_O_m(1) =3D '1' then D_O_in <=3D Dc_I_m(1); else D_O_in <=3D Dc_I_m(0); end if; else if WE_O_m(3) =3D '1' then D_O_in <=3D Dc_I_m(3); else D_O_in <=3D Dc_I_m(2); end if; end if; when others =3D> Out_in :=3D (others=3D>'0'); for J in 0 to MULTIPLE_COPY_NUMBER-1 loop if WE_O_m(J) =3D '1' then Out_in :=3D Out_in or Dc_I_m(J); end if; end loop; D_O_in <=3D Out_in; end case; end process; =20 =20 ---------------------------------------------------------------------------= ---- -- combinational logic data D_O_in is clocked in D_O P3 : process(CLK) begin if CLK'event and CLK =3D CLK_EDGE then if WE_Out =3D '1' then D_O <=3D D_O_in; end if; end if; end process; end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; -- to be connected with a WPC series_module, input_delay_module or multiple= _copy_module1 -- its output comes from the output registers entity CPC1 is generic ( -- to simulate the variable combinational logic length SERIES_CLOCK_NUMBER : positive :=3D SERIES_CLOCK_NUMBER; =20 -- following parameters are used only for this simulation, or optiona= l otherwise DATA_IN_WIDTH : positive :=3D DATA_IN_WIDTH; -- data in width DATA_OUT_WIDTH : positive :=3D DATA_OUT_WIDTH; -- data out width CLK_EDGE : std_logic :=3D '1'; -- '1': rising_edge; '0': falli= ng_edge RESET_DATA : std_logic :=3D '1'; -- RESET assertion data=20 SINI_DATA : std_logic :=3D '1'); -- SINI assertion data port ( CLK : in std_logic; -- any number of input/output signals c= an be here=20 R_O_I : in std_logic :=3D '1'; -- 1: D_O is registers output; 0: com= binatinal output INI : in std_logic; -- '1': initialization data; '0': worki= ng data WE_I : in std_logic; -- '1': write enable to input registers= of a CPC D_I : in unsigned(DATA_IN_WIDTH-1 downto 0); -- input data WE_O_I : in std_logic; -- '1': write enable to output registers = of a CPC D_O : out unsigned(DATA_OUT_WIDTH-1 downto 0) -- output registers'= data ); end CPC1; ---------------------------------------------------------------------------= ---- architecture A of CPC1 is type IN_DATA_ARRAY is array(natural range <>) of unsigned(DATA_IN_WIDTH-= 1 downto 0); -- array of internal registers, total =3D SERIES_CLOCK_NUMBER -- reflecting the number of series clock cycles signal R_I : IN_DATA_ARRAY(SERIES_CLOCK_NUMBER-1 downto 0); = =20 signal R_Out : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output regist= ers ---------------------------------------------------------------------------= ---- begin -- D_O comes from output registers R_Out if R_O_I =3D '1' -- or from combinational output R_I(0) otherwise D_O <=3D R_Out when R_O_I =3D '1' else R_I(0); =20 P0 : process(CLK) begin if CLK'event and CLK =3D CLK_EDGE then if INI =3D '1' then -- for loading initialization simulation -- when INI =3D '1' and WE_I =3D '1',=20 -- input data will be latched into input registers if WE_I =3D '1' then R_I(SERIES_CLOCK_NUMBER-1) <=3D D_I; end if; =20 -- for working simulation elsif SERIES_CLOCK_NUMBER =3D 1 then -- when SERIES_CLOCK_NUMBER =3D '1' and WE_I =3D '1',=20 -- input data will be latched into input registers if WE_I =3D '1' then R_I(0) <=3D D_I; end if; =20 elsif WE_I =3D '1' then -- right shift if there is a new input data R_I <=3D D_I & R_I(SERIES_CLOCK_NUMBER-1 downto 1); else =20 -- extend the most recent input data to right R_I <=3D R_I(SERIES_CLOCK_NUMBER-1) & R_I(SERIES_CLOCK_NUMBER-1= downto 1); end if; -- WE_O_I =3D '1': write enable signal to output registers if WE_O_I =3D '1' then R_Out <=3D R_I(0); end if; =20 end if; =20 end process; end A; =20 ---------------------------------------------------------------------------= ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wave_pipeline_package.all; ---------------------------------------------------------------------------= ---- entity WPC_CPC_TEST is end WPC_CPC_TEST; architecture A of WPC_CPC_TEST is ---------------------------------------------------------------------------= ---- signal CLK : std_logic; signal RESET : std_logic; signal SINI : std_logic; signal ClockSerial: unsigned(9 downto 0); -- for series_module testing signal se_Ready_I : std_logic; -- '1': se_D_I is ready signal se_WE_O : std_logic; -- write enable to output registers signal se_D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal se_D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a signal se_Valid_O : std_logic; -- '1': output data at se_D_O is vali= d signal se_S_O : unsigned(SERIES_CLOCK_NUMBER downto 0); -- right= shiftor -- if wave constant mechanism is accepted in HDL=20 -- wave constant New_series: positive :=3D series_clk_number; -- signal se_S_O : unsigned(New_series downto 0); -- right shif= tor =20 -- for input_delay_module testing signal fb_Ready_I : std_logic; -- '1': input data at fb_D_I is ready signal fb_WE_I_O : std_logic; -- write enable to input register signal fb_WE_O : std_logic; -- write enable to outut registers signal fb_D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal fb_D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a signal fb_Valid_O : std_logic; -- '1': output data at fb_D_O is vali= d signal fb_S_O : unsigned(SERIES_CLOCK_NUMBER downto 0); -- right s= hiftor -- if wave constant mechanism is accepted in HDL; an alien wave constant= declaration -- wave constant fb_series_name: positive :=3D series_clk_number;=20 -- signal fb_S_O : unsigned(fb_series_name downto 0); -- left rota= tor signal fb_R_O : unsigned(INPUT_CLOCK_NUMBER-1 downto 0);-- left ro= tator -- if wave constant mechanism is accepted in HDL -- wave fb_input_name: positive :=3D input_clk_number; -- an alien wave con= stant declaration -- signal fb_R_O : unsigned(fb_input_name-1 downto 0); -- left rota= tor =20 -- for duplciate_module1 testing signal D_I : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input= data signal Ready_I : std_logic; -- data at D= _I is ready -- output data from each set of output registers of CPCs -- for VHDL-2002 signal Dr_O_m : OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); -- for VHDL-2008 -- signal Dr_O_m:OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OUT= _WIDTH-1 downto 0); signal D_O : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output da= ta -- '1': write enable to each of input registers signal WE_I_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 -- '1': write enable to each of output registers signal WE_O_m : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0); signal Valid_O : std_logic; -- data at D_O is valid -- for VHDL-2002 only signal Shift_Array: OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); = =20 -- for VHDL-2008 and if wave constant mechanism is accepted in HDL -- wave Series_name : positive :=3D SERIES_CLOCK_NUMBER; -- an alien wave= constant declaration -- wave Multiple_name: positive :=3D MULTIPLE_COPY_NUMBER; -- an alien wave= constant declaration -- signal Shift_Array: OUT_DATA_ARRAY_8(Multiple_name-1 downto 0)(Series_= name downto 0); -- for duplciate_module2 testing signal D_I2 : unsigned(DATA_IN_WIDTH-1 downto 0); -- new input = data signal Ready_I2 : std_logic; -- '1': D_I2 = is ready -- VHDL_2002, output data from combinational logic of each of CPCs signal Dc_O_m2 : OUT_DATA_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); -- for VHDL-2008 -- signal Dc_O_m2:OUT_DATA_ARRAY_8(MULTIPLE_COPY_NUMBER-1 downto 0)(DATA_OU= T_WIDTH-1 downto 0); signal D_O2 : unsigned(DATA_OUT_WIDTH-1 downto 0); -- output dat= a -- '1': write enable to each of input registers signal WE_I_m2 : unsigned(MULTIPLE_COPY_NUMBER-1 downto 0);=20 signal Valid_O2 : std_logic; -- output data at D_O2 is valid -- for VHDL-2002 only signal Shift_Array2: OUT_SHIFT_ARRAY(MULTIPLE_COPY_NUMBER-1 downto 0); =20 -- for VHDL-2008 and if wave constant mechanism is accepted in HDL -- wave Series_name2 : positive :=3D SERIES_CLOCK_NUMBER; -- an alien wave= constant declaration -- wave Multiple_name2: positive :=3D MULTIPLE_COPY_NUMBER;-- an alien wave= constant declaration -- signal Shift_Array2 : OUT_DATA_ARRAY_8(Multiple_name2-1 downto 0)(Seri= es_name2 downto 0); ---------------------------------------------------------------------------= ---- begin RESET <=3D '1', '0' after 4 ns; MainClock : process begin CLK <=3D '1'; wait for 5 ns; CLK <=3D '0'; wait for 5 ns; end process; =20 Ready_I2 <=3D Ready_I; D_I2 <=3D D_I; =20 assert (INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER) -- report if fals= e report "It should be INPUT_CLOCK_NUMBER <=3D SERIES_CLOCK_NUMBER" severity failure; =20 assert (MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER) -- report if fals= e report "It should be MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER" severity failure; =20 ---------------------------------------------------------------------------= ---- -- CLK_EDGE, RESET_DATA and SINI_DATA are not tested here for simplicity GenerateInput : process(RESET, CLK) begin if RESET =3D '1' then ClockSerial <=3D (others=3D>'0'); SINI <=3D '1'; se_Ready_I <=3D '0'; se_D_I <=3D (0=3D>'1', others=3D>'0'); fb_Ready_I <=3D '0'; fb_D_I <=3D (0=3D>'1', others=3D>'0'); Ready_I <=3D '0'; D_I <=3D (0=3D>'1', others=3D>'0'); elsif CLK'event and CLK =3D '1' then SINI <=3D RESET; ClockSerial <=3D ClockSerial + 1; -- for series_module testing if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) =3D "1000" then -- if ClockSerial(0) /=3D '1' then -- if ClockSerial >=3D 2 then se_Ready_I <=3D '1'; else se_Ready_I <=3D '0'; end if; =20 =20 if se_Ready_I =3D '1' then if se_D_I =3D 9 then -- D_I has 1 digit se_D_I <=3D (others=3D>'0'); else se_D_I <=3D se_D_I+1; end if; =20 end if; =20 ---------------------------------------------------------------------------= ---- -- for input_delay_module testing -- if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) =3D "1000" then -- if ClockSerial(1 downto 0) /=3D "11" then -- if ClockSerial >=3D 2 then if (ClockSerial mod 5) /=3D 0 then fb_Ready_I <=3D '1'; else fb_Ready_I <=3D '0'; end if; =20 =20 if fb_WE_I_O =3D '1' then if fb_D_I =3D 9 then -- D_I has 1 digit fb_D_I <=3D (others=3D>'0'); else fb_D_I <=3D fb_D_I+1; end if; =20 end if; =20 ---------------------------------------------------------------------------= ---- -- for multiple_copy_module1/multiple_copy_module2 testing if ClockSerial(2 downto 0) /=3D "110" and ClockSerial(2 downto 0) = /=3D "001" then -- if ClockSerial(3 downto 0) /=3D "1000" then -- if ClockSerial(0) =3D '1' then -- if ClockSerial >=3D 2 then Ready_I <=3D '1'; else Ready_I <=3D '0'; end if; =20 =20 if Ready_I =3D '1' then if D_I =3D 9 then -- D_I has 1 digit D_I <=3D (others=3D>'0'); else D_I <=3D D_I+1; end if; =20 end if; end if; end process; =20 ---------------------------------------------------------------------------= ---- -- if it is accepted in HDL, add link1 statement -- to establish links between series_module and CPC1 -- link1(critical_A, CPC10, New_series); =20 critical_A : entity work.series_module=20 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER) =20 port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initializaton data; '0': working d= ata WE_I =3D> se_Ready_I, -- data is ready to critical paths WE_O =3D> se_WE_O, -- '1': write enable to output registers Valid_O=3D> se_Valid_O, -- '1': data at se_D_O is valid=20 S_O =3D> se_S_O -- shift regiters info ); CPC10 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional WE_I =3D> se_Ready_I, -- 1. write enable to input registers D_I =3D> se_D_I, -- not related to series_module WE_O_I =3D> se_WE_O, -- 2. new write enable to output registers= =20 D_O =3D> se_D_O -- not related to series_module ); =20 ---------------------------------------------------------------------------= ---- =20 -- if it is accepted in HDL, add link2 statement -- establish links among input_delay_module, fb_user_module, fb_series_name= and fb_input_name -- link2(Feedback_A, fb_user_module1, fb_series_name, fb_input_name); Feedback_A : entity work.input_delay_module generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 INPUT_CLOCK_NUMBER =3D> INPUT_CLOCK_NUMBER, ONE_HOT =3D> ONE_HOT) port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional Ready_I =3D> fb_Ready_I, -- data is ready to write into input regis= ters WE_I_O =3D> fb_WE_I_O, -- '1': write enable to input registers WE_O =3D> fb_WE_O, -- '1': write enable to output registers Valid_O =3D> fb_Valid_O, -- data at output registers is valid S_O =3D> fb_S_O, R_O =3D> fb_R_O ); =20 -- after a feedback_user_module linked with a input_delay_module it beha= ves as normal -- critical path module, but one input data is accepted per INPUT_CLOCK_= NUMBER clock cycles=20 -- and no wave-pipelining can be used through the feedback path=20 fb_user_module1 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initializaton data; '0': working d= ata; optional WE_I =3D> fb_WE_I_O, -- 1. write enable to input registers D_I =3D> fb_D_I, -- not related to input_delay_module WE_O_I =3D> fb_WE_O, -- 2. new write enable to output registers= =20 D_O =3D> fb_D_O -- not related to input_delay_module ); =20 ---------------------------------------------------------------------------= ---- =20 -- if it is accepted in HDL, add link3 statement to establish links among -- multiple_copy_module1, multiple copied CPCs and their linked alien wave = constants -- link3(multiple_A, G0, user_module0, Multiple_name, Series_name);=20 multiple_A : entity work.multiple_copy_module1 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, MULTIPLE_COPY_NUMBER =3D> MULTIPLE_COPY_NUMBER, ONE_HOT =3D> ONE_HOT, DATA_OUT_WIDTH =3D> DATA_OUT_WIDTH)-- it is necessary if width is dif= ferent from default port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working = data Ready_I =3D> Ready_I, -- data is ready for the critical path Dr_I_m =3D> Dr_O_m, -- 1. data from each of output registers WE_I_O_m =3D> WE_I_m, -- 2. write enable to each of input regist= ers WE_O_m =3D> WE_O_m, -- 3. write enable to each of output regis= ters D_O =3D> D_O, -- output data from multiple copied critic= al paths Valid_O =3D> Valid_O, -- '1': data at D_O is valid=20 S_O_m =3D> Shift_Array -- right shiftor's array ); -- user provides his own CPC1 with or without a feedback -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER -- MULTIPLE_COPY_NUMBER gets its proper value through link3() and multip= le_A G0 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate =20 user_module0 : entity work.CPC1 port map ( CLK =3D> CLK, =20 INI =3D> INI, -- '1': initialization data; '0': working = data; optional WE_I =3D> WE_I_m(J), -- 2. write enable to input registers D_I =3D> D_I, -- each has the same data input WE_O_I =3D> WE_O_m(J), -- 3. new write enable to output registers= =20 D_O =3D> Dr_O_m(J) -- 1. each has its own output data ); end generate; =20 ---------------------------------------------------------------------------= ---- -- if it is accepted in HDL, add link3 statement to establish links among -- multiple_copy_module2, multiple copied CPCs and their alien wave constan= ts -- link3(multiple2_A, G2, user_module20, Multiple_name2, Series_name2); multiple2_A : entity work.multiple_copy_module2 generic map ( -- for this simulation only and skip after "wave" is accepted in HDL SERIES_CLOCK_NUMBER =3D> SERIES_CLOCK_NUMBER, =20 MULTIPLE_COPY_NUMBER =3D> MULTIPLE_COPY_NUMBER, ONE_HOT =3D> ONE_HOT, DATA_OUT_WIDTH =3D> DATA_OUT_WIDTH)-- it is necessary if width is dif= ferent from default port map ( CLK =3D> CLK, RESET =3D> RESET, SINI =3D> SINI, INI =3D> INI, -- '1': initialization data; '0': working = data Ready_I =3D> Ready_I2, -- data is ready to critical paths Dc_I_m =3D> Dc_O_m2, -- 1. combinational logic input to each of= output registers WE_I_O_m =3D> WE_I_m2, -- 2. write enable to each of input regist= ers D_O =3D> D_O2, -- output data from multiple copied critic= al paths Valid_O =3D> Valid_O2, -- '1': data at D_O is valid=20 S_O_m =3D> Shift_Array2-- info of right shiftors=20 ); -- user provides his own CPC1 with or without a feedback -- 1 <=3D MULTIPLE_COPY_NUMBER <=3D SERIES_CLOCK_NUMBER -- MULTIPLE_COPY_NUMBER gets its proper value through link3() and multip= le_A G2 : for J in 0 to MULTIPLE_COPY_NUMBER-1 generate =20 user_module20 : entity work.CPC1 port map ( CLK =3D> CLK, =20 R_O_I =3D> '0', -- output D_O comes from combinatinal logi= c INI =3D> INI, -- '1': initializaton data; '0': working d= ata WE_I =3D> WE_I_m2(J), -- 2. write enable to input registers D_I =3D> D_I2, -- each has the same data input WE_O_I =3D> '0', -- its output registers will be optimized = out D_O =3D> Dc_O_m2(J) -- 1. each has its own output data ); end generate; ---------------------------------------------------------------------------= ---- =20 end A; From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.102.66 with SMTP id fm2mr7123360pab.4.1427231058600; Tue, 24 Mar 2015 14:04:18 -0700 (PDT) X-Received: by 10.140.83.165 with SMTP id j34mr105308qgd.8.1427231058552; Tue, 24 Mar 2015 14:04:18 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!z20no2938151igj.0!news-out.google.com!q90ni527qgd.1!nntp.google.com!h3no4602594qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 14:04:17 -0700 (PDT) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.49.104.28; posting-account=9GnU7goAAAAHU53ujXD8Ejd5wZPBXz8p NNTP-Posting-Host: 50.49.104.28 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: Derek Simmons Injection-Date: Tue, 24 Mar 2015 21:04:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8169 If somebody tells me that they are going to school to become a doctor, I co= ngratulate tham and ask them if they have an area of interest. You haven't = told us what or area of interest or what you intend on using it for. So, in= the vein of a column in my favorite guitar magazine titled, "What strings = do you use?," I have answered,"What VHDL and computer design books are on y= our bookshelf." There are a lot of books here but I have gotten rid of a lot more and these= are the ones I've held onto. VHDL LANGUAGE TEXTS Pong P. Chu, "RTL Hardware Design Using VHDL: Coding for Efficiency, Portab= ility, and Scalability," ISBN: 0-471-72092-5. This is my preferred text at = the moment but the big sore spot is its price tag. The information is up to= date. I really liked the chapters Register Transfer Methodology and I foun= d them invaluable in implementing a vector-matrice math processor. [NOTE: A= t one time somebody announced in this group the public release of a library= of vector and matrice primitives. Sure enough, somebody grab the library a= nd did a literal implementation of their algorithm. They came back and bash= ed the library because they ran out of resources. If I was their boss I wou= ld be embarassed and considered sending them on an unpaid sabbatical to lea= rn VHDL and resource sharing.] Peter J. Ashenden, "The designer's Guide to VHDL," ISBN: 1-55860-270-4. Thi= s the text I really learned VHDL from. I made two passes at reading and doi= ng the exercises. The exercises in the text are given a difficulty level of= 1 to 4. On the first pass I did the problems with difficulty rating of 1 t= o 3. On the second pass I created test benches to demonstrate the solutions= and I did the level 4 problems. My favorite problem to talk about is at th= e end of Chapter 14, "Generate Statements", problem 14. The problem ask you= to create a hypercube multicomputer. The solution allows you to paramteriz= e the number of nodes. Each node is made up of a router and a processing el= ement. The router would pass a packet from a node to its destination node f= ollowing a specific set of rules. When it reached its destination the proce= ssor I created would create a new destination node. My test bench showed th= at it could systematically pass the packet to each node. Then I should each= node could route a packet from one node to each of the others. And, finall= y I showed it could route using each of the links between nodes. It makes f= or interesting discussions at job interviews. Sundar Rajan, "Essential VHDL: RTL Synthesis Done Right," ISBN:0-9669590-0-= 0. This book is a fast pace introduction to VHDL and really interesting exa= mples. I would recommend this to somebody that is faced with a small to med= ium size project but also would recommend that they have a copy of CHU's or= ASHENDEN's for a more indepth coverage of material. Peter Wilson, "Design Recipes for FPGAs," ISBN: 978-0-7506-6845-3. I wouldn= 't say they are good examples but I found it useful in solving writers bloc= k. Nothing is more frustrating then trying to do something and you can see = the solution in your head but can connect it with how to implement it. Some= times paging through this I see something related or even unrelated then al= l the peices of the problem I'm trying to solve fall into place. Douglas J. Smith, "HDL Chip Design: A Practical Guide for Designing, Synthe= sizing and Simulating ASICs and FPGAs using VHDl or Verilog," ISBN: 0-96519= 34-3-8. I include this only as an honorable mention because it was a highly= respected text but as VHDL as evolved it has become dated. Some engineers = still cling to it. If somebody referes to the blue book or a blue book, thi= s is the book they referring to. If you can borrow a copy its worth looking= through. I keep my copy because the typography, layout and organization ma= ke it easy to read.=20 ADVANCED VHDL TEXTS Steve Kilts, "Advanced FPGA Design: Architecture, Implementation, and Optim= ization," ISBN: 970-0-470-05437-6. An advance practices text. It guides the= reader through solving more difficult design issues that are more system r= elated then VHDL related. Jean-Pierre Deschamps, G=E9ry Jean Antoine Bioul and Gustavo D. Sutter, "Sy= nthesis of Arithemtaic Circuits: FPGA, ASIC, and Embedded Systems," ISBN: 0= -471-68783-9. The problems I'm normally faced with are math oriented or hea= vily math dependent. There is VHDL code on the author's website for the exa= mples in the text. Charles H. Roth, Jr., "Digital Systems Design Using VHDL," ISBN: 0-534-9509= 9-X. This book is dated. It was from the period of when PCs had 486's for p= rocessors. I liked the examples and exercises. I don't recommend it but if = you find a copy I think its worth your time to page through to see if anyth= ing sparks your interest. The reason I keep it is because it has design exa= mples for UART and floating point multiplier.=20 OTHER Clive "Max" Maxfield, "The Design Warrior's Guide to FPGA's: Devices, Tools= and Flows," ISBN: 0-7506-7604-3. If you are working in industry or a stude= nt you should read this at least once. If you take to heart the topics it c= overs will give your work the WOW factor. When you are writing your design = and engineering documents and you're 2/3 of the way through it, page throug= h this book to see if you are missing anything or you can add something mor= e. If you do that, someday somebody is going to say "Wow, I didn't think of= that!" It talks about all that other stuff that isn't part of coding but i= s just as important, like design flow, reusability, intellectual property, = ect. Wim Vanderbauwhede and Khaled Benkrid, "High-Performance Computing Using FP= GAs," ISBN: 978-1-4614-1790-3. My area of interest is in accelerating appl= ications. So, this book would be of particular interest for my objectives.= =20 COMPUTER ARCHITECTURE Kai Hwang, "Advanced Computer Architecture: Parallelism, Scalability, Progr= ammability," ISBN: 0-07-031622-8. This is a basic computer architecture boo= k. As architects study buildings and arcitecture I think more of an emphasi= s should be given to studying computer systems and computer architecture. Kai Hwang, "Computer Arithmetic: Principles, Architecture, and Design," ISB= N: 0-471-03496-7. This book has case studies on how arithematic functions a= nd pipelines were implemented in computer systems when both processor and m= emory were expensive. I didn't copy it but reading the sections on the TI A= SC gave me my eureka moment for my vector-matrice processor. The TI ASC had= a scalable SIMD architecture. It could be purchased with 1 to 4 math pipes= . Kai Hwang and Fay=E9 A. Briggs, "Computer Architecture and Parallel Process= ing," ISBN: 0-07-031556-6. Were as Hwang's first text was a first semester = text this would be the second semester text for a course study in computer = design and architecture. This book describes the processor architecture of = parallel processors and super computers. More information on the TI ASC and= CDC Star-100.=20 Israel Koren, "Computer Arithmetic Algorithms," ISBN: 1-56881-160-8. The 20= years apart that this book was published from Kai's there isn't a big diff= erence in material and it makes you wonder is Kai was a head of his time or= has so little really changed.=20 From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.43.16.70 with SMTP id px6mr29320179icb.28.1427250244689; Tue, 24 Mar 2015 19:24:04 -0700 (PDT) X-Received: by 10.182.24.5 with SMTP id q5mr67425obf.30.1427250244629; Tue, 24 Mar 2015 19:24:04 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no4553618igj.0!news-out.google.com!db6ni62281igc.0!nntp.google.com!z20no4553609igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Mar 2015 19:24:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:ac9e:4260:1157:ae24; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:ac9e:4260:1157:ae24 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Wed, 25 Mar 2015 02:24:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8170 On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > > Here I publish all source code for public confirmation. > What exactly would you like the public to confirm? Do you have made some specific claims? Given that you have not claimed anything specific, I can only confirm the following: - It does compile (Modelsim 10.3c) - It does synthesize to something (Quartus 14.0; Top level entity=CPC1; 56 Max II logic elements) > > You may copy this part of code to do simulation by yourself. > Why would I want to simulate it? Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.226.46 with SMTP id rp14mr10030195pac.0.1427280328169; Wed, 25 Mar 2015 03:45:28 -0700 (PDT) X-Received: by 10.50.148.98 with SMTP id tr2mr384017igb.3.1427280328111; Wed, 25 Mar 2015 03:45:28 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z20no4718019igj.0!news-out.google.com!db6ni62798igc.0!nntp.google.com!z20no4718014igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 03:45:27 -0700 (PDT) In-Reply-To: <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Wed, 25 Mar 2015 10:45:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 11 Xref: mx02.eternal-september.org comp.lang.vhdl:8171 On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote: > Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer. > > MIT Sues Funai Over 4 HDTV Patents > http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents > > Weng > The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included. -dan From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.65.37 with SMTP id u5mr10319634obs.27.1427281398834; Wed, 25 Mar 2015 04:03:18 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr386646igl.8.1427281398774; Wed, 25 Mar 2015 04:03:18 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z20no3100390igj.0!news-out.google.com!db6ni62798igc.0!nntp.google.com!z20no4726539igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 04:03:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: NCVHDL VHDL-2008 support? From: Daniel Kho Injection-Date: Wed, 25 Mar 2015 11:03:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 12 Xref: mx02.eternal-september.org comp.lang.vhdl:8172 Hi all, I was thinking if I should be trying ncsim/ncvhdl, but before I do that, I'= d like to hear from those of you who have used the tool regarding its suppo= rt on VHDL-2008 features. There isn't much information with a Google search= , so I thought I'd ask a question here. Also, hopefully the simulator complies strictly with the older versions of = VHDL. I am using a simulator which does NOT report errors when I am driving= an unresolved net with multiple sources, which is not legal in VHDL. Hopef= ully, ncsim can do better than that. Best regards, Daniel From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.182.44.199 with SMTP id g7mr4636789obm.11.1427303040208; Wed, 25 Mar 2015 10:04:00 -0700 (PDT) X-Received: by 10.182.247.39 with SMTP id yb7mr108281obc.36.1427303040135; Wed, 25 Mar 2015 10:04:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no3207659igj.0!news-out.google.com!qk8ni67122igc.0!nntp.google.com!z20no3207658igj.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 25 Mar 2015 10:03:59 -0700 (PDT) In-Reply-To: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.179.30.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.179.30.93 References: <00522d52-1e53-4ab5-8c23-e2035623fa8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Learning VHDL beyond basics From: bknpk@hotmail.com Injection-Date: Wed, 25 Mar 2015 17:04:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8173 On Friday, January 9, 2015 at 3:09:03 PM UTC+2, johan.fa...@gmail.com wrote= : > a month ago I decided that I was lacking FPGA knowhow, said and done I or= dered an experiment board (beeing an opensource aficionado I ordered the Lo= gicStart MegaWing bundle with a Papilio One 500k) and two books, Ashenden's= "The Designers Guid to VHDL" and Pong Chu's "FPGA Prototyping by VHDL Exam= ples: Spartan 3". My reasoning behind these two books is that I start with = Ashenden to learn the whole language then go to Pong to learn how to write = syntezisable VHDL, since both contain exercises they make for really good s= elf teaching material. I know Pong is targeting another experiment board bu= t it's the same FPGA and im very confident I can myself make adjustments, e= xcept for e.g. the PS2 port which my papilio thankfully does not have. >=20 > I have now started to search for what to do after these books, how do I g= et more advanced in my FPGA knowledge. I'm a software guy and if I got the = question "I want to start programming" from someone new to programming I wo= uld recomend a good starting book in python, then a good book on how to do = test driven design, then a book about patterns, then moving to C followed b= y a book about object oriented design, then perhaps going for a best practi= ce book and so on, by level of complexity and relevance. I have scoured the= internet (or feels like it) to find such a list regarding FPGA, but at no = luck so far, so thinking of posting the question here. >=20 > I have looked at three books for continued learning after I'm finished wi= th Pong >=20 > Volnei Pedroni: Circuit Design and Simulation with VHDL ; seems to be aim= ed at explaining deeper the differences beetwen syntezisable and simulated = VHDL. Though it seem to go through the VHDL language constructs yet again p= erhaps it is too much overlapping with Pong and Ashenden >=20 > Volnei Pedroni: Finite State Machines in Hardware: Theory and Design ; se= ems a good continuation, I understand that FSM is a very important topic in= HW world and that they are completely different from SW FSM, also it seem = to have excersises after each chapter which is good. >=20 > Pong Chu - RTL Hardware Design Using VHDL: Coding for Efficiency, Portabi= lity, and Scalability ; seems good, no more comments. >=20 > Thats my thinking, any suggestions or comments? Have not come about any b= ooks regarding FPGA testing? Perhaps I should look outside the more hands o= n book to one of the "meta" books out there? May I recommend an IP stack implemented in FPGA. It was simulated using the= free VHDL simulator: GHDL. It was synthesized using xilinx free tool and s= imulated again with post NGD net-list. All scripts and explanations are at: http://bknpk.ddns.net/my_web/IP_STACK/start_1.html From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.66.249.99 with SMTP id yt3mr16920036pac.13.1427448090192; Fri, 27 Mar 2015 02:21:30 -0700 (PDT) X-Received: by 10.140.91.118 with SMTP id y109mr75871qgd.39.1427448090069; Fri, 27 Mar 2015 02:21:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z20no238247igj.0!news-out.google.com!q90ni531qgd.1!nntp.google.com!h3no5129392qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Mar 2015 02:21:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Subject: Quad SPI FLASH memory problems From: niv Injection-Date: Fri, 27 Mar 2015 09:21:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8174 Has anyone tried the Spansion s25fl series of FLASH memories with Quad SPI = interface? I've downloaded their VHDL model, but can't get it to talk. I've written s= ome very simple code to read a few addresses using just single SPI mode, bu= t I get nothing back, and all looks OK in the wave view for the read cycle = (command X"03"). I can see my initialisation data correct in the FLASH arr= ay, but just can't get the model to work, (or create an SDF file with their= tools)! Has anyone had any luck with this model? (I've used an s29... FLASH succes= sful in the past, but that's standard FLASH with addr & data busses etc). Any hints/help welcome. From newsfish@newsfish Tue Dec 29 16:43:46 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Quad SPI FLASH memory problems Date: Fri, 27 Mar 2015 08:21:42 -0400 Organization: Alacron, Inc. Lines: 14 Message-ID: References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Mar 2015 12:22:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32192"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+VgmKBkLIJyAZ6JorZB5+gwc+Ey0F4KPs=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Cancel-Lock: sha1:d1aWXt/orD1zVcs5M0Kw/N6j3ro= Xref: mx02.eternal-september.org comp.lang.vhdl:8175 niv wrote: > Has anyone tried the Spansion s25fl series of FLASH memories with Quad SPI interface? > I've downloaded their VHDL model, but can't get it to talk. I've written some very simple code to read a few addresses using just single SPI mode, but I get nothing back, and all looks OK in the wave view for the read cycle (command X"03"). I can see my initialisation data correct in the FLASH array, but just can't get the model to work, (or create an SDF file with their tools)! > Has anyone had any luck with this model? (I've used an s29... FLASH successful in the past, but that's standard FLASH with addr & data busses etc). > Any hints/help welcome. What are you seeing on the data output? Is it "X" or "U"? Usually the models for these parts allow you to define the contents of the flash memory cells, but it's possible that they start up undefined by default if your model doesn't write them first. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:46 2015 X-Received: by 10.68.168.99 with SMTP id zv3mr23109884pbb.6.1427482677600; Fri, 27 Mar 2015 11:57:57 -0700 (PDT) X-Received: by 10.140.39.148 with SMTP id v20mr336369qgv.24.1427482677512; Fri, 27 Mar 2015 11:57:57 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!z20no708500igj.0!news-out.google.com!q90ni531qgd.1!nntp.google.com!h3no5242316qgf.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 27 Mar 2015 11:57:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1badbaa6-9e1c-4d26-977a-76ec78e08a12@googlegroups.com> Subject: Re: Quad SPI FLASH memory problems From: niv Injection-Date: Fri, 27 Mar 2015 18:57:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8176 I have initialised the memory, I can see the values in the array after "running" for 0 ps. However, the output of the memory on the SPI line remains at 'H', not the data value(s) I'm expecting when reading. From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.68.209.164 with SMTP id mn4mr26725055pbc.8.1427541394673; Sat, 28 Mar 2015 04:16:34 -0700 (PDT) X-Received: by 10.50.35.162 with SMTP id i2mr58124igj.4.1427541394637; Sat, 28 Mar 2015 04:16:34 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no249484igd.0!news-out.google.com!db6ni128igc.0!nntp.google.com!h15no133915igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 04:16:33 -0700 (PDT) In-Reply-To: <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 28 Mar 2015 11:16:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8177 On Wednesday, March 25, 2015 at 3:45:34 AM UTC-7, Daniel Kho wrote: > On Friday, 6 March 2015 02:14:05 UTC+8, Weng Tianxiang wrote: > > Here is an example that MIT has 4 patents for HDTV and now it is suing a Japanese HDTV manufacturer. > > > > MIT Sues Funai Over 4 HDTV Patents > > http://www.law360.com/articles/342212/mit-sues-funai-over-4-hdtv-patents > > > > Weng > > > > The Japanese manufacturer is not a standard body. What was said earlier was that no standard body would want to be burgeoned by patents, IEEE included. > > -dan -dan, It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard. Here is a Wikipedia website for your reference on how international standard body works. http://en.wikipedia.org/wiki/3GPP Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents: http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents: http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions. Weng From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.70.90.4 with SMTP id bs4mr28355054pdb.7.1427563760623; Sat, 28 Mar 2015 10:29:20 -0700 (PDT) X-Received: by 10.140.25.233 with SMTP id 96mr176582qgt.26.1427563760358; Sat, 28 Mar 2015 10:29:20 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no397503igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no153395qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 10:29:20 -0700 (PDT) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.179.30.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.179.30.93 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8e18c445-37bc-4a72-89fe-c02ac04a0402@googlegroups.com> Subject: Re: Quad SPI FLASH memory problems From: bknpk@hotmail.com Injection-Date: Sat, 28 Mar 2015 17:29:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8178 On Friday, March 27, 2015 at 12:21:35 PM UTC+3, niv wrote: > Has anyone tried the Spansion s25fl series of FLASH memories with Quad SP= I interface? > I've downloaded their VHDL model, but can't get it to talk. I've written= some very simple code to read a few addresses using just single SPI mode, = but I get nothing back, and all looks OK in the wave view for the read cycl= e (command X"03"). I can see my initialisation data correct in the FLASH a= rray, but just can't get the model to work, (or create an SDF file with the= ir tools)! > Has anyone had any luck with this model? (I've used an s29... FLASH succ= essful in the past, but that's standard FLASH with addr & data busses etc). > Any hints/help welcome. -------------------------------------------------------- You may want to look on this work, which uses samsung flash "The existing SD slave project was extended recently to support a Samsung f= lash instead of the XILINX ROM components, which are used in the free versi= on of the code. The new design uses a FIFO, build up of XILINX dual port RAM components, in= both the direction of SD read from flash and SD write to flash. It was written in VHDL both design and test-bench..." http://bknpk.ddns.net/my_web/SDIO/sd_to_flash_write.html From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.24.74 with SMTP id s10mr8848941obf.8.1427564328538; Sat, 28 Mar 2015 10:38:48 -0700 (PDT) X-Received: by 10.140.97.137 with SMTP id m9mr404101qge.12.1427564328436; Sat, 28 Mar 2015 10:38:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!h15no401326igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no154810qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 10:38:48 -0700 (PDT) In-Reply-To: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <42500821-75e2-4f2e-b954-17803bbfc79f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Quad SPI FLASH memory problems From: niv Injection-Date: Sat, 28 Mar 2015 17:38:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8179 Thanks for trying to help, but that's not the issue. I have written interf= aces to FLASH memory (with address & data lines etc) quite successfully, it= 's the new Quad SPI version I cannot get to respond to my, so far very simp= le, commands. The stimulus into the SPI in looks as per FLASH data sheet, = but I get not response on the SPI out pin of the FLASH. What I really need is example VHDL code of driving a QSPI FLASH. It may be= the model is not working because I don't have an sdf for it yet, but I exp= ected it to work, albeit without the expected access delays. From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.236.20.234 with SMTP id p70mr22931304yhp.46.1427604419938; Sat, 28 Mar 2015 21:46:59 -0700 (PDT) X-Received: by 10.50.221.44 with SMTP id qb12mr97881igc.11.1427604419896; Sat, 28 Mar 2015 21:46:59 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no229937qgd.1!news-out.google.com!db6ni763igc.0!nntp.google.com!h15no354410igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 28 Mar 2015 21:46:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=119.74.37.137; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 119.74.37.137 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Sun, 29 Mar 2015 04:46:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3197 X-Received-Body-CRC: 2366743841 Xref: mx02.eternal-september.org comp.lang.vhdl:8180 On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > -dan, > It is too simple and naive to think a patent holder should relinquish its= patent rights to let their patents to be part of an international standard= . >=20 > Here is a Wikipedia website for your reference on how international stand= ard body works. >=20 > http://en.wikipedia.org/wiki/3GPP >=20 > Here is a news about standard-essential patents: ITU to address surge in = litigation over standards-essential patents: > =20 > http://www.computerworld.com/article/2505517/technology-law-regulation/it= u--to-address-surge-in-litigation-over-standards-essential-patents.html >=20 > Another related news about standards patents: Nokia, HP, Verizon back FTC= against import bans over standards patents: >=20 > http://www.computerworld.com/article/2504127/technology-law-regulation/no= kia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html >=20 > Why currently VHDL committee has so many difficulties financially to get = industries into its activities? One most important reason is that VHDL is n= ow free to use for all related companies and they don't have to make their = contributions. >=20 > Weng That's the reason why standard bodies have by-laws that make sure any infor= mation submitted or discussed within working groups are not encumbered by p= atents. If you are trying to discuss your patent idea within a working grou= p, you need to declare that the information has been patented. In which cas= e, the Chair will tell the whole group to not use that information in the s= tandardization process. I think this is how it goes for most standard bodie= s. -dan From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.50.73.7 with SMTP id h7mr9016005igv.2.1427618551638; Sun, 29 Mar 2015 01:42:31 -0700 (PDT) X-Received: by 10.50.43.133 with SMTP id w5mr106170igl.16.1427618551601; Sun, 29 Mar 2015 01:42:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no382539igd.0!news-out.google.com!q14ni2214ign.0!nntp.google.com!h15no671028igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 01:42:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.153.32.66; posting-account=0KW5lQoAAABimvhLxpMPGETu7egRGajt NNTP-Posting-Host: 203.153.32.66 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Subject: there is a problem with if statement please help me From: rama hareesh Injection-Date: Sun, 29 Mar 2015 08:42:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8181 here my code is i am doing lift control based on spartan 3e for my 4th year student here there a problem with if condition here my problem will present if srx='1' library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity lift is Port ( b0 : in STD_LOGIC; clk: in std_logic; b1 : in STD_LOGIC; b2 : in STD_LOGIC; srx : in STD_LOGIC; s0 : out STD_LOGIC; s1 : out STD_LOGIC; s2 : out STD_LOGIC; m1 : out STD_LOGIC; m0 : out STD_LOGIC); end lift; architecture Behavioral of lift is type STATE_TYPE is (f0, f1, f2, mup1,mup2,mdown1, mdown0); signal nes:state_type; begin process(b0,b1,b2,srx,clk) begin if(clk' event and clk='1') then case nes is --Ground floor when f0=> s0<='1'; s1<='0'; s2<='0'; if srx='1' then --m1<='0'; --m0<='0'; if b1='1' then s0<='0'; -- s1<='1'; -- s2<='0'; --m1<='1'; --m0<='0'; nes<=mup1; elsif b2='1' then s0<='0'; s1<='0'; s2<='1'; --m1<='1' after 5ns; --m0<='0'; nes<=mup2; else nes<=f0; end if; end if; -- first floor up when f1=> if srx='1' then -- m1<='0'; -- m0<='0'; if b0='1' then s0<='1'; s1<='0'; s2<='0'; m1<='0' after 5ns; m0<='1'; nes<=mdown0; elsif b2='1' then s0<='0'; s1<='0'; s2<='1'; --m1<='1' after 5ns; --m0<='0'; nes<=mup2; else nes<=f1; end if; end if; -- sencond floor when f2=> if srx ='1' then -- m1<='0'; -- m0<='0'; if b0='1' then s0<='1'; s1<='0'; s2<='0'; --m1<='0' after 5ns; --m0<='1'; nes<=mdown0; elsif b1='1' then s0<='0'; s1<='1'; s2<='0'; --m1<='0' after 5ns; --m0<='1'; nes<=mdown1; else nes<=f2; end if; end if; when mup1=> m1<='1'; m0<='0'; s0<='0'; s1<='1'; s2<='0'; if srx='0' then m1<='0'; m0<='0'; nes<=f1; else nes<=mup1; end if; when mup2=> m1<='1'; m0<='0'; nes<=f2; when mdown1=> m1<='0'; m0<='1'; nes<=f1; when mdown0=> m1<='0'; m0<='1'; nes<=f0; end case; end if; end process; end Behavioral; From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.43.100.138 with SMTP id cw10mr12820134icc.5.1427652010349; Sun, 29 Mar 2015 11:00:10 -0700 (PDT) X-Received: by 10.50.66.227 with SMTP id i3mr127597igt.14.1427652010335; Sun, 29 Mar 2015 11:00:10 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no910504igd.0!news-out.google.com!q14ni2565ign.0!nntp.google.com!h15no910493igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 11:00:09 -0700 (PDT) In-Reply-To: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0612675a-5d72-486f-98a3-05ac04a1bd73@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sun, 29 Mar 2015 18:00:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8182 On Saturday, March 28, 2015 at 9:47:01 PM UTC-7, Daniel Kho wrote: > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > > -dan, > > It is too simple and naive to think a patent holder should relinquish its patent rights to let their patents to be part of an international standard. > > > > Here is a Wikipedia website for your reference on how international standard body works. > > > > http://en.wikipedia.org/wiki/3GPP > > > > Here is a news about standard-essential patents: ITU to address surge in litigation over standards-essential patents: > > > > http://www.computerworld.com/article/2505517/technology-law-regulation/itu--to-address-surge-in-litigation-over-standards-essential-patents.html > > > > Another related news about standards patents: Nokia, HP, Verizon back FTC against import bans over standards patents: > > > > http://www.computerworld.com/article/2504127/technology-law-regulation/nokia--hp--verizon-back-ftc-against-import-bans-over-standards-patents.html > > > > Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions. > > > > Weng > > -dan 1. > That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. Agree. 2. > If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. Agree. 3. > In which case, the Chair will tell the whole group to not use that information in the standardization process. Don't agree. You may ask current VHDL committee Chairman Jim Lewis what the by-law of VHDL is in the situation. He is closely watching the development of the issue now. I remember he had recently mentioned in this group to organize a working group in VHDL to develop some patents for the VHDL committee. 4. > I think this is how it goes for most standard bodies. Don't agree. Without patented inventions there would be no all G2, G3, G4 and G5 standards in cellphone and internet industries. Weng > > -dan From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: alb Newsgroups: comp.lang.vhdl Subject: Safe FSM Date: Sun, 29 Mar 2015 22:12:27 +0200 (CEST) Organization: news.individual.net Lines: 34 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Trace: individual.net yc6X4nf4KvV83ud1NTWqqQBDgfEXNf54nfPSbsvXNqubah7Txs Cancel-Lock: sha1:8AD9wb41AlOz1QFuqIgKjdxGLVE= X-Newsreader: PiaoHong.Usenet.Client.Free:1.65 Xref: mx02.eternal-september.org comp.lang.vhdl:8183 Hi everyone, I have an FSM of some (sigh) 150 states and Synplify Pro (from the Libero suite) is not able to recognize it as an FSM since it accepts 128 states max. The code simulates and works well on the target, but we are all aware that the implementation is not protected against non described states. Since we cannot rely on the tool capability to implement a safe FSM, I thought the easier way to implement a safe FSM would be to declare 2^n states explicitly and force the tool to preserve all states that are not reachable by design but could be triggered by an external event (say some heavy ion). Another possibility would be to encode a one hot FSM and monitor the state vector with another process responsible for checking any violation of the one hot coding. Are those reasonable paths? I'm excluding the possibility to split the FSM in hierarchical FSM since it will be a lot of work and raise more questions. Oh by the way, why the heck synthesis tools decide to neglect the "when others" closer unless I specify the safe FSM option? Couldn't they simplify follow the hdl description. Any suggestion/comment is appreciated. Al ----Android NewsGroup Reader---- http://usenet.sinaapp.com/ From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Sun, 29 Mar 2015 22:23:45 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: there is a problem with if statement please help me References: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> In-Reply-To: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150329-1, 29/03/2015), Outbound message X-Antivirus-Status: Clean Lines: 15 Message-ID: <55185f4f$0$3058$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Mar 2015 22:23:43 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1427660623 news-3.free.fr 3058 88.185.146.198:1302 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8184 Le 29/03/2015 10:42, rama hareesh a écrit : > here my code is > i am doing lift control based on spartan 3e for my 4th year student > here there a problem with if condition > here my problem will present if srx='1' Ok, can you now describe the actual problem ? Nicolas --- L'absence de virus dans ce courrier électronique a été vérifiée par le logiciel antivirus Avast. http://www.avast.com From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Sun, 29 Mar 2015 16:29:47 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 29 Mar 2015 20:28:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8818"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182lSaJHGMdtYo1JsRGHvgI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:E+cHwB9SNW7YdjsFya7pheTK93Y= Xref: mx02.eternal-september.org comp.lang.vhdl:8185 On 3/29/2015 4:12 PM, alb wrote: > > Hi everyone, > > I have an FSM of some (sigh) 150 states and Synplify Pro (from > the Libero suite) is not able to recognize it as an FSM since it > accepts 128 states max. The code simulates and works well on the > target, but we are all aware that the implementation is not > protected against non described states. > > Since we cannot rely on the tool capability to implement a safe FSM, > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). > > Another possibility would be to encode a one hot FSM and monitor > the state vector with another process responsible for checking > any violation of the one hot coding. > > Are those reasonable paths? I'm excluding the possibility to split > the FSM in hierarchical FSM since it will be a lot of work and > raise more questions. > > Oh by the way, why the heck synthesis tools decide to neglect the > "when others" closer unless I specify the safe FSM option? > Couldn't they simplify follow the hdl description. > > > Any suggestion/comment is appreciated. Perhaps you can explain what you mean by a "safe" FSM? I have never heard this term. You might consider redesigning your machine as several smaller machines. Then the tool will recognize each of them since they will have less than 128 states. -- Rick From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.1.199 with SMTP id 7mr36924519obo.49.1427662423624; Sun, 29 Mar 2015 13:53:43 -0700 (PDT) X-Received: by 10.182.148.35 with SMTP id tp3mr257522obb.16.1427662423565; Sun, 29 Mar 2015 13:53:43 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no987774igd.0!news-out.google.com!q14ni2673ign.0!nntp.google.com!h15no587678igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 13:53:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Andy Injection-Date: Sun, 29 Mar 2015 20:53:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8186 You can use a syn_preserve attribute on the state register signal to disabl= e fsm compiler and other optimizations (such as due to reachability analysi= s). Then a "when others" choice can assign a legal state value if none of t= he other choices (presumably all the legal states) match. Without syn_prese= rve, the when others choice is usually ignored unless you actually assign a= value (including upon reset) that is not covered by an explicit when choic= e. Note that this does not detect an illegal transition to a legal state (such= as due to an SEU or an improperly synchronized input). Detecting all possible illegal states for a one-hot FSM is expensive. Howev= er, a simple parity check will detect single bit errors in one-hot FSMs (on= e-hot by definition is odd parity). I would also seriously consider breaking up a state machine with that many = states... Andy From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.1.199 with SMTP id 7mr37219821obo.49.1427666899760; Sun, 29 Mar 2015 15:08:19 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr133665igb.1.1427666899741; Sun, 29 Mar 2015 15:08:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no1016860igd.0!news-out.google.com!q14ni2725ign.0!nntp.google.com!h15no1016854igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 29 Mar 2015 15:08:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.43.4.223; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.43.4.223 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Jim Lewis Injection-Date: Sun, 29 Mar 2015 22:08:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8187 Hi Al, I think the most reasonable answer is the one proposed by @rickman, partiti= on the statemachine into multiple statemachines, each with < 128 states.=20 > Since we cannot rely on the tool capability to implement a safe FSM,=20 > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). If you want a safe FSM, then you need hamming distance between the states. = Hence you will need at least 2^(n+1). Code your states as constants that = have a hamming distance and use syn_preserve to keep redundancy from being = removed. Use the when others condition to detect illegal transitions or if= you use a hamming distance of at least 2, you can add the error recovery i= nto the code. =20 This is going to get real tedious and be interesting to debug if you run in= to issues. You will need to simulate your error recovery to prove you did = it right. You will probably be wishing you had enumerated states just for = debug - you could create them and create a mapping between them and the con= stant values just to assist with debug. All of this is alot of work. I would expect the better answer to be to spr= ing for the pay version of the tool. Yes expensive, but it may give you so= me additional options the free tool does not have - like a hamming distance= between states rather than one-hot. I agree with Andy that it is going to= be expensive to do recovery with a one-hot safe statemachine.=20 > Another possibility would be to encode a one hot FSM and monitor > the state vector with another process responsible for checking > any violation of the one hot coding.=20 My recommendation is don't. I have yet to see someone's one-hot VHDL state= machine code actually be a true one-hot statemachine. The problem is that = if you use a case statement to decode your states, most synthesis tools wil= l decode all bits rather than the one bit that determines the state, and he= nce, the state decoding is huge. The start of getting a synthesis tool to = get it right is to assign all outputs to a default value and use an if-end = if structure that only decodes a single bit in the state vector and only as= signs outputs to the opposite value of the default value. The only vector = value allowed in the structure is next state (or current state if you use a= single process statemachine). Next state needs to be defaulted to all zer= os and a state update may only assign a single bit to a '1'. =20 The code gets complicated, ugly, and unreadable by most, hence, my recommen= dation, if you need one-hot, you need the tool to understand your statemach= ine as a statemachine and for it to implement it as a one-hot statemachine. > Oh by the way, why the heck synthesis tools decide to neglect the > "when others" closer unless I specify the safe FSM option? > Couldn't they simplify follow the hdl description. Commercial needs the speed, so those who need the safe option have to work = harder to make it happen. A cruel, but fair balance to the problem. Jim From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:01:23 GMT Lines: 26 Message-ID: References: X-Trace: individual.net VAahCsJtN3Enf4fbjBTegQJsRNniKjoT7ZhvEnIe9XkZdZEA+Y X-Orig-Path: not-for-mail Cancel-Lock: sha1:f6tM25Oy4GufdgzeUh6p0j97tEc= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8188 hi Rick, rickman wrote: [] > Perhaps you can explain what you mean by a "safe" FSM? I have never > heard this term. a safe FSM is an FSM that does not get stuck in an undefined state. > You might consider redesigning your machine as several smaller machines. > Then the tool will recognize each of them since they will have less > than 128 states. Even if I understand this is the best approach, we are talking about a 4.5 KLOC code that took three months to develop and many more to verify and validate on the hardware. I'm not sure I'd want to embark on such a nightmare. The problem is not in coding, is in the architecture of the FSM itself. At the architecture review somebody should have coughed a little harder when looking at the number of states and raise a hand before designers started hammering the code. Now I'm trying to get out of the dirt with the minimum amount of impact. Al From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:15:18 GMT Lines: 51 Message-ID: References: X-Trace: individual.net VHDmGK90d0WBfaxeSHlG3AEcXmiq5cpbY7K8gn136H+pfeLoWV X-Orig-Path: not-for-mail Cancel-Lock: sha1:Ssd1CcqxIf/YAp7+2ZU6wTTACAQ= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8189 Hi Andy, Andy wrote: > You can use a syn_preserve attribute on the state register signal to > disable fsm compiler and other optimizations (such as due to > reachability analysis). Then a "when others" choice can assign a legal > state value if none of the other choices (presumably all the legal > states) match. Without syn_preserve, the when others choice is usually > ignored unless you actually assign a value (including upon reset) that > is not covered by an explicit when choice. I'm not sure it is even needed the syn_preserve, since the tool does not recognize the FSM at all (they admitedly reported the tool has a 128 bit limit for FSM state vector). Considering the 'when others' is not wiped out by their FSM compiler, maybe we are better off than thought. > Note that this does not detect an illegal transition to a legal state > (such as due to an SEU or an improperly synchronized input). That is correct, that's why I'd feel more confortable if states were decoded with a hamming distance greater than 1. We are talking about an implementation that is already 'TMRed', so chances of a double failure causing a transition to a legal state might be very small. Nevertheless SET on combinatorial logic that is not TMRed might give you troubles. The transient may be just enough to have the triplified register to get the wrong value on a perfect triple copy! > Detecting all possible illegal states for a one-hot FSM is expensive. > However, a simple parity check will detect single bit errors in > one-hot FSMs (one-hot by definition is odd parity). This is what I thought. One-hot and odd parity check (no need to verify overflow for cases like '...010101...' since they are too rare to be a real concern). > I would also seriously consider breaking up a state machine with that > many states... As mentioed in a different post in this thread, there's no simple breaking. We would need to get the architecture and shake it a bit before being able to split the number of states in several FSMs. On top of it there's a lot of verification that needs to be re-run as well, also on the real hardware (since long sequences were not verified in simulation). But as you said, maybe splitting, in the end, would be simpler that any other supposedly 'cheaper' alternative. From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: 30 Mar 2015 07:51:05 GMT Lines: 118 Message-ID: References: X-Trace: individual.net uXD1U806/giEZ3LTfffoJg72Gc1fkbzTacA9X7xYdFoNZUAIAZ X-Orig-Path: not-for-mail Cancel-Lock: sha1:MJL4dAumpaDe9UcK4SCcKRf8kLk= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8190 Hi Jim, Jim Lewis wrote: [] > I think the most reasonable answer is the one proposed by @rickman, > partition the statemachine into multiple statemachines, each with < > 128 states. I'm kinda repeating to myself that as well, but I keep having everyone against since it is too 'expensive'. > >> Since we cannot rely on the tool capability to implement a safe FSM, >> I thought the easier way to implement a safe FSM would be to >> declare 2^n states explicitly and force the tool to preserve all >> states that are not reachable by design but could be triggered by an >> external event (say some heavy ion). > If you want a safe FSM, then you need hamming distance between the > states. Hence you will need at least 2^(n+1). Code your states as > constants that have a hamming distance and use syn_preserve to keep > redundancy from being removed. Use the when others condition to > detect illegal transitions or if you use a hamming distance of at > least 2, you can add the error recovery into the code. I haven't understood the 'add the error recovery into the code'. I would have done something like this: process(clk, rst) begin if rst = '1' then -- reset all output signals and state vector here elseif rising_edge(clk) then -- define all legal states here case state is when "ABC" => -- set output here -- set next state here when "DEF" => -- set output here -- set next state here when others => -- set output here -- set safe state here end case; end if; end process; the only place where I can recover from an illegal state would be in the 'when others' branch. > This is going to get real tedious and be interesting to debug if you > run into issues. You will need to simulate your error recovery to > prove you did it right. You will probably be wishing you had > enumerated states just for debug - you could create them and create a > mapping between them and the constant values just to assist with > debug. We normally force the state vector to show what it'll do in the event of an illegal state, this is standard practice, but not in post-synth sims. We do analyze the synthesis report to verify that implementation is correct. Seldom we do analyze the netlist as well. But very rarely we perform post-synth sims. > All of this is alot of work. I would expect the better answer to be > to spring for the pay version of the tool. Yes expensive, but it may > give you some additional options the free tool does not have - like a > hamming distance between states rather than one-hot. I agree with > Andy that it is going to be expensive to do recovery with a one-hot > safe statemachine. unfortunately the tool is the main issue here. Synplify Pro, no matter if paid or not, does not recognize more than 128 bit FSMs (if I understood it correctly). So we cannot really count on it. > >> Another possibility would be to encode a one hot FSM and monitor >> the state vector with another process responsible for checking any >> violation of the one hot coding. > My recommendation is don't. I have yet to see someone's one-hot VHDL > statemachine code actually be a true one-hot statemachine. The > problem is that if you use a case statement to decode your states, > most synthesis tools will decode all bits rather than the one bit that > determines the state, and hence, the state decoding is huge. The > start of getting a synthesis tool to get it right is to assign all > outputs to a default value and use an if-end if structure that only > decodes a single bit in the state vector and only assigns outputs to > the opposite value of the default value. The only vector value > allowed in the structure is next state (or current state if you use a > single process statemachine). Next state needs to be defaulted to all > zeros and a state update may only assign a single bit to a '1'. I see your point. It is possible that we have always used one-hot encoding ending with an enormous amount of resources because of the decoding logic. > The code gets complicated, ugly, and unreadable by most, hence, my > recommendation, if you need one-hot, you need the tool to understand > your statemachine as a statemachine and for it to implement it as a > one-hot statemachine. One-hot is not mandatory, a hamming distance of, say, 2 would be sufficient. >> Oh by the way, why the heck synthesis tools decide to neglect the >> "when others" closer unless I specify the safe FSM option? Couldn't >> they simplify follow the hdl description. > Commercial needs the speed, so those who need the safe option have to > work harder to make it happen. A cruel, but fair balance to the > problem. fair enough...we do it 'not because is easy, but because is hard'! Al From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 03:53:38 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 30 Mar 2015 07:52:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7904"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/cMeWpKqA6v9q9ke0Cr8L4" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:GUM502hOjV2jct0kmKL7b0qHNSQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8191 On 3/30/2015 3:01 AM, alb wrote: > hi Rick, > > rickman wrote: > [] >> Perhaps you can explain what you mean by a "safe" FSM? I have never >> heard this term. > > a safe FSM is an FSM that does not get stuck in an undefined state. > >> You might consider redesigning your machine as several smaller machines. >> Then the tool will recognize each of them since they will have less >> than 128 states. > > Even if I understand this is the best approach, we are talking about a > 4.5 KLOC code that took three months to develop and many more to verify > and validate on the hardware. I'm not sure I'd want to embark on such a > nightmare. > > The problem is not in coding, is in the architecture of the FSM itself. > At the architecture review somebody should have coughed a little harder > when looking at the number of states and raise a hand before designers > started hammering the code. That's what splitting it into multiple FSMs would be, an architecture change. > Now I'm trying to get out of the dirt with the minimum amount of impact. If you just need to have the FSM handle the remaining 2^N-M states why not specify them explicitly? I assume you identify a start state and all the undefined states transition unconditionally to that start state. That can be coded in the "otherwise" clause of a case statement very easily. Or if you aren't using a case statement you can just surround the existing state code with an IF (all the undefined states) go to reset ELSE normal operation ENDIF -- Rick From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.66.155.9 with SMTP id vs9mr37884146pab.20.1427705027119; Mon, 30 Mar 2015 01:43:47 -0700 (PDT) X-Received: by 10.140.109.246 with SMTP id l109mr461177qgf.22.1427705027022; Mon, 30 Mar 2015 01:43:47 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no1317135igd.0!news-out.google.com!q90ni547qgd.1!nntp.google.com!q107no526451qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 01:43:46 -0700 (PDT) In-Reply-To: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.246.134.120; posting-account=mTyLDAoAAADxHZdldD2Jxn0-cKtA0oys NNTP-Posting-Host: 213.246.134.120 References: <145ebc0b-b40a-4a28-8964-74d05f218549@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a7b8bf7-35c2-4748-9a04-5f67c49573e4@googlegroups.com> Subject: Re: there is a problem with if statement please help me From: "colin_toogood@yahoo.com" Injection-Date: Mon, 30 Mar 2015 08:43:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: mx02.eternal-september.org comp.lang.vhdl:8192 A couple of simple things to begin with. 1) You say this code is going in a spartan 3e. THE VERY FIRST THING THAT YOU HAVE TO DO IS UNDERSTAND WHAT AN FPGA IS. Then you will understand that there is no "after 5ns" magic. If you have tried to synthesize yet you will find a "I have ignored this" message in the log files. 2) You have to understand what a process is. Then you will replace your process line with "process(clk)", unless you have cut some asynchronous stuff but I doubt it. Colin From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.97.2 with SMTP id dw2mr38414112obb.0.1427707117864; Mon, 30 Mar 2015 02:18:37 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr159016igq.15.1427707117838; Mon, 30 Mar 2015 02:18:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no816943igd.0!news-out.google.com!q14ni3136ign.0!nntp.google.com!h15no816940igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 02:18:37 -0700 (PDT) In-Reply-To: <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 30 Mar 2015 09:18:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8193 On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote: > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > >=20 > > Why currently VHDL committee has so many difficulties financially to ge= t industries into its activities? One most important reason is that VHDL is= now free to use for all related companies and they don't have to make thei= r contributions. > >=20 >=20 > That's the reason why standard bodies have by-laws that make sure any inf= ormation submitted or discussed within working groups are not encumbered by= patents. If you are trying to discuss your patent idea within a working gr= oup, you need to declare that the information has been patented. In which c= ase, the Chair will tell the whole group to not use that information in the= standardization process. I think this is how it goes for most standard bod= ies. >=20 See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page 4: * The DASC will only accept patented material under paragraph (a) of IEEE Patent Policy Where paragraph (a) is found on PDF Page 2 (Slide #1): a) A general disclaimer to the effect that the patentee will not enforc= e any of its present or future patent(s) whose use would be required t= o=20 implement either mandatory or optional potions of the proposed IEEE standard against any person or entity complying with the standard; o= r=20 The VASG P1076 effort falls under these conditions, no one is going to get = rich on a standard essential patent required to implement the VHDL standard= (nor either Verilog standards also under the auspices of DASC). Also note Page 3 (slide #2): Inappropriate Topics for IEEE WG Meetings * Don't discuss licensing terms or conditions ... From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.70.94.102 with SMTP id db6mr37105170pdb.0.1427709220194; Mon, 30 Mar 2015 02:53:40 -0700 (PDT) X-Received: by 10.50.60.71 with SMTP id f7mr163192igr.10.1427709220148; Mon, 30 Mar 2015 02:53:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!h15no1377774igd.0!news-out.google.com!db6ni1996igc.0!nntp.google.com!h15no1377773igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 02:53:39 -0700 (PDT) In-Reply-To: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=203.125.115.98; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D NNTP-Posting-Host: 203.125.115.98 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Daniel Kho Injection-Date: Mon, 30 Mar 2015 09:53:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8194 On Monday, 30 March 2015 17:18:41 UTC+8, diog...@gmail.com wrote: > The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC). There goes... thanks Dio! From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.66.197.170 with SMTP id iv10mr35113137pac.25.1427720707102; Mon, 30 Mar 2015 06:05:07 -0700 (PDT) X-Received: by 10.140.104.34 with SMTP id z31mr454697qge.11.1427720706983; Mon, 30 Mar 2015 06:05:06 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.216.MISMATCH!h15no1535109igd.0!news-out.google.com!q90ni548qgd.1!nntp.google.com!z60no621757qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 06:05:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f507:e136:acf0:5ff7; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f507:e136:acf0:5ff7 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> Subject: Re: Safe FSM From: KJ Injection-Date: Mon, 30 Mar 2015 13:05:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8195 On Sunday, March 29, 2015 at 6:08:23 PM UTC-4, Jim Lewis wrote: > My recommendation is don't. I have yet to see someone's one-hot VHDL=20 > statemachine code actually be a true one-hot statemachine. The problem i= s=20 > that if you use a case statement to decode your states, most synthesis to= ols=20 > will decode all bits rather than the one bit that determines the state, a= nd=20 > hence, the state decoding is huge. The start of getting a synthesis tool= to=20 > get it right is to ... Do you have an example of this? I just looked at a recent design and what = I see is different number of fanout for the various state bit signals in th= e fitter report which indicates to me that the logic is using only those st= ate bits that it needs. The report doesn't blast out all of the logic equa= tions to validate the final usage but it would seem that if what you say wa= s true, then the fanout for each state bit would at least have to be the sa= me. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.236.29.146 with SMTP id i18mr17059599yha.58.1427723229499; Mon, 30 Mar 2015 06:47:09 -0700 (PDT) X-Received: by 10.140.21.145 with SMTP id 17mr472705qgl.1.1427723229481; Mon, 30 Mar 2015 06:47:09 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no631412qgd.0!news-out.google.com!q90ni547qgd.1!nntp.google.com!q107no631306qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 06:47:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Mon, 30 Mar 2015 13:47:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1741 X-Received-Body-CRC: 157679516 Xref: mx02.eternal-september.org comp.lang.vhdl:8196 Am Sonntag, 29. M=E4rz 2015 22:12:32 UTC+2 schrieb alb: > Since we cannot rely on the tool capability to implement a safe FSM,=20 > I thought the easier way to implement a safe FSM would be to > declare 2^n states explicitly and force the tool to preserve all > states that are not reachable by design but could be triggered by > an external event (say some heavy ion). The easiest way to ensure Synplify keeps all defined states is using 2^n st= ates and cycle at least once (after reset) through all "unused" states. In all other cases you might end up with a result different from your inten= tion. bye Thomas From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.236.32.238 with SMTP id o74mr39129460yha.2.1427728884485; Mon, 30 Mar 2015 08:21:24 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr196333igq.15.1427728884460; Mon, 30 Mar 2015 08:21:24 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no654447qgd.1!news-out.google.com!db6ni2220igc.0!nntp.google.com!h15no1616468igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 08:21:23 -0700 (PDT) In-Reply-To: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <71a7cb6e-6359-4458-89fd-7aca707608d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: KJ Injection-Date: Mon, 30 Mar 2015 15:21:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2627 X-Received-Body-CRC: 618823529 Xref: mx02.eternal-september.org comp.lang.vhdl:8197 On Monday, March 30, 2015 at 9:05:12 AM UTC-4, KJ wrote: > On Sunday, March 29, 2015 at 6:08:23 PM UTC-4, Jim Lewis wrote: > > My recommendation is don't. I have yet to see someone's one-hot VHDL= =20 > > statemachine code actually be a true one-hot statemachine. The problem= is=20 > > that if you use a case statement to decode your states, most synthesis = tools=20 > > will decode all bits rather than the one bit that determines the state,= and=20 > > hence, the state decoding is huge. The start of getting a synthesis to= ol to=20 > > get it right is to ... >=20 > Do you have an example of this? I just looked at a recent design and wha= t I see is different number of fanout for the various state bit signals in = the fitter report which indicates to me that the logic is using only those = state bits that it needs. The report doesn't blast out all of the logic eq= uations to validate the final usage but it would seem that if what you say = was true, then the fanout for each state bit would at least have to be the = same. >=20 > Kevin Jennings Or did you perhaps mean to say "yet to see someone's one-hot VHDL SAFE stat= emachine code actually be a true one-hot statemachine". If you did mean to= only refer to 'safe' state machines with your comment, then decode of all = of the bits would likely be part of the implementation of 'safe'. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.236.11.46 with SMTP id 34mr15778168yhw.22.1427740620331; Mon, 30 Mar 2015 11:37:00 -0700 (PDT) X-Received: by 10.50.119.131 with SMTP id ku3mr223602igb.2.1427740620254; Mon, 30 Mar 2015 11:37:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no712252qgd.0!news-out.google.com!db6ni2347igc.0!nntp.google.com!h15no1784562igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Mar 2015 11:36:59 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=103.255.147.121; posting-account=FbGAbQoAAADo4S2QpylKfP0Gt2DSb2ry NNTP-Posting-Host: 103.255.147.121 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <18c75c96-3d39-4b65-a3bb-58fad0eca63f@googlegroups.com> Subject: Need: Data Architect in Marlborough, MA From: latha.karnti@gmail.com Injection-Date: Mon, 30 Mar 2015 18:37:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1433 X-Received-Body-CRC: 1438712562 Xref: mx02.eternal-september.org comp.lang.vhdl:8198 HI, Please go through below the requirement if you're comfortable please forward his/her resume along with contact number & email-id to panand@sageitinc.net Position: Data Architect Location: Marlborough, MA Duration: 6+ Months Data Governance, Meta data Work Bench, Business Glossary, Pl/Sql, Good analytical and communication skills.. Thanks & Regards, Anand Executive-Talent Acquisition Direct: 972-996-0650 Ext: 339 panand@sageitinc.net From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 18:03:16 -0400 Organization: A noiseless patient Spider Lines: 135 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 30 Mar 2015 22:02:25 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9022"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19mOKF+YOhb68OjT5ZpTyCF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:kAkGx1ki7rv9tGSzLSTEqokS8EY= Xref: mx02.eternal-september.org comp.lang.vhdl:8199 On 3/30/2015 3:51 AM, alb wrote: > Hi Jim, > > Jim Lewis wrote: > [] >> I think the most reasonable answer is the one proposed by @rickman, >> partition the statemachine into multiple statemachines, each with < >> 128 states. > > I'm kinda repeating to myself that as well, but I keep having everyone > against since it is too 'expensive'. > >> >>> Since we cannot rely on the tool capability to implement a safe FSM, >>> I thought the easier way to implement a safe FSM would be to >>> declare 2^n states explicitly and force the tool to preserve all >>> states that are not reachable by design but could be triggered by an >>> external event (say some heavy ion). > >> If you want a safe FSM, then you need hamming distance between the >> states. Hence you will need at least 2^(n+1). Code your states as >> constants that have a hamming distance and use syn_preserve to keep >> redundancy from being removed. Use the when others condition to >> detect illegal transitions or if you use a hamming distance of at >> least 2, you can add the error recovery into the code. > > I haven't understood the 'add the error recovery into the code'. I would > have done something like this: > > > process(clk, rst) > begin > if rst = '1' then > -- reset all output signals and state vector here > elseif rising_edge(clk) then > -- define all legal states here > case state is > when "ABC" => > -- set output here > -- set next state here > when "DEF" => > -- set output here > -- set next state here > when others => > -- set output here > -- set safe state here > end case; > end if; > end process; > > > the only place where I can recover from an illegal state would be in the > 'when others' branch. Not sure what you mean by this. Why do you care if it is the "only" place in the code? This one phrase covers *all* possible states not previously described as valid states. If there are some error states you want to recover from differently then they can be broken out as their own clauses in the case. >> This is going to get real tedious and be interesting to debug if you >> run into issues. You will need to simulate your error recovery to >> prove you did it right. You will probably be wishing you had >> enumerated states just for debug - you could create them and create a >> mapping between them and the constant values just to assist with >> debug. > > We normally force the state vector to show what it'll do in the event of > an illegal state, this is standard practice, but not in post-synth sims. > We do analyze the synthesis report to verify that implementation is > correct. Seldom we do analyze the netlist as well. But very rarely we > perform post-synth sims. > >> All of this is alot of work. I would expect the better answer to be >> to spring for the pay version of the tool. Yes expensive, but it may >> give you some additional options the free tool does not have - like a >> hamming distance between states rather than one-hot. I agree with >> Andy that it is going to be expensive to do recovery with a one-hot >> safe statemachine. > > unfortunately the tool is the main issue here. Synplify Pro, no matter > if paid or not, does not recognize more than 128 bit FSMs (if I > understood it correctly). So we cannot really count on it. > >> >>> Another possibility would be to encode a one hot FSM and monitor >>> the state vector with another process responsible for checking any >>> violation of the one hot coding. > >> My recommendation is don't. I have yet to see someone's one-hot VHDL >> statemachine code actually be a true one-hot statemachine. The >> problem is that if you use a case statement to decode your states, >> most synthesis tools will decode all bits rather than the one bit that >> determines the state, and hence, the state decoding is huge. The >> start of getting a synthesis tool to get it right is to assign all >> outputs to a default value and use an if-end if structure that only >> decodes a single bit in the state vector and only assigns outputs to >> the opposite value of the default value. The only vector value >> allowed in the structure is next state (or current state if you use a >> single process statemachine). Next state needs to be defaulted to all >> zeros and a state update may only assign a single bit to a '1'. > > I see your point. It is possible that we have always used one-hot > encoding ending with an enormous amount of resources because of the > decoding logic. One hot should provide very simple decode other than the error state. The error state could be detected simply by adding all the bits in a simplified adder which knows three states, 0, 1 and "more than one". Only the 1 output is not an error. I doubt the tool is smart enough to synthesize this though. It is something you can add separate from the case statement. >> The code gets complicated, ugly, and unreadable by most, hence, my >> recommendation, if you need one-hot, you need the tool to understand >> your statemachine as a statemachine and for it to implement it as a >> one-hot statemachine. > > One-hot is not mandatory, a hamming distance of, say, 2 would be > sufficient. I see the conversation has added this "Hamming" distance to the requirements. If you need a Hamming distance of 2 between valid states one-hot encoding gives you that automatically. If you need more than 2 one-hot is not possible. I don't know if the tools automatically give you a Hamming distance of 2 even if they recognize your design as a FSM, but it is easy enough to do by specifying the state values. -- Rick From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Mon, 30 Mar 2015 21:51:51 -0400 Organization: A noiseless patient Spider Lines: 62 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Mar 2015 01:51:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="6746"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wf7OF4PYW9M+JQfUtnwLL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Cancel-Lock: sha1:+RE9AowsiU18eoGNrhTDx/ApQrE= Xref: mx02.eternal-september.org comp.lang.vhdl:8200 On 3/30/2015 9:47 AM, Thomas Stanka wrote: > Am Sonntag, 29. März 2015 22:12:32 UTC+2 schrieb alb: >> Since we cannot rely on the tool capability to implement a safe FSM, >> I thought the easier way to implement a safe FSM would be to >> declare 2^n states explicitly and force the tool to preserve all >> states that are not reachable by design but could be triggered by >> an external event (say some heavy ion). > > The easiest way to ensure Synplify keeps all defined states is using 2^n states and cycle at least once (after reset) through all "unused" states. > > In all other cases you might end up with a result different from your intention. I'm not clear on what it means to "preserve" states...? The states are there, legal or illegal. You can't get rid of them. Are you saying the tool can remap the values of the state variable to mean something other than what you intend? If you want the efficiency of one-hot encoding you don't have to use a case statement. Instead of designing it as one state machine of N states and a state variable of N bits, consider each bit to be an independent state machine with entry and exit conditions. These conditions can be put in functions so that they are reused between the exit condition of one state and the entry condition of another. They can all still be described in the same process (quite hairy in the case of the OP's huge FSM). Here is an example... FSM : process (Clk, Rst) begin if ('1' = Rst) then StateA <= '1'; StateB <= '0'; StateC <= '0'; StateD <= '0'; . . . StateZ <= '0'; elsif (rising_edge(Clk)) then if ('0' = StateA) then StateA <= -- insert your state entry conditions here; else StateA <= not -- insert your state exit conditions here end if; -- (if StateA) if ('0' = StateB) then StateB <= -- insert your state entry conditions here; else StateB <= not -- insert your state exit conditions here end if; -- (if StateB) . . . end if; -- (if Rst) end process FSM; It is still the same FSM, but coded to minimize the decoding logic without any issues of what the tool will do. -- Rick From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.47.137 with SMTP id d9mr44763627obn.5.1427790630698; Tue, 31 Mar 2015 01:30:30 -0700 (PDT) X-Received: by 10.140.89.116 with SMTP id u107mr544071qgd.18.1427790630654; Tue, 31 Mar 2015 01:30:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2221718igd.0!news-out.google.com!f74ni1qge.0!nntp.google.com!q107no813812qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 01:30:30 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Tue, 31 Mar 2015 08:30:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8201 Am Dienstag, 31. M=E4rz 2015 03:51:55 UTC+2 schrieb rickman: > > The easiest way to ensure Synplify keeps all defined states is using 2^= n states and cycle at least once (after reset) through all "unused" states. > > > > In all other cases you might end up with a result different from your i= ntention. >=20 > I'm not clear on what it means to "preserve" states...? The states are= =20 > there, legal or illegal. You can't get rid of them. Are you saying the= =20 > tool can remap the values of the state variable to mean something other= =20 > than what you intend? Assume you have 10 user states and fill up to 16 by adding unused_state10-1= 5 than write "when others =3D> state <=3D idle;" This would logically ensure you recover from all states. On RTL simulation = you could even set the fsm by force command to unused state and see the FSM= recovers. But Synplify extracts during synthesise step, that you could not= reach the unused states and therefore starts optimising them in a way that= you might find later on a state from which your FSM cannot recover if it g= et stuck there. The same is valid if you use an counter from 0-9 "if counter < 10 then ... = else counter <=3D 0;". This statement can be optimised by Synplify to code = that might stuck, if your counter ever reaches value 14 due to SEE.=20 For One-Hot situation is even worse, if you consider states not reachable b= y normal operation, but you reach by accident (SEE, metastability,...), lik= e states with zero or two '1's. regards, Thomas From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.182.112.167 with SMTP id ir7mr46771694obb.29.1427815878487; Tue, 31 Mar 2015 08:31:18 -0700 (PDT) X-Received: by 10.50.40.9 with SMTP id t9mr72084igk.7.1427815878472; Tue, 31 Mar 2015 08:31:18 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no2521336igd.0!news-out.google.com!db6ni3162igc.0!nntp.google.com!h15no2521334igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 08:31:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Tue, 31 Mar 2015 15:31:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 66 Xref: mx02.eternal-september.org comp.lang.vhdl:8202 On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote: > On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > >=20 > > Here I publish all source code for public confirmation. > > >=20 > What exactly would you like the public to confirm? Do you have made some= specific claims? >=20 > Given that you have not claimed anything specific, I can only confirm the= following: > - It does compile (Modelsim 10.3c) > - It does synthesize to something (Quartus 14.0; Top level entity=3DCPC1;= 56 Max II logic elements) >=20 > >=20 > > You may copy this part of code to do simulation by yourself. > > >=20 > Why would I want to simulate it? >=20 > Kevin Jennings Here is how I claim to increase very-hard-implemented wave pipelined circui= ts to 100% successful rate. The pairing rules between a WPC and a CPC [0140] Here are the paring rules on how a WPC and a CPC are paired. * A series CPC can be linked with one of four WPC embodiments: o With a WPC series_module: Input data is acceptable on every clock cycl= e. If wave-pipelining requirements are not met, a designer has to either re= peat the attempt with more CPC code modification, change code manually to m= ake it linking with an input_delay_module or a multiple_copy_module, or qui= t the attempt otherwise. o With a WPC input_delay_module: Input data is acceptable on every one o= r more clock cycle and its successful rate is 100%. If the number of input = data clock cycles is large enough, there is at most only one wave of input = data propagating through the CPC on any clock cycle and there are no wave-p= ipelining requirements any more. o With a WPC multiple_copy_module: Input data is acceptable on every clo= ck cycle and its successful rate is 100%. The cost may be the input registe= rs and combinational logic copied multiple times if it is linked with a mul= tiple_copy_module2, or the output registers may also be copied same times i= f it is linked with a multiple_copy_module1. * A feedback CPC can be linked with one of three WPC embodiments: o With a WPC input_delay_module: Input data is acceptable on every feedb= ack or more clock cycles and its successful rate is 100%. If the number of = input data clock cycles is large enough, there is at most only one wave of = input data propagating through the CPC on any clock cycle, and there are no= wave-pipelining requirements any more. o With a WPC multiple_copy_module: Input data is acceptable on every clo= ck cycle and its successful rate is 100%. The cost may be the input registe= rs and combinational logic copied the number of feedback clock cycles or mo= re times if it is linked with a multiple_copy_module2, or the output regist= ers may also be copied same times if it is linked with a multiple_copy_modu= le1. [0141] A linked WPC input_delay_module or multiple_copy_module will dege= nerate to a WPC series_module if a synthesizer later finds that wave-pipeli= ning requirements are met with one copy of the linked CPC and input data ac= ceptable on every clock cycle, and there will be neither code change nor ex= tra logic generated. Weng From newsfish@newsfish Tue Dec 29 16:43:47 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 11:50:00 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 31 Mar 2015 15:49:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10935"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bzSAn3lGjn58btW21Vh0W" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:dptbhF0YSMEu7zye+ZlHQGdAt24= Xref: mx02.eternal-september.org comp.lang.vhdl:8203 On 3/31/2015 4:30 AM, Thomas Stanka wrote: > Am Dienstag, 31. März 2015 03:51:55 UTC+2 schrieb rickman: >>> The easiest way to ensure Synplify keeps all defined states is using 2^n states and cycle at least once (after reset) through all "unused" states. >>> >>> In all other cases you might end up with a result different from your intention. >> >> I'm not clear on what it means to "preserve" states...? The states are >> there, legal or illegal. You can't get rid of them. Are you saying the >> tool can remap the values of the state variable to mean something other >> than what you intend? > > Assume you have 10 user states and fill up to 16 by adding unused_state10-15 than write "when others => state <= idle;" > This would logically ensure you recover from all states. On RTL simulation you could even set the fsm by force command to unused state and see the FSM recovers. But Synplify extracts during synthesise step, that you could not reach the unused states and therefore starts optimising them in a way that you might find later on a state from which your FSM cannot recover if it get stuck there. > > The same is valid if you use an counter from 0-9 "if counter < 10 then ... else counter <= 0;". This statement can be optimised by Synplify to code that might stuck, if your counter ever reaches value 14 due to SEE. > > For One-Hot situation is even worse, if you consider states not reachable by normal operation, but you reach by accident (SEE, metastability,...), like states with zero or two '1's. I was not aware that the tools would perform that level of analysis. Where did you learn this? Is this from the vendor's optimization? I suspect the method of one-hot coding I have described would prevent such optimization since each state is an independent FSM, it would be much harder to analyze and determine the various "impossible" states based on the logical analysis. -- Rick From newsfish@newsfish Tue Dec 29 16:43:47 2015 X-Received: by 10.236.50.227 with SMTP id z63mr38996765yhb.4.1427821823733; Tue, 31 Mar 2015 10:10:23 -0700 (PDT) X-Received: by 10.50.79.131 with SMTP id j3mr90344igx.4.1427821823703; Tue, 31 Mar 2015 10:10:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed3a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no911704qgd.1!news-out.google.com!q14ni4346ign.0!nntp.google.com!h15no2604401igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 10:10:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: KJ Injection-Date: Tue, 31 Mar 2015 17:10:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 28 Xref: mx02.eternal-september.org comp.lang.vhdl:8204 On Tuesday, March 31, 2015 at 11:50:03 AM UTC-4, rickman wrote: >=20 > I suspect the method of one-hot coding I have described would prevent=20 > such optimization since each state is an independent FSM, it would be=20 > much harder to analyze and determine the various "impossible" states=20 > based on the logical analysis. >=20 One hot encoding is exactly the case one can generate a large number of 'im= possible states'. If you have a four state state machine, and it is implem= ented as one-hot, then you will have four flip flops. Those four flip flop= s can theoretically be in any of 16 states; four 'legit' and 12 'impossible= '. Optimized logic that uses the state bit(s) would only look at the individua= l bit to see if a particular state is active (since that is the primary rea= son for using a one-hot encoding in the first place) and would ignore the o= ther state bits. Those state bits can only be interpreted as 'independent = FSMs' if you ignore the possibility of actually getting into 'impossible st= ates', which given a stray energetic space particle hit could happen theref= ore it is not impossible. Bottom line is that one hot encoding definitely does not prevent any vendor= optimization of the issue being discussed. In fact, the vendor optimizati= on to use one-hot (if not explicitly told to not use), creates more potenti= als for this problem (witness a four state machine having 12 impossible sta= tes). Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 13:28:39 -0400 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 Mar 2015 17:27:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3733"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+beSLgkj+4Spikg+FGchzs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:azv9Tz/fhe+WdrhtyDNN89fOn4o= Xref: mx02.eternal-september.org comp.lang.vhdl:8205 On 3/31/2015 1:10 PM, KJ wrote: > On Tuesday, March 31, 2015 at 11:50:03 AM UTC-4, rickman wrote: >> >> I suspect the method of one-hot coding I have described would prevent >> such optimization since each state is an independent FSM, it would be >> much harder to analyze and determine the various "impossible" states >> based on the logical analysis. >> > > One hot encoding is exactly the case one can generate a large number of 'impossible states'. If you have a four state state machine, and it is implemented as one-hot, then you will have four flip flops. Those four flip flops can theoretically be in any of 16 states; four 'legit' and 12 'impossible'. > > Optimized logic that uses the state bit(s) would only look at the individual bit to see if a particular state is active (since that is the primary reason for using a one-hot encoding in the first place) and would ignore the other state bits. Those state bits can only be interpreted as 'independent FSMs' if you ignore the possibility of actually getting into 'impossible states', which given a stray energetic space particle hit could happen therefore it is not impossible. > > Bottom line is that one hot encoding definitely does not prevent any vendor optimization of the issue being discussed. In fact, the vendor optimization to use one-hot (if not explicitly told to not use), creates more potentials for this problem (witness a four state machine having 12 impossible states). I can't say I follow your reasoning. If the vendor's tools look across all logic for sequential logic that depends on other sequential logic and combines it into a FSM that can be optimized, then nearly every design would be treated as a single FSM. What makes this approach a group of separate FSMs which aren't optimized by the tools is that they are separate signals. How exactly do the tools decide what is a FSM and what is not? Of course I haven't tested this. But then I have never seen a tool perform optimization that throws out valid logic that has inputs and outputs. -- Rick From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.182.44.161 with SMTP id f1mr47848409obm.33.1427830280553; Tue, 31 Mar 2015 12:31:20 -0700 (PDT) X-Received: by 10.50.129.98 with SMTP id nv2mr110010igb.1.1427830280529; Tue, 31 Mar 2015 12:31:20 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.216.MISMATCH!h15no2730492igd.0!news-out.google.com!q14ni4436ign.0!nntp.google.com!h15no2730491igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 31 Mar 2015 12:31:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Subject: Re: Safe FSM From: KJ Injection-Date: Tue, 31 Mar 2015 19:31:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8206 On Tuesday, March 31, 2015 at 1:28:42 PM UTC-4, rickman wrote: >=20 > I can't say I follow your reasoning. If the vendor's tools look across= =20 > all logic for sequential logic that depends on other sequential logic=20 > and combines it into a FSM that can be optimized, then nearly every=20 > design would be treated as a single FSM. What makes this approach a=20 > group of separate FSMs which aren't optimized by the tools is that they= =20 > are separate signals. How exactly do the tools decide what is a FSM and= =20 > what is not? >=20 We could be talking different things since I didn't say anything about look= ing across all logic... For FSMs, I think we're talking about the followin= g type of coding: type t_My_States is (Idle, Do_Something, Do_Something_Important, Done); signal Current_State: t_My_States; ... case Current_State is when Idle=3D> ... when Do_Something =3D> ... when Do_Something_Important=3D> ... when Done =3D> ... end case; The synthesis tools don't have to look to far to see that 'Current_State' i= s a single signal. The tool can then choose to implement that single signa= l as one-hot in which case it will use four flip flops which, in theory, ha= ve 16 different combinations. Only 4 of the 16 are 'valid' in that they ar= e described by the code that was written. The other 12 are 'impossible', '= not valid' etc. that can only be reached by things such as an SEU, timing p= roblem, voltage problem and other things that 'should not happen'. Although the implementation of 'Current_State' is in four flops, those four= are not independent. The logic that gets synthesized takes advantage of t= he fact that it is choosing to implement Current_State as one-hot so any de= pendent logic will only have to look at one bit to decide if it is a partic= ular state or not. If some downstream logic depends on being in the 'Idle'= state than the boolean logic that actually gets implemented will depend on= 'Current_State.Idle' (a single bit), as opposed to using all four bits 'Cu= rrent_State[3..0]'. If you then take the above code and add 'when others=3D> Current_State <=3D= Idle' to the case statement as a method to cover those 'impossible' states= , synthesis tools will generally ignore it because I have already covered a= ll of the possible cases in an earlier 'when ...'.=20 > Of course I haven't tested this. But then I have never seen a tool=20 > perform optimization that throws out valid logic that has inputs and=20 > outputs. >=20 I don't know what you're talking about here. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Tue, 31 Mar 2015 18:40:24 -0400 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 31 Mar 2015 22:39:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22838"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/GMlvnaj7BQkQ/hBqKLCSA" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Cancel-Lock: sha1:0p5ufA2/3X3coxDSjKdP6rmr9T8= Xref: mx02.eternal-september.org comp.lang.vhdl:8207 On 3/31/2015 3:31 PM, KJ wrote: > On Tuesday, March 31, 2015 at 1:28:42 PM UTC-4, rickman wrote: >> >> I can't say I follow your reasoning. If the vendor's tools look across >> all logic for sequential logic that depends on other sequential logic >> and combines it into a FSM that can be optimized, then nearly every >> design would be treated as a single FSM. What makes this approach a >> group of separate FSMs which aren't optimized by the tools is that they >> are separate signals. How exactly do the tools decide what is a FSM and >> what is not? >> > > We could be talking different things since I didn't say anything about looking across all logic... For FSMs, I think we're talking about the following type of coding: > > type t_My_States is (Idle, Do_Something, Do_Something_Important, Done); > signal Current_State: t_My_States; > .... > case Current_State is > when Idle=> ... > when Do_Something => ... > when Do_Something_Important=> ... > when Done => ... > end case; > > The synthesis tools don't have to look to far to see that 'Current_State' is a single signal. The tool can then choose to implement that single signal as one-hot in which case it will use four flip flops which, in theory, have 16 different combinations. Only 4 of the 16 are 'valid' in that they are described by the code that was written. The other 12 are 'impossible', 'not valid' etc. that can only be reached by things such as an SEU, timing problem, voltage problem and other things that 'should not happen'. > > Although the implementation of 'Current_State' is in four flops, those four are not independent. The logic that gets synthesized takes advantage of the fact that it is choosing to implement Current_State as one-hot so any dependent logic will only have to look at one bit to decide if it is a particular state or not. If some downstream logic depends on being in the 'Idle' state than the boolean logic that actually gets implemented will depend on 'Current_State.Idle' (a single bit), as opposed to using all four bits 'Current_State[3..0]'. > > If you then take the above code and add 'when others=> Current_State <= Idle' to the case statement as a method to cover those 'impossible' states, synthesis tools will generally ignore it because I have already covered all of the possible cases in an earlier 'when ...'. This is exactly my point. Don't code like this. Code the one hot states independently and the tool won't be able to see it as one large FSM. Instead each state will appear as a separate FSM with nothing to be optimized out. Error detection will consist of adding the state bits and if the count is not exactly one, go to a safe state, a signal that sets all the separate state bits to the appropriate value. I supplied code for this earlier, but here is a version I like better based on the transition specification rather than the present state value. FSM : process (Clk, Rst) begin if ('1' = Rst) then StateA <= '1'; StateB <= '0'; StateC <= '0'; StateD <= '0'; . . . StateZ <= '0'; elsif (rising_edge(Clk)) then if ( /state transition condition from X to A/ ) then StateX <= '0'; StateA <= '1'; end if; if ( /state transition condition from A to B/ ) then StateA <= '0'; StateB <= '1'; end if; . . . if ( error condition ) then StateA <= '0'; StateB <= '0'; ... all state signals defined ... StateZ <= '0'; end if; -- Error recovery end if; -- (if Rst) end process FSM; It would be trivial to create and maintain this from a state diagram. There is a one to one mapping of the state transitions to the functional sections of code. Rather than have a huge process, this could be simplified by writing each transition as a procedure. Unfortunately this might be a bit awkward to maintain as each procedure will require a custom list of inputs and outputs in two places in the code. But it might lend itself to some reuse of functions. An advantage of the previous state oriented method is that each signal is only controlled from a single IF statement so there is no interaction between the different sections. In the transition oriented code each state signal is set in one IF statement and reset in another so that there may be some mixing of conditions because the order in which they occur implies priority. Just thinking out loud here... >> Of course I haven't tested this. But then I have never seen a tool >> perform optimization that throws out valid logic that has inputs and >> outputs. >> > I don't know what you're talking about here. I believe someone mentioned that if cases were included for the error states that because the tool understands these states can not be reached it removes the logic for transitioning to "safe" states. I've never seen this behavior. I have only seen logic optimized away because it has either the input or output disconnected. -- Rick From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.68.134.66 with SMTP id pi2mr48106013pbb.9.1427878131768; Wed, 01 Apr 2015 01:48:51 -0700 (PDT) X-Received: by 10.140.108.38 with SMTP id i35mr541624qgf.3.1427878131511; Wed, 01 Apr 2015 01:48:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.glorb.com!m20no121019iga.0!news-out.google.com!q90ni2qgd.1!nntp.google.com!q107no1043026qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 01:48:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Safe FSM From: Thomas Stanka Injection-Date: Wed, 01 Apr 2015 08:48:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8208 Am Dienstag, 31. M=E4rz 2015 17:50:03 UTC+2 schrieb rickman: > I was not aware that the tools would perform that level of analysis.=20 > Where did you learn this? Is this from the vendor's optimization? Just perform structural equivalence check of designs synthesised by Synplif= y (without synkeep or similar), ask yourself why the tool finds differences= even in rather simple counters and than verify the equivalence check patte= rn is right by simulating the netlist. This is not necessary happen the first 1-2 designs, but if you do this seve= ral times you learn what to expect. best regards, Thomas From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Wed, 1 Apr 2015 11:02:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 63 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 1 Apr 2015 11:02:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="844"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ApLuDMckBfybMt+2q7AHLZOq7eorXCG0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:Ok8oMKr+cHkS8MQL1iEGmWDvnC4= Xref: mx02.eternal-september.org comp.lang.vhdl:8209 On Tue, 31 Mar 2015 18:40:24 -0400, rickman wrote: > On 3/31/2015 3:31 PM, KJ wrote: >> If you then take the above code and add 'when others=> Current_State <= >> Idle' to the case statement as a method to cover those 'impossible' >> states, synthesis tools will generally ignore it because I have already >> covered all of the possible cases in an earlier 'when ...'. > > This is exactly my point. Don't code like this. Code the one hot > states independently and the tool won't be able to see it as one large > FSM. Instead each state will appear as a separate FSM with nothing to > be optimized out. Error detection will consist of adding the state bits > and if the count is not exactly one, go to a safe state, a signal that > sets all the separate state bits to the appropriate value. I supplied > code for this earlier, but here is a version I like better based on the > transition specification rather than the present state value. > > FSM : process (Clk, Rst) > begin > if ('1' = Rst) then > StateA <= '1'; > StateB <= '0'; > StateC <= '0'; > StateD <= '0'; > . > . > . > StateZ <= '0'; I see where you're going with this, making every bit of every state assignment explicit. You could do the same without the clutter, by declaring State to be an array of bits, indexed by A to Z, and then: ------------------------------------------------------------- type State_Index is (A,B,C,...Z); type State_Type is array (State_Index) of bit; signal State : State_Type; constant State_A : State_Type is (A => '1', others => '0'); ... constant State_Z : State_Type is (Z => '1', others => '0'); ------------------------------------------------------------- All boiler plate, hide it in a package. But now your state machine is written as: ------------------------------------------------------------- FSM : process (Clk, Rst) begin if ('1' = Rst) then State <= State_A; elsif Rising_Edge(Clk) then ... ------------------------------------------------------------- all completely compatible with the traditional way of writing a state machine. In other words, we can retrofit your approach to any existing state machine - without any rewrite to them - simply by replacing its State_Type (an enumeration) declaration with the (packaged) declarations above. -- Brian From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.70.234 with SMTP id p70mr48831857yhd.56.1427892235860; Wed, 01 Apr 2015 05:43:55 -0700 (PDT) X-Received: by 10.140.91.47 with SMTP id y44mr80950qgd.39.1427892235845; Wed, 01 Apr 2015 05:43:55 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no1080219qgd.1!news-out.google.com!q90ni1qgd.1!nntp.google.com!z60no94303qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 05:43:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> Subject: Asynchronous MUTEX IN VHDL From: Charles Effiong Injection-Date: Wed, 01 Apr 2015 12:43:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: mx02.eternal-september.org comp.lang.vhdl:8210 Hi all, I need help. 1. Does anyone knows a gate level implementation of asynchronous metastability filter for mutex ? I couldn't find a gate level description online. 2. I created a MUTEX using two NAND gate. Interface is as below: entity ME is Port ( R1 : in STD_LOGIC; R2 : in STD_LOGIC; G1 : out STD_LOGIC; G2 : out STD_LOGIC); end ME; In my testbench, I have something like this: wait for clock_cycle; R1 <= '1'; wait for clock_cycle; R2 <= '1'; After running simulation, the output G1, G2 is 'U' :( If I change one of R1,R2 to be '0' it works. What could be wrong ? 3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it. Any help or reference materials would be appreciated. Thanks From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.50.103.41 with SMTP id ft9mr9699213igb.3.1427899720409; Wed, 01 Apr 2015 07:48:40 -0700 (PDT) X-Received: by 10.140.87.70 with SMTP id q64mr642517qgd.10.1427899720335; Wed, 01 Apr 2015 07:48:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!m20no206137iga.0!news-out.google.com!q90ni4qgd.1!nntp.google.com!z60no113508qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 07:48:40 -0700 (PDT) In-Reply-To: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.243.218.178; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go NNTP-Posting-Host: 195.243.218.178 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: hssig Injection-Date: Wed, 01 Apr 2015 14:48:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8211 Please spare us. I am so tired of reading your confusing and snotty postings. From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.42.76.145 with SMTP id e17mr74050185ick.34.1427909127351; Wed, 01 Apr 2015 10:25:27 -0700 (PDT) X-Received: by 10.50.1.113 with SMTP id 17mr236658igl.8.1427909127302; Wed, 01 Apr 2015 10:25:27 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed4a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!l13no380551iga.0!news-out.google.com!db6ni4151igc.0!nntp.google.com!m20no253835iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 10:25:26 -0700 (PDT) In-Reply-To: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <0b0a317c-3f71-467d-aa70-6d18b8ff42bd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Asynchronous MUTEX IN VHDL From: KJ Injection-Date: Wed, 01 Apr 2015 17:25:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 18 Xref: mx02.eternal-september.org comp.lang.vhdl:8212 On Wednesday, April 1, 2015 at 8:43:57 AM UTC-4, Charles Effiong wrote: > > After running simulation, the output G1, G2 is 'U' :( If I change one of R1,R2 to be '0' it works. What could be wrong ? > It's your code and you haven't posted it so it's your problem to figure out. > 3. Does anyone knows how to code an asynchronous arbiter that can be used to control a MUX or demux. I'm did the coding but have some problems simulating it. > Seems pretty simple to me... if (R1 = '1') then G1 <= '1'; G2 <= '0'; else G1 <= '0'; G2 <= R2; end if; Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Non-contiguous Subtypes Date: Wed, 1 Apr 2015 20:50:20 +0000 (UTC) Organization: A noiseless patient Spider Lines: 12 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 1 Apr 2015 20:50:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="1c311ff5f358f6f093526cc26a26a1ec"; logging-data="5735"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mVkIrO/4foGISyfzAnCQ1" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:6ExorhrvEs04I5R1tYtVNwNxxTI= Xref: mx02.eternal-september.org comp.lang.vhdl:8213 Random question while it's on my mind. So, there's VHDL support for declaring contiguous subtypes. subtype t_index is integer range 0 to 7; Is there any syntax for declaring discontiguous subtypes? Something like: subtype t_axi_datawidth is integer (8, 16, 32, 64, 128, 256, 512, 1024); -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.50.103.41 with SMTP id ft9mr12148486igb.3.1427931352298; Wed, 01 Apr 2015 16:35:52 -0700 (PDT) X-Received: by 10.50.111.233 with SMTP id il9mr279954igb.13.1427931352283; Wed, 01 Apr 2015 16:35:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no522258iga.0!news-out.google.com!db6ni4365igc.0!nntp.google.com!m20no833iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Apr 2015 16:35:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <622673bb-6d01-45b9-9c66-b896999fc926@googlegroups.com> Subject: Re: Non-contiguous Subtypes From: diogratia@gmail.com Injection-Date: Wed, 01 Apr 2015 23:35:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8214 On Thursday, April 2, 2015 at 9:51:15 AM UTC+13, Rob Gaddi wrote: > Random question while it's on my mind. So, there's VHDL support for=20 > declaring contiguous subtypes. >=20 > subtype t_index is integer range 0 to 7; >=20 > Is there any syntax for declaring discontiguous subtypes? Something like= : >=20 > subtype t_axi_datawidth is integer (8, 16, 32, 64, 128, 256, 512, 1024)= ; No. IEEE Std 1076-2008 5.2 Scalar types, 5.2.1 General: Scalar types consist of enumeration types, integer types, physical types, a= nd floating-point types. Enumeration types and integer types are called dis= crete types. Integer types, floating-point types, and physical types are ca= lled numeric types. All scalar types are ordered; that is, all relational o= perators are predefined for their values. Each value of a discrete or physi= cal type has a position number that is an integer value. --=20 It's that position number which is used for numeric operations. 5.2.3 Integer types, 5.2.3.1 General: An integer type definition defines an integer type whose set of values incl= udes those of the specified range. Integer_type_definition ::=3D range_constraint -- Back to 5.2.1: range_constraint ::=3D range range range ::=3D=20 range_attribute_name | simple_expression direction simple_expression=20 direction ::=3D to | downto -- Only constrained range Back to 5.2.3.1: Integer literals are the literals of an anonymous predefined type that is c= alled universal_integer in this standard. Other integer types have no liter= als. However, for each integer type there exists an implicit conversion tha= t converts a value of type universal_integer into the corresponding value (= if any) of the integer type (see 9.3.6). The position number of an integer value is the corresponding value of the t= ype universal_integer. -- So we have two aspects to a type, position and value. For integer types pos= ition is given as a universal_integer, convertible to the integer type, and= it's position is also tied to universal_integer. =20 While you're proposed subtype is discrete, arithmetic operation results can= 't be expressed in it inclusively, for instance any two of it's values adde= d together don't result in a value of the proposed subtype. 5.2.3.1: The same arithmetic operators are predefined for all integer types (see 9.2= ). It is an error if the execution of such an operation (in particular, an = implicit conversion) cannot deliver the correct result (that is, if the val= ue corresponding to the mathematical result is not a value of the integer t= ype). -- Notice you can't use your subtype values as an enumeration type, an enumera= tion literal is either an identifier or a character literal (5.2.2.1). You could create an enumeration type and use it as an index into a constant= array of integer values: entity axiwidth is end entity; architecture foo of axiwidth is type axi_datawidth is ( AXI_WIDTH8, AXI_WIDTH16, AXI_WIDTH32,=20 AXI_WIDTH64, AXI_WIDTH128, AXI_WIDTH256, AXI_WIDTH_512, AXI_WIDTH1024); type axi_values is array (axi_datawidth) of positive; constant axi_datawidth_value: axi_values :=3D ( 8, 16, 32, 64,= =20 128, 256, 512, 1024);= =20 signal a: integer :=3D axi_datawidth_value(AXI_WIDTH16); begin RESULT: assert FALSE report "a =3D " & integer'image(a) severity NOTE; end architecture; =20 And if you wanted to access them by position of the axi_datawidth type you = could convert position to value by using axi_datawidth'VAL. From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Safe FSM Date: Wed, 01 Apr 2015 19:38:36 -0400 Organization: A noiseless patient Spider Lines: 71 Message-ID: References: <33043105-35ea-4efd-aaf4-5192b5c5036e@googlegroups.com> <7dccf795-f4c1-4108-b548-8158427f2275@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Apr 2015 23:37:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7758"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+o1QrUZkorb0kVgpX2EUcj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 In-Reply-To: Cancel-Lock: sha1:lCqoLQ35iHxT95OZrC+Mwk9+Skg= Xref: mx02.eternal-september.org comp.lang.vhdl:8215 On 4/1/2015 7:02 AM, Brian Drummond wrote: > On Tue, 31 Mar 2015 18:40:24 -0400, rickman wrote: > >> On 3/31/2015 3:31 PM, KJ wrote: > >>> If you then take the above code and add 'when others=> Current_State <= >>> Idle' to the case statement as a method to cover those 'impossible' >>> states, synthesis tools will generally ignore it because I have already >>> covered all of the possible cases in an earlier 'when ...'. >> >> This is exactly my point. Don't code like this. Code the one hot >> states independently and the tool won't be able to see it as one large >> FSM. Instead each state will appear as a separate FSM with nothing to >> be optimized out. Error detection will consist of adding the state bits >> and if the count is not exactly one, go to a safe state, a signal that >> sets all the separate state bits to the appropriate value. I supplied >> code for this earlier, but here is a version I like better based on the >> transition specification rather than the present state value. >> >> FSM : process (Clk, Rst) >> begin >> if ('1' = Rst) then >> StateA <= '1'; >> StateB <= '0'; >> StateC <= '0'; >> StateD <= '0'; >> . >> . >> . >> StateZ <= '0'; > > I see where you're going with this, making every bit of every state > assignment explicit. > > You could do the same without the clutter, by declaring State to be an > array of bits, indexed by A to Z, and then: > > ------------------------------------------------------------- > type State_Index is (A,B,C,...Z); > type State_Type is array (State_Index) of bit; > > signal State : State_Type; > constant State_A : State_Type is (A => '1', others => '0'); > ... > constant State_Z : State_Type is (Z => '1', others => '0'); > ------------------------------------------------------------- > All boiler plate, hide it in a package. > > But now your state machine is written as: > ------------------------------------------------------------- > FSM : process (Clk, Rst) > begin > if ('1' = Rst) then > State <= State_A; > elsif Rising_Edge(Clk) then ... > ------------------------------------------------------------- > all completely compatible with the traditional way of writing a state > machine. In other words, we can retrofit your approach to any existing > state machine - without any rewrite to them - simply by replacing its > State_Type (an enumeration) declaration with the (packaged) declarations > above. I was never a fan of the "traditional" way of describing a state machien. But my concern would be that your method would not get around the FSM recognition by the tools. You are still using one signal for the state variable, it just happens to have N bits just like any other state variable with more than two bits. -- Rick From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.97.99 with SMTP id s63mr7935790yhf.40.1428146798400; Sat, 04 Apr 2015 04:26:38 -0700 (PDT) X-Received: by 10.51.17.10 with SMTP id ga10mr140142igd.6.1428146798372; Sat, 04 Apr 2015 04:26:38 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no451261qga.1!news-out.google.com!db6ni6690igc.0!nntp.google.com!l13no599405iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 4 Apr 2015 04:26:37 -0700 (PDT) In-Reply-To: <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=104.172.32.254; posting-account=uXeJ4gkAAADS8JQB6S6LUjzELiulwQRn NNTP-Posting-Host: 104.172.32.254 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <52d82a64-961d-4327-addf-f2c25da12775@googlegroups.com> <3d37df8f-8c7d-49e9-a359-84e102540856@googlegroups.com> <17e2d2ba-518a-4112-8134-ac6b20b83844@googlegroups.com> <93020ca1-07dc-4067-9451-d3fe07b89c0c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93a688d8-0559-46c6-ac5b-5170f9c1f65e@googlegroups.com> Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: Weng Tianxiang Injection-Date: Sat, 04 Apr 2015 11:26:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 173 Xref: mx02.eternal-september.org comp.lang.vhdl:8216 On Monday, March 30, 2015 at 2:18:41 AM UTC-7, diog...@gmail.com wrote: > On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote: > > On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote: > > >=20 > > > Why currently VHDL committee has so many difficulties financially to = get industries into its activities? One most important reason is that VHDL = is now free to use for all related companies and they don't have to make th= eir contributions. > > >=20 > >=20 > > That's the reason why standard bodies have by-laws that make sure any i= nformation submitted or discussed within working groups are not encumbered = by patents. If you are trying to discuss your patent idea within a working = group, you need to declare that the information has been patented. In which= case, the Chair will tell the whole group to not use that information in t= he standardization process. I think this is how it goes for most standard b= odies. > >=20 >=20 > See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page = 4: >=20 > * The DASC will only accept patented material > under paragraph (a) of IEEE Patent Policy >=20 > Where paragraph (a) is found on PDF Page 2 (Slide #1): >=20 > a) A general disclaimer to the effect that the patentee will not enfo= rce > any of its present or future patent(s) whose use would be required= to=20 > implement either mandatory or optional potions of the proposed IEE= E > standard against any person or entity complying with the standard;= or=20 >=20 >=20 > The VASG P1076 effort falls under these conditions, no one is going to ge= t rich on a standard essential patent required to implement the VHDL standa= rd (nor either Verilog standards also under the auspices of DASC). >=20 > Also note Page 3 (slide #2): >=20 > Inappropriate Topics for IEEE WG Meetings > * Don't discuss licensing terms or conditions > ... -dio, Thank you for your good information.=20 No matter whether or not I get rich through it, I will perfect my invented = method to make contribution to science. I will have another two successive patent applications about the same topic= s to publish in this group to perfect "the systematic method of coding wave= pipelined circuits in HDL" so that it will be used universally in all mode= rn 4-core processors someday, not mention in FPGA. If someone is tired of reading new inventions, please stay away and you are= not forced or flirted to read those "confusing and snotty" inventions. Weng Here are some important sections in my patent application: New concurrent link statement in HDL [0137] In order to let a synthesizer identify which code is a wave-pipel= ining ready code and help check the correctness of connections and paired t= ype between a WPC instantiation and a CPC instantiation, three versions of = new concurrent link statement are suggested to be introduced into HDL. [0138] Here is the definition of new concurrent link statement in bold t= ype based on VHDL-2002:=20 concurrent_statement ::=3D block_statement | link_statement | process_statement | concurrent_procedure_call_statement | concurrent_assertion_statement | concurrent_signal_assignment_statement | component_instantiation_statement | generate_statement link_statement ::=3D [ link_label : ] link_name ( wave_pipelining_component_label ,=20 critical_path_component_label [ , alias_wave_constant_list ] ) ; link_label ::=3D label link_name ::=3D link1 | link2 | link3=20 wave_pipelining_component_label ::=3D label critical_path_component_label ::=3D=20 series_component_label |input_delay_component_label |multiple_copy_component_label series_component_label ::=3D label input_delay_component_label ::=3D label multiple_copy_component_label ::=3D generate_label , copy_component_label copy_component_label ::=3D label label ::=3D identifier [0139] The set of following rules is called link statement mechanism: * Link1 statement links a WPC series_module instantiation with a series CPC= instantiation and optional alias wave constants whose initial value is wav= e constant series_clock_number and which share the wave constant value of t= he linked WPC series_module. * Link2 statement links a WPC input_delay_module instantiation with a serie= s or a feedback CPC instantiation, and optional alias wave constants whose = initial value is either wave constant series_clock_number or input_clock_nu= mber and which share the wave constant value of the linked WPC input_delay_= module. * Link3 statement links a WPC multiple_copy_module instantiation with a gen= erate statement, a series or a feedback CPC instantiation, and optional ali= as wave constants whose initial value is either wave constant series_clock_= number or multiple_copy_number and which share the wave constant value of t= he linked WPC multiple_copy_module. * Wave_pipelining_component_label is the label marking the instantiation of= a WPC series_module, input_delay_module or multiple_copy_module.=20 * Critical_path_component_label is the label marking a CPC instantiation.= =20 o Series_component_label is the label marking the instantiation of a ser= ies CPC linked by a link1 statement. o Input_delay_component_label is the label marking the instantiation of = a series or a feedback CPC linked by a link2 statement. o Multiple_copy_component_label contains two labels, the first one is ge= nerate_label marking a generate statement which generates multiple copied C= PCs, the second is copy_component_label marking the instantiation of one of= multiple copied series or feedback CPCs and linked by a link3 statement.= =20 * Both wave_pipelining_component_label and critical_path_component_label mu= st be located within the concurrent statement area of same architecture bas= ed on VHDL-2002, and can be referenced before they are defined in a link st= atement which is located in the same concurrent statement area.=20 * An alias wave constant must be visible to the link statement it involves. * When a WPC multiple_copy_module is instantiated and linked with a generat= e statement through a link3 statement, the wave constant multiple_copy_numb= er in the multiple_copy_module receives its new initial value through wave = constant mechanism under slow mode and target mode, respectively, and the l= inked generate statement uses the wave constant multiple_copy_number consta= nt value to generate 1 or more CPC under slow mode and target mode, respect= ively. The range used in the generate statement is fixed and must be from 0= to multiple_copy_number-1 or multiple_copy_number-1 downto 0. The following several sections will not be published because it is related = to synthesizing technology: How a synthesizer determines wave constant values for a linked pair of a WP= C and a CPC. How a synthesizer gets wave constant values of a WPC under target mode. How a synthesizer gets an alias wave constant value under target mode. How a designer generates a successful wave-pipelined design in HDL. Thank you for your patient reading. Weng=20 From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.229.233 with SMTP id h99mr13576439yhq.42.1428261141421; Sun, 05 Apr 2015 12:12:21 -0700 (PDT) X-Received: by 10.140.23.163 with SMTP id 32mr133471qgp.13.1428261141343; Sun, 05 Apr 2015 12:12:21 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no695852qga.1!news-out.google.com!q14ni5765ign.0!nntp.google.com!j5no695850qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 12:12:21 -0700 (PDT) In-Reply-To: <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:a4c6:c67c:efb8:2a28; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:a4c6:c67c:efb8:2a28 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: KJ Injection-Date: Sun, 05 Apr 2015 19:12:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2975 X-Received-Body-CRC: 284686477 Xref: mx02.eternal-september.org comp.lang.vhdl:8217 On Tuesday, March 31, 2015 at 11:31:35 AM UTC-4, Weng Tianxiang wrote: > On Tuesday, March 24, 2015 at 7:24:11 PM UTC-7, KJ wrote: > > On Tuesday, March 24, 2015 at 2:24:31 PM UTC-4, Weng Tianxiang wrote: > > >=20 > > > Here I publish all source code for public confirmation. > > > > >=20 > > What exactly would you like the public to confirm? Do you have made so= me specific claims? > >=20 > > Given that you have not claimed anything specific, I can only confirm t= he following: > > - It does compile (Modelsim 10.3c) > > - It does synthesize to something (Quartus 14.0; Top level entity=3DCPC= 1; 56 Max II logic elements) > >=20 > > >=20 > > > You may copy this part of code to do simulation by yourself. > > > > >=20 > > Why would I want to simulate it? > >=20 > > Kevin Jennings >=20 > Here is how I claim to increase very-hard-implemented wave pipelined circ= uits to 100% successful rate. >=20 Since you had requested 'public confirmation', the 'public' states that you= r claim can be refuted, not confirmed. Maybe you'll have better luck at US= PTO. Then again, you may actually have a requirement now to disclose this = thread to USPTO as being relevant background information regarding your pro= posed invention. Kevin From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.43.146 with SMTP id l18mr14363399yhb.55.1428261162035; Sun, 05 Apr 2015 12:12:42 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr136882qgz.21.1428261161997; Sun, 05 Apr 2015 12:12:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no896142qgd.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no896141qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 12:12:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> Subject: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Sun, 05 Apr 2015 19:12:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2035 X-Received-Body-CRC: 1646991532 Xref: mx02.eternal-september.org comp.lang.vhdl:8218 Hi, I have this NOT gate code: entity NOTgate is generic (latency : time); Port ( Data_in : in STD_LOGIC; Data_out : out STD_LOGIC); end NOTgate; architecture NOTgate_arch of NOTgate is signal data_temp : STD_LOGIC := '0'; begin process (Data_in) begin data_temp <= NOT Data_in; end process; Data_out <= transport data_temp after latency; end NOTgate_arch; I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below: entity NOTG is generic (latency : time); Port ( Data_in : in STD_LOGIC); end NOTG; architecture NOTG_arch of NOTG is signal sig_in : STD_LOGIC := '0'; begin sig_in <= Data_in; NOTG0 : Entity work.NOTgate port map( Data_in => sig_in, Data_out => sig_in, ); end NOTG_arch; This doesn't work. Where am I missing it? Thanks From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.redatomik.org!nntpfeed.proxad.net!proxad.net!feeder2-2.proxad.net!cleanfeed1-a.proxad.net!nnrp2-2.free.fr!not-for-mail Date: Sun, 05 Apr 2015 22:44:18 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> In-Reply-To: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150405-1, 05/04/2015), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: <55219ea1$0$3342$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 05 Apr 2015 22:44:18 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1428266658 news-4.free.fr 3342 88.185.146.198:1717 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8219 Le 05/04/2015 21:12, Charles Effiong a écrit : [...] > I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below: > > entity NOTG is > generic (latency : time); > Port ( > Data_in : in STD_LOGIC); > end NOTG; > > architecture NOTG_arch of NOTG is > signal sig_in : STD_LOGIC := '0'; > begin > sig_in <= Data_in; > > NOTG0 : Entity work.NOTgate > port map( > Data_in => sig_in, > Data_out => sig_in, > ); > end NOTG_arch; > > This doesn't work. Where am I missing it? Thanks What exactly doesn't work ? I see several problems. First, there shouldn't be a comma after data_out => sig_in since it's the last association of the list. This is where you close the parenthesis. Second, you create two drivers on sig_in, one is the entity input, the other is the not gate output. What exactly do you think you're doing ? Third, I don't know how the tool you're using optimizes the code but basically, you're trying to drive an input through sig_in. This doesn't work. Last, are you simulating this or trying to synthesize it ? (hint : synthesis won't work) Nicolas From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.182.97.2 with SMTP id dw2mr14426660obb.0.1428268311722; Sun, 05 Apr 2015 14:11:51 -0700 (PDT) X-Received: by 10.140.47.56 with SMTP id l53mr134216qga.25.1428268311614; Sun, 05 Apr 2015 14:11:51 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1268633iga.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no913473qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 14:11:51 -0700 (PDT) In-Reply-To: <55219ea1$0$3342$426a34cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Sun, 05 Apr 2015 21:11:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8220 On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: > Le 05/04/2015 21:12, Charles Effiong a =E9crit : > [...] > > I now want to connect the inverter's output to its input to form a feed= back loop. I Created another component as below: > > > > entity NOTG is > > generic (latency : time); > > Port ( > > Data_in : in STD_LOGIC); > > end NOTG; > > > > architecture NOTG_arch of NOTG is > > signal sig_in : STD_LOGIC :=3D '0'; > > begin > > sig_in <=3D Data_in; > > > > NOTG0 : Entity work.NOTgate > > port map( > > Data_in =3D> sig_in, =09 > > Data_out =3D> sig_in, > > ); > > end NOTG_arch; > > > > This doesn't work. Where am I missing it? Thanks >=20 > What exactly doesn't work ? I see several problems. > First, there shouldn't be a comma after data_out =3D> sig_in since it's= =20 > the last association of the list. This is where you close the parenthesis= . > Second, you create two drivers on sig_in, one is the entity input, the=20 > other is the not gate output. What exactly do you think you're doing ? > Third, I don't know how the tool you're using optimizes the code but=20 > basically, you're trying to drive an input through sig_in. This doesn't= =20 > work. > Last, are you simulating this or trying to synthesize it ? (hint :=20 > synthesis won't work) >=20 > Nicolas Thanks @Nicolas.=20 "First, there shouldn't be a comma after data_out =3D> sig_in since it's=20 the last association of the list" That was a typo, I fixed that but it still doesn't work.=20 Basically, I want to connect the inverter's output to it's input so as to f= orm a feed back loop. What should I do ? From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 05 Apr 2015 19:01:47 -0500 Date: Mon, 06 Apr 2015 01:01:47 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 58 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-zigwmTWLpNhTEkAZwGuYCDR6F9BmUWHfSAs692VBBzupUw7R9HYMvD7nBY1RtbeWkE/pYZqPI2S9V3J!vuzzOGsxEb2LbXGVDm0JQRFAQ2yT4EL9zFbdslmsTwSrmJt720Tx1NLrswaPNZAWszS8mzR3LvxT!Zgh3K7R5Csl2Ye6D0ayNwECE0g== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2973 Xref: mx02.eternal-september.org comp.lang.vhdl:8221 On 05/04/15 22:11, Charles Effiong wrote: > On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: >> Le 05/04/2015 21:12, Charles Effiong a écrit : >> What exactly doesn't work ? I see several problems. >> First, there shouldn't be a comma after data_out => sig_in since it's >> the last association of the list. This is where you close the parenthesis. >> Second, you create two drivers on sig_in, one is the entity input, the >> other is the not gate output. What exactly do you think you're doing ? >> Third, I don't know how the tool you're using optimizes the code but >> basically, you're trying to drive an input through sig_in. This doesn't >> work. >> Last, are you simulating this or trying to synthesize it ? (hint : >> synthesis won't work) >> >> Nicolas > > Thanks @Nicolas. > > "First, there shouldn't be a comma after data_out => sig_in since it's > the last association of the list" > > That was a typo, I fixed that but it still doesn't work. > > Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ? > Don't you just want entity NOTG is generic (latency : time); Port ( Data_in : in STD_LOGIC); end NOTG; architecture NOTG_arch of NOTG is signal sig_in : STD_LOGIC := '0'; begin -- sig_in <= Data_in; -- <====== ?? NOTG0 : Entity work.NOTgate generic map (latency => latency) -- <======= you forgot this port map( Data_in => sig_in, Data_out => sig_in ); end NOTG_arch; ? I'm not sure what Data_in is for? Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.69.13.226 with SMTP id fb2mr14786132pbd.0.1428286091447; Sun, 05 Apr 2015 19:08:11 -0700 (PDT) X-Received: by 10.50.176.200 with SMTP id ck8mr60121igc.12.1428286091413; Sun, 05 Apr 2015 19:08:11 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!l13no1348347iga.0!news-out.google.com!db6ni8110igc.0!nntp.google.com!m20no1114962iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 19:08:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.57.181.101; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.57.181.101 References: <442409be-d9bc-4ad6-ba6c-4b9d19436a79@googlegroups.com> <56e891f6-1856-4823-adc6-d433074aae4f@googlegroups.com> <7b59ed11-0c21-4434-b68d-f5ceccb93d93@googlegroups.com> <6275f094-46a6-421a-9b1b-5a77c04cc5b6@googlegroups.com> <8494bf7d-be43-4d53-ab38-29c436c989d4@googlegroups.com> <747015e8-e00f-478d-a8f6-6766a5bdf65a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: New invention: Systematic method of coding wave pipelined circuits in HDL From: diogratia@gmail.com Injection-Date: Mon, 06 Apr 2015 02:08:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8222 On Thursday, April 2, 2015 at 3:48:44 AM UTC+13, hssig wrote: > Please spare us. I am so tired of reading your confusing and snotty postings. hssig - Water off a ducks back. He didn't take the hint. It seems no matter how anyone attempts to discourage him he continues on like some dreary (in an Edgar Allan Poe sense) Energizer bunny. From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.50.43.229 with SMTP id z5mr16234698igl.3.1428294535005; Sun, 05 Apr 2015 21:28:55 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr630936igt.17.1428294534981; Sun, 05 Apr 2015 21:28:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no1374704iga.0!news-out.google.com!db6ni8267igc.0!nntp.google.com!l13no1374694iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Apr 2015 21:28:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.16.22.65; posting-account=B-IhCwoAAACJWXsdr6tDUzWsruhD9tjI NNTP-Posting-Host: 117.16.22.65 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7c78fa9c-1452-42e8-8df5-f6b2f01263a8@googlegroups.com> Subject: Graduate Research Assistantship at the Computer Systems Lab, College of Electronics and Information Engineering, Chosun University, Gwangju, Republic of Korea From: Olufemi Adeluyi Injection-Date: Mon, 06 Apr 2015 04:28:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8223 Graduate Research Assistantship at the Computer Systems Lab, College of Ele= ctronics and Information Engineering, Chosun University, Gwangju, Republic = of Korea =3D=3D=3D We seek skillful, hard working and highly motivated candidates with good cr= edentials to join our dynamic international research team as PhD or Integra= ted MSc-PhD students. There are vacancies in the following areas of focus: a. Configurable Computing b. Embedded Computing c. Self-Aware Computing For a Fall Semester (September 1, 2015) admission, interested applicants sh= ould apply by Monday, April 27, 2015=20 An applicant must meet the following requirements: * Hold a Bachelor's or Master's degree by September 1, 2015 o For an Integrated MSc-PhD program: students should hold a Bachelor's deg= ree or a diploma that is equivalent to or higher than Bachelor's degree o For a Doctoral program: students should hold a Master's degree or a diplo= ma that is equivalent to or higher than Master's degree. * Important Requirements: o Good background in the listed area(s) of research o Good programming skills o Good English language skills- written and oral (For applicants whose moth= er tongue is not English: IELTS 6.5 or higher OR TOEFL IBT 90) o Good ability to cooperate with others in a multicultural environment o A cumulative GPA score of 80% or higher Application Procedure =3D=3D=3D Interested applicants should send the following to Prof Lee, Jeong-A, Depa= rtment of Computer Engineering by the application dead= line. 1) Study plan (clearly stating the research topics you are interested in. W= e would like to know your research interests and their relation to the give= n research areas) 2) Academic transcripts 3) Brief summary of most recent thesis and the status (eg accepted, in prog= ress, submitted, etc) 4) CV (to include names, date of birth, nationality, gender, contact detail= s, education, work experience, publications and referees) Only electronic applications are accepted. All items should be merged as on= e pdf file with the name Familyname_Firstname_Chosun_App2015.pdf. and must = be sent by the stated date with "2015 Application for Research Assistantshi= p at Computer Systems Lab" as the e-mail subject. From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.50.117.8 with SMTP id ka8mr35023800igb.6.1428309419367; Mon, 06 Apr 2015 01:36:59 -0700 (PDT) X-Received: by 10.140.18.237 with SMTP id 100mr153931qgf.8.1428309419239; Mon, 06 Apr 2015 01:36:59 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1153986iga.0!news-out.google.com!k20ni2qgd.0!nntp.google.com!z60no975763qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Apr 2015 01:36:59 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Mon, 06 Apr 2015 08:36:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8224 On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: > On 05/04/15 22:11, Charles Effiong wrote: > > On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: > >> Le 05/04/2015 21:12, Charles Effiong a =E9crit : > > >> What exactly doesn't work ? I see several problems. > >> First, there shouldn't be a comma after data_out =3D> sig_in since it'= s=20 > >> the last association of the list. This is where you close the parenthe= sis. > >> Second, you create two drivers on sig_in, one is the entity input, the= =20 > >> other is the not gate output. What exactly do you think you're doing ? > >> Third, I don't know how the tool you're using optimizes the code but= =20 > >> basically, you're trying to drive an input through sig_in. This doesn'= t=20 > >> work. > >> Last, are you simulating this or trying to synthesize it ? (hint :=20 > >> synthesis won't work) > >> > >> Nicolas > >=20 > > Thanks @Nicolas.=20 > >=20 > > "First, there shouldn't be a comma after data_out =3D> sig_in since it'= s=20 > > the last association of the list" > >=20 > > That was a typo, I fixed that but it still doesn't work.=20 > >=20 > > Basically, I want to connect the inverter's output to it's input so as = to form a feed back loop. What should I do ? > >=20 >=20 > Don't you just want >=20 > entity NOTG is > generic (latency : time); > Port ( > Data_in : in STD_LOGIC); > end NOTG; >=20 > architecture NOTG_arch of NOTG is > signal sig_in : STD_LOGIC :=3D '0'; > begin >=20 > -- sig_in <=3D Data_in; -- <=3D=3D=3D=3D=3D=3D ?? >=20 > NOTG0 : Entity work.NOTgate > generic map (latency =3D> latency) -- <=3D=3D=3D=3D=3D=3D=3D yo= u forgot this > port map( > Data_in =3D> sig_in, =09 > Data_out =3D> sig_in > ); > end NOTG_arch; >=20 > ? >=20 > I'm not sure what Data_in is for? >=20 > Alan >=20 >=20 > --=20 > Alan Fitch Thanks @Alan. I want an initial entry point into the circuit, hence "Data_i= n" I guess this is wrong. Also how can I connect the NOT gate output to it'= s input to form a loop? From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 06 Apr 2015 08:29:07 -0500 Date: Mon, 06 Apr 2015 14:29:07 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> In-Reply-To: <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 73 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-kYJgJKtF9CSLKdvAy2mUEYc2k2QLasTVgLgX/Ub6SxEnmIwCCVSanN4/iX0ACh4gJGyKKY2AXQTC6g7!Zs+sRR/utFHCB8Ul6SHX/Cm9osESHjKfbXARA3lVngbXYgk+xg58X3Re780bjwnNX7iE2U14ddjv!1mbd/YFMMV6O0EkyFT5LxHo6mg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3665 Xref: mx02.eternal-september.org comp.lang.vhdl:8225 On 06/04/15 09:36, Charles Effiong wrote: > On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: >> On 05/04/15 22:11, Charles Effiong wrote: >>> On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote: >>>> Le 05/04/2015 21:12, Charles Effiong a écrit : >> >>>> What exactly doesn't work ? I see several problems. >>>> First, there shouldn't be a comma after data_out => sig_in since it's >>>> the last association of the list. This is where you close the parenthesis. >>>> Second, you create two drivers on sig_in, one is the entity input, the >>>> other is the not gate output. What exactly do you think you're doing ? >>>> Third, I don't know how the tool you're using optimizes the code but >>>> basically, you're trying to drive an input through sig_in. This doesn't >>>> work. >>>> Last, are you simulating this or trying to synthesize it ? (hint : >>>> synthesis won't work) >>>> >>>> Nicolas >>> >>> Thanks @Nicolas. >>> >>> "First, there shouldn't be a comma after data_out => sig_in since it's >>> the last association of the list" >>> >>> That was a typo, I fixed that but it still doesn't work. >>> >>> Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ? >>> >> >> Don't you just want >> >> entity NOTG is >> generic (latency : time); >> Port ( >> Data_in : in STD_LOGIC); >> end NOTG; >> >> architecture NOTG_arch of NOTG is >> signal sig_in : STD_LOGIC := '0'; >> begin >> >> -- sig_in <= Data_in; -- <====== ?? >> >> NOTG0 : Entity work.NOTgate >> generic map (latency => latency) -- <======= you forgot this >> port map( >> Data_in => sig_in, >> Data_out => sig_in >> ); >> end NOTG_arch; >> >> ? >> >> I'm not sure what Data_in is for? >> >> Alan >> >> >> -- >> Alan Fitch > > Thanks @Alan. I want an initial entry point into the circuit, hence "Data_in" I guess this is wrong. Also how can I connect the NOT gate output to it's input to form a loop? > I don't know what you mean by "initial entry point". I showed you how to connect the input to the output above, regards Alan -- Alan Fitch From newsfish@newsfish Tue Dec 29 16:43:48 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!news.muarf.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp4-2.free.fr!not-for-mail Date: Mon, 06 Apr 2015 16:30:01 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Connect output of inverter to it's input References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150406-0, 06/04/2015), Outbound message X-Antivirus-Status: Clean Lines: 8 Message-ID: <55229866$0$3191$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 06 Apr 2015 16:29:59 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1428330599 news-1.free.fr 3191 88.185.146.198:1437 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8226 Le 05/04/2015 23:11, Charles Effiong a écrit : > That was a typo, I fixed that but it still doesn't work. You still don't say what exactly doesn't work. That's like going to your doctor and telling him "Doctor, I'm sick" and hoping he'll cure you with that much information. Nicolas From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.182.44.199 with SMTP id g7mr25537145obm.11.1428421653984; Tue, 07 Apr 2015 08:47:33 -0700 (PDT) X-Received: by 10.50.90.178 with SMTP id bx18mr77300igb.13.1428421653968; Tue, 07 Apr 2015 08:47:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2083307iga.0!news-out.google.com!n7ni1259igk.0!nntp.google.com!l13no2083297iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Apr 2015 08:47:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> Subject: What is wrong tihis function code? From: fl Injection-Date: Tue, 07 Apr 2015 15:47:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8227 Hi, I am learning to write a VHDL function code. Modelsim complains that something wrong at function line. The code is: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; function s1qrt ( d : unsigned ) return unsigned is variable a : unsigned(31 downto 0) := d; --original input. variable q : unsigned(15 downto 0) := (others => '0'); --result. variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder. variable i : integer := 0; begin -- for i in 0 to 15 loop right(0) := '1'; right(1) := r(17); right(17 downto 2) := q; left(1 downto 0) := a(31 downto 30); left(17 downto 2) := r(15 downto 0); a(31 downto 2) := a(29 downto 0); --shifting by 2 bit. if ( r(17) = '1') then r := left + right; else r := left - right; end if; q(15 downto 1) := q(14 downto 0); q(0) := not r(17); -- end loop; return q; end s1qrt; I cannot make it out what is wrong. Could you help me? Thanks, From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.70.48.206 with SMTP id o14mr24960286pdn.1.1428430422699; Tue, 07 Apr 2015 11:13:42 -0700 (PDT) X-Received: by 10.50.57.104 with SMTP id h8mr98724igq.15.1428430422663; Tue, 07 Apr 2015 11:13:42 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2150315iga.0!news-out.google.com!db6ni9744igc.0!nntp.google.com!l13no2150311iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Apr 2015 11:13:42 -0700 (PDT) In-Reply-To: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <9e5eb9d1-72f2-4894-b3fd-0c2233dbb3ea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b9af879-90bf-4d3c-af35-f4f37454479e@googlegroups.com> Subject: Re: What is wrong tihis function code? From: KJ Injection-Date: Tue, 07 Apr 2015 18:13:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8228 On Tuesday, April 7, 2015 at 11:47:37 AM UTC-4, fl wrote: > Hi, > I am learning to write a VHDL function code. Modelsim complains that something > wrong at function line. The code is: > > library IEEE; > use IEEE.std_logic_1164.all; > use ieee.numeric_std.all; > function s1qrt ( d : unsigned ) return unsigned is > variable a : unsigned(31 downto 0) := d; --original input. > variable q : unsigned(15 downto 0) := (others => '0'); --result. > variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder. > variable i : integer := 0; > begin > -- for i in 0 to 15 loop > right(0) := '1'; > right(1) := r(17); > right(17 downto 2) := q; > left(1 downto 0) := a(31 downto 30); > left(17 downto 2) := r(15 downto 0); > a(31 downto 2) := a(29 downto 0); --shifting by 2 bit. > if ( r(17) = '1') then > r := left + right; > else > r := left - right; > end if; > > q(15 downto 1) := q(14 downto 0); > q(0) := not r(17); > -- end loop; > return q; > > end s1qrt; > > I cannot make it out what is wrong. Could you help me? > > Thanks, Functions must always be embedded within something such as a package or an entity/architecture. The general hierarchy is: - entity: This will define the interface (i.e. inputs and outputs) of a design - architecture: This defines the logic implemented given the entity I/O. A function can be defined within an architecture or within a process. Below shows where it would go. Functions can also be defined in packages, but let's defer that for now entity foo is port map(....) end foo; architecture rtl of foo is function s1qrt ( d : unsigned ) return unsigned is ... end function s1qrt; begin process(...) function s1qrt ( d : unsigned ) return unsigned is ... end function s1qrt; begin end process; end rtl; Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.43.178.201 with SMTP id ox9mr25880533icc.12.1428579549941; Thu, 09 Apr 2015 04:39:09 -0700 (PDT) X-Received: by 10.140.30.118 with SMTP id c109mr424268qgc.15.1428579549799; Thu, 09 Apr 2015 04:39:09 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no2965906iga.0!news-out.google.com!k20ni70qgd.0!nntp.google.com!j5no511671qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 04:39:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 References: <703a45a3-0d92-4c2d-99aa-b19f389efb50@googlegroups.com> <55219ea1$0$3342$426a34cc@news.free.fr> <7695d6c6-0585-4f1e-809e-b18eff0cc4cd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Connect output of inverter to it's input From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 11:39:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8229 On Monday, April 6, 2015 at 3:29:09 PM UTC+2, Alan Fitch wrote: > On 06/04/15 09:36, Charles Effiong wrote: > > On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote: > >> On 05/04/15 22:11, Charles Effiong wrote: > >>> On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote= : > >>>> Le 05/04/2015 21:12, Charles Effiong a =E9crit : > >> > >>>> What exactly doesn't work ? I see several problems. > >>>> First, there shouldn't be a comma after data_out =3D> sig_in since i= t's=20 > >>>> the last association of the list. This is where you close the parent= hesis. > >>>> Second, you create two drivers on sig_in, one is the entity input, t= he=20 > >>>> other is the not gate output. What exactly do you think you're doing= ? > >>>> Third, I don't know how the tool you're using optimizes the code but= =20 > >>>> basically, you're trying to drive an input through sig_in. This does= n't=20 > >>>> work. > >>>> Last, are you simulating this or trying to synthesize it ? (hint := =20 > >>>> synthesis won't work) > >>>> > >>>> Nicolas > >>> > >>> Thanks @Nicolas.=20 > >>> > >>> "First, there shouldn't be a comma after data_out =3D> sig_in since i= t's=20 > >>> the last association of the list" > >>> > >>> That was a typo, I fixed that but it still doesn't work.=20 > >>> > >>> Basically, I want to connect the inverter's output to it's input so a= s to form a feed back loop. What should I do ? > >>> > >> > >> Don't you just want > >> > >> entity NOTG is > >> generic (latency : time); > >> Port ( > >> Data_in : in STD_LOGIC); > >> end NOTG; > >> > >> architecture NOTG_arch of NOTG is > >> signal sig_in : STD_LOGIC :=3D '0'; > >> begin > >> > >> -- sig_in <=3D Data_in; -- <=3D=3D=3D=3D=3D=3D ?? > >> > >> NOTG0 : Entity work.NOTgate > >> generic map (latency =3D> latency) -- <=3D=3D=3D=3D=3D=3D=3D= you forgot this > >> port map( > >> Data_in =3D> sig_in, =09 > >> Data_out =3D> sig_in > >> ); > >> end NOTG_arch; > >> > >> ? > >> > >> I'm not sure what Data_in is for? > >> > >> Alan > >> > >> > >> --=20 > >> Alan Fitch > >=20 > > Thanks @Alan. I want an initial entry point into the circuit, hence "Da= ta_in" I guess this is wrong. Also how can I connect the NOT gate output to= it's input to form a loop? > >=20 >=20 > I don't know what you mean by "initial entry point". > I showed you how to connect the input to the output above, >=20 > regards > Alan >=20 >=20 > --=20 > Alan Fitch Hi @Alan thanks, I figured it out From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.216.52 with SMTP id f50mr25122647yhp.13.1428579725019; Thu, 09 Apr 2015 04:42:05 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr422163qgz.21.1428579724963; Thu, 09 Apr 2015 04:42:04 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no513081qgd.0!news-out.google.com!k20ni71qgd.0!nntp.google.com!z60no513078qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 04:42:04 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=193.49.106.57; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 193.49.106.57 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: 2 to 1 dual rail mux From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 11:42:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:8230 Hi all, I need to implement a 1 bit "2 to 1 dual rail mux". I successfully implemented 2 to 1 mux using bundled data protocol but it doesn't suit my purpose. Any help or link to tutorials that could help would be appreciated. Thanks From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.140.145.199 with SMTP id 190mr21317343qhr.2.1428611574159; Thu, 09 Apr 2015 13:32:54 -0700 (PDT) X-Received: by 10.140.43.7 with SMTP id d7mr458710qga.17.1428611574103; Thu, 09 Apr 2015 13:32:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no598277qgd.0!news-out.google.com!k20ni79qgd.0!nntp.google.com!z60no598275qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Apr 2015 13:32:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=82.216.67.64; posting-account=zRVTZgoAAABlbiMxuvOrcBbQ-QBF1YwY NNTP-Posting-Host: 82.216.67.64 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80c3f984-f079-4aaf-ac96-3a697c3e270f@googlegroups.com> Subject: Re: 2 to 1 dual rail mux From: Charles Effiong Injection-Date: Thu, 09 Apr 2015 20:32:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1562 X-Received-Body-CRC: 1380614350 Xref: mx02.eternal-september.org comp.lang.vhdl:8231 On Thursday, April 9, 2015 at 1:42:06 PM UTC+2, Charles Effiong wrote: > Hi all, > > I need to implement a 1 bit "2 to 1 dual rail mux". I successfully implemented 2 to 1 mux using bundled data protocol but it doesn't suit my purpose. > > Any help or link to tutorials that could help would be appreciated. > > Thanks Hi all, I figured out how to create an n bit dual rail mux. Contact me if you are interested in the implementation. Regards From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.182.27.139 with SMTP id t11mr2196706obg.38.1428733256115; Fri, 10 Apr 2015 23:20:56 -0700 (PDT) X-Received: by 10.140.100.136 with SMTP id s8mr66129qge.2.1428733255967; Fri, 10 Apr 2015 23:20:55 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2564928iga.0!news-out.google.com!k20ni104qgd.0!nntp.google.com!j5no830740qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Apr 2015 23:20:55 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c877065-28fb-40bc-b675-dc4417fcf139@googlegroups.com> Subject: Does anybody use systemc instead of VHDL From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 06:20:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8232 Hi I just wanted to know if people use systemc instead VHDL. Systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of C++ and SCV (for writing constraints). For big designs where RTL completion takes a lot of time, systemc can be used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM). Pini From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.42.58.69 with SMTP id g5mr9117431ich.14.1428760354489; Sat, 11 Apr 2015 06:52:34 -0700 (PDT) X-Received: by 10.140.29.119 with SMTP id a110mr80671qga.20.1428760353319; Sat, 11 Apr 2015 06:52:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2653429iga.0!news-out.google.com!a41ni58qgf.1!nntp.google.com!z60no891369qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 06:52:33 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: implementing list (is access record) From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 13:52:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8233 I would like to share this work example: "This examples demonstrates how to create lists in VHDL. This may be useful in implementing a FIFO quickly in a test-bench. I used list style coding to read an unknown number of bytes, during simulation at time 0, from a file. The data is to be later driven to a DUT." http://bknpk.ddns.net/my_web/SDIO/vhdl_is_access_lists.html From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.236.63.230 with SMTP id a66mr8296967yhd.51.1428760883530; Sat, 11 Apr 2015 07:01:23 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr84924qgi.26.1428760883484; Sat, 11 Apr 2015 07:01:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no891711qga.1!news-out.google.com!k20ni108qgd.0!nntp.google.com!j5no891707qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 07:01:23 -0700 (PDT) In-Reply-To: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <77cfdf08-418a-48f6-808d-c18bfc414305@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5e146ba4-c39a-4b40-b692-e6774fe18415@googlegroups.com> Subject: Re: c-language to VHDL converter From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 14:01:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1970 X-Received-Body-CRC: 1290841998 Xref: mx02.eternal-september.org comp.lang.vhdl:8234 On Wednesday, March 4, 2015 at 10:38:38 AM UTC+2, Sai Jaswanth wrote: > hi friends can any one help me in knowing how to convert the c-code to VH= DL directly by any software. (or) can we compile C-code in xilinx IDE? Have you considered systemc flow. Systemc is a synthesis-able sub-class of = C++. It can be used for cycle accurate simulation and there are commercial = synthesis tools. Systemc is also used to create pre-RTL model for simulati= on (loosely-timed or approximate timed) models. If your design is purely C++ you can use the free OSCI simulator. Its insta= llation is simple (on debian): http://bknpk.ddns.net/my_web/SystemC_MyFirst/sysc2_3_0Nscv_install.html It comes with SCV, which allows to write nice constraints: http://bknpk.ddns.net/my_web/SystemC_MyFirst/scv_cmp_err_pop_constraint.htm= l From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.66.237.140 with SMTP id vc12mr9579180pac.44.1428778169989; Sat, 11 Apr 2015 11:49:29 -0700 (PDT) X-Received: by 10.140.87.70 with SMTP id q64mr93573qgd.10.1428778169730; Sat, 11 Apr 2015 11:49:29 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2734484iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no940262qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:49:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <650b67e1-5ade-410d-a92d-da8ac431bbee@googlegroups.com> Subject: Re: Random Number Generator From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:49:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8235 On Thursday, July 10, 1997 at 10:00:00 AM UTC+3, Tim Holmes wrote: > Could anyone tell me how to create a "random" number generator in > VHDL. I imagine that the only method is to use a LFSR approach with > a seed. > > If there are any other ideas, then please let me know. > > Cheers. > > Tim > Hewlett Packard This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please visit me at http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.66.182.166 with SMTP id ef6mr9441699pac.42.1428778224601; Sat, 11 Apr 2015 11:50:24 -0700 (PDT) X-Received: by 10.140.101.148 with SMTP id u20mr93052qge.5.1428778224332; Sat, 11 Apr 2015 11:50:24 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4050317iga.0!news-out.google.com!k20ni111qgd.0!nntp.google.com!j5no939181qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:50:24 -0700 (PDT) In-Reply-To: <6q6ci5$9na$1@o.online.no> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <6q6ci5$9na$1@o.online.no> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: random integer generator From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:50:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8236 On Tuesday, August 4, 1998 at 10:00:00 AM UTC+3, Jon Eirik Sternang wrote: > Does anyone have a random generator that returns > integers between [a,b] (i.e. returns a integer > value between a and b) > > thanks > > Jon Eirik This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please check http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Tue Dec 29 16:43:48 2015 X-Received: by 10.66.101.100 with SMTP id ff4mr9522900pab.24.1428778272832; Sat, 11 Apr 2015 11:51:12 -0700 (PDT) X-Received: by 10.140.108.229 with SMTP id j92mr95326qgf.27.1428778272574; Sat, 11 Apr 2015 11:51:12 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4050693iga.0!news-out.google.com!k20ni111qgd.0!nntp.google.com!j5no939239qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:51:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <88cfa1bb-4707-482e-90d6-26960aafc088@googlegroups.com> Subject: Re: Random Number Generator in VHDL From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:51:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8237 On Saturday, January 20, 1996 at 10:00:00 AM UTC+2, Lynn West wrote: > Is there a simple way to generate random numbers (preferably both > itegers and bit_vector or std_logic_vector type) in VHDL. I seem to > vaguely remember such but cannot find it in my books. (I have not yet > figured out how to master access to the FAQ for this newsgroup, so > cannot look there). > > Obvously something could be conjured up with a set of differently-timed > clocks, but I am hoping for something simpler than that. > > Thanks, > > Lynn West This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. Please read also http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.182.246.67 with SMTP id xu3mr9873475obc.18.1428778366637; Sat, 11 Apr 2015 11:52:46 -0700 (PDT) X-Received: by 10.140.92.51 with SMTP id a48mr91834qge.16.1428778366516; Sat, 11 Apr 2015 11:52:46 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no2735687iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no940871qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:52:46 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ecad407-f267-4d42-853e-03978c9a6c6f@googlegroups.com> Subject: Re: random number generator function From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:52:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8238 On Thursday, November 22, 2007 at 7:34:59 AM UTC+2, bb wrote: > Hi, > > I am creating a finite state machine, and within one of the states I > need to obtrain a random number by calling a function. > > random_value <= rand_val; > > I am new to VHDL. > > Thanks, This page explains how I randomize the delay between packet injections to the DUT. To generate random numbers from within the VHDL test-bench, I used a random function in the following way. ... library my_lib; use my_lib.my_package.all; ... signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000"; signal rand_packet_delayi: integer; ... rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay); --write(my_line, rand_packet_delay'path_name); --write(my_line, string'(" ")); --hwrite(my_line, rand_packet_delay); --write(my_line, string'(" ")); --write(my_line, now); --writeline(output, my_line); --packet send ended if(unsigned(rand_packet_delay) > 3) then rand_packet_delayi <= conv_integer(rand_packet_delay); else rand_packet_delayi <= conv_integer(rand_packet_delay) + 3; end if; for j in 1 to rand_packet_delayi loop wait until rx_clk'event and rx_clk = '1'; end loop; Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. This is discussed at http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.42.154.133 with SMTP id q5mr11305805icw.4.1428778476440; Sat, 11 Apr 2015 11:54:36 -0700 (PDT) X-Received: by 10.140.83.165 with SMTP id j34mr93192qgd.23.1428778476314; Sat, 11 Apr 2015 11:54:36 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4052121iga.0!news-out.google.com!a41ni65qgf.1!nntp.google.com!z60no941092qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 11 Apr 2015 11:54:36 -0700 (PDT) In-Reply-To: <3A1BC2F0.DE7A9566@imms.de> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.180.168.226; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.180.168.226 References: <3A1BC2F0.DE7A9566@imms.de> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <539713fb-23fc-4290-b9d1-5365fc2e963f@googlegroups.com> Subject: Re: Getting the current instance name From: bknpk@hotmail.com Injection-Date: Sat, 11 Apr 2015 18:54:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8239 On Wednesday, November 22, 2000 at 10:00:00 AM UTC+2, Kai Troester wrote: > Hi > > In a package I have a procedure which should print the time, the > instance and a message (I don't want to use the assert statements). My > problem is getting the name of the instance which is calling this > procedure without passing an additional parameter beside the message. > For time one can use 'now', but for the instance ? Does somebody have a > clue ? > > Thanx, Kai > -- > ----- Dipl. Ing. Kai Troester ------------------------------------- > Design Engineer -- System Design > IMMS - Institute of microelectronics and mechatronic systems > Langewiesener Strasse 22, 98693 Ilmenau, Germany > Tel: +49(3677)6783-52 | Fax: +49(3677)6783-38 > mailto:kai.troester@imms.de | http://www.imms.de/~troester > ------------------------------------------------------------------- While it is simple in VERILOG (%m in the display system function), in VHDL a bit more code writing is required. $display("dbg instance name %m at %d", $time); An example how to print an instance name in systemc is also available on this site. The importance of such debug information is when a design contains many instances of the very same component. First text IO library has to be called and line variable should be declared. Please refer to print example to see details. Next you have to select between two options: One is: instance name only in debug string and the other option gives more information such as entry and architecture names. Syntax example is given below: if(newByte = '1') then write (my_line, string'("path ")); write (my_line, clk'path_name);--short write (my_line, string'(" ")); writeline(output, my_line); write (my_line, string'("inst ")); write (my_line, clk'instance_name);--long write (my_line, string'(" ")); writeline(output, my_line); Please see a detailed explication at http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.50.20.135 with SMTP id n7mr13211630ige.8.1428871899493; Sun, 12 Apr 2015 13:51:39 -0700 (PDT) X-Received: by 10.50.4.34 with SMTP id h2mr136512igh.7.1428871899481; Sun, 12 Apr 2015 13:51:39 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!l13no4507766iga.0!news-out.google.com!n7ni5964igk.0!nntp.google.com!l13no4507764iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Apr 2015 13:51:38 -0700 (PDT) In-Reply-To: <3a24f454.12426254@news.dial.pipex.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.61.225.236; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.61.225.236 References: <3A1BC2F0.DE7A9566@imms.de> <3a1e49db.8965550@news.dial.pipex.com> <8vohtg$s7o$1@nnrp1.deja.com> <900td0$5dv$1@nnrp1.deja.com> <3a24f454.12426254@news.dial.pipex.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Getting the current instance name From: diogratia@gmail.com Injection-Date: Sun, 12 Apr 2015 20:51:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8240 On Wednesday, November 29, 2000 at 9:00:00 PM UTC+13, e...@riverside-machin= es.com.nospam wrote: > >Srini wrote: > >> > >> I am not sure if I understand the reasoning well here. I thought it > >> would be possible to "freeze" the "instance name" during Elaboration > >> (When the complete design hierearchy is known). So why should it be > >> known during Compilation itself (as an example Generics can be changed > >> during elaboration - isn't it?) >=20 > This was just my guess as to why it's implemented this way. In > general, you can't determine a complete hierarchical path to a named > item until runtime. Consider that subprograms are only elaborated at > runtime. It could be a real headache for a simulator to work out a > path to an item in a recursive procedure, for example, at runtime. >=20 > Evan A procedure call is a statement. A function call is an expression. Subprogr= am calls collectively use dynamic elaboration (Today we push the parameters= on a calling stack leaving space for a return value, and pop the whole mes= s when the call is complete and any return value has been evaluated). The only way to get the calling location is through a passed parameter on t= he calling stack.=20 There is a proposal to pass the calling_path in a hidden fashion on the cal= l stack (as an attribute which is a basic operation). That would require a= significant amount of overhead putting some potentially long string on the= calling stack impacting performance tremendously. =20 You could abstract that away to making a call a pseudo object, where you on= ly pass an index that tells you were to find it. Not sure if a 32 bit value= would be large enough. Somewhere there'd be a table of instance paths, pat= h names, calling paths and the calling overhead for the index would still b= e enough to significantly impact performance when all operators are functio= ns and all other operations of a type are basic operations. You could exemp= t predefined operators, but VHDL would still pay a heavy price because of i= t's strong typing. The value proposition doesn't appear to be there leaving user space solutio= ns. The alternative would be either to bite the bullet and pass the path as a p= arameter or restructure to use the equivalent of a POSIX logging call allow= ing the calling location to report the path. For the former you could use d= efault values allowing the parameters to only be passed for debugging. The = default values would be a zero length string for the path and a possibly a = boolean for determining whether or not report the path. Detecting error conditions is tough for function calls, strong typing doesn= 't allow in band error reporting, requiring either a returned record or mir= ror functions returning an error condition separately. The idea here is to = determine when the calling location reports it's instance path. What this boils down to is that VHDL isn't like other languages. It serves = for hardware descriptions that can be readily formally proven and that reli= es on strong typing. Despite rumors to the contrary it isn't a general purp= ose programming language, you can't bend it to other purposes readily. For = instance you couldn't implement a VHDL simulator in VHDL without describing= the simulation cycle in terms of hardware. The good news is you could put = it in an FPGA. From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.227.131 with SMTP id d3mr4880201yhq.41.1429372261014; Sat, 18 Apr 2015 08:51:01 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr108817qgi.26.1429372260962; Sat, 18 Apr 2015 08:51:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed3a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no2462085qgd.0!news-out.google.com!a41ni744qgf.1!nntp.google.com!z60no2462083qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 18 Apr 2015 08:51:00 -0700 (PDT) In-Reply-To: <0c4ad78c-03b3-4dcd-ae8f-fff345880be1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2001:7a8:1:121:d6ae:52ff:feb9:69e6; posting-account=eZ2POwoAAAAkkSW9RBzdSdr76Z-qmY_N NNTP-Posting-Host: 2001:7a8:1:121:d6ae:52ff:feb9:69e6 References: <0c4ad78c-03b3-4dcd-ae8f-fff345880be1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PADRE E FIGLIO DI PUTTANA, PIERLUIGI BOSCHI DI AREZZO E BANCA ETRURIA, SU INPUT DI BATTONA BERLUSCONICCHIA MARIA ELENA BOSCHI, HA PASSATO INSIDER SU BANCHE POPOLARI A VERME DAVIDE SERRA DI ALGEBRIS E TWITTER ED HA BECCATO STECCA DI 1.000.000 From: Memoche Sedici Injection-Date: Sat, 18 Apr 2015 15:51:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 466 Xref: mx02.eternal-september.org comp.lang.vhdl:8241 SCHIFOSO BASTARDO NEOPIDUISTA PIER LUIGI BOSCHI BANCA ETRURIA AREZZO (OLTRE= CHE MEGALAVA CASH MAFIOSO) SU INPUT DI RATTONI BERLUSCORROTTI MARIA ELENA = BOSCHI E MATTEO RENZI, HA PASSATO INSIDER SU BANCHE POPOLARI A FASCIOPORCO = DAVIDE SERRA ALGEBRIS E.. =20 A META' FEBBRAIO 2014, IL COLERICISSIMO TOPO DI FOGNA DAVIDE SERRA DI ALGEB= RIS E TWITTER, HA, NON RICEVUTO, MA LUI STESSO ARCHITETTATO ( COSA MOLTISSI= MO PIU=B4 GRAVE) L'INSIDER TRADING SULLE BANCHE POPOLARI BECCATO DAL BASTAR= DO DITTATORE BERLUS-CO-RROTTISSIMO MATTEO RENZI ( UNITO ALLA BAGASCIONA BER= LUS-CO-RROTTISSIMA MARIA ELENA BOSCHI, ED IL, DI QUEST=B4ULTIMA, DELINQUENT= E PADRE, NOTO MEGA RICICLA SOLDI MAFIOSI: PIER LUIGI BOSCHI DI AREZZO E BAN= CA ETRURIA). ED HA PURE RAGLIATO CHE COMPRA BANCHE POPOLARI " BEN" DAL MARZ= O 2014. SPUTTANANDOSI ANCORA DI PIU', COME UN IMBECILLE, COME UN PEDERASTA = SODOMIZZA BAMBINI IN TANZANIA, COME UN MEGA COCAINOMANE, QUALE DA SEMPRE, S= TO LERCISSIMO COLLETTO DI DAVIDE SERRA, E' E STRA E'. NON PER NIENTE... IL = SUO CESSO STECCATISSIMO MATTEO RENZI (CHE VIA "SS", SPINTA E STECCHE DI SIL= VIO BERLUSCONI E DAVIDE SERRA, HA SCIPPATO SEGRETERIA PD E PALAZZO CHIGI), = HA RICEVUTO DA STO PORCO HITLERIANO DI ALGEBRIS, INDICAZIONI, ANZI, ASSOLUT= ISSIMI ORDINI, SU COME RIFORMARE LE POPOLARI. SUBITO: NEL FEBBRAIO 2014. "O= VVISSIMAMENTE", DETTO IMMENSO PAPPA TANGENTI DI MATTEO RENZI HA OBBEDITO AG= LI ORDINI ( IMMENSO PAPPA TANGENTI DI MATTEO RENZI, FIGLIO DI MOSTRUOSISSIM= AMENTE BASTARDO, LADRO, TRUFFATORE TIZIANO RENZI, NOTO IN TUTTA TOSCANA COM= E " IL BANCAROTTIERE FRAUDOLENTO DI SATANA"). E PER QUESTO, STO TOPASTRO DI= FOGNA NAZISTA, ANZI, STO TOPASTRO DI FOG-NA-ZISTA DI DAVIDE SERRA DI TWIT= TER ED ALGEBRIS, SI E' MESSO A COMPRARE BANCHE POPOLARI, OHIBO', GUARDA CAS= O, DAL MARZO 2014. UN MESE DOPO L'ARRIVO FASCIOCAMORRISTA DI MATTEO RENZI D= I PALAZZO CHIGI (ULLALA' CHE COINCIDENZA, ULLALA'). INSIDER ARCHITETTATO DA= L NUOVO BERNARD MADOFF, OSSIA DAVIDE SERRA, IN PIENISSIMO, E'!!! TRATTASI = DI MANDRIA DI PORCI FASCIOCAMORRISTI, TIPO, ANCHE, NOTO AVANZO DI GALERA PA= OLO BARRAI (DI CRIMINALISSIMA WMO, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOC= RATE 26 MILANO E CRIMINALISSIMA BLOG MERCATO "MERDATO"LIBERO), CHE SI FINGO= NO DEL PD, X... DISTRUGGERLO, INFILTRARLO A MORTE, RENDERLO DIARREA BERLUSC= ONICCHIA! VOGLIAMO UNA ACCESISSIMA E VINCENTISSIMA REVOLUCIOOOOOON! VOGLIAM= O IL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, FALLITO ED IN GALERA= ! SUBITO! PLS, DOTTOR SERGIO MATTARELLA, CI DIA UNA MANO! IN ONORE A SUO FR= ATELLO UCCISO DA COSA NOSTRA ( COSA NOSTRA CHE QUANDO SI METTE LA FASCISTIS= SIMA CRAVATTA DOLCE E GABBANA, SIGNIFICA SILVIO BERLUSCONI, DAVIDE SERRA E = PAOLO BARRAI, GLIELO POSSO, NON SOLO ASSICURARE, MA ANCHE PROVARE). IN ONOR= E AD ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO, FATTI SPAPPOLARE, SICURISS= IMAMENTE, DA SILVIO BERLUSCONI, VIA, A SUA VOLTA, BERLUSCONIANISSIMA MAFIA!= ED OLTRE A VOLER SILVIO BERLUSCONI FALLITO ED IN GALERA, VOGLIAMO VEDERE I= L SUO PICCIOTTO INCRAVATTATO, IL FACCENDIERE DI BERLUSCONAZISTI, PADANAZIST= I, E CRIMINALITA' ORGANIZZATE DI MEZZO MONDO, PAOLO BARRAI DI MALAVITOSA WM= O, PURE, IN GALERA! VOGLIAMO IL NUOVO GIANCARLO LANDE, IL NUOVO BERNARD MAD= OFF, IL NUOVO MICHELE SINDONA, VERME CRIMINALISSIMO DAVIDE SERRA DI TWITTER= ED ALGEBRIS, FALLITO, E PER LO MENO, PER QUALCHE MESE, IN GALERA! CHE SIA = ETICISSSIMA E VINCENTISSIMA REVOLUCIOOOOON!=20 COME DA OTTIMO SITO INFORMARE X RESISTERE:=20 http://www.informarexresistere.fr/2015/01/27/qualcuno-sapeva-in-anticipo-ch= e-il-governo-avrebbe-varato-un-provvedimento-sulle-banche-popolari-enormi-s= peculazioni/=20 =20 COME DA CORRIERE DELLA SERA, DI, OTTIMAMENTE, ANTIRENZUSCONIANO FERRUCCI= O DE BORTOLI, UOMO DA NON TOCCARE E A TUTTI I COSTI:=20 http://www.corriere.it/economia/15_gennaio_24/quei-movimenti-un-po-sospetti= -popolari-f59ffb1c-a3a5-11e4-808e-442fa7f91611.shtml=20 =20 Acquisti consistenti prima della riforma che ha abolito il voto capitario. = La famiglia Boschi ha sicurissimamente passato insider trading a Londra, tr= amite noto ladro, truffatore, nazifascista, immensamente ricicla soldi mafi= osi, che affatto va' in Tanzania a fare del bene, in quanto vi va' a ricicl= are cash di (sua) LL Lega Ladrona, come per suoi gusti sessuali di tipo dep= ravatissimo: avanzo di galera Davide Serra di Algebris e Twitter ( che anzi= , di stra certo, ha architettato la suddetta "mafia sulle Banche Popolari",= gia=B4dal Febbraio 2014, dall=B4inizio della topaia a Palazzo Chigi, chiam= ata, non Governo Renzi, ma Governo Renzusconi). Ci chiediamo ora: dove pren= deranno, le mazzette, i vermi nazifascisti Pier Luigi Boschi di Banca Etrur= ia e sua zoccolona ( di fatto) Berlusconicchia Maria Elena Boschi ( bastard= a puttanazista che vuole sgozzare la giustizia via estremissimamente ingius= ta salvaberlusconi http://www.blitzquotidiano.it/rassegna-stampa/libero-ren= zi-per-fare-la-pace-offre-la-salva-berlusconi-che-fara-mattarella-2090491/.= ... che qui, non per niente, slingua=20 http://www.corriere.it/methode_image/2014/08/08/Politica/Foto%20Politica%20= -%20Trattate/6ebdfe07bdd8cb1fe88af8343f8a5b1c-012-kXsC-U43030145012273wcB-5= 93x443@Corriere-Web-Sezioni.jpg?v=3D20140808175213=20 un topo di fogna corrotto, ndranghetista, fascista, estortore di soldi alla= Banca Popolare di Lodi .. pezzo di merda criminalissimo Paolo Romani:=20 http://www.repubblica.it/2005/l/sezioni/economia/banche21/ipolitici/ipoliti= ci.html )?=20 A) Alle Bahamas=20 B) Alle Bermuda=20 C) A Panama=20 D) Ad Hong Kong=20 E) A Singapore=20 F) Alle Mauritius ( "roba" tipo Svizzera e' da anni 70, 80: stile nazim= afioso pedofilo Silvio Berlusconi e suo B-o-ttino Craxi.. dai.. please)=20 Lauti premi a chi azzecca per primo!!!=20 ---=20 BRAVO, BRAVO, DAVVERO BRAVISSIMO ELIO LANNUTTI A QUERELARE STO VERME BERLU= S-CORROTTTISSIMO DI MATTEO RENZI:=20 http://www.ilfattoquotidiano.it/2015/01/21/denuncia-per-renzi/1357263/=20 CHE SBEFFEGGIA PM PER BENE, EROICI, SALVA NAZIONE ( SPESSO SPAPPOLATI, = COME IL NAZIMAFIOSO PEDOFILO STRAGISTA SILVIO BERLUSCONI FECE FARE CON GLI = ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO.. SILVIO BERLUSCONI, PROPRIO IL = POR-CO-RRUTTORE MAXIMO DI MATTEO RENZI... ULLALA=B4CHE COINCIDENZINA, ULLAL= A=B4). TIPO QUELLI DI PALERMO, BARI, MILANO, NAPOLI, DICENDO, ANZI, RAGLIAN= DO LORO: "'OOOO OO CHE PAURA, MI FANNO, OO OO"=20 http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-pau= ra-sciopero-sindacati-polizia-illegale/295911/=20 CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE = FRA POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO = RENZI!=20 https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-di-= me-il-2-febbraio-carmelo-lopapa/=20 "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERL= USCONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA= BLOCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGL= I ULTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNE= R, FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVR= EBBERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU MI ASSICURI= LA NOCCIOLINA DI BEN 50 MILIONI DI EURO DI SCONTO, VIA MILLE-STECCATISSIME= -PROROGHE" http://www.affaritaliani.it/economia/milleproroghe-sfratti-frequenze-tv1702= 15.html=20 "IO TI VOTO LE RIFORME DI AUGUSTO PINOCHET CHE VUOI IMPORRE, TU METTI AL QU= IRINALE UN FANTOCCIO DI MIA PROPRIETA', CHE COMPRO QUANDO VOGLIO QUALE GIUL= IANO AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... O MEGLIO ANCORA, SE PARL= IAMO DI MIEI FASCIOBAMBOCCI ALLA PIERFERDINANDO CASINI O GIANNI LETTA... TU= TTI MIEI PUPAZZI CHE MI HAN GIA' GARANTITO CHE CON SEI EURO E MEZZO CASH, M= I FIRMEREBBERO TUTTE LE GRAZIE CHE VOGLIO IN NOME DELLA MIA.... PACIFICAZIO= NE ALLA VASELLINA... E ... SPECIALMENTE ...GIUSTO PER ANDARE SUL SICURO....= MI FAI ANCHE E SUBITO UNA NORMINA DECAPITANTE NOIOSISSIMI CONCETTI COME DE= MOCRAZIA E GIUSTIZIA CHE IMPONGA IL MIO TORNARE IN POLITICA, COSI' CHE POSS= A FOTTERE IL POPOLO CIUCCIO, LE LEGGI, DOZZINE DI (GRANDISSIMI) MAGISTRATI = COME ILDA BOCASSINI, EDMONDO BRUTI LIBERATI, NINO DI MATTEO, ROBERTO SCARPI= NATO, FABIO DE PASQUALE, HENRY WOODCOCK, PASQUALE DRAGO, ATTRAVERSO LA ( BA= STARDAMENTE VIGLIACCHISSIMA) IMMUNITA' EVITA GALERA, CHE MI RI RITROVEREI"!= =20 http://www.ilfattoquotidiano.it/2015/01/18/salva-berlusconi-alessandro-pace= -manina-renzi-reato-falso/1349562/=20 http://www.ilfattoquotidiano.it/2015/01/08/salva-berlusconi-mucchetti-renzi= -venga-senato-spiegare-successo/1322595/=20 http://www.ilfattoquotidiano.it/2015/01/06/salva-berlusconi-coppi-ammette-q= uella-norma-segnale-per-quirinale/1318110/=20 IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERLUSCON= IANISSIME) CHE STAI APPRONTANDO, TU MI FAI PAPPARE RAI WAY E TELECOM, COSI= =B4CHE POSSA CONTROLLARE CHIUNQUE NON MI LECCHI IL DI DIETRO, DISTRUGGENDOG= LI LA VITA ( VEDI DISARTICOLAZIONI CON MEZZI TRAMAUTICI, ALIAS, SPESSO, ASS= ASSINI=20 http://comuni.it/servizi/forumbb/viewtopic.php?p=3D539677=20 http://www.antimafiaduemila.com/200712201537/terzo-millennio/terzo-millenni= o-anno-vid-numero-5-2006-nd51/pezzi-eversivi-di-uno-stato-a-pezzi.html=20 http://freeforumzone.leonardo.it/lofi/SERVIZIETTI-POCO-SEGRETI-MARCO-TRAVAG= LIO-/D5676425.html )=20 E SPECIALMENTE, POSSA CONTROLLARE TUTTE LE INTERCETTAZIONI AMBIENTALI E TEL= EFONICHE DEI PM, E QUINDI, SGOZZARE, STILE BERLUSCONIANISSIME ISIS ED AL QA= EDA, LA GIUSTIZIA. INFATTI, GIA=B4AI TEMPI, I PORCORROTTI GIULIANO TAVAROLI= ED EMANUELE CIPRIANI, STUPRAVANO A MORTE, LA DEMOCRAZIA, PER ME, SILVIO BE= RLUSCONI, PIU=B4CHE PER MARCO TRONCHETTI PROVERA. CHI CONTROLLA LE TELEFONA= TE, E=B4DA SEMPRE, IL NUOVO DUCE, E IO, SILVIO BERLUSCONI, LO SONO, NEL MIO= PAESE, ED ORMAI, DA QUASI MEZZO SECOLO"!!!=20 ECCO DOVE CI PORTANO BASTARDI LAVA CASH MAFIOSO A GO GO COME I MALAVITOSINC= RAVATTATI DAVIDE SERRA DI ALGEBRIS E TWITTER INSIEME AL RENATO VALLANZASCA = UNITO AD UGO FANTOZZI DELLA FINANZA, NOTO AVANZO DI GALERA, GIA=B4VARIE VOL= TE IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.6.1965, DI CRIMINALISSIMO W= MO, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MILANO E CRIMINALISSIMO= BLOG MERCATO "MERDATO" LIBERO ( DUE VERMI REPELLENTI CHE RICICLANO ALL'EST= ERO VAGONI DI SOLDI DI COSA NOSTRA, CAMORRA, NDRANGHETA O LADRATI SE NON PU= RE FRUTTO DI MEGA MAZZETTE IN DIREZIONE LL LEGA LADRONA ED EX PDL POPOLO DI= LADRONI; IN CONGIUNZIONE CON BANCHIERI DELINQUENTISSIMI, SPESSO PURE MANDA= NTI DI OMICIDI O "SUICIDATE", COME FATTO CON DAVID ROSSI DI MONTE PASCHI, Q= UALI GLI ASSASSINI ENNIO DORIS E MASSIMO DORIS DI BANCA MEDIOLANUM; O QUALE= "O MASSONE CAMORRISTA" GIUSEPPE SABATO DI BANCA ESPERIA E GRAN LOGGIA MASS= ONICA ITALIANA=20 http://www.gruppoesperia.it/chi-siamo/giuseppe-sabato.html=20 https://books.google.it/books?id=3DB1mEj0GtktIC&pg=3DPT304&lpg=3DPT304&dq= =3DGIUSEPPE+SABATO+LICIO+GELLI&source=3Dbl&ots=3DGqtu0KYRmD&sig=3Dd2TOz9sZD= Y6563zIPxwnNYcbxb4&hl=3Dit&sa=3DX&ei=3DI-i_VOOsBMLlUonCgZgI&ved=3D0CFMQ6AEw= CA#v=3Donepage&q=3DGIUSEPPE%20SABATO%20LICIO%20GELLI&f=3Dfalse=20 TUTTI DEL GRUPPO MA-F-INIVEST DI " STEFANO BONTATE, MARCELLO DELL'UTRI,= TOTO RIINA, LICIO GELLI, BERNARDO PROVENZANO E SILVIO BERLUSCONI: " OO CHE= CASO, OO")! E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STEC= CATISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE = MICHELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER = PROTEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROT= TIERE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA = SODOMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOL= O CIUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE CON LATTE A= LLA BOCCA: MATTEO RENZI!=20 http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_ren= zie.html=20 https://www.youtube.com/watch?v=3DA7Ngp6JrK9A=20 http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-paga= ti-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375=20 CHE VIA ASSASSINE MASSONERIE NAZIFASCISTE, VER E PROPRIE MASSONAZISTERIE,= =20 FA DA TRAMITE FRA LO STRAGISTA NAZIMAFIOSO PEDOFILO SILVIO BERLUSCONI, LA F= ASCIOLESBICA MARINA BERLUSCONI E SUO FIGLIO BERLUS-CO-RROTTISSIMO MATTEO RE= NZI, PER FAR SI CHE BERLUSCONIA WOULD NEVER DIE!=20 http://www.dagospia.com/rubrica-3/politica/mascherina-ti-conosco-dopo-aver-= fatto-contro-pelu-renzi-76510.htm=20 http://www.laretenonperdona.it/2013/06/16/cause-e-fallimenti-aziendali-i-da= nni-di-papa-renzi/=20 http://www.huffingtonpost.it/news/renzi-boy-scout-licio-gelli/=20 http://www.ilfattoquotidiano.it/2014/12/21/tiziano-renzi-i-pm-interrogano-p= adre-premier-indagato-per-bancarotta/1285579/=20 http://micheledisalvo.com/tutti-gli-amici-di-matteo-renzi.html=20 http://www.affaritaliani.it/cronache/renzi-e-i-legami-con-la-massoneria0210= 14.html=20 VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE, QU= ELLO ANTI MAFIA NAZIFASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E = SEL! A FARE IL SUO VERO LAVORO, OSSIA LA ZOCCOLA DI STRADA, STA BATTONA HIT= LERIANA, CHE SI CREDE MODELLA MA E' CESSO STRA COLMO DI CELLULITE, DI MARIA= ELENA BOSCHI: http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-bikini-rosa-in-= spiaggia-a-marina-di-pietrasanta-581617_tn.jpg FIGLIA DI ALTRO VERME CRIMI= NALISSIMO: MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA ETRURIA (DOPO= AVER PASSATO TUTTA UNA VITA A TRAFFICARE CON COOP VICINISSIME A MAFIA, CAM= ORRA E NDRANGHETA, NON PER NIENTE, STILE "RENZUSCONIANISSIMI" SALVATORE BUZ= ZI E MASSIMO CARMINATI)! PS SEMPRE VINCENTISSIMI I GENI BORSISTICI GEORGE S= OROS E MICHELE NISTA A PUNTARE SULLA SPAGNA. PARREBBE CHE DOPO AVER SAPUTO = CHE IL MIGLIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NISTA, VEDA NON = MALE LA SPAGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO, MANCO FOSSERO= NOCCIOLINE, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI BANCO SANTAND= ER. NON SARA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON LO E' ALCUN P= AESE DEL PIANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE NON MANCANO (= MA SONO AL MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA DI RENZUSCONI= A)! PERO', NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI VI E' DEMOCRAZI= A VERA. SIA AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMETTENTISSIMO PAB= LO IGLESIAS DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRONA DI MADRID, = VERMI STRAGISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERLUSCONI, CHE SI= FAN LE LEGGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLTRE CHE PER SGO= ZZARE A MORTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. E QUESTO, O IN PROPRIO, = O COMPRANDOSI RAGAZZINI CORROTTISSIMI CHIAMANTISI MATTEO, COME MATTEO RENZI= (OGGI). O IL NUOVO ADOLF HITLER: MATTEO SALVINI (DOMANI). MENTRE L'UNICO P= ADRONE, L'UNICO VERO BOSS DEL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSC= ONI, UN ALTRO MATTEO, MATTEO MESSINA DENARO, SORRIDE E DICE " BRAVO MIO PRE= STANOME BEDDU SILVIO BERLUSCONI, HAI TRASFORMATO L'ITALIA IN RENZUSCONIA, C= HE IN REALTA' SEMPRE BERLUSCONIA E', AAAAAAA... COME PIACE A MMMIA, AAAA...= . E' TUTTO UNA COSA NOSTRA, SILVIUZZEDDU BEDDU .. CONTINUA COSI' CHE TI TRO= VIAMO QUALCHE ALTRA BEDDA PROSTITUTA DI 12-14 ANNI PELLU TEMPU LIBERO, AAAA= A.... QUESTA VOLTA CAMBIAMO, AAAA... TE LA TROVIAMO FILIPPINA E LA FACCIAMO= PASSARE PER LA NIPOTE DEL RE DELLA THAILANDIA, BHUMIBOL ADULYADEJ, IL RE P= IU' RICCO DEL MONDO ... CHE SPESSO E VOLENTIERI "ABOLISCE UFFICIALISSIMAMEN= TE LA DEMOCRAZIA"... SI... SILVIUZZEDDU BEDDU DA COSA NOSTRA, TI TROVIAMO U= NA BAMBINA FILIPPINA DI 12 ANNI DA SBAVARE E TOCCARE QUANTO VUOI... E LA FA= CCIAMO PASSARE PER LA NIPOTE THAILANDESE DI BHUMIBOL ADULYADEJ, AAAA.... CO= SI' VEDRAI CHE QUANDO TELEFONI, PREOCCUPATISSIMO, DA PARIGI ( TANTO, FRA PO= CO, NELLA TUA DITTATURA DELLE BANANAS DI RENZUSCONIA, SUBITO, IL PASSAPORTO= , TI RIDARANNO), I POLIZIOTTI O QUESTORI, SOLO E SEMPRE LA TUA VOLONTA', FA= RANNO, AAA"!!! "... ANZI, ANCORA, AAA.. SCUSA, SILVIUZZEDDU BEDDUZZU, MA AN= CHE SE TI CITASSERO IN GIUDIZIO, IN CASSAZIONE, POI, AVREMMO GIUDICI CORROT= TISSIMI E MASSONI COME NOI, STILE PREZZOLATISSIMO GIUDICE NICOLA MILO ( NON= PER NIENTE, NOSTRO NOTO PORCORROTTO CHE GIA' USAMMO PER SGOZZARE LA INCHIE= STA WHY NOT) CHE SEMPRE TI ASSOLVEREBBERO, AA E STRA AAAAA"!!!=20 PS.=20 MA SCUSATE, PLS: CHE ALTRO VI ASPETTERESTE CON UN LURIDO FASCIOMAFIOSO PREZ= ZOLATISSIMO COME ANGELINO ALFANO AL VIMINALE??? CHE BACIAVA ANCHE SULLA BOC= CA, SANGUINARI KILLER DI COSA NOSTRA COME CROCE NAPOLI https://www.facebook= .com/notes/informare-controinformando-news/quando-angelino-alfano-baciava-i= l-boss-mafioso-croce-napoli/177333725657619STO VERME NAZINDRANGHETISTA DI A= NGELINO ALFANO RICEVE CENTINAIA DI MIGLIAIA DI EURO DAI DUE SOCI INDISSOLUB= ILI DI COSA NOSTRA.. QUANDO IN CRAVATTA: MATTEO MESSINA DENARO E SILVIO BER= LUSCONI. VOLETE MAI CHE SI AUTO IMPOVERISCA, METTENDOLI IN CARCERE COME STR= A DOVREBBE FARE... ANZI, COME AVREBBE GIA' STRA DOVUTO FARE E DA ANNI? D'AL= TRONDE, AVERE UNO SCARAFAGGIO PROTEGGENTE TUTTE LE MALAVITE DELLO STIVALE, = COME ANGELINO ALFANO, AL VIMINALE, E' PARI PARI A METTERE ARSENIO LUPIN E G= AMBADILEGNO COME CHIEFS DELLA SECURITY DELLA CASSAFORTE DI BANKITALIA... E'= COME AVERE IL MOSTRO DI MARCINELLE INSIEME ALL'ACCLARATO PEDOFILO SILVIO B= ERLUSCONI.. COME ORGANIZZATORI DI UN PARTY AL BUIO, IN BIKINI, E PER BAMBIN= E DI 12 ANNI... E' COME CERCARE FOCHE ALL'HABANA O GHEPARDI NELLE TERRE ART= ICHE!!! IDIOZIE AUTODISTRUTTIVISSIME CHE SPIEGANO IN STRA PIENO PERCHE' IL = PAESE DI MIA MADRE, EX REPUBBLICA ITALIANA, DAL 1994, PUZZONA DITTATURA FAS= CIOCAMORRISTA DI BERLUSCONIA, PRIMA, RENZUSCONIA, ORA, CONTINUI CON I SUOI= INSTOPPABILI DECLINI. ED' E' SUPERATA IN TUTTO, NEL MONDO, DA EX CANI E PO= RCI. SOON BACK!!! ANTONY WHITEHOUSE. ANTI NAZIMAFIA BERLUSCONIANA. LONDON. = UK. El martes, 3 de febrero de 2015, 17:17:55 (UTC+1), MICHELE RAGAZZI. ODEY GI= ANO. escribi=F3: > PADRE E FIGLIO DI PUTTANA, PIERLUIGI BOSCHI DI AREZZO E BANCA ETRURIA, SU= INPUT DI BATTONA BERLUSCONICCHIA MARIA ELENA BOSCHI, HA PASSATO INSIDER SU= BANCHE POPOLARI A VERME DAVIDE SERRA DI ALGEBRIS E TWITTER ED HA BECCATO = STECCA DI 1.000.000 EURO A? > =20 > STO BASTARDO NAZINDRANGHETISTA DI DAVIDE SERRA DI ALGEBRIS E TWITTER HA R= ICEVUTO L'INSIDER TRADING SULLE BANCHE POPOLARI DA NOTO LAVA SOLDI MAFIOSI = PIER LUIGI BOSCHI DI AREZZO E BANCA ETRURIA. HA PURE RAGLIATO CHE COMPRA BA= NCHE POPOLARI DAL MARZO 2014. SPUTTANANDOSI ANCORA DI PIU', COME UN IMBECIL= LE, PEDERASTA SODOMIZZA BAMBINI E MEGA COCAINOMANE, QUALE DA SEMPRE E'. IL = SUO POR-CO-RROTTISSIMO MATTEO RENZI (CHE VIA "SS", SPINTA E STECCHE DI SILV= IO BERLUSCONI, HA SCIPPATO SEGRETERIA PD E PALAZZO CHIGI, NEL SECONDO CASO = COL FEBBRAIO 2014), GLI HA PASSATO, ATTRAVERSO "A ZOCCOLONA BERLUSCONICCHIA= , STECCATISSIMA E CELLULITOSA" MARIA ELENA BOSCHI http://www.dagospia.com/= img/foto/08-2014/maria-elena-boschi-bikini-rosa-in-spiaggia-a-marina-di-pie= trasanta-581617_tn.jpg E IL VERME MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCH= I DI BANCA ETRURIA, L'INSIDER SULLE BANCHE POPOLARI. E PER QUESTO, STO ESCR= EMENTO HITLERIANO DI DAVIDE SERRA DI TWITTER E ALGEBRIS, SI E' MESSO A COMP= RARE BANCHE POPOLARI DAL MARZO 2014. UN MESE DOPO (ULLALA CHE COINCIDENZA, = ULLALA). SEMPRE INSIDER E'. TRATTASI DI MANDRIA DI PORCI FASCIOCAMORRISTI,= TIPO, ANCHE, NOTO AVANZO DI GALERA PAOLO BARRAI (DI CRIMINALISSIME WMO, BS= I ITALIA SRL DI VIA SOCRATE 26 MILANO E BLOG "MERDATO"LIBERO), CHE SI FINGO= NO DEL PD, X... DISTRUGGERLO, INFILTRARLO A MORTE, RENDERLO DIARREA BERLUSC= ONICCHIA! VOGLIAMO UNA ACCESISSIMA E VINCENTISSIMA REVOLUCIOOOOOON! VOGLIAM= O IL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, FALLITO ED IN GALERA= ! SUBITO! PLS, DOTTOR SERGIO MATTARELLA, CI DIA UNA MANO. IN ONORE A SUO FR= ATELLO UCCISO DALLA MAFIA ( MAFIA CHE QUANDO SI METTE LA FASCISTISSIMA CRAV= ATTA DOLCE E GABBANA, SIGNIFICA SILVIO BERLUSCONI E DAVIDE SERRA). IN ONORE= AD ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO, FATTI SPAPPOLARE, SICURISSI= MAMENTE, DA SILVIO BERLUSCONI, VIA, A SUA VOLTA, BERLUSCONIANISSIMA COSA NO= STRA! ED OLTRE A VOLER SILVIO BERLUSCONI FALLITO ED IN GALERA, VOGLIAMO VED= ERE IL SUO PICCIOTTO INCRAVATTATO, IL FACCENDIERE DI BERLUSCONAZISTI, PADAN= AZISTI, E CRIMINALITA' ORGANIZZATE DI MEZZO MONDO, PAOLO BARRAI DI MALAVITO= SA WMO, PURE, IN GALERA! VOGLIAMO IL NUOVO GIANCARLO LANDE, IL NUOVO BERNAR= D MADOFF, IL NUOVO MICHELE SINDONA, VERME CRIMINALISSIMO DAVIDE SERRA DI TW= ITTER ED ALGEBRIS, FALLITO, E PER LO MENO, PER QUALCHE MESE, IN GALERA! CHE= SIA ETICISSSIMA E VINCENTISSIMA REVOLUCIOOOOON! > COME DA OTTIMO SITO INFORMARE X RESISTERE: > http://www.informarexresistere.fr/2015/01/27/qualcuno-sapeva-in-anticipo-= che-il-governo-avrebbe-varato-un-provvedimento-sulle-banche-popolari-enormi= -speculazioni/ > COME DA CORRIERE DELLA SERA, DI, OTTIMAMENTE, ANTIRENZUSCONIANO FERRUCCI= O DE BORTOLI, DA NON TOCCARE E A TUTTI I COSTI: > http://www.corriere.it/economia/15_gennaio_24/quei-movimenti-un-po-sospet= ti-popolari-f59ffb1c-a3a5-11e4-808e-442fa7f91611.shtml > Acquisti consistenti prima della riforma che ha abolito il voto capitari= o. La famiglia Boschi ha sicurissimamente passato insider trading a Londra,= tramite noto ladro, truffatore, nazifascista, immensamente ricicla soldi m= afiosi, che affatto va' in Tanzania a fare del bene, in quanto vi va' a ric= iclare cash di (sua) LL Lega Ladrona, come per suoi gusti sessuali di tipo = depravatissimo: avanzo di galera Davide Serra di Algebris e Twitter. Dove p= renderanno, le mazzette, ora, i vermi nazifascisti Pier Luigi Boschi di Ban= ca Etruria e sua zoccolona ( di fatto) Berlusconicchia Maria Elena Boschi (= bastarda puttanazista che vuole sgozzare la giustizia via estremissimament= e ingiusta salvaberlusconi http://www.blitzquotidiano.it/rassegna-stampa/li= bero-renzi-per-fare-la-pace-offre-la-salva-berlusconi-che-fara-mattarella-2= 090491/ .... che qui, non per niente, slingua un topo di fogna corrotto, nd= ranghetista, fascista, estortore di soldi alla Banca Popolare di Lodihttp:/= /www.repubblica.it/2005/l/sezioni/economia/banche21/ipolitici/ipolitici.htm= l .. pezzo di merda criminalissimo Paolo Romani > http://www.corriere.it/methode_image/2014/08/08/Politica/Foto%20Politica%= 20-%20Trattate/6ebdfe07bdd8cb1fe88af8343f8a5b1c-012-kXsC-U43030145012273wcB= -593x443@Corriere-Web-Sezioni.jpg?v=3D20140808175213 )? > A) Alle Bahamas > B) Alle Bermuda > C) A Panama > D) Ad Hong Kong > E) A Singapore > F) Alle Mauritius ( "roba" tipo Svizzera e' da anni 70, 80: stile nazima= fioso pedofilo Silvio Berlusconi e suo B-o-ttino Craxi, dai, please) > Lauti premi a chi azzecca per primo. > --- > BRAVO, BRAVO, DAVVERO BRAVISSIMO ELIO LANNUTTI A QUERELARE STO VERME BERL= US-CORROTTTISSIMO DI MATTEO RENZI: > http://www.ilfattoquotidiano.it/2015/01/21/denuncia-per-renzi/1357263/ > CHE SBEFFEGGIA PM PER BENE, EROICI, SALVA NAZIONE ( SPESSO FATTI ESPLODE= RE, COME IL NAZIMAFIOSO PEDOFILO STRAGISTA SILVIO BERLUSCONI FECE FARE CON = GLI ETERNI GIOVANNI FALCONE E PAOLO BORSELLINO). TIPO QUELLI DI PALERMO, BA= RI, MILANO, NAPOLI, DICENDO, ANZI, RAGLIANDO LORO: "'OOOO OO CHE PAURA, MI = FANNO, OO OO" > http://tv.ilfattoquotidiano.it/2014/09/10/renzi-anm-protesta-brrrrr-che-p= aura-sciopero-sindacati-polizia-illegale/295911/ > CHE RABBIA MOSTRUOSISSIMA, QUESTO VERMINOSO, CRIMINALISSIMO TRAFFICARE F= RA POR-CO-RRUTTORE MAXIMO SILVIO BERLUSCONI E POR-CO-RROTTO MAXIMO MATTEO R= ENZI! > https://ilgrandetsunami.wordpress.com/2015/01/17/berlusconi-che-ne-sara-d= i-me-il-2-febbraio-carmelo-lopapa/ > "IO TI VOTO LE RIFORME (ODIOSISSIMAMENTE MAFIOSE E FASCISTE, OSSIA BERLU= SCONIANISSIME) CHE STAI APPRONTANDO ( VEDI SENATORI NON ELETTI E CAPOLISTA = BLOCCATI, COSA CHE ANCHE I VERMINOSI MATTEO RENZI E SILVIO BERLUSCONI DEGLI= ULTIMI 8 DECENNI, OSSIA ADOLF HITLER, BENITO MUSSOLINI, ALFREDO STROESSNER= , FRANCISCO FRANCO, EMILIO EDUARDO MASSERA, AUGUSTO PINOCHET E POL POT AVRE= BBERO SENTITO TANTISSIMO PUDORE AL SOL PROVARE A PENSARNE), TU METTI AL QUI= RINALE UN FANTOCCIO DI MIA PROPRIETA' CHE COMPRO QUANDO VOGLIO QUALE GIULIA= NO AMATO, VALTER VELTRONI O ANNA FINOCCHIARO ... O MEGLIO ANCORA, SE PARLIA= MO DI MIEI FASCIOBAMBOCCI ALLA PIERFERDINANDO CASINI O GIANNI LETTA... TUTT= I MIEI PUPAZZI CHE MI HAN GIA' GARANTITO CHE CON SEI EURO E MEZZO CASH, MI = FIRMEREBBERO TUTTE LE GRAZIE CHE VOGLIO IN NOME DELLA MIA.... PACIFICAZIONE= ALLA VASELLINA... E ... SPECIALMENTE ...GIUSTO PER ANDARE SUL SICURO.... M= I FAI ANCHE E SUBITO UNA NORMINA DECAPITANTE NOIOSISSIMI CONCETTI COME DEMO= CRAZIA E GIUSTIZIA CHE IMPONGA IL MIO TORNARE IN POLITICA, COSI' CHE POSSA = FOTTERE IL POPOLO CIUCCIO, LE LEGGI, DOZZINE DI (GRANDISSIMI) MAGISTRATI CO= ME ILDA BOCASSINI, EDMONDO BRUTI LIBERATI, NINO DI MATTEO, ROBERTO SCARPINA= TO, FABIO DE PASQUALE, HENRY WOODCOCK, PASQUALE DRAGO, ATTRAVERSO LA ( BAST= ARDAMENTE VIGLIACCHISSIMA) IMMUNITA' EVITA GALERA, CHE MI RI RITROVEREI"! > http://www.ilfattoquotidiano.it/2015/01/18/salva-berlusconi-alessandro-pa= ce-manina-renzi-reato-falso/1349562/ > http://www.ilfattoquotidiano.it/2015/01/08/salva-berlusconi-mucchetti-ren= zi-venga-senato-spiegare-successo/1322595/ > http://www.ilfattoquotidiano.it/2015/01/06/salva-berlusconi-coppi-ammette= -quella-norma-segnale-per-quirinale/1318110/ > ECCO DOVE CI PORTANO BASTARDI LAVA CASH MAFIOSO A GO GO COME I MALAVITOS= INCRAVATTATI DAVIDE SERRA DI ALGEBRIS E TWITTER INSIEME AL RENATO VALLANZAS= CA UNITO AD UGO FANTOZZI DELLA FINANZA, NOTO AVANZO DI GALERA PAOLO BARRAI = NATO A MILANO IL 28.6.1965, DI CRIMINALISSIMO WMO, CRIMINALISSIMA BSI ITALI= A SRL DI VIA SOCRATE 26 MILANO E CRIMINALISSIMO BLOG MERCATO "MERDATO" LIBE= RO ( DUE VERMI REPELLENTI CHE RICICLANO ALL'ESTERO VAGONI DI SOLDI DI COSA = NOSTRA, CAMORRA, NDRANGHETA O LADRATI SE NON PURE FRUTTO DI MEGA MAZZETTE I= N DIREZIONE LL LEGA LADRONA ED EX PDL POPOLO DI LADRONI; IN CONGIUNZIONE CO= N BANCHIERI DELINQUENTISSIMI, SPESSO PURE MANDANTI DI OMICIDI O "SUICIDATE"= , COME FATTO CON DAVID ROSSI DI MONTE PASCHI, QUALI GLI ASSASSINI ENNIO DOR= IS E MASSIMO DORIS DI BANCA MEDIOLANUM; O QUALE "O MASSONE CAMORRISTA" GIUS= EPPE SABATO DI BANCA ESPERIA > http://www.gruppoesperia.it/chi-siamo/giuseppe-sabato.html > https://books.google.it/books?id=3DB1mEj0GtktIC&pg=3DPT304&lpg=3DPT304&dq= =3DGIUSEPPE+SABATO+LICIO+GELLI&source=3Dbl&ots=3DGqtu0KYRmD&sig=3Dd2TOz9sZD= Y6563zIPxwnNYcbxb4&hl=3Dit&sa=3DX&ei=3DI-i_VOOsBMLlUonCgZgI&ved=3D0CFMQ6AEw= CA#v=3Donepage&q=3DGIUSEPPE%20SABATO%20LICIO%20GELLI&f=3Dfalse > TUTTI DEL GRUPPO MA-F-INIVEST DI " STEFANO BONTATE, MARCELLO DELL'UTRI, = TOTO RIINA, LICIO GELLI, BERNARDO PROVENZANO E SILVIO BERLUSCONI: " OO CHE = CASO, OO")! E PROPRIO MENTRE VIENO ACCLARATO CHE STO VERME COLERICO E STECC= ATISSIMO DI MATTEO RENZI, COME INTUITO DA GENIO BORSISTICO ED EROE CIVILE M= ICHELE NISTA DA ANNI E NON "SOLO" 11 MESI, E' IN POLITICA, IN PRIMIS, PER P= ROTEGGERE IL TOPO DI FOGNA DI SUO PADRE, TIZIANO RENZI. ACCERTATO BANCAROTT= IERE FRAUDOLENTISSIMO, ACCERTATO NEOPIDUISTA LADRONE E TRUFFATORE! CHE HA S= ODOMIZZATO UN MILIONE DI EURO A FIDI TOSCANA E LI HA FATTI PAGARE AL POPOLO= CIUCCIO, VIA SUO BASTARDO NAZIMAFIOSO POR-CO-RROTTO DITTATORE MATTEO RENZI= ! > http://www.beppegrillo.it/2015/01/i_conflitti_dinteressi_della_famiglia_r= enzie.html > https://www.youtube.com/watch?v=3DA7Ngp6JrK9A > http://robertoiacobone.altervista.org/debiti-azienda-di-famiglia-renzi-pa= gati-dal-governo-renzi/?doing_wp_cron=3D1421500410.9769570827484130859375 > VOGLIAMO A PALAZZO CHIGI STEFANO FASSINA SUBITO! INSIEME AL PD PER BENE,= QUELLO ANTI MAFIA FASCISTA DI MATTEO RENZI! INSIEME, OVVIAMENTE, A M5S E S= EL! A FARE IL SUO VERO LAVORO, OSSIA LA ZOCCOLA DI STRADA, STA BATTONA HITL= ERIANA, CHE SI CREDE MODELLA MA E' CESSO STRA COLMO DI CELLULITE, DI MARIA = ELENA BOSCHI http://www.dagospia.com/img/foto/08-2014/maria-elena-boschi-bi= kini-rosa-in-spiaggia-a-marina-di-pietrasanta-581617_tn.jpg FIGLIA DI ALTR= O VERME CRIMINALISSIMO: MEGA LAVA SOLDI MAFIOSI PIER LUIGI BOSCHI DI BANCA = ETRURIA (DOPO AVER PASSATO TUTTA UNA VITA A TRAFFICARE CON COOP VICINISSIME= A MAFIA, CAMORRA E NDRANGHETA, NON PER NIENTE, STILE "RENZUSCONIANISSIMI" = SALVATORE BUZZI E MASSIMO CARMINATI)! AL QUIRINALE UN UOMO O DONNA VERA, AL= LA NINO DI MATTEO O ILDA BOCASSINI, CHE FACCIA TRASLOCARE IL CANCROMICIDA D= EL MONDO INTERO, SILVIO BERLUSCONI, DA PALAZZO GRAZIOLI A PALAZZO UCCIARDON= E E SUBITO. O VERA RIVOLUZIONE SARA'! RIVOLUZIONE RIPRISTINANTE VERA DEMOCR= ACIA Y LIBERTAD! PS SEMPRE VINCENTISSIMI I GENI BORSISTICI GEORGE SOROS E M= ICHELE NISTA A PUNTARE SULLA SPAGNA. PARREBBE CHE DOPO AVER SAPUTO CHE IL M= IGLIORE FIUTO PER QUALSIASI COSA AL MONDO, MICHELE NISTA, VEDA NON MALE LA = SPAGNA, GEORGE SOROS ABBIA DECISO DI METTERCI SUBITO, MANCO FOSSERO NOCCIOL= INE, 500 MILIONI DI EURO, NELL'AUMENTO DI CAPITALE DI BANCO SANTANDER. NON = SARA' UN PAESE IMMUNE DI DIFETTI, LA SPAGNA, COME NON LO E' ALCUN PAESE DEL= PIANETA TERRA. ANCHE LI, GLI SCANDALI PER CORRUZIONE NON MANCANO ( MA SONO= AL MASSIMO UN DECIMO, RISPETTO A QUELLI DELLA CLOACA DI RENZUSCONIA)! PERO= ', NONOSTANTE MEZZO SECOLO DI NAZIFASCISMO, OGGI LI VI E' DEMOCRAZIA VERA. = SIA AL POTERE MARIANO RAJOY DELL'OPUS DEI O IL PROMETTENTISSIMO PABLO IGLES= IAS DI PODEMOS. NON VI SONO, SULLA GOVERNATIVA POLTRONA DI MADRID, VERMI ST= RAGISTI, FASCIOCAMORRISTI E PEDOFILI ALLA SILVIO BERLUSCONI, CHE SI FAN LE = LEGGI PER GONFIARSI LE TASCHE DI SOLDI LERCISSIMI OLTRE CHE PER SGOZZARE A = MORTE DEMOCRAZIA E GIUSTIZIA, OGNI GIORNO. E QUESTO, O IN PROPRIO, O COMPRA= NDOSI RAGAZZINI CORROTTISSIMI CHIAMANTISI MATTEO, COME MATTEO RENZI (OGGI).= O IL NUOVO ADOLF HITLER: MATTEO SALVINI (DOMANI). MENTRE L'UNICO PADRONE, = L'UNICO VERO BOSS DEL CANCROMICIDA DEL MONDO INTERO, SILVIO BERLUSCONI, UN = ALTRO MATTEO, MATTEO MESSINA DENARO, SORRIDE E DICE " BRAVO MIO PRESTANOME = BEDDU SILVIO BERLUSCONI, HAI TRASFORMATO L'ITALIA IN RENZUSCONIA, CHE IN RE= ALTA' SEMPRE BERLUSCONIA E', AAAAAAA... COME PIACE A MMMIA, AAAA.... E' TUT= TO UNA COSA NOSTRA, SILVIUZZEDDU BEDDU ..... CONTINUA COSI' CHE TI TROVIAMO= QUALCHE ALTRA BEDDA PROSTITUTA DI 12-14 ANNI PELLU TEMPU LIBERO, AAAAA....= QUESTA VOLTA CAMBIAMO, AAAA... TE LA TROVIAMO FILIPPINA E LA FACCIAMO PASS= ARE PER LA NIPOTE DEL RE DELLA THAILANDIA, BHUMIBOL ADULYADEJ, IL RE PIU' R= ICCO DEL MONDO... CHE SPESSO E VOLENTIERI "ABOLISCE UFFICIALISSIMAMENTE LA = DEMOCRAZIA"... SI... SILVIUZZEDDU BEDDU DA COSA NOSTRA, TI TROVIAMO UNA BAM= BINA FILIPPINA DI 12 ANNI DA SBAVARE E TOCCARE QUANTO VUOI... E LA FACCIAMO= PASSARE PER LA NIPOTE THAILANDESE DI BHUMIBOL ADULYADEJ, AAAA.... COSI' VE= DRAI CHE QUANDO TELEFONI, PREOCCUPATISSIMO, DA PARIGI ( TANTO, FRA POCO, NE= LLA TUA DITTATURA DELLE BANANAS DI RENZUSCONIA, SUBITO, IL PASSAPORTO, TI R= IDARANNO), I POLIZIOTTI O QUESTORI, SOLO E SEMPRE LA TUA VOLONTA', FARANNO,= AAA"!!! From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.97.99 with SMTP id s63mr28628946yhf.40.1429601311682; Tue, 21 Apr 2015 00:28:31 -0700 (PDT) X-Received: by 10.50.3.105 with SMTP id b9mr27447igb.15.1429601311648; Tue, 21 Apr 2015 00:28:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!bcyclone04.am1.xlned.com!bcyclone04.am1.xlned.com!newsfeed.xs4all.nl!newsfeed1.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no2916802qgd.0!news-out.google.com!n7ni12892igk.0!nntp.google.com!l13no8020113iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Apr 2015 00:28:30 -0700 (PDT) In-Reply-To: <2m2g84$nqf@schema.fiu.edu> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=110.34.10.193; posting-account=4-AGgQoAAACioZu5dOMA_VCIzHyEbA8D NNTP-Posting-Host: 110.34.10.193 References: <2m2g84$nqf@schema.fiu.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Subject: Re: 8-bit Shift Register VHDL Behavioral From: ektelcom@gmail.com Injection-Date: Tue, 21 Apr 2015 07:28:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 17 X-Received-Bytes: 1898 X-Received-Body-CRC: 3996828251 Xref: mx02.eternal-september.org comp.lang.vhdl:8242 On Tuesday, March 15, 1994 at 1:53:36 AM UTC+5:45, Habibie wrote: > Could someone please email me a copy of the above subject? I am relatively > new to VHDL language. I would like to simulate an 8-bit shift register. > > Thank you very much. > -habibie@srse.fiu.edu > > Note: Sorry for previous wrong post. you can design shift register in many ways, 1. using for loop http://appliedelectronicsengineering.blogspot.com/2015/04/using-for-loop-for-4-bit-shift-register_21.html 2. using a straight forward approach http://appliedelectronicsengineering.blogspot.com/2015/04/straight-forward-way-to-describe-shift.html and there are also other ways From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: 8-bit Shift Register VHDL Behavioral Date: Tue, 21 Apr 2015 11:52:22 -0400 Organization: Alacron, Inc. Lines: 9 Message-ID: References: <2m2g84$nqf@schema.fiu.edu> <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 21 Apr 2015 15:52:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="22107"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Wo8I/PHv2uV1+oyTotCsMoADfpr1GPts=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <07fa0cd1-d487-4148-86ce-923a855be9ab@googlegroups.com> Cancel-Lock: sha1:+fWCJS8bZAk4BW3/D4X62GNs4JU= Xref: mx02.eternal-september.org comp.lang.vhdl:8243 ektelcom@gmail.com wrote: > On Tuesday, March 15, 1994 at 1:53:36 AM UTC+5:45, Habibie wrote: [snip] A 21-year-old thread. This must be some sort of record. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.45.98 with SMTP id o62mr38325477yhb.42.1429717099813; Wed, 22 Apr 2015 08:38:19 -0700 (PDT) X-Received: by 10.140.93.14 with SMTP id c14mr392827qge.42.1429717099733; Wed, 22 Apr 2015 08:38:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3168454qgd.0!news-out.google.com!k20ni1016qgd.0!nntp.google.com!j5no3167576qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Apr 2015 08:38:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.65.14.93; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 109.65.14.93 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Some tips how to print debug message from VHDL From: bknpk@hotmail.com Injection-Date: Wed, 22 Apr 2015 15:38:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 4 Xref: mx02.eternal-september.org comp.lang.vhdl:8244 I would like to share the following work: "...Recently I worked on an AHB project. I had many errors to debug in the initial bring up. Part of them were better debugged with print messages. The project contained some VHDL records, which GHDL (free VHDL simulator) does not dump to VCD wave. ..." http://bknpk.ddns.net/my_web/SDIO/vhdl_print_1_tips.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 23 Apr 2015 02:15:43 -0500 From: AhmedSokar Subject: Re: VHDL-AMS Q'ltf Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 98d4f114-395c-42c9-954c-b3469c3a0672 References: <1175689970.720561.150100@p77g2000hsh.googlegroups.com> Message-ID: Date: Thu, 23 Apr 2015 02:15:43 -0500 Lines: 4 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Kg1SHqNryLpb3c/ivYZmdJ7ojbjH384Dpt5fLKjoDC0EsWsBa4qslmumIUb1tBUAMY0DcJ6Sv/y4My3!pW8kdg1QK215pyYvxg6+OnNWfPABGzP2F/gvUiU/WBD5uhljQZa/eAeLSW54L5QoZgNA11Yl+nok!nBQ= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1017 Xref: mx02.eternal-september.org comp.lang.vhdl:8245 any solution for this problem yet? From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Thu, 23 Apr 2015 23:01:49 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL-AMS Q'ltf References: <1175689970.720561.150100@p77g2000hsh.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 7 Message-ID: <55395dbd$0$3027$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Apr 2015 23:01:50 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1429822910 news-1.free.fr 3027 88.185.146.198:2061 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8246 Le 23/04/2015 09:15, AhmedSokar a écrit : > any solution for this problem yet? 8 years later... Obviously, no. Nico From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.66.147.132 with SMTP id tk4mr12603890pab.23.1429896812417; Fri, 24 Apr 2015 10:33:32 -0700 (PDT) X-Received: by 10.140.38.232 with SMTP id t95mr146003qgt.36.1429896812157; Fri, 24 Apr 2015 10:33:32 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no5999622iga.0!news-out.google.com!k20ni1061qgd.0!nntp.google.com!z60no3539105qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Apr 2015 10:33:32 -0700 (PDT) In-Reply-To: <3h8mi2$ktb@vixen.cso.uiuc.edu> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=130.83.40.160; posting-account=1rGkOwoAAABn-dNxEVrNRvHKGXSYJRiG NNTP-Posting-Host: 130.83.40.160 References: <3h8mi2$ktb@vixen.cso.uiuc.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: component implication in Synopsys From: ghada.dessouky@gmail.com Injection-Date: Fri, 24 Apr 2015 17:33:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8247 10 years later....I am struggling with that problem now. Any ideas since then :D? On Tuesday, February 7, 1995 at 9:52:18 PM UTC+1, Matthew Todd Gavin wrote: > In Synopsys, "component implication" occurs during synthesis, when you map > a function call to a component instantiation. The code below maps the > function call "check_one_count" to the entity one_counter. Whenever the > function is called in the code, the corresponding component is > instantiated. > > The problem is this: the entity uses a generic so that its input vector > (vin) can be of any length. When component implication is done, the > inputs to the corresponding function must be of _known_ length, or the > implication will not work. So my function parameter > > signal vin: in std_logic_vector; > > screws up the component implication. However, there is no way to pass in > the information for the length of vin, if we want to keep the design > generic. > > So is it possible to use component implication to imply a component > which has variable-length input/output? Just wondering if anyone had > encountered this besides me. > > Thanks, > > Matt > > -- check if there are exactly c high std_logics in v > function check_one_count > (signal vin: in std_logic_vector; n,c: integer) return std_logic is > -- pragma map_to_entity one_counter > -- pragma return_port_name c_ones > -- contents of this function are ignored but should > -- match the functionality of the module counter > variable count: integer range 0 to vin'length; > begin > count := 0; > for i in vin'range loop > if vin(i) = '1' then > count := count +1; > end if; > end loop; > > if (count = c) then > return '1'; > else > return '0'; > end if; > end; > > > > -- > ********************************************************* > Matt Gavin BSEE U of Iowa '93 > mtgavin@uiuc.edu Go Iowa Hawks!!!!! > http://www.cen.uiuc.edu/~mg12861/matt.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.25.35 with SMTP id y23mr2187458yhy.9.1429930788223; Fri, 24 Apr 2015 19:59:48 -0700 (PDT) X-Received: by 10.50.73.136 with SMTP id l8mr20285igv.0.1429930788196; Fri, 24 Apr 2015 19:59:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3596259qgd.0!news-out.google.com!db6ni25048igc.0!nntp.google.com!m20no6083540iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 24 Apr 2015 19:59:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.61.239.206; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 122.61.239.206 References: <3h8mi2$ktb@vixen.cso.uiuc.edu> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: component implication in Synopsys From: diogratia@gmail.com Injection-Date: Sat, 25 Apr 2015 02:59:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 3283 X-Received-Body-CRC: 436468072 Xref: mx02.eternal-september.org comp.lang.vhdl:8248 Try taking off your shoes and socks when you count the years That's 20 year= s on. Instead of trolling through very old posts you could consider the issue in = terms of the modern specification of the the VHDL language (IEEE Std 1076-2= 008). (At the head post of this thread does stand out like a sore thumb doe= sn't it?) Try 4.4 Subprogram instantiation declarations in the standard where you'll = find that those function calls can be instantiated providing separation by = usage for varying length array parameter arguments. What we used to colloqu= ially refer to as uniquifying. The intended use is for this very purpose. http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/dta_type_genericity.pdf VHDL-200x Data Types and Abstractions White Paper 1, Type Genericity Peter Ashenden 1 Introduction Reuse of a design unit can be improved by making it applicable in a wider s= et of contexts, for example, by making it more generic. VHDL currently incl= udes a mechanism, generic constants, that allows components and entities to= be parameterized with formal constants. Actual generi c constants are spec= ified when components are instantiated and when entities are bound. The gen= eric constant mechanism is widely used to specify timing parameters and arr= ay port bounds, among other things. In this proposal we extend the generic mechanism of VHDL to improve support= for reuse. There are two main aspects to the extension. The first is to al= low subprograms and packages to have generic interface clauses. The second = is to allow formal types in a generic interface clause, making the generic = item reusable for a variety of different types. Formal subprograms and form= al packages are also allowed as a corollary to allowing formal type =20 -- If it's not supported today, it's due to a lack of -2008 support. Complain = to your synthesis vendor. It's a lack of love for VHDL on the part of your = synthesis vendor. And otherwise you're exhibiting hyperopia, unable to see = clearly into the historical record of the more recent past. From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 27 Apr 2015 01:09:45 -0500 From: Sumathigokul Subject: Re: TCL CODE WITH VHDL Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 1c74f010-f680-4d48-9462-34a57db641e6 References: <1135946281.847362.112360@g44g2000cwa.googlegroups.com> Message-ID: Date: Mon, 27 Apr 2015 01:09:45 -0500 Lines: 12 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-PffWCaI3BNZ+l67c1AFrGAoAnmdMoamFq9oUeu7HF4fnNw6NRLVIrvPd9b+4lyS8Wu4/Ba0Y7UtpPVQ!AslSzqQwkaeFg2oazNsQTB3ZHAk4DVDwnn4UD2RQP83c+hKjrBjkOMNF5Nj6qVanee/ccrZkUnbL!NKg= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1684 Xref: mx02.eternal-september.org comp.lang.vhdl:8249 Hi all... I have two doubts. 1. My first doubt is how to write the tcl script which locates my existing .vhd file and insert new line of code in it or replaces some of the existing codes and save the modified .vhd code back to same folder or in another new folder??? 2. My second doubt is if i want to modify .vhd code already existing (statement of my first doubt) using TCL command, how i can perform it? for example, to force any value at .vhd file using tcl command, am running that particular command in any of the simulation tool's command line. Similarly, if i write a tcl script to modify .vhd file, where can i run that file (i.e. using which tool) ??? Regards, Sumathi G. From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.43.130.198 with SMTP id hn6mr819790icc.26.1430266157749; Tue, 28 Apr 2015 17:09:17 -0700 (PDT) X-Received: by 10.182.181.10 with SMTP id ds10mr99064obc.12.1430266157692; Tue, 28 Apr 2015 17:09:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!l13no11395434iga.0!news-out.google.com!kd3ni2787igb.0!nntp.google.com!m20no7000164iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Apr 2015 17:09:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.72.133.197; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 71.72.133.197 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3a6b6b23-c122-4785-bbd5-af9bb147410d@googlegroups.com> Subject: Interested in VHDL and FPGA Development? From: Jackie Christman Injection-Date: Wed, 29 Apr 2015 00:09:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8250 Check out my course for only $15! Unlimited and Lifetime Access! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=FIVERR15 From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.52.7.194 with SMTP id l2mr5805856vda.12.1431006255863; Thu, 07 May 2015 06:44:15 -0700 (PDT) X-Received: by 10.50.73.136 with SMTP id l8mr336835igv.0.1431006255781; Thu, 07 May 2015 06:44:15 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no5856441qga.1!news-out.google.com!kd3ni10371igb.0!nntp.google.com!m20no9155339iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 May 2015 06:44:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.35; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.35 References: <1a399a67-85c3-47c5-92d9-1003c2b1cbea@googlegroups.com> <4ac81172-843a-4404-b643-13c3e526308c@googlegroups.com> <537337b1$0$27153$e4fe514c@dreader35.news.xs4all.nl> <1d311eb0-daeb-48ff-98c5-95131f0bc97c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <23ebe552-8bdc-4825-a4ad-69588d2757ae@googlegroups.com> Subject: Re: Can I replace this procedure with a function (VHDL 2008 problem)? From: Jim Lewis Injection-Date: Thu, 07 May 2015 13:44:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8251 A very latent reply, however, in my scoreboard that does this, I keep a previous item pointer that I deallocate on entering pop and leave the previous item in when I exit. From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.68.180.5 with SMTP id dk5mr2377312pbc.3.1431051235171; Thu, 07 May 2015 19:13:55 -0700 (PDT) X-Received: by 10.140.23.166 with SMTP id 35mr24971qgp.12.1431051234873; Thu, 07 May 2015 19:13:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no9333529iga.0!news-out.google.com!t92ni215qga.1!nntp.google.com!z60no5970869qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 7 May 2015 19:13:54 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.204.56.74; posting-account=uG-J6goAAAAcwMKpgt64lolkjJA4c0tE NNTP-Posting-Host: 73.204.56.74 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> Subject: Support Vector Machine VHDL From: Gee Won Han Injection-Date: Fri, 08 May 2015 02:13:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: mx02.eternal-september.org comp.lang.vhdl:8252 I would like to know if there someone has a VHDL code for Support Vector Machine. I would also like to know if someone could explain to me this line of code res: out sfixed(7 downto -10) I know what is downto, but I have never seen it to a negative number before. Does that mean this is sfixed is 17 bits? Thanks From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.70.118.99 with SMTP id kl3mr4821902pdb.12.1431082670501; Fri, 08 May 2015 03:57:50 -0700 (PDT) X-Received: by 10.140.41.164 with SMTP id z33mr40276qgz.21.1431082670241; Fri, 08 May 2015 03:57:50 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no329241iga.0!news-out.google.com!k20ni1978qgd.0!nntp.google.com!z60no6034759qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 03:57:50 -0700 (PDT) In-Reply-To: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:e875:f73d:c499:eae0; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:e875:f73d:c499:eae0 References: <45879c82-6637-4679-adc2-045a9cdfbb62@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Support Vector Machine VHDL From: KJ Injection-Date: Fri, 08 May 2015 10:57:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: mx02.eternal-september.org comp.lang.vhdl:8253 On Thursday, May 7, 2015 at 10:13:58 PM UTC-4, Gee Won Han wrote: >=20 > I would also like to know if someone could explain to me this line of cod= e >=20 > res: out sfixed(7 downto -10) >=20 >=20 > I know what is downto, but I have never seen it to a negative number befo= re. > Does that mean this is sfixed is 17 bits? >=20 sfixed is a data type that represents a signed fixed point number. There a= re 8 bits to the left of the point (7 downto 0) and there are 10 bits to th= e right of the point (-1 downto -10). There is also a type called ufixed w= hich is simply the unsigned version. Go here www.eda-stds.org/fphdl to get to the VHDL fixed and floating point = package. There is a user's guide that should be able to answer additional = questions you would have on how to use these packages. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.38.194 with SMTP id a42mr7616510yhb.4.1431107197092; Fri, 08 May 2015 10:46:37 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr73843qge.40.1431107197013; Fri, 08 May 2015 10:46:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no6109424qga.1!news-out.google.com!k20ni1998qgd.0!nntp.google.com!j5no6109422qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 10:46:36 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.255.163; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.255.163 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Subject: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Fri, 08 May 2015 17:46:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1527 X-Received-Body-CRC: 2720090035 Xref: mx02.eternal-september.org comp.lang.vhdl:8254 Hello, I'm learning an opensource cad tool called alliance , it takes a vhdl design and turns it into a wafer digital layout , its VHDL compiler is called SYF , the problem is that a code that compiled successfully on modelsim won't compile here , my VHDL is not very strong so I hope someone could give my an explanation : the problem is with variable declaration process(CS,wordin,reset) variable addr : std_logic_vector (7 DOWNTO 0); begin ... error : ILLEGAL DECLARATION at the variable declaration line any help ? From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Fri, 08 May 2015 14:56:19 -0400 Organization: Alacron, Inc. Lines: 27 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 8 May 2015 18:55:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="2766"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19VYPxxUN9MGzhyQYbFjEiooGx9NGfFQJ0=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Cancel-Lock: sha1:zLclc/C4bR+f2UrXFCAneBiu5ao= Xref: mx02.eternal-september.org comp.lang.vhdl:8255 yaser fathy wrote: > Hello, > > I'm learning an opensource cad tool called alliance , it takes a vhdl > design and turns it into a wafer digital layout , its VHDL compiler is > called SYF , the problem is that a code that compiled successfully on > modelsim won't compile here , my VHDL is not very strong so I hope > someone could give my an explanation : > > the problem is with variable declaration > > process(CS,wordin,reset) > variable addr : std_logic_vector (7 DOWNTO 0); > begin > ... > > error : ILLEGAL DECLARATION > at the variable declaration line > > any help ? Maybe try naming the process, so the variable has an obvious hierarchical name like: proc_name: process (CS, wordin, reset) variable . . . From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.182.29.70 with SMTP id i6mr83065obh.27.1431121100277; Fri, 08 May 2015 14:38:20 -0700 (PDT) X-Received: by 10.140.31.196 with SMTP id f62mr1328qgf.30.1431121100087; Fri, 08 May 2015 14:38:20 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no623168iga.0!news-out.google.com!k20ni2008qgd.0!nntp.google.com!j5no6152950qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 8 May 2015 14:38:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.255.163; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.255.163 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Fri, 08 May 2015 21:38:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8256 thanks for your reply , but still not working. From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Fri, 08 May 2015 18:16:00 -0400 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 8 May 2015 22:14:56 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="19761"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Dhng0b8pivpbt97CSNGV6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <66ea8bf3-3e4b-4098-ace7-3339b39a4eb0@googlegroups.com> Cancel-Lock: sha1:QKU1KfmaZwVHkGwGEfcaMvNDaow= Xref: mx02.eternal-september.org comp.lang.vhdl:8257 On 5/8/2015 5:38 PM, yaser fathy wrote: > thanks for your reply , but still not working. Something else is wrong. It won't be the first time the tool points to the wrong place to find an error. Check a few lines ahead of the process declaration. Any mistakes there? -- Rick From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sat, 9 May 2015 10:32:47 +0000 (UTC) Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 9 May 2015 10:32:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="5354"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18v0fbF02L803cmAIG/dx7bq281Zcugrm0=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:pKvrFTi/eEmfRa3G/aGoNAfZ01c= Xref: mx02.eternal-september.org comp.lang.vhdl:8258 On Fri, 08 May 2015 10:46:36 -0700, yaser fathy wrote: > Hello, > > I'm learning an opensource cad tool called alliance , it takes a vhdl > design and turns it into a wafer digital layout , its VHDL compiler is > called SYF , the problem is that a code that compiled successfully on > modelsim won't compile here , Your code looks OK (from the fragment posted). How recent is this version of Alliance, how well maintained is it, and what is its support for newer versions of VHDL? My understanding is that Alliance is not actively supported, so it may not understand some perfectly legal constructs used in modern VHDL. (I'd be delighted f someone told me I'm wrong on this, but I haven't heard of any recent activity). -- Brian From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.66.151.234 with SMTP id ut10mr5955247pab.6.1431194801813; Sat, 09 May 2015 11:06:41 -0700 (PDT) X-Received: by 10.140.107.69 with SMTP id g63mr43332qgf.31.1431194801516; Sat, 09 May 2015 11:06:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!m20no1051472iga.0!news-out.google.com!t92ni259qga.1!nntp.google.com!j5no6314068qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 11:06:41 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=128.6.168.245; posting-account=p7IJzgkAAACsFeCX1coqmBrFeWDIplQ_ NNTP-Posting-Host: 128.6.168.245 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Verification of AVR8 Soft Core From: ssh105 Injection-Date: Sat, 09 May 2015 18:06:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8259 Hi, I managed to find some code for the AVR8 Soft Processor for the Arduino. It's VHDL code that you can implement on an FPGA to simulate the Arduino. You can find it here: http://papilio.cc/index.php?n=Papilio.ArduinoCore Does anyone know if it's possible to run some kind of VHDL formalism/hardware verification on it? Thanks in advance! From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.182.142.37 with SMTP id rt5mr6865524obb.47.1431202380896; Sat, 09 May 2015 13:13:00 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr47397qgi.26.1431202380820; Sat, 09 May 2015 13:13:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no1110799iga.0!news-out.google.com!k20ni2048qgd.0!nntp.google.com!j5no6336756qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 13:13:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=41.226.202.39; posting-account=GxHQuAoAAAD5XUAW3CvS5ZEcFMip9aZO NNTP-Posting-Host: 41.226.202.39 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Subject: 2spartan connected via Bluetooth From: Sam Souliez Injection-Date: Sat, 09 May 2015 20:13:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: mx02.eternal-september.org comp.lang.vhdl:8260 Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start Need you help guys ! From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp5-1.free.fr!not-for-mail Date: Sat, 09 May 2015 22:21:24 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 2spartan connected via Bluetooth References: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> In-Reply-To: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 8 Message-ID: <554e6c43$0$3034$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 09 May 2015 22:21:23 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1431202883 news-3.free.fr 3034 88.185.146.198:1788 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8261 Le 09/05/2015 22:13, Sam Souliez a écrit : > Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start > Need you help guys ! Look at the BT module datasheet, there's certainly plenty of extremely useful information inside. Nicolas From newsfish@newsfish Tue Dec 29 16:43:49 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: 2spartan connected via Bluetooth Date: Sat, 09 May 2015 16:31:33 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 9 May 2015 20:30:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10977"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19mclIk8vntC5pyYGnncucr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <5ddb2dae-63bb-4293-9c19-2aca1029bc38@googlegroups.com> Cancel-Lock: sha1:BZI5Wt5p/nTeYsHxd3NstTS1lzE= Xref: mx02.eternal-september.org comp.lang.vhdl:8262 On 5/9/2015 4:13 PM, Sam Souliez wrote: > Can anyone help me with my projet i have to connect to spartan 6 or 3 using VHDl language via bluetooth mpodule but i don't where i start > Need you help guys ! The easy way is to use a bluetooth module that provides a serial interface. Then all your FPGA design needs to do is push characters out the serial port and receive what comes back. Look for HC-05 on ebay. I have some which I will be working with very soon. -- Rick From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.70.135.10 with SMTP id po10mr7353546pdb.2.1431209679301; Sat, 09 May 2015 15:14:39 -0700 (PDT) X-Received: by 10.140.105.133 with SMTP id c5mr53086qgf.28.1431209679046; Sat, 09 May 2015 15:14:39 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1160754iga.0!news-out.google.com!t92ni268qga.1!nntp.google.com!z60no6355795qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 15:14:38 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=158.227.185.115; posting-account=-EGgzQkAAAAEZAPEk3dU_oy6cNScQ5_l NNTP-Posting-Host: 158.227.185.115 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> Subject: Reducing verbosity in structural entity declaration From: unaimc@gmail.com Injection-Date: Sat, 09 May 2015 22:14:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8263 Hello, I recently learnt that, since VHDL'93, components are not needed any more, = and entities can be directly instantiated [0]. So that I can replace this a= rchitecture --entity testent is -- port ( CLK: in std_logic ); --end testent; --architecture withcomponents of testent is ---component mycomp ---port ( CLK, D: in std_logic; --- Q: out std_logic ); ---end component; ---signal f2s: std_logic; --begin ---MODA: mycomp port map ( CLK, open, f2s); ---MODB: mycomp port map ( CLK, f2s, open); --end withcomponents; with --architecture withoutcomponents of testent is ---signal f2s: std_logic; --begin ---MODA: entity work.mycomp port map ( CLK, open, f2s); ---MODB: entity work.mycomp port map ( CLK, f2s, open); --end withoutcomponents; On top of that, I would like to know whether VHDL supports any expression s= o that the declaration of the signal 'f2s' is not required. Something simil= ar to: --architecture direct of testent is --begin ---MODA: entity work.mycomp port map ( CLK, open, MODB.D); ---MODB: entity work.mycomp port map ( CLK, MODA.Q, open); --end direct; Which from my point of view would be explained as: can VHDL understand the = ports of an instantiated entity as if it was a record? I've tried it in ISE= with no success, and I've found no similar examples, so I would say that i= t's not supported. However, I'd like to know your opinions, in case you thi= nk that such a feature makes sense, or to hear of alternatives to achieve a= similar scheme. I've found this message [1] sent to the VHDL-200X - DASC mailing list in Fe= b 2003, which is much ambitious than what I'm asking. However, since it is = related, I'd like to be pointed to any later reference on it, if any. ---- Moreover, although I've presented a really simple example, I'd like to use = such a feature inside generate environments. Thus, to achieve so, besides s= upporting such an expression, the label of the instantiation should provide= references to each of the actually synthetized modules. A shift register, = with such an implicit declarations, would be: --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----case k generate -----when 0 =3D> ------MODS(k): entity work.mycomp port map ( CLK, open, MODS(k+1).D); -----when 7 =3D> ------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D)= ; -----when others =3D> ------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, open); ----end generate; ---end generate; --end direct; or --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----MODS(k): case k generate -----when 0 =3D> ------entity work.mycomp port map ( CLK, open, MODS(k+1).D); -----when 7 =3D> ------entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D); -----when others =3D> ------entity work.mycomp port map ( CLK, MODS(k-1).Q, open); ----end generate; ---end generate; --end direct; I'm quite sure that this is not supported neither in VHDL'93 nor in VHDL'08= . Nevertheless, to those of you who know the internals, does this feature(s= ) make any sense to you? Or is rather specific? [0] http://www.sigasi.com/content/four-and-half-ways-write-vhdl-instantiati= ons [1] http://www.eda.org/vhdl-200x/hm/0040.html From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.40.8 with SMTP id e8mr7375236yhb.35.1431210586242; Sat, 09 May 2015 15:29:46 -0700 (PDT) X-Received: by 10.140.102.75 with SMTP id v69mr52333qge.19.1431210586187; Sat, 09 May 2015 15:29:46 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!j5no6356020qga.1!news-out.google.com!k20ni2059qgd.0!nntp.google.com!j5no6356014qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 15:29:46 -0700 (PDT) In-Reply-To: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=158.227.185.115; posting-account=-EGgzQkAAAAEZAPEk3dU_oy6cNScQ5_l NNTP-Posting-Host: 158.227.185.115 References: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reducing verbosity in structural entity declaration From: unaimc@gmail.com Injection-Date: Sat, 09 May 2015 22:29:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 9 Xref: mx02.eternal-september.org comp.lang.vhdl:8264 As a bonus conceptual script, this is what I would expect to be nearly minimum verbosity while still maintaing VHDL syntax (with richer generate structures): --architecture direct of testent is --begin ---MODS: for k in 7 downto 0 generate ----MODS(k): entity work.mycomp port map ( CLK, -----[case k generate when 0 => open; when others => MODS(k-1).Q; end generate;] , -----[case k generate when 7 => open; when others => MODS(k+1).D; end generate;] ); ---end generate; --end direct; From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.182.45.138 with SMTP id n10mr8194366obm.4.1431217505907; Sat, 09 May 2015 17:25:05 -0700 (PDT) X-Received: by 10.140.29.119 with SMTP id a110mr50130qga.20.1431217505806; Sat, 09 May 2015 17:25:05 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m20no1199399iga.0!news-out.google.com!k20ni2063qgd.0!nntp.google.com!j5no6368567qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 9 May 2015 17:25:05 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:80ae:3f64:4c4a:fc98; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:80ae:3f64:4c4a:fc98 References: <553ae1d3-5a04-4dc7-858c-d65f127aa89d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Reducing verbosity in structural entity declaration From: KJ Injection-Date: Sun, 10 May 2015 00:25:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8265 On Saturday, May 9, 2015 at 6:29:47 PM UTC-4, una...@gmail.com wrote: You can't do exactly what you want since you're using 'MODS' both as the na= me of the instantiation as well as the name of a signal. However, you will= need to define the record structure and make an array of it anyway so ther= e will be just as much typing to do that, naming the signal uniquely isn't = any time saver. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.68.142.7 with SMTP id rs7mr10783571pbb.4.1431256300585; Sun, 10 May 2015 04:11:40 -0700 (PDT) X-Received: by 10.140.94.47 with SMTP id f44mr67601qge.22.1431256300271; Sun, 10 May 2015 04:11:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!m20no10002558iga.0!news-out.google.com!k20ni2075qgd.0!nntp.google.com!j5no6438781qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 04:11:40 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <365da0e4-cb6a-48ca-a3fa-f1b0be728414@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Sun, 10 May 2015 11:11:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:8266 the version is 5 copyrighted 2015 if I remove the variable declaration and make a similar signal declaration (before the begin) it compiles and simulates successfully. From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.66.121.137 with SMTP id lk9mr11129780pab.11.1431256383312; Sun, 10 May 2015 04:13:03 -0700 (PDT) X-Received: by 10.140.20.40 with SMTP id 37mr68846qgi.26.1431256383006; Sun, 10 May 2015 04:13:03 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!m20no1394343iga.0!news-out.google.com!t92ni287qga.1!nntp.google.com!z60no6439939qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 04:13:02 -0700 (PDT) In-Reply-To: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Subject: Re: Alliance CAD tool VHDL problem From: yaser fathy Injection-Date: Sun, 10 May 2015 11:13:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8267 the version is 5 copyrighted 2015 if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully. From newsfish@newsfish Tue Dec 29 16:43:49 2015 X-Received: by 10.236.7.133 with SMTP id 5mr11520402yhp.3.1431262038388; Sun, 10 May 2015 05:47:18 -0700 (PDT) X-Received: by 10.140.31.196 with SMTP id f62mr74161qgf.30.1431262038269; Sun, 10 May 2015 05:47:18 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j5no6453414qga.1!news-out.google.com!t92ni290qga.1!nntp.google.com!z60no6454416qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 10 May 2015 05:47:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.32.233.105; posting-account=6a35pQoAAAA1NUzz4btw_dkd1bkuTEJc NNTP-Posting-Host: 197.32.233.105 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Input storage in FSM From: yaser fathy Injection-Date: Sun, 10 May 2015 12:47:18 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1403 X-Received-Body-CRC: 312294366 Xref: mx02.eternal-september.org comp.lang.vhdl:8268 Hello, I want to create a fsm that takes a few inputs during its cycle and output these inputs at the end of the cycle . I wanted to use variables to store these input but the compiler won't accept variable declaration , so I used signals , now the code compiles fine , but the output doesn't show at the end , and the compiler log sais: output x is assigned by only 2 states refering to the signal I used to store the input From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sun, 10 May 2015 21:45:19 -0400 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 01:44:15 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="16518"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bZ4Yd0NjGaDIlqNcsqWnQ" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Cancel-Lock: sha1:a3y5xu4dUNtf5L454a9LFcnWjgs= Xref: mx02.eternal-september.org comp.lang.vhdl:8269 On 5/10/2015 7:13 AM, yaser fathy wrote: > the version is 5 copyrighted 2015 > > if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully. > While that probably is one workaround, you have to be careful if you start to do this globally on a design. Declaring the variable outside the process makes it shared, and you want to be careful not to use it elsewhere. Also you could have multiple processes with the same name for a local variable, and you would then have to re-name these when you pull them out of the process. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Alliance CAD tool VHDL problem Date: Sun, 10 May 2015 22:01:26 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <9be2e975-2807-428d-8947-18e87d99c1d6@googlegroups.com> <35f9adc8-0c16-48b8-8c62-9528a3f0be3f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 02:00:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="19271"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NvWH5C50/dnnvwvncBOIy" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: Cancel-Lock: sha1:CqNykxLJYRd8ezBS2PkWoImMIxo= Xref: mx02.eternal-september.org comp.lang.vhdl:8270 On 5/10/2015 9:45 PM, Gabor wrote: > On 5/10/2015 7:13 AM, yaser fathy wrote: >> the version is 5 copyrighted 2015 >> >> if I remove the variable declaration and make a similar signal >> declaration (before the process) it compiles and simulates successfully. >> > > While that probably is one workaround, you have to be careful > if you start to do this globally on a design. Declaring the > variable outside the process makes it shared, and you want > to be careful not to use it elsewhere. Also you could have > multiple processes with the same name for a local variable, > and you would then have to re-name these when you pull them > out of the process. > OK I see from your new thread that you didn't declare shared variables but rather signals. You do understand that signals do not take on their assigned values until the process completes while variables take on the new value right away? So just moving the declaration outside the process will change the logic if you make the variable into a signal. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 16:59:00 +0000 (UTC) Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 May 2015 16:59:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="10055d0a889852f8818324769e017ab0"; logging-data="2970"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/tfHMcfj+dI7lD22hZdX4T" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:uqV8Cxq33tJXsbOmmwbVRJo+80Y= Xref: mx02.eternal-september.org comp.lang.vhdl:8271 On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: > Hello, > > I want to create a fsm that takes a few inputs during its cycle and > output these inputs at the end of the cycle . > > I wanted to use variables to store these input but the compiler won't > accept variable declaration , so I used signals , now the code compiles > fine , but the output doesn't show at the end , and the compiler log > sais: > > output x is assigned by only 2 states refering to the signal I used to > store the input That sounds like you've made an utter hash of things. I don't know of any compilers that won't accept VHDL legal variable definitions, so that's the first sign something's badly wrong. And whatever message you've got there regarding the output means that your state machine logic is probably some horrific tangle of combinational and clocked processes. You want to write the entire thing in a single process. Google for vhdl single process state machine. You'll get a ton of hits; most of which will be crap. Spend the time reading through them, valid and crap alike, until you understand the concept. Be willing to blow an hour on it. Then, and here's the part you won't like, delete your entire existing architecture definition. Wipe it out. It's wrong, it's a mess, I can tell you without even reading it. Even if you manage to cobble together code that seems to work from it, you'll miss something. It's what, 30 lines of code? 40? Write it fresh with a clear idea of how it should be structured; you'll get there in half the time. What you've currently got can only get in your way. So ends the advice of Rob. As an aside to the other old farts around here, I was going to point him to Mike Tressler's site for specific examples, and couldn't find even archives of it. Anyone still have a reference for it? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!not-for-mail Date: Mon, 11 May 2015 19:22:14 +0100 From: Andy Botterill User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM References: In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 25 Message-ID: <5550f357$0$28970$bed64819@gradwell.net> NNTP-Posting-Host: d639f4a5.gradwell.net X-Trace: DXC=m34=ge=kWGo:=KiVkUL^lgaEW\3OJZ9ZcPo1k6Q\TjcoYjMIT`6J^KoOT6Q0a]eYDbA2:ZUKJ>:m`K>VKND1bjBiAT9C^SG@jHd X-Complaints-To: abuse@gradwell.net X-Received-Bytes: 1486 X-Received-Body-CRC: 4101716920 Xref: mx02.eternal-september.org comp.lang.vhdl:8272 On 11/05/15 17:59, Rob Gaddi wrote: > On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: > > > As an aside to the other old farts around here, I was going to point him > to Mike Tressler's site for specific examples, and couldn't find even > archives of it. Anyone still have a reference for it? This was posted in 2007. http://home.comcast.net/~mike_treseler/ Unfortunately that URL does not exist any more. Look at page 31 of this http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl.pdf It does refer to Mike Treseler's code and gives an example. The powerpoint points to a Verizon place which does not exist as well. Hopefully Mike will come back....... From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 15:51:29 -0400 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <5550f357$0$28970$bed64819@gradwell.net> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 11 May 2015 19:50:27 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22139"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19HqlyVEJXT7RIUbpyiTPhf" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 In-Reply-To: <5550f357$0$28970$bed64819@gradwell.net> Cancel-Lock: sha1:k1XFTGz/XelhWx/Y+q6UsyF3D1g= Xref: mx02.eternal-september.org comp.lang.vhdl:8273 On 5/11/2015 2:22 PM, Andy Botterill wrote: > On 11/05/15 17:59, Rob Gaddi wrote: >> On Sun, 10 May 2015 05:47:18 -0700, yaser fathy wrote: >> >> >> As an aside to the other old farts around here, I was going to point him >> to Mike Tressler's site for specific examples, and couldn't find even >> archives of it. Anyone still have a reference for it? > > This was posted in 2007. > > http://home.comcast.net/~mike_treseler/ > > Unfortunately that URL does not exist any more. > > Look at page 31 of this > http://ens.ewi.tudelft.nl/Education/courses/et4351/structured_vhdl.pdf > > It does refer to Mike Treseler's code and gives an example. > > The powerpoint points to a Verizon place which does not exist as well. > > Hopefully Mike will come back....... I don't see where he has posted here since 2013. Searching a bit on the web uncovers him as being at Microsoft working on the XBox since Dec 2013. So that may explain it. He may be working on a black ops sort of thing and not allowed to participate in social media. -- Rick From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Input storage in FSM Date: Mon, 11 May 2015 22:47:46 +0000 (UTC) Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <5550f357$0$28970$bed64819@gradwell.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 May 2015 22:47:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="10055d0a889852f8818324769e017ab0"; logging-data="2970"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19hw5kbAWrMNGXOQ9j4GhHB" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/kpkgzQc0/kJMfogQCa+5Neg+7w= Xref: mx02.eternal-september.org comp.lang.vhdl:8274 On Mon, 11 May 2015 15:51:29 -0400, rickman wrote: > On 5/11/2015 2:22 PM, Andy Botterill wrote: >> >> Hopefully Mike will come back....... > > I don't see where he has posted here since 2013. Searching a bit on the > web uncovers him as being at Microsoft working on the XBox since Dec > 2013. So that may explain it. He may be working on a black ops sort of > thing and not allowed to participate in social media. This is USENET. Who's social? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.66.219.130 with SMTP id po2mr38667934pac.46.1432039531910; Tue, 19 May 2015 05:45:31 -0700 (PDT) X-Received: by 10.140.95.109 with SMTP id h100mr389578qge.6.1432039531853; Tue, 19 May 2015 05:45:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!j8no5672518igd.0!news-out.google.com!t92ni24958qga.1!nntp.google.com!z60no2307849qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 19 May 2015 05:45:31 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.253.6.210; posting-account=fNDqwQoAAAB4_FDM62R1eG1rPB785aCE NNTP-Posting-Host: 197.253.6.210 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MOD operator From: theultimateiq@gmail.com Injection-Date: Tue, 19 May 2015 12:45:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1774 X-Received-Body-CRC: 1394926736 Xref: mx02.eternal-september.org comp.lang.vhdl:8275 Dear Guilherme, I have been working on implementing a main memory for days now but it keeps= showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't det= ermine definition of operator ""**"" -- found 0 possible definitions" and t= his has seriously slow down my coding speed. Can you help me out by telling= me the possible causes as well as the possible solution to this error. I was browsing through the net when I came across the solution provided to = the similar problem. I adopted the solution but unfortunately it doesn't un= ravel the problem. Best regards, Adetola Akinwale. From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: MOD operator Date: Wed, 20 May 2015 10:34:34 -0400 Organization: Alacron, Inc. Lines: 19 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 May 2015 14:32:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="10714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++G4t+JDV4WcSTSnmQvkIkswRQD513jG8=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ZsW3HRuHKVhD0M7GMxvVopRwRgI= Xref: mx02.eternal-september.org comp.lang.vhdl:8276 theultimateiq@gmail.com wrote: > Dear Guilherme, > > I have been working on implementing a main memory for days now but it keeps showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't determine definition of operator ""**"" -- found 0 possible definitions" and this has seriously slow down my coding speed. Can you help me out by telling me the possible causes as well as the possible solution to this error. > > I was browsing through the net when I came across the solution provided to the similar problem. I adopted the solution but unfortunately it doesn't unravel the problem. > > Best regards, > > Adetola Akinwale. Sounds like a library issue. What libraries are you using in the design? One thing to note is that the error message may also be misleading. Sometimes "found 0 definitions" really means that it found multiple definitions (from different libraries) and has no way to determine which to use. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.66.118.198 with SMTP id ko6mr47777305pab.28.1432136782264; Wed, 20 May 2015 08:46:22 -0700 (PDT) X-Received: by 10.182.19.194 with SMTP id h2mr247580obe.41.1432136782180; Wed, 20 May 2015 08:46:22 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!h15no7010035igd.0!news-out.google.com!kd3ni22899igb.0!nntp.google.com!j8no6893627igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 20 May 2015 08:46:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.36 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: MOD operator From: Andy Injection-Date: Wed, 20 May 2015 15:46:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:8277 You didn't say what types of data you are supplying as operands. "**" may only be defined for integer and real. Andy From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: MOD operator Date: Wed, 20 May 2015 12:22:18 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 20 May 2015 16:21:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="5505"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zsrbISsnIk3/7oV2wP4Xq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:SkGURjwibcqUPSfVptPp6seHVns= Xref: mx02.eternal-september.org comp.lang.vhdl:8278 On 5/19/2015 8:45 AM, theultimateiq@gmail.com wrote: > Dear Guilherme, > > I have been working on implementing a main memory for days now but it keeps showing error: "Error (10327): VHDL error at memory_pkg.vhd(16): can't determine definition of operator ""**"" -- found 0 possible definitions" and this has seriously slow down my coding speed. Can you help me out by telling me the possible causes as well as the possible solution to this error. > > I was browsing through the net when I came across the solution provided to the similar problem. I adopted the solution but unfortunately it doesn't unravel the problem. I'm a bit confused. Your subject is about the MOD operator but you list the exponentiation operator? Can you give us some more info? What are your data types? Show us how the operator is used. -- Rick From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.67.23.36 with SMTP id hx4mr2623968pad.45.1432206907848; Thu, 21 May 2015 04:15:07 -0700 (PDT) X-Received: by 10.50.152.102 with SMTP id ux6mr41624igb.0.1432206907782; Thu, 21 May 2015 04:15:07 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!bcyclone01.am1.xlned.com!bcyclone01.am1.xlned.com!lightspeed.eweka.nl!lightspeed.eweka.nl!j8no7377791igd.0!news-out.google.com!n7ni40127igk.0!nntp.google.com!j8no7377789igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 May 2015 04:15:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Do you think my code is right on DFF with only variable usage From: fl Injection-Date: Thu, 21 May 2015 11:15:07 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Body-CRC: 3344972750 X-Received-Bytes: 1836 Lines: 32 Xref: mx02.eternal-september.org comp.lang.vhdl:8279 Hi, I see a question online: how will u write d ff using variables alone Below is my VHDL code. Because I do not see any specialties in the code, I suspect that the code is not it is supposed to be. What is your opinion on the question? Thanks, .................. process(CLR,PRE,CLK) --process with sensitivity list. variable v_d: std_ulogic := '0'; begin if (CLR = '1') then --Asynchronous clear input v_d := '0'; else if(PRE = '1') then --Asynchronous set input v_d := '1'; else if ( CE = '1' and falling_edge(CLK) ) then v_d := '1'; end if; end if; end if; Q <= v_d; end process; From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.236.19.51 with SMTP id m39mr3040908yhm.31.1432210095288; Thu, 21 May 2015 05:08:15 -0700 (PDT) X-Received: by 10.50.7.101 with SMTP id i5mr563257iga.15.1432210095236; Thu, 21 May 2015 05:08:15 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3017600qgd.1!news-out.google.com!n7ni40167igk.0!nntp.google.com!j8no7396134igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 21 May 2015 05:08:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Do you think my code is right on DFF with only variable usage From: KJ Injection-Date: Thu, 21 May 2015 12:08:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 27 Xref: mx02.eternal-september.org comp.lang.vhdl:8280 On Thursday, May 21, 2015 at 7:15:11 AM UTC-4, fl wrote: > Hi, >=20 > I see a question online: >=20 > how will u write d ff using variables alone >=20 > Below is my VHDL code. Because I do not see any specialties in the code, > I suspect that the code is not it is supposed to be.=20 >=20 > What is your opinion on the question? >=20 >=20 1. You didn't actually use the 'D' input of the flip flop. Corrected code = is: if ( CE =3D '1' and falling_edge(CLK) ) then=20 v_d :=3D d; -- OLD v_d :=3D '1';=20 end if; 2. The assignment "Q <=3D v_d" makes use of a signal which violates your st= atement of "using variables alone". Obviously in order to be able to use t= he output of the flip flop outside of the process you have to use a signal,= so what exactly is your point of trying to have a process that supposedly = only uses variables (but doesn't). Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.182.79.234 with SMTP id m10mr10452780obx.22.1432302956849; Fri, 22 May 2015 06:55:56 -0700 (PDT) X-Received: by 10.50.18.20 with SMTP id s20mr94722igd.14.1432302956787; Fri, 22 May 2015 06:55:56 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no7897880igd.0!news-out.google.com!n7ni41145igk.0!nntp.google.com!j8no7897872igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 06:55:56 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What meaning of two '#'s in a to_signed function? From: fl Injection-Date: Fri, 22 May 2015 13:55:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8281 Hi, I see the following VHDL code: in5_out1_re <= to_signed(2#0000000000#, 10); What meaning of the two '#'s above? Thanks From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.67.14.194 with SMTP id fi2mr10230887pad.29.1432308683864; Fri, 22 May 2015 08:31:23 -0700 (PDT) X-Received: by 10.50.64.179 with SMTP id p19mr83483igs.6.1432308683775; Fri, 22 May 2015 08:31:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7608033igd.0!news-out.google.com!n7ni41200igk.0!nntp.google.com!j8no7937657igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 08:31:23 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d245057-e57c-46e4-ae07-978ed67253d7@googlegroups.com> Subject: Re: What meaning of two '#'s in a to_signed function? From: KJ Injection-Date: Fri, 22 May 2015 15:31:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8282 On Friday, May 22, 2015 at 9:55:59 AM UTC-4, fl wrote: > Hi, > > I see the following VHDL code: > > > in5_out1_re <= to_signed(2#0000000000#, 10); > > > What meaning of the two '#'s above? > > Thanks VHDL allows you to specify a base for a numeric literal. So if you want the number 65535, you can specify it as 65535 -- Implicit base 10 10#65535# -- Explicit base 10 16#FFFF# -- Hex 8#177777# -- Octal 2#1111111111111111# -- Binary The # symbol delimits the beginning and end of the numeric literal. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.50.66.167 with SMTP id g7mr8865215igt.11.1432348270397; Fri, 22 May 2015 19:31:10 -0700 (PDT) X-Received: by 10.50.43.129 with SMTP id w1mr176380igl.0.1432348270342; Fri, 22 May 2015 19:31:10 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no7726971igd.0!news-out.google.com!kd3ni25172igb.0!nntp.google.com!j8no8154009igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 22 May 2015 19:31:09 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Subject: What return value should be besides '0' and '1' for this function? From: fl Injection-Date: Sat, 23 May 2015 02:31:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8283 Hi, I read the following code. I know that std_logic has value '0', '1', 'Z' and 'X' etc. There are only two values are considered below. Do you think it is an imperfect function or not? Thanks, FUNCTION to_integer( x : IN std_logic) RETURN integer IS VARIABLE int: integer; BEGIN IF x = '0' THEN int := 0; ELSE int := 1; END IF; RETURN int; END; From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What return value should be besides '0' and '1' for this function? Date: Fri, 22 May 2015 22:40:06 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 23 May 2015 02:38:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25707"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LurDKR+04k2KrYUgguMeW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Cancel-Lock: sha1:DIiZdOQj7EuaUnXMUg2ciyM7l+A= Xref: mx02.eternal-september.org comp.lang.vhdl:8284 On 5/22/2015 10:31 PM, fl wrote: > Hi, > > I read the following code. I know that std_logic has value '0', '1', 'Z' and > 'X' etc. > > There are only two values are considered below. Do you think it is an > imperfect function or not? > > > Thanks, > > > > > FUNCTION to_integer( x : IN std_logic) RETURN integer IS > VARIABLE int: integer; > BEGIN > IF x = '0' THEN > int := 0; > ELSE > int := 1; > END IF; > RETURN int; > END; Not sure why you say only two values are "considered". The input can be any of a number of states and all are translated to an integer 1 except for the input of '0' which is translated to 0. Is that what you want? std_logic can also be 'H' or 'L' which are often equated to '1' and '0' respectively. -- Rick From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: What return value should be besides '0' and '1' for this function? Date: Sat, 23 May 2015 09:52:30 +0000 (UTC) Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 23 May 2015 09:52:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="29105"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18lQmJF0ner7xW18z/6u+ozwo2vUjJTXsU=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:PnbvPwQIHht8zbHiJ93A3zJSMDM= Xref: mx02.eternal-september.org comp.lang.vhdl:8285 On Fri, 22 May 2015 19:31:09 -0700, fl wrote: > Hi, > There are only two values are considered below. Do you think it is an > imperfect function or not? > As Rickman hints, this function is definitely erroneous in converting 'L' to '1'. If you are only allowed 0 and 1 as return values, there is no choice but to resolve all the others 'U','Z' etc to either 0 or 1, and your choice to resolve them (except for 'L') as 1 is probably as good as any. I would recommend declaring a new Integer type (or at the very least a subtype) restricted in range to (0 to 1) and return that type, to make it crystal clear what this function does (and to catch unintended errors such as passing 2 (or -2143863148) as a value to code which was only written to handle 0,1. -- Brian From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.182.16.163 with SMTP id h3mr20074324obd.14.1432432052966; Sat, 23 May 2015 18:47:32 -0700 (PDT) X-Received: by 10.50.8.7 with SMTP id n7mr238009iga.15.1432432052950; Sat, 23 May 2015 18:47:32 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no8581654igd.0!news-out.google.com!kd3ni26054igb.0!nntp.google.com!j8no8581647igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 May 2015 18:47:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 References: <19e831f3-7aee-4231-8b8e-a6b7e9d79bcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What return value should be besides '0' and '1' for this function? From: fl Injection-Date: Sun, 24 May 2015 01:47:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8286 On Saturday, May 23, 2015 at 2:53:43 AM UTC-7, Brian Drummond wrote: > On Fri, 22 May 2015 19:31:09 -0700, fl wrote: > > > Hi, > > > There are only two values are considered below. Do you think it is an > > imperfect function or not? > > > > As Rickman hints, this function is definitely erroneous in converting 'L' > to '1'. > > If you are only allowed 0 and 1 as return values, there is no choice but > to resolve all the others 'U','Z' etc to either 0 or 1, and your choice > to resolve them (except for 'L') as 1 is probably as good as any. > > I would recommend declaring a new Integer type (or at the very least a > subtype) restricted in range to (0 to 1) and return that type, to make it > crystal clear what this function does (and to catch unintended errors > such as passing 2 (or -2143863148) as a value to code which was only > written to handle 0,1. > > -- Brian Great thanks to both of you. From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.236.61.230 with SMTP id w66mr19956806yhc.26.1432433313199; Sat, 23 May 2015 19:08:33 -0700 (PDT) X-Received: by 10.50.79.164 with SMTP id k4mr238550igx.6.1432433313150; Sat, 23 May 2015 19:08:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3477131qgd.0!news-out.google.com!kd3ni26054igb.0!nntp.google.com!j8no8585730igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 23 May 2015 19:08:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Subject: What is your VHDL design flow for a complex project? From: fl Injection-Date: Sun, 24 May 2015 02:08:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2225 X-Received-Body-CRC: 2090543819 Xref: mx02.eternal-september.org comp.lang.vhdl:8287 Hi, I have quite several years of digital logic design, days in TTL and CPLD. I even designed several small FPGA projects with VHDL. For complex FPGA project, I once used Xilinx System Generator on that project. I know the basics on FPGA design, such as timing constraints, some attributes about place and route. But I still feel very incompetence at VHDL on a large project. Of course, if I had the opportunity on a large VHDL project, I can get there sooner or later. Here I just want to get your advice on a large VHDL project procedures. Let me make my question a little clear. I guess it may work using top-down or down-top for a large project. My concern is mainly about clock timing at different modules (entities?). At System Generator, I can try to add z^-1 to some modules to get the desired result output. For a large VHDL project, it looks like much more troublesome on a delay unit trials. For example, on an FFT design, I think I should make the basic butterfly unit work. Then, I still feel uncomfortable on the following procedures to add the required index/address calculation using VHDL code. Could you give me some help? What procedures do you take on a large VHDL project? Thanks, From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Sat, 23 May 2015 23:20:42 -0400 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 24 May 2015 03:19:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13587"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Fo0cWrSs3B7vmDdZs06mF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> Cancel-Lock: sha1:xd0HVHr2FwW6qjlZ9/8vqXz9uVg= Xref: mx02.eternal-september.org comp.lang.vhdl:8288 On 5/23/2015 10:08 PM, fl wrote: > Hi, > > I have quite several years of digital logic design, days in TTL and CPLD. I > even designed several small FPGA projects with VHDL. For complex FPGA project, > I once used Xilinx System Generator on that project. > > I know the basics on FPGA design, such as timing constraints, some attributes > about place and route. But I still feel very incompetence at VHDL on a large > project. Of course, if I had the opportunity on a large VHDL project, I can > get there sooner or later. Here I just want to get your advice on a large > VHDL project procedures. > > Let me make my question a little clear. I guess it may work using top-down > or down-top for a large project. My concern is mainly about clock timing at > different modules (entities?). At System Generator, I can try to add z^-1 to > some modules to get the desired result output. For a large VHDL project, it > looks like much more troublesome on a delay unit trials. For example, on an > FFT design, I think I should make the basic butterfly unit work. Then, I still > feel uncomfortable on the following procedures to add the required > index/address calculation using VHDL code. > > Could you give me some help? What procedures do you take on a large VHDL > project? I'm not sure what to tell you. I do most projects in a similar manner. I do a top down design with some idea of the complexity of each module. If modules are so complex that you have no idea of the pipeline delays you need to do more work on those modules to determine how fast they can run and how many pipeline delays there will be (register delays). Once you have that info, you can redesign the interconnect to keep everything synchronized. Some would call that bottom up implementation. I have always found block diagrams to be my friend and to help me understand all the relationships between modules. An FFT is actually easy to implement once you understand how they work. They often need pipelining to make them run fast. I have never found pipelining of a linear flow to be difficult. Do you have feedback paths that make your design more complex? What else are you using other than FFTs? -- Rick From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.141.23.133 with SMTP id z127mr3832527qhd.5.1432475032142; Sun, 24 May 2015 06:43:52 -0700 (PDT) X-Received: by 10.50.137.101 with SMTP id qh5mr264364igb.3.1432475032106; Sun, 24 May 2015 06:43:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no3548166qgd.1!news-out.google.com!n7ni42893igk.0!nntp.google.com!h15no8046995igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 24 May 2015 06:43:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.27.220.131; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 76.27.220.131 References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Subject: Re: What is your VHDL design flow for a complex project? From: fl Injection-Date: Sun, 24 May 2015 13:43:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 55 Xref: mx02.eternal-september.org comp.lang.vhdl:8289 On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: > On 5/23/2015 10:08 PM, fl wrote: > > Hi, > > > > I have quite several years of digital logic design, days in TTL and CPLD. I > > even designed several small FPGA projects with VHDL. For complex FPGA project, > > I once used Xilinx System Generator on that project. > > > > I know the basics on FPGA design, such as timing constraints, some attributes > > about place and route. But I still feel very incompetence at VHDL on a large > > project. Of course, if I had the opportunity on a large VHDL project, I can > > get there sooner or later. Here I just want to get your advice on a large > > VHDL project procedures. > > > > Let me make my question a little clear. I guess it may work using top-down > > or down-top for a large project. My concern is mainly about clock timing at > > different modules (entities?). At System Generator, I can try to add z^-1 to > > some modules to get the desired result output. For a large VHDL project, it > > looks like much more troublesome on a delay unit trials. For example, on an > > FFT design, I think I should make the basic butterfly unit work. Then, I still > > feel uncomfortable on the following procedures to add the required > > index/address calculation using VHDL code. > > > > Could you give me some help? What procedures do you take on a large VHDL > > project? > > I'm not sure what to tell you. I do most projects in a similar manner. > I do a top down design with some idea of the complexity of each > module. If modules are so complex that you have no idea of the pipeline > delays you need to do more work on those modules to determine how fast > they can run and how many pipeline delays there will be (register > delays). Once you have that info, you can redesign the interconnect to > keep everything synchronized. Some would call that bottom up > implementation. > > I have always found block diagrams to be my friend and to help me > understand all the relationships between modules. An FFT is actually > easy to implement once you understand how they work. They often need > pipelining to make them run fast. I have never found pipelining of a > linear flow to be difficult. Do you have feedback paths that make your > design more complex? What else are you using other than FFTs? > > -- > > Rick Thanks, Rick. I can imagine it could be more difficult when there is feedback for a high speed module. FFT has a simple, regular structure. For me, I am still in the phase of FFT. I know FFT and its coding in C, even in assembly code. I do not have time to finish a VHDL FFT yet. The main difficulties are about the memory addressing, twiddle coef selection etc. Yes, I need to be patient to work on these interconnect between memory, twiddle and multipliers. From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Sun, 24 May 2015 10:33:13 -0400 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 24 May 2015 14:32:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9535"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18STOxt2eAj+v6ATi6ojMgM" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Cancel-Lock: sha1:g0kp9RTUsVq9y5LAJsiiiajHQt0= Xref: mx02.eternal-september.org comp.lang.vhdl:8290 On 5/24/2015 9:43 AM, fl wrote: > On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: >> On 5/23/2015 10:08 PM, fl wrote: >>> Hi, >>> >>> I have quite several years of digital logic design, days in TTL and CPLD. I >>> even designed several small FPGA projects with VHDL. For complex FPGA project, >>> I once used Xilinx System Generator on that project. >>> >>> I know the basics on FPGA design, such as timing constraints, some attributes >>> about place and route. But I still feel very incompetence at VHDL on a large >>> project. Of course, if I had the opportunity on a large VHDL project, I can >>> get there sooner or later. Here I just want to get your advice on a large >>> VHDL project procedures. >>> >>> Let me make my question a little clear. I guess it may work using top-down >>> or down-top for a large project. My concern is mainly about clock timing at >>> different modules (entities?). At System Generator, I can try to add z^-1 to >>> some modules to get the desired result output. For a large VHDL project, it >>> looks like much more troublesome on a delay unit trials. For example, on an >>> FFT design, I think I should make the basic butterfly unit work. Then, I still >>> feel uncomfortable on the following procedures to add the required >>> index/address calculation using VHDL code. >>> >>> Could you give me some help? What procedures do you take on a large VHDL >>> project? >> >> I'm not sure what to tell you. I do most projects in a similar manner. >> I do a top down design with some idea of the complexity of each >> module. If modules are so complex that you have no idea of the pipeline >> delays you need to do more work on those modules to determine how fast >> they can run and how many pipeline delays there will be (register >> delays). Once you have that info, you can redesign the interconnect to >> keep everything synchronized. Some would call that bottom up >> implementation. >> >> I have always found block diagrams to be my friend and to help me >> understand all the relationships between modules. An FFT is actually >> easy to implement once you understand how they work. They often need >> pipelining to make them run fast. I have never found pipelining of a >> linear flow to be difficult. Do you have feedback paths that make your >> design more complex? What else are you using other than FFTs? >> >> -- >> >> Rick > > Thanks, Rick. I can imagine it could be more difficult when there is > feedback for a high speed module. FFT has a simple, regular structure. > For me, I am still in the phase of FFT. I know FFT and its coding in C, > even in assembly code. I do not have time to finish a VHDL FFT yet. The main > difficulties are about the memory addressing, twiddle coef selection etc. > Yes, I need to be patient to work on these interconnect between memory, > twiddle and multipliers. Maybe this stuff comes easier to me than most. I cut my teeth on signal processing back in the 80's working on array processors. They were rack cabinets of boards which did the same thing DSP chips do now. I was testing boards in the machine and so got to see and debug every part of the device at a micro level. I think the key to designing an FFT in hardware is much like these machines. First understand the timing of the multiplier. Then everything else will be to feed data to and from the multiplier so it never rests. -- Rick From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.50.114.129 with SMTP id jg1mr27880688igb.3.1432614803046; Mon, 25 May 2015 21:33:23 -0700 (PDT) X-Received: by 10.140.104.72 with SMTP id z66mr13734qge.14.1432614802877; Mon, 25 May 2015 21:33:22 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!j8no9543260igd.0!news-out.google.com!k20ni44933qgd.0!nntp.google.com!z60no3844919qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 25 May 2015 21:33:22 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.46.198.142; posting-account=fZovLAoAAAD3S-AUwPsJor4VbxwCeVmC NNTP-Posting-Host: 62.46.198.142 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> Subject: how to generate random time delays for simulation during compile time From: mubinicyer@gmail.com Injection-Date: Tue, 26 May 2015 04:33:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8291 I have ring oscilator design, I am generating 32 ring oscillators using fol= lowing code. How can I generate random time delays instead of loop variable= "i"? (I am sorry for code, it doesn't look like code formatted, I am writi= ng this post from mobile browser) for i in 0 to nr_entries-1 generate =20 multiple_n: w_entity=20 generic map (delay =3D> (i+1) * 1 ps , chain_len =3D> nr_chains) -- d= elay must be "random" from 100 to 300 ps port map ( rst_i =3D> s_rst, out_o =3D> s_inp(i) ); end generate; From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.42.129.20 with SMTP id o20mr37322269ics.19.1432671147366; Tue, 26 May 2015 13:12:27 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr359733qge.33.1432671147332; Tue, 26 May 2015 13:12:27 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no9902145igd.0!news-out.google.com!k20ni44948qgd.0!nntp.google.com!z60no3984277qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 13:12:27 -0700 (PDT) In-Reply-To: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=190.247.132.79; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 190.247.132.79 References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> Subject: Re: how to generate random time delays for simulation during compile time From: Leonardo Capossio Injection-Date: Tue, 26 May 2015 20:12:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8292 El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribi= =F3: > I have ring oscilator design, I am generating 32 ring oscillators using f= ollowing code. How can I generate random time delays instead of loop variab= le "i"? (I am sorry for code, it doesn't look like code formatted, I am wri= ting this post from mobile browser) >=20 > for i in 0 to nr_entries-1 generate =20 > multiple_n: w_entity=20 > generic map (delay =3D> (i+1) * 1 ps , chain_len =3D> nr_chains) --= delay must be "random" from 100 to 300 ps > port map ( > rst_i =3D> s_rst, > out_o =3D> s_inp(i) > ); > end generate; A well known trick, a quick search returns: http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.h= tml From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.42.50.210 with SMTP id b18mr38362491icg.17.1432674782507; Tue, 26 May 2015 14:13:02 -0700 (PDT) X-Received: by 10.140.94.166 with SMTP id g35mr105969qge.1.1432674782329; Tue, 26 May 2015 14:13:02 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!j8no9924168igd.0!news-out.google.com!k20ni44951qgd.0!nntp.google.com!z60no3992918qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 14:13:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.112.103.16; posting-account=Uy1rkAoAAABZ1DIR2wcD1AFFThUQYsGJ NNTP-Posting-Host: 79.112.103.16 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Subject: Assign same signal in one block - Verilog From: george.isachi@gmail.com Injection-Date: Tue, 26 May 2015 21:13:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8293 Hi, I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look: parameter VALID_BIT = 0; [...] if(data_in_cfg[VALID_BIT] == 0) begin data_out_cfg <= {DATA_WIDTH{1'b1}}; data_out_cfg[VALID_BIT] <= 1'b0; end else begin data_out_cfg <= (data_in_cfg >> BIT_NUMBERS); data_out_cfg[VALID_BIT] <= 1'b1; end From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp1-1.free.fr!not-for-mail Date: Tue, 26 May 2015 23:49:21 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: how to generate random time delays for simulation during compile time References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> In-Reply-To: <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 23 Message-ID: <5564ea61$0$2981$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 26 May 2015 23:49:21 CEST NNTP-Posting-Host: 88.185.146.198 X-Trace: 1432676961 news-3.free.fr 2981 88.185.146.198:1836 X-Complaints-To: abuse@proxad.net Xref: mx02.eternal-september.org comp.lang.vhdl:8294 Le 26/05/2015 22:12, Leonardo Capossio a écrit : > El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribió: >> I have ring oscilator design, I am generating 32 ring oscillators using following code. How can I generate random time delays instead of loop variable "i"? (I am sorry for code, it doesn't look like code formatted, I am writing this post from mobile browser) >> >> for i in 0 to nr_entries-1 generate >> multiple_n: w_entity >> generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- delay must be "random" from 100 to 300 ps >> port map ( >> rst_i => s_rst, >> out_o => s_inp(i) >> ); >> end generate; > > A well known trick, a quick search returns: > http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.html Very nice but it won't work for a generic parameter, as requested by the original poster. It is probably possible to use the UNIFORM procedure from the math_real package to generate pseudo-random numbers inside the for...generate loop. Nicolas From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.236.61.82 with SMTP id v58mr38816566yhc.15.1432693469747; Tue, 26 May 2015 19:24:29 -0700 (PDT) X-Received: by 10.182.219.42 with SMTP id pl10mr179577obc.29.1432693469631; Tue, 26 May 2015 19:24:29 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no4021260qgd.1!news-out.google.com!kd3ni28818igb.0!nntp.google.com!m20no1786iga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 26 May 2015 19:24:29 -0700 (PDT) In-Reply-To: <5564ea61$0$2981$426a74cc@news.free.fr> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <202713bb-2243-4ea2-9487-7c9f92dbc0d6@googlegroups.com> <91cd81d4-e919-4232-87a9-f91d20d56e8e@googlegroups.com> <5564ea61$0$2981$426a74cc@news.free.fr> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03916ea5-bdd3-4918-bcbb-0e4c7b90c9bf@googlegroups.com> Subject: Re: how to generate random time delays for simulation during compile time From: Andy Injection-Date: Wed, 27 May 2015 02:24:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:8295 Take a look at Open Source VHDL Verification Methodology (osvvm.org). It provides constrained randomization, coverage modeling and more. You need to declare constant(s) initialized by function calls, then map the generics to the constants. Andy From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Assign same signal in one block - Verilog Followup-To: comp.lang.verilog Date: Wed, 27 May 2015 08:47:22 -0400 Organization: Alacron, Inc. Lines: 28 Message-ID: References: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 27 May 2015 12:45:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="32264"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+h7NFgYPXbxbCRiMl/rv1e4D8gzNF7G10=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <42df585d-1ebc-444c-a785-cf8cbf043b8a@googlegroups.com> Cancel-Lock: sha1:z4G5xYDSdAljaaNUNjV6uisZQ90= Xref: mx02.eternal-september.org comp.lang.vhdl:8296 george.isachi@gmail.com wrote: > Hi, > > I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look: > > parameter VALID_BIT = 0; > [...] > if(data_in_cfg[VALID_BIT] == 0) begin > data_out_cfg <= {DATA_WIDTH{1'b1}}; > data_out_cfg[VALID_BIT] <= 1'b0; > end else begin > data_out_cfg <= (data_in_cfg >> BIT_NUMBERS); > data_out_cfg[VALID_BIT] <= 1'b1; > end You do realize this is a VHDL newsgroup - setting follow-up to comp.lang.verilog It's not clear what your question is. Are you talking about first assigning all bits of data_out_cfg and then assigning only the VALID bit? That's perfectly acceptable and the final assigned value would be the same as if you only assigned bits other than the VALID bit in the first assignment (no "double" assignment). i.e. the last assignment "wins" when you make more than one. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.52.168.130 with SMTP id zw2mr28418660vdb.5.1433161300355; Mon, 01 Jun 2015 05:21:40 -0700 (PDT) X-Received: by 10.140.28.73 with SMTP id 67mr260427qgy.36.1433161300257; Mon, 01 Jun 2015 05:21:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z60no4982985qgd.1!news-out.google.com!4ni134qgh.1!nntp.google.com!z60no4982979qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 1 Jun 2015 05:21:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <11cc4d88-cc6f-4cd9-9822-84690d0aa3bb@googlegroups.com> <3d5223cc-06c1-487a-b039-3abb7d6caced@googlegroups.com> <236c4dcb-ae8f-40ef-ad22-b1b5e823eb87@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Open source unit testing framework release From: olof.kraigher@gmail.com Injection-Date: Mon, 01 Jun 2015 12:21:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 3 Xref: mx02.eternal-september.org comp.lang.vhdl:8297 We have now officially added VUnit support for GHDL. Big thanks to Tristan who fixed many bugs and implemented some nice features for this to be possible. I would like to recommend anyone who has not used GHDL for a while to take a look at it again as there have been major improvements and lots of VHDL 2008 support added lately. From newsfish@newsfish Tue Dec 29 16:43:50 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 02 Jun 2015 17:12:59 -0500 From: Irhamish Subject: Re: Carry Save Adder (CSA) Verilog code Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: 5d78c448-4830-45c4-bfea-e5fb0898b98a References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> Message-ID: Date: Tue, 02 Jun 2015 17:12:59 -0500 Lines: 5 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-HNc5CNEhdi6PaDRmMaT384zbpgUKTNx0WW6S2J7ldSPGyX1NtbOeEd1fcOW/crHPmxEEnFKUmAJxSK2!U5L3p4VyCCXrfhrBRiGxo2zlQTzbaJY7lNQglSYavwHZNvf14SnzPAxvp5y4JD0Pq3Jv/CFUvCMZ!6h4= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1045 Xref: mx02.eternal-september.org comp.lang.vhdl:8298 need 3 to 2 compresser..!! with figures From newsfish@newsfish Tue Dec 29 16:43:50 2015 X-Received: by 10.13.202.211 with SMTP id m202mr18078255ywd.19.1433768070514; Mon, 08 Jun 2015 05:54:30 -0700 (PDT) X-Received: by 10.50.4.34 with SMTP id h2mr160843igh.7.1433768070485; Mon, 08 Jun 2015 05:54:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no5829qgd.0!news-out.google.com!n7ni4248igk.0!nntp.google.com!h15no62756igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jun 2015 05:54:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=138.128.222.98; posting-account=XUZW3woAAAAvqjhEa35ql7jqrM4YjoTn NNTP-Posting-Host: 138.128.222.98 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Subject: verilog syntax check From: Yang Luo Injection-Date: Mon, 08 Jun 2015 12:54:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: mx02.eternal-september.org comp.lang.vhdl:8299 I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict. There are some examples: 1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line. Example code: input [D_SIZE: 0] i_a; wire signed [D_SIZE: 0] w_a; assign w_ia = i_a; 2) When using unassigned variable , the same situation with above. Example code: wire signed [D_SIZE: 0] w_ib; wire signed [D_SIZE: 0] w_id; wire signed [D_SIZE: 0] w_bd; assign w_bd = w_ib - w_id; Question: How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do? Another question: Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled? From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: verilog syntax check Date: Mon, 08 Jun 2015 13:34:12 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 8 Jun 2015 17:32:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="11456"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/+Fzm/PxYqvm4U0nJprjTx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Cancel-Lock: sha1:Afc7PYVDkgrFSqKUYUXGDJOYvLI= Xref: mx02.eternal-september.org comp.lang.vhdl:8300 On 6/8/2015 8:54 AM, Yang Luo wrote: > I'm using modelsim se 10.1c. I find that modelsim for syntax checking is not strict. > There are some examples: > 1) I use default settings to build a project. There is no error or warning whenn compiling but I used an undefined variable, only when simulating the signal is red line. > Example code: > input [D_SIZE: 0] i_a; > wire signed [D_SIZE: 0] w_a; > assign w_ia = i_a; > 2) When using unassigned variable , the same situation with above. > Example code: > wire signed [D_SIZE: 0] w_ib; > wire signed [D_SIZE: 0] w_id; > wire signed [D_SIZE: 0] w_bd; > assign w_bd = w_ib - w_id; > Question: > How should I do to get more strict syntax checking in modelsim? If modelsim cannot get strict checking, is there other software can do? > Another question: > Modelsim rebuilding and cleanup project, how to operate? how to operate that I can know the compilation is all recompiled? I see you posted this to the verilog and VHDL groups. You might try posting to the FPGA group instead of VHDL. -- Rick From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.50.50.97 with SMTP id b1mr20053656igo.9.1433795257404; Mon, 08 Jun 2015 13:27:37 -0700 (PDT) X-Received: by 10.50.72.42 with SMTP id a10mr193856igv.14.1433795257374; Mon, 08 Jun 2015 13:27:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no251835igd.0!news-out.google.com!kd3ni458igb.0!nntp.google.com!h15no251833igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 8 Jun 2015 13:27:36 -0700 (PDT) In-Reply-To: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: <47c9fc4f-faf1-4ed0-8333-af132b083574@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6b20d495-2426-4e83-884a-e2819aa93d25@googlegroups.com> Subject: Re: verilog syntax check From: KJ Injection-Date: Mon, 08 Jun 2015 20:27:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8301 On Monday, June 8, 2015 at 8:54:31 AM UTC-4, Yang Luo wrote: > Question: > How should I do to get more strict syntax checking in modelsim? If models= im cannot get strict checking, is there other software can do? If your code is intended to be synthesized at some point, then a relatively= easy to catch unconnected inputs like you have in your code is simply to r= un it through synthesis (i.e. Quartus if targeting Altera). An unconnected= input during synthesis will cause a warning to be reported. Peruse the li= st of warnings and go from there. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.43.69.83 with SMTP id yb19mr7719636icb.32.1433971557665; Wed, 10 Jun 2015 14:25:57 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr102819qgg.21.1433971557539; Wed, 10 Jun 2015 14:25:57 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed2a.news.xs4all.nl!xs4all!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no1266841igd.0!news-out.google.com!k20ni414qgd.0!nntp.google.com!q107no471996qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 10 Jun 2015 14:25:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <138ebd46-75c7-4a5e-bcb7-6c29bf3b4d30@googlegroups.com> Subject: Increased test performance with VUnit From: Lars Asplund Injection-Date: Wed, 10 Jun 2015 21:25:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 42 Xref: mx02.eternal-september.org comp.lang.vhdl:8302 VUnit, the open source unit testing framework for VHDL (https://github.com/= LarsAsplund/vunit), has now added support for multithreaded execution. Than= ks to the nature of unit testing with several independent test cases in eac= h testbench (test suite) it lends itself to parallel execution. Simply take= your VUnit run script and add the -p option to specify the number of threa= ds/test cases you want to run in parallel. python run.py -p For example, the figures below show the relative speed improvements for dif= ferent number of threads when running on my quad core laptop with ModelSim-= Altera Starter Edition under Windows. My script runs a couple of testbenche= s, each with several test cases, for a total of about 60 test cases. If my = simulation threads never blocked on anything like I/O it wouldn't be much p= oint in using more threads than the number of cores but since that's not th= e case the example shows improved performance beyond that point. Eventually= you don't get any more performance by adding threads and there are differe= nt reasons for that. You can't be faster than your slowest test case, there= 's no point in having more threads than the number of test cases, at some p= oint the overhead of another thread is larger than the gain of the added pa= rallelism. You have to experiment to find your optimum. number of threads: speed improvement 1: 1.0x 2: 1.8x 3: 2.5x 4: 2.8x 5: 3.1x 6: 3.3x 7: 3.4x 8: 3.4x 9: 3.5x 10: 3.5x 11: 3.6x 12: 3.5x 13: 3.5x 14: 3.4x 15: 3.4x 16: 3.3x 17: 3.3x 18: 3.3x 19: 3.2x 20: 3.1x From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.43.69.83 with SMTP id yb19mr19264218icb.32.1434116383590; Fri, 12 Jun 2015 06:39:43 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr215692qgf.7.1434116383449; Fri, 12 Jun 2015 06:39:43 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2100715igd.0!news-out.google.com!k20ni1129qgd.0!nntp.google.com!z60no823261qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 12 Jun 2015 06:39:43 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.114.130; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.114.130 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Subject: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Fri, 12 Jun 2015 13:39:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8303 According to the Wilson Report (2014 Wilson Research Group Functional Verif= ication Study) on average 50% of FPGA designers' time is spent on verificat= ion, and almost half of that verification time is spent on debugging. This = means: 1. Good reports for unexpected design behaviour is critical. 2. Good progress reporting is also critical. 3. Good basic testbench features are required Thus we need a library with good functionality for mismatch reporting, prog= ress reporting and for checks etc. that are needed for every single testben= ch; like=20 - checking value against expected - waiting for something to happen - with a timeout - checking stability of a signal - waiting for a signal to be stable for a given time (with timeout) The only free library library (to my knowledge) to provide all this functio= nality is Bitvis Utility Library.=20 A bonus feature of this library is that the user threshold is extremely low= , as this has been a main goal throughout the development. Advanced feature= s are available when you need them. The library is free and open source, - and you will be up and running withi= n 20 min (by browsing through the downloadable PPT presentation). The library has been checked to work with simulators from Mentor, Aldec and= Xilinx. Version 2.5 with lots of new functionality was just published. If this sounds interesting, you should read the below intro. You can download the library and PPT from http://bitvis.no/resources/utilit= y-library-download/ without any registration. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D TB Purpose The purpose of a testbench (TB) is to check the behaviour of your DUT (Devi= ce Under Test). This really goes without saying, - but sometimes stating th= e obvious is really needed. For any testbench you always provide stimuli an= d check the response. Sometimes this is a simple operation, and sometimes t= his is really complex. Most testbenches do however have some basic checking= aspects in common. Basic Checking Aspects Checking a signal value against an expected value - sometimes with partial = don't care or a margin Checking stability on a given signal (that a certain time has elapsed since= the last signal event) Waiting for a signal change or specific value on a signal Improving TB development efficiency and quality The checks above are easily implemented in VHDL, or better - in self-made s= ub-programs. The challenge is not to make the actual procedures and functio= ns, but to add functionality to these checks to allow far more efficient TB= development and problem debugging. The following are some examples that wi= ll significantly speed up your FPGA development: Reporting the actual mismatch - like 'was 0xFE, but expected 0xFF' yields i= mportant debug-information Reporting what is actually being checked - like 'Checking correct CRC for p= acket 1' yields another piece of important information Reporting the source of a failing mismatch leads the problem search in the = right direction (e.g. problem in UART 1) A positive acknowledge when passing the test is very useful when building t= he TB, BFMs, Analysers, etc Allowing the positive acknowledge to be filtered away is really useful when= this part is working Counting alerts (errors, warnings, etc) and potentially stopping on N error= s allows good debugging flexibility Ignoring certain alerts is useful when provoking a misbehaviour Timeout on waiting for an event to happen inside a given time window - with= a proper message - rather than hanging on a 'wait until' Adding this functionality makes everything simpler, faster and better. The = TB code will be more understandable (by anyone) and far simpler to maintain= and extend. Debugging of both the DUT and TB will be far more efficient. T= he progress report will be more understandable and make more sense to anyon= e. And the quality of the design and the TB will increase significantly. A major impact on TB development Now going back to the introduction. The sad fact is that for most testbench= es a lot of development time is wasted and the quality of the TB is insuffi= cient, and a major reason for this is the lack of a structured approach to = logging and checking. The good news is that all this functionality is avail= able for free through Bitvis Utility Library. Bitvis Utility Library is a f= ree, open source VHDL library that will yield a major efficiency and qualit= y improvement for almost all FPGA (or ASIC) development. The library has be= en downloaded by developers all over the world, and the feedback has been v= ery good - also from specialists in the VHDL community. Bitvis Utility Library also has excellent support for logging/reporting and= verbosity control (see a previous post on LinkedIn). The combination of th= e logging/reporting/verbosity and checking support - all provided with Bitv= is Utility Library - now makes it possible to develop more structured testb= enches, with better verification of DUT functionality and better simulation= transcripts with progress report and debug-support - and at the same time = reduce the development workload and schedule. For more advanced testbenches you might need additional support and TB stru= cture for coverage (e.g. via OSVVM) and simultaneous access (stimuli/check)= (e.g. via UVVM) on multiple interfaces, but you still need the functionali= ty provided by Bitvis Utility Library as your base. A very low user threshold An essential feature of this library is that it has an extremely low user t= hreshold, and at the same time has advanced options available when needed f= or more complex testbenches. You will be up and running, making far better = testbenches in less than one hour. Invest 10 minutes to browse through our powerpoint presentations on 'Making= a simple, structured and efficient VHDL testbench - Step-by-step' and/or '= Bitvis Utility Library Concepts and usage', both available for download (wi= th no registration) from http://bitvis.no/resources/utility-library-downloa= d/. The library may be downloaded from the same page. The library is free, and there is no catch. Enjoy :-) From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 12 Jun 2015 14:28:29 GMT Lines: 47 Message-ID: References: X-Trace: individual.net lyDO62yrMKUkMB2UU+ve7w+lXcWMK8YnPokVnhNdXuFrHrf4QQ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Y2i1RvbateQ8O3+dUNkf/aQI4xo= sha1:cf4uz5V3BoIokWpFkFGmQtHG02s= User-Agent: tin/2.1.1-20120623 ("Mulindry") (UNIX) (Linux/3.2.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8304 Hi everyeone, last attempt... I'm cross-posting here from the SystemC Accellera Forum and comp.arch.fpga since I *hope* I'm going to receive more feedback here than there. alb wrote: [] > I've recently started to wonder what kind of project I can start with > to get my hands on SystemC and TLM. I know there are tons of tutorials, > getting started like materials, open libraries, open platforms and I > believe I can get my head around most of that stuff, but one thing I'd > like to get advice on is how complex should be my first project to make > my learning process more effective. > > I've started proposing modelling with SystemC in my group because we > often lack of a tool to explore the bottle neck of our architectures > and realize about it too late down in the development phase. I've got > granted a 30% of my time for the next 6 months to learn SystemC and TLM > and come up with a reasonably shaped showcase. > > One of our core challenges is mass storage (for space applications), > therefore I thought about modelling a possible architecture involving > NAND Flash storage handled through some processor and high speed data > link. > > Most of the elements of this fictitious architecture are somehow > available on the net and I would have started plugging things together > for a start. > > Does this sound too naive, or is this application too complex to be > achievable in such a short time? > > One critical element in this task would be to make the management > understand how much they should invest in 'training/learning' before > getting some benefit out of it. > > Any pointer/suggestion/comment is highly appreciated, > > Al > -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: Sat, 13 Jun 2015 11:52:50 +0000 (UTC) Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 13 Jun 2015 11:52:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="12069"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX183SDvkXFNUdfFBpsHZihZxcr1rpS9/o0s=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:F3x4V6mfKLuSC2hUBUKNljPf2UA= Xref: mx02.eternal-september.org comp.lang.vhdl:8305 On Fri, 12 Jun 2015 14:28:29 +0000, alb wrote: > Hi everyeone, last attempt... > > I'm cross-posting here from the SystemC Accellera Forum and > comp.arch.fpga since I *hope* I'm going to receive more feedback here > than there. Since you cross-posted to comp.lang.vhdl, the feedback you might expect is that AnythingC is likely to be too firmly based on a foundation of sand, and therefore an unnecessarily difficult road to hardware. at least that's my opinion, and it's why I do some relatively high level modelling in VHDL. Anything synthesisable via C is also potentially synthesisable via VHDL, with less room for compiler-diagnosable errors. Where this potential isn't translated into practice, we need to nudge the synth tool vendors a little... Where VHDL gives up I use a very similar language, but in which I can for example create arbitrary fixed point types (natively, not via extensions) write generic algorithms, and instantiate them with both float and these fixed types to evaluate accuracy, determine the word lengths required, and so on. That gives me a sound basis for a trivial port to VHDL. It also gives me full object orientation where I need it, and access via import mechanisms to anything written in C or C++. Design-by-contract via pre/postconditions is also available though I haven't used that yet, nor have I used the formal proof extensions, but these are much more attractive options to me than anything I've seen offered by System-C. Unfortunately this doesn't help you with System-C. -- Brian From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source Date: Sat, 13 Jun 2015 12:05:43 +0000 (UTC) Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 13 Jun 2015 12:05:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="12069"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19aABQLBKRxr6pYc62Go9mf+4zWxylOggQ=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:/wi0UUBQ/6iHU/LUUuTr5VvdP9o= Xref: mx02.eternal-september.org comp.lang.vhdl:8306 On Fri, 12 Jun 2015 06:39:43 -0700, espen.tallaksen wrote: > According to the Wilson Report (2014 Wilson Research Group Functional > Verification Study) on average 50% of FPGA designers' time is spent on > verification, and almost half of that verification time is spent on > debugging. This means: > > 1. Good reports for unexpected design behaviour is critical. > 2. Good progress reporting is also critical. > 3. Good basic testbench features are required > > Thus we need a library with good functionality for mismatch reporting, > progress reporting and for checks etc. that are needed for every single > testbench; like - checking value against expected - waiting for > something to happen - with a timeout - checking stability of a signal - > waiting for a signal to be stable for a given time (with timeout) > > The only free library library (to my knowledge) to provide all this > functionality is Bitvis Utility Library. It's great to see a resurgence in VHDL tool development! How does it compare with other modern VHDL testbench libraries like OSVVM and Vunit? Especially great to see lively competition between open-source tools, where it sometimes feels like the commercial vendors wish VHDL would die quietly... http://osvvm.org/ https://github.com/LarsAsplund/vunit Have you tried it with GHDL and GTKwave, to keep the whole simulation toolchain open source? https://sourceforge.net/projects/ghdl-updates/ Both the above libraries now work with the leading edge of GHDL, and have pushed its VHDL-2008 support forwards so another GHDL release should happen soon. Tristan, ghdl's main developer, has been especially active lately in making this happen. So, any reports of incompatibilities between Bitvis and GHDL would be welcomed via https://sourceforge.net/p/ghdl-updates/tickets/?source=navbar Thanks, -- Brian From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.129.128.199 with SMTP id q190mr28345534ywf.44.1434231864241; Sat, 13 Jun 2015 14:44:24 -0700 (PDT) X-Received: by 10.182.44.163 with SMTP id f3mr157177obm.7.1434231864162; Sat, 13 Jun 2015 14:44:24 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1064671qgd.1!news-out.google.com!n7ni9344igk.0!nntp.google.com!h15no2746654igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 13 Jun 2015 14:44:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Sat, 13 Jun 2015 21:44:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8307 My two cents embedded below with "MK>": > at least that's my opinion, and it's why I do some relatively high level= =20 > modelling in VHDL. Anything synthesisable via C is also potentially=20 > synthesisable via VHDL, with less room for compiler-diagnosable errors.= =20 > Where this potential isn't translated into practice, we need to nudge the= =20 > synth tool vendors a little... MK> High level synthesis is a trend. Though there is still a long way to go= , I believe eventually the design methodology will evolve to HLS just as ho= w GL evolved to RTL. Some major EDA vendors are spending more and more effo= rt on developing HLS tools and some already get proven in real projects (se= e CtoS / Stratus for example). I'm not saying how good HLS is today, but le= arning SystemC can definitely give you some fresh ideas on those fancy stuf= f. Moreover, SystemC is not all about HLS. For examples: (1) It gives you the ability for fast prototyping / architecture exploring.= VHDL doesn't give you all the kits required for System level modeling and = the turnaround time for architecture exploring is not short with VHDL. (2) It has faster simulation speed. Although you can do some high level mod= eling with VHDL or Verilog, the simulation speed is not as fast as SystemC.= We've done some experiments on bringing up Linux on an ARM based SoC in si= mulation, with models coded up in SystemC and Verilog individually. One big= reason is the differences between the simulation engines. The VHDL simulat= ion engine almost has a fixed scheduling semantics and accuracy. In general= it cannot give you "coarse granularity" type of simulation (it may look li= ke, but the engine itself is not).=20 (3) It's much easier coding virtual platform with SystemC / TLM. Again, tak= ing the Linux bootup example and consider how complex it would be if modeli= ng all components with VHDL. Yes, you can have some IPs to accelerate the w= ork, but it's still much more complex than using C++. MK> Today it's really a trade-off between accuracy and speed when consideri= ng SystemC vs VHDL/Verilog. There are a lot of places where SystemC can hel= p you the most. Also, there is nothing to prevent you from doing mixed simu= lation. Actually TLM + RTL (some companies call it "soft hybrid") gets pret= ty popular these days. > Where VHDL gives up I use a very similar language, but in which I can for= =20 > example create arbitrary fixed point types (natively, not via extensions)= =20 > write generic algorithms, and instantiate them with both float and these= =20 > fixed types to evaluate accuracy, determine the word lengths required,=20 > and so on.=20 MK> Regarding the fixed point types, it's transparent to the user whether o= r not the type in SystemC is native. For generic programming there is no re= ason why SystemC cannot do it - it's C++ essentially therefore it comes wit= h the best GP tool kits. > It also gives me full object orientation where I need it, and access via= =20 > import mechanisms to anything written in C or C++. Design-by-contract via= =20 > pre/postconditions is also available though I haven't used that yet, nor= =20 > have I used the formal proof extensions, but these are much more=20 > attractive options to me than anything I've seen offered by System-C. MK> Design-by-contract is also achievable in C++ (although may not be that = attractive). For example, the Contract++ is already adopted by Boost. Again= SystemC itself is just a C++ library and there is nothing to prevent you f= rom using other C++ libraries.=20 From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.182.52.199 with SMTP id v7mr37241770obo.36.1434355856578; Mon, 15 Jun 2015 01:10:56 -0700 (PDT) X-Received: by 10.140.109.35 with SMTP id k32mr341701qgf.34.1434355856473; Mon, 15 Jun 2015 01:10:56 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no2808103igd.0!news-out.google.com!k20ni1860qgd.0!nntp.google.com!z60no1281913qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jun 2015 01:10:56 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.114.130; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.114.130 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 15 Jun 2015 08:10:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8308 > It's great to see a resurgence in VHDL tool development! >=20 > How does it compare with other modern VHDL testbench libraries like OSVVM= =20 > and Vunit? >=20 > Especially great to see lively competition between open-source tools,=20 > where it sometimes feels like the commercial vendors wish VHDL would die= =20 > quietly... >=20 > http://osvvm.org/ > https://github.com/LarsAsplund/vunit >=20 > Have you tried it with GHDL and GTKwave, to keep the whole simulation=20 > toolchain open source? >=20 > https://sourceforge.net/projects/ghdl-updates/ >=20 > Both the above libraries now work with the leading edge of GHDL, and have= =20 > pushed its VHDL-2008 support forwards so another GHDL release should=20 > happen soon. Tristan, ghdl's main developer, has been especially active= =20 > lately in making this happen. >=20 > So, any reports of incompatibilities between Bitvis and GHDL would be=20 > welcomed via=20 > https://sourceforge.net/p/ghdl-updates/tickets/?source=3Dnavbar >=20 > Thanks, > -- Brian Hi Brian, Bitvis Utility Library (BVUL) is complementary to OSVVM and Vunit - with so= me minor overlaps. The coverage and advanced random gen. of OSVVM and the u= nit test support of Vunit are great in combination with Bitvis Utility Libr= ary's checking/await and log/alert features. The main advantage with our li= brary is that it provides the functionality you need for every single VHDL = testbench independent of verification approach, - with a very low user thre= shold. We will soon make a new release of BVUL, where you can combine the coverage= and random generation of OSVVM seamlessly with BVUL, resulting in a major = improvement for more advanced testbenches. With respect to Vunit, Lars Asplund of Synective Labs (maintainer of Vunit)= stated already in February 2014 that he had used BVUL with Vunit and that = it works perfectly well. BVUL has been tested OK with Riviera Pro (Aldec), Modelsim (Mentor) and Viv= ado Sim (Xilinx). We can check compatibility with GHDL as well. (Currently we support a 2008, 2002 and 93 -version of BVUL, but we will soo= n only continue to develop the 2008 version.) Any feedback on BVUL is appreciated. -Espen From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.129.104.86 with SMTP id d83mr36415294ywc.12.1434364811506; Mon, 15 Jun 2015 03:40:11 -0700 (PDT) X-Received: by 10.140.19.170 with SMTP id 39mr31771qgh.9.1434364811468; Mon, 15 Jun 2015 03:40:11 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1302649qgd.1!news-out.google.com!4ni1697qgh.1!nntp.google.com!z60no1302647qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 15 Jun 2015 03:40:11 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <77978758-969d-4dcc-8c7f-d4469c024425@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 15 Jun 2015 10:40:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8309 Den m=E5ndag 15 juni 2015 kl. 10:10:59 UTC+2 skrev espen.t...@bitvis.no: > > It's great to see a resurgence in VHDL tool development! > >=20 > > How does it compare with other modern VHDL testbench libraries like OSV= VM=20 > > and Vunit? > >=20 > > Especially great to see lively competition between open-source tools,= =20 > > where it sometimes feels like the commercial vendors wish VHDL would di= e=20 > > quietly... > >=20 > > http://osvvm.org/ > > https://github.com/LarsAsplund/vunit > >=20 > > Have you tried it with GHDL and GTKwave, to keep the whole simulation= =20 > > toolchain open source? > >=20 > > https://sourceforge.net/projects/ghdl-updates/ > >=20 > > Both the above libraries now work with the leading edge of GHDL, and ha= ve=20 > > pushed its VHDL-2008 support forwards so another GHDL release should=20 > > happen soon. Tristan, ghdl's main developer, has been especially active= =20 > > lately in making this happen. > >=20 > > So, any reports of incompatibilities between Bitvis and GHDL would be= =20 > > welcomed via=20 > > https://sourceforge.net/p/ghdl-updates/tickets/?source=3Dnavbar > >=20 > > Thanks, > > -- Brian >=20 > Hi Brian, >=20 > Bitvis Utility Library (BVUL) is complementary to OSVVM and Vunit - with = some minor overlaps. The coverage and advanced random gen. of OSVVM and the= unit test support of Vunit are great in combination with Bitvis Utility Li= brary's checking/await and log/alert features. The main advantage with our = library is that it provides the functionality you need for every single VHD= L testbench independent of verification approach, - with a very low user th= reshold. > We will soon make a new release of BVUL, where you can combine the covera= ge and random generation of OSVVM seamlessly with BVUL, resulting in a majo= r improvement for more advanced testbenches. > With respect to Vunit, Lars Asplund of Synective Labs (maintainer of Vuni= t) stated already in February 2014 that he had used BVUL with Vunit and tha= t it works perfectly well. > BVUL has been tested OK with Riviera Pro (Aldec), Modelsim (Mentor) and V= ivado Sim (Xilinx). We can check compatibility with GHDL as well. > (Currently we support a 2008, 2002 and 93 -version of BVUL, but we will s= oon only continue to develop the 2008 version.) >=20 > Any feedback on BVUL is appreciated. > -Espen Hi Brian and Espen, The logging, the checking, and the unit test running functionality of VUnit= are layers building on top of each other (in that order) and they have a l= oose coupling. This means that it is easy to use the unit test running func= tionality on top of other assertion solutions as well, e.g. plain VHDL asse= rts or BVUL or OVL or OSVVM which also added similar functionality earlier = this year. Integration with the OSVVM functionality is described in https:/= /github.com/LarsAsplund/vunit/blob/master/examples/osvvm_integration/osvvm_= integration.md and the same principle applies to BVUL as well. The layered approach also means that the VUnit logging and checking functio= nality can be used standalone for other verification approaches without the= layer for running unit tests. When used standalone you can choose between = the VHDL-93 or VHDL-200x versions depending on the simulator you have. VUni= t's official support is currently limited to supporting ModelSim and GHDL b= ut that limitation is driven by making the unit test running layer to work = since that layer involves scripting of the simulator. The other layers are = not limited in this way. /Lars From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 15 Jun 2015 20:19:33 GMT Lines: 51 Message-ID: References: X-Trace: individual.net CNaDJgAkSzo/EnapeBJZMQ2tjnGlrcFSro16/c17OLWOue8G2i X-Orig-Path: not-for-mail Cancel-Lock: sha1:QfshSkk+7G93ogkohwGP8EWsijg= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8310 Hi Brian, Brian Drummond wrote: >> I'm cross-posting here from the SystemC Accellera Forum and >> comp.arch.fpga since I *hope* I'm going to receive more feedback here >> than there. > > Since you cross-posted to comp.lang.vhdl, the feedback you might expect > is that AnythingC is likely to be too firmly based on a foundation of > sand, and therefore an unnecessarily difficult road to hardware. Uhm, I'm not sure I've fully grasped what you wanted to say here. Just to clarify my intentions, I'm not looking for synthesizable SystemC, I know enough of VHDL for not needing another language to synthesize what I want to synthesize. My aim here is to leverage more the possibility to perform Architecture exploration. While deciding where to cut the system in pieces you dramatically impose constraints that might be turning into bottlenecks and get your project doomed. [] > Where VHDL gives up I use a very similar language, but in which I can for > example create arbitrary fixed point types (natively, not via extensions) > write generic algorithms, and instantiate them with both float and these > fixed types to evaluate accuracy, determine the word lengths required, > and so on. What kind of language are you referring to? > That gives me a sound basis for a trivial port to VHDL. > > It also gives me full object orientation where I need it, and access via > import mechanisms to anything written in C or C++. Design-by-contract via > pre/postconditions is also available though I haven't used that yet, nor > have I used the formal proof extensions, but these are much more > attractive options to me than anything I've seen offered by System-C. Designing by contract is a paradigm, you can build it in assembler or in any other language. Some of them support it natively, some others through a set of libraries, but the bottom line is still the same. Even if a bit OT, here a nice link (http://dbc.rubyforge.org/) about a ruby utility to parse contracts written in C comments and generate the necessary code compliant to the Design by Contract paradigm. > Unfortunately this doesn't help you with System-C. Discussing always helps, in one way or another! Al From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.141.23.133 with SMTP id z127mr1415023qhd.5.1434473306780; Tue, 16 Jun 2015 09:48:26 -0700 (PDT) X-Received: by 10.140.88.80 with SMTP id s74mr32569qgd.16.1434473306754; Tue, 16 Jun 2015 09:48:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no1555825qgd.1!news-out.google.com!k20ni2053qgd.0!nntp.google.com!q107no1557319qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 09:48:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Tue, 16 Jun 2015 16:48:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8311 Hi Al, If the lack of TLM in VHDL is your only reason for looking at other languag= es I recommend that you have a look at the open source com mechanism that w= as added to VUnit a month ago. It implements high-level message passing for= VHDL which you need to do TLM. I should probably describe com in a post of= its own but here are some pointers The user guide for com can be found at https://github.com/LarsAsplund/vunit= /blob/master/vhdl/com/user_guide.md and a testbench example is found at https://github.com/LarsAsplund/vunit/tr= ee/master/examples/com. Com was developed by a number of VUnit community me= mbers. We took our private code and ideas, improved on that, and came up wi= th the solution that you can download. Everything was done in the open so i= f you want to follow the discussion you can have a look at this thread http= s://github.com/LarsAsplund/vunit/issues/23. Com is a separate module in the= VUnit project so it can be used standalone (but we recommend you to use VU= nit anyway :-))=20 From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 16 Jun 2015 21:30:34 GMT Lines: 41 Message-ID: References: X-Trace: individual.net N9f0PfvKx/IlrDM/NXbqrQxyrxle5O+Nitp3xFq49j3zp5hgZJ X-Orig-Path: not-for-mail Cancel-Lock: sha1:F9EmQzQclYNLUFI0CG8icpQ0aiQ= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8312 Hi Lars, Lars Asplund wrote: > If the lack of TLM in VHDL is your only reason for looking at other > languages I recommend that you have a look at the open source com > mechanism that was added to VUnit a month ago. It implements > high-level message passing for VHDL which you need to do TLM. I should > probably describe com in a post of its own but here are some pointers. Thanks for the pointers! While some level of modeling can be done in VHDL, and maybe should be done at that level, you certainly do not want to venture with it when you're facing multiple cores/interfaces interacting with each other. SystemC has been conceived for modeling and especially for providing a simulation platform to run a real algorithm on top, while still permitting performance analysis and architectural exploration. Sure, I can change the size of the bus in my VHDL model and get to the same results, but I suppose it's more efficient to use SystemC rather than VHDL (and believe me, I'm a big fan of VHDL!). On top of it, why using the same language when you can learn a new one? There are potentially new paradigms at your disposal and enriching your vocabulary would only help your reasoning ;-). > > The user guide for com can be found at > https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_guide.md > and a testbench example is found at > https://github.com/LarsAsplund/vunit/tree/master/examples/com. Com was > developed by a number of VUnit community members. We took our private > code and ideas, improved on that, and came up with the solution that > you can download. Everything was done in the open so if you want to > follow the discussion you can have a look at this thread > https://github.com/LarsAsplund/vunit/issues/23. Com is a separate > module in the VUnit project so it can be used standalone (but we > recommend you to use VUnit anyway :-)) Thanks again for the pointer! Al From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 16 Jun 2015 21:50:35 GMT Lines: 68 Message-ID: References: X-Trace: individual.net Bktt/WRpY9jKGQxTnb0ltAUKlGPmZe0un/l929lF5c6+bYAH2J X-Orig-Path: not-for-mail Cancel-Lock: sha1:aEMgEymKs87vaxbI37PuAVgOH28= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8313 Hi Michael, I was about to post a reply yesterday when my computer crashed and I lost everything, that's why it took me more than foreseen to shape a followup to your post. Please follow inline. michael6866 wrote: > My two cents embedded below with "MK>": I suggest for the next time you follow some simple quoting rules. Please see here for a nice guideline: http://linux.sgms-centre.com/misc/netiquette.php#quoting [] > MK> High level synthesis is a trend. Though there is still a long way > to go, I believe eventually the design methodology will evolve to HLS > just as how GL evolved to RTL. Some major EDA vendors are spending > more and more effort on developing HLS tools and some already get > proven in real projects (see CtoS / Stratus for example). I'm not > saying how good HLS is today, but learning SystemC can definitely give > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > all about HLS. For examples: I'm not interested at the moment to HLS and even less to the synthesizable subsets of SystemC. I'm more into system architecture and performance analysis. > (2) It has faster simulation speed. [] Beaware of simulation speed comparisons. If you minimize the amount of signals and maximize the number of variables, you should be getting a very nice improve (both in maintainability and interoperability with other models). > (3) It's much easier coding virtual platform with SystemC / TLM. [] I agree, the main reason is to still learn a new language, so that I can 'talk' more clearly! A model is also a type of executable specification, which in my type of environment is rarely implemented, but huge benefits would arise whenever is done. > MK> Today it's really a trade-off between accuracy and speed when > considering SystemC vs VHDL/Verilog. There are a lot of places where > SystemC can help you the most. Also, there is nothing to prevent you > from doing mixed simulation. Actually TLM + RTL (some companies call > it "soft hybrid") gets pretty popular these days. You also need to take into account another factor: model availability. The amount of effort to write a simple model in VHDL vs SystemC is certainly not measureable though, therefore often forgotten. [] >> It also gives me full object orientation where I need it, and access via >> import mechanisms to anything written in C or C++. Design-by-contract via >> pre/postconditions is also available though I haven't used that yet, nor >> have I used the formal proof extensions, but these are much more >> attractive options to me than anything I've seen offered by System-C. > MK> Design-by-contract is also achievable in C++ (although may not be > that attractive). For example, the Contract++ is already adopted by > Boost. Again SystemC itself is just a C++ library and there is nothing > to prevent you from using other C++ libraries. There exist a ruby utility since more than 10 years (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), which inserts C code starting from some markup in the comments. I've never used it but seems to me pretty well done. Al From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.66.101.40 with SMTP id fd8mr3980507pab.14.1434502299086; Tue, 16 Jun 2015 17:51:39 -0700 (PDT) X-Received: by 10.182.68.51 with SMTP id s19mr33925obt.6.1434502299006; Tue, 16 Jun 2015 17:51:39 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!h15no4255683igd.0!news-out.google.com!kd3ni8596igb.0!nntp.google.com!h15no4255682igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 17:51:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Wed, 17 Jun 2015 00:51:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 76 Xref: mx02.eternal-september.org comp.lang.vhdl:8314 On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: > I suggest for the next time you follow some simple quoting rules. Please > see here for a nice guideline: > http://linux.sgms-centre.com/misc/netiquette.php#quoting Sorry I'm used to the embedded style as that's the one I used at work. Hopefully I'll get it right this time :) > > [] > > MK> High level synthesis is a trend. Though there is still a long way > > to go, I believe eventually the design methodology will evolve to HLS > > just as how GL evolved to RTL. Some major EDA vendors are spending > > more and more effort on developing HLS tools and some already get > > proven in real projects (see CtoS / Stratus for example). I'm not > > saying how good HLS is today, but learning SystemC can definitely give > > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > > all about HLS. For examples: > > I'm not interested at the moment to HLS and even less to the > synthesizable subsets of SystemC. I'm more into system architecture and > performance analysis. Understood. I was replying to Brian. The point is HLS is a powerful technology and it will thrive soon. > > > (2) It has faster simulation speed. [] > > Beaware of simulation speed comparisons. If you minimize the amount of > signals and maximize the number of variables, you should be getting a > very nice improve (both in maintainability and interoperability with > other models). Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. > > > (3) It's much easier coding virtual platform with SystemC / TLM. > [] > > I agree, the main reason is to still learn a new language, so that I can > 'talk' more clearly! A model is also a type of executable specification, > which in my type of environment is rarely implemented, but huge benefits > would arise whenever is done. You're talking about golden reference. In that case there are many choices besides SystemC. Of course SystemC is among the best so it's well worth learning. > > > MK> Today it's really a trade-off between accuracy and speed when > > considering SystemC vs VHDL/Verilog. There are a lot of places where > > SystemC can help you the most. Also, there is nothing to prevent you > > from doing mixed simulation. Actually TLM + RTL (some companies call > > it "soft hybrid") gets pretty popular these days. > > You also need to take into account another factor: model availability. > The amount of effort to write a simple model in VHDL vs SystemC is > certainly not measureable though, therefore often forgotten. Agree. However number of SystemC IP is much less than the RTL one today. The good thing is many companies are starting on the former. > > [] > >> It also gives me full object orientation where I need it, and access via > >> import mechanisms to anything written in C or C++. Design-by-contract via > >> pre/postconditions is also available though I haven't used that yet, nor > >> have I used the formal proof extensions, but these are much more > >> attractive options to me than anything I've seen offered by System-C. > > > MK> Design-by-contract is also achievable in C++ (although may not be > > that attractive). For example, the Contract++ is already adopted by > > Boost. Again SystemC itself is just a C++ library and there is nothing > > to prevent you from using other C++ libraries. > > There exist a ruby utility since more than 10 years > (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), > which inserts C code starting from some markup in the comments. I've > never used it but seems to me pretty well done. Thanks for the Info. However I don't use design by contract. My reply was merely to point out it's achievable in C++ world. > > Al Regards, Michael From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.68.143.229 with SMTP id sh5mr3815566pbb.11.1434502500899; Tue, 16 Jun 2015 17:55:00 -0700 (PDT) X-Received: by 10.182.19.194 with SMTP id h2mr32711obe.41.1434502500769; Tue, 16 Jun 2015 17:55:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4256581igd.0!news-out.google.com!7ni495igs.0!nntp.google.com!h15no3330129igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 16 Jun 2015 17:55:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> Subject: Re: hands on experience on SystemC From: michael6866 Injection-Date: Wed, 17 Jun 2015 00:55:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8315 On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: > I suggest for the next time you follow some simple quoting rules. Please > see here for a nice guideline: > http://linux.sgms-centre.com/misc/netiquette.php#quoting Sorry I'm used to the embedded style as that's the one I used at work. Hopefully I'll get it right this time :) > > [] > > MK> High level synthesis is a trend. Though there is still a long way > > to go, I believe eventually the design methodology will evolve to HLS > > just as how GL evolved to RTL. Some major EDA vendors are spending > > more and more effort on developing HLS tools and some already get > > proven in real projects (see CtoS / Stratus for example). I'm not > > saying how good HLS is today, but learning SystemC can definitely give > > you some fresh ideas on those fancy stuff. Moreover, SystemC is not > > all about HLS. For examples: > > I'm not interested at the moment to HLS and even less to the > synthesizable subsets of SystemC. I'm more into system architecture and > performance analysis. Understood. I was replying to Brian. The point is HLS is a powerful technology and it will thrive soon. > > > (2) It has faster simulation speed. [] > > Beaware of simulation speed comparisons. If you minimize the amount of > signals and maximize the number of variables, you should be getting a > very nice improve (both in maintainability and interoperability with > other models). Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. > > > (3) It's much easier coding virtual platform with SystemC / TLM. > [] > > I agree, the main reason is to still learn a new language, so that I can > 'talk' more clearly! A model is also a type of executable specification, > which in my type of environment is rarely implemented, but huge benefits > would arise whenever is done. You're talking about golden reference. In that case there are many choices besides SystemC. Of course SystemC is among the best so it's well worth learning. > > > MK> Today it's really a trade-off between accuracy and speed when > > considering SystemC vs VHDL/Verilog. There are a lot of places where > > SystemC can help you the most. Also, there is nothing to prevent you > > from doing mixed simulation. Actually TLM + RTL (some companies call > > it "soft hybrid") gets pretty popular these days. > > You also need to take into account another factor: model availability. > The amount of effort to write a simple model in VHDL vs SystemC is > certainly not measureable though, therefore often forgotten. Agree. However number of SystemC IP is much less than the RTL one today. The good thing is many companies are starting on the former. > > [] > >> It also gives me full object orientation where I need it, and access via > >> import mechanisms to anything written in C or C++. Design-by-contract via > >> pre/postconditions is also available though I haven't used that yet, nor > >> have I used the formal proof extensions, but these are much more > >> attractive options to me than anything I've seen offered by System-C. > > > MK> Design-by-contract is also achievable in C++ (although may not be > > that attractive). For example, the Contract++ is already adopted by > > Boost. Again SystemC itself is just a C++ library and there is nothing > > to prevent you from using other C++ libraries. > > There exist a ruby utility since more than 10 years > (http://www.onlamp.com/pub/a/onlamp/2004/10/28/design_by_contract_in_c.html), > which inserts C code starting from some markup in the comments. I've > never used it but seems to me pretty well done. Thanks for the Info. However I don't use design by contract. My reply was merely to point out it's achievable in C++ world. > > Al Regards, Michael From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.140.235.204 with SMTP id g195mr5468946qhc.3.1434525398793; Wed, 17 Jun 2015 00:16:38 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr77300qge.10.1434525398778; Wed, 17 Jun 2015 00:16:38 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!q107no1660124qgd.0!news-out.google.com!4ni1982qgh.1!nntp.google.com!z60no1658626qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jun 2015 00:16:38 -0700 (PDT) In-Reply-To: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Wed, 17 Jun 2015 07:16:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2260 X-Received-Body-CRC: 1723880145 Xref: mx02.eternal-september.org comp.lang.vhdl:8316 Hi Al, Thanks for sharing. The reason for me asking is that the message passing in= VUnit wasn't developed to support TLM for hardware out of the box. It was = developed to enable high-level communication within testbenches, not within= the DUT. In that context we want to be focused on the information to excha= nge and with whom. We don't want to know where our counterparts are located= , we don't want communication to take time, we don't want to be exposed to = FIFOs limiting the communication capacity and so on. These are things that = becomes more interesting when you want to model hardware and it can be adde= d as an extra layer of functionality on top of the "pure" message passing. = Since you're working across the range of abstraction levels I'm interested = to see under what circumstances, if any, you see use cases for TLM in VHDL. A bit off topic... /Lars From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.70.127.174 with SMTP id nh14mr11444413pdb.8.1434610343205; Wed, 17 Jun 2015 23:52:23 -0700 (PDT) X-Received: by 10.140.20.148 with SMTP id 20mr65754qgj.20.1434610342949; Wed, 17 Jun 2015 23:52:22 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no4857739igd.0!news-out.google.com!k20ni2479qgd.0!nntp.google.com!z60no1863310qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 17 Jun 2015 23:52:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Thu, 18 Jun 2015 06:52:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8317 Just to clarify; VUnit is also independent of the verification approach of = the user. I have personally used to run constrained random verification usi= ng OSVVM, multi hour long end-to-end tests against golden reference data as= well as small directed unit tests. Typically a project would have a bit of= each. In projects I have been involved in where there were 200+ tests my e= stimate was that 60% were constrained random, 30% directed and 10% big end = to end. What makes VUnit different is that it is not just a VHDL library. It tries = to be a complete testing tool for VHDL in which the library features you de= scribe are one important piece of the puzzle. The cornerstones of VUnit are= : 1) Support for dependency scanning and incremental compilation. So that the edit/compile/run cycle is a fast as possible. 2) A VHDL library for checks/asserts/logging that are needed for writing the a= ctual test bench. Procedures for saving/loading test data to/from .csv and = .raw files etc. We also re-distribute OSVVM since it provides additional li= brary capabilities for random number generation, and coverage. 3) A Python command line interface such that tests can be automatically run ei= ther in batch or in GUI with minimal user effort. Such that test can be con= figured to run for all combinations of generic values. Such that tests can = be run in parallel. Such that VHDL testing can be integrated with Continous= Integration environments such as Jenkins.=20 The BVUL fills the role of 2) and could probably replace the corresponding = libraries that were created specifically for VUnit. As Lars Asplund mention= s the checking and logging libraries are orthogonal to other parts of VUnit= making it possible to use BVUL instead of the VUnit builtin checks. Replac= ing the built in parts of VUnit with BVUL has not been something I have inv= estigated that much since I would rather focus on adding missing functional= ity to VUnit rather than replacing existing functionality with something of= another flavor. Although 2) is an important part of the puzzle without 1) and 3) it is just= not as productive since the user has to perform a lot of manual work to ru= n, compile and administer their tests. Many companies have some home-brew v= ariant of 3) of varying quality though. The goal of VUnit was to make peopl= e stop re-inventing the wheel making their proprietary in-house solutions a= nd instead use the man hours to improve something that everyone can use. = =20 // The second main author of VUnit From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.68.94.35 with SMTP id cz3mr19127155pbb.5.1434707551383; Fri, 19 Jun 2015 02:52:31 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr91893qge.33.1434707551119; Fri, 19 Jun 2015 02:52:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5413284igd.0!news-out.google.com!4ni2206qgh.1!nntp.google.com!z60no2075346qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 02:52:30 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=89.221.115.64; posting-account=pPdiQAoAAABXyXlRIf4K6f14FyZc1g3D NNTP-Posting-Host: 89.221.115.64 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> Subject: Qucs stops working when I try to simulate scheme . From: edgars.visockis@gmail.com Injection-Date: Fri, 19 Jun 2015 09:52:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8318 Hi, I have test next week and I've been playing with VHDL language recently= and run into this error which I cant understand, maybe someone can help me= .=20 I'm testing simple generator who generates numbers from 0 to 7. Here is the= code : ----------------------------------------------- package mxx is subtype mytype is integer range 0 to 7; end package; library IEEE; use WORK.mxx.ALL; use IEEE.std_logic_1164.ALL; entity eightval_generators is generic (ti : time :=3D10 ns); port (sk : out mytype); end entity; architecture normala of eightval_generators is begin process begin for i in 0 to 7 loop sk <=3D i; wait for ti;=09 end loop; end process; end architecture; ----------------------------------------------- I have created schematic for code with appropriate output port and my simul= ation type is TimeList Digital simulation. If I change mytype to integer I = don't get error and all works. But for practice I wanted to use subtype and= limit it to my needs and add all of this as package to my project. But thi= s results in error which I would like to clear out . From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: al.basili@gmail.com (alb) Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC Date: 19 Jun 2015 10:11:53 GMT Lines: 77 Message-ID: References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> X-Trace: individual.net 8/Q324Clue0dumMC0l01sgzkBNeb+1P7xcpFyIZzdfFF6b8xq+ X-Orig-Path: not-for-mail Cancel-Lock: sha1:Tv/LQT/Z4UKvhQQ0TXYVnjELo6o= User-Agent: tin/2.2.1-20140504 ("Tober an Righ") (UNIX) (Linux/3.16.0-4-686-pae (i686)) Xref: mx02.eternal-september.org comp.lang.vhdl:8319 Hi Lars, Lars Asplund wrote: [] > Thanks for sharing. The reason for me asking is that the message > passing in VUnit wasn't developed to support TLM for hardware out of > the box. It was developed to enable high-level communication within > testbenches, not within the DUT. I'm not sure to which question or statement you're referring to. I think DUT need to be described with purely non-synthesizable construct that focus on the architecture rather than the details. This model can leverage the TLM message passing mechanism in order to do architecture exploration and allow to build a verification environment. Unfortunately this step is too often tossed away of the development plan to only find ourselves in the weeds too many weeks/months later. Non-synthesizable VHDL is also poorly taught and valued in undergraduate courses, the focus on the synthesizable subset of the language casts some habits into designers that are hard to break and lead eventually to poor perfomance. I've seen professionals writing testbenches as if they were to be synthesized! That's not what the language allows us to do. Likely some libraries and utilities are popping out and maybe help designers to write better simulation environments. > In that context we want to be focused > on the information to exchange and with whom. We don't want to know > where our counterparts are located, we don't want communication to > take time, we don't want to be exposed to FIFOs limiting the > communication capacity and so on. These are things that becomes more > interesting when you want to model hardware and it can be added as an > extra layer of functionality on top of the "pure" message passing. Message passing is an extremely important concept that is often forgotten when you are head down hitting your keyboard to write RTL. Building a function thinking in terms of messages passed from one point to another is a powerful tool that allows to see where these messages interact in the datapath and may help find a better way to avoid bottlenecks. I want/need to focus on the 'what's going on' part of the game, rather than on 'how is going on' and FWIK this is what a 'tool' like SystemC/TLM has been thought for. I believe I can do the same in non-synthesizable VHDL but I'd like to explore new constructs and see what suits the best for what. > Since you're working across the range of abstraction levels I'm > interested to see under what circumstances, if any, you see use cases > for TLM in VHDL. I think about TLM as a methodology rather than a library and what is important here is shifting approach according to the need. I know of a tool (TauhopHLS) which converts vhdl-2008 syntax into synthesizable vhdl-93, with the promise to bridge the gap between an high level modeling and the registers ticking. I haven't used the tool (yet), but 'standardizing' designs through a set of high level constructs is not less than building a libc for hardware! Why would you want to take care about the bits and pieces that happen behind the scenes? Let someone else optimize it for you, someone who knows the target technology better than you can possibly know and focus on the application *you* need to design. Resources in the FPGAs are increasing at an incredible pace and yet there are tons of designers that meticoulously care about the registers and the gates...on a million gates device? Good luck! Anyway, we definitely drifted OT here, but I'll venture in learning SystemC/TLM and see where this path will lead me to ;-). Alan Fitch, who maybe listening here, have pointed me to an incredibly well done tutorial by embecosm: http://www.embecosm.com/resources/appnotes/#EAN1. I'll see where I'll find myself in the end. Al From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.13.219.75 with SMTP id d72mr174664ywe.4.1434723640012; Fri, 19 Jun 2015 07:20:40 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr298511qgd.29.1434723639951; Fri, 19 Jun 2015 07:20:39 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no2121401qgd.1!news-out.google.com!k20ni2707qgd.0!nntp.google.com!q107no2123054qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 07:20:39 -0700 (PDT) In-Reply-To: <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Fri, 19 Jun 2015 14:20:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8320 Hi Olof, I agree that BVUL only covers your item 2 above, but then again item 2 is where you can actually save by far the most hours in a complex FPGA project. Items 1 and 3 are also important, and will save quite a few hours. BVUL is however not just another flavour. BVUL has verbosity control, optional positive acknowledge on checks and some very important additional checks resulting in faster testbench development and faster debugging. We will also very soon integrate BVUL tighter with OSVVM and add even more advanced verification capabilities through UVVM (to be released soon). I think perhaps it could be great if we could cooperate on the combination Vunit and BVUL, so that we could get the best out of two worlds, but we could take that discussion off line ;-) -Espen From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.50.44.13 with SMTP id a13mr5662594igm.3.1434736970647; Fri, 19 Jun 2015 11:02:50 -0700 (PDT) X-Received: by 10.140.97.33 with SMTP id l30mr259202qge.23.1434736969470; Fri, 19 Jun 2015 11:02:49 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!h15no4125579igd.0!news-out.google.com!k20ni2729qgd.0!nntp.google.com!q107no2162690qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 11:02:49 -0700 (PDT) In-Reply-To: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=64.125.175.43; posting-account=K8s34AgAAAC82s807L1UbC9jiRrCGO8U NNTP-Posting-Host: 64.125.175.43 References: <55275971-1f7c-4322-8e23-266c09863f1a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Qucs stops working when I try to simulate scheme . From: Jackie Christman Injection-Date: Fri, 19 Jun 2015 18:02:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8321 Hey check out my course for only $5 - this will help you with VHDL! https://www.udemy.com/vhdl-and-fpga-development-for-beginners-and-intermediates/?couponCode=5guys From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.182.241.105 with SMTP id wh9mr25308516obc.47.1434779902346; Fri, 19 Jun 2015 22:58:22 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr343235qge.40.1434779902226; Fri, 19 Jun 2015 22:58:22 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no5832274igd.0!news-out.google.com!k20ni2788qgd.0!nntp.google.com!z60no2237349qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 19 Jun 2015 22:58:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 05:58:22 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8322 Espen, first I want to just note that the corresponding libraries in VUnit = also have the features you describe. Secondly, maybe this is down to personal preference but I would not value 1= ) and 3) less than 2). For most projects the majority of test benches do no= t need to be that advanced; check_equal with automatic report of "got vs ex= pected", random number generation, and some simple watchdog or timeout cove= rs 90% of the need.=20 My personal testing preference is that each VHDL entity should have a test = bench achieving full functional coverage. It is important to do this to dri= ve the design into a good partition of loosely coupled and testable entitie= s. Most entities will be small and their corresponding test benches run fas= t and then there is not much need for advanced logging or delayed failure. = In such a situation I have a strong preference for immediate failure on a f= ailing alert/check since when stopping immediately the VHDL call stack can = be emitted at the point of failure. I would rather open the simulator GUI a= nd look at the waveform or single step through the code past the failure, w= hich can be done by just running VUnit command line with the --gui flag. Th= e larger end-to-end tests are also required even using the above philosophy= and in such a situation more advanced logging and delayed alert/check fail= ure can be more useful but still check_equal takes you very far.=20 My experience is that without 1) and 3) many people tend to fall back into = just having the large end-to-end tests since it is such a burden to maintai= n the scripts to handle the small 200+ test cases which would have made the= code base a lot easier to maintain, with fever bugs and more modularity. V= Unit lets you just add a test to your testbench or add a new testbench and = it is automatically part of the test suite due to the test scanner feature.= When writing the test it also lets the user focus completely on their task= allowing them to effortlessly edit/compile/re-run with the just a single c= ommand. With all that said I would be interested in trying to collaborate in some w= ay and I have sent you a personal email. I can just note that we are doing = similar things and to me it seems a shame to fragment a small community by = having multiple competing/exclusive implementations of the same puzzle piec= e. On Friday, June 19, 2015 at 4:20:42 PM UTC+2, espen.t...@bitvis.no wrote: > Hi Olof, >=20 > I agree that BVUL only covers your item 2 above, but then again item 2 is= where you can actually save by far the most hours in a complex FPGA projec= t. Items 1 and 3 are also important, and will save quite a few hours. >=20 > BVUL is however not just another flavour. BVUL has verbosity control, opt= ional positive acknowledge on checks and some very important additional che= cks resulting in faster testbench development and faster debugging. > We will also very soon integrate BVUL tighter with OSVVM and add even mor= e advanced verification capabilities through UVVM (to be released soon). >=20 > I think perhaps it could be great if we could cooperate on the combinatio= n Vunit and BVUL, so that we could get the best out of two worlds, but we c= ould take that discussion off line ;-) >=20 > -Espen From newsfish@newsfish Tue Dec 29 16:43:51 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source Date: Sat, 20 Jun 2015 10:20:37 +0000 (UTC) Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 20 Jun 2015 10:20:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="9537"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18YQgCPTHkvjy2enU6KI+MPg2w3ZQT74ic=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:8z9QYH4+JxYpOREoOvl0CLFpx1M= Xref: mx02.eternal-september.org comp.lang.vhdl:8323 On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: > Hi Olof, > > I agree that BVUL only covers your item 2 above, but then again item 2 > is where you can actually save by far the most hours in a complex FPGA > project. Items 1 and 3 are also important, and will save quite a few > hours. > > I think perhaps it could be great if we could cooperate on the > combination Vunit and BVUL, so that we could get the best out of two > worlds, but we could take that discussion off line ;-) By all means take the details off-line but please summarize the outcome here! Thanks to yourself, Olof and Lars for discussing - and indeed, creating - these useful tools! -- Brian From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.13.207.1 with SMTP id r1mr26642799ywd.46.1434801044279; Sat, 20 Jun 2015 04:50:44 -0700 (PDT) X-Received: by 10.140.42.161 with SMTP id c30mr90868qga.30.1434801044262; Sat, 20 Jun 2015 04:50:44 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z60no2279880qgd.1!news-out.google.com!k20ni2820qgd.0!nntp.google.com!z60no2279879qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 04:50:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 11:50:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8324 I downloaded the BVUL to have a look. It looks very similar to what we have= in VUnit. I noticed the example test bench bitvis_irqc/tb/irqc_tb.vhd coul= d benefit from the VUnit Python/VHDL automation. My interpretation is that = you use log messages with ID_LOG_HDR to visually/textually separate differe= nt independent test cases. I count 8 of those. With VUnit you could have th= ose 8 as actual independent test cases run in different simulations (or opt= ionally all in the same simulation) with individual pass/fail in the test r= eport. An individual specific test can be easily run from command line usin= g wildcard (*) pattern. VUnit would also ensure that each test case got its= own dedicated output folder to gather all simulation artifacts such as the= complete stderr/stdout, wlf and transcript as well as any other user defin= ed outputs such as images other binary data files. =20 On Saturday, June 20, 2015 at 12:21:59 PM UTC+2, Brian Drummond wrote: > On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: >=20 > > Hi Olof, > >=20 > > I agree that BVUL only covers your item 2 above, but then again item 2 > > is where you can actually save by far the most hours in a complex FPGA > > project. Items 1 and 3 are also important, and will save quite a few > > hours. > >=20 > > I think perhaps it could be great if we could cooperate on the > > combination Vunit and BVUL, so that we could get the best out of two > > worlds, but we could take that discussion off line ;-) >=20 > By all means take the details off-line but please summarize the outcome= =20 > here! >=20 > Thanks to yourself, Olof and Lars for discussing - and indeed, creating -= =20 > these useful tools! >=20 > -- Brian From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.50.4.34 with SMTP id h2mr10579021igh.8.1434803236450; Sat, 20 Jun 2015 05:27:16 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr38034qgg.21.1434803236322; Sat, 20 Jun 2015 05:27:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no138590igd.0!news-out.google.com!k20ni2820qgd.0!nntp.google.com!z60no2284026qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 05:27:16 -0700 (PDT) In-Reply-To: <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <4e76b32f-723c-4e70-a5be-38e6053f68e1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 12:27:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8325 I made a small effort to split the irqc_tb.vhd into use separate test using= VUnit. I had some problem with test independence of the "Check irq acknowl= edge and re-enable test" depending on a variable value from the previous "C= heck autonomy for all interrupts" test case but I soon found and fixed it. = I also ensured your _Alert.txt and _Log.txt files ended up in the test spec= ific output folders. I did not need to use any of your hardcoded compile sc= ripts since VUnit figured out the dependencies automatically. The non-verbo= se textual output when running looked like this. (The pass being in green c= olor in a real terminal): Starting irqc_lib.irqc_tb.Check defaults on output ports pass (P=3D1 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check defaults on output po= rts (0.9 seconds) Starting irqc_lib.irqc_tb.Check register defaults and access write read pass (P=3D2 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check register defaults and= access write read (0.3 seconds) Starting irqc_lib.irqc_tb.Check register trigger clear mechanism pass (P=3D3 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check register trigger clea= r mechanism (0.3 seconds) Starting irqc_lib.irqc_tb.Check interrupt sources IER IPR and irq2cpu pass (P=3D4 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check interrupt sources IER= IPR and irq2cpu (0.3 seconds) Starting irqc_lib.irqc_tb.Check autonomy for all interrupts pass (P=3D5 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check autonomy for all inte= rrupts (0.3 seconds) Starting irqc_lib.irqc_tb.Check irq acknowledge and re-enable pass (P=3D6 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check irq acknowledge and r= e-enable (0.3 seconds) Starting irqc_lib.irqc_tb.Check Reset pass (P=3D7 S=3D0 F=3D0 T=3D7) irqc_lib.irqc_tb.Check Reset (0.3 seconds) =3D=3D=3D=3D Summary =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D pass irqc_lib.irqc_tb.Check defaults on output ports (0.9 se= conds) pass irqc_lib.irqc_tb.Check register defaults and access write read (0.3 se= conds) pass irqc_lib.irqc_tb.Check register trigger clear mechanism (0.3 se= conds) pass irqc_lib.irqc_tb.Check interrupt sources IER IPR and irq2cpu (0.3 se= conds) pass irqc_lib.irqc_tb.Check autonomy for all interrupts (0.3 se= conds) pass irqc_lib.irqc_tb.Check irq acknowledge and re-enable (0.3 se= conds) pass irqc_lib.irqc_tb.Check Reset (0.3 se= conds) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D pass 7 of 7 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Total time was 2.6 seconds Elapsed time was 2.6 seconds =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D All passed! The run.py file used to drive everything looked like this: from os.path import dirname, join from vunit import VUnit root =3D dirname(__file__) ui =3D VUnit.from_argv() bvul_lib =3D ui.add_library("bitvis_util") bvul_lib.add_source_files(join(root, "bitvis_util", "src2008", "*.vhd")) bitvis_vip_spi_lib =3D ui.add_library("bitvis_vip_sbi") bitvis_vip_spi_lib.add_source_files(join(root, "bitvis_vip_sbi", "src", "*.= vhd")) irqc_lib =3D ui.add_library("irqc_lib") irqc_lib.add_source_files(join(root, "bitvis_irqc", "src", "*.vhd")) irqc_lib.add_source_files(join(root, "bitvis_irqc", "tb", "*.vhd")) ui.main() The modified irqc_tb.vhd looked like this: (The name collision with your an= d our log method prevented me from using our VHDL-2008 context for the VUni= t packages forcing me to use them individually to avoid exposing our log): --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtainin= g -- a copy of this VHDL code and associated documentation files (for 'Bitvis= Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the = following conditions: -- - This copyright notice shall be included as is in all copies or substa= ntial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a pa= rt of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be= removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOU= T WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS = FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLA= IM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT O= F OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ---------------------------------------------------------------------------= --------------- -- VHDL unit : Bitvis IRQC Library : irqc_tb -- -- Description : See dedicated powerpoint presentation and README-file(s) ---------------------------------------------------------------------------= --------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library STD; use std.textio.all; -- library ieee_proposed; -- use ieee_proposed.standard_additions.all; -- use ieee_proposed.std_logic_1164_additions.all; library vunit_lib; use vunit_lib.run_types_pkg.all; use vunit_lib.run_pkg.all; use vunit_lib.run_base_pkg.all; library bitvis_util; use bitvis_util.types_pkg.all; use bitvis_util.string_methods_pkg.all; use bitvis_util.adaptations_pkg.all; use bitvis_util.methods_pkg.all; library bitvis_vip_sbi; use bitvis_vip_sbi.sbi_bfm_pkg.all; use work.irqc_pif_pkg.all; -- Test case entity entity irqc_tb is generic (runner_cfg : runner_cfg_t); end entity; -- Test case architecture architecture func of irqc_tb is -- DSP interface and general control signals signal clk : std_logic :=3D '0'; signal arst : std_logic :=3D '0'; -- CPU interface signal cs : std_logic :=3D '0'; signal addr : unsigned(2 downto 0) :=3D (others =3D> '0'= ); signal wr : std_logic :=3D '0'; signal rd : std_logic :=3D '0'; signal din : std_logic_vector(7 downto 0) :=3D (others =3D> '0'= ); signal dout : std_logic_vector(7 downto 0) :=3D (others =3D> '0'= ); signal rdy : std_logic :=3D '1'; -- Always ready in the same c= lock cycle -- Interrupt related signals signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) :=3D (o= thers =3D> '0'); signal irq2cpu : std_logic :=3D '0'; signal irq2cpu_ack : std_logic :=3D '0'; signal clock_ena : boolean :=3D false; constant C_CLK_PERIOD : time :=3D 10 ns; procedure clock_gen( signal clock_signal : inout std_logic; signal clock_ena : in boolean; constant clock_period : in time ) is variable v_first_half_clk_period : time :=3D C_CLK_PERIOD / 2; begin loop if not clock_ena then wait until clock_ena; end if; wait for v_first_half_clk_period; clock_signal <=3D not clock_signal; wait for (clock_period - v_first_half_clk_period); clock_signal <=3D not clock_signal; end loop; end; subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0); -- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. = reduce width) function trim( constant source : std_logic_vector; constant num_bits : positive :=3D C_NUM_SOURCES) return t_irq_source is variable v_result : std_logic_vector(source'length-1 downto 0) :=3D sou= rce; begin return v_result(num_bits-1 downto 0); end; -- Fit a given vector to the number of irq sources by masking with zeros = above irq width function fit( constant source : std_logic_vector; constant num_bits : positive :=3D C_NUM_SOURCES) return std_logic_vector is variable v_result : std_logic_vector(source'length-1 downto 0) :=3D (ot= hers =3D> '0'); variable v_source : std_logic_vector(source'length-1 downto 0) :=3D sou= rce; begin v_result(num_bits-1 downto 0) :=3D v_source(num_bits-1 downto 0); return v_result; end; begin -------------------------------------------------------------------------= ---- -- Instantiate DUT -------------------------------------------------------------------------= ---- i_irqc: entity work.irqc port map ( -- DSP interface and general control signals clk =3D> clk, arst =3D> arst, -- CPU interface cs =3D> cs, addr =3D> addr, wr =3D> wr, rd =3D> rd, din =3D> din, dout =3D> dout, -- Interrupt related signals irq_source =3D> irq_source, irq2cpu =3D> irq2cpu, irq2cpu_ack =3D> irq2cpu_ack ); -- Set upt clock generator clock_gen(clk, clock_ena, 10 ns); ------------------------------------------------ -- PROCESS: p_main ------------------------------------------------ p_main: process constant C_SCOPE : string :=3D C_TB_SCOPE_DEFAULT; procedure pulse( signal target : inout std_logic; signal clock_signal : in std_logic; constant num_periods : in natural; constant msg : in string ) is begin if num_periods > 0 then wait until falling_edge(clock_signal); target <=3D '1'; for i in 1 to num_periods loop wait until falling_edge(clock_signal); end loop; else target <=3D '1'; wait for 0 ns; -- Delta cycle only end if; target <=3D '0'; log(ID_SEQUENCER_SUB, msg, C_SCOPE); end; procedure pulse( signal target : inout std_logic_vector; constant pulse_value : in std_logic_vector; signal clock_signal : in std_logic; constant num_periods : in natural; constant msg : in string) is begin if num_periods > 0 then wait until falling_edge(clock_signal); target <=3D pulse_value; for i in 1 to num_periods loop wait until falling_edge(clock_signal); end loop; else target <=3D pulse_value; wait for 0 ns; -- Delta cycle only end if; target(target'range) <=3D (others =3D> '0'); log(ID_SEQUENCER_SUB, "Pulsed to " & to_string(pulse_value, HEX, AS_I= S, INCL_RADIX) & ". " & msg, C_SCOPE); end; -- Log overloads for simplification procedure log( msg : string) is begin log(ID_SEQUENCER, msg, C_SCOPE); end; -- Overloads for PIF BFMs for SBI (Simple Bus Interface) procedure write( constant addr_value : in natural; constant data_value : in std_logic_vector; constant msg : in string) is begin sbi_write(to_unsigned(addr_value, addr'length), data_value, msg, clk, cs, addr, rd, wr, rdy, din, C_CLK_PERIOD, C_SCOPE); end; procedure check( constant addr_value : in natural; constant data_exp : in std_logic_vector; constant alert_level : in t_alert_level; constant msg : in string) is begin sbi_check(to_unsigned(addr_value, addr'length), data_exp, alert_level= , msg, clk, cs, addr, rd, wr, rdy, dout, C_CLK_PERIOD, C_SCOPE); end; procedure set_inputs_passive( dummy : t_void) is begin cs <=3D '0'; addr <=3D (others =3D> '0'); wr <=3D '0'; rd <=3D '0'; din <=3D (others =3D> '0'); irq_source <=3D (others =3D> '0'); irq2cpu_ack <=3D '0'; log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE); end; variable v_time_stamp : time :=3D 0 ns; variable v_irq_mask : std_logic_vector(7 downto 0); variable v_irq_mask_inv : std_logic_vector(7 downto 0); begin test_runner_setup(runner, runner_cfg); -- Use VUnit output path set_log_file_name(output_path(runner_cfg) & "_Log.txt"); set_alert_file_name(output_path(runner_cfg) & "_Alert.txt"); -- Print the configuration to the log report_global_ctrl(VOID); report_msg_id_panel(VOID); enable_log_msg(ALL_MESSAGES); --disable_log_msg(ALL_MESSAGES); --enable_log_msg(ID_LOG_HDR); log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE); ------------------------------------------------------------ set_inputs_passive(VOID); clock_ena <=3D true; -- to start clock generator pulse(arst, clk, 10, "Pulsed reset-signal - active for 10T"); v_time_stamp :=3D now; -- time from which irq2cpu should be stable off= until triggered check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt s= ource", C_SCOPE); check_value(C_NUM_SOURCES <=3D 8, TB_WARNING, "This TB is only checking= IRQC with up to 8 interrupt sources", C_SCOPE); while test_suite loop if run("Check defaults on output ports") then check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default = inactive", C_SCOPE); check_value(dout, x"00", ERROR, "Register data bus output must be d= efault passive"); elsif run("Check register defaults and access write read") then log("\nChecking Register defaults"); check(C_ADDR_IRR, x"00", ERROR, "IRR default"); check(C_ADDR_IER, x"00", ERROR, "IER default"); check(C_ADDR_IPR, x"00", ERROR, "IPR default"); check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED defaul= t"); log("\nChecking Register Write/Read"); write(C_ADDR_IER, fit(x"55"), "IER"); check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback"); write(C_ADDR_IER, fit(x"AA"), "IER"); check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback"); write(C_ADDR_IER, fit(x"00"), "IER"); check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback"); elsif run("Check register trigger clear mechanism") then write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts"); check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR"); write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts"); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR"); write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts"); check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR"); write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts"); check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR"); elsif run("Check interrupt sources IER IPR and irq2cpu") then log("\nChecking interrupts and IRR"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T"); check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts"); check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts"); check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses"); pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts"); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses"); write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts"); pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts"); check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all"); log("Checking IER IPR and irq2cpu"); write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts"); write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts"= ); check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active"); check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should= not be active"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interru= pt to CPU"); check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should= now be active"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be in= active", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu", C_SCOPE); pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interr= upt"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt exp= ected immediately", C_SCOPE); v_time_stamp :=3D now; -- from time of stable active irq2cpu check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active"); check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active"); log("\nMore details checked in the autonomy section below"); check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be ac= tive", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu", C_SCOPE); elsif run("Check autonomy for all interrupts") then write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts"); write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); for i in 0 to C_NUM_SOURCES-1 loop log(" "); log("- Checking irq_source(" & to_string(i) & ") and all correspo= nding functionality"); log("- - Check interrupt activation not affected by non related i= nterrupts or registers"); v_time_stamp :=3D now; -- from time of stable inactive irq2cpu v_irq_mask :=3D (i =3D> '1', others =3D> '0'); v_irq_mask_inv :=3D (i =3D> '0', others =3D> '1'); write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt"); pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-en= abled interrupts"); write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled = interrupts"); check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet trigge= red"); check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be = inactive", C_SCOPE); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes all= owed on irq2cpu", C_SCOPE); pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled in= terrupt"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt e= xpected immediately", C_SCOPE); check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered"); check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected"= ); log("\n- - Check interrupt deactivation not affected by non relat= ed interrupts or registers"); v_time_stamp :=3D now; -- from time of stable active irq2cpu write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled in= terrupts"); write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts"); write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interru= pts"); pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts"); write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes all= owed on irq2cpu (=3D'1')", C_SCOPE); write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts bu= t disable selected"); check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active",= C_SCOPE); check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all"); write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled in= terrupts"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt d= eactivation expected immediately", C_SCOPE); write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt= "); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt r= eactivation expected immediately", C_SCOPE); check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for select= ed"); write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt"); check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inacti= ve", C_SCOPE); check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive"); check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive"); write(C_ADDR_IER, x"00", "IER : Disable all interrupts"); end loop; report_alert_counters(INTERMEDIATE); -- Report intermediate counter= s elsif run("Check irq acknowledge and re-enable") then log("- Activate interrupt"); write(C_ADDR_ITR, x"01", "ICR : Set single upper interrupt"); write(C_ADDR_IER, x"01", "IER : Enable single upper interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt act= ivation expected", C_SCOPE); v_time_stamp :=3D now; -- from time of stable active irq2cpu log("\n- Try potential malfunction"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU again - should not affect anything"); write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should n= ot affect anything"); write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - = should not affect anything"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu (=3D'1')", C_SCOPE); log("\n- Acknowledge and deactivate interrupt"); pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation expected", C_SCOPE); v_time_stamp :=3D now; -- from time of stable inactive irq2cpu log("\n- Test for potential malfunction"); write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable int= errupt to CPU again - should not affect anything"); write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - = should not affect anything"); write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should n= ot affect anything"); write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts"); write(C_ADDR_IER, x"FF", "IER : Enable all interrupts"); pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts"); pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack"); check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allow= ed on irq2cpu (=3D'0')", C_SCOPE); log("\n- Re-/de-activation"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrup= t to CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt rea= ctivation expected", C_SCOPE); write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate = interrupt to CPU"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation expected", C_SCOPE); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrup= t to CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt rea= ctivation expected", C_SCOPE); elsif run("Check Reset") then log("- Activate all interrupts"); write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts"); write(C_ADDR_IER, x"FF", "IER : Enable all interrupts"); write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to = CPU"); await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt act= ivation expected", C_SCOPE); pulse(arst, clk, 1, "Pulse reset"); await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt dea= ctivation", C_SCOPE); check(C_ADDR_IER, x"00", ERROR, "IER all inactive"); check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive"); check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive"); end if; end loop; --=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -- Ending the simulation -----------------------------------------------------------------------= --------------- wait for 1000 ns; -- to allow some time for completion report_alert_counters(FINAL); -- Report final counters and print conclu= sion for simulation (Success/Fail) test_runner_cleanup(runner); wait; -- to stop completely end process p_main; end func; On Saturday, June 20, 2015 at 1:50:45 PM UTC+2, olof.k...@gmail.com wrote: > I downloaded the BVUL to have a look. It looks very similar to what we ha= ve in VUnit. I noticed the example test bench bitvis_irqc/tb/irqc_tb.vhd co= uld benefit from the VUnit Python/VHDL automation. My interpretation is tha= t you use log messages with ID_LOG_HDR to visually/textually separate diffe= rent independent test cases. I count 8 of those. With VUnit you could have = those 8 as actual independent test cases run in different simulations (or o= ptionally all in the same simulation) with individual pass/fail in the test= report. An individual specific test can be easily run from command line us= ing wildcard (*) pattern. VUnit would also ensure that each test case got i= ts own dedicated output folder to gather all simulation artifacts such as t= he complete stderr/stdout, wlf and transcript as well as any other user def= ined outputs such as images other binary data files. =20 >=20 > On Saturday, June 20, 2015 at 12:21:59 PM UTC+2, Brian Drummond wrote: > > On Fri, 19 Jun 2015 07:20:39 -0700, espen.tallaksen wrote: > >=20 > > > Hi Olof, > > >=20 > > > I agree that BVUL only covers your item 2 above, but then again item = 2 > > > is where you can actually save by far the most hours in a complex FPG= A > > > project. Items 1 and 3 are also important, and will save quite a few > > > hours. > > >=20 > > > I think perhaps it could be great if we could cooperate on the > > > combination Vunit and BVUL, so that we could get the best out of two > > > worlds, but we could take that discussion off line ;-) > >=20 > > By all means take the details off-line but please summarize the outcome= =20 > > here! > >=20 > > Thanks to yourself, Olof and Lars for discussing - and indeed, creating= -=20 > > these useful tools! > >=20 > > -- Brian From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.140.234.150 with SMTP id f144mr26436305qhc.9.1434803280949; Sat, 20 Jun 2015 05:28:00 -0700 (PDT) X-Received: by 10.140.48.11 with SMTP id n11mr346798qga.35.1434803280887; Sat, 20 Jun 2015 05:28:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!q107no2286154qgd.0!news-out.google.com!k20ni2822qgd.0!nntp.google.com!q107no2286149qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 05:28:00 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5de9dc79-f386-4969-bb72-992724b3fa50@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Sat, 20 Jun 2015 12:28:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8326 P.S My previous post looks best when viewed with a monospace font. From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.68.195.166 with SMTP id if6mr26987082pbc.6.1434811693338; Sat, 20 Jun 2015 07:48:13 -0700 (PDT) X-Received: by 10.140.81.149 with SMTP id f21mr358718qgd.8.1434811693060; Sat, 20 Jun 2015 07:48:13 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!h15no6012414igd.0!news-out.google.com!k20ni2835qgd.0!nntp.google.com!q107no2309379qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 20 Jun 2015 07:48:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <0e87b19b-b8a3-4d20-921e-44653d734360@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <651b8d33-937b-48e3-a463-9335450780f6@googlegroups.com> Subject: Re: hands on experience on SystemC From: Lars Asplund Injection-Date: Sat, 20 Jun 2015 14:48:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8327 Den fredag 19 juni 2015 kl. 12:11:56 UTC+2 skrev alb: Hi Al, > > Thanks for sharing. The reason for me asking is that the message=20 > > passing in VUnit wasn't developed to support TLM for hardware out of=20 > > the box. It was developed to enable high-level communication within=20 > > testbenches, not within the DUT.=20 >=20 > I'm not sure to which question or statement you're referring to.=20 >=20 What I'm saying is that message passing in VUnit wasn't developed to suppor= t design space exploration of the to be synthesized hardware. It was develo= ped to have message passing which takes no time and has no capacity limitat= ions which is very useful within testbenches (outside of the DUT). When we = did this I recognized that it can be used for your purposes as well if supp= ort for those delay and capacity limitations is added. We decided to leave = this for the future to see what users want and when I saw this thread I sta= rted to wonder if the future is here. Anyway, you have time to learn something new so you should. Good luck! /Lars From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.13.231.133 with SMTP id q127mr54082403ywe.31.1435160719972; Wed, 24 Jun 2015 08:45:19 -0700 (PDT) X-Received: by 10.140.33.76 with SMTP id i70mr297667qgi.14.1435160719864; Wed, 24 Jun 2015 08:45:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z60no3079191qgd.1!news-out.google.com!k20ni3166qgd.0!nntp.google.com!q107no3080944qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jun 2015 08:45:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.94.31.2; posting-account=jtCNBQoAAADZI8arfM1SMrp1bc394Q4R NNTP-Posting-Host: 192.94.31.2 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6ef8a71a-87ee-4559-b7c7-5dcf5003e723@googlegroups.com> Subject: Hierarchical References and indexes From: dlp Injection-Date: Wed, 24 Jun 2015 15:45:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 13 Xref: mx02.eternal-september.org comp.lang.vhdl:8328 Hi, With external names, is there a way to use a generate index to select an instance? That is, gen: for i in 0 to 7 generate foo(i) <= << signal .tb.uut"i".MySig : std_logic >>; end generate; Where "i" should range from uut0 to uut7 ? Thanks dlp From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.52.72.161 with SMTP id e1mr53946884vdv.14.1435164120431; Wed, 24 Jun 2015 09:42:00 -0700 (PDT) X-Received: by 10.140.93.38 with SMTP id c35mr205394qge.38.1435164120371; Wed, 24 Jun 2015 09:42:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z60no3090954qgd.1!news-out.google.com!k20ni3172qgd.0!nntp.google.com!z60no3090949qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 24 Jun 2015 09:42:00 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Simplified Testbench Communication with Open Source Message Passing Mechanism From: Lars Asplund Injection-Date: Wed, 24 Jun 2015 16:42:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 7895 X-Received-Body-CRC: 947369722 Xref: mx02.eternal-september.org comp.lang.vhdl:8329 One of the previous posts (https://groups.google.com/forum/#!topic/comp.lan= g.vhdl/QYoZ_ufMP3g) went off topic to discuss the case for high-level model= ling in VHDL using message passing. This is a post to bring the discussion = on topic again by presenting the VUnit solution to message passing. Are the= re things you would like to see that is not covered by message passing in i= ts purest form? For example, using message passing to model communication i= n hardware which takes time and has capacity limitations. /Lars Summary =3D=3D=3D=3D=3D=3D=3D When your testbench grows to include several concurrent statements like pro= cesses and components surrounding the DUT it becomes important to coordinat= e the verification effort between these statements. This can be as simple a= s using synchronizing events implemented with boolean signals but when comm= unication involves significant information exchange and many modes like asy= nchronous, synchronous, broadcasting, and two-way interaction it becomes mu= ch more challenging. VUnit, the open source unit testing framework for VHDL= , includes a high-level message passing mechanism to handle this complexity (https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_= guide.md) Concept =3D=3D=3D=3D=3D=3D=3D In real life we use different modes of communication all the time when maki= ng phone calls, sending emails, and posting status updates on Facebook. We = do this with ease because the services we use let us focus on the informati= on to exchange and with whom. We don't have to know where our counterparts = are located and we don't have to care about infrastructure details like put= ting messages into FIFOs, routing them to the correct destination and so on= . The VUnit message passing mechanism, a.k.a. com, takes this approach to h= igh-level testbench communication and let you communicate using intuitive s= ubprogram calls like send, receive, publish, and request. The next section provides a few examples on how com is used. The complete t= utorial for com can be found at https://github.com/LarsAsplund/vunit/blob/m= aster/vhdl/com/user_guide.md and a testbench example is found at https://gi= thub.com/LarsAsplund/vunit/tree/master/examples/com. Com was developed in t= he open by a number of community members. If you want to see the discussion= s that led to this solution have a look at this thread https://github.com/L= arsAsplund/vunit/issues/23 Examples =3D=3D=3D=3D=3D=3D=3D=3D Inspired by the actor model (https://en.wikipedia.org/?title=3DActor_model)= a statement like a process that wants to communicate creates an actor for = itself variable test_sequencer : actor_t :=3D create("test sequencer"); To communicate with another statement you must find its actor, e.g. variable driver : actor_t :=3D find("driver"); A message can now be sent over the net(work). Any communication problems ar= e reported in the returned send receipt send(net,test_sequencer,driver,"Hello!",receipt); Messages are received, in this case by the driver, with the blocking receiv= e procedure. The received payload can then be processed. Here I'm just prin= ting it. receive(net,driver,message); report message.payload.all; Note that the locations of the actors are hidden, they can be in different = processes in the same file, in different files, or even in the same process= . You don't have to change the communication if you refactor the code such = that actors are moved. No details about the transport of messages are expos= ed other than that there is some sort of net(work) involved. Message passin= g is, in this case, asynchronous, you can send thousands of messages before= the receive procedure is called. The send call takes no time, only delta c= ycles. In this case I'm sending a string message and string is the only datatype c= om natively handles. Other datatypes have to be encoded/decoded to/from str= ing. For example, you can send an integer as encode(my_integer) and receive= it with my_integer :=3D decode(message.payload.all); Encode and decode functions for standard VHDL and IEEE datatypes are provid= ed by com, but more importantly, com will generate these functions for your= custom datatypes as well. For example, if you have a write_mem transaction= defined by a record like this type addr_data_msg_t is record msg_type : addr_data_msg_type_t; addr : integer; data : std_logic_vector(7 downto 0); end record addr_data_msg_t; where msg_type is a custom enumeration with values representing the bus tra= nsactions for which this record is used, e.g. write_mem, then com will prov= ide you with an encode function so you can do send(net,test_sequencer,driver,encode((write_mem, 17, X"A5")),receipt); but there is also a named encode function which makes the code more readabl= e send(net,test_sequencer,driver,write_mem(17, X"A5"),receipt); which you can wrap in a local procedure to get something even more readable write_mem(17, X"A5"); On the receiving side you will have support for parsing messages that arriv= e. They can have different msg_type and can be based on different records receive(net, driver, message); case get_msg_type(message.payload.all) is when write_mem =3D> -- Process write mem transaction when read_mem =3D> -- Process read mem transaction ... So you don't have to do anything other than defining your message types to = get the necessary support functions. If you want to broadcast a message to anyone interested you do publish inst= ead of send and remove the receiver parameter publish(net,test_sequencer,"Hello!",status); Actors interested in these publications have to subscribe to the publishing= actor and then receive messages in the normal way using the receive proced= ure. subscribe(driver,find("test sequencer"),status); You don't have to change anything to the publisher or existing subscribers = if a new actor becomes interested in what's being published and subscribes. Two-way interaction can be handled in a number or ways but the simplest way= to send a request and wait for a reply is request(net,test_sequencer,driver,request_msg,reply_msg); This will return the reply matching the request even if other messages arri= ve while waiting for the reply or requests are handled out of order at the = receiving side. A request can be the basis for a synchronous transaction li= ke read_mem, i.e. the call will return when the data is available. These were a few examples of what you can do. For more examples and details= jump to https://github.com/LarsAsplund/vunit/blob/master/vhdl/com/user_guide.md From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.50.13.97 with SMTP id g1mr14591962igc.13.1435570004492; Mon, 29 Jun 2015 02:26:44 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr153837qge.19.1435570004463; Mon, 29 Jun 2015 02:26:44 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2159390igd.0!news-out.google.com!4ni21980qgh.1!nntp.google.com!j5no1085873qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 02:26:44 -0700 (PDT) In-Reply-To: <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 29 Jun 2015 09:26:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8330 Hi Olof, My explanation to why BVUL is not just another flavour was unfortunately fa= r too brief. Let me elaborate a bit without doing any direct comparisons. - BVUL has ID-based verbosity control. Most other systems are priority base= d. Prioritising log-messages may seem like a good idea, but only works for = very basic testbenches. Simple example: What has the higher priority; a mes= sage saying you have received a packet header, or a message saying you have= received a complete packet? Obviously your priorities change from when yo= u debug your receiver, detecting header, address, correct CRC etc to when y= our receiver is properly debugged and you anly want to know that you have r= eceived a correct packet - or even 100 packets.... An ID-based verbosity s= ystem where you enable say ID_PACKET_HDR, ID_PACKET_COMPLETE and ID_PACKET_= DATA separately allows full flexibility and changing your priorities as you= develop your testbench. An ID-based verbosity control system is far easier= to use, as you control things based on functionality, which is just what y= ou want. It may even be used as a priority based system if you really want = to, but not he other way around. - BVUL has positive acknowledge on all checks, so that you may get a messag= e saying that check this and that (detailed info) has been executed and was= OK, and not just an alert if it fails (plus potential counting). The posit= ive acknowledge may of course be turned off. Very few systems have this cap= ability. - BVUL also have some other very useful features that most other libraries = do not have, but I think perhaps the most important aspect of BVUL is the e= xtremely low user threshold. We advice browsing through our provided PPT to= get an overview, but once you have done that - all feedback so far has bee= n that it is dead simple to use. In my experience as a consultant for 20 years now the testbench structure i= s the worst source of time wasting. If we take an average 5000 man hour FPGA development project I would say th= at on average the verification part (say 2500h) could have been reduced by = at least 1000 hours if they had structured their testbenches properly, and = provided good progress reports (logging) and alert handling. The IRQC example is more like a 20 hour project. I have included two bugs i= n the design and presented this at universities and in our course 'FPGA Dev= elopment Best Practices' and shown them the testbench log/alert transcript = only. They have always found the source of the bugs just by looking at the = transcript for less than 30 seconds - with no need for the wave view. The W= ilson report shows that nearly half of the verification time is spent on de= bugging. Then a proper progress report is key to efficiency. For larger designs of course even more so. I have definitely seen that proper regression testing mechanisms is also im= portant, which is why I say that your issues 1 and 3 are in fact also impor= tant, but my experience is that in this 5000 man hour project this would gi= ve an average improvement of say 100 hours, which is also very important. O= f course there are projects where this number is far higher, but similarly = there are projects wasting another 2000-3000 hours due to bad testbench str= ucture. Immediate stop on an error is my preferred way as well for simpler debuggin= g, but having a good progress report prior to the error helps a lot. (Sometimes however you run your test overnight, and then you may want to de= tect more bugs - either by running more separate test cases -e.g. using VUn= it, or by getting further into a test case which is really time consuming b= ecause it needs to be (some tests cannot be cut into short pieces). Again - I really do like the unit testing features of VUnit, and we do need= a structured approach to regression testing. This is why I think it would = have been great to cooperate to make all parts better. (I'll come back to t= hat in a separate response "further down")=20 From newsfish@newsfish Tue Dec 29 16:43:51 2015 X-Received: by 10.42.249.8 with SMTP id mi8mr10214127icb.15.1435570740465; Mon, 29 Jun 2015 02:39:00 -0700 (PDT) X-Received: by 10.140.37.129 with SMTP id r1mr151783qgr.18.1435570740433; Mon, 29 Jun 2015 02:39:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2168745igd.0!news-out.google.com!4ni22040qgh.1!nntp.google.com!z60no1011733qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 02:39:00 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2bbe9e22-3775-4261-b566-29302210b4ed@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Mon, 29 Jun 2015 09:39:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8331 Hi Brian, You wanted a summary of our off-line discussion on potential cooperation between VUnit and BVUL. I think the very brief version is that we agree to look into collaboration opportunities when they appear, but just now we are not quite there. Olof did however demonstrate the Unit testing capabilities of VUnit, and the fact that BVUL may be used seamlessly with VUnit, without making changes to any of them. -Espen From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.70.16.101 with SMTP id f5mr20923727pdd.14.1435599472116; Mon, 29 Jun 2015 10:37:52 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr71557qge.33.1435599472058; Mon, 29 Jun 2015 10:37:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j8no1836055igd.0!news-out.google.com!4ni24745qgh.1!nntp.google.com!j5no1245049qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 29 Jun 2015 10:37:51 -0700 (PDT) In-Reply-To: <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Mon, 29 Jun 2015 17:37:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 72 Xref: mx02.eternal-september.org comp.lang.vhdl:8332 Espen,=20 I can agree that lack of proper testbench structure is a big cause of ineff= iciency in a typical FPGA project. I wouldn't say that this is mostly due t= o missing library features but rather that due to lack of software/verifica= tion skills. It quite possible to write a good test bench without any suppo= rting library and also possible to write a poor test bench using a good sup= porting library. People will not learn to write good test benches quickly b= y using either BVUL or VUnit but rather primary by working in teams with pe= ople that possess the skills and secondary by taking verification courses. = Also in my opinion writing good test benches is more of a software skill. T= he people I know that are good at writing test benches also have software e= xperience and the people I know that are worse at it do not have much softw= are experience are are more purely hardware oriented. The libraries provide= d by BVUL/VUnit/OSVVM will provide the good test bench developer with bette= r tools than they would have taken the time to create for themselves and th= at is a still a big benefit. How great that it is possible to use them all = together further increasing the toolbox of the test bench writer.=20 I also agree that debugging is a big time waster. The solution is primarily= to avoid the need for debugging rather than making it easier. First let me= identify two types of debugging:=20 I) The first kind is when a bug is reported in the field and it must be re-= produced. The work performed while reproducing the bug can be called debugg= ing.=20 II) The second kind is when an existing module is extended or modified and = it causes a regression in an existing test. The process of figuring out why= the regression test failed can be called debugging.=20 The road to reducing the need for debugging is the use of a better verifica= tion methodology. By having many small tests that test a small piece of fun= ctionality the debugging effort in II) is greatly reduced. A large module c= an be significantly harder to modify or re-use when it only has a large end= -to-end test compared to when it has many smaller tests or even testw for i= t's sub-modules. Also when having small and quick tests the designer can re= -run the test more often even for smaller modifications, the easiest bug to= find is in the line you just wrote 10 seconds ago. The end-to-end test is = still necessary to ensure that the parts work as a whole but it should only= catch integration issues and not faults in the individual parts.=20 Lots of research and testimonies from software the development world, from = which there are many parallels to FPGA-development and a lot to learn, has = shown that using the method to write many small test of small parts increas= es the quality of the code base. It forces the design to be more modular an= d less tightly coupled with more well defined interfaces. This reduces the = likely-hood to have bugs which cause I) and also reduces the cost of modifi= cation/re-use. I have seen many 3000-line state machines in large modules w= ith only a big end-to-end test which should really have been split up into = multiple smaller parts. Such modules sooner or later just have to be re-wri= tten because they cannot accommodate new functionality. In many complex pro= jects or projects using agile methods the development process is nothing mo= re than a steady stream of modifications making the reduction of their cost= very beneficial. Many companies can also save money from re-using modules = between product families or new products with more or less modifications. I= n my opinion it is good regression testing that facilitates re-use rather t= han any IP-packaging format or similar stuff. So how does the methodology described above relate to VUnit? Well it was cr= eated to facilitate the methodology by significantly reducing the cost of h= aving many tests per test bench and many test benches both from the regress= ion testing use case as well as from a daily coding edit/compile/run use ca= se were a designer wants to quickly re-run multiple tests/test benches for = each small modification. It is by using this methodology, enabled by VUnit,= that a typical project can save a lot of time and dramatically increase qu= ality and re-usability. Just having the VHDL-part of VUnit or BVUL alone co= uld not nearly as well enable the above methodology but it is an important = piece of the puzzle non the less. I finally conclude that any BVUL user could benefit from using VUnit togeth= er with BVUL enabling the above methodology without using the parts of VUni= t that are redundant with BVUL as I have shown in my previous posts. From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.129.81.70 with SMTP id f67mr27813211ywb.7.1435654220584; Tue, 30 Jun 2015 01:50:20 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr50737qge.3.1435654220567; Tue, 30 Jun 2015 01:50:20 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j5no1467884qga.1!news-out.google.com!w15ni12593qge.0!nntp.google.com!z60no1390312qgd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 01:50:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Tue, 30 Jun 2015 08:50:20 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8333 Hi Olof, I final comment from my side. I agree with many of your points, but I think writing a good testbench depe= nds far more on your experience, structure, awareness of ROI (return on inv= estments) of such structure and a good methodology. The quality of this tes= tbench is *the* main key to efficiency and quality. And of course BVUL (or other similar libraires) is just one piece in this p= uzzle. For simple testbenches it is a major piece, but for complex testbenc= hes it is a minor piece, but still a corner stone for other pieces. For com= plex testbenches their structure is by far the most important piece. To ver= ify corner cases you need to be able to control different interfaces simult= aneously in a controlled manner, and for this Verfication components is the= best approach. We will hopefully present a solution for that at FPGAworld = in September with 'UVVM', that handles this in a very structured manner. Ot= her important pieces in this puzzle are constraint random, coverage, scoreb= oards, etc. I still agree that unit testing is also very important, but unfortunately f= or some applications some simulations are time consuming because you just h= ave to run for a long time before your DUT reaches a certain state, and you= have to verify that e.g. lots of different submodules work together as exp= ected. (By comparison verifying for instance the *implementation* of filter= s and sub-filters is dead simple.) Most huge state machines are bad design structure, but I guess that is a di= fferent discussion. (We spend nearly a day on that alone in our course 'FPG= A Development Best Practices'. So I agree this is definitely a problem form= many FPGA projects.)=20 Handling (or not handling) the complex verification scenarios is where lots= of projects are wasting several hundred man hours and sometimes far more t= han thousand man hours - either because they do labtest/patch-iterations fo= r ever or because they don't structure their testbenches sufficiently. And = for this they need methodology, awareness, structure at all levels and debu= g-support. BVUL is just a library that supports this approach very well, bu= t only for the basic logging, alert handling, proper verbosity control, che= cks and awaits. OSVVM is a different library that is excellent for contrain= ed random and coverage. Another library is UVVM (to be released in Septembe= r) that provides a very structured verification component environment and T= LM for a really understandable handling of simultaneous stimuli and checkin= g of multiple interfaces. In fact the combination of these three libraries = provides a unified testbench approach. And they could all work together with VUnit for unit testing :-) From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.50.128.231 with SMTP id nr7mr23346960igb.11.1435666999793; Tue, 30 Jun 2015 05:23:19 -0700 (PDT) X-Received: by 10.140.91.19 with SMTP id y19mr104273qgd.6.1435666999764; Tue, 30 Jun 2015 05:23:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2336130igd.0!news-out.google.com!w15ni13172qge.0!nntp.google.com!j5no1530960qga.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 05:23:19 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <48fee56f-9b65-413e-a046-cc830ba4b79e@googlegroups.com> <2c86a8c3-b324-4baf-a492-85337a92e408@googlegroups.com> <6f94f772-1cd3-43bd-b11a-7694bd10d872@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Tue, 30 Jun 2015 12:23:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8334 Hello, Interesting discussion! As Espen mentioned we will take small steps where we find common grounds an= d in the first iteration VUnit will provide better support for coexistence = between the two libraries in addition to the possibilities already existing= . We will provide means to handle the name collision that exists for the lo= g procedures and we will also provide a thoroughly documented example on ho= w coexistence is achieved. I'll get back when this is on Github. Next, I would like to comment on the last few posts. Olof had already said = a lot about the productivity gains with unit testing but this is very impor= tant point so I will add a bit more (and probably repeat a bit) First of all, the productivity gain of unit testing is NOT a result of the = time saved running all your self-testing testbenches automatically rather t= hen opening the GUI, load the testbench, and then hit run for each and ever= y one. It comes because it enables very short code/test cycles so you can s= tart test early and do it frequently. When I say frequently I mean at the p= ace you add bugs to your code which is many times a day (at least I do). Th= is frequency won't happen unless you have a tool chain supporting that. Som= e benefits are: - The obvious one is that the sooner you find the bug the less damage for y= ou and your team. Ideally you should find the bug when the code is still fr= esh in the developer's mind. - When you have a fully automated test environment you also become very res= ponsive to the changes in requirements and design that happens all the time= in most projects. If you can fix these change requests and quickly make su= re that everything still works then you have a competitive edge. Take the V= Unit project as an example. Since it was released about half a year ago 8 c= ontributors have done about 250 commits which added about 30000 lines of so= mething (code and documentation) and removed about 12000 lines. An enhanced= version of the tool is typically made public one or several times a week (= and it's not about continuous bug fixing). Considering that we support seve= ral simulators, VHDL standards, Python versions, and operating systems this= would not be possible to do unless we had test suites verifying the qualit= y of each and every release. Ok, we don't have the many hour tests, synthes= is and place and route but even if you have the release cycle can be very q= uick if you automate - When test becomes such an integral part of what the developer do it also = starts to affect the quality of the code in a positive way. Code that is ha= rd to test is a bad code smell, i.e. an indication of bad quality. This mea= ns that the drive to do low-level testing also enhances the quality at that= level. You may discover these bad smells when testing later at a higher le= vel as well but then it's much harder to correct. Since test drives the des= ign many unit test practioners adopt test-driven design (TDD) where the bas= ic concept is to write the test first and then implement the design that ma= kes that test pass. What I'm saying is that unit testing enables a way of working affecting man= y parts of the project not just verification and that's why it has such an = impact. The effect on project success rates has been showed in research Some words about what we support and what we don't. VUnit also use "ID-based verbosity control" but we don't call it ID but sou= rce. For example, here I'm doing a debug log with no special source: debug("This is a debug message); But I can add a source (ID) if I want: debug("This is a debug message", "Some source name"); If I want to stop messages from "Some source name" to appear on stdout I ca= n add stop_source("Some source name", display_handler, filter); What I done is to add a stop filter to the display handler. I can individua= lly decide what filters to have for the log file (if any) by using the file= _handler instead. The filter returned is there so that it can be removed. I= can add many filters to a handler, have pass filters, filter on log level,= e.g. log all debug messages to file but don't show them on the display. I = can also filter hierarchies. https://github.com/LarsAsplund/vunit/blob/mast= er/examples/logging/logging_example.vhd will show the different capabilitie= s VUnit doesn't support positive acknowledge on the checker/assert/alert leve= l. It hasn't really been asked for but I opened this issue (https://github.= com/LarsAsplund/vunit/issues/53) so that you can support its addition. It's= an easy fix. I think the reason for not normally seeing this among unit te= st frameworks is that it yields a lot of text. For example, the VUnit VHDL = part is verified with 22 test suites containing 280 test cases containing 1= 600 checks/asserts. We keep them public so that you can make your own modif= ications and possibly contribute code and be confident you didn't destroy a= nything (see https://github.com/LarsAsplund/vunit/blob/master/developing.md= ). When developing a piece of code I mostly run the test suite for that cod= e. Such a test suites contains, on average, 13 test cases and 75 checks. A = summary of 13 test cases is a good overview which you might read. 75 "passe= d" is a bit much a may not even fit in your window.=20 When we describe VUnit we usually go directly for the end goal with full au= tomation since that provides the greatest value. However, you can do this i= s smaller steps to set a threshold that fits you. I've seen different appro= aches to start using VUnit depending on project background but here is one = way starting with a pure VHDL testbench which makes it similar to BVUL. For= simplicity I've excluded any real DUT and only test basic VHDL behaviour. library vunit_lib; context vunit_lib.vunit_context; -- Get= all VUnit-related functionality entity tb_comp_lang_vhdl_example is generic ( runner_cfg : runner_cfg_t :=3D runner_cfg_default); -- U= se configuration from script or defaults end entity tb_comp_lang_vhdl_example; architecture test_fixture of tb_comp_lang_vhdl_example is begin -- Normally I would have a DUT, clock generators and so on here =20 test_runner: process is variable filter : log_filter_t; begin test_runner_setup(runner, runner_cfg); -- Set= up with provided configuration logger_init(runner_trace_logger, display_format =3D> raw); -- E= nable runner trace log on display with "raw" format. Only active on file by= default pass_level(runner_trace_logger, info, display_handler, filter); -- Exl= ude details and only display basic info, in this case currently active test= case while test_suite loop -- Loo= p over the set of test cases if run("Test that addition works") then -- Eve= ry if statement branch like this defines a named test case check(1 + 1 =3D 2, "VHDL can't do addition!"); -- U= se various checks for verification elsif run("Test that subtraction works") then check_equal(5 - 3, 2); end if; end loop; info(LF & "=3D=3D=3D Summary =3D=3D=3D"); info(to_string(get_checker_stat)); -- Mak= e an info message of basic statistics test_runner_cleanup(runner); -- Wra= p-up end process test_runner; end; This will result i the following output in Modelsim # Test case: Test that addition works # Test case: Test that subtraction works #=20 # =3D=3D=3D Summary =3D=3D=3D # Checks: 2 # Passed: 2 # Failed: 0 Making this fully automated with Python requires another baby step. Just ad= d this run.py script from vunit import VUnit from os.path import join, dirname ui =3D VUnit.from_argv() lib =3D ui.add_library("lib") lib.add_source_files(join(dirname(__file__), "*.vhd")) ui.main() The three last lines are the most interesting. First create a VHDL library = called lib. Then add all the .vhd files found in the same directory as this= script file (in this case we only have one file). Then call main to run. I= t will find all VHDL files, figure out their dependencies so that they can = be compiled in the correct order and only compile what's needed based on ch= anges. Then it will find all testbenches (only one) and run their test case= s. Just type python run.py and you'll get the following result Starting lib.tb_comp_lang_vhdl_example.Test that addition works pass (P=3D1 S=3D0 F=3D0 T=3D2) lib.tb_comp_lang_vhdl_example.Test that addi= tion works (1 .9 seconds) Starting lib.tb_comp_lang_vhdl_example.Test that subtraction works pass (P=3D2 S=3D0 F=3D0 T=3D2) lib.tb_comp_lang_vhdl_example.Test that subt= raction works (0.5 seconds) =3D=3D=3D=3D Summary =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D pass lib.tb_comp_lang_vhdl_example.Test that addition works (1.9 seconds= ) pass lib.tb_comp_lang_vhdl_example.Test that subtraction works (0.5 seconds= ) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D pass 2 of 2 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D Total time was 2.4 seconds Elapsed time was 2.4 seconds =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D All passed! So it's really not very complicated. From run.py you also get various optio= ns (do python run.py -h to see them all) like running the tests on many par= allel cores and open and run a specific test case in the GUI. /Lars From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.50.66.146 with SMTP id f18mr24409566igt.11.1435677909005; Tue, 30 Jun 2015 08:25:09 -0700 (PDT) X-Received: by 10.50.66.141 with SMTP id f13mr293529igt.4.1435677908978; Tue, 30 Jun 2015 08:25:08 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!j8no2455781igd.0!news-out.google.com!a16ni9310ign.0!nntp.google.com!j8no3384066igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 08:25:08 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Tue, 30 Jun 2015 15:25:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8335 On Friday, June 12, 2015 at 9:39:45 AM UTC-4, espen.t...@bitvis.no wrote: > on average 50% of FPGA designers' time is spent on verification, and=20 > almost half of that verification time is spent on debugging. This means: >=20 > 1. Good reports for unexpected design behaviour is critical. > 2. Good progress reporting is also critical. > 3. Good basic testbench features are required >=20 > Thus we need a library with good functionality for mismatch reporting,=20 > progress reporting and for checks etc. that are needed for every single= =20 > testbench; like=20 Since one can just as easily do all of the above with straight VHDL and be = just as concise or even more so, it does not really follow that what is nee= ded is a 'library with good...'. =20 > - checking value against expected > - waiting for something to happen - with a timeout > - checking stability of a signal > - waiting for a signal to be stable for a given time (with timeout) >=20 > The only free library library (to my knowledge) to provide all this=20 > functionality is Bitvis Utility Library.=20 OK, but the VHDL language provides this as well. >=20 > If this sounds interesting, you should read the below intro. > You can download the library and PPT from=20 > http://bitvis.no/resources/utility-library-download/ without any=20 > registration. Thanks for providing, that in itself is a useful service. My read is that the library is way to low level to be an effective archive = to capture the original intent of the testbench which means that a testbenc= h written using Bitvis will be just as opaque as the testbenches you compla= in about now. As an example of checking register function (from slide 31 o= f the PowerPoint): write(C_ADDR_ITR, x"AA", "ITR : Set interrupts"); check(C_ADDR_IRR, x"AA", ERROR, "IRR"); Some simple observations: - The hard coded constants x"AA" are not independent. Changing one require= s you to change the second one. But this is not controlled by the code in = any way. - Similarly, as one works through the rest of the script, there are other h= idden dependencies that occur. - The expected response of the DUT is implicit (the reading back of data fr= om IRR and expecting it to be the same as what was written into ITR). At f= irst glance, one almost might thought it was an error to write to one regis= ter and expect some other register to read back that same data. The code y= ou have is actually just an undetectable typo away from being a 'write then= read back' test of just ITR (or IRR). - Although this particular test is simply testing the bits somewhat indepen= dently, those bits typically have definitions from a record but here you're= totally ignoring those definitions and turning on and off bits in a byte w= ith no regard for what that bit defines. While OK for a simple read/write = testing as you're showing, there is nothing in Bitvis that would let it sca= le it up to something more general which is what you would want once you ge= t beyond the simple read/write tests. Consider now this could be written i= n vanilla VHDL: -- Let's check operation of the 'This' and 'That' interrupt bits Fpga_Reg.ITR :=3D ( This_Interrupt =3D> "1", That_Interrupt =3D> "1", Reserved =3D> (others =3D> '0') ); reg_write(Fpga_Reg.ITR); Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is expecte= d=20 Fpga_Reg_Readback.IRR :=3D reg_read; assert (Fpga_Reg.IRR =3D Fpga_Reg_Readback.IRR) report "IRR register did not read back correctly" & LF & "Expected: Fpga_Reg.IRR=3D" & image(Fpga_Reg.IER) & LF & "Actual: Fpga_Reg_Readback.IRR=3D" & image(Fpga_Reg_Readback.IRR) severity ERROR; While the code is wordier, it is also self-documenting. Using the Bitvis li= brary, one would have to dig into a whole lot more design specific detail a= nd documentation (that is outside the scope of the testbench itself) just t= o understand what the testbench is trying to accomplish. With what I've sh= own, that should not be the case. As a bonus, you don't have any of the sh= ortcomings that I pointed out earlier either. Of course the main issue is that Bitvis, since it is attempting to be gener= ic, cannot be design specific, but in order to get good code clarity you do= want the executable code to be design specific. You do want to have execu= table that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then have a re= sponse of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex consta= nts...that then have to change as the 'Off_To_The_Races' bit gets moved fro= m bit 5 to bit 6. Testbench modelling at the top design level should start by modeling the bo= ard that the design will be put into. This then naturally leads to modelin= g the system that the board goes into as well. Following that approach pro= duces a library of parts that can then be reused in other testbenches becau= se they are modeling actual parts, not just something cobbled together to c= ontrol/check interface ABC of design XYZ. It will also produce XYZ design = specific stuff as well. I have yet to have a time when 'verbosity control' was something I would wa= nt. The testbench will stop on an error and I have the complete log file t= hat I need to debug the problem. What you don't mention at all that is use= ful is simply to produce multiple log files. For example, logging transact= ion that occur on a particular interface to a CSV file so that it can be pu= lled up in Excel. Using those interface log files along with the main tran= script log file is a powerful debug aid. I don't want to seem to be too harsh, it's not that I think the library is = 'bad'. Much of what you have is useful info, but the library while it may = improve how some people today write a testbench eventually it will stunt te= stbench development because it does not go far enough to produce maintainab= le code. While I accept that you have found users that find it useful, for= me it would be a big step backwards since it would produce less maintainab= le code and probably take just as long, or longer to develop in the first p= lace. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.140.146.133 with SMTP id 127mr29467116qhs.8.1435691352256; Tue, 30 Jun 2015 12:09:12 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr276239qge.19.1435691352241; Tue, 30 Jun 2015 12:09:12 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!t90no71380qga.0!news-out.google.com!w15ni14370qge.0!nntp.google.com!t90no71376qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 12:09:12 -0700 (PDT) In-Reply-To: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Tue, 30 Jun 2015 19:09:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 76 X-Original-Bytes: 6330 Xref: mx02.eternal-september.org comp.lang.vhdl:8336 Kevin, I agree with you that using low level checks in test benches makes them wor= se and hard to maintain. A good test bench will contain a lot of supporting= code to enable the actual test to be as high level as possible and read al= most as a specification.=20 This is why I previously argued that I do not think the check/log library i= s the most important part missing to experienced test bench writers. The de= signer still needs to write a lot of project specific supporting code to ra= ise the abstraction level of the test bench (and design). Many designers wo= uld still write unmaintainable test benches using BVUL/VUnit/OSVVM without = the proper experience. On the other hand the unique features of VUnit such as the Python test runn= ing and compilation automation provides a feature rich and rock solid imple= mentation of something that many VHDL teams re-invent all the time in the f= orm of a pile of scripts of varying quality. Using VUnit the design team ca= n focus entirely on writing their high level test benches while the entire = test running and compilation is managed by VUnit.=20 I can testify that in my latest project we used VUnit to manage well over 2= 00 test cases with test benches automatically configured to run for all gol= den data in a folder and test configured to run with all interesting combin= ations of generics. Many test benches contained multiple tests that were ru= n in individual simulations but that benefited from a shared test bench inf= rastructure. The test cases could be run on Jenkins using multiple machines= and processor cores. The test cases could be opened in the simulator GUI w= ith everything set up by just issuing a command. Just the necessary files w= ere recompiled when re-running. All it took was writing a VUnit run.py file= of about 100 lines where most of the code was related project specifics su= ch as enumerating the golden reference data and creating generic combinatio= ns to configure the multiple test runs of the same test bench/test case.=20 VUnit provides the features that all serious verification efforts need righ= t away without modification and the potential for re-use is the greatest. I= gives every team access to a turn key solution worth several man-months of= work. I should also say that the low level functions found in the VHDL par= t of VUnit as well as BVUL/OSVVM are still useful and saves redoing some re= dundant work but they would not take that many days for the experienced VHD= L designer to re-implement the essential parts of them compared to implemen= ting something comparable to the sophisticated automation features of VUnit= which would not be possible within the budget of a single project. I also should say there are a lot of advanced features of BVUL and especial= ly OSVVM that can be really useful in some situations though that would wou= ld take the average designer many weeks to implement. Although a lot of cod= e has to be design specific due to the static nature of VHDL it is great th= e people have taken the time to make the obviously general parts available = as open source such that they do not need to be re-invented. In general I t= hink the FPGA/VHDL community is too shy of sharing their code and experienc= es compared to the software community. There is also a lack of standardizat= ion in verification tools and libraries compared to the software community = where specific languages have de-facto standard testing tools that everyone= uses. =20 The top two re-usable VHDL library features I tend to use are the check_equ= al procedures of VUnit, the dynamic array type of VUnit, as well as the ran= dom number generation from OSVVM. It does not mean that I use the check_equ= al procedures directly often but rather as part of higher level design spec= ific checking procedures that I create. A higher level checking procedure s= till must sometime contain a primitive check_equal of std_logic_vector, sig= ned, unsigned or integer etc. It is nice not to have to create a "Got XXXX = expected XXXX" message in manual assert statements all the time. Just becau= se there is a primitive method does not mean that you are encouraged to use= it directly. I suspect that the BVUL authors realize this but when showing= examples one does not want to obfuscate the usage to much by showing a sim= ple case. Our VUnit examples are also simplistic for the same reasons.=20 Due to the static nature of VHDL a library can not provide much general fun= ctionality and one must often write redundant code even with 2008 generic p= ackages. Since VUnit is not just a VHDL library but also Python framework w= hich parses the code we can do better in removing the need for redundant co= de by using code generation were packages are scanned for records for which= automatic to_string and check_equal can be generated. We have some such co= de-generation/pre-processing features already and plan to add more as use c= ases are identified. From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.42.73.70 with SMTP id r6mr31922289icj.30.1435695734376; Tue, 30 Jun 2015 13:22:14 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr135170qgd.29.1435695734347; Tue, 30 Jun 2015 13:22:14 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no165378igc.0!news-out.google.com!w15ni14519qge.0!nntp.google.com!t90no95407qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 13:22:14 -0700 (PDT) In-Reply-To: <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Tue, 30 Jun 2015 20:22:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8337 Hi Kevin, Although I agree that a lot can be done with plain VHDL I still think there= are use cases for both verbosity control and support procedures replacing = assert statements. One place where I think verbosity control is useful is when you have a trac= e log like the one I showed in the previous comment (runner_trace_logger). = I don't want to filter what goes to file because I don't know what will be = interesting before I have the problems that caused me to open the file. The= file may become very large but as you suggest the CSV format (we call it v= erbose_csv) enable you to use the power of your spreadsheet tool to reduce = the file to the interesting parts. During long simulations I may also want = to get some progress from the trace log on stdout but there's no point if I= can't reduce that output to a message pace which I can read. For that I us= e verbosity control on the log level. When it comes to assert statements like the one you mention I think they ca= n be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not read= back correctly"); while still being self-documenting. Given that a check for equality is one = of the most common ones this will save you a lot of redundant typing. In ca= se of an error you will get the following output (level format). ERROR: Equality check failed! Got 1. Expected 0. IRR register did not read = back correctly. Another good thing about standard check and log procedures, at least for us= writing tools, is that they are easier to parse such that you can add code= -related feature not available in VHDL itself. For example, if you enable t= he location preprocessor in your VUnit run script (ui.enable_location_prepr= ocessing()) and the have a log like this info("Some log message"); the output will be like this (verbose format) 0 ps: INFO in (tb_demo.vhd:27): Some log message This is useful when finding things and filtering your CSV file in Excel. A = drawback is that it is the preprocessed file you will see in the simulator = and you my be tempted to edit that one and not the original file. Another issue with convenience procedures like check_equal is that we suppo= rt a commonly used but limited set of data types so if you want to make an = equality check between other types you're back to the plain assert. But to = do the assert in your example you need to define "=3D" and image() for that= type. If you define a to_string() function instead of image() and enable t= he check preprocessing (ui.enable_check_preprocessing()) you can do like th= is check_relation(Fpga_Reg =3D Fpga_Reg_Readback, "Registers did not read back= correctly"); and a failed test will output this ERROR: Relation Fpga_Reg =3D Fpga_Reg_Readback failed! Left is ('1', '1'). = Right is ('1', '0'). Registers did not read back correctly check_relation can be used with any relational operator and type as long as= the operator and to_string() functions are defined. There are some drawbac= ks, primarily if an operand is a function with side effects. This function = is called twice, one time when checking the relation and one time when calc= ulating the error response string. This is not obvious when looking at the = procedure call before it has been preprocessed. For more details see https:= //github.com/LarsAsplund/vunit/blob/master/examples/vhdl/check/check_exampl= e.vhd /Lars From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.182.48.232 with SMTP id p8mr32351192obn.43.1435721486134; Tue, 30 Jun 2015 20:31:26 -0700 (PDT) X-Received: by 10.140.19.76 with SMTP id 70mr297805qgg.21.1435721486026; Tue, 30 Jun 2015 20:31:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no202523igc.0!news-out.google.com!4ni33175qgh.1!nntp.google.com!t90no144344qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 20:31:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:7113:740f:81a6:3226; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:7113:740f:81a6:3226 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Wed, 01 Jul 2015 03:31:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8338 On Tuesday, June 30, 2015 at 4:22:16 PM UTC-4, Lars Asplund wrote: > Hi Kevin, >=20 > One place where I think verbosity control is useful is when you have a tr= ace=20 > log like the one I showed in the previous comment (runner_trace_logger). = I=20 > don't want to filter what goes to file because I don't know what will be= =20 > interesting before I have the problems that caused me to open the file. Exactly. No filtering. At the point where the sim stops at an assertion, = I have everything I need so there is no need to filter anything. I also do= n't necessarily need to look at everything in the file since I'm debugging = a specific problem. I would look at the transcript window or file for basi= c information, I would look at auxiliary files if necessary but primarily I= will be looking at the signals and variables at the point where the sim st= opped in order to determine why the assertion condition failed. > During long simulations I may also want to get some progress from the tra= ce=20 > log on stdout but there's no point if I can't reduce that output to a mes= sage=20 > pace which I can read. For that I use verbosity control on the log level. For that I simply grab the scroll bar which effectively pauses the window. = Or, if I have the transcript set to go to an output file rather than the G= UI, I simply open the file in a text editor while the sim keeps on running. >=20 > When it comes to assert statements like the one you mention I think they = can=20 > be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 >=20 > check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not re= ad=20 > back correctly"); >=20 Not quite. Your example, which I was following, looked like ITR and IRR we= re both software registers. Both of them looked to be eight bits wide whic= h implies to me, that the individual bits would be defined in a record and = used the way that I was showing. So the comparison between the ITR and IRR= would be between two design specific record types, not just std_logic. This means that your example here of check_equal wouldn't work without firs= t creating an override of check_equal that works with those specific record= types. That's OK, but it means that now when you define new record types,= you'll have to also create a 'check_equal' override. Right now, when I cr= eate a record type, there will typically be overridden functions of to_std_= ulogic_vector, from_std_logic_vector and frequently, but not always image. = Having to add another override for 'check_equal' is more work, so I would = have to be convinced of the value to do so first. Actually, of late, what = I've found to be more useful is a 'diff_image' function that takes two reco= rd type arguments and returns an image only where record elements between t= he two are different. That way, I'm not eyeballing 10 different fields tha= t are the same to weed out the one or two that are different when the asser= tion fails and prints the 'diff_image'. > while still being self-documenting. Given that a check for equality is on= e of=20 > the most common ones this will save you a lot of redundant typing.=20 I agree that wrapping the assertion into a procedure will typically save ty= ping. On the other hand, many times that typing is only actually done one = time within a procedure that may gets called all over the place so the savi= ngs on typing isn't really there. >=20 > Another good thing about standard check and log procedures, at least for = us=20 > writing tools, is that they are easier to parse such that you can add cod= e- > related feature not available in VHDL itself. For example, if you enable = the=20 > location preprocessor in your VUnit run script=20 > (ui.enable_location_preprocessing()) and the have a log like this >=20 > info("Some log message"); >=20 > the output will be like this (verbose format) >=20 > 0 ps: INFO in (tb_demo.vhd:27): Some log message >=20 > This is useful when finding things and filtering your CSV file in Excel. = A=20 > drawback is that it is the preprocessed file you will see in the simulato= r=20 > and you my be tempted to edit that one and not the original file. >=20 We may be talking about different things. Whereas the assertion output log= ging and whatever one puts to the console is one thing, the CSV files I wou= ld typically generate are totally separate files that are not nearly so fre= e form as what would go to the console/transcript window. As an example, there might be a monitor procedure which takes address, data= , read/write commands, wait/ack signals all as inputs and whenever a transa= ction on that bus completes, a new line is written with sim time, address, = command, data. No filtering or simply using Excel's built-in filtering has= always been enough, no pre-processing needed. The one drawback is that Ex= cel locks the file when it opens so one has to either make a copy of the fi= le if the sim is still running, or you have to stop the sim. Otherwise, th= e sim quickly stops because it won't be able to write out that new line. B= ut even that isn't all that bad, because it doesn't actually crash Modelsim= , it just stops the sim on the 'file_open' but the subsequent writes to the= file complete normally (since I don't start the sim then until I have fini= shed looking at the CSV file) so I haven't actually lost anything. It seems= to be an odd, but fortuitous feature/bug of Modelsim. > Another issue with convenience procedures like check_equal is that we sup= port=20 > a commonly used but limited set of data types so if you want to make an= =20 > equality check between other types you're back to the plain assert. I think the better approach as I mentioned earlier would be to override che= ck_equal to work with the custom type. Within that overridden procedure on= e would call the Bitvis library check_equal procedure on the individual ele= ments of the custom type. > But to do the assert in your example you need to define "=3D" and image()= for that type. Yes for 'image', but no you don't for '=3D'. > If you define a to_string() function instead of image() and enable the ch= eck=20 > preprocessing (ui.enable_check_preprocessing()) you can do like this >=20 > check_relation(Fpga_Reg =3D Fpga_Reg_Readback, "Registers did not read ba= ck correctly"); >=20 > and a failed test will output this >=20 > ERROR: Relation Fpga_Reg =3D Fpga_Reg_Readback failed! Left is ('1', '1')= . Right is ('1', '0'). Registers did not read back correctly >=20 I don't see how you can only pass in a Boolean (i.e. "Fpga_Reg =3D Fpga_Reg= _Readback" and have it print out the individual 'left' and 'right' sides of= that comparison. Did you not include something? Looking through the Zip = file from Bitvis, I couldn't find any 'check_relation' so it's not clear to= me what is going on here. > check_relation can be used with any relational operator and type as long = as=20 > the operator and to_string() functions are defined. Again, it's not clear to me what 'check_relation' actually is since it appe= ars to take as input a Boolean and a text string. > For more details see https://github.com/LarsAsplund/vunit/blob/master/exa= mples/vhdl/check/check_example.vhd Unfortunately, that file does not have the source for 'check_relation', onl= y examples (which are essentially like you've shown here) which would not a= llow you to separate the two things that are being compared (i.e. This =3D = That) to report individually on 'This' and 'That'. All you can report on i= s the Boolean that is the result of comparing 'This' with 'That'. Anyway, the bigger issue I thought was the way that the PPT example seemed = to indicate how clean and easy it is to have simple read and write procedur= es that are only working with hard coded constants. The reality is that th= ose hard coded constants would be a maintenance nightmare since they are co= mpletely separated from the underlying design elements. The effect of chan= ging a constant from x"AA" to x"AB" and how that change would then ripple i= nto and affect upcoming statements was not addressed at all. Removing the = design specific elements and working only with std_logic/std_logic_vectors = at the 'higher level' testbench source code level is a mistake and will bec= ome a maintenance nightmare for whoever follows this approach. The proper = place to work with std_logic/std_logic_vectors is only within helper functi= ons and procedures that encapsulate something. The 'higher level' testbenc= h code would only be working with this encapsulating function/procedure so = the fact that it then converts something to std_logic/std_logic_vectors is = just something that happens behind the scenes...which is exactly what you w= ould want. I realize the PPT is taking an easy to understand example so as to focus on= the testbench aspects but that is not an excuse for this kind of oversight= . As a thought experiment, take the PPT example and simply add the conditi= on that certain bits in either ITR or IRR or both will always be 0 even if = they are written as 1 (i.e. the bits are being reserved for future use whic= h is not an uncommon thing). To put that change in, the way I approach it = would involve changes to only the to_std_ulogic_vector, from_std_logic_vect= or functions that I mentioned previously. These functions exist in the sam= e package as the defining record type. Edit those two functions to force 0= on the appropriate bit fields, recompile and you're done. Zero changes at= the testbench level. I could also easily take it a step further and add a= n assertion inside those functions that checks to see if those bit fields r= eally are 0. Now look at what you would have to edit with the PPT source t= hat is shown...a whole bunch of editing of hard coded constants. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.67.6.196 with SMTP id cw4mr31782673pad.46.1435728559650; Tue, 30 Jun 2015 22:29:19 -0700 (PDT) X-Received: by 10.140.98.138 with SMTP id o10mr186263qge.33.1435728559394; Tue, 30 Jun 2015 22:29:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!ff1no316816igc.0!news-out.google.com!4ni33175qgh.1!nntp.google.com!t90no153865qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 22:29:19 -0700 (PDT) In-Reply-To: <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.113.191.174; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 213.113.191.174 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <37c3c8f4-f1a6-42e0-879f-50647da19d04@googlegroups.com> <0cad22af-1ab1-45c9-a3a6-1801303777ad@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1157a6ab-68e9-4f58-8c26-4ed280e4fb3d@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: olof.kraigher@gmail.com Injection-Date: Wed, 01 Jul 2015 05:29:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8339 Kevin,=20 Lars is talking about the VUnit procedure check_relation and not anything i= n Bitvis. The reason it looks like it takes a boolean but can show a string= message is that the code is pre-processed by a Python script rewriting the= call. Such pre-processing is an optional feature that can be enabled in VU= nit. As I mentioned in my previous reply to you, since VUnit is not just a = VHDL library but a complete tool it could do things like preprocessing and = code generation on the fly. Code generation of to_string and check_equal on= all records within a package is something that we are thinking about doing= to save redundant code. We are still exploring this area. From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.129.90.214 with SMTP id o205mr31863437ywb.1.1435731966392; Tue, 30 Jun 2015 23:26:06 -0700 (PDT) X-Received: by 10.140.100.136 with SMTP id s8mr284739qge.2.1435731966355; Tue, 30 Jun 2015 23:26:06 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!t90no159675qga.0!news-out.google.com!4ni33200qgh.1!nntp.google.com!t90no159673qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 30 Jun 2015 23:26:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.121.237.82; posting-account=fZovLAoAAAD3S-AUwPsJor4VbxwCeVmC NNTP-Posting-Host: 80.121.237.82 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Subject: How to generate unique ID for each FPGA using Ring Oscillator PUF From: mubinicyer@gmail.com Injection-Date: Wed, 01 Jul 2015 06:26:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 8218 X-Received-Body-CRC: 1223908378 Xref: mx02.eternal-september.org comp.lang.vhdl:8340 Hi, I am designing a Physically Uncolonable Function using Ring Oscillator on F= PGA (Spartan6). However, it does not generate uniqe ID for each chip, it ge= nerates exactly same value for different chips. Different ROs must generate= different frequency due to die-imperfection. I will compare those frequenc= ies and generate bits, which should be unique for each chip, since each chi= p has different physicall die-imperfection. First, I generate 16 ROs, each with 51 inverter gates, all of them are conn= ected to two multiplexers, I connected the select inputs of multiplexers wi= th 8-bit dip-switch. Outputs of multiplexers are connected to two 16-bit co= unters. Outputs of counters are connected to a comparator, If first counter= reachs end value (111...11) (if it is faster than second counter) comparat= or gives '1', if second counter is faster than first, comparator gives a '0= '. This generates only one bit. I replicated this design 16-times to genera= te 16-bit response. The first bits of this response (3 downto 0) are connec= ted to 4-leds. I tested the design with 3 different chips, they give exactl= y same respnose, which is not desired. How can I make it in order to have different responses? Thanks. ring_oscillator.vhd: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ring_oscilator is generic (delay: time :=3D 200ps; chain_len: integer :=3D 16); port( rst_i : in std_logic; ro_o : out std_logic); end ring_oscilator; architecture Behavioral of ring_oscilator is signal chain : std_logic_vector(chain_len downto 0); attribute keep: boolean; attribute keep of chain: signal is true; begin --assert chain_len mod 2 =3D 1 report "Length of ring must be an odd number= !" severity failure; gen_chain: for i in 1 to chain_len generate chain(i) <=3D not chain(i-1) after delay; end generate; chain(0) <=3D chain(chain_len) nor rst_i after delay; ro_o <=3D chain(chain_len); end Behavioral; debounce.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity debouncer is generic( counter_size : INTEGER :=3D 19); --counter size (19 bits gives 10.5ms= with 50MHz clock) port( clk_i : in std_logic; --input clock button_i : in std_logic; --input signal to be debounced enable_i : in std_logic; -- for simulation result_o : out std_logic); --debounced signal end debouncer; ARCHITECTURE logic of debouncer is signal flipflops : std_logic_vector(1 downto 0); --input flip flops signal counter_set : std_logic; --sync reset to zero signal counter_out : std_logic_vector(counter_size downto 0) :=3D (others= =3D> '0'); --counter output begin counter_set <=3D flipflops(0) xor flipflops(1); --determine when to sta= rt/reset counter =20 process(clk_i) begin if rising_edge(clk_i) then flipflops(0) <=3D button_i; flipflops(1) <=3D flipflops(0); =09 if enable_i =3D '1' then if(counter_set =3D '1') then --reset counter because in= put is changing counter_out <=3D (others =3D> '0'); elsif(counter_out(counter_size) =3D '0') then --stable input time is not= yet met counter_out <=3D counter_out + 1; else --stable input time is met result_o <=3D flipflops(1); end if; else result_o <=3D button_i; end if; end if; end process; end logic; top.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_misc.ALL; use IEEE.std_logic_unsigned.ALL; use ieee.numeric_std.all; entity top is Generic ( nr_ro : natural :=3D 16; puf_width : natural :=3D 16 ); Port ( =09 shift_i : in std_logic ; --debug dout_o : out std_logic_vector(3 downto 0); --debug =09 sel_i : in std_logic_vector(7 downto 0); --debug=09 clk_i : in STD_LOGIC; rst_i : in STD_LOGIC--;=20 -- puf_out : out STD_LOGIC_VECTOR (puf_width-1 downto 0) ); end top; architecture Behavioral of top is constant c_width : natural :=3D puf_width; constant c_number_of_ro : natural :=3D nr_ro; =20 -----------------------------DEBUG------------------------------------- signal s_sel : std_logic_vector(7 downto 0) :=3D (others =3D> '0'); signal s_dout : std_logic_vector(3 downto 0) :=3D (others =3D> '0'); signal s_shift : std_logic :=3D '0'; signal s_shift_pre : std_logic :=3D '0'; signal s_pulse : std_logic :=3D '0'; =09 signal s_msb : integer range 0 to 16 :=3D 4; -----------------------------------------------------------------------=09 signal s_reset : std_logic :=3D '0'; signal s_finish : std_logic_vector (c_width-1 downto 0):=3D (others =3D>= '0'); signal s_finished : std_logic :=3D '0'; signal s_puf_out : std_logic_vector (c_width-1 downto 0):=3D (others =3D>= '0'); --------------components---------------------------- component puf_bit generic ( nr_ro: natural :=3D c_number_of_ro ); port ( clk_i : in std_logic; rst_i : in std_logic; sel1_i : in unsigned(3 downto 0); sel2_i : in unsigned(3 downto 0); finish_o : out std_logic; puf_bit_o : out std_logic ); end component; component debouncer generic(counter_size : integer :=3D 19); --counter size (19 bits gives 1= 0.5ms with 50MHz clock) port( clk_i : in std_logic; --input clock button_i : in std_logic; --input signal to be debounced enable_i : in std_logic;=20 result_o : out std_logic); --debounced signal end component; begin Generate_PUF: for i in 0 to c_width-1 generate =09 Multiple_Puf_Bits: puf_bit=20 generic map (nr_ro =3D> c_number_of_ro) port map ( clk_i =3D> clk_i,=20 rst_i =3D> s_reset,=20 sel1_i =3D> unsigned(s_sel(3 downto 0)), =20 sel2_i =3D> unsigned(s_sel(7 downto 4)), finish_o =3D> s_finish(i), puf_bit_o =3D> s_puf_out(i) ); end generate; =09 reset_debounce: debouncer generic map (counter_size =3D> 19) port map (clk_i =3D> clk_i, button_i =3D> not rst_i, enable_i =3D> '1'= , result_o =3D> s_reset); --On FPGA board btn is low active =09 btn_debounce: debouncer generic map (counter_size =3D> 19) port map (clk_i =3D> clk_i, button_i =3D> not shift_i, enable_i =3D> '= 1', result_o =3D> s_shift); --On FPGA board btn is low active =09 s_finished <=3D AND_REDUCE(s_finish); ------------ debug-------------------------------- s_sel <=3D sel_i; =20 dout_o <=3D s_puf_out(7 downto 4); ----------------------------------------------=09 end Behavioral; From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.140.238.201 with SMTP id j192mr32919590qhc.14.1435734960577; Wed, 01 Jul 2015 00:16:00 -0700 (PDT) X-Received: by 10.140.105.10 with SMTP id b10mr291171qgf.26.1435734960559; Wed, 01 Jul 2015 00:16:00 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!t90no165573qga.0!news-out.google.com!w15ni14608qge.0!nntp.google.com!s91no165563qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 00:15:58 -0700 (PDT) In-Reply-To: <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.165.206.11; posting-account=FPy8ZgoAAABAPST4VlpRVJBCjaUMgWSD NNTP-Posting-Host: 85.165.206.11 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: espen.tallaksen@bitvis.no Injection-Date: Wed, 01 Jul 2015 07:16:00 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8341 Hi Kevin, Please see comments below. tirsdag 30. juni 2015 17.25.11 UTC+2 skrev KJ f=F8lgende: > On Friday, June 12, 2015 at 9:39:45 AM UTC-4, espen.t...@bitvis.no wrote: > > on average 50% of FPGA designers' time is spent on verification, and=20 > > almost half of that verification time is spent on debugging. This means= : > >=20 > > 1. Good reports for unexpected design behaviour is critical. > > 2. Good progress reporting is also critical. > > 3. Good basic testbench features are required > >=20 > > Thus we need a library with good functionality for mismatch reporting,= =20 > > progress reporting and for checks etc. that are needed for every single= =20 > > testbench; like=20 >=20 > Since one can just as easily do all of the above with straight VHDL and b= e just as concise or even more so, it does not really follow that what is n= eeded is a 'library with good...'. =20 Anything provided with almost any library can be done with straight vhdl. The point of a support library is 1. Improve overview, readability, maintainability and structure 2. Reduce amount of writing ONLY if all above is satisfied. >=20 > > - checking value against expected > > - waiting for something to happen - with a timeout > > - checking stability of a signal > > - waiting for a signal to be stable for a given time (with timeout) > >=20 > > The only free library library (to my knowledge) to provide all this=20 > > functionality is Bitvis Utility Library.=20 >=20 > OK, but the VHDL language provides this as well. See above comment. >=20 > >=20 > > If this sounds interesting, you should read the below intro. > > You can download the library and PPT from=20 > > http://bitvis.no/resources/utility-library-download/ without any=20 > > registration. >=20 > Thanks for providing, that in itself is a useful service. >=20 > My read is that the library is way to low level to be an effective archiv= e to capture the original intent of the testbench which means that a testbe= nch written using Bitvis will be just as opaque as the testbenches you comp= lain about now. As an example of checking register function (from slide 31= of the PowerPoint): >=20 > write(C_ADDR_ITR, x"AA", "ITR : Set interrupts"); > check(C_ADDR_IRR, x"AA", ERROR, "IRR"); >=20 > Some simple observations: > - The hard coded constants x"AA" are not independent. Changing one requi= res you to change the second one. But this is not controlled by the code i= n any way. Totally agree, but this was not at all the point in this example. The point is you write=20 'write(, , ) rather than lots of signal wiggling and other= vhdl statements. Almost everybody make BFMs (Bus Functional Modules) these days just for tha= t reason. The use of VHDL constants rather than literals is of course recommended, bu= t that was not the point here. > - Similarly, as one works through the rest of the script, there are other= hidden dependencies that occur. Again - this is up to the user. It has nothing to do with using the library= . > - The expected response of the DUT is implicit (the reading back of data = from IRR and expecting it to be the same as what was written into ITR). At= first glance, one almost might thought it was an error to write to one reg= ister and expect some other register to read back that same data. The code= you have is actually just an undetectable typo away from being a 'write th= en read back' test of just ITR (or IRR). I'm not sure I understand what you mean here, but again the DUT has nothing= to do with the library. The functionality of the ITR register is in fact very useful to system debu= gging. There are better ways of doing a write/read test, but again this is not the= point here. The examples here are also used in a course we have, where we later discuss= using constants, records, overloads, procedures calling procedures, etc. > - Although this particular test is simply testing the bits somewhat indep= endently, those bits typically have definitions from a record but here you'= re totally ignoring those definitions and turning on and off bits in a byte= with no regard for what that bit defines. While OK for a simple read/writ= e testing as you're showing, there is nothing in Bitvis that would let it s= cale it up to something more general which is what you would want once you = get beyond the simple read/write tests. Consider now this could be written= in vanilla VHDL: >=20 > -- Let's check operation of the 'This' and 'That' interrupt bits > Fpga_Reg.ITR :=3D > ( > This_Interrupt =3D> "1", > That_Interrupt =3D> "1", > Reserved =3D> (others =3D> '0') > ); > reg_write(Fpga_Reg.ITR); > Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is expec= ted=20 IRR is not supposed to be the same as ITR. More bits may be set in IRR from= previous interrupts or ITR writes. > Fpga_Reg_Readback.IRR :=3D reg_read; >=20 > assert (Fpga_Reg.IRR =3D Fpga_Reg_Readback.IRR) report > "IRR register did not read back correctly" & LF & > "Expected: Fpga_Reg.IRR=3D" & image(Fpga_Reg.IER) & LF & > "Actual: Fpga_Reg_Readback.IRR=3D" & image(Fpga_Reg_Readback.IRR) > severity ERROR; >=20 > While the code is wordier, it is also self-documenting. Using the Bitvis = library, one would have to dig into a whole lot more design specific detail= and documentation (that is outside the scope of the testbench itself) just= to understand what the testbench is trying to accomplish. With what I've = shown, that should not be the case. As a bonus, you don't have any of the = shortcomings that I pointed out earlier either. The shortcomings is up to the user. Use good constant names, records, etc. Nothing to do with BVUL. The BFM is in fact also not a part of BVUL, but I would definitely recommen= d it rather than using explicit assert statements. A BFM is more readable, easier to maintain, etc. Yes - you do have to understand the functionality of any procedure you use,= but without procedures and functions it is difficult to handle complex tes= tbenches. In this case one has to read somewhere that parameter 1 is addr, = p2 is data and p3 is message, OR you could use explicit parameter mapping. = In fact as long as you use unsigned, std_logic_vector and string respective= ly for these parameters you can't go wrong (other than compile error). There is a powerpoint presentation on how to use the library and the BFMs. = This can be browsed as a file, or you can even watch a 1 hour webinar. Ever= ything should be more obvious then. >=20 > Of course the main issue is that Bitvis, since it is attempting to be gen= eric, cannot be design specific, but in order to get good code clarity you = do want the executable code to be design specific. You do want to have exe= cutable that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then have a = response of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex cons= tants...that then have to change as the 'Off_To_The_Races' bit gets moved f= rom bit 5 to bit 6. BVUL does not stop you from using records. That is your choice.=20 > Testbench modelling at the top design level should start by modeling the = board that the design will be put into. This then naturally leads to model= ing the system that the board goes into as well. Following that approach p= roduces a library of parts that can then be reused in other testbenches bec= ause they are modeling actual parts, not just something cobbled together to= control/check interface ABC of design XYZ. It will also produce XYZ desig= n specific stuff as well. BVUL is only one piece in the puzzle. Please see my post above - starting w= ith 'Hi Olof, I final comment from my side'.=20 >=20 > I have yet to have a time when 'verbosity control' was something I would = want. The testbench will stop on an error and I have the complete log file= that I need to debug the problem. What you don't mention at all that is u= seful is simply to produce multiple log files. For example, logging transa= ction that occur on a particular interface to a CSV file so that it can be = pulled up in Excel. Using those interface log files along with the main tr= anscript log file is a powerful debug aid. For those who do post processing in other tools that is a good approach. There is nothing stopping you from using BVUL that way. For those who want to look at the transcript or a log file directly - verbo= sity control could be very useful. Also ID-based verbosity control allows very simple filtering as you have bo= th the scope and the ID available for that. >=20 > I don't want to seem to be too harsh, it's not that I think the library i= s 'bad'. Much of what you have is useful info, but the library while it ma= y improve how some people today write a testbench eventually it will stunt = testbench development because it does not go far enough to produce maintain= able code. While I accept that you have found users that find it useful, f= or me it would be a big step backwards since it would produce less maintain= able code and probably take just as long, or longer to develop in the first= place. There will always be different opinions and taste, but please spend the tim= e to go through the PPT to see the purpose of some of the features. >=20 > Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.182.214.9 with SMTP id nw9mr10439078obc.5.1435736512144; Wed, 01 Jul 2015 00:41:52 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr47017qge.3.1435736512034; Wed, 01 Jul 2015 00:41:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!ff1no358233igc.0!news-out.google.com!w15ni14611qge.0!nntp.google.com!t90no169106qga.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 00:41:51 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f0ba28b-a7db-4b1c-9455-862000b146ba@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Wed, 01 Jul 2015 07:41:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 170 Xref: mx02.eternal-september.org comp.lang.vhdl:8342 Hi Kevin In addition to what Olof said Den onsdag 1 juli 2015 kl. 05:31:28 UTC+2 skrev KJ: > On Tuesday, June 30, 2015 at 4:22:16 PM UTC-4, Lars Asplund wrote: > > Hi Kevin, > >=20 > > One place where I think verbosity control is useful is when you have a = trace=20 > > log like the one I showed in the previous comment (runner_trace_logger)= . I=20 > > don't want to filter what goes to file because I don't know what will b= e=20 > > interesting before I have the problems that caused me to open the file. >=20 > Exactly. No filtering. At the point where the sim stops at an assertion= , I have everything I need so there is no need to filter anything. I also = don't necessarily need to look at everything in the file since I'm debuggin= g a specific problem. I would look at the transcript window or file for ba= sic information, I would look at auxiliary files if necessary but primarily= I will be looking at the signals and variables at the point where the sim = stopped in order to determine why the assertion condition failed. >=20 > > During long simulations I may also want to get some progress from the t= race=20 > > log on stdout but there's no point if I can't reduce that output to a m= essage=20 > > pace which I can read. For that I use verbosity control on the log leve= l. >=20 > For that I simply grab the scroll bar which effectively pauses the window= . Or, if I have the transcript set to go to an output file rather than the= GUI, I simply open the file in a text editor while the sim keeps on runnin= g. I guess how you browse for information is much of a personal preference but= what I'm trying to say is that if I can't know in advance what information= that will be interesting I do not filter (and save to file). If I do know = in advance that I want to see that basic progress information among the tho= usands of debug message lines I rather set stdout verbosity than doing that= browsing. >=20 > >=20 > > When it comes to assert statements like the one you mention I think the= y can=20 > > be reduced to (here I'm assuming that IRR and ITR are std_logic).=20 > >=20 > > check_equal(Fpga_Reg.IRR, Fpga_Reg_Readback.IRR, "IRR register did not = read=20 > > back correctly"); > >=20 >=20 > Not quite. Your example, which I was following, looked like ITR and IRR = were both software registers. Both of them looked to be eight bits wide wh= ich implies to me, that the individual bits would be defined in a record an= d used the way that I was showing. So the comparison between the ITR and I= RR would be between two design specific record types, not just std_logic. >=20 > This means that your example here of check_equal wouldn't work without fi= rst creating an override of check_equal that works with those specific reco= rd types. That's OK, but it means that now when you define new record type= s, you'll have to also create a 'check_equal' override. Right now, when I = create a record type, there will typically be overridden functions of to_st= d_ulogic_vector, from_std_logic_vector and frequently, but not always image= . Having to add another override for 'check_equal' is more work, so I woul= d have to be convinced of the value to do so first. Actually, of late, wha= t I've found to be more useful is a 'diff_image' function that takes two re= cord type arguments and returns an image only where record elements between= the two are different. That way, I'm not eyeballing 10 different fields t= hat are the same to weed out the one or two that are different when the ass= ertion fails and prints the 'diff_image'. >=20 > > while still being self-documenting. Given that a check for equality is = one of=20 > > the most common ones this will save you a lot of redundant typing.=20 >=20 > I agree that wrapping the assertion into a procedure will typically save = typing. On the other hand, many times that typing is only actually done on= e time within a procedure that may gets called all over the place so the sa= vings on typing isn't really there. The idea is that check_equal should cover commonly used data types. If you = miss something that you feel is "common" you can create an issue on https:/= /github.com/LarsAsplund/vunit/issues. For other types you can use check_relation which will get some of the work = done for you. >=20 > >=20 > > Another good thing about standard check and log procedures, at least fo= r us=20 > > writing tools, is that they are easier to parse such that you can add c= ode- > > related feature not available in VHDL itself. For example, if you enabl= e the=20 > > location preprocessor in your VUnit run script=20 > > (ui.enable_location_preprocessing()) and the have a log like this > >=20 > > info("Some log message"); > >=20 > > the output will be like this (verbose format) > >=20 > > 0 ps: INFO in (tb_demo.vhd:27): Some log message > >=20 > > This is useful when finding things and filtering your CSV file in Excel= . A=20 > > drawback is that it is the preprocessed file you will see in the simula= tor=20 > > and you my be tempted to edit that one and not the original file. > >=20 >=20 > We may be talking about different things. Whereas the assertion output l= ogging and whatever one puts to the console is one thing, the CSV files I w= ould typically generate are totally separate files that are not nearly so f= ree form as what would go to the console/transcript window. >=20 > As an example, there might be a monitor procedure which takes address, da= ta, read/write commands, wait/ack signals all as inputs and whenever a tran= saction on that bus completes, a new line is written with sim time, address= , command, data. No filtering or simply using Excel's built-in filtering h= as always been enough, no pre-processing needed. The one drawback is that = Excel locks the file when it opens so one has to either make a copy of the = file if the sim is still running, or you have to stop the sim. Otherwise, = the sim quickly stops because it won't be able to write out that new line. = But even that isn't all that bad, because it doesn't actually crash Models= im, it just stops the sim on the 'file_open' but the subsequent writes to t= he file complete normally (since I don't start the sim then until I have fi= nished looking at the CSV file) so I haven't actually lost anything. It see= ms to be an odd, but fortuitous feature/bug of Modelsim. > Sorry for being a bit unclear here. What I meant was that having easy-to-pa= rse procedures like check() instead of assert and log() instead of report m= akes it easier to create preprocessing features like adding location inform= ation (file name and line number) to output messages. VHDL can give you *wh= en* something happened with "now" but not *where* it happen which is also v= ery interesting. You can optionally have this for both logs and checks but = I gave a log example (info("Some log message");) because I think that's whe= re you have the most value. With checks it can add a value if you don't sto= p at the first error but when you do you'll get the same and more informati= on from the call stack. > > For more details see https://github.com/LarsAsplund/vunit/blob/master/e= xamples/vhdl/check/check_example.vhd >=20 > Unfortunately, that file does not have the source for 'check_relation', o= nly examples (which are essentially like you've shown here) which would not= allow you to separate the two things that are being compared (i.e. This = =3D That) to report individually on 'This' and 'That'. All you can report = on is the Boolean that is the result of comparing 'This' with 'That'. >=20 As Olof mentioned the examples in the file are simplified to focus on the f= unctionality of the checks but I wasn't pointing to that. I was pointing at= some of the drawbacks of check_relation which are listed on line 215-217. = If you want to see how checks are implemented you should start here https:/= /github.com/LarsAsplund/vunit/tree/master/vhdl/check and if you want to see= how the preprocessing supporting check_relation works you should go to htt= ps://github.com/LarsAsplund/vunit/blob/master/vunit/check_preprocessor.py Regards, Lars From newsfish@newsfish Tue Dec 29 16:43:52 2015 X-Received: by 10.140.238.201 with SMTP id j192mr34135178qhc.14.1435751132330; Wed, 01 Jul 2015 04:45:32 -0700 (PDT) X-Received: by 10.140.38.180 with SMTP id t49mr324133qgt.9.1435751132311; Wed, 01 Jul 2015 04:45:32 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!s91no201901qgd.1!news-out.google.com!4ni33209qgh.1!nntp.google.com!s91no201896qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 1 Jul 2015 04:45:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:1986:560d:8afa:771c; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:1986:560d:8afa:771c References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: KJ Injection-Date: Wed, 01 Jul 2015 11:45:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8343 On Wednesday, July 1, 2015 at 3:16:04 AM UTC-4, espen.t...@bitvis.no wrote: > > Since one can just as easily do all of the above with straight VHDL and= be=20 > > just as concise or even more so, it does not really follow that what is= =20 > > needed is a 'library with good...'. =20 >=20 > Anything provided with almost any library can be done with straight vhdl. > The point of a support library is > 1. Improve overview, readability, maintainability and structure > 2. Reduce amount of writing ONLY if all above is satisfied. >=20 The examples in the PowerPoint compared with how I showed I would handle th= at same example do not agree with your statement. What I showed was self-d= ocumenting and more maintainable. What I was showing is only 'more writing= ' if you don't consider the additional documentation that would need to be = written to explain the testbench itself. > > Some simple observations: > > - The hard coded constants x"AA" are not independent. Changing one=20 > > requires you to change the second one. But this is not controlled by t= he=20 > > code in any way. >=20 > Totally agree, but this was not at all the point in this example. > The point is you write=20 > 'write(, , ) rather than lots of signal wiggling and oth= er=20 > vhdl statements. > Almost everybody make BFMs (Bus Functional Modules) these days just for t= hat=20 > reason. What I showed in my example was even simpler, no address was required at al= l at the top testbench level. What I showed was: reg_write(Fpga_Reg.ITR);=20 Fpga_Reg_Readback.IRR :=3D reg_read;=20 This is simpler than the Bitvis approach. Now obviously an address at some= point is required, but that address would be in the lower level helper pro= cedure that takes as input an argument of the specified record type. What = Bitvis demonstrated is read/write using std_logic_vectors. While this will= be needed, it should not be used at the top level of the testbench as Bitv= is was advocating. > The use of VHDL constants rather than literals is of course recommended, = but > that was not the point here. The point as I got it was how to use the Bitvis library in a testbench. Wh= at was advocated was using calls to the Bitvis library at the top level of = the testbench. The Bitvis library by itself does not provide the lower lev= el signal twiddling for a particular interface, a user would need to write = that. With my approach they would have to do this as well. At the testben= ch top level, the use of design independent std_logic_vectors as shown by B= itvis provides a less robust, less readable way than my approach which is t= o provide a simpler interface procedure which is explicitly tied to design = specific record definitions. > > - Similarly, as one works through the rest of the script, there are oth= er=20 > > hidden dependencies that occur. >=20 > Again - this is up to the user. It has nothing to do with using the libra= ry. >=20 No, but Bitvis provided the example to show the library. What I was demons= trating is the maintainability problems you will run into if you follow thi= s approach. You showed how easy and clean it is to have read/write procedu= res. I showed a slightly easier and cleaner approach, the main advantage t= hough is that it avoids those maintainability problems. The Bitvis example does not show the mess that would go into computing all = those hard coded constants which is where the mess and hidden dependencies = would make that approach much less maintainable then you seem to think. Wh= ile you can sit back and say the computation of those constants is outside = of the scope of the Bitvis library (and I agree it is), by not showing what= that code would look like using Bitvis and now not comparing it to how I p= ropose it should look, you're trying to avoid the issue. It's not that I d= on't think that Bitvis does what it says, it's that what it does doesn't be= long at the top level of the testbench and since it doesn't really provide = the lowest level of the testbench, it's not clear at what level it really w= ould be useful to me. > > - The expected response of the DUT is implicit (the reading back of dat= a=20 > > from IRR and expecting it to be the same as what was written into ITR).= At=20 > > first glance, one almost might thought it was an error to write to one= =20 > > register and expect some other register to read back that same data. T= he=20 > > code you have is actually just an undetectable typo away from being=20 > > a 'write then read back' test of just ITR (or IRR). >=20 > I'm not sure I understand what you mean here, but again the DUT has nothi= ng=20 > to do with the library. The point is that how the DUT is supposed to respond to something (i.e. the= write to ITR) is something that should be clear in the testbench. I made = that expected response explicit. The Bitvis example did not and actually c= ould be interpreted in a totally different way...because of the way the top= level testbench was written. > The functionality of the ITR register is in fact very useful to system=20 > debugging. Yes it is. > There are better ways of doing a write/read test, but again this is not t= he=20 > point here. The Bitvis example was not a write/read test. It was a functionality test.= You write to one register and expect a response from a different register= . A write/read test would check the response from the same register. > The examples here are also used in a course we have, where we later discu= ss > using constants, records, overloads, procedures calling procedures, etc. OK >=20 > >=20 > > -- Let's check operation of the 'This' and 'That' interrupt bits > > Fpga_Reg.ITR :=3D > > ( > > This_Interrupt =3D> "1", > > That_Interrupt =3D> "1", > > Reserved =3D> (others =3D> '0') > > ); > > reg_write(Fpga_Reg.ITR); > > Fpga_Reg.IRR :=3D Fpga_Reg.ITR; -- This is the DUT response that is exp= ected=20 >=20 > IRR is not supposed to be the same as ITR. More bits may be set in IRR fr= om=20 > previous interrupts or ITR writes. But not at that point in the testbench. The 'more bits' part shows up in a= totally undocumented way further down. With my approach, again that behav= ior would have been self-documenting. With the Bitvis example all that is = provided is a slew of hard coded constants with no code backing up the comp= utation of those constants. > >=20 > > While the code is wordier, it is also self-documenting. Using the Bitvi= s=20 > > library, one would have to dig into a whole lot more design specific de= tail=20 > > and documentation (that is outside the scope of the testbench itself) j= ust=20 > > to understand what the testbench is trying to accomplish. With what I'= ve=20 > > shown, that should not be the case. As a bonus, you don't have any of = the=20 > > shortcomings that I pointed out earlier either. >=20 > The shortcomings is up to the user. Use good constant names, records, etc= . > Nothing to do with BVUL. Agreed that the shortcoming has nothing to do with the library itself. But= the shortcoming will be inherent in anyone who uses that library. However= , if you take a different approach as I showed, you don't have that shortco= ming at all. > The BFM is in fact also not a part of BVUL, but I would definitely recomm= end=20 > it rather than using explicit assert statements. > A BFM is more readable, easier to maintain, etc. But that is not the point. My example also uses bus functional models (reg= _write and reg_read). The assertions are at the higher level. After you d= o that read, did you get the right result. > Yes - you do have to understand the functionality of any procedure you us= e,=20 > but without procedures and functions it is difficult to handle complex=20 > testbenches. In this case one has to read somewhere that parameter 1 is a= ddr,=20 > p2 is data and p3 is message, OR you could use explicit parameter mapping= .=20 If you use the Bitvis library that is...however if you use my approach ther= e is only one parameter to the write which is the register that you want to= write and there are no parameters to the read. It's also just as easy to = have a 'read and compare' procedure which takes only one parameter which is= the expected result. That would hide the assertion statement that you thi= nk is so objectionable. I didn't take my example that far simply because t= he Bitvis example didn't either. > In fact as long as you use unsigned, std_logic_vector and string respecti= vely=20 > for these parameters you can't go wrong (other than compile error). Sure you can, in fact that is exactly where you will go wrong. Here are so= me examples of errors you will have that are completely avoidable in the fi= rst place: - Reading or writing the wrong address (i.e. passing the value of the addre= ss of ITR rather than IRR) - Changing the value of some hard coded constant in one place and not consi= dering what else has to change as a result. What I showed would take that = completely into account. What Bitvis showed was 'well you as the user have= to find and fix those things' >=20 > There is a powerpoint presentation on how to use the library and the BFMs= .=20 > This can be browsed as a file, or you can even watch a 1 hour webinar.=20 > Everything should be more obvious then. Wow...did you not even notice that was where I got the example from in the = first place? > >=20 > > Of course the main issue is that Bitvis, since it is attempting to be= =20 > > generic, cannot be design specific, but in order to get good code clari= ty=20 > > you do want the executable code to be design specific. You do want to = have=20 > > executable that looks like 'Control_Reg.Fire_The_Gun :=3D "1"' to then = have a=20 > > response of 'Status_Reg.Off_To_The_Races :=3D "1"', not hard coded hex= =20 > > constants...that then have to change as the 'Off_To_The_Races' bit gets= =20 > > moved from bit 5 to bit 6. >=20 > BVUL does not stop you from using records. That is your choice.=20 >=20 What I described are the issues you will have if you choose to use somethin= g like the Bitvis approach in the first place. > > I have yet to have a time when 'verbosity control' was something I woul= d=20 > > want. The testbench will stop on an error and I have the complete log = file=20 > > that I need to debug the problem. What you don't mention at all that i= s=20 > > useful is simply to produce multiple log files. For example, logging= =20 > > transaction that occur on a particular interface to a CSV file so that = it=20 > > can be pulled up in Excel. Using those interface log files along with = the=20 > > main transcript log file is a powerful debug aid. >=20 > For those who do post processing in other tools that is a good approach. > There is nothing stopping you from using BVUL that way. > For those who want to look at the transcript or a log file directly -=20 > verbosity control could be very useful. I don't use any post processing tools. I use the output files directly and= I said, have not found verbosity control to be anything that I would want = since I don't know ahead of time what I won't end up needing to look at to = debug a problem...which is the whole reason for generating those output fil= es. >=20 > There will always be different opinions and taste, but please spend the t= ime=20 > to go through the PPT to see the purpose of some of the features. >=20 I did spend the time to go through PPT, and I've posted what I see as short= comings. They are not shortcomings of the Bitvis library itself. They are= shortcomings for anyone who chooses to use the library. However, the idea= s represented (i.e. BFMs, encapsulation, etc.) are good, it's just that try= ing to bundle that idea into a generic library like Bitvis is not such a go= od idea. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: John Speth Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 10:10:47 -0700 Organization: Aioe.org NNTP Server Lines: 6 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> NNTP-Posting-Host: QdUvumOrAsvsJh8lexF6xQ.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8344 On 6/30/2015 11:26 PM, mubinicyer@gmail.com wrote: > Physically Uncolonable Function Please describe what that means. JJS From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 14:24:26 -0400 Organization: Alacron, Inc. Lines: 12 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Jul 2015 18:23:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="15523"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18UMsgGwwHLq3/fLpD6+JEyLlJy4Hm1eqk=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:ayjrizklyGYtcrqR4e+RYLhi0NA= Xref: mx02.eternal-september.org comp.lang.vhdl:8345 John Speth wrote: > On 6/30/2015 11:26 PM, mubinicyer@gmail.com wrote: >> Physically Uncolonable Function > > Please describe what that means. > > JJS Probably means that it is impervious to colonoscopy ;-) -- Gabor From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Wed, 01 Jul 2015 14:35:45 -0400 Organization: Alacron, Inc. Lines: 35 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 1 Jul 2015 18:34:41 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="19587"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mT6DoHf+LuzX5/A23xMBppIyIhEzgenc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Cancel-Lock: sha1:HYJgfCn2RnSkyfixhpQusZ9afqg= Xref: mx02.eternal-september.org comp.lang.vhdl:8346 mubinicyer@gmail.com wrote: > Hi, > > I am designing a Physically Uncolonable Function using Ring Oscillator on FPGA (Spartan6). However, it does not generate uniqe ID for each chip, it generates exactly same value for different chips. Different ROs must generate different frequency due to die-imperfection. I will compare those frequencies and generate bits, which should be unique for each chip, since each chip has different physicall die-imperfection. > > First, I generate 16 ROs, each with 51 inverter gates, all of them are connected to two multiplexers, I connected the select inputs of multiplexers with 8-bit dip-switch. Outputs of multiplexers are connected to two 16-bit counters. Outputs of counters are connected to a comparator, If first counter reachs end value (111...11) (if it is faster than second counter) comparator gives '1', if second counter is faster than first, comparator gives a '0'. This generates only one bit. I replicated this design 16-times to generate 16-bit response. The first bits of this response (3 downto 0) are connected to 4-leds. I tested the design with 3 different chips, they give exactly same respnose, which is not desired. > How can I make it in order to have different responses? > > Thanks. > I think you are working on a faulty premise. While there will be a frequency difference for ring oscillators from device to device, the relative frequency of two such oscillators within any device will probably be similar. A lot of this has to do with routing delays, which cannot be easily matched from one section of the device to another. So even the static timing analysis will probably tell you right off the bat that oscillator "A" has more prop delay in the ring than oscillator "B" and so on. It's not just the LUT count. If you are trying to determine a unique device by measuring some quality of each of 16 distinct regions in the device, you need a more reliable way to make this measurement. If you want to use ring oscillators, I would start by using a fairly long counter to determine the relative speed, and instead of just seeing which one reaches terminal count first, latch the actual value of the other counter when that terminal count is reached. Then look at these relative numbers on a sampling of die to see if there is enough information to find a useful threshold to tell the devices apart. Even then you'd need to look at these values over a range of temperature and voltage conditions to make sure you can "fingerprint" the device reliably using just the process differences. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.roellig-ltd.de!open-news-network.org!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx27.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: hands on experience on SystemC References: In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150701-2, 01/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1435780301 86.17.210.161 (Wed, 01 Jul 2015 19:51:41 UTC) NNTP-Posting-Date: Wed, 01 Jul 2015 19:51:41 UTC Organization: virginmedia.com Date: Wed, 01 Jul 2015 20:51:39 +0100 X-Received-Body-CRC: 4093968850 X-Received-Bytes: 2796 Xref: mx02.eternal-september.org comp.lang.vhdl:8347 On 17/06/2015 01:51, michael6866 wrote: > On Tuesday, June 16, 2015 at 5:50:37 PM UTC-4, alb wrote: ..snip > >> >>> (2) It has faster simulation speed. [] >> >> Beaware of simulation speed comparisons. If you minimize the amount of >> signals and maximize the number of variables, you should be getting a >> very nice improve (both in maintainability and interoperability with >> other models). > Agree. However even with the same magnitude of signals / variables, SystemC is still much faster. As I mentioned this is because the way the RTL simulation engine works is different than the SystemC kernel. It is not, from what I understand the SystemC kernel is very close to the one used in VHDL. For this reason it is very easy for a VHDL engineer to pick up SystemC (leaving the C++ horrors aside) as you get the same signal/variables/process goodness. I am so happy the OSCI developers didn't pick the blocking and unblocking spaghetti model ;-) I am also pretty sure you are incorrect regarding the speed of models with the same number of events. Most vendors (re)use the OSCI reference simulator and although they might have tweaked it a bit it is still miles away from a modern VHDL kernel you find in say Modelsim/Riviera/NCSIM/etc. I have done a simple test were I converted a few simple RTL VHDL models into SystemC (same number of events, same architecture) and compared the speed. The VHDL models were roughly 2-3x faster than SystemC both executed on Modelsim. Regards, Hans www-ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!feed.xsnews.nl!fbe001.ams.xsnews.nl!news.roellig-ltd.de!open-news-network.org!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 06:09:45 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 12:09:47 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 19 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-5WkBOFlhtqDYOxK07NG6YS/QkaYi+ujjmpMlQo1sEpnIyv56Naf+dftxwaQiN2GpEifRgkEea2uqFF9!RlO5KjfYZokAGorUbmyz1Az3b4ZFBga2Xl9/eq16z6++F7G+HHZ8U+QjYaIddNPiznwNNQNJjDKc!6T6wiY5Zw8LmGz1GhHNdYdkwCqs= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1747 Xref: mx02.eternal-september.org comp.lang.vhdl:8348 >wrote in message=20 >news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >Hi, >I am designing a Physically Uncolonable Function using Ring = Oscillator... Why not just read the random contents of some internal ram as part of = the=20 boot sequence. IME it will contain a random but device specific contents = not=20 dependant on temperature, just manufacturing differences from die to = die. Andy=20 From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 10:51:12 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 14:49:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16777"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/aAs5Ttgqe+1ZOZswUUAxs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:O2WiOWa2zb8RsuI9VVO8BaCnxj4= Xref: mx02.eternal-september.org comp.lang.vhdl:8349 On 7/2/2015 7:09 AM, Andy Bennett wrote: > > >> wrote in message >> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... > >> Hi, > >> I am designing a Physically Uncolonable Function using Ring Oscillator... > > Why not just read the random contents of some internal ram as part of > the boot sequence. IME it will contain a random but device specific > contents not dependant on temperature, just manufacturing differences > from die to die. Why would you expect the power up contents of RAM to depend any more on manufacturing differences than the ring oscillator frequency? -- Rick From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:01:24 -0400 Organization: Alacron, Inc. Lines: 35 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:00:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="20579"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fDS74+dpYPMUHnHDoUtykRLUIItPaUEs=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:1KoI1mbj1faPg9UvqBBKPKvuj9g= Xref: mx02.eternal-september.org comp.lang.vhdl:8350 rickman wrote: > On 7/2/2015 7:09 AM, Andy Bennett wrote: >> >> >>> wrote in message >>> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >> >>> Hi, >> >>> I am designing a Physically Uncolonable Function using Ring >>> Oscillator... >> >> Why not just read the random contents of some internal ram as part of >> the boot sequence. IME it will contain a random but device specific >> contents not dependant on temperature, just manufacturing differences >> from die to die. > > Why would you expect the power up contents of RAM to depend any more on > manufacturing differences than the ring oscillator frequency? > A) In xilinx parts, that is very hard to do because the bitstream will load the BRAM contents along with every other storage element in the part. You would need to have special tools and some intimate part knowledge to selectively load the part at configuration. B) Whether or not it depends more or less on manufactuing differences than a ring oscillator, his original method was flawed in that it presumed that the manufacturing differences where the only thing affecting the relative oscillator frequencies. In fact, place and route differences would typically swamp any effect of manufacturing process unless the design were carefully hand routed and replicated. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:08:22 -0400 Organization: A noiseless patient Spider Lines: 50 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:06:57 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="21469"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181pcZdpRHdqTrF2/eL5DhL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:UbwQ1+Brq2L5goKqDRhWC8fAi3Q= Xref: mx02.eternal-september.org comp.lang.vhdl:8351 On 7/2/2015 11:01 AM, GaborSzakacs wrote: > rickman wrote: >> On 7/2/2015 7:09 AM, Andy Bennett wrote: >>> >>> >>>> wrote in message >>>> news:8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com... >>> >>>> Hi, >>> >>>> I am designing a Physically Uncolonable Function using Ring >>>> Oscillator... >>> >>> Why not just read the random contents of some internal ram as part of >>> the boot sequence. IME it will contain a random but device specific >>> contents not dependant on temperature, just manufacturing differences >>> from die to die. >> >> Why would you expect the power up contents of RAM to depend any more >> on manufacturing differences than the ring oscillator frequency? >> > > A) In xilinx parts, that is very hard to do because the bitstream > will load the BRAM contents along with every other storage element > in the part. You would need to have special tools and some intimate > part knowledge to selectively load the part at configuration. I am not sure that is correct. I don't have all the details of every FPGA family memorized, but I do recall reading that someone, somewhere allows block RAM contents to be preserved through configurations as an option in the bit stream. I am pretty sure that was a Xilinx part I read that about. So it is not so much "intimate knowledge" as it is reading the fine manual. > B) Whether or not it depends more or less on manufactuing differences > than a ring oscillator, his original method was flawed in that it > presumed that the manufacturing differences where the only thing > affecting the relative oscillator frequencies. In fact, place and > route differences would typically swamp any effect of manufacturing > process unless the design were carefully hand routed and replicated. I am not debating that. I am asking why anyone would expect the power up contents of RAM to be useful in distinguishing individual parts. The ring oscillator frequency at least has a chance of working if the design method is adapted to deal with the designed in differences. -- Rick From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 10:22:42 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 16:22:45 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: Lines: 27 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ttNGnmRVTVk8E2Ia2KE033nntVL6RW2iqcw9V3V5+EGZ65AMpTSnR5z1dUYfuw1EFG8ed24WgzGAmJd!zOZh37UvOZNvpm2M1MUFYMWIdGkmfavEoizAa3OHwo4YZK0L6SVbWoQ7Ybem+UM8a5C9JvRzHt3S!/qiqI4+tWQ7oackqhXt84nheN6Y= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2297 Xref: mx02.eternal-september.org comp.lang.vhdl:8352 On 7/2/2015 11:01 AM, GaborSzakacs wrote: > rickman wrote: >I am not debating that. I am asking why anyone would expect the power = up=20 >contents of RAM to be useful in distinguishing individual parts. The = ring=20 >oscillator frequency at least has a chance of working if the design = method=20 >is adapted to deal with the designed in differences. I don't know about Xilinx parts, but certainly Altera Cyclone and = Stratix=20 parts have the option of configuring RAM at power up with a don't care=20 option, and at the same time you configure the RAM so write is = permanently=20 held low you can treat it as unconfigured ROM - it will not be loaded = from=20 flash at power up and will contain random values due to manufacturing=20 tolerances. As I said before, IME the values are consistant from power = up to=20 power up. Andy. From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 11:28:54 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 15:27:29 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="26222"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX196f7UCl5nzWXdYne0qf1V6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:vm/4bprHW+lNJf7hMndG9hqyVvg= Xref: mx02.eternal-september.org comp.lang.vhdl:8353 On 7/2/2015 11:22 AM, Andy Bennett wrote: > > On 7/2/2015 11:01 AM, GaborSzakacs wrote: >> rickman wrote: > >> I am not debating that. I am asking why anyone would expect the power >> up contents of RAM to be useful in distinguishing individual parts. >> The ring oscillator frequency at least has a chance of working if the >> design method is adapted to deal with the designed in differences. > > I don't know about Xilinx parts, but certainly Altera Cyclone and > Stratix parts have the option of configuring RAM at power up with a > don't care option, and at the same time you configure the RAM so write > is permanently held low you can treat it as unconfigured ROM - it will > not be loaded from flash at power up and will contain random values due > to manufacturing tolerances. As I said before, IME the values are > consistant from power up to power up. But have you tested that the contents depend on "manufacturing tolerances"? I can see where the contents of the RAM would also be more dependent on design differences than manufacturing tolerances. -- Rick From newsfish@newsfish Tue Dec 29 16:43:52 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Thu, 02 Jul 2015 11:34:17 -0500 From: "Andy Bennett" Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> In-Reply-To: Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 2 Jul 2015 17:34:20 +0100 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="Windows-1252"; reply-type=response Content-Transfer-Encoding: quoted-printable X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 16.4.3528.331 X-MimeOLE: Produced By Microsoft MimeOLE V16.4.3528.331 Message-ID: <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-hXGG1vsTMKr6vrX3l7UmkwNGjJYVfbs0EJlFi5s0mBb/5BCo8IfpsZTqwE7A3z9FASkHJCx7OCYUEGJ!zeVbGDFhBmAtvSUUQ/imE/eFeTKfjtTbmnXTKWsrjTheGgtObRYXwkUj57FjqOJzRIadZWkzjMYS!ZdEQhRl66qAsyzoBGXHWvxE9nYg= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2343 Xref: mx02.eternal-september.org comp.lang.vhdl:8354 "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... On 7/2/2015 11:22 AM, Andy Bennett wrote: > > On 7/2/2015 11:01 AM, GaborSzakacs wrote: >> rickman wrote: > >But have you tested that the contents depend on "manufacturing = tolerances"?=20 >I can see where the contents of the RAM would also be more dependent on = >design differences than manufacturing tolerances. Not sure what you mean by design differences - the RAM blocks are = defined=20 blocks on the silicon, not synthesised from the logic array. I have only tested the same FPGA design (mine) on the same FPGA part = type=20 across a number of different parts and got random RAM contents between=20 parts, but the same contents for each part over multiple power ups and=20 temperatures. I have not investigated further. Andy=20 From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 12:51:05 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 16:49:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14231"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX180G953fxe/ttxCZaz2msFv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Cancel-Lock: sha1:T5m8FeniWtnNEu9ZDgMAob+49Io= Xref: mx02.eternal-september.org comp.lang.vhdl:8355 On 7/2/2015 12:34 PM, Andy Bennett wrote: > > > "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... > > On 7/2/2015 11:22 AM, Andy Bennett wrote: >> >> On 7/2/2015 11:01 AM, GaborSzakacs wrote: >>> rickman wrote: >> > >> But have you tested that the contents depend on "manufacturing >> tolerances"? I can see where the contents of the RAM would also be >> more dependent on design differences than manufacturing tolerances. > > Not sure what you mean by design differences - the RAM blocks are > defined blocks on the silicon, not synthesised from the logic array. > I have only tested the same FPGA design (mine) on the same FPGA part > type across a number of different parts and got random RAM contents > between parts, but the same contents for each part over multiple power > ups and temperatures. > I have not investigated further. If what you have seen is accurate across the various product lines and production batches, then a checksum or CRC on a block RAM should serve as a useful fingerprint. I would be very concerned that this finger print would be 100% repeatable. If it depends on manufacturing tolerances I would expect there to be a finite possibility of one or more bits being on the hairy edge and some small amount of noise determining the resting state rather than the device specifics. I guess it might be better to just record the entire block content and allowing for some small number of bits changing from read to read. -- Rick From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Thu, 02 Jul 2015 16:25:53 -0400 Organization: Alacron, Inc. Lines: 43 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 2 Jul 2015 20:25:04 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="1115"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18MZC/1Gzp531UhrRPdpsvuxyrTiO94zaQ=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:Izzy2rWamv7rLHgoVw0EJWKVjDI= Xref: mx02.eternal-september.org comp.lang.vhdl:8356 rickman wrote: > On 7/2/2015 12:34 PM, Andy Bennett wrote: >> >> >> "rickman" wrote in message news:mn3l91$pje$1@dont-email.me... >> >> On 7/2/2015 11:22 AM, Andy Bennett wrote: >>> >>> On 7/2/2015 11:01 AM, GaborSzakacs wrote: >>>> rickman wrote: >>> >> >>> But have you tested that the contents depend on "manufacturing >>> tolerances"? I can see where the contents of the RAM would also be >>> more dependent on design differences than manufacturing tolerances. >> >> Not sure what you mean by design differences - the RAM blocks are >> defined blocks on the silicon, not synthesised from the logic array. >> I have only tested the same FPGA design (mine) on the same FPGA part >> type across a number of different parts and got random RAM contents >> between parts, but the same contents for each part over multiple power >> ups and temperatures. >> I have not investigated further. > > If what you have seen is accurate across the various product lines and > production batches, then a checksum or CRC on a block RAM should serve > as a useful fingerprint. I would be very concerned that this finger > print would be 100% repeatable. If it depends on manufacturing > tolerances I would expect there to be a finite possibility of one or > more bits being on the hairy edge and some small amount of noise > determining the resting state rather than the device specifics. > > I guess it might be better to just record the entire block content and > allowing for some small number of bits changing from read to read. > On the other hand, I have to wonder why you need this functionality on an older Spartan 3 part. All the newer Xilinx series including Spartan 3A DSP have a serial number ("Device DNA") built in to provide a reliable mechanism to lock a design to a particular part. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 04 Jul 2015 12:47:07 GMT Lines: 16 Message-ID: <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 374328bc.news.astraweb.com X-Trace: DXC=Coc6YjV:h>iJRZZkg^aP1jL?0kYOcDh@j]WEZ@Q1WnGeE3=kG9hhb7bHI6bY5_;LhiEBe]G`V^KXg\X\Za@iJeXm9O\=`f7CS1d Xref: mx02.eternal-september.org comp.lang.vhdl:8357 On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: > On the other hand, I have to wonder why you need this functionality on > an older Spartan 3 part. All the newer Xilinx series including Spartan > 3A DSP have a serial number ("Device DNA") built in to provide a > reliable mechanism to lock a design to a particular part. >From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique - up to 32 devices can have the same serial number (Reference: UG470). Presumably this came from a desire to improve yield and reduce costs, rather than from a desire to make it completely useless to designers. I believe the older devices (up to and including V6) are still safe. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news.astraweb.com!border6.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Newsgroups: comp.lang.vhdl References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 04 Jul 2015 17:31:23 GMT Lines: 48 Message-ID: <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: cfb3845c.news.astraweb.com X-Trace: DXC=NUm5^ICWTod]`e1HJ8=:?`L?0kYOcDh@jO13VQ=noH4ih:BbU8OZ3AmHI6bY5_;LhiEBe]G`V^KXg\X\Za@iJeXm=fLB\mo4W1b Xref: mx02.eternal-september.org comp.lang.vhdl:8358 On Sat, 04 Jul 2015 12:47:07 +0000, Allan Herriman wrote: > On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: > >> On the other hand, I have to wonder why you need this functionality on >> an older Spartan 3 part. All the newer Xilinx series including Spartan >> 3A DSP have a serial number ("Device DNA") built in to provide a >> reliable mechanism to lock a design to a particular part. > > From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique > - > up to 32 devices can have the same serial number (Reference: UG470). > Presumably this came from a desire to improve yield and reduce costs, > rather than from a desire to make it completely useless to designers. > > I believe the older devices (up to and including V6) are still safe. Correction (after I re-read some documentation): The Spartan 3A devices have a 57 bit number, a 55 bits slice of which is guaranteed to be unique. (Reference: UG332) The Xilinx V6 devices have a 64 bit number that is *not* guaranteed to be unique, and can be read out over JTAG. A 57 bit slice of the 64 bit number (also not guaranteed to be unique) can be read out inside the FPGA. The remaining 7 bits are described as "reserved". (Reference: UG360) The Xilinx V7 devices have a 64 bit number that is unique, and can be read out over JTAG. A 57 bit slice of the 64 bit number can be read out inside the FPGA. That 57 bit slice is *not* guaranteed to be unique. (Reference: UG470) Xilinx Ultrascale (and presumably Ultrascale Plus) devices have a longer (96 bit) sequence that is unique, and all 96 bits can be read out inside the FPGA. (Reference: UG570) BTW, they use efuse technology, and are programmed at the factory. The Spartan 3A ones are guaranteed for 10 years or 30 million read cycles. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: First steps using VUnit Date: Sun, 05 Jul 2015 01:23:20 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 4 Jul 2015 23:22:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3a996b8dd3a472e8b1724458c31fcf8d"; logging-data="3211"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18l+tfNcaubfvkXoG/nu70P" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 Cancel-Lock: sha1:e0k3mre9fwvK9iTiye6F29/X+Yc= Xref: mx02.eternal-september.org comp.lang.vhdl:8359 Hello, in the last few weeks I read much about VUnit and so I wanted to make some experiences. I cloned VUnit form Github and tried to run the example "tb_example". But when running the run.py script, using "python run.py -v lib.tb_example*", I get the following error message: Traceback (most recent call last): File "run.py", line 2, in from vunit import VUnit ImportError: No module named vunit I tried to add the vunit path to PYTHONPATH enviroment, but this also gives me the same error message. I'm using Python 2.7.5 but I'm an absolutly noob (this is the first time, I ever have called python in my console ;)). So can someone give me a hint what I'm doing wrong? I read the user_guide.md on Github page a several times, but I can't find the missing information I need to get the example running. Thanks a lot, Tobias From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.52.114.37 with SMTP id jd5mr1466269vdb.2.1436080885865; Sun, 05 Jul 2015 00:21:25 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr564432qge.19.1436080885804; Sun, 05 Jul 2015 00:21:25 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!m107no171060qgd.1!news-out.google.com!4ni53551qgh.1!nntp.google.com!w90no504505qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Jul 2015 00:21:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Sun, 05 Jul 2015 07:21:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 6 Xref: mx02.eternal-september.org comp.lang.vhdl:8360 Hi Tobias, What is your PYTHONPATH pointing to? It should point to the top directory in which you have the vunit, vhdl, examples directories and not to the vunit directory one level down. Regards, Lars From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Sun, 05 Jul 2015 11:03:35 +0200 Organization: A noiseless patient Spider Lines: 19 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 5 Jul 2015 09:02:11 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="55b24bab51ed7fd1d5eadb079c167ef4"; logging-data="30670"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/3Cqz08QHa5nyyG9vsD9H0" User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Cancel-Lock: sha1:onqx3mgL5S0Spkx1ckYyKFyd5uo= Xref: mx02.eternal-september.org comp.lang.vhdl:8361 Am 05.07.2015 um 09:21 schrieb Lars Asplund: > Hi Tobias, > > What is your PYTHONPATH pointing to? It should point to the top directory in which you have the vunit, vhdl, examples directories and not to the vunit directory one level down. > > Regards, > > Lars > Hey Lars, thanks a lot, it is working now. I tried everything except your solution. Maybe you can add this information to the user_guide.md, then it's clear for Python noobs how to get VUnit starting. Best regards, Tobias From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.52.114.37 with SMTP id jd5mr2598789vdb.2.1436099642368; Sun, 05 Jul 2015 05:34:02 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr402629qgf.7.1436099642308; Sun, 05 Jul 2015 05:34:02 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m107no255801qgd.1!news-out.google.com!w15ni22819qge.0!nntp.google.com!m107no255796qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 5 Jul 2015 05:34:02 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.64.66.196; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 213.64.66.196 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Sun, 05 Jul 2015 12:34:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1686 X-Received-Body-CRC: 2213371889 Xref: mx02.eternal-september.org comp.lang.vhdl:8362 Hi Tobias, I made an addition to the user guide to make this clear. Thanks for pointin= g that out. Don't hesitate to get back with more questions if you have trou= ble with Python. Most VHDL developers have no Python experience so it's imp= ortant that our documentation covers the basics to get started. Once you're= up and running you really don't need that much Python skills. Making basic= run scripts is a copy/paste exercise from the given examples. Best Regards, Lars From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Mon, 6 Jul 2015 10:28:06 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 08:25:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="7143"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++LyALhAeUIyaMPdlXawmD" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: Cancel-Lock: sha1:UGlxffPo8fgftiXHFkv6huON0Ss= Xref: mx02.eternal-september.org comp.lang.vhdl:8363 Am 05.07.2015 um 14:34 schrieb Lars Asplund: > Hi Tobias, > > I made an addition to the user guide to make this clear. Thanks for pointing that out. Don't hesitate to get back with more questions if you have trouble with Python. Most VHDL developers have no Python experience so it's important that our documentation covers the basics to get started. Once you're up and running you really don't need that much Python skills. Making basic run scripts is a copy/paste exercise from the given examples. > > Best Regards, > Lars > Hi Lars, thanks a lot for updating the user guide. I think it contains every information which is needed to get a first example running. Now I'm at the point where I have a Jenkins Server which run the VUnit regression tests on every commit. After the run I can see the JUnit reports, so I think the beginning is done. The next step will be to run a multiple regression test of a huge design. I also saw on the Github page, that there is a discussion how VUnit can be integrated better into Sigasi. When this also works smoothly, I will setup a CI server in our firm. Best regards, Tobias From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.182.186.67 with SMTP id fi3mr69131721obc.49.1436188721218; Mon, 06 Jul 2015 06:18:41 -0700 (PDT) X-Received: by 10.140.35.170 with SMTP id n39mr167554qgn.0.1436188721179; Mon, 06 Jul 2015 06:18:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!wf20no645079igc.0!news-out.google.com!4ni66258qgh.1!nntp.google.com!w90no947923qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 6 Jul 2015 06:18:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.138.132.22; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 79.138.132.22 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Mon, 06 Jul 2015 13:18:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8364 Hi Tobias, Seems like you have very good progress! You say that you have a huge design to test. Does this means that test time= is an issue for you? You might have seen the -p option that allow you to r= un test cases in parallel on several cores. There are also discussions with= other VUnit users to do load balancing between slaves using Jenkins plugin= s. Btw, do you have ideas for what you want from a Sigasi integration? If so, = please join the discussion here https://github.com/LarsAsplund/vunit/issues= /18. Best Regards,=20 Lars From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: How to generate unique ID for each FPGA using Ring Oscillator PUF Date: Mon, 06 Jul 2015 09:27:06 -0400 Organization: Alacron, Inc. Lines: 56 Message-ID: References: <8fd7b0b6-582b-44c5-84be-7ce09e7b59c3@googlegroups.com> <5L-dnWArHuaU9QjInZ2dnUU78WmdnZ2d@brightview.co.uk> <5597d5ca$0$1586$c3e8da3$5496439d@news.astraweb.com> <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 13:27:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="191b44ae8df4ebffb47a6af452bf0f24"; logging-data="5668"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/YFL0AlS/UmaFZBtmp6qYofL3woHewRbc=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <5598186b$0$1674$c3e8da3$5496439d@news.astraweb.com> Cancel-Lock: sha1:a42CRP4F5LACbIjnp7aRy5FExpM= Xref: mx02.eternal-september.org comp.lang.vhdl:8365 Allan Herriman wrote: > On Sat, 04 Jul 2015 12:47:07 +0000, Allan Herriman wrote: > >> On Thu, 02 Jul 2015 16:25:53 -0400, GaborSzakacs wrote: >> >>> On the other hand, I have to wonder why you need this functionality on >>> an older Spartan 3 part. All the newer Xilinx series including Spartan >>> 3A DSP have a serial number ("Device DNA") built in to provide a >>> reliable mechanism to lock a design to a particular part. >> From Virtex 7 onwards, Xilinx Device DNA is not guaranteed to be unique >> - >> up to 32 devices can have the same serial number (Reference: UG470). >> Presumably this came from a desire to improve yield and reduce costs, >> rather than from a desire to make it completely useless to designers. >> >> I believe the older devices (up to and including V6) are still safe. > > > Correction (after I re-read some documentation): > > > The Spartan 3A devices have a 57 bit number, a 55 bits slice of which is > guaranteed to be unique. (Reference: UG332) > > > The Xilinx V6 devices have a 64 bit number that is *not* guaranteed to be > unique, and can be read out over JTAG. A 57 bit slice of the 64 bit > number (also not guaranteed to be unique) can be read out inside the > FPGA. The remaining 7 bits are described as "reserved". (Reference: > UG360) > > > The Xilinx V7 devices have a 64 bit number that is unique, and can be > read out over JTAG. A 57 bit slice of the 64 bit number can be read out > inside the FPGA. That 57 bit slice is *not* guaranteed to be unique. > (Reference: UG470) > > > Xilinx Ultrascale (and presumably Ultrascale Plus) devices have a longer > (96 bit) sequence that is unique, and all 96 bits can be read out inside > the FPGA. (Reference: UG570) > > > BTW, they use efuse technology, and are programmed at the factory. The > Spartan 3A ones are guaranteed for 10 years or 30 million read cycles. > > Regards, > Allan Spartan 6 and I believe V6 also have a limit on read cycles. This was fixed for 7-series parts. It's actually quite easy to run into the read cycle limit if you are not careful and make code that reads it continuously rather than just once after configuration. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: First steps using VUnit Date: Mon, 6 Jul 2015 17:00:07 +0200 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 6 Jul 2015 14:57:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="29990"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18u5nYv8qs/So6No1Q1i2yW" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> Cancel-Lock: sha1:5UBkuLUObdYDD94PsOhUc3NdLhs= Xref: mx02.eternal-september.org comp.lang.vhdl:8366 Hi Lars, > Seems like you have very good progress! > Yes, I'm a bit suprised that everything went so fast ;) > You say that you have a huge design to test. Does this means that test time is an issue for you? You might have seen the -p option that allow you to run test cases in parallel on several cores. There are also discussions with other VUnit users to do load balancing between slaves using Jenkins plugins. Yes test time is absolutly an issue, but this depends on my IPs. These are mainly for video algorithm and thereore I have to simulate a complete frame, which can't parallelize effectivly. But I can try to run the same IP using different regression setups in parallel. I have to find out if this is possible with my Modelsim license. If I remember correctly there can only run one Modelsim instance at the same time. > Btw, do you have ideas for what you want from a Sigasi integration? If so, please join the discussion here https://github.com/LarsAsplund/vunit/issues/18. I think what Phillipe mentioned is the right way. For me as Sigasi user, this means I would have to drag the VUnit folder into eclipse, right-click on the needed VHDL source files (i.e. vunit/vhdl/200x) and set them as library vunit_lib. Two clicks and VUnit is ready to use with Sigasi. Now I have to choose the correct VUnit files for "linking" in the right library, which is pretty annoying. Maybe when I'm a bit more in this topic I can give you some suggestions for improvements. The guys from Sigasi seem to me also very interested in improving their software. The fusion of both can lead to an easy to use regression suite without limitations in complexity. Best regards, Tobias From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.66.246.193 with SMTP id xy1mr4036643pac.44.1436258345180; Tue, 07 Jul 2015 01:39:05 -0700 (PDT) X-Received: by 10.140.47.68 with SMTP id l62mr35941qga.42.1436258345135; Tue, 07 Jul 2015 01:39:05 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!wf20no1210799igc.0!news-out.google.com!4ni73753qgh.1!nntp.google.com!w90no1255697qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Jul 2015 01:39:04 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.138.134.188; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 79.138.134.188 References: <81ebe9d2-dca1-4afd-845a-109f3f32dcdb@googlegroups.com> <405ea1dd-ec4c-4d40-bc71-1edece2d4048@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: First steps using VUnit From: Lars Asplund Injection-Date: Tue, 07 Jul 2015 08:39:05 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2876 X-Received-Body-CRC: 1203559508 Xref: mx02.eternal-september.org comp.lang.vhdl:8367 Den m=E5ndag 6 juli 2015 kl. 16:59:17 UTC+2 skrev Tobias Baumann: > Hi Lars, >=20 > > Seems like you have very good progress! > > >=20 > Yes, I'm a bit suprised that everything went so fast ;) >=20 > > You say that you have a huge design to test. Does this means that test = time is an issue for you? You might have seen the -p option that allow you = to run test cases in parallel on several cores. There are also discussions = with other VUnit users to do load balancing between slaves using Jenkins pl= ugins. >=20 > Yes test time is absolutly an issue, but this depends on my IPs. These=20 > are mainly for video algorithm and thereore I have to simulate a=20 > complete frame, which can't parallelize effectivly. But I can try to run= =20 > the same IP using different regression setups in parallel. I have to=20 > find out if this is possible with my Modelsim license. If I remember=20 > correctly there can only run one Modelsim instance at the same=20 Running in parallel with different setups is a good idea. Once you have tha= t you can ask yourself if all these tests need to run with the full frame s= ize. You can also select to run a subset of the tests on every commit and t= hen let the rest run over night. As you might have seen we also support GHDL to avoid that licence problem. = We've had good support from the GHDL to make this happen. The updated versi= on is yet to be released as a binary so you need to build from source. Best Regards,=20 Lars From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.66.190.41 with SMTP id gn9mr5392222pac.2.1436280606863; Tue, 07 Jul 2015 07:50:06 -0700 (PDT) X-Received: by 10.140.102.66 with SMTP id v60mr60351qge.19.1436280606776; Tue, 07 Jul 2015 07:50:06 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!wf20no1472880igc.0!news-out.google.com!4ni76218qgh.1!nntp.google.com!m107no1053412qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 7 Jul 2015 07:50:06 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.150.32.12; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 83.150.32.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Subject: Register map auto-generation From: Leonardo Capossio Injection-Date: Tue, 07 Jul 2015 14:50:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8368 Hello, I wonder if anyone knows an open-source processor or a generic progr= am that will generate a register map for a given embedded processor (Z80-co= py or OpenRisc or similar) and architecture in both VHDL and C (header file= s or library files with addresses) ? From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.61.MISMATCH!peer01.fr7!news.highwinds-media.com!post01.fr7!fx11.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150707-0, 07/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 18 Message-ID: NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1436285817 86.17.210.161 (Tue, 07 Jul 2015 16:16:57 UTC) NNTP-Posting-Date: Tue, 07 Jul 2015 16:16:57 UTC Organization: virginmedia.com Date: Tue, 07 Jul 2015 17:16:55 +0100 X-Received-Body-CRC: 2110237940 X-Received-Bytes: 1722 Xref: mx02.eternal-september.org comp.lang.vhdl:8369 On 07/07/2015 15:50, Leonardo Capossio wrote: > Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses) ? > Not 100% sure what you are after but if you want to generate RTL and associated c files from some register specifications then have a look at IDesignSpec, you can download a free version from cnet, http://download.cnet.com/IDesignSpec-for-Word-2007-2010/3000-20418_4-75728342.html There might be later versions available on the Agnisys website, Good luck, Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.13.254.131 with SMTP id o125mr12899186ywf.56.1436366968658; Wed, 08 Jul 2015 07:49:28 -0700 (PDT) X-Received: by 10.140.38.180 with SMTP id t49mr156816qgt.9.1436366968601; Wed, 08 Jul 2015 07:49:28 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!w90no1729707qge.0!news-out.google.com!4ni79758qgh.1!nntp.google.com!w90no1729702qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 8 Jul 2015 07:49:28 -0700 (PDT) In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Chris Higgs Injection-Date: Wed, 08 Jul 2015 14:49:28 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 8 Xref: mx02.eternal-september.org comp.lang.vhdl:8370 On Tuesday, 7 July 2015 15:50:09 UTC+1, Leonardo Capossio wrote: > Hello, I wonder if anyone knows an open-source processor or a generic pro= gram that will generate a register map for a given embedded processor (Z80-= copy or OpenRisc or similar) and architecture in both VHDL and C (header fi= les or library files with addresses)? Do you already have the registers defined in machine readable format? You could take a look at AirHDL from Guy Eschemann: http://airhdl.com/ From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.ag!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.61.MISMATCH!peer01.fr7!news.highwinds-media.com!post01.fr7!fx16.am4.POSTED!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Antivirus: avast! (VPS 150708-0, 08/07/2015), Outbound message X-Antivirus-Status: Clean Lines: 27 Message-ID: <3rcnx.21161$wM2.3993@fx16.am4> NNTP-Posting-Host: 86.17.210.161 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1436373823 86.17.210.161 (Wed, 08 Jul 2015 16:43:43 UTC) NNTP-Posting-Date: Wed, 08 Jul 2015 16:43:43 UTC Organization: virginmedia.com Date: Wed, 08 Jul 2015 17:43:41 +0100 X-Received-Body-CRC: 3765655758 X-Received-Bytes: 2295 Xref: mx02.eternal-september.org comp.lang.vhdl:8371 On 08/07/2015 15:49, Chris Higgs wrote: > On Tuesday, 7 July 2015 15:50:09 UTC+1, Leonardo Capossio wrote: >> Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses)? > > Do you already have the registers defined in machine readable format? > > You could take a look at AirHDL from Guy Eschemann: http://airhdl.com/ > Hi Chris, Looks like an interesting tool although the usage terms seems a bit harsh: In these terms and conditions, “your user content” means material (including without limitation text, images, audio material, video material and audio-visual material) that you submit to this website, for whatever purpose. You grant to airhdl.com a worldwide, irrevocable, non-exclusive, royalty-free license to use, reproduce, adapt, publish, translate and distribute your user content in any existing or future media. You also grant to airhdl.com the right to sub-license these rights, and the right to bring an action for infringement of these rights. Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.70.35.34 with SMTP id e2mr18738958pdj.6.1436438206917; Thu, 09 Jul 2015 03:36:46 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr227065qge.3.1436438206659; Thu, 09 Jul 2015 03:36:46 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!i4no328690ige.0!news-out.google.com!w15ni32278qge.0!nntp.google.com!m107no1577610qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jul 2015 03:36:46 -0700 (PDT) In-Reply-To: <3rcnx.21161$wM2.3993@fx16.am4> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> <3rcnx.21161$wM2.3993@fx16.am4> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Chris Higgs Injection-Date: Thu, 09 Jul 2015 10:36:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 12 Xref: mx02.eternal-september.org comp.lang.vhdl:8372 Greetings Hans! On Wednesday, 8 July 2015 17:43:46 UTC+1, HT-Lab wrote: > > Looks like an interesting tool although the usage terms seems a bit harsh I don't use AirHDL in anger as we have internal tools for that purpose, however I am enjoying the gradual acceptance of hosted tools. I agree that the privacy policy is off-putting. It appears that they're generated from some standard template[1] which may not be ideally suited to this use case. I've CC'd Guy, perhaps he can comment. [1] http://www.privacypolicyonline.com From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Carry Save Adder (CSA) Verilog code Date: Thu, 9 Jul 2015 17:47:46 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 10 Message-ID: References: <1163419252.983205.36600@b28g2000cwb.googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8373 Irhamish wrote: > need 3 to 2 compresser..!! with figures Carry save adders are just ordinary full adders. It is how you wire them up that matters. I would put a full adder in a module, oops, entity, and then reference that the appropriate number of times. -- glen From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: WORK Date: Thu, 9 Jul 2015 17:52:53 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 14 Message-ID: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8374 I don't understand the use of WORK in VHDL. I have a large module, well entity in VHDL, that references many other entities without any problem. But then I wanted one of those to reference an entity, and got errors from Xilinx ISE. The fix seems to be to put WORK. in front of the entity name. Am I supposed to put WORK. in front of all the entity refernces? I am more used to verilog, but structural VHDL isn't all that different from structural verilog, if you change a few words. -- glen From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 9 Jul 2015 17:58:52 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8375 fl wrote: > On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: (snip) >> I have always found block diagrams to be my friend and to help me >> understand all the relationships between modules. An FFT is actually >> easy to implement once you understand how they work. They often need >> pipelining to make them run fast. I have never found pipelining of a >> linear flow to be difficult. Do you have feedback paths that make your >> design more complex? What else are you using other than FFTs? > Thanks, Rick. I can imagine it could be more difficult when there is > feedback for a high speed module. FFT has a simple, regular structure. > For me, I am still in the phase of FFT. I know FFT and its coding in C, > even in assembly code. I do not have time to finish a VHDL FFT yet. > The main difficulties are about the memory addressing, twiddle coef > selection etc. > Yes, I need to be patient to work on these interconnect between memory, > twiddle and multipliers. My favorite use for FPGAs is systolic array processors. I think you can make a systolic array for FFT, but haven't actually tried to do it. Once you figure it out, they are easy to write and debug. -- glen From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.182.24.70 with SMTP id s6mr20884563obf.42.1436465067885; Thu, 09 Jul 2015 11:04:27 -0700 (PDT) X-Received: by 10.140.92.247 with SMTP id b110mr264311qge.6.1436465067744; Thu, 09 Jul 2015 11:04:27 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!i4no438232ige.0!news-out.google.com!w15ni32300qge.0!nntp.google.com!m107no1660217qgd.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jul 2015 11:04:27 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.169.242.59; posting-account=KP_pzAoAAAAOIfvJpkBnN2sZWIGGE9eX NNTP-Posting-Host: 80.169.242.59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: CCC=CIUCCIA CAZZI DI CAVALLO PAOLO BARRAI DI CRIMINALI BSI ITALIA SRL E WMO SA PANAMA, APPENA CACCIATO (E FATTO CONDANNARE A GALERA) DA CITIBANK, PRIMA DI SPENNARE POLLI VIA WEB, FECE FILM PEDOPORNOMOSESSUALI E CON CAVALLI! CIUCCIANDO FALLII EQUINI.. From: "CHE SIA REVOLUCIOOON!!!" Injection-Date: Thu, 09 Jul 2015 18:04:27 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 56782 X-Received-Body-CRC: 1021365998 Xref: mx02.eternal-september.org comp.lang.vhdl:8376 CCC=3DCIUCCIA CAZZI DI CAVALLO PAOLO BARRAI DI CRIMINALI BSI ITALIA SRL E W= MO SA PANAMA, APPENA CACCIATO (E FATTO CONDANNARE A GALERA) DA CITIBANK, PR= IMA DI SPENNARE POLLI VIA WEB, FECE FILM PEDOPORNOMOSESSUALI E CON CAVALLI!= CIUCCIANDO FALLII EQUINI.. -NAZIRAZZISTA, MEGA RICICLA CASH MAFIOSO PAOLO BARRAI DI CRIMINALISSIMA WMO= SA PANAMA (IN COMBUTTA CON BESTIA MALAVITOSA GERARDO SEGAT DI DELINQUENTIS= SIMA FIDUCIARIA T&F TAX AND FINANCE SA LUGANO... NON PER NIENTE USATA DA NO= TO NAZINDRANGHETISTA TIRANNO PEDOFILO STRAGISTA SILVIO BERLUSCONI: DETTO QU= ESTO, DETTO TUTTO... DIREI).=20 -LADRO, TRUFFATORE, AZZERA RISPARMI DI OGNUNO E SEMPRE, TUTTE LE VOLTE FALS= ISSIMO, TRUFFATORE, LADRO, MANDANTE DI OMICIDI, TERRORISTA NERO "ED IN NERO= ", GIA' VARIE VOLTE CONDANNATO AL CARCERE": PAOLO BARRAI (NATO A MILANO IL = 28.06.1965)! DI CRIMINALISSIMA WMO SA PANAMA E CRIMINALISSIMA BSI ITALIA SR= L DI VIA SOCRATE 26 MILANO (OLTRE CHE, COME DETTO, MEGALAVA CASH DI COSA NO= STRA, CAMORRA, NDRANGHETA, NARCOS COLOMBIANI, MESSICANI E RUSSI.... NONCHE'= POLITI-C-RIMINALE, CONNESSO A FASCIOPORCI SILVIO BERLUSCONI, MARINA BERLUS= CONI, MASSIMO DORIS, ENNIO DORIS, DAVIDE SERRA, UMBERTO BOSSI E MATTEO SALV= INI)! STALKA A MORTE CHI LO FOTOGRAFA E SE "UNO" INSISTE, L'ASSASSINO PAOLO= BARRAI FA "SUICIDARE" DAVVERO!!! - FREQUENTISSIMO MANDANTE DI BERLUSCONIANI E LEGHISTI OMICIDI MASCHERATI DA= FINTI INCIDENTI, MALORI, PIU' SPESSO ANCORA, "SUICIDATE", PAOLO BARRAI DI = CRIMINALISSIMA WMO SA PANAMA ( ALLA DAVID ROSSI DI MONTE PASCHI O CORSO BOV= IO O ALBERTO CAPERNA O PIETRO SAVIOTTI O GIORGIO PANTO O PAOLO ALBERTI O AD= AMO BOVE O MICHELE LANDI O ANDREA PININFARINA O VINCENZO PARISI O ANTONIO M= ANGANELLI O MIKE BONGIORNO O.... ALLA GENITORI DI CLEMENTINA FORLEO O .... = ALLA GERARDO DAMBROSIO.. PER NON DIRE DEGLI ETERNI GIOVANNI FALCONE E PAOLO= BORSELLINO... TUTTA GRANDE GENTE FATTA AMMAZZARE IN MILLE DIVERSI MODI DAG= LI ASSASSINI, FINANCO STRAGISTI, SILVIO BERLUSCONI, MARINA BERLUSCONI, ENNI= O DORIS, MASSIMO DORIS, UMBERTO BOSSI, ROBERTO MARONI, MATTEO SALVINI E I T= ERRORISTI NERI E SPECIALMENTE " IN NERO", PAOLO BARRAI E MAURIZIO BARBERO, = NOTO PEDERASTA ASSASSINO DI TECHNOSKY: POTETE STARNE STRA CERTI)=20 -NOTO NAZIPEDERASTA PAOLO BARRAI (28.06.1965) DI MALAVITOSE WMO, PROF:IT E = BSI ITALIA SRL DI VIA SOCRATE 26 A MILANO, CHE PER DIFENDERE IL SUO MANDANT= E FASCIOCAMORRISTA, STRAGISTA E NOTO PEDOFILO COME LUI, SILVIO BERLUSCONI (= NOTARE BENE, PLEASE, CHE STO SODOMIZZA BAMBINI DI FIAMMA TRICOLORE, FORZA = NUOVA, CASA POUND, FORZA ITALIA E LL - LEGA LADRONA, PAOLO BARRAI, E' IN PO= SSESSO DA ANNI DELLA REPELLENTE, VOMITEVOLISSIMA TESSERA DI ORGOGLIO PEDOFI= LO:=20 http://en.wikipedia.org/wiki/North_American_Man/Boy_Love_Association ) HA S= PESSO DETTO E SCRITTO: " CHE LA PEDOFILIA NON E' UN REATO, IN QUANTO NEL TE= RZO MONDO, TANTE BAMBINE DI 10, 11, 12 ANNI, RIMANGONO IN CINTA"! PER AGGIU= NGERE IN PRIVATO E SPESSISSIMO, FRASI DA FAR MEGA SUPER STRA ACCAPONARE LA = PELLE, OSSIA, CHE E' FIERO DI AVER SODOMIZZATO I SUOI FIGLI RICCARDO BARRAI= E COSTANZA BARRAI FIN DALLA NASCITA! MOSTRANDO ANCHE DELLE FOTO PEDOPORNOM= OSESSUALI, IN CUI "ATTORE" ERA LO STESSO NAZIPEDERASTA PAOLO BARRAI! FOTO D= I FILM PER PEDOFILI OMOSESSUALI O PEDOFILI IN GENERE ( COME PAOLO BARRAI E = SUO PAPPONE NAZIMAFIOSO SILVIO BERLUSCONI) DEGLI ANNI 2000, 2001, 2002 (OSS= IA, APPENA DOPO CHE LO STESSO AVANZO DI GALERA PAOLO BARRAI VENIVA CACCIATO= MALISSIMAMENTE DA CITIBANK PER CRIMINI EFFERATI CHE LO STESSO, LI, COMMETT= EVA, PER POI VENIR CONDANNATO AL CARCERE SU DENUNCIA DI CITIBANK: COSA DI C= UI PRESTO SCRIVEREMO). IN CUI '" LA STAR" ERA PROPRIO DETTO PPP PUZZONE PER= VERTITO PAZZO DI PAOLO BARRAI. RAFFIGURATO A FARE FILM PORNO CON RAGAZZINI = DI 12-14-16 ANNI! O, SCIOCCANTISSIMAMENTE, MENTRE FACENTE SESSO ORALE E NON= SOLO, CON CAVALLI ( FOTO CHE ERANO IN INTERNET E CHE, APPENA IL TUTTO INIZ= IO' A VENIRE A GALLA, LO STESSO FALLITO DEPRAVATO PAOLO BARRAI, PER POTER P= IU' FACILMENTE "SPENNARE POLLI IN RETE" VIA SUE TRUFFE FINANZIARIO-NAZI-MED= IATICHE, FECE CANCELLARE))! QUI MI FERMO O LA MIA BILE O PANCREAS O FEGATO = O STOMACO O CUORE O TUTTO QUESTO INSIEME, FAN CRACK, E MI MANDAN ALL' ALTRO= MONDO SUBITO!=20 TORNIAMO SU TERRENI PIU' "NORMALI", PLEASE, PER QUANTO LE COSE ESTREMAMENTE= ORRIDE APPENA DESCRITTE, SONO SUPER STRA VERE!!!=20 -FASCIONDRANGHETISTA, LADRO, TRUFFATORE, SPENNA POLLI DEL WEB, PERICOLOSISS= IMO AZZERARISPARMI, MEGA LAVA SOLDI DI COSA NOSTRA, CAMORRA, NDRANGHETA, O = SOLDI POLITI-C-RIMINALISSIMI, ESATTAMENTE FRUTTI DI MEGA MAZZETTE O RUBERIE= DI LL LEGA LADRONA ED EX PDL, POPOLO DI LADRONI. PLURI PREGIUDICATO, DIVER= SE VOLTE FINITO IN CARCERE: PAOLO BARRAI NATO A MILANO IL 28.06.1965=20 https://it.linkedin.com/pub/dir/?first=3DPAOLO&last=3DBARRAI&search=3DSearc= h=20 (RICICLANTE CASH CHE COLA ANCHE SANGUE DI MORTI AMMAZZATI; NON SOLO PER PRI= MA CITATE MALAVITE ORGANIZZATE O AL CAPONE MISTI AD ADOLF HITLER DELLA POLI= TICA, COME SILVIO BERLUSCONI E MATTEO SALVINI; MA ANCHE PER VIA DI SUOI CAM= ERATA KILLER QUALI MASSIMO CARMINATI E GENNARO MOKBEL; COME, AI TEMPI, TANT= O QUANTO, PER ALTRI SUOI CAMERATA DELINQUENTISSIMI QUALI WALTER LAVITOLA, A= LESSANDRO PROTO, FRANCO FIORITO E FRANCESCO BELSITO; O PER PICCIOTTINCRAVAT= TATI QUALI IL PERICOLOSISSIMO MEGARICICLA SOLDI MAFIOSI: GIOVANNI RAIMONDI = DI DI PIA PARTECIPAZIONI 20121 MILANO FORO BUONAPARTE 12; GIA' DI MALAVITOS= A BANCA SAI, MALAVITOSA GIOVANNI RAIMONDI SIM E MALAVITOSO GIOVANNI RAIMOND= I AGENTE DI CAMBIO; DA SEMPRE, QUEST'ULTIMO, FACENTE OGNI TIPO DI DELITTO F= INANZIARIO, CON O PER, SUOI PAPPONI MA-F-ASCISTI ENNIO DORIS, MASSIMO DORIS= , SILVIO BERLUSCONI, PAOLO LIGRESTI ED IGNAZIO LA RUSSA). COLLETTO ARCI FET= IDO PAOLO BARRAI DI CRIMINALISSIMO WMOGROUP, CRIMINALISSIMA BSI ITALIA SRL = DI VIA SOCRATE 26 MILANO E PRECIPITANTE BLOG MERCATO 'MERDATO' LIBERO ( TAL= MENTE PRECIPITANTE CHE DALLA VERGOGNA ESTREMA DI MOSTRARE CHE GLI VI SONO R= IMASTI, AL MASSIMO, 3 LETTORIDIOTI AL GIORNO, HA LEVATO DALLO STESSO IL CON= TATORE: IAMM E STRA IAMM BEEE). PRIMA DI CONTINUARE A DESCRIVERE QUESTO UGO= FANTOZZI ( OSSIA SEMPRE PERDENTISSIMO) MISTO A RENATO VALLANZASCA ( OSSIA = SEMPRE CRIMINALISSIMO), DELLA FINANZA, CHE E' IL COLLETTO LERCIO PAOLO BARR= AI, VORREI, PER INIZIARE, SOTTOLINEARE COME MAI E POI MAI SI SIAN VISTI DEI= CAGNACCI BRUCIA AVERI ALTRUI COME L'AVANZO DI GALERA PAOLO BARRAI STESSO, = UNITO AL NOTO LADRO, TRUFFATORE, SEMPRE SBAGLIANTE IN BORSA, FEDERICO IZZI = CONOSCIUTO A TUTTI COME 'ER ZIO ROMOLO DELLA CAMORRA'. UNA PROVA? ALTRO CHE= UNA, VE NE SONO MILIARDI DI PROVE! IAMM BELL, IA! INIZIAMO SOLO CON 2 'PRO= VETTE' SU MILIONI DI MILIONI ( PRESTO CENTINAIA DI MIGLIAIA DI BLOGS CHE LE= MOSTRERANNO TUTTE, LE CANNATE DISTRUGGI RISPARMI DI MIGLIAIA DI PERSONE, D= I PAOLO BARRAI DI ESTREMISSIMAMENTE MALAVITOSA WMO)! IL 5.9.14 DICEVAN DI V= ENDERE, CHE IL DOW JONES A GIORNI SAREBBE CROLLATO SOTTO 15.000 DA 17200 CI= RCA OVE ERA=20 http://www.mercatoliberonews.com/2014/10/dow-jones-atteso-in-area-15000.htm= l=20 "INFATTI".... AAAH, SIAMO SCHIZZATI IN SU FINO AI MASSIMI DI TUTTI I TEMPI!= QUASI 18.000! SIAM SCHIZZATI IN SU E TANTISSIMO! MILIARDESIMA, "ENNESISSIM= A" LORO CANNATA!=20 DA SCHIATTARE DAL RIDERE! GUARDATE QUI, PLS, COSA, L'ESCREMENTO NAZISTA, LA= VA SOLDI MAFIOSI, LADRO, TRUFFATORE FEDERICO IZZI (AGAIN AND AGAIN AND AGAI= N: NOTO A TUTTI COME "ER ZIO ROMOLO DELLA CAMORRA" IN QUANTO CAMPA SOLO E S= EMPRE DI RICICLAGGIO DI SOLDI ASSASSINI), RAGLIAVA IL 5.9.14: http://www.mercatolibero.info/zio-romolo-i-mercati-esagerato/ ESATTAMENTE DA QUELLA DATA, IL DOW JONES E' SCHIZZATO IN SU COME UN RAZZO https://es.finance.yahoo.com/echarts?s=3D%5EDJI GIUSTO... COSI'... PER MENZIONARNE UN ALTRA, UNA SU MILIONI DI MILIONI, LA = PRIMA CHE MI VIENE IN MENTE... FACEVA VENDERE AZIONI AD INIZIO 1.2012 E TUT= TO E' SALITO PER 3 MESI! http://mercatoliberotraderpergioco.blogspot.fr/2012/01/ci-attende-un-gennai= o-di-ribassi.html FACEVA POI COMPRARE, OVVIAMENTE, AI MASSIMI, IN PIENA PRIMAVERA 2012, E SIA= M CROLLATI DA 13270 A 12115!!! FRA L'ALTRO STO SCHIFOSO PEZZO DI ME.DA DI F= EDERICO IZZI NOTO COME "ER ZIO ROMOLO DELLA CAMORRA", COME LO E' OGNI ESCRE= MENTO BERLUSCONICCHIO, E' UN TUTT'UNO CON MALAVITE DI TUTTO IL MERIDIONE DI= FECCIA DITTATORIALE DI "RENZUSCONIA". E, TENTEVI DURO, DELLA BANDA DELLA M= AGLIANA. OLTRE CHE CON PRIMA CITATI VERMI DEI GIRI DI MASSIMO CARMINATI E G= ENNARO MOKBEL! COME UN ESTRATTO DI RECENTE VINCENTISSIMO TESTO CHE GIRA PER= LA RETE, STRA DIMOSTRA: "...BESTIA CHE MEGA TRUFFA VIA WEB E FA SEMPRE PER= DERE TUTTI I RISPARMI DI TUTTI, PUZZONE CRIMINALE FEDERICO IZZI DI ROMA. NO= TO COME ZIO ROMOLO! VICINISSIMO AD ENRICO NICOLETTI, NOTO MALAVITOSO BANCHI= ERE DELLA BANCA DELLA MAGLIANAhttp://www.agoravox.it/Arrestato-Enrico-Nicol= etti-il.html , VICINISSIMO A TERRORISTI NAZISTI COME MASSIMO CARMINATI E GE= NNARO MOKBEL! VICINISSIMO AI CRUDELI ASSASSINI "CASALESI", VIA, NOTORIAMENT= E, MEGA OMICIDA FAMIGLIA CAMORRISTA DEI BARDELLINO http://www.ilfattoquotidiano.it/2011/12/10/affari-politici-camorra-formia-a= vamposto-laziale-casalesi/176674/ PRESSO FORMIA E LATINA ...." ....D'ALTRONDE.... STO VERMINOSO AVANZO DI GALERA IN QUANTO PIU' VOLTE ARRESTATO, PAOLO BARRAI= DI CRIMINALISSIMA WMO, CRIMINALISSIMA BSI ITALIA SRL DI VIA SOCRATE 26 MIL= ANO E CRIMINALISSIMO BLOG MERCATO "MERDATO" LIBERO.... QUANDO SCROCCAVA GRA= TIS IL GENIO BORSISTICO ED EROE CIVILE MICHELE NISTA ( DI CUI PRESTO SCRIVE= RO' NON POCO), E SOLO E SEMPRE GRAZIE A MICHELE, CI GUADAGNAVA PARECCHI SOL= DI, SCRIVEVA LA MERA VERITA', OSSIA CHE MICHELE NISTA ERA (ED ANCORA E') IL= NUMERO UNO AL MONDO IN FIUTO BORSISTICO, COME PURE POLITICO ED INVESTIGATI= VO! ORA, INVECE, SICCOME NON LO RIESCE A SCROCCARE PIU', LO VUOLE MORTO! MA= I VISTO UN BASTARDO, FALSONE, TRUFFATORE, SFACCIATO, SCAFATO LADRO E I ASSI= CURO, PURE MANDANTE DI OMICIDI, COME PRESTO PROVEREMO, COME PAOLO BARRAI DI= MALAVITOSISSIMA WMO! TORNIAMO A MICHELE, DI CUI ACCENNAVO. ECCO UNO SCRITTO CHE GIRA SU INTERNET= , E CHE, ASSICURO, SCRIVE ASSOUTISSIME, E, TANTO QUANTO, PROVABILISSIME VER= ITA': "GENIO BORSISTICO ED EROE CIVILE MICHELE NISTA (michelenista@gmx.com)= . AZZECCA IN AZIONI E MATERIE PRIME, SEMPRE. SU TUTTO. OGNI GIORNO. IN OGNI= ANGOLO DEL PIANETA TERRA. SIA A LIVELLO DI AZIONARIO, CHE DI MATERIE PRIME= . GENIO IN INVESTIMENTI MOBILIARI, MA PURE UN EROE. STA DISTRUGGENDO IL MAF= ASCISTASSASSINO, PEDOFILO SILVIO BERLUSCONI E SALVANDO, COSI', L'ITALIA, CH= E GIUSTAMENTE, CHIAMA, AL MOMENTO, DITTATURA FASCIONDRANGHETISTA DI BERLUSC= ONIA!!! MAI VISTO UN ASSOLUTO GENIO COME MICHELE NISTA. AZZECCA IN AZIONI E MATERIE= PRIME SEMPRE, SEMPRE, SEMPRE. E NON SOLO IN AZIONI A MATERIE PRIME, MA SU = TUTTO. AZZECCA SU TUTTO, E ANCHE CON NOVE, DODICI MEDI DI ANTICIPO. LO DICE= CARTA CHE CANTA, LO DICONO SUE EMAILS E POST. IL GRANDISSIMO GENIO E RE MI= DA MICHELE NISTA, HA PRESO IL RIBASSO DEL DOW JONES DEL 2007 E 2008, IL RIA= LZO DEL MARZO 2009, IL MINIMO DEL DOW JONES A 9700, DEL LUGLIO 2010, IL RIA= LZO DI INIZIO AUTUNNO 2010, IL RIBASSO DEL MAGGIO 2011, E L'ESPLOSIVO RIALZ= O CHE CI HA PORTATO AI GIORNI NOSTRI. AZZECCA SU TUTTO E' SEMPRE, IL GENIO = MICHELE NISTA. SU TUTTO E SEMPRE. MA COME FA??? MICHELE NISTA, UN GRANDISSI= MO GENIO, IL PIU' GRANDE GENIO BORSISTICO, DA SECOLI IN QUA. LO DICONO TONN= ELLATE DI FATTI, LO DICE CARTA STAMPATA DA INTERNET, CHE CANTA COME UN USIG= NOLO. MICHELE NISTA, SEI UN GRANDISSIMO GENIO"! Ciao a tutti. Mi chiamo Gianni, sono di Rimini, e vivo tra la mia citta' na= tale e Stoccolma, essendo mia moglie svedese. Devo dire che ho grande vogli= a di esprimere la mia gioia di conoscere l'assolutissimo genio Michele Nist= a (michelenista@gmx.com), di cui son felicissimo e arricchitissimo cliente.= Un genio senza se e senza ma. Genio e eroe, in quanto sta salvandoci anche= dalla dittatura maf..ascista ed assassina di Silvio Berlusconi. Con una cr= eativita', energia, coraggio, e specialmente, risultati vincentissimi, che = non trovi da nessuna altra parte, e mai. Non sbaglia mai e stra mai, ovvero= , azzecca sempre, facendo fare tantissimi soldi, a tutti, in previsioni su = azioni e materie prime. Ma azzecca anche, qualsiasi previsione in politica,= calcio. Qualunque altra cosa. Michele Nista e' una vera e propria success = machine, tutti i giorni dell'anno. Michele Nista e' un grandissimo Re Mida,= uno dei piu' grandi Re Mida di tutti i tempi, in azioni, materie prime e n= on solo. E questo da fine anni 80, non solo da ora. O da due, tre anni. E' = molto boicottato, il genio Michele Nista, da un topo di fogna, gia' condann= ato al carcere in Italia, Brasile, e indagato in Inghilterra, che e' il pervertito sessuale, nazista, minacciante morte, e q= uindi, assassino: Paolo Barrai di Mercato Libero. Non mi credete su che verme sia l'assassino fallito Paolo Barrai che attacc= a sempre, il genio in azioni e materie prime, nonche', eroe civile, Michele= Nista? Allora date un'occhiata a cosa scrive chi da lui, si e' visto, di f= atto, derubare milioni di euro, tutti risparmi che aveva: Gruppo di risparmiatori truffati da bastardissimo criminale, pluri pregiudi= cato, avanzo di galera Paolo Barrai ( Blog Mercato "Merdato" Libero). Da in= capace, delinquente, ladro, mega lava EURO mafiosi o "politicriminali", pad= anazista, berlusconazista, razzista, antisemita, super cocainomane, acclara= to pedofilo, frequente mandante di omicidi Paolo Barrai ( Mercato Libero no= to a tutto il mondo come Mer-d-ato Libero). Si, assolutamente, pure assassi= no Paolo Barrai ( "suicidatore" di David Rossi di Mps ma non solo). Schifos= o lava cash mafioso e killer Paolo Barrai nato a Milano il 28.6.1965. E, pr= ima di ora scappare come un vile ratto, a Lugano, in Svizzera (avendo paura= di venire arrestato, in quanto indagato da Procure di Mezza Italia) e fra = poco ancora pi=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=B9 lontan= o: a Panama ( ove lo proteggerebbe il criminalissimo nazifascista corrottis= simo ambasciatore lava EURO e $ mafiosi Giancarlo Maria Curcio http://www.ambpanama.esteri.it/Ambasciata_Panama/Menu/Ambasciata/Ambasciato= re/ non per niente, vicino al noto camorrist-avanzo di galera Valter Lavitola http://www.ilfattoquotidiano.it/2012/05/01/ecco-legami-valter-lavitola-lamb= asciatore-curcio-panama/214621/ http://www.bergamonews.it/politica/lavitola-e-berlusconi-intercettazoni-e-r= icatti-hard-di-panama-183608) =20 Verme repellente Paolo Barrai di Mercato Libero: facente sue terrificanti d= elinquenze in cravatta da casa ( comprata attraverso centinaia di estorsion= i di quando trafficava in Citibank e tantissimi altri crimini) di Via Ippod= romo 105 Milano. O DAGLI UFFICI DI MALAVITOSA, MEGA LAVA SOLDI DI COSA NOST= RA, LADRONA, BASTARDAMENTE CRIMINALE BSI ITALIA SRL DI VIA SOCRATE 26 MILAN= O. IN MANO A SUO PADRE, NOTO PADANAZIS-T-RUFFATORE E PURE NOTO PEDERASTA VI= NCENZO BARRAI. ABITANTE IN VIA PADOVA 282 A MILANO E NATO A MILANO IL 3.5.1= 938 Ciao, sono Antonella di Milano, e faccio parte di un foltissimo gruppo di c= lienti derubati di tutto, dall'assolutamente criminale Paolo Barrai (Mercat= o Libero, ormai noto nel mondo intero come Mer-d-ato Libero). Costui =C3=83= =C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 davvero un bastardo assass= ino sicario. A tutti noi, uniti ora in una associazione " Risparmiatori tru= ffati da spietato criminale Paolo Barrai di Mercato Libero (e siamo gia' in= centoventi, dico centiventi: di tutta Italia, Brasile, Germania e Svizzera= )" ci fece andare corti ( al ribasso) sul mercato azionario italiano a iniz= io 2009 (col Dow Jones ai minimi degli ultimi decenni: 6900; cosa che avreb= be potuto fare solo l'Ugo Fantozzi misto a Renato Vallanzasca della Finanza= : Paolo Barrai). Abbiam perso quasi tutti tra il 70 e il 100 per cento dei = nostri investimenti. E quando gli telefonavamo per chiedere semplicemente c= he fare, mentre il mercato saliva rapidissimamente, dal Marzo 2009 in avant= i, egli, se non meglio dire, "esso", come un vile ratto, scappava. Si facev= a sempre negare al telefono. Mandavamo e mails, nessuna risposta. Citofanav= amo agli uffici di ultra truffatrice, ultra malavitosa, ultra ladrona Bsi I= talia Srl di Via Socrate 26 a Milano di suo padre, notoriamente pure pedofi= lo, oltre che mega ricicla soldi criminal-istituzionali o mafiosi, Vincenzo= Barrai di Via Padova 282 a Milano, ci vedeva dalla telecamera e nemmeno ci= rispondeva. Nemmeno ci apriva il cancello di entrata. Io non sto offendend= o, sto solo dicendo la mera verit=C3=83=C6=92=C3=86=E2=80=99 . E fra poco l= a faremo sapere a fior fior di Tribunali di mezza Italia, anzi, mezzo Piane= ta Terrra!!! Che i delinquenti ti debbano fare fessa, e pure non permettano= replica, no eeeee. Il neofascismo e la mafia del delinquente, del ladro, d= el truffatore, del professionalmente incapacissimo, del davvero bastardo de= ntro e fuori Paolo Barrai di Mercato Libero alias Mer-d-ato Libero, a noi n= on fa nessuna paura. Una truffata, derubata di tutto, dal verme assassino Paolo Barrai (gi=C3=83= =C6=92=C3=86=E2=80=99 riciclante soldi di Mafia, Camorra, Ndrangheta, come = di mastodontici ladrocinii o mega corruzione di Umberto Bossi e Silvio Berl= usconi). Fra l=C3=83=C6=92=C3=A2=E2=82=AC=C5=A1=C3=83=E2=80=9A=C3=82=C2=B4a= ltro, socio, non compare di malavita, ma socio di: arrestato Alessandro Proto http://www.ilfattoquotidiano.it/2013/02/14/manipolazione-del-mercato-arrest= ato-a-milano-finanziere-alessandro-proto/500117/ arrestato Francesco Belsito http://www.ilsole24ore.com/art/notizie/2013-04-24/arrestato-belsito-tesorie= re-lega-093844.shtml?uuid=3DAb3Bm4pH detto questo detto tutto.. immaginerei!! Mi ha bruciato 700.000 euro. Tutto quello che avevo. Ma a tanti altri ha br= uciato 1, 2, 3, 5, 7, 10 milioni di euro. Facendo comprare il gas naturale = a 5$ e passa, che in poche settimane crollava a 1,9$. Facendo vendere il Do= w Jones a 6900, ossia ai minimi di tanti ultimi anni. Dow Jones che ora qua= si vale il doppio. E senza che lui prendesse telefonate, rispondesse ad ema= ils. Senza dare indicazione alcuna a noi clienti terrorizzati! Come uno str= uzzo che dalla paura e coscienza di essere incapacissimo a livello di fiuto= per investimenti, mette la testa sotto la sabbia. =20 Il verme brucia risparmi di una vita Paolo Barrai oltre ad essere il peggio= re consulente per investimenti borsistici o di qualsiasi altro tipo, ove in= esorabilmente sbaglia sempre (ha fatto comprare case in Brasile, a Porto Se= guro ... ove lo attendono 8 ANNI DI GALERA SE VI CI TORNA, E NE SCRIVER=C3= =83=C6=92=C3=86=E2=80=99=C3=83=C2=A2=C3=A2=E2=80=9A=C2=AC=C3=85=E2=80=9C PR= ESTISSIMO.. dicevo... ha fatto comprare case in Brasile, a Porto Seguro, co= l real a 2,1 contro l'euro.. e ora son state tutte sequestrate dall'anti ma= fia Brasiliana, per mega riciclaggio per conto di Cosa Nostra, Camorra e Nd= rangheta.. e comunque, il real brasiliano =C3=83=C6=92=C3=86=E2=80=99=C3=83= =E2=80=9A=C3=82=C2=A8 passato dai massimi di 2,1 contro l'euro, livello di = quando il cagnaccio idiota, brucia risparmi di una vita, Paolo Barrai, ha f= atto comprare, financo a 3,2 contro euro.. creando perdite economiche immen= se, in ogni caso, a chi come " un ciuccio ei napule" le avesse con lui acqu= istate). Ove mai, mai e ri mai ne azzecca mezza! =C3=83=C6=92=C3=86=E2=80= =99=C3=83=C2=A2=C3=A2=E2=80=9A=C2=AC=C3=82=C2=B0 anche un irresponsabile, a= rrogante, nazista, razzista, lava soldi mafiosi, codardo, ladro, truffatore= , criminale, falsissimo, pedofilo, si, PEDOFILO PAOLO BARRAI (SE NO CHE BER= LUSCONES SAREBBE, SCUSATE???)!!! ANCHE QUI LO PROVER=C3=83=C6=92=C3=86=E2= =80=99=C3=83=C2=A2=C3=A2=E2=80=9A=C2=AC=C3=A2=E2=80=9E=C2=A2 E PRESTISSIMO)= !!!!!! E mi dicono che ha pregresse, pure varie condanne al carcere. A Milano (com= e da questi seguenti articoli: il criminalissimo "funzionario nei guai" di = Citibank, a seguito dell'arresto del suo "Kameraden Berlusconazisten und Pa= danazisten" Pietro Terenzio, come da fine scritto che qui segue, =C3=83=C6= =92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 assolutissimamente lui: http://archiviostorico.corriere.it/2001/febbraio/02/Arrestato_imprenditore_= delle_truffe_fiscali_co_7_0102023408.shtml http://ricerca.repubblica.it/repubblica/archivio/repubblica/2001/02/19/maxi= -evasione-da-400-miliardi-terenzio-sotto-torchio.html). A Biella: http://www.finanzaonline.com/forum/messaggi-archiviati-fol/637689= -piccole-sim-con-l-acqua-alla-gola-bregliano-e-nuovi-investimenti.html Ed in Brasile, ove ha passato giornate e giornate in prigione nel Marzo 201= 1 e ove lo attendono ora, se vi ci torna: OTTO ANNI DI CARCERE! SENTENZIATI= SSIMO!!! Come qui super provato, pure. E da siti di tutto il Globo terrestr= e!!! http://4.bp.blogspot.com/-aqbT4KlYsmw/TcLbvUUpkeI/AAAAAAAAAe4/TiDPLR0LH_U/s= 1600/barrai+ind-pag01.jpg http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D2996 http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D3000 http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D3004 http://portoseguroagora.blogspot.co.uk/2011/03/porto-seguro-o-blogueiro-ita= liano-sera.html http://noticiasdeportoseguro.blogspot.co.uk/2011/03/quem-e-pietro-paolo-bar= rai.html http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato.html http://www.osollo.com.br/online/index.php/crimes/3052-blogueiro-italiano-se= ra-indiciado-por-estelionato-calunia-e-difamacao-pela-policia-civil-de-port= o-seguro http://www.osollo.com.br/online/index.php/crimes/3079-blogueiro-barrai-quer= -constituir-sindicato-so-para-estrangeiros-em-porto-seguro http://www.francodarochanews.jex.com.br/acontece+agora/policia+-+noticias+p= olicia+civil+investiga+blogueiro+suspeito+de+estelionato+blogueiro+paolo+ba= rrai+a+internet+esta+virando+cada+vez+mais+palco+para+crimes+e+investigacoe= s+que+ultrapassam+fronteiras+e+nacoes+a+policia+civil+de+porto+seguro+esta+= invest http://www.umbuzada.com/v2/imprimir_noticia.php?id=3D1869 http://www.geraldojose.com.br/index.php?sessao=3Dnoticia&cod_noticia=3D1395= 0 https://groups.google.com/forum/#!topic/comp.soft-sys.matlab/j3oyd-SmJ88 http://inquisitore.org/2013/08/26/paolo-barrai-se-lo-conosci-lo-eviti/ http://www.consob.it/main/documenti/hide/afflittivi/pec/mercati/2013/d18579= .htm Aaa, ad averlo saputo prima e non essermi fidata di sta bastarda, criminali= sssima Lega Nord =3D LL =3D Lega Ladrona, di cui ero parte, e che mi ha mes= so in contatto col loro affiliato mafioso, brucia risparmi di una vita e su= per truffatore Paolo Barrai. Ora mi son sfogata qui. Presto lo ri far=C3=83= =C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=B3 in fronte a Guardia di Fin= anza, Polizia, Carabinieri, Magistrati, Giudici! E con me, almeno altre 120= persone! Oooo!! Non cascateci, ne scrivo proprio per questo!!! Via subito = e per sempre dal criminale, delinquente, ladro, truffatore, professionalmen= te bestia: Paolo Barrai di Mercato Libero!!!!! E BASTA ANCHE CON STO EX PDL= =3D POPOLO DI LADRONI!! E LL=3D LEGA LADRONA!!! CAPACI SOLO DI ACCUMULARE = MAZZETTE DI FINMECCANICA, ENEL, ENI, ENAV, TECHNOSKY, MAFIA, CAMORRA, NDRAN= GHETA, DITTATORI SU DITTATORI QUALI GHEDDAFI E NON SOLO (COME DITTARORI SON= O I VERMI BASTARDI ED ANCHE ASSASSINI, VI ASSICURO: UMBERTO BOSSI E SILVIO = BERLUSCONI)! E PER CENTINAIA DI MILIONI DI EURO! CAPACI SOLO DI FREGARE TON= NELLATE DI SOLDI VIA QUOTE LATTE E RIMBORSI ELETTORALI! E POI METTERE TUTTO= ALL'ESTERO PRESSO CRIMINALISSIMA FINTER BANK LUGANO DI DELINQUENTI IN CRAV= ATTA FILIPPO CRIPPA E GIOVANNI DEI CAS (MA DI CERTO NON SOLO)!! O PRESSO SU= PER LAVA SOLDI CRIMINALISSIMI, FINECO DI ALESSANDRO FOTI. DEL BANCHIERE PRE= FERITO DA NDRANGHETA, CAMORRA E COSA NOSTRA: ALESSANDRO FOTI DI FINECO! E I= L TUTTO PROPRIO ATTRAVERSO QUESTO COLLETTO VERMINOSO, DA RINCHIUDERE IN GAL= ERA E SUBITO, DI PAOLO BARRAI (CHE OLTRE A RICICLARE SOLDI CRIMINALISSIMI P= RIMA CITATI, LO FA ANCHE PER I SUPER LADRONI LIGRESTI DI SAI FONDIARIA.....= OVE NON PER NIENTE LAVORAVA IL BANCHIERE CIELLINO PREFERITO DA TUTTE LE MA= LAVITE: GIOVANNI RAIMONDI... ORA DI NETSYSTEM, EX DI MALAVITOSISSIME BANCA = SAI, GIOVANNI RAIMONDI SIM E GIOVANNI RAIMONDI AGENTE DI CAMBIO)! Antonella= di Milano. PS 1 NON POCCO NON AGGIUNGERE, PER "QUASI" TERMINARE, CHE L'AVANZO DI GALERA, PU= RE ASSASSINO PAOLO BARRAI ( HA FATTO SUICIDARE DAVID ROSSI DI MONTE PASCHI = PER UNA GUERRA DI SEO IN CORSO FRA DAVID ROSSI STESSO, E.. CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI MASSIMO DORIS D= I BANCA MEDIOLANUM CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI ENNIO DORIS DI = BANCA MEDIOLANUM CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI EDOARDO LOMBARD= I DI BANCA ESPERIA E BANCA MEDIOLANUM CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI GIOVANNI PIROVA= NI DI BANCA MEDIOLANUM CRIMINALISSIMO LAVA EURO MAFIOSI E PURE MANDANTE DI OMICIDI OSCAR DI MONTIG= NY DI BANCA MEDIOLANUM ... GUERRA CHE DAVID ROSSI DI MONTE PASCHI STAVA VINCENDO, DA QUI IL TAGLIA= RGLI LE VENE E FARLO VOLARE DALLA FINESTRA.. ALTRO CHE SUICIDIO) HA APPENA = BECCATO "ALTRI" 70.000 EURO DI MULTA! DALLA CONSOB! PER I SUOI SOLITI BASTA= RDISSIMI CRIMINI IN CRAVATTA! http://www.consob.it/main/documenti/hide/afflittivi/pec/mercati/2013/d18579= .htm http://www.advisoronline.it/albo/consob/22190-consob-sanziona-a-raffica.act= ion http://www.bluetg.it/banche-e-reti/179-promotori/28601-qmultaq-da-70mila-eu= ro-per-un-ex-promotore-che-ha-violato-gli-obblighi-informativi.html http://www.finanzaonline.com/forum/trading-line/1454952-barrai-spiega-come-= non-pagare-la-tobin-2.html http://www.maidireborsa.it/showthread.php?27302-Paolo-Barrai-di-Mercato-Lib= ero-sanzionato-dalla-Consob http://inquisitore.org/2013/09/23/paolo-barrai-condannato-dalla-consob/ https://www.google.it/#q=3Dpaolo+barrai+consob PS 2 AGGIUNGEREI A MO' CI CONTROPROVA DEL SOPRA RIPORTATO UN TESTO BELLISSI= MO CHE HO TROVATO IN RETE. CIAO E GRAZIE PER EVENTUALE COMPRENSIONE E PAZIE= NZA PER I TANTI LINKS SOPRA DESCRITTI, FATTI SALTARE DA STI ASSASSINI BERLU= SCONAZISTI E PADANAZISTI, PER OVVIE RAGIONI DI LORO IMMENSO IMBARAZZO!!! 1) OCHO, PLEASE, A QUESTA GANG KILLER, FASCISTISSIMA, ANTISEMITA, ANTIEUROP= EA, ANTIAMERICANA, MEGA LAVA SOLDI MAFIOSI O POLITICRIMINALI A GO GO ( COME= DETTO, PADANAZISTA E BERLUSCONAZISTA). DA TENERE MOLTO, MOLTO, MOLTISSIMO = ALL'OCCHIO! QUESTA!!! FREQUENTISSIMI MANDANTI DI OMICIDI, NAZINDRANGHETISTI, MEGA LAVA SOLDI LERC= ISSIMI A GOGO : A) PERICOLOSISSIMO AVANZO DI GALERA PAOLO BARRAI DI MOVIMENTI TIPO " KU KLU= K KLAN PADANO" E SIA "FIAMMA TRICOLORE CHE FORZA NUOVA CHE CASA POUND": COLLETTO CRIMINALISSIMO PAOLO BARRAI: GIA' CACCIATO A SBERLE DA CITIBANK PE= R CRIMINI EFFERATI CHE LI EFFETTUAVA (come da questo seguente articolo: il = criminalissimo "funzionario nei guai" di Citibank di fine scritto =C3=83=C6= =92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 l'assolutamente scafatissimo = delinquente Paolo Barrai: http://archiviostorico.corriere.it/2001/febbraio/02/Arrestato_imprenditore_= delle_truffe_fiscali_co_7_0102023408.shtml), CON MULTE DI QUASI 100.000 EUR= O DA PARTE DI CONSOBhttp://www.consob.it/main/documenti/hide/afflittivi/pec= /mercati/2013/d18579.htm, GIA' CON GUAI LEGALI SERISSIMI A BIELLA, CONDANNA= TO AL CARCERE A MILANO E, TETNETEVI FORTE, PLS, FINANCO A PORTO SEGURO IN B= RASILE http://www.portonewsnet.com.br/?mw=3Dnoticias&w=3D2996 http://portoseguroagora.blogspot.co.uk/2011/03/porto-seguro-o-blogueiro-ita= liano-sera.html http://noticiasdeportoseguro.blogspot.co.uk/2011/03/quem-e-pietro-paolo-bar= rai.html http://www.rotadosertao.com/noticia/10516-porto-seguro-policia-investiga-bl= ogueiro-italiano-suspeito-de-estelionato http://www.jornalgrandebahia.com.br/2011/03/policia-civil-de-porto-seguro-i= nvestiga-blogueiro-italiano-suspeito-de-estelionato.html http://www.osollo.com.br/online/index.php/crimes/3052-blogueiro-italiano-se= ra-indiciado-por-estelionato-calunia-e-difamacao-pela-policia-civil-de-port= o-seguro http://www.osollo.com.br/online/index.php/crimes/3079-blogueiro-barrai-quer= -constituir-sindicato-so-para-estrangeiros-em-porto-seguro http://www.francodarochanews.jex.com.br/acontece+agora/policia+-+noticias+p= olicia+civil+investiga+blogueiro+suspeito+de+estelionato+blogueiro+paolo+ba= rrai+a+internet+esta+virando+cada+vez+mais+palco+para+crimes+e+investigacoe= s+que+ultrapassam+fronteiras+e+nacoes+a+policia+civil+de+porto+seguro+esta+= invest http://www.umbuzada.com/v2/imprimir_noticia.php?id=3D1869 http://www.geraldojose.com.br/index.php?sessao=3Dnoticia&cod_noticia=3D1395= 0 PUZZONE AVANZO DI GALERA PAOLO BARRAI DEL BLOG MERCATO "MERDATO' LIBERO. IL= SUO AVER FONDATO IL VERMINOSO, TERRORISTICO, SANGUINARIO "KU KLUK KLAN PAD= ANO"... IL SUO ASSASSINO NAZIRAZZISMO LO PORTA A DEFINIRE OBAMA BARACK ( PE= R NOI, IN QUANTO A RISULTATI, OSSIA UNICA COSA CHE CONTA, AFFATTO MALE PRES= IDENTE US), UN BASTARDO NERO ( GOOGLE BOUT IT: "MERCATO LIBERO E' PER LA GR= ANDE MADRE RUSSIA") O INNEGGIANDO INTANTO AL NAZIFASCISTA COME LUI ( E COME "SUOI" NAZIMAFIOSI E = POR-CO-RROTTI MANDANTI QUALI MATTEO SALVINI, UMBERTO BOSSI, GIULIANO FERRAR= A, MAURIZIO BELPIETRO, ENNIO DORIS, MASSIMO DORIS, MARINA BERLUSCONI E SPEC= IALMENTE, PROPRIO KAPO' PEDOFILO NUMERO UNO, PROPRIO KA-P-EDOFILO MAXIMO: S= ILVIO BERLUSCONI) A VLADIMIR PUTIN, CHE NON HA ESITATO UN SECONDO A FAR SFR= ACELLARE 300 PERSONE CHE NON GLI AVEVAN FATTO MAI NULLA DI MALE, CHE VOLAVA= NO A 10.000 METRI DI ALTEZZA, IN GRAN PARTE SCIENZIATI CHE SALVAVANO MIGLIA= IA DI PERSONE DALL'AIDS ( GOOGLE BOUT IT: "MERCATO LIBERO E' PER LA GRANDE = MADRE RUSSIA"). L'ASSASSINO NAZIRAZZISTA PAOLO BARRAI TRAFFICA CRIMINALISSIMAMENTE CON SERV= IZI SEGRETI RUSSI, UNGHERESI, SIRIANI, VICINI ALL'ISIS, DI QUALSIASI TOPAIA= DI ESTREMISSIMA DESTRA. E SVIZZERI ( E' PAGATO PER SPINGERE TUTO IL NORD D= EL VERMINAIO INCIUCIARO DI "RENZUSCONIA" VERSO BERNA, DA QUI IL SUO SPINGER= E IN QUESTA DIREZIONE, OGNI GIORNO, VIA PRECIPITANTE BLOG "MERDATO" LIBERO)= . PREPARANDO CON LORO OMICIDI "DI SCOMODI", RICICLAGGI DI CASH MALAVITOSISS= IMO, LADRATE, TRUFFE, FRODI ( PUR, OVVIAMENTE, CERCANDO VIGLIACCHISSIMAMENT= E DI DEPISTARE IL TUTTO, VIA, SUO PRECIPITANTE, LETTO ORMAI DA NESSUNO, BLO= G MERCATO "MERDATO"LIBERO... PASSATO DA 10.000 LETTORI AL GIORNO QUANDO VI = SCRIVEVA NEL 2007, 2008 E INIZIO 2009, GENIO BORSISTICO ED EROE CIVILE MICH= ELE NISTA, AI PRESENTI 90 LETTORI AL GIORNO, CHE SONO POI 20 AL MASSIMO, AL= NETTO DI SOFTWARE TAROCCONI CHE L'AVANZO DI GALERA PAOLO BARRAI USA DA SEM= PRE PER MOLTIPLICARE IL NUMERO DEI TRE PADANAZISTI E BERLUSCONAZISTI CHE AN= CORA LO LEGGONO). LAST BUT CERTAINLY NOT LEAST: MANDANTE DELL'OMICIDIO E AF= FATTO SUICIDIO DI DAVID ROSSI DI MONTE PASCHI, PER UNA GUERRA DI SEO, SEARC= H ENGINE OPTIMIZATION, CHE DAVID ROSSI AVEVA INGAGGIATO CON IL SICARIO BERL= USCONAZISTA E PADANAZISTA PAOLO BARRAI E I SUOI MANDANTI, ALIAS GLI ASSASSI= NI IN CRAVATTA DOLCE E GABBANA: MASSIMO DORIS MEDIOLANUM, ENNIO DORIS MEDIO= LANUM, EDOARDO LOMBARDI MEDIOLANUM, OSCAR DI MONTIGNY MEDIOLANUM, GIOVANNI = PIROVANO MEDIOLANUL, ETTORE PARLATO SPADAFORA MEDIOLANUM ( SANGUINARISSIME,= ULTRA OMICIDA OVRA E GESTAPO PRIVATE DI SILVIO BERLUSCONI ED ENNIO DORIS P= RIMA TAGLIARONO LE VENE A DAVID ROSSI DI MONTE PASCHI E POI LO FECERO VOLAR= E DALLA FINESTRA PER ASSICURARSI DI CERTA MORTE, LE FAMOSE EMAILS CHE DAVID= ROSSI "AVREBBE" MANDATO A VERTICI DI MONTE PASCHI PER ANNUNCIARE SUO SUICI= DIO ERAN TUTTE TUTTE E STRA TUTTE FALSE, IN QUANTO SCRITTE E FATTE PARTIRE = DA HACKERS DEL 'BERLUSCONAZISTA E PADANAZISTA' TANTO QUANTO, HACKING TEAM, = "NON PER NIENTE" FINANZIATO DAI DUE VERMI MEGA KAPO' DI PAOLO BARRAI E I DO= RIS: ROBERTO MARONI E SILVIO BERLUSCONI... COME VEDETE TUTTO STRA QUADRA) - TERRORISTA ASSASSINO DI ESTREMISSIMA DESTRA: MAURIZIO BARBERO DI TECHNOSK= Y MONTESETTEPANI E MERCATO "MERDATO LIBERO NEWS http://it.linkedin.com/pub/maurizio-barbero/8/197/a52 ( ORGANIZZANTE OMICID= I DI CHIUNQUE "SCOMODO" CON SUO KAMERADEN, ACCLARATO KILLER DI SILVIO FANEL= LA, NAZISTA GENOVESE GIOVANNI BATTISTA FENICI CHE AL VERME OMICIDA MAURIZIO= BARBERO DI TECHNOSKY MONTESETTEPANI ERA UNITO ANCHE DA UNA STORIA OMOSESSU= ALE, OLTRE CHE DA COMPLOTTI TERRORISTICI ASSASSINI NERI... "E SPECIALMENTE = IN NERO") - LA NOTA PROSTITUTA E PORNOSTAR AMATORIALE FACENTE TANTE ORGE AD (H)AR(D)C= ORE, ELISA COGNO DELLA RICICLANTISSIMA DENARI DI COSA NOSTRA, CAMORRA E NDR= ANGHETA: FRUIMEX DI ALBA. COME PURE DI MERCATO "MERDATO" LIBERO NEWS ( ZOCC= OLA CON SWASTIKA NEL CUORE NERO, CHE HA; MIGNOTTONA DI CORTE, PARTECIPANTE = A CENTINAIA DI ORGE AD H-AR-D-CORE E NON SOLO CON SUOI PAESANI NAZI-CUUNENS= I: DANIELA SANTANCHE' E FLAVIO BRIATORE) http://www.linkedin.com/pub/elisa-alba-elisa-fruimex/1b/25b/212 http://www.= impresaitalia.info/MSTDB80753147/fruimex-di-cogno-elisa-e-c-sas/alba.aspx D- LA SCHIFOSA BISCIA DI ESTREMISSIMA DESTRA, MEGA RICICLANTE CASH MAFIOSO = VIA PANAMA E BTCOINS, DELINQUENTE VERMINOSO GIACOMO ZUCCO DEI NAZIRAZZISTI = TEA PARTIES DI BERLUSCONIA, ANZI, PUZZOLENTE RENZUSCONIAhttps://twitter.com= /giacomozucco - ALTRI VERMI VARI, ASSOLUTI TERRORISTI DI ESTREMA DESTRA, PARTE DI STA PAD= ANAZISTA E BERLUSCONAZISTA GANG, SONO IL FONDATORE DEL, DA ASSOLUTI BRIVIDI= , "ORGOGLIO PEDOFILO PADANO": STEFANO BASSI DEL BLOG IL GRANDE BLUFFhttps:/= /twitter.com/grandebluff ED UN CRIMINALISSIMO FACCENDIERE ROMANO, ASSOLUTA = LAVATRICE DI PROVENTI MEGASSASSINI DI BANDA DELLA MAGLIANA, NDRANGHETA E CA= MORRA: FEDERICO IZZI NOTO COME "ER ZIO ROMOLO DEI CASALESI" https://it-it.facebook.com/pages/Zio-Romolo/71267552792 COSTORO SONO DEI COLERA KILLER CHE ODIANO GLI EBREI, CHI DI CENTROSINISTRA,= CHIUNQUE NON SIA NAZISKIN IN CRAVATTA COME LORO. ED IN MANIERA VISCERALISS= IMA. FAN PARTE DI MASSONERIE DI ESTREMISSIMA DESTRA, CON A CAPO, ANZI, A KA= PO', COME AL SOLITO, LICIO GELLI (NOTO VERME DEPISTATORE; QUINDI, ANCHE LOR= O, OGNI TANTO, SUL WEB, OVVIAMENTE, DEPISTANO, E SI FINGONO, RIPETO, FINGON= O, NON NEMICI DEGLI EBREI, O DEGLI USA O DELL'EUROPA; MA SONO ANTISEMITISSI= MI, ANTI USA, ANTI EUROPA, FILO HITLERIANI ALL'ESTREMO E PRESTO LO DIMOSTRE= REMO). IL TUTTO INSIEME AI BANCHIERI PIU' AMATI DALLE MALAVITE MONDIALI E N= ON SOLO DEL CESSO TIRANNICO DI RENZUSCONIA: http://www.gruppoesperia.it/en/About-Us/giuseppe-sabato.htmlGIUSEPPE SABATO= ED EDOARDO LOMBARDI DI BANCA ESPERIA (IL BANCHIERE PIU' "VENERATO" DA OGNI= CAMORRISTA DEL MONDO: GIUSEPPE SABATO DI BANCA ESPERIA; BASTARDISSIMO NUOV= O JOSEF MENGELE DEL CREDITO, CHE CON LICIO GELLI, NEL 1999, AVEVA FONDATO, = NON PER NIENTE, IL VERMINAIO PUZZOLENTISSIMO DELLA GRAN LOGGIA MASSONICA IT= ALIANA: https://books.google.it/books?id=3DRNdU9ZOLYCAC&pg=3DPT179&lpg=3DPT179&dq= =3Dgiuseppe+sabato+gran+loggia&source=3Dbl&ots=3DfN_a403ROF&sig=3DSeHj23vOf= eM-iKOBfr9Ir6l8llM&hl=3Dit&sa=3DX&ei=3DpZZsVeDeEsGYsgGiz4CgCg&ved=3D0CDkQ6A= EwAw#v=3Donepage&q=3Dgiuseppe%20sabato%20gran%20loggia&f=3Dfalse). UNITI AI= MICHELE SINDONA DEI GIORNI NOSTRI: ENNIO DORIS E MASSIMO DORIS DI BANCA ME= DIOLANUM (BANCA ESPERIA E BANCA MEDIOLANUM SONO DI FATTO LA STESSA FOGNA: S= ONO IL DETERSIVO FINANZIARIO NUMERO UNO DI COSA NOSTRA http://espresso.repubblica.it/palazzo/2008/05/15/news/vado-riciclo-e-torno-= 1.8408 CAMORRA, NDRANGHETA, SACRA CORONA UNITA, MA ANCHE DI NARCOS COLOMBIA= NI, NARCOS MESSICANI, MAFIA RUSSA, MAFIA ALBANESE, MAFIA RUMENA)! DICEVO, A= NYWAY: I KAMERADEN MASSO-N-AZIFASCISTI, CUGINETTI DI VERMI STRAGISTI COME A= NDERS BEHRING BREIVIK, GAETANO SAYA, RICCARDO SINDOCA, MARCO MANCINI, GENNA= RO MOKBEL, GIULIANO TACAROLI, EMANUELE CIPRIANI, MARCO MANCINI, VALTER LAVI= TOLA ( L'ESCREMENTO ASSASSINO E NAZIMAFIOSO PAOLO BARRAI E' NE PIU' NE MENO= CHE IL NUOVO VALTER LAVITOLA, AL MILIARDO E BILIARDO PER CENTO), NEL CESSO= DI BERLUSCONIA, ANZI, DA ODIARE AL MASSIMO, INCIUCIARA, LADRONA, DITTATORI= ALE E CORROTTISSIMA RENZUSCONIA, SONO I MEGA LAVA SOLDI ASSASSINI, MANDANTI= DI OMICIDI A GOGO, TERRORISTI DI ESTREMISSIMA DESTRA, RAZZISTI TANTO DA AV= ER APPENA FONDATO IL "KU KLUK KLAN PADANO" E TOPAIA NERA PRIMA CITATA". UNA= COLERICISSIMA FOGNA, OVVIAMENTE, FINANZIATA, CON CASH DI AR-COR-LEONE, DAI= SCHIFOSI FASCIOCAMORRISTI SILVIO BERLUSCONI E LICIO GELLI. E COME LO SCHIF= OSISSIMO NOTO DEPISTATORE E FALSISSIMO SILVIO BERLUSCONI SI FINGE OGNI TANT= O, AMICO DEGLI EBREI, MA DA DECENNI, RIPETO, DECENNI, ABBIAMO DOZZINE DI TE= STIMONI, IN PRIVATO RAGLIA SIMIL BARZELLETTE PER DECEREBRATI VISCIDI LECCHI= NI TIPO " SCUSATE, SONO ANDATO IN BAGNO OVE HO APPENA FATTO I MIEI BISOGNI,= MA NON VI ERA ABBASTANZA CARTA IGIENICA... HO ANCORA IL DI DIETRO SPORCO E= NON HO DEL SAPONE, AVETE UN EBREO"? OPPURE: " DI SOLITO NON FUMO, MA AKCUN= I MIEI AMICI TEXANI NAZISTI DEI TEA PARTIES MI HAN APPENA REGALATO UN MEGA = SIGARO... VORREI FARMELO ( CI CHIEDIAMO: IN CHE SENSO?), MA IL MIO ACCENDIN= O HA FINITO IL GAS... AVETE PER CASO UN EBREO"? COSI', ALLO STESSO TEMPO, I= L PERICOLOSISSIMO MANDANTE DI OMICIDI, GIA' PLURI CONDANNATO AL CARCERE, NO= N SOLO A MILANO, MA ANCHEM PARREBBE, A BIELLA ED IN BRASILE, PAOLO BARRAI, = FINGE, A SCOPO DI DEPISTAGGIO, SUL WEB, DI LECCARE PERSONE CHE DEFINISCE EB= REI DI COLOMBIA E PANAMA VICINISSIMI AI CARTELLI DI CALI', BOGOTA E DI MEDE= LLIN. MA GUARDATE ORA, PLS, COSA SCRIVE AD UN ASSOLUTO GENIO BORSISTICO MISTO AD = EROE CIVILE, ANTI NAZIFASCISMO E MAFIA DI SILVIO BERLUSCONI, DI GRAN SUCCES= SO, A LONDRA: MICHELE NISTA. GUARDATE COME GLI DAVA DEL GENIO NEL 2007, 200= 8 E PRIMA PARTE DEL 2009, QUANDO SCROCCAVA L'IMMENSO TALENTO BORSISTICO DI = MICHELE NISTA FACENDOCI MILIONI DI EURO ( IN NERO "FISCALE E POLITICO") E G= UARDATE, PLS, COSA SCRIVEVA DI MICHELE DAL 2010 IN POI, A) IN QUANTO MICHELE AVENTE PARZIALE SANGUE EBREO B) UNA VOLTA CHE IL SEMPRE VINCENTISSIMO MICHELE NISTA DECISE DI NON AVER P= IU' NULLA A CHE FARE COL VERME CRIMINALISSIMO PAOLO BARRAI DOPO AVER SCOPER= TO DEI PUTRIDISSIMI RICICLAGGI DI CASH MAFIOSO, BERLUSCONAZISTA E PADANAZIS= TA CHE PAOLO BARRAI EFFETTUAVA E STRA EFFETTUA ORA PIU' CHE MAI IN GIRO PER= IL MONDO. GUARDATE, GUARDATE, PLS, DA BRIVIDI ASSOLUTI: IL FIUTO DI UN AMICO... Post del Febbraio 2008 Qualche anno fa a Milano la borsa chiudeva poco dopo pranzo. Nel pomeriggio se un operatore istituzionale cercava titoli italiani sapeva dove andare.... Telefonava a Michele Nista. Michele Nista era un vero grandissimo broker, altro che macchina telematica. E riusciva anche a trovare prezzi migliori della macchina stessa facendo felice sia il venditore che il compratore. Anche con la chiusura dei mercati alle 17.30 Michele =C3=83=C6=92=C3=86=E2= =80=99=C3=83=E2=80=9A=C3=82=C2=A8 sempre riuscito a trovare l'introvabile. Non esisteva e ancora esiste la "missione impossibile" per Michele Nista. Un milione di Generali? Bastavano pochi minuti e venivano trovate al giusto prezzo. Poi Michele si =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3= =82=C2=A8 allontanato dal mercato, ma a Novembre l'ho incontrato dopo tanto tempo. Abbiamo bevuto un caff=C3=83=C6=92=C3=86=E2=80= =99=C3=83=E2=80=9A=C3=82=C2=A8 e abbiamo parlato del mercato... Caro Michele, farai anche altre cose ora ma il fiuto per gli affari, quello no...non ti manca. Michele, non sar=C3=83=C6=92=C3=86=E2=80=99 forse= un macroeconomista, ne uno studioso di bilanci, ma ha una particolare dote...il senso degli affari. Pochi come lui si muovono nel mercato con la stessa spavalderia. Anche nel Settembre 2007 non si =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A= =C3=82=C2=A8 sbagliato...mentre i molti urlavano al rally di Natale e il Dow Jones era intorno ai 14.000 il mio caro amico Michele mi ha guardato fisso negli occhi e mi ha detto "Ehi doctor....il Dow arriver=C3=83=C6=92=C3=86=E2=80=99 a 11.800 fra poco e poi= a 8000" Caro Michele sei stato bravo, anzi bravissimo... Ah dimenticavo di dirvi che la scorsa settimana ho incontrato Michele, questa volta non abbiamo preso un caff=C3=83=C6=92=C3=86=E2=80=99= =C3=83=E2=80=9A=C3=82=C2=A8...ma siamo passati a un pranzo anche se frugale) Sapete cosa mi ha confidato guardandomi ancora una= volta negli occhi? "ehi Doctor fra poco il dow Jones arriva a 10.800 e poi giu, fino a 8000 e poi ulteriormente giu fin sotto 7000"??? Sapete che vi dico...che se fossi Bernanke comincerei a preoccuparmi seriament, L'INIEZIONE DI DROGA DETTATA DAL TAGLIO DEI TASSI NON E' CHE UN ESTREMO TENTATIVO DI SALVARE UN MODELLO ECONOMICO ALLO SFASCIO. Vai Michele, continua cosi'!!! ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~ ALTRO POST, IN QUESTO CASO, SCRITTO IN QUESTO CASO, A META' APRILE 2009 UN GRAZIE A MICHELE NISTA Unico ad avvisare i nostri lettori di un DOW a 7700 (quando valeva 13.000) Unico ad avvisare che i mercati americani sarebbero ripartiti con le rondini, unico che a fine febbraio ha detto di comprare e di guardare le quotazioni a luglio. Michele ha affermato pi=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2= =B9 volte che Obama riporter=C3=83=C6=92=C3=86=E2=80=99 ai massimi il Dow a fine mandato. Io personalmente non sono daccordo sulla sua ultima visione= . ma questo =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 MERCATO LIBER= O un blog capace di selezionare delle persone differenti ma capaci di individuare i trend. MICHELE NISTA SEI UNA FORZA, A LIVELLO DI INTUITO, IL MIGLIORE AL MONDO INT= ERO!!! Pubblicato da mercatolibero a luned=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80= =9A=C3=82=C2=AC, aprile 13, 2009 O QUESTO. MICHELE NISTA SEI UN GRANDE!!! La scorsa settimana abbiamo scritto un articolo sulla spartizione della tv di stato e della possibile vendita di rete 4 da parte di Berlusconi. L'articolo era frutto di una chiaccherata con lo stanatartufi, = genio, in quanto a fiuto per gli affari, energie e coraggio, Guru di azioni, valute e commodities mondiali: Michele Nista. Michele =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 in gr= an forma e non lo ferma pi=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82= =C2=B9 nessuno. O il nostro articolo =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8= stato letto da Di Pietro ....o qualcosa bolla in pentola nel campo delle televisioni....( segue articolo) ...Insomma, Michele Nista, ha intuito tutto al volo, ed alla perfezione, co= me sempre. Bravo Michele sei un mito ED INFINE, POST, CHE RICEVETTE " SOLO" 203 COMMENTI MICHELE GRAZIE (MICHELE NISTA!) A nome di Mercato libero e di tutto lo staff vorrei ringraziare Michele Nista per lo stupendo lavoro fatto su questo sito da 18 mesi. Molti nuovi lettori non sanno tutto quello che ha predetto e poi si =C3=83= =C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 puntualmente avverato. NON HA SBAGLIATO UNA VOLTA. E francamente se anche domani dovesse prendere un abbaglio....non =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3= =82=C2=A8 importante. Ha salvato il culo ha migliaia di persone predicendo il DOW a 6900 quando stava a 10.000 (e predicendo il Dow a 10.000 quando stava a 13.500). Ha detto ripetutamente che il mercato sarebbe salito con l'arrivo delle rondini e cos=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=AC = =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 stato (e il rialzo n= on =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=A8 stato di quelli piccoli....)! MA QUALE BLOG O BANCHIERE, O PROMOTORE, O TRADER O PRIVATE BANKER HA SAPUTO SOLO AVVICINARSI A TALI PREVISIONI (NON NASCONDO CHE ANCHE IO ERO SCETTICO QUANDO PARLAVA DI DOW A 6900!) Grazie ancora Michele Nista e ricordati che appena rientri in Italia organizziamo una bella serata con i nostri amici lettori. CHIEDO A TUTTI COLORO CHE LO APPREZZANO DI SPENDERE DUE MINUTI A POSTARE UN COMMENTO SUL SUO GRANDE LAVORO CON NOI. Pubblicato da consulenza finanziaria di Mercato Libero a marted=C3=83=C6=92= =C3=86=E2=80=99=C3=83=E2=80=9A=C3=82=C2=AC, aprile 28, 2009 203 commenti Salvarisparmio ha detto... Grnade Michele, ti dobbiamo noi lettori molto . Remigio 28 aprile 2009 18.24 Anonimo ha detto... io sono nuovo del blog e anche della borsa, non ci ho capito molto, ma di u= na cosa sono sicuro:Michele Nista =C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80= =9A=C3=82=C2=A8 un grande 28 aprile 2009 18.27 Andrew234 ha detto... Inizio io: GRAZIE MICHELE PER TUTTO QUELLO CHE HAI FATTO PER NOI!!!non cura= rti di quello che dice qualche imb..... Continua ad aiutarci!! IN MEZZO A QUESTI COMMENTI, VE NE SONO "SOLO" ALTRI 203 E DI ENORME GAUDIO! 28 aprile 2009 18.37 Marco sapa ha detto... Grandissimo Michele Nista, chi critica di solito =C3=83=C6=92=C3=86=E2=80= =99=C3=83=E2=80=9A=C3=82=C2=A8 invidioso oppure non ha capito una mazza di = borsa...seguendoti mi son salvato le chiappe...migliaiai di euro di ringraz= iamneti!! Marco 28 aprile 2009 18.46 Grande Michele !!!!! ciao genio michele nista GUARDATE ORA, PLS, COSA EMAIL AVA, LO STESSO CRIMINALISSIMO, PURE MANDANTE = DI OMICIDI O 'RAFFINATE SUICIDATE", RAZZISTA, NAZISTA, MEGA LAVA CASH MAFIO= SO COME POLITI-C-RIMINALE, PAOLO BARRAI, DOPO CHE MICHELE NISTA NON VOLLE A= VERCI PIU' NULLA A CHE FARE, NELL'AGOSTO 2009, VENENDO A SAPERE CHE LO STES= SO RICICLAVA SOLDI DI COSA NOSTRA, CAMORRA, NDRANGHETA, COME PURE SOLDI RUB= ATI DA LL, LEGA LADRONA E PDL, POPOLO DI LADRONI, UNITI A CASH STRA COLMO D= I CORRUTELA DI PADANAZISTE E BERLUSCONAZISTE FINMECCANICA, ENAV E TECHNOSKY= ! da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Oggi sono andato a pisciare sulla tomba di tuo padre, piu' tardi ci vado = a cagare pure. Ha fatto bene Berlusconi a farlo ammazzare, ahahahah. Grazie= per farti scroccare su euro, gas naturale e caffe robusta. Io sbaglio semp= re nei mercati, ma grazie a te, riesco ancora a sopravvivere, ahahaha". --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com "Presto Berlusconi e il mio Bossi, manderanno sicari mafiosi o dei servizi = segreti, a Londra, a farti sparare, ahahaha. Ti scrocchiamo e poi ti sparia= mo pure, come si fa con un ciupa ciupa usato, ahahah. L'Italia e' nostra, e= ' nazifascista. A morte gli ebrei. A noi!!!" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Speriamo che ti venga una trombosi alla gamba, ho fatto un post di solida= rieta' su di te, per fingermi corretto, in realta', non vedo l'ora che ti a= mmazzano. Voi bastardi ebrei, o amici di ebrei, dovrete tutti crepare soffr= endo" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Ti ho fatto infiltrare da Filati del Piemonte, da Angelo Pegli, da Gianlu= ca Gualandri, da Stelvio Callimaci, sei pieno di mie spie. Io prendo un po'= di prestanome, e ti infiltro. E intanto, faccio passare per mie, idee che = sono tue. E fra poco ti faro' pure sparare a Londra, ahahahah. Crepa bastar= do, chi lavora con gli ebrei, deve bruciare nei forni". --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Stelvio Callimaci sta facendo un ottimo lavoro, mi passa tutti i tuoi inp= uts e io li faccio passare per miei, ahahahahaah; manda inputs, manda, e io= vi faccio i soldi, ahahahah; presto ti spariamo in faccia, Nista comunista= di merda, Berlusconi e Bossi non si criticano, si adorano, ahahahaha; noi = della Lega, presto faremo migliaia di morti" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " bravo ottimi post continua cos=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A= =C3=82=C2=AC.. presto ti spariamo in faccia... Nista, sei il primo della li= sta, la Lega spara, ammazza, non perdona, il mondo e' nostro, della destra.= .. Paolo Barrai ammazza, la Lega ammazza, ahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " sei troppo dolce ti sta forse leccando il culo tua ma-re!!! hahahaha, vai vai.... ma non perdere lucidit=C3=83=C6=92=C3=86=E2=80=99 per i tuoi clienti....att= endono impazienti gli inputs" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " di infiltrati come stelvio e filati ne abbiamo tanti ahahahaah, e presto = ti verremo a trovare a Londra, io e Michele Milla, e come facemmo con Ubald= o Gaggio, ti ammazzeremo, ahaha" ---- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " non correre...la gamba potrebbe non seguirti... Nista, presto saliremo a = Londra e ti spareremo in bocca.... la mia Lega non perdona, la Lega uccide,= ahhaha.. e' vero, abbiamo ammazzato noi Giorgio Panto e Paolo Alberti, per= che' andarono con Prodi, e presto ammazzeremo anche a te, la Lega non perdo= na, la Lega ammazza tantissimo... ahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " credo che stai per finire...ahahahaha.. fra poco ti spariamo in bocca, Ni= sta bastardo, Nista primo della lista, anzi no...abbiamo bisogno dei tuoi a= rticoli da esaltato.. ti diamo ancora 15 giorni e poi ti spariamo in faccia= , la Lega ammazza, Bossi fa ammazzare, prepara il testamento, sei morto, ah= ah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " mi dicono che a londra stanno predisponendo un forno .....e gli manca mat= eriale!!! vi ficchiamo dentro te e William Levi... voglio un nuovo nazismo.= . voglio vedere tutti gli ebrei e chi lavora con gli ebrei, come fai te, br= uciare... evviva il nazismo.. evviva la Lega, che e' il nuovo nazismo, Berl= usconi muove la mafia, noi i nazisti, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " buona trombosi.. Nista ti ammazziamo noi, se vuoi.. crepa presto o noi de= l Pdl e della Lega ti ammazziamo.. come gia' abbiamo fatto con tuo padre.. = Berlusconi e Bossi ammazzano, e presto lo vedrai.. Heil Hitler, Heil Mussol= ini, Heil Bossi, Heil Berlusconi, Heil Barrai, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " ahahahahaha, presto ti spareremo in faccia...Nista sei morto, Nista ti am= mazzeremo, Nista sei condannato a crepare... Nista, divieni Berlusconiano, = come ti volevo fare diventare un anno fa, o ti ammazziamo, Nista morto, aha= ah" 3) da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " grazie per la fantastica azzeccata su dow jones, gas naturale e per il ta= ntissimo resto.. ahahahaha, vamos siamo forti! non mi morire per strada!!! come mi ha detto Don...non mi morire per strada...perche' fra poco salgo io= a Londra, a scaricarti una p38 in bocca... Stefano Bassi de il Grande Bluf= f e io siamo assassini, terroristi neri, e presto ti ammazzeremo, ahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " sempre nemici... ognuno persegue i suoi obbiettivi.... tanto tu sei conda= nnato a morte... Berlusconi e Bossi han gia deciso: Nista come Falcone e Bo= rsellino, Nista sparato in bocca, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " non ti deconcentro, scusa devi preparar i report che cos=C3=83=C6=92=C3=86=E2=80=99=C3=83=E2=80=9A=C3= =82=C2=AC ci dai gli inputs vincentissimi come sempre, scusami... dai impeg= nati, impegnati, che presto io, Berlusconi e Bossi, ti faremo sparare dritt= o in faccia, ahahaha" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " Marina Berlusconi ha gia' messo il pollice verso, Marina Berlusconi ti ha= condannato a morte..ha gia' avvertito la mafia di eseguire, di ammazzarti.= . e se non esegue la mafia, eseguono i servizi segreti di destra, fascisti = come me, della Lega ... Nista sei un morto ormai, ahahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " ahahahah, passa ancora un po' di dritte che qui si fanno soldi a palate .= ..lavora schiavo ... lavora, che fra poco, Berlusconi e Bossi ti fanno spar= are in bocca.. via nostre Mafia e Servizi Segreti.... non criticare mai piu= ' Berlusconi o ti ammazziamo, bastardo.. Berlusconi e Bossi non si critican= o, si adorano.. il problema e' che Marina Berlusconi ha gia' ordinato di am= mazzarti, e quella non perdona, la Lega e' il nuovo nazismo e tappa le bocc= he ammazzando, Nista, ormai sei morto, ahahahhah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " salutami william levi ...lo sento bruciare...come legna sul fuoco....o me= glio ...il suo cadavere puo' essere usato per il sapone, ahahahahah..presto= sara' nuovo nazismo, e chiunque lavora con gli ebrei come fai te... diverr= a' legna per i forni, ahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " fammi qualche articolo come nel passato .....ti prego tantissimo. A natal= e ti regalo un forno crematorio per William... Nista, noi Berlusconiani sia= mo la mafia, e tu sei condannato a morte, cosi' impari a non divenire uno d= ei nostri, ahahahah" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " attento a chi incontri a londra....ahahahaah... dai, sei bravo, azzecchi = sempre, e' vero, voglio scroccarti un po' di piu', prima di ammazzarti... N= ista e Levi nei forni di Auschwitz, si, nei forni di Auschwitz, w la Lega, = w il Nazismo" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " POVERO BASTARDO CHE SI PERMETTE DI ESSERE DI CENTROSINISTRA: PRESTO TI SC= HIACCEREMO, LA LEGA UCCIDE, BERLUSCONI UCCIDE, IO, PAOLO BARRAI, UCCIDO, W = LA LEGA, W IL NAZISMO, W LA MAFIA, E INTANTO TI SCROCCO SEMPRE" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com " MI DICONO CHE DI NOTTE SULLA TOMBA DI TUO PADRE CI VANNO A CAGARE I VERMI= ... E ANCHE CHE PRESTO TI AMMAZZERANNO A LONDRA....... FATTI SCROCCARE IN S= ILENZIO O IO E STEFANO BASSI DE IL GRANDE BLUFF TI FAREMO AMMAZZARE... ANCH= E STEFANO BAGNOLI E' UN ASSASSINO COME NOI... NISTA, LA SENTENZA C'E', PRES= TO TI AMMAZZEREMO, W LA LEGA, W IL NAZISMO, W IL PDL, W LA MAFIA, AHAHA" --- da criminalissima mercatiliberi@gmail.com e criminalissima paolobarrai@gmail.com" sei un bastardo che si permette l'i= mpermettibile: essere di centrosinistra! e questo basta e avanza per essere= sparato in faccia, la Lega uccide, Berlusconi uccide, io, Paolo Barrai, uc= cido, w la Lega, e il Nazismo, w Berlusconi, w la Mafia, a noi, a noi, sei = morto, ahaahaha" From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 09 Jul 2015 14:05:09 -0400 Organization: A noiseless patient Spider Lines: 41 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:05:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17683"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wL/N8SEzCUFqYJ7y9LVHv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:cPWF2pWuAyTcpSfT+FOm/IEgTeY= Xref: mx02.eternal-september.org comp.lang.vhdl:8377 On 7/9/2015 1:58 PM, glen herrmannsfeldt wrote: > fl wrote: >> On Saturday, May 23, 2015 at 8:20:47 PM UTC-7, rickman wrote: > > (snip) >>> I have always found block diagrams to be my friend and to help me >>> understand all the relationships between modules. An FFT is actually >>> easy to implement once you understand how they work. They often need >>> pipelining to make them run fast. I have never found pipelining of a >>> linear flow to be difficult. Do you have feedback paths that make your >>> design more complex? What else are you using other than FFTs? > >> Thanks, Rick. I can imagine it could be more difficult when there is >> feedback for a high speed module. FFT has a simple, regular structure. >> For me, I am still in the phase of FFT. I know FFT and its coding in C, >> even in assembly code. I do not have time to finish a VHDL FFT yet. >> The main difficulties are about the memory addressing, twiddle coef >> selection etc. >> Yes, I need to be patient to work on these interconnect between memory, >> twiddle and multipliers. > > My favorite use for FPGAs is systolic array processors. > > I think you can make a systolic array for FFT, but haven't > actually tried to do it. > > Once you figure it out, they are easy to write and debug. > > -- glen A systolic array is useful when you have a *lot* of work to be done and it can be broken into units that allow the data to flow through the processors. I'm probably not doing justice to the "proper" definition. I think this type of design is not very common and is rather specialized. What applications have you found that utilized systolic processing? -- Rick From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 09 Jul 2015 14:19:53 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:18:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="17683"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+yXv21WMTkjFw/ZfXNpKMc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:qbpCQLX1sVk9BBe1QMpl7XjVI/o= Xref: mx02.eternal-september.org comp.lang.vhdl:8378 On 7/9/2015 1:52 PM, glen herrmannsfeldt wrote: > I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references > many other entities without any problem. But then I wanted > one of those to reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > > I am more used to verilog, but structural VHDL isn't all that > different from structural verilog, if you change a few words. Work is the default working directory of the tools where all the code that is not specifically assigned to a library/package resides. I won't say I am overly familiar with all the details of using libraries. I often just mess with stuff until it works. But I don't recall ever having to add "work" to the name of an entity for the tools to find it. Perhaps you have tweaked something that changed the default? -- Rick From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 09 Jul 2015 14:30:32 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 18:29:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vNpX/XQntixi8hEbktcXn" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:ipXEBjZxxAmhyVfJpCqBw49bnTo= Xref: mx02.eternal-september.org comp.lang.vhdl:8379 On 7/9/2015 2:19 PM, rickman wrote: > On 7/9/2015 1:52 PM, glen herrmannsfeldt wrote: >> I don't understand the use of WORK in VHDL. >> >> I have a large module, well entity in VHDL, that references >> many other entities without any problem. But then I wanted >> one of those to reference an entity, and got errors from Xilinx ISE. >> >> The fix seems to be to put WORK. in front of the entity name. >> >> Am I supposed to put WORK. in front of all the entity refernces? >> >> I am more used to verilog, but structural VHDL isn't all that >> different from structural verilog, if you change a few words. > > Work is the default working directory of the tools where all the code > that is not specifically assigned to a library/package resides. I won't > say I am overly familiar with all the details of using libraries. I > often just mess with stuff until it works. But I don't recall ever > having to add "work" to the name of an entity for the tools to find it. > Perhaps you have tweaked something that changed the default? BTW, is this a Maynard G Krebs thread? WORK!!?? -- Rick From newsfish@newsfish Tue Dec 29 16:43:53 2015 X-Received: by 10.66.121.79 with SMTP id li15mr21239589pab.12.1436466837654; Thu, 09 Jul 2015 11:33:57 -0700 (PDT) X-Received: by 10.50.23.71 with SMTP id k7mr476613igf.6.1436466837620; Thu, 09 Jul 2015 11:33:57 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!qs7no3145889igc.0!news-out.google.com!t2ni5579igk.0!nntp.google.com!qs7no3145879igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 9 Jul 2015 11:33:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> Subject: Re: WORK From: KJ Injection-Date: Thu, 09 Jul 2015 18:33:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8380 On Thursday, July 9, 2015 at 1:52:57 PM UTC-4, glen herrmannsfeldt wrote: > I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references > many other entities without any problem. But then I wanted > one of those to reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > Yes. To instantiate entity xyz directly you would type: My_Thingy : entity work.xyz port map(...); The other way is to define a component in which case you would instantiate the component this way: My_Thingy : xyz port map(...); But creating a component is busy work that can lead to other problems. Better to use the direct entity instantiation as shown in the first example. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: WORK Date: Thu, 9 Jul 2015 20:44:58 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 45 Message-ID: References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8381 KJ wrote: > On Thursday, July 9, 2015 at 1:52:57 PM UTC-4, glen herrmannsfeldt wrote: >> I don't understand the use of WORK in VHDL. >> I have a large module, well entity in VHDL, that references >> many other entities without any problem. But then I wanted >> one of those to reference an entity, and got errors from Xilinx ISE. (snip) >> Am I supposed to put WORK. in front of all the entity refernces? > Yes. To instantiate entity xyz directly you would type: > My_Thingy : entity work.xyz port map(...); > The other way is to define a component in which case you would > instantiate the component this way: > My_Thingy : xyz port map(...); > But creating a component is busy work that can lead to other > problems. Better to use the direct entity instantiation as shown > in the first example. Yes, I first learned component, but quickly found out about entity and is so much easier. (Though I often put in a comment explaining the ports so I don't forget.) It seems to work for the first level without work. but not deeper. The Xilinx explanation compares it to Java's this, which you normally don't need to put in front of every variable and method reference. It sounds like work is supposed to be the default. It seems that Xilinx uses a different parser for Spartan 6, which is part of the explanation for why this recently came up. Can I say: library work; and get around needing it for each one? thanks, -- glen From newsfish@newsfish Tue Dec 29 16:43:53 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 9 Jul 2015 20:49:27 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8382 rickman wrote: (snip, I wrote) >> My favorite use for FPGAs is systolic array processors. >> I think you can make a systolic array for FFT, but haven't >> actually tried to do it. >> Once you figure it out, they are easy to write and debug. (snip) > A systolic array is useful when you have a *lot* of work to be done and > it can be broken into units that allow the data to flow through the > processors. I'm probably not doing justice to the "proper" definition. > I think this type of design is not very common and is rather > specialized. What applications have you found that utilized systolic > processing? I have used it for dynamic programming for DNA and protein sequence comparison. There are nice algorithms for computing alignment scores including insertions and deletions using dynamic programming. (The algorithm used by unix diff was first used for protein sequence comparison, and later for diff.) I believe that convolution and FIR filters also make nice systolic arrays, I am not so sure about IIR, though. -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Thu, 09 Jul 2015 17:44:40 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 9 Jul 2015 21:43:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4747"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18d73/Di++Tmyh/lOkMdEi6" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:tSJPyjoLHdbWUkLr8gOoqiR0s3g= Xref: mx02.eternal-september.org comp.lang.vhdl:8383 On 7/9/2015 4:49 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> My favorite use for FPGAs is systolic array processors. > >>> I think you can make a systolic array for FFT, but haven't >>> actually tried to do it. > >>> Once you figure it out, they are easy to write and debug. > > (snip) >> A systolic array is useful when you have a *lot* of work to be done and >> it can be broken into units that allow the data to flow through the >> processors. I'm probably not doing justice to the "proper" definition. > >> I think this type of design is not very common and is rather >> specialized. What applications have you found that utilized systolic >> processing? > > I have used it for dynamic programming for DNA and protein > sequence comparison. There are nice algorithms for computing > alignment scores including insertions and deletions using > dynamic programming. (The algorithm used by unix diff was first > used for protein sequence comparison, and later for diff.) > > I believe that convolution and FIR filters also make nice systolic > arrays, I am not so sure about IIR, though. Yeah, I work on protein sequence comparison nearly every day.. lol Yes, I'd say that was a rather specialized application. Do they still use FPGAs for that or have they moved on to GPUs? I remember *many* years ago when the buzzword was "workstations". Not sure who it was, but I think someone at NIH was working on providing molecular interaction simulations using 3D joysticks with force feedback. I never heard if they continued the research. So I don't know if they had any problems with computing power or not. I am pretty sure it was not pursued enough to have a general solution and instead only simulated specific molecules that had been entered into the system. This could have used systolic processing at that time, but by now would be pretty easy on a GPU I am sure. -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: What is your VHDL design flow for a complex project? Date: Fri, 10 Jul 2015 00:38:02 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 41 Message-ID: References: <085e33c4-35a9-4061-b11d-a4328cc0737f@googlegroups.com> <93d4165e-5bc0-4a1b-b2f5-ffb49d21dfee@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8384 rickman wrote: (snip, I wrote) >> I have used it for dynamic programming for DNA and protein >> sequence comparison. There are nice algorithms for computing >> alignment scores including insertions and deletions using >> dynamic programming. (The algorithm used by unix diff was first >> used for protein sequence comparison, and later for diff.) >> I believe that convolution and FIR filters also make nice systolic >> arrays, I am not so sure about IIR, though. > Yeah, I work on protein sequence comparison nearly every day.. lol > Yes, I'd say that was a rather specialized application. > Do they still use FPGAs for that or have they moved on to GPUs? For the usual problems, it is fixed point add/subtract with a small number of bits. It is very efficient in an FPGA, and not so good in GPU. Sequencers some years ago could generate 1e9 base/day, and they might be much faster now. Dynamic programming is O(N**2) (which is pretty good when you include insertion and deletion), but that means 2e19 add/subtract per day to compare against one human genome. Eight bits, or maybe only five or six, is enough. But for HMM calculations, floating point is sometimes better. > I remember *many* years ago when the buzzword was "workstations". Not > sure who it was, but I think someone at NIH was working on providing > molecular interaction simulations using 3D joysticks with force > feedback. I never heard if they continued the research. So I don't > know if they had any problems with computing power or not. I am pretty > sure it was not pursued enough to have a general solution and instead > only simulated specific molecules that had been entered into the system. > This could have used systolic processing at that time, but by now > would be pretty easy on a GPU I am sure. -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: WORK Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 10 Jul 2015 10:57:07 GMT Lines: 80 Message-ID: <559fa503$0$2754$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: c56e0cd4.news.astraweb.com X-Trace: DXC=>P>[Q?5kHNhJRZZkg^aP1jL?0kYOcDh@jZD3?OaX:Skmh:BbU8OZ3Am I don't understand the use of WORK in VHDL. > > I have a large module, well entity in VHDL, that references many other > entities without any problem. But then I wanted one of those to > reference an entity, and got errors from Xilinx ISE. > > The fix seems to be to put WORK. in front of the entity name. > > Am I supposed to put WORK. in front of all the entity refernces? > > I am more used to verilog, but structural VHDL isn't all that different > from structural verilog, if you change a few words. >From a 2002 comp.lang.vhdl post of mine ... [In an entity instantiation] entity 'E' will need to be qualified in some way. I know of three ways: 1. library lib; -- not needed if 'lib' is work use lib.E; ... label : entity E generic map ( ... 2. library lib; -- not needed if 'lib' is work use lib.all; -- 'all' picks up E (and possibly other stuff) ... label : entity E generic map ( ... 3. library lib; -- not needed if 'lib' is work ... label : entity lib.E generic map ( ... All three methods should work in any 1993 (or later) compliant VHDL compiler. Method 3 is by far the most popular. Also, most designers only use one library, so the entity instantiation will typically look like: label : entity work.E generic map ( ... It's also possible to specify an architecture, e.g. label : entity lib.E(A) generic map ( ... would select architecture "A" of entity "E" in the library "lib". This is handy in testbenches if you want to instantiate two different architectures for the same entity, without needing to use a configuration. I rarely use component instantiations, but when I do, I include the (optional) component keyword to make them stand out in my source code, e.g. label : component E generic map ( ... Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: WORK Newsgroups: comp.lang.vhdl References: <559fa503$0$2754$c3e8da3$76491128@news.astraweb.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 10 Jul 2015 11:06:43 GMT Lines: 83 Message-ID: <559fa743$0$2754$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 67c9fe51.news.astraweb.com X-Trace: DXC==RUHg@438ceF1iA^=`ZUjbL?0kYOcDh@jZD3?OaX:Skmh:BbU8OZ3Am On Thu, 09 Jul 2015 17:52:53 +0000, glen herrmannsfeldt wrote: > >> I don't understand the use of WORK in VHDL. >> >> I have a large module, well entity in VHDL, that references many other >> entities without any problem. But then I wanted one of those to >> reference an entity, and got errors from Xilinx ISE. >> >> The fix seems to be to put WORK. in front of the entity name. >> >> Am I supposed to put WORK. in front of all the entity refernces? >> >> I am more used to verilog, but structural VHDL isn't all that different >> from structural verilog, if you change a few words. > > > > From a 2002 comp.lang.vhdl post of mine ... > > > [In an entity instantiation] entity 'E' will need to be qualified in > some way. I know of three ways: > > 1. > library lib; -- not needed if 'lib' is work use lib.E; > ... > label : entity E > generic map ( > ... > > 2. > library lib; -- not needed if 'lib' is work use lib.all; -- 'all' > picks up E (and possibly other stuff) > ... > label : entity E > generic map ( > ... > > 3. > library lib; -- not needed if 'lib' is work ... > label : entity lib.E > generic map ( > ... > > > All three methods should work in any 1993 (or later) compliant VHDL > compiler. Method 3 is by far the most popular. Also, most designers > only use one library, so the entity instantiation will typically look > like: > > label : entity work.E > generic map ( > ... > > > It's also possible to specify an architecture, e.g. > > label : entity lib.E(A) > generic map ( > ... > > would select architecture "A" of entity "E" in the library "lib". This > is handy in testbenches if you want to instantiate two different > architectures for the same entity, without needing to use a > configuration. > > > I rarely use component instantiations, but when I do, I include the > (optional) component keyword to make them stand out in my source code, > e.g. > > label : component E > generic map ( > ... > Pan's word wrap strikes again. Those use clauses were meant to be on new lines. Allan From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.66.237.2 with SMTP id uy2mr27591538pac.11.1436542717942; Fri, 10 Jul 2015 08:38:37 -0700 (PDT) X-Received: by 10.50.23.71 with SMTP id k7mr66384igf.6.1436542717907; Fri, 10 Jul 2015 08:38:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!qs7no3497521igc.0!news-out.google.com!a16ni14013ign.0!nntp.google.com!i4no649099ige.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jul 2015 08:38:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.72.186; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.72.186 References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: WORK From: Jim Lewis Injection-Date: Fri, 10 Jul 2015 15:38:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 Xref: mx02.eternal-september.org comp.lang.vhdl:8387 One motivation to use component instantiation is they can be configured with a configuration declaration. In a testbench, this allows you to remove components from a simulation when they are not in use, and hence, do core level simulations using a chip level testbench. My goal is the reduction of the number of unique testbench frameworks I need to support. It is planned to revise configurations to allow the architecture of direct entity instances (the one you prefer without component declarations) to be configured, but it will take time to get it into the standard and then more time to get it in a simulator. Jim From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.182.24.70 with SMTP id s6mr27480334obf.42.1436551658192; Fri, 10 Jul 2015 11:07:38 -0700 (PDT) X-Received: by 10.140.101.22 with SMTP id t22mr328398qge.32.1436551658058; Fri, 10 Jul 2015 11:07:38 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no3550608igc.0!news-out.google.com!w15ni32387qge.0!nntp.google.com!z61no154512qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 10 Jul 2015 11:07:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.173.36 References: <60e03e31-1ef5-45d9-a327-7e89f8b884ca@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: WORK From: Andy Injection-Date: Fri, 10 Jul 2015 18:07:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8388 There are additional options for "configuring" entities without using compo= nents using 93 - 2008 versions of VHDL. They all require that the entity in= stantiation in the design code NOT specify the architecture (optional, in p= arentheses after the entity name). When elaborated, if no architecture is specified in the entity instantiatio= n, the most recently analyzed architecture for the entity will be used. Thu= s, if for simulation, you analyze (compiled) a new architecture for an enti= ty, AFTER the original architecture is analyzed, the new architecture will = be used for the entity in the simulation.=20 Such an architecture may be completely different (empty/benign/broken, gate= level, behavioral, etc.) than the original architecture. Such an architecture can also re-instantiate the entity with the original a= rchitecture by specifying the original architecture with its entity instant= iation. I call this a "wrapper" architecture. A wrapper architecture can ef= fectively alter the generic map, assert conditions on intefaces and even mo= dify interface behavior (such as forcing output data to X when the valid si= gnal is not asserted). A wrapper architecture can also conditionally do the= se things based on a generic value, using if-generate statements as needed. In practice such "configurations" are managed through compile scripts rathe= r than a configuration unit. Sometimes it is easier to just bite the bullet= and use configurations & components, but for limited cases, it is easier t= o manage the compile scripts. Or, just wait until vhdl 201x. BTW, "work" provides a library-name-independent method of specifying that a= needed resource can be found in the same library which contains the refere= ncing unit. This provides independence from the name of the library. This a= llows, among other ways, the same library code to be compiled into differen= t libraries, with different names, and referenced separately for different/= duplicate purposes. Imagine a design that uses a package do declare a bunch= of "global" signals, but you want to run a simulation that includes more t= han one copy of the design, but those global signals can't be shared betwee= n both copies. Compile one copy of the design into one library, and another= copy into another library, and their "global" signals will be local to eac= h design copy. Andy From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Maurice SAAB Newsgroups: comp.lang.vhdl Subject: ROM, how? Date: Sat, 11 Jul 2015 13:27:16 +0300 Organization: Aioe.org NNTP Server Lines: 5 Message-ID: NNTP-Posting-Host: HIL1RaQAV9ekVSPTby4cHg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 X-Notice: Filtered by postfilter v. 0.8.2 X-Mozilla-News-Host: news://nntp.aioe.org:119 Xref: mx02.eternal-september.org comp.lang.vhdl:8389 Hello: how to instantiate a ROM with its content in a test-bench? thanks From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: ROM, how? Date: Sat, 11 Jul 2015 23:50:29 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 36 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8390 Maurice SAAB wrote: > how to instantiate a ROM with its content in a test-bench? I don't know about test bench, but I do ROM with a constant array: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type entity i3601 is port ( Q : out std_logic_vector(3 downto 0); A : in std_logic_vector(7 downto 0); CS1, CS2 : in std_logic); end entity i3601; architecture i3601 of i3601 is type ROM is array(0 to 255) of std_logic_vector(3 downto 0); constant ROM1: ROM := ( X"1", X"2", X"3", OTHERS => X"0"); begin Q <= ROM1(to_integer(unsigned(A))) when (CS1 or CS2)='0' else X"F"; end architecture i3601; Having the OTHERS => X"0" at the end, even if you fill the whole array, allows the last element to have a trailing comma. C allows array initialization to have a trailing comma, but not VDHL. For some reason that I don't know, you have to use type. Just declaring a constant of the appropriate type doesn't work. -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: IN and OUT of the same entity? Date: Sat, 11 Jul 2015 23:58:34 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 22 Message-ID: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8391 I have a design that gets errors from Xilinx ISE, which looks fine to me. It connects IN and OUT ports together: signal y105: std_logic; a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, y105, open, OUTON, vcc, OUTON, vcc, y108e); The first y105 is an IN to N109, the second is OUT. ISE says: "Line 531: Formal has no actual or default value." and is the port of the first y105. There is a similar error when another instantiation also uses IN and OUT ports, but not exactly the same way. It seems to me a strange restriction. Is it supposed to do that? -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sat, 11 Jul 2015 20:23:15 -0400 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 00:21:49 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="23812"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190dWyaUUSIW14HpKtQbapp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:CkSHNfdJGjJ/aXZgVPABeExLaIU= Xref: mx02.eternal-september.org comp.lang.vhdl:8392 On 7/11/2015 7:58 PM, glen herrmannsfeldt wrote: > I have a design that gets errors from Xilinx ISE, which looks > fine to me. It connects IN and OUT ports together: > > signal y105: std_logic; > > a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, > y105, open, OUTON, vcc, OUTON, vcc, y108e); > > > The first y105 is an IN to N109, the second is OUT. > > ISE says: "Line 531: Formal has no actual or default value." > > and is the port of the first y105. > > There is a similar error when another instantiation also uses > IN and OUT ports, but not exactly the same way. > > It seems to me a strange restriction. Is it supposed to do that? I think that depends on what you have inside the entity. Do you have the same connection inside? lol just kidding I'm not clear on what you are coding. Is this an entity declaration? I see the entity keyword, but this is not the syntax for an entity declaration. Is this something I missed in VHDL 2008? -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 03:30:14 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 21 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8393 glen herrmannsfeldt wrote: > I have a design that gets errors from Xilinx ISE, which looks > fine to me. It connects IN and OUT ports together: > a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, > y105, open, OUTON, vcc, OUTON, vcc, y108e); > The first y105 is an IN to N109, the second is OUT. > ISE says: "Line 531: Formal has no actual or default value." OK, maybe this was obvious to everyone else, but the file is pretty big and I didn't notice. I forgot to say "port map". I have no idea what it thinks it does, but it complains about the third signal, j1. No obvious message like "you idiot, you forgot to say PORT MAP:. thanks, all. -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 02:03:03 -0400 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 06:01:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="4630"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Ev/ApYVvX/qzfprZaO6K5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:mMzj4RqPRzECxKprJLk0kAmLXYo= Xref: mx02.eternal-september.org comp.lang.vhdl:8394 On 7/11/2015 11:30 PM, glen herrmannsfeldt wrote: > glen herrmannsfeldt wrote: >> I have a design that gets errors from Xilinx ISE, which looks >> fine to me. It connects IN and OUT ports together: > >> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >> y105, open, OUTON, vcc, OUTON, vcc, y108e); > >> The first y105 is an IN to N109, the second is OUT. > >> ISE says: "Line 531: Formal has no actual or default value." > > OK, maybe this was obvious to everyone else, but the file is > pretty big and I didn't notice. I forgot to say "port map". > > I have no idea what it thinks it does, but it complains about > the third signal, j1. No obvious message like "you idiot, you forgot > to say PORT MAP:. > > thanks, all. Lol, I thought it was messed up but I didn't want to assume I was right and you were wrong. It has been well over a year since I've written any VHDL and maybe a lot longer than that. Glad you figured it out. Compilers can be pretty retarded about reporting what is really wrong. I'm still not clear on the entity part. The keyword "entity" needs to be removed too, right? You are using positional association in your association list. I always use named association. It is more to type, but prevents some types of hard to find mistakes and might help the tools report better error messages. It is not hard to use an editor macro to create the named association list for a component instantiation and some tools will create it for you. I make it from the port declaration of the entity. That is one of the "issues" of VHDL... the excessive typing.... or do I want to say incessant as in, "I can't take the incessant beating of the jungle drums!" or in this case, "I can't take the incessant typing of the Smith Corona!" -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 09:17:41 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 59 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8395 rickman wrote: (snip, I wrote) >>> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >>> y105, open, OUTON, vcc, OUTON, vcc, y108e); (snip, then I wrote) >> OK, maybe this was obvious to everyone else, but the file is >> pretty big and I didn't notice. I forgot to say "port map". (snip) > Lol, I thought it was messed up but I didn't want to assume I was right > and you were wrong. It has been well over a year since I've written any > VHDL and maybe a lot longer than that. Glad you figured it out. > Compilers can be pretty retarded about reporting what is really wrong. I am more used to verilog, but if I put the VHDL words in the right place, it mostly works. I mostly write structural verilog, and so now structural VHDL. > I'm still not clear on the entity part. The keyword "entity" > needs to be removed too, right? No, the word entity is right. I didn't completely figure it out, but there is component and entity, where entity has the keyword. > You are using positional association in your association list. I always > use named association. It is more to type, but prevents some types of > hard to find mistakes and might help the tools report better error > messages. It is not hard to use an editor macro to create the named > association list for a component instantiation and some tools will > create it for you. I make it from the port declaration of the entity. > That is one of the "issues" of VHDL... the excessive typing.... or do I > want to say incessant as in, "I can't take the incessant beating of the > jungle drums!" or in this case, "I can't take the incessant typing of > the Smith Corona!" The design is based on a TTL design, so the entities are TTL ICs. I thought about the other way, but in either case I need to go carefully through the design and verify the ports. There are a lot of 74109 and 74161, so once I figure out the order for each, I just have to verify them. The signal names are the original names, which often don't mean much to me. Sometiems I have to make a name, mostly for TTL gates. (I use entity for everything except simple gates, and the VHDL equivalent of continuous assignment for gates.) In most cases, I put the output ports first, then the input ports. The 74109 is a dual FF, so it is out then in for the first, and out then in for the second. -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 13:42:59 -0400 Organization: A noiseless patient Spider Lines: 94 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 12 Jul 2015 17:41:33 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="8364"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX189PveUQqkZ1FUNxVFWr4Pr" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:iRHHQk0AVAZVnibCMBZlToelzPc= Xref: mx02.eternal-september.org comp.lang.vhdl:8396 On 7/12/2015 5:17 AM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) > >>>> a105: entity work.N109(COLL, open, y105, vcc, xLDRESET, vcc, xTCLK, >>>> y105, open, OUTON, vcc, OUTON, vcc, y108e); > > (snip, then I wrote) >>> OK, maybe this was obvious to everyone else, but the file is >>> pretty big and I didn't notice. I forgot to say "port map". > > (snip) > >> Lol, I thought it was messed up but I didn't want to assume I was right >> and you were wrong. It has been well over a year since I've written any >> VHDL and maybe a lot longer than that. Glad you figured it out. >> Compilers can be pretty retarded about reporting what is really wrong. > > I am more used to verilog, but if I put the VHDL words in the > right place, it mostly works. > > I mostly write structural verilog, and so now structural VHDL. So why are you using VHDL instead of Verilog? I've wanted to learn Verilog for some time now, but when I am doing paid work I stick to what I know. I haven't done a "for fun" HDL project in a while so I haven't done much with Verilog. >> I'm still not clear on the entity part. The keyword "entity" >> needs to be removed too, right? > > No, the word entity is right. > > I didn't completely figure it out, but there is component and > entity, where entity has the keyword. "Entity" is used to define the parameter list of an entity. It seems I was unaware that it can also be used in a component instantiation when you wish to skip having a component declaration. A component declaration is like a function prototype in C, it defines the interface for local use. By adding the keyword "entity" to the component instantiation it eliminates the need for the component declaration. However, this is now called an "entity" instantiation and will not work with configurations... very complex... >> You are using positional association in your association list. I always >> use named association. It is more to type, but prevents some types of >> hard to find mistakes and might help the tools report better error >> messages. It is not hard to use an editor macro to create the named >> association list for a component instantiation and some tools will >> create it for you. I make it from the port declaration of the entity. >> That is one of the "issues" of VHDL... the excessive typing.... or do I >> want to say incessant as in, "I can't take the incessant beating of the >> jungle drums!" or in this case, "I can't take the incessant typing of >> the Smith Corona!" > > The design is based on a TTL design, so the entities are TTL ICs. Should I assume this means the parameters are in pin number order? Sounds like spice, but that doesn't make it good. You can still use named association. > I thought about the other way, but in either case I need to go > carefully through the design and verify the ports. There are a > lot of 74109 and 74161, so once I figure out the order for each, > I just have to verify them. The signal names are the original > names, which often don't mean much to me. Sometiems I have to > make a name, mostly for TTL gates. (I use entity for everything > except simple gates, and the VHDL equivalent of continuous > assignment for gates.) > > In most cases, I put the output ports first, then the input ports. > The 74109 is a dual FF, so it is out then in for the first, > and out then in for the second. If you use pin number based names for the TTL entities, you could use named association which would make the verification trivial, well, assuming you are copying this from a pin number oriented list of some sort. Otherwise, why use TTL devices? P01 => ralph, P02 => betty, ... You may be unpleasantly surprised at how easy it is to make a mistake using positional association. -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: IN and OUT of the same entity? Date: Sun, 12 Jul 2015 20:11:57 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 83 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8397 rickman wrote: (snip, I wrote) >> I am more used to verilog, but if I put the VHDL words in the >> right place, it mostly works. >> I mostly write structural verilog, and so now structural VHDL. > So why are you using VHDL instead of Verilog? I've wanted to learn > Verilog for some time now, but when I am doing paid work I stick to what > I know. I haven't done a "for fun" HDL project in a while so I haven't > done much with Verilog. It wasn't my choice. >>> I'm still not clear on the entity part. The keyword "entity" >>> needs to be removed too, right? >> No, the word entity is right. >> I didn't completely figure it out, but there is component and >> entity, where entity has the keyword. > "Entity" is used to define the parameter list of an entity. It seems I > was unaware that it can also be used in a component instantiation when > you wish to skip having a component declaration. A component > declaration is like a function prototype in C, it defines the interface > for local use. By adding the keyword "entity" to the component > instantiation it eliminates the need for the component declaration. > However, this is now called an "entity" instantiation and will not work > with configurations... very complex... I think that is the way I understand it. Since verilog doesn't require the declaration, I didn't think that VHDL should. Then I found out about entity and used that. I still have comments explaining the order, the way I want to read them. >>> You are using positional association in your association list. I always >>> use named association. It is more to type, but prevents some types of >>> hard to find mistakes and might help the tools report better error >>> messages. (snip) >> The design is based on a TTL design, so the entities are TTL ICs. > Should I assume this means the parameters are in pin number order? > Sounds like spice, but that doesn't make it good. You can still use > named association. No, they aren't in that order on the original. I choose the order that I like. (snip) >> In most cases, I put the output ports first, then the input ports. >> The 74109 is a dual FF, so it is out then in for the first, >> and out then in for the second. > If you use pin number based names for the TTL entities, you could use > named association which would make the verification trivial, well, > assuming you are copying this from a pin number oriented list of some > sort. Otherwise, why use TTL devices? > P01 => ralph, > P02 => betty, > ... > You may be unpleasantly surprised at how easy it is to make a mistake > using positional association. I have been doing Fortran and C programming for years, and I know that it can be a problem. But we live with it in those cases. (Fortran now allows for names, but most don't use them. But it didn't when I first started.) -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.50.25.233 with SMTP id f9mr13690665igg.8.1436737303229; Sun, 12 Jul 2015 14:41:43 -0700 (PDT) X-Received: by 10.50.62.10 with SMTP id u10mr1460igr.12.1436737303207; Sun, 12 Jul 2015 14:41:43 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no4370568igc.0!news-out.google.com!t2ni8559igk.0!nntp.google.com!qs7no4370563igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Jul 2015 14:41:42 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.5.154.164; posting-account=8oCTNQoAAACLdX6nA43RerI2nCrfLpJE NNTP-Posting-Host: 185.5.154.164 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <898bd013-12a3-447e-89c5-e61e79bb245b@googlegroups.com> Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: ABFAROUK Injection-Date: Sun, 12 Jul 2015 21:41:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8398 Instantiating a Verilog Module in a VHDL Design Unit In a mixed language design, you can instantiate a Verilog module in a VHDL design unit. To Instantiate a Verilog Module in a VHDL Design Unit Declare a VHDL component with the same name as the Verilog module (respecting case sensitivity) that you want to instantiate. For example, COMPONENT FD PORT ( Q : out STD_ULOGIC; D : in STD_ULOGIC; C : in STD_ULOGIC ); END COMPONENT; Use named association to instantiate the Verilog module. For example, UUT : FD PORT MAP( Q => O, D => I, C => CLK); Since Verilog is case sensitive, named associations and the local port names that you use in the component declaration must match the case of the corresponding Verilog port names. On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > QS: If the answer to the above question is yes, how to achieve this? > > Thanks in advance > > JO From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.66.149.67 with SMTP id ty3mr17460198pab.24.1436738477614; Sun, 12 Jul 2015 15:01:17 -0700 (PDT) X-Received: by 10.140.94.166 with SMTP id g35mr439433qge.1.1436738477375; Sun, 12 Jul 2015 15:01:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!qs7no4375949igc.0!news-out.google.com!w15ni32550qge.0!nntp.google.com!e109no491964qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 12 Jul 2015 15:01:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.216.14.34; posting-account=8oCTNQoAAACLdX6nA43RerI2nCrfLpJE NNTP-Posting-Host: 37.216.14.34 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: How to instantiate a verilog block inside a VHDL entity? From: ABFAROUK Injection-Date: Sun, 12 Jul 2015 22:01:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8399 and on the conterary: Instantiating a VHDL Module in a Verilog Design Unit In a mixed language design, you can instantiate a VHDL module in a Vesign design unit. To Instantiate a VHDL Module in a Verilog Design Unit Instantiate the VHDL entity as if it were a Verilog module. For example, module testbench ; wire in, clk; wire out; FD FD1( .Q(Q_OUT), .C(CLK); .D(A); ); On Monday, February 17, 2014 at 12:03:27 PM UTC+3, thunder wrote: > Hello > > > My design consists of VHDL blocks. Now i need to instantiate a verilog block inside my VHDL block. > > QS: Is it possible to instantiate a verilog block inside a VHDL block? > QS: If the answer to the above question is yes, how to achieve this? > > Thanks in advance > > JO From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.182.219.225 with SMTP id pr1mr46661117obc.23.1436820199145; Mon, 13 Jul 2015 13:43:19 -0700 (PDT) X-Received: by 10.140.85.11 with SMTP id m11mr497451qgd.29.1436820199118; Mon, 13 Jul 2015 13:43:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!pg9no429180igb.0!news-out.google.com!4ni80201qgh.1!nntp.google.com!z61no744888qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 13 Jul 2015 13:43:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=181.168.151.94; posting-account=sYkI-woAAABUpyXM6sTHXu9B9DxljKdx NNTP-Posting-Host: 181.168.151.94 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: Leonardo Capossio Injection-Date: Mon, 13 Jul 2015 20:43:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 22 Xref: mx02.eternal-september.org comp.lang.vhdl:8400 On Tuesday, July 7, 2015 at 1:17:00 PM UTC-3, HT-Lab wrote: > On 07/07/2015 15:50, Leonardo Capossio wrote: > > Hello, I wonder if anyone knows an open-source processor or a generic p= rogram that will generate a register map for a given embedded processor (Z8= 0-copy or OpenRisc or similar) and architecture in both VHDL and C (header = files or library files with addresses) ? > > >=20 > Not 100% sure what you are after but if you want to generate RTL and=20 > associated c files from some register specifications then have a look at= =20 > IDesignSpec, you can download a free version from cnet, >=20 > http://download.cnet.com/IDesignSpec-for-Word-2007-2010/3000-20418_4-7572= 8342.html >=20 > There might be later versions available on the Agnisys website, >=20 > Good luck, > Hans > www.ht-lab.com Thanks, I was looking for something like this. From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Tobias Baumann Newsgroups: comp.lang.vhdl Subject: Re: Register map auto-generation Date: Tue, 14 Jul 2015 10:26:38 +0200 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 14 Jul 2015 08:23:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f6d85d2002bb0fd91efb8c1e7e8d917a"; logging-data="26931"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1++gA9CXgyIWb9bnYJwwTPQ" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.0.1 In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Cancel-Lock: sha1:Pq6Vx0YXS+5GN9rdsBn/THHM8KM= Xref: mx02.eternal-september.org comp.lang.vhdl:8401 Am 07.07.2015 um 16:50 schrieb Leonardo Capossio: > Hello, I wonder if anyone knows an open-source processor or a generic program that will generate a register map for a given embedded processor (Z80-copy or OpenRisc or similar) and architecture in both VHDL and C (header files or library files with addresses) ? > Hi, here we have the same problem, but no tool satisfied our needs. So we designed something own on MySQL and PHP base, which can be imported directly into Excel Sheets via "MySQL for Excel". Redards, Tobias From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.129.81.201 with SMTP id f192mr37522415ywb.37.1437467539364; Tue, 21 Jul 2015 01:32:19 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr238255igx.15.1437467539335; Tue, 21 Jul 2015 01:32:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no2355424qge.0!news-out.google.com!a16ni24133ign.0!nntp.google.com!pg9no2655808igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 01:32:18 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Subject: convert from verilog to vhdl From: Mat18111992 Injection-Date: Tue, 21 Jul 2015 08:32:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 78 Xref: mx02.eternal-september.org comp.lang.vhdl:8402 Hello everyone. I had a code for fixed point division by Verilog. I tried to rewrite it with VHDL but not successfull. Can somebody help me? Thanks so much. module division #( //Parameterized values parameter Q = 4, // number of fraction bits parameter N = 8 ) ( input [N-1:0] i_dividend, input [N-1:0] i_divisor, input i_start, input i_clk, output [N-1:0] o_quotient_out, output o_complete, output o_overflow ); reg [2*N+Q-3:0] reg_working_quotient;// Our working copy of the quotient reg [N-1:0] reg_quotient; // Final quotient reg [N-2+Q:0] reg_working_dividend;// Working copy of the dividend reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor reg [$clog2(N-1+Q):0] reg_count; reg reg_done; // Computation completed flag reg reg_sign; // The quotient's sign bit reg reg_overflow; // Overflow flag initial reg_done = 1'b1; initial reg_overflow = 1'b0; initial reg_sign = 1'b0; initial reg_working_quotient = 0; initial reg_quotient = 0; initial reg_working_dividend = 0; initial reg_working_divisor = 0; initial reg_count = 0; assign o_quotient_out[N-2:0] = reg_quotient[N-2:0];//division results assign o_quotient_out[N-1] = reg_sign; //The sign of the quotient assign o_complete = reg_done; assign o_overflow = reg_overflow; always @( posedge i_clk ) begin if( reg_done && i_start ) begin //This is our startup condition reg_done<=1'b0; reg_count<=N+Q-1; reg_working_quotient<=0; reg_working_dividend<=0; reg_working_divisor<=0; reg_overflow <= (i_divisor[N-2:0])?1'b0:1'b1;// check divisor =0 or !=0 reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; end else if(!reg_done) begin reg_working_divisor <= reg_working_divisor >> 1; if(reg_working_dividend >= reg_working_divisor) begin reg_working_quotient[reg_count<=1'b1; reg_working_dividend <= reg_working_dividend - reg_working_divisor; end if(!(reg_count | 0)) begin //count = 0 reg_done<=1'b1; reg_quotient <= reg_working_quotient; reg_overflow <= (reg_working_quotient[2*N+Q-3:N]) ? 1'b1 : 1'b0; end else reg_count <= reg_count - 1; end end endmodule From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.66.199.71 with SMTP id ji7mr38014242pac.23.1437476700004; Tue, 21 Jul 2015 04:05:00 -0700 (PDT) X-Received: by 10.140.102.172 with SMTP id w41mr516252qge.40.1437476699952; Tue, 21 Jul 2015 04:04:59 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!newsfeed.fsmpi.rwth-aachen.de!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!209.85.213.215.MISMATCH!pg9no2693427igb.0!news-out.google.com!b31ni277qge.0!nntp.google.com!69no1015660qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 04:04:59 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: convert from verilog to vhdl From: Thomas Stanka Injection-Date: Tue, 21 Jul 2015 11:04:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8403 Am Dienstag, 21. Juli 2015 10:32:22 UTC+2 schrieb Mat18111992: > Hello everyone. I had a code for fixed point division by Verilog. I tried to rewrite it with VHDL but not successfull. Can somebody help me? Thanks so much. Are you looking for someone to write the same code in VHDL? Than it helps to write something about the amount of money you like to spend. If you like to have free help, you might get more information when asking specific questions. Maybe add your VHDL code as well and present the points where you had trouble. Or start with concrete points you need help with. Quick and dirty: Open Synthesis tool, read verilog, perform synthesis and write out vhdl. regards, Thomas From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.52.189.7 with SMTP id ge7mr10261650vdc.6.1437479633368; Tue, 21 Jul 2015 04:53:53 -0700 (PDT) X-Received: by 10.50.138.70 with SMTP id qo6mr259397igb.5.1437479633334; Tue, 21 Jul 2015 04:53:53 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z61no2386924qge.0!news-out.google.com!t2ni17228igk.0!nntp.google.com!pg9no2704979igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 04:53:52 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> Subject: Re: convert from verilog to vhdl From: Mat18111992 Injection-Date: Tue, 21 Jul 2015 11:53:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4922 X-Received-Body-CRC: 987902038 Xref: mx02.eternal-september.org comp.lang.vhdl:8404 Thanks Thomas. Here are VHDL code and testbench of mine. When I run simulation, I get an error :"Fatal: (vsim-3420) Array lengths do not match. Left is 11 (10 downto 0). Right is 18 (17 downto 0)." Can you give me some indication? Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --use ieee.math_real.all; entity division_m is generic( INPUT_WIDTH : integer :=8; FRAC : integer :=4); port ( clk : in std_logic; reset : in std_logic; dividend : in signed(INPUT_WIDTH-1 downto 0); divisor : in signed(INPUT_WIDTH-1 downto 0); quotient : out signed(INPUT_WIDTH-1 downto 0) --overflow : out std_logic ) ; end entity ; -- division_m architecture behavior of division_m is begin divider : process( clk, reset ) variable dividend_reg : signed(INPUT_WIDTH+FRAC-2 downto 0); variable divisor_reg : signed(2*INPUT_WIDTH+FRAC-3 downto 0); variable quotient_reg : signed(2*INPUT_WIDTH+FRAC-3 downto 0); begin if rising_edge(clk) then if reset = '1' then quotient <= (others => '0'); else dividend_reg := dividend(INPUT_WIDTH-2 downto 0)&(FRAC-1 downto 0 =>'0'); divisor_reg := divisor(INPUT_WIDTH-2 downto 0)&(INPUT_WIDTH+FRAC-2 downto 0 => '0'); for i in INPUT_WIDTH+FRAC-1 downto 0 loop divisor_reg := divisor_reg sll 1; if (dividend_reg >= divisor_reg) then quotient_reg(i) := '1'; dividend_reg := dividend_reg - divisor_reg; else quotient_reg(i) := '0'; end if ; end loop ; quotient(INPUT_WIDTH-1) <= dividend(INPUT_WIDTH-1) xor divisor(INPUT_WIDTH-1); quotient(INPUT_WIDTH-2 downto 0) <= quotient_reg(INPUT_WIDTH-2 downto 0); end if ; end if ; end process ; -- divider end architecture ; -- behavior Testbench: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division_m_tb is end division_m_tb; architecture behavioral of division_m_tb is component division_m generic ( INPUT_WIDTH : integer; FRAC : integer); port ( clk : in std_logic; reset : in std_logic; dividend : in signed(INPUT_WIDTH-1 downto 0); divisor : in signed(INPUT_WIDTH-1 downto 0); quotient : out signed(INPUT_WIDTH-1 downto 0)); end component; -- component generics constant INPUT_WIDTH : integer := 8; constant FRAC : integer := 4; -- component ports signal reset : std_logic; signal dividend : signed(INPUT_WIDTH-1 downto 0); signal divisor : signed(INPUT_WIDTH-1 downto 0); signal quotient : signed(INPUT_WIDTH-1 downto 0); -- clock signal clk : std_logic := '1'; begin -- behavioral -- component instantiation DUT : division_m generic map ( INPUT_WIDTH => INPUT_WIDTH, FRAC => FRAC) port map ( clk => clk, reset => reset, dividend => dividend, divisor => divisor, quotient => quotient); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin --signal assignments reset <= '1'; --data_in <= (others => '0'); wait for 20 ns; wait until rising_edge(clk); reset <= '0'; dividend <= "01110000"; --7 divisor <= "00100000"; --2 wait until rising_edge(clk); dividend <= "01001000"; --4,5 divisor <= "00100000"; --2 wait until rising_edge(clk); dividend <= "01011000"; --5,5 divisor <= "00101100"; --2,75 wait until rising_edge(clk); dividend <= "01101110"; --6,875 divisor <= "00110000"; --3 --wait until rising_edge(clk); --data_in <= (others => '0'); wait; end process WaveGen_Proc; end behavioral; From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.13.200.67 with SMTP id k64mr38041124ywd.54.1437487586841; Tue, 21 Jul 2015 07:06:26 -0700 (PDT) X-Received: by 10.140.91.182 with SMTP id z51mr159472qgd.5.1437487586817; Tue, 21 Jul 2015 07:06:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z61no2408353qge.0!news-out.google.com!4ni81702qgh.1!nntp.google.com!z61no2408348qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 21 Jul 2015 07:06:26 -0700 (PDT) In-Reply-To: <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> <76c0f83e-61a9-4c65-9a06-99cd42ab6664@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: convert from verilog to vhdl From: Thomas Stanka Injection-Date: Tue, 21 Jul 2015 14:06:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8405 Am Dienstag, 21. Juli 2015 13:53:56 UTC+2 schrieb Mat18111992: > Thanks Thomas. > Here are VHDL code and testbench of mine. When I run simulation, I get an error :"Fatal: (vsim-3420) Array lengths do not match. Left is 11 (10 downto 0). Right is 18 (17 downto 0)." Can you give me some indication? You missed to post the line number for that error. Open editor go to that line number. You will see there something like Left <= Right ( might be ":=" for variables insterad of "<=") with Left beeing vector of 11 bit and right of 18 bit width. This is impossible in VHDL (and common mistake). In your code Divisor and Quotient are good candidates for 18 bit width. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.182.240.233 with SMTP id wd9mr1516878obc.45.1437555768202; Wed, 22 Jul 2015 02:02:48 -0700 (PDT) X-Received: by 10.50.50.228 with SMTP id f4mr1220igo.0.1437555768168; Wed, 22 Jul 2015 02:02:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no1234796igg.0!news-out.google.com!a16ni25097ign.0!nntp.google.com!pg9no2976162igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 02:02:47 -0700 (PDT) In-Reply-To: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=118.70.129.184; posting-account=2xiWIAoAAAARmmv1zwxT-I9-ZqoxLA0D NNTP-Posting-Host: 118.70.129.184 References: <0a0c1901-71f9-4ba1-9748-8a1857c4bf84@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <407608ee-7af7-44cd-8319-88dc8fd4661c@googlegroups.com> Subject: Re: convert from verilog to vhdl From: Mat18111992 Injection-Date: Wed, 22 Jul 2015 09:02:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8406 Thomas. Below is the code I have rewritten to implement pipelined module fixed-point division. Signal quotient_reg was calculated correctly but when I use the assignment sentence : " quotient(INPUT_WIDTH-2 downto 0) <= std_logic_vector(quotient_reg(INPUT_WIDTH-2 downto 0));" The output signal (quotient) is not correct, it get unknown value. How I fix this error? Thanks again!! Code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division is generic( INPUT_WIDTH : integer :=8; FRAC : integer :=4); port ( clk : in std_logic; reset : in std_logic; dividend : in std_logic_vector(INPUT_WIDTH-1 downto 0); divisor : in std_logic_vector(INPUT_WIDTH-1 downto 0); quotient : out std_logic_vector(INPUT_WIDTH-1 downto 0) ) ; end entity ; -- division architecture behavior of division is constant N : integer := INPUT_WIDTH+FRAC-1; constant K : integer := 2*INPUT_WIDTH+FRAC-3; type dividend_array is array (0 to N) of unsigned(K downto 0); type divisor_array is array (0 to N) of unsigned(K downto 0); signal dividend_reg : dividend_array; signal divisor_reg : divisor_array; signal quotient_reg : std_logic_vector(N-1 downto 0); begin divider : process( clk, reset ) variable tmp : unsigned(K downto 0); begin if rising_edge(clk) then if reset = '1' then quotient <= (others => '0'); quotient_reg <= (others => '0'); dividend_reg <= (others =>(others => '0')); divisor_reg <= (others =>(others => '0')); else dividend_reg(N) <= (K downto N => '0') & unsigned(dividend(INPUT_WIDTH-2 downto 0)) & (FRAC-1 downto 0 =>'0'); divisor_reg(N) <= unsigned(divisor(INPUT_WIDTH-2 downto 0)) & (N-1 downto 0 => '0'); quotient_reg <= (others => '0'); for i in N-1 downto 0 loop tmp := '0'&divisor_reg(i+1)(K downto 1); if (std_logic_vector(dividend_reg(i+1)) >= std_logic_vector(tmp)) then quotient_reg(i) <= '1'; dividend_reg(i) <= dividend_reg(i+1) - tmp; divisor_reg(i) <= '0'&divisor_reg(i+1)(K downto 1); else quotient_reg(i) <= '0'; dividend_reg(i) <= dividend_reg(i+1); divisor_reg(i) <= '0'&divisor_reg(i+1)(K downto 1); end if ; end loop; end if ; end if ; end process ; -- divider quotient(INPUT_WIDTH-1) <= dividend(INPUT_WIDTH-1) xor divisor(INPUT_WIDTH-1); quotient(INPUT_WIDTH-2 downto 0) <= std_logic_vector(quotient_reg(INPUT_WIDTH-2 downto 0)); end architecture ; -- behavior Testbench: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity division_tb is end division_tb; architecture behavioral of division_tb is component division generic ( INPUT_WIDTH : integer; FRAC : integer); port ( clk : in std_logic; reset : in std_logic; dividend : in std_logic_vector(INPUT_WIDTH-1 downto 0); divisor : in std_logic_vector(INPUT_WIDTH-1 downto 0); quotient : out std_logic_vector(INPUT_WIDTH-1 downto 0)); end component; -- component generics constant INPUT_WIDTH : integer := 8; constant FRAC : integer := 4; -- component ports signal reset : std_logic; signal dividend : std_logic_vector(INPUT_WIDTH-1 downto 0); signal divisor : std_logic_vector(INPUT_WIDTH-1 downto 0); signal quotient : std_logic_vector(INPUT_WIDTH-1 downto 0); -- clock signal clk : std_logic := '1'; begin -- behavioral -- component instantiation DUT : division generic map ( INPUT_WIDTH => INPUT_WIDTH, FRAC => FRAC) port map ( clk => clk, reset => reset, dividend => dividend, divisor => divisor, quotient => quotient); -- clock generation clk <= not clk after 10 ns; -- waveform generation: execute 7/2=3.5 WaveGen_Proc : process begin --signal assignments reset <= '1'; --data_in <= (others => '0'); wait for 20 ns; wait until rising_edge(clk); reset <= '0'; dividend <= "01110000"; --7 divisor <= "00100000"; --2 wait; end process WaveGen_Proc; end behavioral; From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.129.111.132 with SMTP id k126mr1860535ywc.10.1437560726762; Wed, 22 Jul 2015 03:25:26 -0700 (PDT) X-Received: by 10.140.97.55 with SMTP id l52mr27346qge.36.1437560726701; Wed, 22 Jul 2015 03:25:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!69no1214777qgl.1!news-out.google.com!4ni81753qgh.1!nntp.google.com!z61no2577985qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 03:25:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=147.156.81.119; posting-account=NlPq2woAAAA-uXcyqWpX4ngsDfFAtgcq NNTP-Posting-Host: 147.156.81.119 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94a082f2-4df5-4a36-ab23-d54c3a757cb2@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: luutey@gmail.com Injection-Date: Wed, 22 Jul 2015 10:25:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:8407 Hi Ralf, I had a similar problem and your solution solved it. Thanks. :) From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.107.170.25 with SMTP id t25mr1899362ioe.18.1437560860346; Wed, 22 Jul 2015 03:27:40 -0700 (PDT) X-Received: by 10.140.99.44 with SMTP id p41mr28322qge.3.1437560860210; Wed, 22 Jul 2015 03:27:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.ripco.com!news.glorb.com!f3no1268756igg.0!news-out.google.com!4ni81752qgh.1!nntp.google.com!69no1215215qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 22 Jul 2015 03:27:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=147.156.81.119; posting-account=NlPq2woAAAA-uXcyqWpX4ngsDfFAtgcq NNTP-Posting-Host: 147.156.81.119 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <973acfae-7973-4be0-a18a-4845a836e140@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: Bare-Metal Injection-Date: Wed, 22 Jul 2015 10:27:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8408 On Friday, November 9, 2012 at 8:23:29 AM UTC+1, Ralf Hildebrandt wrote: > Hi py! > > > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? > > Declare a signal in a package - a "global" signal. Write to this signal > inside your subcomponent, read this signal wherever you want. All you > need is to include this package in all components where you read/write > this signal. > > To make this subcomponent synthesizeable use > -- pragma translate_off > ... your problemativ VHDL code here ... > -- pragma translate_off > > As an alternative you can use a "shared variable". This can be written > from several locations while the signal should be written only from one > location. > > Ralf Hi Ralf, I had a similar problem and your solution solved it. Thanks. :) From newsfish@newsfish Tue Dec 29 16:43:54 2015 X-Received: by 10.182.213.166 with SMTP id nt6mr9001878obc.3.1437666217648; Thu, 23 Jul 2015 08:43:37 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr188417qge.10.1437666217620; Thu, 23 Jul 2015 08:43:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!pg9no3378628igb.0!news-out.google.com!4ni81865qgh.1!nntp.google.com!69no1481498qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 23 Jul 2015 08:43:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=151.40.190.158; posting-account=AXSUuQoAAACXwhXPPNv87DD39TdEGi6i NNTP-Posting-Host: 151.40.190.158 References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7bc89abb-8b05-4b09-b02d-cb0650267004@googlegroups.com> Subject: Re: Generate statement with varying signal width From: Andrea Campera Injection-Date: Thu, 23 Jul 2015 15:43:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8409 Hello guys, i saw it is an old topic but i'm struggling with such a problem in these days and unfortunately i saw no answer to Matt's question. The problem is this can be done with Verilog (at least > 2005). you can access variables declared in a generate statement using label.variable. There are lots of recursive structures with variable data size, and i guess VHDL can not easily provide a way to describe them. I tried to use hierarchinal names with VHDL 2008 but i was not able to find a way to reference a signal from another loop iteration. here is an example in Verilog (sorry for no indentation) genvar i; generate for(i=0;i Subject: About fpga board From: abdrhblushi@gmail.com Injection-Date: Mon, 27 Jul 2015 03:32:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8410 Hi I am working with group research in college We work on fpga board we finish coding on matlab now we want convert this code to vhdl i knew about the feature that matlab allow me to convert but as what i read it is for small code or not? i dont have any previous knowledge about this board also i am not dealing a lot with assimbly language, so i want ask How long it will take to learn vhdl virelog language? And is there any tool or way could help to convert code? From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sun, 26 Jul 2015 23:52:21 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 03:50:53 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="25848"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199908qSXwm1Mq9wX9V5IQa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> Cancel-Lock: sha1:syoUQkaheA1IxHrrndRjg/gNsK4= Xref: mx02.eternal-september.org comp.lang.vhdl:8411 On 7/26/2015 11:32 PM, abdrhblushi@gmail.com wrote: > Hi > > I am working with group research in college We work on fpga board we > finish coding on matlab now we want convert this code to vhdl i knew > about the feature that matlab allow me to convert but as what i read > it is for small code or not? i dont have any previous knowledge about > this board also i am not dealing a lot with assimbly language, > > so i want ask How long it will take to learn vhdl virelog language? > And is there any tool or way could help to convert code? Verilog and VHDL are two separate HDLs (Hardware Description Language) for the same job. Asking how long it will take to learn them is like asking, "how long is a piece of string?" That will depend on you. Is your class a coding class or a hardware design class? If the purpose is to learn an HDL what are you having trouble with? If the purpose is to learn to design hardware, then why do you need to learn an HDL? Can't Matlab pump out an HDL file? -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Mon, 27 Jul 2015 06:31:24 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 37 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8412 abdrhblushi@gmail.com wrote: > I am working with group research in college > We work on fpga board we finish coding on matlab now we > want convert this code to vhdl i knew about the feature that matlab > allow me to convert but as what i read it is for small code or not? > i dont have any previous knowledge about this board also i am > not dealing a lot with assimbly language, Why do you want to convert to VHDL for an FPGA? You don't say at all what kind of algorithm it is, which can make a big difference. Usually you do it to make it faster, but you don't say how fast it needs to be. > so i want ask > How long it will take to learn vhdl virelog language? If you understand digital logic, have wired up TTL gates to make working systems, then it won't take very long, If you haven't, then a long time. > And is there any tool or way could help to convert code? There might be, but you don't want to use it if it does. FPGA implementations of algorithms are usually different from Matlab implementations. If you don't understand the details of the algorithms, there is no use in doing it. (Note that you can implement a processor in the FPGA, then run Matlab on that processor. That likely isn't the reason to use the FPGA or VHDL.) -- glen From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 12:34:21 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 16:32:50 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13669"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+k5lcbBQQJni2tQOEeZBiK" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 Cancel-Lock: sha1:eaJxT9m+XUdZtvjecmw85I0TNfs= Xref: mx02.eternal-september.org comp.arch.fpga:22004 comp.lang.vhdl:8413 comp.lang.verilog:4034 I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the compiler, but the entire bitstream generation! http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/ Several people have built on each other's work to provide "a fully open source Verilog to bitstream development tool chain for the Lattice iCE40LP with support for more devices in the works." http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ https://github.com/cseed/arachne-pnr I haven't tried any of it yet, but I am very impressed that they are reverse engineering the devices so that they can generate bit streams and not rely on the vendor. -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 13:25:18 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 17:23:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3607"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qX5G9+U00DRBO2r6NvscX" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:q51eqYRtzoWUMOrj8ScJ+KQG6G0= Xref: mx02.eternal-september.org comp.arch.fpga:22005 comp.lang.vhdl:8414 comp.lang.verilog:4035 On 7/27/2015 12:34 PM, rickman wrote: > I am very impressed. I was reading about Antti's incredibly tiny FPGA > project board and saw a mention of a FOSS FPGA toolchain. Not just the > compiler, but the entire bitstream generation! > > http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/ > > > Several people have built on each other's work to provide "a fully open > source Verilog to bitstream development tool chain for the Lattice > iCE40LP with support for more devices in the works." > > http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ > > https://github.com/cseed/arachne-pnr > > I haven't tried any of it yet, but I am very impressed that they are > reverse engineering the devices so that they can generate bit streams > and not rely on the vendor. I found another link relating to the tools called "IceStorm". http://www.clifford.at/icestorm/ -- Rick From newsfish@newsfish Tue Dec 29 16:43:54 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 27 Jul 2015 12:57:12 -0500 From: Tim Wescott Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-ID: Date: Mon, 27 Jul 2015 12:57:12 -0500 Lines: 32 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-tfOwO5oKwqItXbQefmcDdF9yE28vOGJm7v+vw2HpDne/k0XHUIkyVY/M+kGrj3FqMwX5OoaVSo4COpx!a8FqR+R4AIk8g46vlDeGlbiB252XhlRd7/k3EjDG9QwVTY9yCnZvnrsk7pGj/yecnbo0WpoDjbfs X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2258 X-Received-Bytes: 2370 X-Received-Body-CRC: 2447858364 Xref: mx02.eternal-september.org comp.arch.fpga:22006 comp.lang.vhdl:8415 comp.lang.verilog:4036 On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: > I am very impressed. I was reading about Antti's incredibly tiny FPGA > project board and saw a mention of a FOSS FPGA toolchain. Not just the > compiler, but the entire bitstream generation! > > http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas- that-small/ > > Several people have built on each other's work to provide "a fully open > source Verilog to bitstream development tool chain for the Lattice > iCE40LP with support for more devices in the works." > > http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ > > https://github.com/cseed/arachne-pnr > > I haven't tried any of it yet, but I am very impressed that they are > reverse engineering the devices so that they can generate bit streams > and not rely on the vendor. Kewl. It'll be even more kewl if it shames the vendors into being open with their bitstream specifications. I have no idea why they seem to feel this needs to be held so close to their chests. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 14:30:34 -0400 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 27 Jul 2015 18:29:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20847"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+iAhN1wfQLe63UDEmb1Bg+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:8AAkuFZmch7faNs0+X8rM5kgedg= Xref: mx02.eternal-september.org comp.arch.fpga:22007 comp.lang.vhdl:8416 comp.lang.verilog:4037 On 7/27/2015 1:57 PM, Tim Wescott wrote: > On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: > >> I am very impressed. I was reading about Antti's incredibly tiny FPGA >> project board and saw a mention of a FOSS FPGA toolchain. Not just the >> compiler, but the entire bitstream generation! >> >> http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas- > that-small/ >> >> Several people have built on each other's work to provide "a fully open >> source Verilog to bitstream development tool chain for the Lattice >> iCE40LP with support for more devices in the works." >> >> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/ >> >> https://github.com/cseed/arachne-pnr >> >> I haven't tried any of it yet, but I am very impressed that they are >> reverse engineering the devices so that they can generate bit streams >> and not rely on the vendor. > > Kewl. > > It'll be even more kewl if it shames the vendors into being open with > their bitstream specifications. I have no idea why they seem to feel > this needs to be held so close to their chests. I seriously doubt this will ever happen. They have all done this nearly 100% of the time and I'm sure they are convinced it is the best way to do business. From what they have said their concern is that with open source tools their hardware will be subject to "problems" caused by poor tools. Or maybe they limit access to chip features through the tools which they couldn't do with FOSS tools. I seem to recall someone ranting that a line of Altera parts had some devices which were labeled as smaller chips but would load and run a bitstream for a larger part. I expect this would show up quickly and clearly if the tools were FOSS. Those who have been in this business long enough may remember the line of parts Xilinx made specifically to support an open bit stream. It was popular with academia and a number of papers were written about researchy things you might do with it. I'm not sure what Xilinx's motive was for producing these chips, but they dropped the line and crushed the molds. I'm pretty sure there is no mention of these parts anywhere on their site now. Or did I only dream all of that? -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Mon, 27 Jul 2015 21:01:31 +0100 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Injection-Date: Mon, 27 Jul 2015 19:59:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9163fd05fabfda4407ad86bfb650ef6a"; logging-data="9725"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/RuwkaQ500IajQzOX90ivR" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:EZvlXqhQc2RoQsHiB8mWB8xlhrE= X-Priority: 3 X-MSMail-Priority: Normal Xref: mx02.eternal-september.org comp.arch.fpga:22008 comp.lang.vhdl:8417 comp.lang.verilog:4038 > Those who have been in this business long enough may remember the line of > parts Xilinx made specifically to support an open bit stream. It was > popular with academia and a number of papers were written about researchy > things you might do with it. I'm not sure what Xilinx's motive was for > producing these chips, but they dropped the line and crushed the molds. > I'm pretty sure there is no mention of these parts anywhere on their site > now. Or did I only dream all of that? Maybe you will also be interested in this: https://recon.cx/2015/slides/recon2015-18-andrew-zonenberg-From-Silicon-to-Compiler.pdf Tomas D. From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.182.230.3 with SMTP id su3mr31862503obc.6.1438044069440; Mon, 27 Jul 2015 17:41:09 -0700 (PDT) X-Received: by 10.140.96.137 with SMTP id k9mr493197qge.10.1438044069283; Mon, 27 Jul 2015 17:41:09 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no3754802igg.0!news-out.google.com!4ni82402qgh.1!nntp.google.com!69no2334689qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 27 Jul 2015 17:41:08 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.40.1.190; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 37.40.1.190 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 28 Jul 2015 00:41:09 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8418 The story was that we had AES(advance encryption standard) algorithm and we= want to put it in fpga board to use it in our college, the problem now i t= ry to implement some example of code to test the board but i faced difficul= ty and i felt that i am on the middel of the ocean and i forget to swim. I = am thinking to take courses but it not available in my country or college,= and i have to finish the work within two=A0month From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Mon, 27 Jul 2015 21:27:01 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 01:25:38 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3099"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ftkpzr2eO9s9kWPPZW9CS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> Cancel-Lock: sha1:Uy4lScYU5JNXh3Gj5EpCYod7/kY= Xref: mx02.eternal-september.org comp.lang.vhdl:8419 On 7/27/2015 8:41 PM, abdrhblushi@gmail.com wrote: > The story was that we had AES(advance encryption standard) algorithm > and we want to put it in fpga board to use it in our college, the > problem now i try to implement some example of code to test the board > but i faced difficulty and i felt that i am on the middel of the > ocean and i forget to swim. I am thinking to take courses but it not > available in my country or college, and i have to finish the work > within two month Rather than fight the FPGA which can be a PITA, run your code on the simulator. You should be able to input and output files for the data you want to decrypt/encrypt. You can watch every value in every part of the design without needing to place probes. If the simulation works ok then you need to look for issues related to the possible errors that won't show in simulation. These errors are checked for in other ways or are usually avoided by paying attention to the few specific details involved such as clock domain crossing. But the simulation is the starting point. A friend used to have the email tag line, "If the dead in tombs are entombed, are the dead in crypts encrypted?" -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 28 Jul 2015 01:41:07 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8420 abdrhblushi@gmail.com wrote: > The story was that we had AES(advance encryption standard) > algorithm and we want to put it in fpga board to use it in > our college, the problem now i try to implement some example > of code to test the board but i faced difficulty and i felt > that i am on the middel of the ocean and i forget to swim. It is usual to feel lost at the beginning of learning something new, so don't worry about that. But you do need to learn to think about wires and signals, if you haven't before. You can do this separate from learning VHDL. Have you done any electronic projects before? Analog or digital? > I am thinking to take courses but it not available in my > country or college, and i have to finish the work within > two month There should be some Coursera courses that cover enough. -- glen From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Organization: A noiseless patient Spider Lines: 48 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="22833"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19zX8UWf483O79UzPk/+rHoux6eZ1mFzRc=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:acqp4WTKaoSl8IkY+ct/V6VvHzY= Xref: mx02.eternal-september.org comp.arch.fpga:22009 comp.lang.vhdl:8421 comp.lang.verilog:4039 On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > On 7/27/2015 1:57 PM, Tim Wescott wrote: >> On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: >> >>> I am very impressed. I was reading about Antti's incredibly tiny FPGA >>> project board and saw a mention of a FOSS FPGA toolchain. Not just >>> the compiler, but the entire bitstream generation! >>> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40- fpgas/ > Excellent! Though I'm not surprised it's Lattice, I vaguely recall looking through an early (pre-2000) toolchain of theirs and thinking the details were closer to the surface than with other vendors. > Those who have been in this business long enough may remember the line > of parts Xilinx made specifically to support an open bit stream. It was > popular with academia and a number of papers were written about > researchy things you might do with it. I'm not sure what Xilinx's > motive was for producing these chips, but they dropped the line and > crushed the molds. I'm pretty sure there is no mention of these parts > anywhere on their site now. Or did I only dream all of that? Indeed you didn't dream the XC6200 series. It wasn't so much that Xilinx developed them, as they bought the company that did (Algotronics or Algotronix I think, based in Edinburgh). Presumably they bought them for tech in general or possibly some key patents rather than the specific device family. Which was something of a dead end in other respects, too fine grained (I believe' 1 gate, 1FF per CLB). Much simpler and more regular, but wouldn't scale too well to million-CLB devices dominated by routing, where the XC4000 and later devices would give the same capacity with a much smaller and cheaper die. I think it was that simple regular structure that made opening the bitstream format attractive, as well as killing the device long-term. You may also recall a company that successfully reverse-engineered the bitstream for Xilinx devices, and started to market their own independent toolchain. Yup, Xilinx bought them too. But their name lives on in the .ncd (neocad) file extension. -- Brian From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 13:32:39 -0400 Organization: A noiseless patient Spider Lines: 87 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 17:31:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="16270"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18xzUbYmDPK2Hk64jDJ+HKl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:l/DK0/nGcVkS2kBrOw9PbcWeIXo= Xref: mx02.eternal-september.org comp.arch.fpga:22010 comp.lang.vhdl:8422 comp.lang.verilog:4040 On 7/28/2015 6:06 AM, Brian Drummond wrote: > On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > >> On 7/27/2015 1:57 PM, Tim Wescott wrote: >>> On Mon, 27 Jul 2015 12:34:21 -0400, rickman wrote: >>> >>>> I am very impressed. I was reading about Antti's incredibly tiny FPGA >>>> project board and saw a mention of a FOSS FPGA toolchain. Not just >>>> the compiler, but the entire bitstream generation! > >>>> http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40- > fpgas/ >> > > Excellent! Though I'm not surprised it's Lattice, I vaguely recall > looking through an early (pre-2000) toolchain of theirs and thinking the > details were closer to the surface than with other vendors. > >> Those who have been in this business long enough may remember the line >> of parts Xilinx made specifically to support an open bit stream. It was >> popular with academia and a number of papers were written about >> researchy things you might do with it. I'm not sure what Xilinx's >> motive was for producing these chips, but they dropped the line and >> crushed the molds. I'm pretty sure there is no mention of these parts >> anywhere on their site now. Or did I only dream all of that? > > Indeed you didn't dream the XC6200 series. It wasn't so much that Xilinx > developed them, as they bought the company that did (Algotronics or > Algotronix I think, based in Edinburgh). Presumably they bought them for > tech in general or possibly some key patents rather than the specific > device family. > > Which was something of a dead end in other respects, too fine grained (I > believe' 1 gate, 1FF per CLB). Much simpler and more regular, but > wouldn't scale too well to million-CLB devices dominated by routing, > where the XC4000 and later devices would give the same capacity with a > much smaller and cheaper die. > > I think it was that simple regular structure that made opening the > bitstream format attractive, as well as killing the device long-term. > > You may also recall a company that successfully reverse-engineered the > bitstream for Xilinx devices, and started to market their own independent > toolchain. It has been a very long time, but I don't think NeoCAD was spitting out bitstreams for Xilinx parts where they? I may not remember it right, but I thought their claim to fame was their router which did a better job than the Xilinx tools which is why Xilinx bought them. Rather than bury the NeoCAD tools and moving on, they shipped the NeoCAD tools as their main tool. They reverse engineered the routing I know. I guess it wouldn't be so hard to figure out the bit stream too. I recall that NeoCAD was supporting other companies because they realized what a large job it was to write their own tools. So other new entries to the market used NeoCAD as their only tool. There were clauses in place to give them rights to the software if NeoCAD was bought by a competitor, which is what happened. I'm not sure that was much solace since they all ended up having to support their own software at that point which is what they were trying to get away from. > Yup, Xilinx bought them too. But their name lives on in the .ncd (neocad) > file extension. I seem to recall having the NeoCAD tools for some product other than Xilinx. It may be the ORCA devices which Lucent produced with their license from Xilinx. Not an XC4000 clone, but used Xilinx patents with similar functionality. I seem to recall they had the first CLBs where all components were not equivalent. Lattice does that in several of their FPGA lines now that they have the Lucent FPGA products and Xilinx licenses. I recall that Altera has terms in their software to limit what you can do with the bit stream. If you want to make an ASIC you *have* to come to them. That killed a company who was providing exactly that service, bit stream to ASIC. Do all the FPGA makers do that? I would think that alone would be reason enough to reverse engineer the bit stream. That company could then produce the bit stream themselves which would retain the 1:1 relation between your verified FPGA design and the ASIC. Maybe that is why FPGA companies don't want FOSS tools? It would take away their ASIC business. Is that very popular anymore? I haven't seen it promoted in years. -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.182.219.225 with SMTP id pr1mr35979769obc.23.1438108519356; Tue, 28 Jul 2015 11:35:19 -0700 (PDT) X-Received: by 10.140.109.132 with SMTP id l4mr563096qgf.15.1438108519214; Tue, 28 Jul 2015 11:35:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!pg9no4787198igb.0!news-out.google.com!4ni82491qgh.1!nntp.google.com!69no2480418qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 28 Jul 2015 11:35:18 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=37.40.3.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 37.40.3.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 28 Jul 2015 18:35:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8423 There is no way back so i will make more effort to learn it in two months, what are your advices and guidelines for me? I will be thankful From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 28 Jul 2015 18:53:17 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 14 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8424 abdrhblushi@gmail.com wrote: > There is no way back so i will make more effort to learn it > in two months, what are your advices and guidelines for me? > I will be thankful What have you done before? It is hard to say much without knowing that. Have you built any electronic circuits? Even simple ones? Have you worked at all with TTL circuits? -- glen From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!border2.nntp.ams1.giganews.com!nntp.giganews.com!buffer2.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 28 Jul 2015 13:59:38 -0500 Date: Tue, 28 Jul 2015 19:59:38 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150728195938.5dcc9e5e@HP-6550b> References: X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 46 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ZHjtYtKJ1EnGJ1L5oI4NAm3pgUIe3ZwMtmT0qdKl1MLrp5JXHrWfUOkkCf2u45dvtG0bx1fmEWPE8PE!0nNaGzKrUkYR5t7nkVcdOv49L9o1dGRioyrHr48mkLoi7ELV4D9IgKvYXLhz8qIOwszL/dQSi5sD!CUVE X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3101 Xref: mx02.eternal-september.org comp.arch.fpga:22012 comp.lang.vhdl:8425 comp.lang.verilog:4041 On Tue, 28 Jul 2015 13:32:39 -0400 rickman wrote: > I recall that NeoCAD was supporting other companies because > they realized what a large job it was to write their own > tools. So other new entries to the market used NeoCAD as > their only tool. There were clauses in place to give them > rights to the software if NeoCAD was bought by a competitor, > which is what happened. I'm not sure that was much solace > since they all ended up having to support their own software > at that point which is what they were trying to get away from. > > > Yup, Xilinx bought them too. But their name lives on in > > the .ncd (neocad) file extension. > > I seem to recall having the NeoCAD tools for some product > other than Xilinx. It may be the ORCA devices which Lucent > produced with their license from Xilinx. Not an XC4000 clone, > but used Xilinx patents with similar functionality. I seem to > recall they had the first CLBs where all components were not > equivalent. Lattice does that in several of their FPGA lines > now that they have the Lucent FPGA products and Xilinx > licenses. And NeoCAD is still around: ************************************************************ ** Lattice Synthesis Engine ** ************************************************************ synthesis -f "spi12_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.4.0.80 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Tue Jul 28 19:53:33 2015 Jan Coombs -- email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 28 Jul 2015 14:55:48 -0500 Date: Tue, 28 Jul 2015 20:55:48 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150728205548.1ede5368@HP-6550b> References: X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 49 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-3NtGAmJJf8k81iwYYqlsCWv2q2V+bVeAi2p+mfATetLI1NNnahOlYd1GTzefKXawAaVsFZKFB+19itB!M0K+2IxM3TfRcejuRDJqeqww9OeCgQw3Z/KpLNxnc6I+pQJF755dXUXTDmnxFXKqlIvYlGq+UdW2!BgfR X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3104 Xref: mx02.eternal-september.org comp.arch.fpga:22013 comp.lang.vhdl:8426 comp.lang.verilog:4042 On Tue, 28 Jul 2015 10:06:48 +0000 (UTC) Brian Drummond wrote: > On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: > > > Those who have been in this business long enough may > > remember the line of parts Xilinx made specifically to > > support an open bit stream. [...] I'm pretty sure there > > is no mention of these parts anywhere on their site now. Or > > did I only dream all of that? > > Indeed you didn't dream the XC6200 series. It wasn't so much > that Xilinx developed them, as they bought the company that > did (Algotronics or Algotronix I think, based in Edinburgh). > Presumably they bought them for tech in general or possibly > some key patents rather than the specific device family. > > Which was something of a dead end in other respects, too fine > grained (I believe' 1 gate, 1FF per CLB). Much simpler and > more regular, but wouldn't scale too well to million-CLB > devices dominated by routing, where the XC4000 and later > devices would give the same capacity with a much smaller and > cheaper die. How about half a half a LUT or FF per CLB then? The Microsemi "IGLOO nano Low Power Flash" FPGAs are very similar in size and capability to the Lattice iCE40 range, except: The basic building block is either a flop or a LUT3 equivalent circuit, and these are then grouped into 8x8 blocks. [1] Innovation seems to come from smaller companies: as Lattice inherited the iCE40 series from SiliconBlue, Microsemi got the IGLOO parts from Actel, and the technology seen even earlier with ConcurrentLogic. An open-source toolchain for the IGLOO parts could be an unusually powerful tool in the hands of a creative designer. Jan Coombs -- [1] pg 73 of http://www.microsemi.com/document-portal/doc_view/130695-igloo-nano-low-power-flash-fpgas-datasheet email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 28 Jul 2015 16:10:51 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <20150728205548.1ede5368@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 28 Jul 2015 20:09:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="23684"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18eE2hl2yKD92Yzz4jhXKEe" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <20150728205548.1ede5368@HP-6550b> Cancel-Lock: sha1:6a3AATpwz2MeHeyOw3tuL7NruYM= Xref: mx02.eternal-september.org comp.arch.fpga:22014 comp.lang.vhdl:8427 comp.lang.verilog:4043 On 7/28/2015 3:55 PM, Jan Coombs On Tue, 28 Jul 2015 10:06:48 +0000 (UTC) > Brian Drummond wrote: > >> On Mon, 27 Jul 2015 14:30:34 -0400, rickman wrote: >> >>> Those who have been in this business long enough may >>> remember the line of parts Xilinx made specifically to >>> support an open bit stream. [...] I'm pretty sure there >>> is no mention of these parts anywhere on their site now. Or >>> did I only dream all of that? >> >> Indeed you didn't dream the XC6200 series. It wasn't so much >> that Xilinx developed them, as they bought the company that >> did (Algotronics or Algotronix I think, based in Edinburgh). >> Presumably they bought them for tech in general or possibly >> some key patents rather than the specific device family. >> >> Which was something of a dead end in other respects, too fine >> grained (I believe' 1 gate, 1FF per CLB). Much simpler and >> more regular, but wouldn't scale too well to million-CLB >> devices dominated by routing, where the XC4000 and later >> devices would give the same capacity with a much smaller and >> cheaper die. > > How about half a half a LUT or FF per CLB then? > > The Microsemi "IGLOO nano Low Power Flash" FPGAs are very > similar in size and capability to the Lattice iCE40 range, > except: > > The basic building block is either a flop or a LUT3 equivalent > circuit, and these are then grouped into 8x8 blocks. [1] > > Innovation seems to come from smaller companies: as Lattice > inherited the iCE40 series from SiliconBlue, I wouldn't say Lattice "inherited" the iCE40 family. That was what they bought, the rest of the SiBlue company came for free. > Microsemi > got the IGLOO parts from Actel, and the technology seen > even earlier with ConcurrentLogic. I don't think Concurrent Logic ended up in the hands of Actel. I know they were bought by Atmel and died a very slow death of being unfunded. I received training from the guy at Atmel who was the champion of that line. They never made an effort to keep up with process technology advances to reduce the costs. That said, I expect they knew the way to go was something more like the Xilinx/Altera routes. The fine grained architecture without routing resources just won't work for larger designs. As Xilinx used to say, "We sell you the routing and give you the logic for free." > An open-source toolchain for the IGLOO parts could be an > unusually powerful tool in the hands of a creative designer. I have looked at the Igloo parts but never been impressed. Why would an open source tool chain improve them or any other part? -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!border1.nntp.ams1.giganews.com!nntp.giganews.com!buffer1.nntp.ams1.giganews.com!local2.nntp.ams1.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 29 Jul 2015 04:50:08 -0500 Date: Wed, 29 Jul 2015 10:50:09 +0100 From: Jan Coombs > Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Message-ID: <20150729105009.412968bf@HP-6550b> References: <20150728205548.1ede5368@HP-6550b> X-Newsreader: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-x6X3iApQ5fwLBgy9DCcnYY72BW60vj9FeSsUpC5MSI62h2LXdsQzr0zw3N8bDdeCCrEkC65TZgS2lkb!8ICMvSaN5IfirGlR+RtCfA/HvHJlRBXU63fOUCBkvzqGMaCF7tRLdk8EkpuuvlNRH0cMFy5eP9Q4!ANAk X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2261 Xref: mx02.eternal-september.org comp.arch.fpga:22015 comp.lang.vhdl:8428 comp.lang.verilog:4044 On Tue, 28 Jul 2015 16:10:51 -0400 rickman wrote: > On 7/28/2015 3:55 PM, Jan Coombs > An open-source toolchain for the IGLOO parts could be an > > unusually powerful tool in the hands of a creative designer. > > I have looked at the Igloo parts but never been impressed. > Why would an open source tool chain improve them or any other > part? Because open source tools allow exploration of techniques which are restricted using regular tools. a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks if using IceStorm, one or more parts might die during (mal?)practice) b) IGLOO - because you would then be able to create complex logic without the noise or random signal states inherent in using lookup tables. One possibility might be asynchronous logic. c) [others] no idea, unless they are close relatives of the above parts. (like ProASIC3) Jan Coombs -- email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 29 Jul 2015 12:32:08 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 29 Jul 2015 16:30:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="3011"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Yd4AKQEc4YZGTN+KUCzKA" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <20150729105009.412968bf@HP-6550b> Cancel-Lock: sha1:reopWSWsLrX5ewW8ATNx0Z6YROU= Xref: mx02.eternal-september.org comp.arch.fpga:22017 comp.lang.vhdl:8429 comp.lang.verilog:4045 On 7/29/2015 5:50 AM, Jan Coombs On Tue, 28 Jul 2015 16:10:51 -0400 > rickman wrote: > >> On 7/28/2015 3:55 PM, Jan Coombs >> An open-source toolchain for the IGLOO parts could be an >>> unusually powerful tool in the hands of a creative designer. >> >> I have looked at the Igloo parts but never been impressed. >> Why would an open source tool chain improve them or any other >> part? > > Because open source tools allow exploration of techniques which > are restricted using regular tools. I'm not sure what this means. What "techniques" are restricted by the vendor's tools? Are we talking about techniques that are useful in a design environment or research? > a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 > sticks if using IceStorm, one or more parts might die during > (mal?)practice) I thoought I had read the thread. What did I miss? All I've seen is that there are alternative tools available that may or may not be as good as the vendor's tools. Other than not having to fight the licensing, what improvement do the alternative tools provide? > b) IGLOO - because you would then be able to create complex > logic without the noise or random signal states inherent in > using lookup tables. One possibility might be asynchronous > logic. ??? What logic won't the Igloo tools create? Sounds like I clearly need to avoid the Microsemi parts. > c) [others] no idea, unless they are close relatives of the > above parts. (like ProASIC3) ok -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.13.245.6 with SMTP id e6mr43333840ywf.27.1438192775030; Wed, 29 Jul 2015 10:59:35 -0700 (PDT) X-Received: by 10.140.37.129 with SMTP id r1mr620134qgr.18.1438192774973; Wed, 29 Jul 2015 10:59:34 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no4022151qge.0!news-out.google.com!4ni82620qgh.1!nntp.google.com!z61no4022150qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 29 Jul 2015 10:59:34 -0700 (PDT) In-Reply-To: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2a02:1812:510:7f00:896:b5f0:24ad:b755; posting-account=Y8jO5woAAABQjiGcTkoIyOEHis_U9pYB NNTP-Posting-Host: 2a02:1812:510:7f00:896:b5f0:24ad:b755 References: <72456d4d-6163-4ace-957f-674eb55a38a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Register map auto-generation From: jan Injection-Date: Wed, 29 Jul 2015 17:59:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: mx02.eternal-september.org comp.lang.vhdl:8430 Maybe this: https://github.com/oddball/ipxact2systemverilog A Open-Source Python script to covert IP-XACT to VHDL/SystemVerilog/PDF/... From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.182.79.165 with SMTP id k5mr9117159obx.38.1438455234092; Sat, 01 Aug 2015 11:53:54 -0700 (PDT) X-Received: by 10.140.21.74 with SMTP id 68mr81683qgk.16.1438455234022; Sat, 01 Aug 2015 11:53:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!f3no6023622igg.0!news-out.google.com!b31ni3247qge.0!nntp.google.com!69no3292107qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Aug 2015 11:53:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.154.147.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 85.154.147.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sat, 01 Aug 2015 18:53:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8431 I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 01 Aug 2015 15:26:38 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Aug 2015 19:25:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="28283"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zg4/0ptUBpqvR7ZINo6W2" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> Cancel-Lock: sha1:RE/i2N5aaAzq9zp215sCWl2LuA0= Xref: mx02.eternal-september.org comp.lang.vhdl:8432 On 8/1/2015 2:53 PM, abdrhblushi@gmail.com wrote: > I didn't do any thaings of what you said, but i am ready to do any things to be in the true way to learn it Are you familiar with programming languages? Which ones and how much? A software designer came to this group once asking for help writing a "Hello world" program in HDL. Many of us told him it would be a difficult job if he didn't learn to "think" in hardware. I spent some time coaching him a bit and he had no trouble at all doing what he needed to do. Turns out you can write HDL similar to software as long as you observe a few basic rules. So this might not be such a difficult task if you can get Matlab to spit out some working code like C for example. Doesn't Matlab spit out an HDL though? I'm pretty sure I've heard of that. First think you need to do is to pick a starting point. I think working from the Matlab code is the last option you should pursue. -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.50.8.1 with SMTP id n1mr9930709iga.1.1438459027017; Sat, 01 Aug 2015 12:57:07 -0700 (PDT) X-Received: by 10.140.20.21 with SMTP id 21mr87748qgi.9.1438459026948; Sat, 01 Aug 2015 12:57:06 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!f3no6049172igg.0!news-out.google.com!b31ni3263qge.0!nntp.google.com!z61no4666259qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 1 Aug 2015 12:57:06 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.154.147.82; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 85.154.147.82 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sat, 01 Aug 2015 19:57:06 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 5 Xref: mx02.eternal-september.org comp.lang.vhdl:8433 I am good in java I understand the logic of it very well So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it.. Thank you very much for your help From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 01 Aug 2015 19:56:41 -0400 Organization: A noiseless patient Spider Lines: 15 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 1 Aug 2015 23:55:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="20107"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+cvcvr6rxUjs7WBVktHm9+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Cancel-Lock: sha1:lPb8sEQIRTM5pynhYQsgT9zGIxU= Xref: mx02.eternal-september.org comp.lang.vhdl:8434 On 8/1/2015 3:57 PM, abdrhblushi@gmail.com wrote: > I am good in java > I understand the logic of it very well > > So i will do what you said then i will return to show you the result and what i understand, now i have final exam after finishing i will try it.. Showing me Java won't mean much to me as I don't write or read it. I am pretty sure MatLab will translate your Matlab code to an HDL. Why not use that for a first pass. We can help you massage that code to make it work the way you want I expect. Likely easier than trying to teach you HDL from your understanding of Java. -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.66.185.195 with SMTP id fe3mr2514638pac.13.1438686503190; Tue, 04 Aug 2015 04:08:23 -0700 (PDT) X-Received: by 10.140.81.38 with SMTP id e35mr28900qgd.3.1438686503095; Tue, 04 Aug 2015 04:08:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no7301757igg.0!news-out.google.com!78ni5929qge.1!nntp.google.com!69no3798786qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 04:08:22 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.140.141.107; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.140.141.107 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 04 Aug 2015 11:08:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8435 It is good idea i will send all codes that i want to convert to your email, please send it for me, My email: abdrhblushi@gmail.com With regards From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 04 Aug 2015 12:35:27 -0400 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 16:33:52 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="1669"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+JKkCFVYAfOmyIgiX+ABKs" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:ReUzuZa0+7PhsLjU5FZgMXCYs+w= Xref: mx02.eternal-september.org comp.lang.vhdl:8436 On 8/4/2015 7:08 AM, abdrhblushi@gmail.com wrote: > It is good idea i will send all codes that i want to convert to your email, please send it for me, > My email: abdrhblushi@gmail.com What type of code do you have? -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.13.229.198 with SMTP id o189mr3993399ywe.36.1438707422344; Tue, 04 Aug 2015 09:57:02 -0700 (PDT) X-Received: by 10.140.97.55 with SMTP id l52mr56226qge.36.1438707422287; Tue, 04 Aug 2015 09:57:02 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no5224448qge.0!news-out.google.com!78ni6270qge.1!nntp.google.com!z61no5224445qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 09:57:02 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.242.139.195; posting-account=nUlK9goAAACu3kqCZ7wyRXwYlqENGl59 NNTP-Posting-Host: 109.242.139.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: implement galois polynomial mod From: Parfa Injection-Date: Tue, 04 Aug 2015 16:57:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8437 Hi, I am quite new in VHDL, I Would like to ask if anybody could help me with implementing an synthesizable modulo operator between a fixed sized (128 bits) galois polynomial and a variable sized (8-128 bits) galois polynomial. From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: implement galois polynomial mod Date: Tue, 4 Aug 2015 17:52:53 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 12 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8438 Parfa wrote: > Hi, I am quite new in VHDL, > I Would like to ask if anybody could help me with implementing > an synthesizable modulo operator between a fixed sized (128 bits) > galois polynomial and a variable sized (8-128 bits) galois polynomial. Probably not, but it is important to know how fast it has to be, and whether or not it can be pipelined. -- glen From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.66.237.2 with SMTP id uy2mr4679195pac.11.1438716598131; Tue, 04 Aug 2015 12:29:58 -0700 (PDT) X-Received: by 10.140.36.170 with SMTP id p39mr66940qgp.28.1438716598082; Tue, 04 Aug 2015 12:29:58 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no7523563igg.0!news-out.google.com!78ni6447qge.1!nntp.google.com!69no3886752qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 12:29:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=109.242.139.195; posting-account=nUlK9goAAACu3kqCZ7wyRXwYlqENGl59 NNTP-Posting-Host: 109.242.139.195 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: implement galois polynomial mod From: Parfa Injection-Date: Tue, 04 Aug 2015 19:29:58 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8439 =CE=A4=CE=B7 =CE=A4=CF=81=CE=AF=CF=84=CE=B7, 4 =CE=91=CF=85=CE=B3=CE=BF=CF= =8D=CF=83=CF=84=CE=BF=CF=85 2015 - 7:57:06 =CE=BC.=CE=BC. UTC+3, =CE=BF =CF= =87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 Parfa =CE=AD=CE=B3=CF=81=CE=B1=CF= =88=CE=B5: > Hi, I am quite new in VHDL, I Would like to ask if anybody could help me = with implementing an synthesizable modulo operator between a fixed sized (1= 28 bits) galois polynomial and a variable sized (8-128 bits) galois polynom= ial. Is something like "Reed Solomon Encoder" the answer? From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.107.38.11 with SMTP id m11mr4877641iom.15.1438718864115; Tue, 04 Aug 2015 13:07:44 -0700 (PDT) X-Received: by 10.140.97.199 with SMTP id m65mr64766qge.29.1438718864047; Tue, 04 Aug 2015 13:07:44 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!pg9no7076010igb.0!news-out.google.com!78ni6464qge.1!nntp.google.com!z61no5258247qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 4 Aug 2015 13:07:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.140.178.39; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.140.178.39 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Tue, 04 Aug 2015 20:07:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8440 Matlab code From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Aleksandar Kuktin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 4 Aug 2015 23:05:00 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 15 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> NNTP-Posting-Host: NcDLOX2QlKEv0KECGquTJw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Pan/0.135 (Tomorrow I'll Wake Up and Scald Myself with Tea; Unknown) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.arch.fpga:22048 comp.lang.vhdl:8441 comp.lang.verilog:4047 On Wed, 29 Jul 2015 12:32:08 -0400, rickman wrote: > On 7/29/2015 5:50 AM, Jan Coombs > a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks >> if using IceStorm, one or more parts might die during (mal?)practice) > > I thoought I had read the thread. What did I miss? All I've seen is > that there are alternative tools available that may or may not be as > good as the vendor's tools. Other than not having to fight the > licensing, what improvement do the alternative tools provide? Hackability. If you have an itch, you can scratch it yourself with FOSS tools. If you discover a bug, you can fix it yourself. If you want to repurpose, optimize or otherwise change the tool, you can do it with FOSS. From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Tue, 04 Aug 2015 19:46:38 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 23:45:10 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XZK0S1ByBvFP8DPDYHX3K" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:PJ2sbzX5tDTOGTyd8dhrC4Kli6A= Xref: mx02.eternal-september.org comp.arch.fpga:22050 comp.lang.vhdl:8442 comp.lang.verilog:4048 On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: > On Wed, 29 Jul 2015 12:32:08 -0400, rickman wrote: > >> On 7/29/2015 5:50 AM, Jan Coombs >>> a) iCE40 - see rest of thread. (Note suggestion to buy 3 iCE40 sticks >>> if using IceStorm, one or more parts might die during (mal?)practice) >> >> I thoought I had read the thread. What did I miss? All I've seen is >> that there are alternative tools available that may or may not be as >> good as the vendor's tools. Other than not having to fight the >> licensing, what improvement do the alternative tools provide? > > Hackability. If you have an itch, you can scratch it yourself with FOSS > tools. If you discover a bug, you can fix it yourself. If you want to > repurpose, optimize or otherwise change the tool, you can do it with FOSS. That's great. But only important to a small few. I use tools to get work done. I have zero interest in digging into the code of the tools without a real need. I have not found any bugs in the vendor's tools that would make me want to spend weeks learning how they work in the, most likely, vain hope that I could fix them. I think FOSS is great and I am very happy to see that finally happen in an end to end toolchain for an FPGA. But it is statements like this that I don't understand, "An open-source toolchain for the IGLOO parts could be an unusually powerful tool in the hands of a creative designer", or this "Because open source tools allow exploration of techniques which are restricted using regular tools." Not trying to give anyone grief. I'd just like to understand what people expect to happen with FOSS that isn't happening with the vendor's closed, but free tools. -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Tue, 04 Aug 2015 19:47:30 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 4 Aug 2015 23:45:56 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="7679"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18bwqZ6WdaZiqtcRYxB7CzL" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:KSg4zmGZ7+q0uBBg4vtDEySVvDM= Xref: mx02.eternal-september.org comp.lang.vhdl:8443 On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote: > Matlab code Have you asked Matlab to convert your design to an HDL yet? -- Rick From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: implement galois polynomial mod Date: Wed, 5 Aug 2015 12:29:08 +0000 (UTC) Organization: A noiseless patient Spider Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 5 Aug 2015 12:29:08 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="32182"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/7aM/4OjsaQgFeuLZatKI7bVIqelhAh64=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vGEwTgiodKJy5RjBPmDxPnlOrx8= Xref: mx02.eternal-september.org comp.lang.vhdl:8444 On Tue, 04 Aug 2015 12:29:57 -0700, Parfa wrote: > Τη ΤÏίτη, 4 ΑυγοÏστου 2015 - 7:57:06 μ.μ. UTC+3, ο χÏήστης Parfa έγÏαψε: >> Hi, I am quite new in VHDL, I Would like to ask if anybody could help >> me with implementing an synthesizable modulo operator between a fixed >> sized (128 bits) galois polynomial and a variable sized (8-128 bits) >> galois polynomial. > > Is something like "Reed Solomon Encoder" the answer? At this level, the question has nothing whatsoever to do with VHDL, so find generic answers (not language-specific) to the question. Actually translating from a proven answer into VHDL is likely to be relatively easy, so don't worry about VHDL yet. Any questions about that translation are likely to be answerable here. -- Brian From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 12:32:20 +0000 (UTC) Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 5 Aug 2015 12:32:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="32182"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/6lvrReY9ZLpIl5c44xWD0a0P42xGcFMM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:P0rqXp1ki6Q49DW2DuwA19xvzGU= Xref: mx02.eternal-september.org comp.lang.vhdl:8445 On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote: > On 8/4/2015 4:07 PM, abdrhblushi@gmail.com wrote: >> Matlab code > > Have you asked Matlab to convert your design to an HDL yet? That requires an expensive additional tool, strangely called called "HDL Coder", and last time I looked it generated hilariously awful VHDL. It's probably easier to convert from Matlab to VHDL by hand that work with HDL Coder's output... -- Brian From newsfish@newsfish Tue Dec 29 16:43:55 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 19:45:34 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 25 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8446 Brian Drummond wrote: > On Tue, 04 Aug 2015 19:47:30 -0400, rickman wrote: (snip) >> Have you asked Matlab to convert your design to an HDL yet? > That requires an expensive additional tool, strangely called called "HDL > Coder", and last time I looked it generated hilariously awful VHDL. It's > probably easier to convert from Matlab to VHDL by hand that work with HDL > Coder's output... That is what I would expect. Well, there is an easy way, which is to generate code for a soft processor in ROM, and then generate VHDL for the processor. Many years ago, I had some perl programs that ran too slow (1 MB/min). I found a perl2c converter, converted to C, and found it was just as slow. The converter generates the internal code that perl uses, and the interpreter for that code. Often the useful hardware implementation of an algorithm is completely different from the usual software implementations. It is unusual for tools to figure that out. -- glen From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.70.41.102 with SMTP id e6mr8487133pdl.10.1438805861248; Wed, 05 Aug 2015 13:17:41 -0700 (PDT) X-Received: by 10.140.28.2 with SMTP id 2mr35607qgy.9.1438805861164; Wed, 05 Aug 2015 13:17:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!f3no8042990igg.0!news-out.google.com!78ni7944qge.1!nntp.google.com!69no4098539qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Aug 2015 13:17:40 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.161.45.40; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU NNTP-Posting-Host: 86.161.45.40 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Finally! A Completely Open Complete FPGA Toolchain From: Jezmo Injection-Date: Wed, 05 Aug 2015 20:17:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 5 Xref: mx02.eternal-september.org comp.lang.vhdl:8447 Its the usual fantasy of the open source community that somehow open source= tools will open up unheard of advantages because you can fiddle with and p= robably break the sourcecode. It never happensin real life and like rick iI= have yet to see anything obviously broken in the code produced by major ve= ndors and I have no desire to spend months working out the inner workings o= f a program which has taken hundreds of man years to write. From newsfish@newsfish Tue Dec 29 16:43:55 2015 X-Received: by 10.50.43.231 with SMTP id z7mr1060018igl.7.1438806823380; Wed, 05 Aug 2015 13:33:43 -0700 (PDT) X-Received: by 10.140.106.247 with SMTP id e110mr134643qgf.7.1438806823311; Wed, 05 Aug 2015 13:33:43 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f3no8050390igg.0!news-out.google.com!78ni7944qge.1!nntp.google.com!69no4101382qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 5 Aug 2015 13:33:43 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.161.45.40; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU NNTP-Posting-Host: 86.161.45.40 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Subject: Finally! A Completely Open Complete FPGA Toolchain From: Jezmo Injection-Date: Wed, 05 Aug 2015 20:33:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8448 As a working engineer ive got designs to produce, my boss would not be plea= sed if I told him I was going to spend a month adding functionality to a lo= gic synthesis tool. Most FOSS advocates are software kiddies who have never= grown up and hang on every word of people such as Stallman From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 17:00:25 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 20:58:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="13365"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+OOx8NUiTH+VY4dIJzUJYI" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:9tAmFxhLIabQWKyA9euU9OoSAZM= Xref: mx02.eternal-september.org comp.lang.vhdl:8449 On 8/5/2015 3:45 PM, glen herrmannsfeldt wrote: > > Often the useful hardware implementation of an algorithm is > completely different from the usual software implementations. > It is unusual for tools to figure that out. That is pretty obvious if you give it a bit of thought. A CPU running software is a *HUGE* finite state machine (FSM) with the memory containing the majority of the state along with the fewer registers in the CPU. The memory contents are all accessed through a very large multiplexer and operations on this FSM are time multiplexed and controlled by a program stored in memory. In an FPGA or ASIC the logic can all be designed in parallel with the much less happening sequentially. The design could be done in the same way with the very large multiplexers. The program can be done with logic rather than a stored program, but the access to the large FSM still requires a lot of multiplexers. So while it is possible to duplicate the actual CPU in an FPGA, it is seldom the best way to utilize an FPGA. The same problem can be implemented with a lot fewer gates by tailoring the algorithm to take advantage of the parallel nature of the FPGA and only implementing the specific data paths required by the problem. The generic CPU gains efficiency by the repetition of the regular arrays in memory which can be made both small and cheap but only with a sequential algorithm. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 17:08:50 -0400 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 21:07:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="14353"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190JME24sV6zRYprcR/Do2h" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <717b37df-bd92-45ce-bc94-6600e872a27e@googlegroups.com> Cancel-Lock: sha1:JtHTsYUvTauXxTKxM9eOf2nVvFk= Xref: mx02.eternal-september.org comp.lang.vhdl:8450 On 8/5/2015 4:33 PM, Jezmo wrote: > As a working engineer ive got designs to produce, my boss would not be pleased if I told him I was going to spend a month adding functionality to a logic synthesis tool. Most FOSS advocates are software kiddies who have never grown up and hang on every word of people such as Stallman I'm not sure I would make any statement like that. I think FOSS is more important or at least more useful in software because it can be a complete package. With hardware it is a bit harder because the hardware itself can be difficult to make accessible in the same way. Regardless, I am not trying to argue with anyone. I was asking for a clarification of what people expect from having open source tools. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 21:22:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 42 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8451 rickman wrote: (snip, I wrote) >> Often the useful hardware implementation of an algorithm is >> completely different from the usual software implementations. >> It is unusual for tools to figure that out. > That is pretty obvious if you give it a bit of thought. A CPU running > software is a *HUGE* finite state machine (FSM) with the memory > containing the majority of the state along with the fewer registers in > the CPU. The memory contents are all accessed through a very large > multiplexer and operations on this FSM are time multiplexed and > controlled by a program stored in memory. In one of these newsgroups, a year or two ago, I called microprocessors the biggest waste of transistors, for this reason. These days, billions of transistors to funnel data through a (small number) of thousand transistor ALUs, and back out again. With systolic arrays, it is often not hard to chain together a large number of arithmetic blocks, each operating every clock cycle. > In an FPGA or ASIC the logic can all be designed in parallel with the > much less happening sequentially. The design could be done in the same > way with the very large multiplexers. The program can be done with > logic rather than a stored program, but the access to the large FSM > still requires a lot of multiplexers. So while it is possible to > duplicate the actual CPU in an FPGA, it is seldom the best way to > utilize an FPGA. The same problem can be implemented with a lot fewer > gates by tailoring the algorithm to take advantage of the parallel > nature of the FPGA and only implementing the specific data paths > required by the problem. The generic CPU gains efficiency by the > repetition of the regular arrays in memory which can be made both small > and cheap but only with a sequential algorithm. There is the assumption that some things can be done in parallel, but yes. -- glen From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder1.news.weretis.net!news.solani.org!.POSTED!not-for-mail From: Philipp Klaus Krause Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 23:30:53 +0200 Organization: solani.org Lines: 43 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: solani.org 1438810252 27887 eJwFwQkBwDAIA0BLLU8GcoAS/xJ254qL+QwOczpZdhwPUKV19mxJRe0boa5SrAsRSdg92vkDL4kRkw== (5 Aug 2015 21:30:52 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Wed, 5 Aug 2015 21:30:52 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 X-User-ID: eJwFwYEBwDAEBMCVPJ5mHCT2H6F3tEBMejCcy211hajvvdn5pJAjizDZPp/pufZSMZgqkv0DE9MQ5g== In-Reply-To: Cancel-Lock: sha1:CrMgWvf3fJbqA/FyqyIiWEY5Mmc= X-NNTP-Posting-Host: eJwFwYEBwDAEBMCVSP7RcRD2H6F3vKbWDqOBy9XKuEuMnehFb1ZPrIrAJz2FqE/lRRJ2Hn8s1xFX Xref: mx02.eternal-september.org comp.arch.fpga:22051 comp.lang.vhdl:8452 comp.lang.verilog:4049 On 05.08.2015 01:46, rickman wrote: > On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >> >> Hackability. If you have an itch, you can scratch it yourself with FOSS >> tools. If you discover a bug, you can fix it yourself. If you want to >> repurpose, optimize or otherwise change the tool, you can do it with >> FOSS. > > That's great. But only important to a small few. I use tools to get > work done. I have zero interest in digging into the code of the tools > without a real need. I have not found any bugs in the vendor's tools > that would make me want to spend weeks learning how they work in the, > most likely, vain hope that I could fix them. > > I think FOSS is great and I am very happy to see that finally happen in > an end to end toolchain for an FPGA. But it is statements like this > that I don't understand, "An open-source toolchain for the IGLOO parts > could be an unusually powerful tool in the hands of a creative > designer", or this "Because open source tools allow exploration of > techniques which are restricted using regular tools." > > Not trying to give anyone grief. I'd just like to understand what > people expect to happen with FOSS that isn't happening with the vendor's > closed, but free tools. > Same thing that's happening with compilers all the time. Just a personal example: A log time ago I decided to make a few games for the ColecoVision console. The ColecoVision uses a Z80, and at the tie all the other homebrew game developers used an old DOS eval version of IAR within Windows. I used the free sdcc compiler. Not always being happy with the generated code I started improving it, ad later became the maintainer of the Z80 port. A few years ago I joined the group for theory of computer science at the univesity in Frankfurt as a PhD student. I found that I could apply graph structure theory in compiler construction. This resulted in some quite unusual optimizations in SDCC currently not found in any other compiler. Philipp From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Wed, 05 Aug 2015 18:50:11 -0400 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 22:48:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="9073"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Sivq91JD13kVyCFo6igWt" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:L2ZgX6lxLYJC+DgSicHPAFX2iR4= Xref: mx02.eternal-september.org comp.arch.fpga:22052 comp.lang.vhdl:8453 comp.lang.verilog:4050 On 8/5/2015 5:30 PM, Philipp Klaus Krause wrote: > On 05.08.2015 01:46, rickman wrote: >> On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >>> >>> Hackability. If you have an itch, you can scratch it yourself with FOSS >>> tools. If you discover a bug, you can fix it yourself. If you want to >>> repurpose, optimize or otherwise change the tool, you can do it with >>> FOSS. >> >> That's great. But only important to a small few. I use tools to get >> work done. I have zero interest in digging into the code of the tools >> without a real need. I have not found any bugs in the vendor's tools >> that would make me want to spend weeks learning how they work in the, >> most likely, vain hope that I could fix them. >> >> I think FOSS is great and I am very happy to see that finally happen in >> an end to end toolchain for an FPGA. But it is statements like this >> that I don't understand, "An open-source toolchain for the IGLOO parts >> could be an unusually powerful tool in the hands of a creative >> designer", or this "Because open source tools allow exploration of >> techniques which are restricted using regular tools." >> >> Not trying to give anyone grief. I'd just like to understand what >> people expect to happen with FOSS that isn't happening with the vendor's >> closed, but free tools. >> > > Same thing that's happening with compilers all the time. > > Just a personal example: > A log time ago I decided to make a few games for the ColecoVision > console. The ColecoVision uses a Z80, and at the tie all the other > homebrew game developers used an old DOS eval version of IAR within > Windows. I used the free sdcc compiler. Not always being happy with the > generated code I started improving it, ad later became the maintainer of > the Z80 port. > A few years ago I joined the group for theory of computer science at the > univesity in Frankfurt as a PhD student. I found that I could apply > graph structure theory in compiler construction. This resulted in some > quite unusual optimizations in SDCC currently not found in any other > compiler. I think this is the point some are making. The examples of the utility of FOSS often point to more obscure examples which impact a relatively small number of users. I appreciate the fact that being able to tinker with the tools can be very useful to a few. But those few must have the need as well as the ability. With hardware development both are less likely to happen. Maybe I just don't have enough imagination. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 18:58:03 -0400 Organization: A noiseless patient Spider Lines: 61 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 22:56:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="10092"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Laq0u8116h1ryMoOSQ4q3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:CJlB8QTR5VU+ZnoUnq+B/cNbWZQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8454 On 8/5/2015 5:22 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> Often the useful hardware implementation of an algorithm is >>> completely different from the usual software implementations. >>> It is unusual for tools to figure that out. > >> That is pretty obvious if you give it a bit of thought. A CPU running >> software is a *HUGE* finite state machine (FSM) with the memory >> containing the majority of the state along with the fewer registers in >> the CPU. The memory contents are all accessed through a very large >> multiplexer and operations on this FSM are time multiplexed and >> controlled by a program stored in memory. > > In one of these newsgroups, a year or two ago, I called > microprocessors the biggest waste of transistors, for this reason. > > These days, billions of transistors to funnel data through a > (small number) of thousand transistor ALUs, and back out again. A very efficient use of the ALU while wasting so many elements in the memory mux. In reality the comparison is cost vs. the application needs. Often the things that need to be done can be done sequentially, even when they appear to be done in parallel. So while an FPGA may more fully utilize the transistor count, it often wastes the performance capabilities of those transistors while a CPU more fully exploits them. > With systolic arrays, it is often not hard to chain together a > large number of arithmetic blocks, each operating every clock cycle. > >> In an FPGA or ASIC the logic can all be designed in parallel with the >> much less happening sequentially. The design could be done in the same >> way with the very large multiplexers. The program can be done with >> logic rather than a stored program, but the access to the large FSM >> still requires a lot of multiplexers. So while it is possible to >> duplicate the actual CPU in an FPGA, it is seldom the best way to >> utilize an FPGA. The same problem can be implemented with a lot fewer >> gates by tailoring the algorithm to take advantage of the parallel >> nature of the FPGA and only implementing the specific data paths >> required by the problem. The generic CPU gains efficiency by the >> repetition of the regular arrays in memory which can be made both small >> and cheap but only with a sequential algorithm. > > There is the assumption that some things can be done in parallel, > but yes. Perhaps "parallel" is not the best term. In hardware they would be called concurrent. That doesn't mean the output of one isn't the input of another. It just means the two operations are working at the same time on separate hardware whether or not they are actually doing anything useful all the time. There are many ways to compare solutions to computing needs. Many like the familiarity of CPUs (every problem looks like a nail) while others like the flexibility of FPGAs (Swiss army knife). -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 5 Aug 2015 23:50:45 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 50 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8455 rickman wrote: (snip, I wrote) >> In one of these newsgroups, a year or two ago, I called >> microprocessors the biggest waste of transistors, for this reason. >> These days, billions of transistors to funnel data through a >> (small number) of thousand transistor ALUs, and back out again. > A very efficient use of the ALU while wasting so many elements in the > memory mux. In reality the comparison is cost vs. the application > needs. Often the things that need to be done can be done sequentially, > even when they appear to be done in parallel. So while an FPGA may more > fully utilize the transistor count, it often wastes the performance > capabilities of those transistors while a CPU more fully exploits them. Yes. I was thinking about using either a microprocessor or FPGA to build a digital clock. In either case, a large fraction of the time there is nothing to do. (That is, relative to the switch rate.) Our home computers spend most of the time not doing anything useful. >> With systolic arrays, it is often not hard to chain together a >> large number of arithmetic blocks, each operating every clock cycle. >>> In an FPGA or ASIC the logic can all be designed in parallel with the >>> much less happening sequentially. The design could be done in the same >>> way with the very large multiplexers. The program can be done with >>> logic rather than a stored program, but the access to the large FSM >>> still requires a lot of multiplexers. (snip) >> There is the assumption that some things can be done in parallel, >> but yes. > Perhaps "parallel" is not the best term. In hardware they would be > called concurrent. That doesn't mean the output of one isn't the input > of another. It just means the two operations are working at the same > time on separate hardware whether or not they are actually doing > anything useful all the time. > There are many ways to compare solutions to computing needs. Many like > the familiarity of CPUs (every problem looks like a nail) while others > like the flexibility of FPGAs (Swiss army knife). Interesting way to say it. -- glen From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Wed, 05 Aug 2015 20:00:57 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 5 Aug 2015 23:59:25 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c3dfb0c42f2565cb68aa569be809f91b"; logging-data="22222"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18V807dWXQrexTnx5sra637" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:C9G8E8j820TXjwX8zaejCWDlf+8= Xref: mx02.eternal-september.org comp.lang.vhdl:8456 On 8/5/2015 7:50 PM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip, I wrote) >>> In one of these newsgroups, a year or two ago, I called >>> microprocessors the biggest waste of transistors, for this reason. > >>> These days, billions of transistors to funnel data through a >>> (small number) of thousand transistor ALUs, and back out again. > >> A very efficient use of the ALU while wasting so many elements in the >> memory mux. In reality the comparison is cost vs. the application >> needs. Often the things that need to be done can be done sequentially, >> even when they appear to be done in parallel. So while an FPGA may more >> fully utilize the transistor count, it often wastes the performance >> capabilities of those transistors while a CPU more fully exploits them. > > Yes. I was thinking about using either a microprocessor or FPGA > to build a digital clock. In either case, a large fraction of the > time there is nothing to do. (That is, relative to the switch rate.) Does the clock need to do anything special? Why a custom clock? >> There are many ways to compare solutions to computing needs. Many like >> the familiarity of CPUs (every problem looks like a nail) while others >> like the flexibility of FPGAs (Swiss army knife). > > Interesting way to say it. Sometimes it is hard to find a reasonable analogy. This one is as good as any I guess. Analogies have lots of compression, only so much fidelity. How's that for a metaphor? -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Aleksandar Kuktin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Finally! A Completely Open Complete FPGA Toolchain Date: Sat, 8 Aug 2015 16:42:36 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 66 Message-ID: References: <20150728205548.1ede5368@HP-6550b> <20150729105009.412968bf@HP-6550b> NNTP-Posting-Host: ahs5SQI0OQwb4BmKmMxtWg.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@aioe.org User-Agent: Pan/0.135 (Tomorrow I'll Wake Up and Scald Myself with Tea; Unknown) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.arch.fpga:22066 comp.lang.vhdl:8457 comp.lang.verilog:4051 The quoted post has beed turned upside-down for the purposes of my typing. On Wed, 05 Aug 2015 18:50:11 -0400, rickman wrote: > Maybe I just don't have enough imagination. A distinct possibility. On Wed, 05 Aug 2015 18:50:11 -0400, rickman wrote: > On 8/5/2015 5:30 PM, Philipp Klaus Krause wrote: >> On 05.08.2015 01:46, rickman wrote: >>> On 8/4/2015 7:05 PM, Aleksandar Kuktin wrote: >>>> >>>> Hackability. If you have an itch, you can scratch it yourself with >>>> FOSS tools. If you discover a bug, you can fix it yourself. If you >>>> want to repurpose, optimize or otherwise change the tool, you can do >>>> it with FOSS. >>> >>> That's great. But only important to a small few. Few matter. How many ISA designers are there? Yet, if they get good tools that let them creatively hack out the solution, we're all better of. Same with random dudes banging on some FPGA somewhere. You never know where the next thing you want will appear, and having good peer-reviewed tools creates more potential for good stuff to be made. >>> I use tools to get work done. I have zero interest in digging into >>> the code of the tools without a real need. I have not found any bugs >>> in the vendor's tools that would make me want to spend weeks learning >>> how they work in the, most likely, vain hope that I could fix them. Maybe you just didn't try hard enough? Maybe you did but didn't notice you found a gaping bug in vendor tools. >>> Not trying to give anyone grief. I'd just like to understand what >>> people expect to happen with FOSS that isn't happening with the >>> vendor's closed, but free tools. Maybe you would be able to generate a FPGA handheld device that can reconfigure itself on the fly. Like a smartphone^H^H^H^H^H^H^H^H^H^H PDA^H^H^H trikoder that runs on some energy-efficient MIPS and that has a scriptable (meaning CLI) synthesizer that you can feed random Verilog sources and then instantiate an Ethernet device so you can jack yourself in while at home, a FM radio to listen to while driving down the road, a TV receiver with HDMA output so you can view the news and maybe a vibrator or something for the evening. Anyway, that's what I want to have and can't right now but COULD have with FOSS tools (since I'm not gonna use QEMU to instantiate a VM so I could synthesize on my phone). >> This resulted in some quite unusual optimizations in SDCC currently >> not found in any other compiler. Okay, now we need to check out SDCC. > I think this is the point some are making. The examples of the utility > of FOSS often point to more obscure examples which impact a relatively > small number of users. I appreciate the fact that being able to tinker > with the tools can be very useful to a few. But those few must have the > need as well as the ability. > With hardware development both are less likely to happen. But they will happen nevertheless. From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.50.142.39 with SMTP id rt7mr8145094igb.5.1439141425119; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) X-Received: by 10.140.96.138 with SMTP id k10mr172128qge.18.1439141424996; Sun, 09 Aug 2015 10:30:24 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!se8no1087996igc.0!news-out.google.com!78ni9027qge.1!nntp.google.com!69no4677791qgl.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:30:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:30:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8458 I tried to convert it but i face many difficulties: with small code i done it without problem, but with more complexity code i found a lot of errors From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.50.178.165 with SMTP id cz5mr8155766igc.10.1439141425295; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) X-Received: by 10.140.47.80 with SMTP id l74mr110542qga.42.1439141425175; Sun, 09 Aug 2015 10:30:25 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!news.glorb.com!se8no1088002igc.0!news-out.google.com!78ni9030qge.1!nntp.google.com!z61no6041603qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:30:24 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0db7e6e7-3dec-429b-af4a-121f08f5ef13@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:30:25 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8459 I tried to convert it but i face many difficulties: with small code i done it without problem, but with more complexity code i found a lot of errors From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.129.111.132 with SMTP id k126mr15883846ywc.10.1439141994826; Sun, 09 Aug 2015 10:39:54 -0700 (PDT) X-Received: by 10.140.20.147 with SMTP id 19mr155621qgj.20.1439141994788; Sun, 09 Aug 2015 10:39:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z61no6042543qge.0!news-out.google.com!78ni9030qge.1!nntp.google.com!z61no6042540qge.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 9 Aug 2015 10:39:54 -0700 (PDT) In-Reply-To: <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.41.219; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.41.219 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Sun, 09 Aug 2015 17:39:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 1 Xref: mx02.eternal-september.org comp.lang.vhdl:8460 I have this feature "HDL Coder" but as what i said i found a lot of errors and tired from tying without got any result. From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.68.238.74 with SMTP id vi10mr25131348pbc.9.1439304160896; Tue, 11 Aug 2015 07:42:40 -0700 (PDT) X-Received: by 10.140.81.38 with SMTP id e35mr278170qgd.3.1439304160654; Tue, 11 Aug 2015 07:42:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no1983760igc.0!news-out.google.com!78ni9206qge.1!nntp.google.com!69no317381qgi.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 11 Aug 2015 07:42:40 -0700 (PDT) In-Reply-To: <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: About fpga board From: Thomas Stanka Injection-Date: Tue, 11 Aug 2015 14:42:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8461 Am Sonntag, 9. August 2015 19:39:57 UTC+2 schrieb abdrh...@gmail.com: > I have this feature "HDL=20 > Coder" but as what i said i found a lot of errors and tired from tying wi= thout got any result. I know how to read and detected that there is a library containing books, w= hat can I do to transplantate a human heart within 2 months? The only reasonable answer is to spend your time finding an expert to do th= is task.=20 Two month is an extrem small time to bring an unspecified project from Matl= ab to FPGA. Depending on the constraints, even a group of experts might hav= e trouble with this task. Ofc if you design is "Hello World"-Style, we can = help you teaching yourself to do this within 2 months, but as you already w= rote you lack fundamental prerequisites and detected your problem is more c= omplex than a simple example. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.141.28.206 with SMTP id f197mr4680291qhe.10.1439371937962; Wed, 12 Aug 2015 02:32:17 -0700 (PDT) X-Received: by 10.140.20.56 with SMTP id 53mr266997qgi.9.1439371937948; Wed, 12 Aug 2015 02:32:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!69no545002qgi.0!news-out.google.com!b31ni6180qge.0!nntp.google.com!y105no14692qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 12 Aug 2015 02:32:17 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=188.135.47.199; posting-account=jOAqcwoAAAA7WE2jPQ3PDmhfuWWej7Jx NNTP-Posting-Host: 188.135.47.199 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <94785a02-8002-4ebb-93a3-0fc5fa39bb6a@googlegroups.com> Subject: Re: About fpga board From: abdrhblushi@gmail.com Injection-Date: Wed, 12 Aug 2015 09:32:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8462 I understood what you said , I need long time to learn it, but yes i said t= hat i will learn it in two month, by that i mean i want to do this task wit= hin two month, but as what i understand from discussion it is also difficul= t, also the problem i cant send shot screen to this group, to allow you to = know what i am doing and what is the problem i faced, i am here because i n= eed help to do this task, it is clear that who are in this group have good = knowledge in fpga board, anyone feel he can help me please make me know tha= t by sending email on=20 abdrhblushi@gmail.com With regards From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Fri, 14 Aug 2015 22:46:02 -0400 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 15 Aug 2015 02:44:20 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="23795"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19T7cKEKJgQC42KDd2c+vQv" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:GdkOdUfoalZhZYwKnfoWQJ829gQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8463 On 8/11/2015 10:42 AM, Thomas Stanka wrote: > Am Sonntag, 9. August 2015 19:39:57 UTC+2 schrieb abdrh...@gmail.com: >> I have this feature "HDL >> Coder" but as what i said i found a lot of errors and tired from tying without got any result. > > I know how to read and detected that there is a library containing books, what can I do to transplantate a human heart within 2 months? > > The only reasonable answer is to spend your time finding an expert to do this task. > Two month is an extrem small time to bring an unspecified project from Matlab to FPGA. Depending on the constraints, even a group of experts might have trouble with this task. Ofc if you design is "Hello World"-Style, we can help you teaching yourself to do this within 2 months, but as you already wrote you lack fundamental prerequisites and detected your problem is more complex than a simple example. I think the difficulty of coding HDL is a bit overstated. I think anyone with familiarity with coding in general can port a matlab program to an FPGA in two months. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: About fpga board Date: Sat, 15 Aug 2015 04:27:19 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8464 rickman wrote: > On 8/11/2015 10:42 AM, Thomas Stanka wrote: (snip) >> Two month is an extrem small time to bring an unspecified >> project from Matlab to FPGA. Depending on the constraints, >> even a group of experts might have trouble with this task. >> Ofc if you design is "Hello World"-Style, we can help you >> teaching yourself to do this within 2 months, but as you >> already wrote you lack fundamental prerequisites and detected >> your problem is more complex than a simple example. > I think the difficulty of coding HDL is a bit overstated. I think > anyone with familiarity with coding in general can port a > matlab program to an FPGA in two months. Some people who are good at writing sequential software have a hard time thinking in terms of hardware and writing HDL. There are many things that can be written in Matlab that are easy to write in HDL, and many that are hard. Some might not be hard, but are hard if you want them to run fast, which is often the reason for a hardware implementation. -- glen From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.129.74.3 with SMTP id x3mr807913ywa.34.1439812413670; Mon, 17 Aug 2015 04:53:33 -0700 (PDT) X-Received: by 10.140.25.144 with SMTP id 16mr7761qgt.41.1439812413652; Mon, 17 Aug 2015 04:53:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!69no1628857qgi.0!news-out.google.com!78ni14231qge.1!nntp.google.com!y105no1099077qge.1!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 17 Aug 2015 04:53:33 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <044d978d-f183-4476-a6c7-0089502b4fcd@googlegroups.com> <43765a10-9646-4b4e-a064-a83b407ab458@googlegroups.com> <67767811-e543-4e4d-866b-ff83df39122e@googlegroups.com> <40fb6463-9e28-4070-a167-042a3bb15a32@googlegroups.com> <5ac6e15c-52cb-497b-a528-f695c27f51d0@googlegroups.com> <217df4db-e608-4e24-a844-74ebf77401ce@googlegroups.com> <5a95b096-6312-44b1-b596-bf4ef3df88a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <89930d0c-f240-41a9-b201-3c2d1fb34f95@googlegroups.com> Subject: Re: About fpga board From: Thomas Stanka Injection-Date: Mon, 17 Aug 2015 11:53:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8465 Am Samstag, 15. August 2015 04:46:05 UTC+2 schrieb rickman: > I think the difficulty of coding HDL is a bit overstated. I think > anyone with familiarity with coding in general can port a matlab program > to an FPGA in two months. That clearly depends on difficulty of design, which none of us can tell. Converting something well structured or very small projects will often take less than 2 months. But matlab from people knowing nothing about digital design tend to be in the other complexity class. I saw FPGA designs for which 2 months were not enough to bring ready verified RTL (written by experienced designer) to functioning bitstream because of hard constraints. regards, Thomas From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.107.28.2 with SMTP id c2mr7221955ioc.16.1439921993642; Tue, 18 Aug 2015 11:19:53 -0700 (PDT) X-Received: by 10.182.116.197 with SMTP id jy5mr54485obb.24.1439921993540; Tue, 18 Aug 2015 11:19:53 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no6049515igc.0!news-out.google.com!o13ni16197igw.0!nntp.google.com!x6no1841674igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Aug 2015 11:19:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:282:900:3419:543d:1533:f14f:4757; posting-account=qZLM8QoAAACRAs_14Hx_kIEfoLk6dWLT NNTP-Posting-Host: 2601:282:900:3419:543d:1533:f14f:4757 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: kevin.m.neilson@gmail.com Injection-Date: Tue, 18 Aug 2015 18:19:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8466 This is one of the most nonsensical things I've ever heard. From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 19:05:58 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 16 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8467 kevin.m.neilson@gmail.com wrote: > This is one of the most nonsensical things I've ever heard. Is this supposed to be a question? OK, my news reader cuts of the subject line. If you put something in the subject line related to the question, also put it in the message. For most uses, you want a specific width. A better question is why std_logic instead of bit. (And why does std_logic have to be so long, and have a _ in it.) -- glen From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.182.142.72 with SMTP id ru8mr7742630obb.47.1439928718246; Tue, 18 Aug 2015 13:11:58 -0700 (PDT) X-Received: by 10.182.114.196 with SMTP id ji4mr56478obb.11.1439928718219; Tue, 18 Aug 2015 13:11:58 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!x6no1873106igd.0!news-out.google.com!o13ni16208igw.0!nntp.google.com!x6no1873105igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 18 Aug 2015 13:11:57 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: KJ Injection-Date: Tue, 18 Aug 2015 20:11:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1815 X-Received-Body-CRC: 3984828630 Xref: mx02.eternal-september.org comp.lang.vhdl:8468 On Tuesday, August 18, 2015 at 3:06:02 PM UTC-4, glen herrmannsfeldt wrote: > kev....neilson@gmail.... wrote: > > > This is one of the most nonsensical things I've ever heard. > > Is this supposed to be a question? > > OK, my news reader cuts of the subject line. If you put something > in the subject line related to the question, also put it in the message. > It was a question (asked and answered) back in Feb 2013 when the thread was first started...no idea what today's post is supposed to be about. KJ From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 20:21:51 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 18 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8469 KJ wrote: (snip, I wrote) >> OK, my news reader cuts of the subject line. If you put something >> in the subject line related to the question, also put it in the message. > It was a question (asked and answered) back in Feb 2013 when the > thread was first started...no idea what today's post is supposed > to be about. As I mostly write for synthesis, and not simulation, I have wondered why use std_logic instead of bit. My newsreader cut of the subject until I did the reply, when I saw the whole subject. It does sometimes bother me that VHDL makes the conversion between bit_vector and unsigned so complicated. (Compared to verilog.) -- glen From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Tue, 18 Aug 2015 16:28:02 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 18 Aug 2015 20:26:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="303e81565e2b5fa7258cbfe788d7b00f"; logging-data="14051"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y1Lu8S54+07O6qrMX/W0b" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: Cancel-Lock: sha1:38k1gYygUrKzjnHgg+H95PAmJ0c= Xref: mx02.eternal-september.org comp.lang.vhdl:8470 On 8/18/2015 4:21 PM, glen herrmannsfeldt wrote: > KJ wrote: > > (snip, I wrote) >>> OK, my news reader cuts of the subject line. If you put something >>> in the subject line related to the question, also put it in the message. > >> It was a question (asked and answered) back in Feb 2013 when the >> thread was first started...no idea what today's post is supposed >> to be about. > > As I mostly write for synthesis, and not simulation, I have wondered > why use std_logic instead of bit. My newsreader cut of the subject > until I did the reply, when I saw the whole subject. > > It does sometimes bother me that VHDL makes the conversion between > bit_vector and unsigned so complicated. (Compared to verilog.) VHDL lets you make it a simple function call. You just need to create the function. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.68.230.100 with SMTP id sx4mr6612917pbc.4.1440164148500; Fri, 21 Aug 2015 06:35:48 -0700 (PDT) X-Received: by 10.50.66.129 with SMTP id f1mr54061igt.4.1440164148463; Fri, 21 Aug 2015 06:35:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no7701965igc.0!news-out.google.com!nt1ni10918igb.0!nntp.google.com!x6no2910786igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Aug 2015 06:35:47 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <46d978ab-8e1a-48ef-abed-a0efd9f55e28@googlegroups.com> <51049893-e2c3-4d93-afa4-425686c77924@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <470db89a-ba52-4a18-bc39-c7cd40ea6dc2@googlegroups.com> Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? From: Andy Injection-Date: Fri, 21 Aug 2015 13:35:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8471 On Tuesday, August 18, 2015 at 3:21:56 PM UTC-5, glen herrmannsfeldt wrote: > > It does sometimes bother me that VHDL makes the conversion between > bit_vector and unsigned so complicated. (Compared to verilog.) > > -- glen Use numeric_bit or numeric_bit_unsigned packages from the IEEE library. The latter defines arithmetic operators and conversions to/from integer for bit_vector. The former defines signed/unsigned types as unconstrained arrays of bit, closely related (and easily converted) to bit_vector, along with to/from integer conversion and arithmetic operators. All standard IEEE HVDL since 2008. Andy From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.182.29.70 with SMTP id i6mr7525351obh.27.1440178407154; Fri, 21 Aug 2015 10:33:27 -0700 (PDT) X-Received: by 10.50.147.39 with SMTP id th7mr90127igb.12.1440178407132; Fri, 21 Aug 2015 10:33:27 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!se8no7825601igc.0!news-out.google.com!nt1ni11079igb.0!nntp.google.com!x6no2994162igd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 21 Aug 2015 10:33:26 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=178.61.0.144; posting-account=4HDlsQoAAAB7P7nl9cc1e3iTy9R8VKWM NNTP-Posting-Host: 178.61.0.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com> Subject: Re: C\C++ to VHDL Converter From: ahmedablak0@gmail.com Injection-Date: Fri, 21 Aug 2015 17:33:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8472 On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote: > Hi all VHDL experts, > Is there any tools which can convert a C\C++ source file to VHDL . For > example If I have a C source code for a MP3 decoder , Can any tool can > convert it into VHDL equivalent. There is some facility in FPGA Advantage to > generate a wrapper VHDL for a C File , what exactly is that ? Does that > mean I can synthesize a C\C++ file by creating a VHDL Wrapper. > Please help Take a look at Handel-C. All you have to do is to rewrite couple of statements so that Handel-C compiles and generates VHDL, Verilog, EDIF, and SystemC for you. Use Mentor Graphic DK Design Suite 5. From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why ever use std_logic_vector intead of signed/unsigned? Date: Fri, 21 Aug 2015 14:16:00 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <994c3db1-197b-4657-b93b-211e473cdaef@googlegroups.com> <20130220165402.16675481@rg.highlandtechnology.com> <20130221101935.684c8a5c@rg.highlandtechnology.com> <1443d209-9f02-4550-b9dd-e141899701c0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 21 Aug 2015 18:14:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="5409ba4ff362da07b493a33fe9fa84b5"; logging-data="26548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1813x4L3OxZLbPv861KalBa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 In-Reply-To: <1443d209-9f02-4550-b9dd-e141899701c0@googlegroups.com> Cancel-Lock: sha1:r+V3C7kO2JVPAhxaMfaJ7hvHQE0= Xref: mx02.eternal-september.org comp.lang.vhdl:8473 On 2/22/2013 11:40 AM, kevin.neilson@xilinx.com wrote: > This is the idea I'm getting. I haven't gotten a good answer about > why I should ever use slv, and I'm getting the idea it's only still > around because of inertia. The responses seem to be: > 1. SLV is better *because* of its limitations. You *could* use > signed/unsigned, but why, when you could use something that does even > less? > 2. But wait: with the new 2008 libraries, SLV is about as > good as signed/unsigned. (So why not just use signed/unsigned?) > 3. Other cores like CoreGen cores will use SLV, so you have to also in > order to interface them. (This is valid, although I try to avoid > CoreGen when possible, and I can always convert, possibly even in the > instantiation with 2008.) I don't really understand your questions. Why do you care what others think of the various types? I can assure you that there is no "intent" to the types other than what they *can* be used for. I have discussed similar issues with some of the people who worked on the VHDL standard and they aren't thinking of all the details of how you will want to use the language. Their intent was to give a framework within which you can do *lots* of things with minimal limitations but lots of protection. -- Rick From newsfish@newsfish Tue Dec 29 16:43:56 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: "Tomas D." Newsgroups: comp.lang.vhdl Subject: Re: C\C++ to VHDL Converter Date: Sat, 22 Aug 2015 15:40:29 +0100 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com> Injection-Date: Sat, 22 Aug 2015 14:38:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="d2848e2cfbf3375876b534c8a8ca5fdd"; logging-data="31444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19s2D6wG9kH1u3UjS1zwlgw" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.2180 Cancel-Lock: sha1:+KZYa0neZm8QgwIDa/GL9H+ldBs= X-Priority: 3 X-MSMail-Priority: Normal Xref: mx02.eternal-september.org comp.lang.vhdl:8474 wrote in message news:0ae05f82-6d7f-49f9-9b00-1da23034e98c@googlegroups.com... > On Tuesday, September 17, 2002 at 12:27:21 PM UTC+3, DJohn wrote: >> Hi all VHDL experts, >> Is there any tools which can convert a C\C++ source file to VHDL . For >> example If I have a C source code for a MP3 decoder , Can any tool can >> convert it into VHDL equivalent. There is some facility in FPGA Advantage >> to >> generate a wrapper VHDL for a C File , what exactly is that ? Does that >> mean I can synthesize a C\C++ file by creating a VHDL Wrapper. >> Please help > > Take a look at Handel-C. All you have to do is to rewrite couple of > statements so that Handel-C compiles and generates VHDL, Verilog, EDIF, > and SystemC for you. Use Mentor Graphic DK Design Suite 5. Why not to have a look at Vivado HLS? Altera also has something, that will be available soon. From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.50.3.97 with SMTP id b1mr18290137igb.10.1440410689025; Mon, 24 Aug 2015 03:04:49 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr218914igx.15.1440410689009; Mon, 24 Aug 2015 03:04:49 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!se8no9362804igc.0!news-out.google.com!nt1ni13533igb.0!nntp.google.com!se8no9362800igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Aug 2015 03:04:48 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 24 Aug 2015 10:04:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8475 Hi, I've now added an example and made some smaller modification to simplify us= ing BVUL check and logging functionality with VUnit. The example testbench = (https://github.com/LarsAsplund/vunit/blob/bitvis-utility-library-integrati= on/examples/vhdl/bvul_integration/test/tb_bvul_integration.vhd) has a lot o= f comments so you can just read it to get the basic idea. If you have any c= omments you can post them with the BVUL integration issue (https://github.c= om/LarsAsplund/vunit/issues/54) or comment the code itself (https://github.= com/LarsAsplund/vunit/commit/ccd6ec83e3ff95d3518834eb9864298769621f47). The best way is of course to test it out for real. If you're new to VUnit y= ou can download and run the example like this git clone https://github.com/LarsAsplund/vunit.git cd vunit git checkout bitvis-utility-library-integration cd examples\vhdl\bvul_integration python run.py -b If you want to start out just using your simulator like you're used to you = can compile everything with the run script. python run.py -b --comp= ile In the bvul_integration directory you'll find vunit_out which contains the = compiled output. For example, vunit_out/modelsim is the directory to go to = if you're using ModelSim. The testbench is compiled into library lib.=20 The example is currently on its own branch, I will leave it there for a whi= le to see if there are any comments. After that I'll merge it to the VUnit = mainline. /Lars From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.13.203.77 with SMTP id n74mr22073590ywd.35.1440411012499; Mon, 24 Aug 2015 03:10:12 -0700 (PDT) X-Received: by 10.50.79.193 with SMTP id l1mr221426igx.2.1440411012398; Mon, 24 Aug 2015 03:10:12 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!69no3202584qgi.0!news-out.google.com!nt1ni13533igb.0!nntp.google.com!se8no9365147igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 24 Aug 2015 03:10:11 -0700 (PDT) In-Reply-To: <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=195.33.129.54; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 195.33.129.54 References: <1715f49c-b629-4c90-b3d2-3cf18c9c9a09@googlegroups.com> <3eb21a51-bd9a-43d2-9539-bce7a0c0212c@googlegroups.com> <818ec8f7-3658-47e4-982d-3c7c9db17083@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: The best VHDL library around for basic testbench checking functionality is free - and open source From: Lars Asplund Injection-Date: Mon, 24 Aug 2015 10:10:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 2 Xref: mx02.eternal-september.org comp.lang.vhdl:8476 Note that you need a Github account to be able to create comments. /Lars From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.50.164.133 with SMTP id yq5mr3489665igb.1.1440690275897; Thu, 27 Aug 2015 08:44:35 -0700 (PDT) X-Received: by 10.50.22.103 with SMTP id c7mr97643igf.13.1440690275806; Thu, 27 Aug 2015 08:44:35 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.glorb.com!u8no1072252igq.0!news-out.google.com!nt1ni16645igb.0!nntp.google.com!u8no1072241igq.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 27 Aug 2015 08:44:35 -0700 (PDT) In-Reply-To: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=101.222.169.101; posting-account=Z5mP8goAAAC1q1CatkgJob_1UBro830S NNTP-Posting-Host: 101.222.169.101 References: <916391a6-2482-430d-9766-f1807b3139fc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: ethernet on spartan 3an From: lavanya.vlsi@gmail.com Injection-Date: Thu, 27 Aug 2015 15:44:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8477 Hello... Im lavanya working on ethernet of spartan 3 series .. I need the reference design of your code for my interfacing with my module in project.. Please u have also some questions but if i have reference design den i can work with my ip core code... Im also using a RTL code gof ethernet...i have completed its but im facing no communication between PC and FPGA Please kindly provide a referece code to me. Thanks & regards Lavanya From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.129.71.10 with SMTP id u10mr32269593ywa.51.1441236551960; Wed, 02 Sep 2015 16:29:11 -0700 (PDT) X-Received: by 10.50.221.104 with SMTP id qd8mr25357igc.1.1441236551912; Wed, 02 Sep 2015 16:29:11 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no346892qge.1!news-out.google.com!nt1ni22621igb.0!nntp.google.com!kq10no857259igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 2 Sep 2015 16:29:11 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.31.106.34 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: "N." Injection-Date: Wed, 02 Sep 2015 23:29:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 25 Xref: mx02.eternal-september.org comp.lang.vhdl:8478 Hello, I'm trying to port a very old design that had formerly used the deprecated = STD_LOGIC_ARITH library with the new NUMERIC_STD library.=20 The old design has a substantial amount of unsigned additions of the follow= ing format :=20 c_slv <=3D a_slv + b_slv; or=20 c_slv <=3D a_slv + 10; I realize I should probably go through all of the code and recast it all to= "unsigned" to make it play nice with numeric_std, but was curious if it wa= s still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUMER= IC_STD. As far as I can tell, it doesn't look like the overloaded functions= will conflict at all. PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUMER= IC_STD_UNSIGNED is out. Thanks. From newsfish@newsfish Tue Dec 29 16:43:56 2015 X-Received: by 10.66.122.102 with SMTP id lr6mr43713356pab.44.1441286436858; Thu, 03 Sep 2015 06:20:36 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr159240igg.16.1441286436815; Thu, 03 Sep 2015 06:20:36 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no825495igb.0!news-out.google.com!nt1ni23135igb.0!nntp.google.com!kq10no1102915igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 06:20:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.75.45; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.75.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: Jim Lewis Injection-Date: Thu, 03 Sep 2015 13:20:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8479 std_logic_unsigned will work fine with Numeric_std. Actually for a little humor, there are conflicts between std_logic_arith an= d std_logic_unsigned which cause ambiguity that do not exist in numeric_std= . Hence, not only does it work with numeric_std, it works better with nume= ric_std than with std_logic_arith. :) My rule for RTL is that if it is math, it should be in either type signed o= r unsigned. =20 I also try to keep a pragmatic rule for updates and do not change old code = unless it uses type unsigned or signed as a port or something internal to i= t is changing and there value to switching to the numeric_std package - ie:= this block is going to be around for quite some time in the future. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.52.107.106 with SMTP id hb10mr25543640vdb.1.1441292246461; Thu, 03 Sep 2015 07:57:26 -0700 (PDT) X-Received: by 10.50.152.6 with SMTP id uu6mr174800igb.4.1441292246423; Thu, 03 Sep 2015 07:57:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no472133qge.0!news-out.google.com!nt1ni23183igb.0!nntp.google.com!kq10no1145240igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 07:57:25 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=xwpbfwoAAADIe9Ai8BOQAnMovPUEIm-Y NNTP-Posting-Host: 192.35.35.35 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <05177f6e-3595-4590-9570-403e1359dc1a@googlegroups.com> Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: "N." Injection-Date: Thu, 03 Sep 2015 14:57:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8480 On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote: > std_logic_unsigned will work fine with Numeric_std. >=20 > Actually for a little humor, there are conflicts between std_logic_arith = and std_logic_unsigned which cause ambiguity that do not exist in numeric_s= td. Hence, not only does it work with numeric_std, it works better with nu= meric_std than with std_logic_arith. :) >=20 > My rule for RTL is that if it is math, it should be in either type signed= or unsigned. =20 >=20 > I also try to keep a pragmatic rule for updates and do not change old cod= e unless it uses type unsigned or signed as a port or something internal to= it is changing and there value to switching to the numeric_std package - i= e: this block is going to be around for quite some time in the future. Thanks Jim.=20 My design's ports are still set at std_logic and std_logic_vector, mainly d= ue to the fact that the numerous cores I'm using generated by CoreGen are s= till using this convention. I will think about converting the math related = ports to unsigned/signed for future designs. BTW, I enjoyed your write-up on VHDL math tricks :) Very good reference. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.32.212 with SMTP id g203mr472828iog.25.1441305242766; Thu, 03 Sep 2015 11:34:02 -0700 (PDT) X-Received: by 10.50.50.101 with SMTP id b5mr199836igo.12.1441305242709; Thu, 03 Sep 2015 11:34:02 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no5022igb.0!news-out.google.com!f6ni14igi.0!nntp.google.com!kq10no5017igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 3 Sep 2015 11:34:01 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.42 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c97d2e0-49ab-45f9-9c70-c6654841f8d2@googlegroups.com> Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: Andy Injection-Date: Thu, 03 Sep 2015 18:34:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8481 On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote: > My rule for RTL is that if it is math, it should be in either type signed or unsigned. Agreed, and I would add the IEEE VHDL fixed point types (ufixed or sfixed) and floating point type (float) to that list. Andy From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.157.11 with SMTP id g11mr4235035ioe.7.1441384418065; Fri, 04 Sep 2015 09:33:38 -0700 (PDT) X-Received: by 10.50.30.197 with SMTP id u5mr71123igh.5.1441384418049; Fri, 04 Sep 2015 09:33:38 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!kq10no516469igb.0!news-out.google.com!nt1ni919igb.0!nntp.google.com!kq10no516463igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Sep 2015 09:33:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> Subject: PSL syntax help From: niv Injection-Date: Fri, 04 Sep 2015 16:33:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 33 Xref: mx02.eternal-september.org comp.lang.vhdl:8482 Hi, I'm trying to get a PSL vunit to work, but having some trouble (as usual)! (I'm using Modelsim 10.1d) The vunit is as follows: vunit interface_check (iface(struct)) { default clock is clk; assert never {wren AND fifo_full}; -- works OK. assert never {rden AND fifo_empty}; -- works OK. assert always (req -> next[2](gnt)); -- works OK. assert always (req -> next[3](gnt)); -- works OK. assert always (req -> next[4](gnt)); -- works OK. assert always (req -> next[5](gnt)); -- works OK. -- BUT, I should be able to replace above 4 lines with something like: assert always (req -> next[*2..5](gnt)); -- which does not compile. -- OR assert always (req -> next[*2:5](gnt)); -- which does not compile. } Could someone please explain what I'm doing wrong? I've tried all sorts of minor variations, but can't get the composite assertion to compile. Regards, Niv. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.182.241.72 with SMTP id wg8mr5367365obc.2.1441399634701; Fri, 04 Sep 2015 13:47:14 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr93349igt.10.1441399634644; Fri, 04 Sep 2015 13:47:14 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.glorb.com!kq10no546571igb.0!news-out.google.com!f6ni1090igi.0!nntp.google.com!kq10no642674igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 4 Sep 2015 13:47:13 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=197.210.224.219; posting-account=2PprfAoAAADxNzeuAYJhBnpsN-StXr74 NNTP-Posting-Host: 197.210.224.219 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Subject: pls i need a vhdl code for a 16bit slicer From: Aderemi Injection-Date: Fri, 04 Sep 2015 20:47:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8483 pls i need a vhdl code for a 16bit slicer From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.50.50.179 with SMTP id d19mr8556904igo.6.1441456997982; Sat, 05 Sep 2015 05:43:17 -0700 (PDT) X-Received: by 10.50.72.16 with SMTP id z16mr26985igu.8.1441456997925; Sat, 05 Sep 2015 05:43:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no916131igb.0!news-out.google.com!f6ni1733igi.0!nntp.google.com!kq10no730602igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 05:43:17 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:f074:1ce8:5191:5aa; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:f074:1ce8:5191:5aa References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: pls i need a vhdl code for a 16bit slicer From: KJ Injection-Date: Sat, 05 Sep 2015 12:43:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 7 Xref: mx02.eternal-september.org comp.lang.vhdl:8484 On Friday, September 4, 2015 at 4:47:18 PM UTC-4, Aderemi wrote: > pls i need a vhdl code for a 16bit slicer Code can be found in a file that is typically opened with a text editor. Without you providing any real requirements, don't expect to get any sort of useful feedback from anybody. Kevin From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.159.132 with SMTP id i126mr2526319ioe.23.1441465169389; Sat, 05 Sep 2015 07:59:29 -0700 (PDT) X-Received: by 10.50.122.103 with SMTP id lr7mr16078igb.10.1441465169334; Sat, 05 Sep 2015 07:59:29 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no969076igb.0!news-out.google.com!f6ni1813igi.0!nntp.google.com!kq10no771022igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 07:59:28 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.226.127.233; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 83.226.127.233 References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1a6d815f-775f-4305-8cb8-1b5d4c916983@googlegroups.com> Subject: pls i need a vhdl code for a 16bit slicer From: olof.kraigher@gmail.com Injection-Date: Sat, 05 Sep 2015 14:59:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 5 Xref: mx02.eternal-september.org comp.lang.vhdl:8485 It is unlikely that someone will help you with such a vague question. You m= ake an impression of being a student that is either way over your head or s= imply lazy or both. In either case getting the code will not help you more = than possibly cheat an assignment. To be employable in the future you actua= lly need to learn something. If you do not realize this you are wasting you= r time. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.19.153 with SMTP id 25mr9037004iot.24.1441465237690; Sat, 05 Sep 2015 08:00:37 -0700 (PDT) X-Received: by 10.50.12.69 with SMTP id w5mr124652igb.13.1441465237623; Sat, 05 Sep 2015 08:00:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!enother.net!enother.net!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no771440igb.0!news-out.google.com!f6ni1813igi.0!nntp.google.com!kq10no771429igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 5 Sep 2015 08:00:36 -0700 (PDT) In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=83.226.127.233; posting-account=4yMaIAoAAACq4riIkxihBqe0gThIBN-n NNTP-Posting-Host: 83.226.127.233 References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: pls i need a vhdl code for a 16bit slicer From: olof.kraigher@gmail.com Injection-Date: Sat, 05 Sep 2015 15:00:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 1551 X-Received-Body-CRC: 4221742351 Xref: mx02.eternal-september.org comp.lang.vhdl:8486 It is unlikely that someone will help you with such a vague question. You m= ake an impression of being a student that is either way over your head or s= imply lazy or both. In either case getting the code will not help you more = than possibly cheat an assignment. To be employable in the future you actua= lly need to learn something. If you do not realize this you are wasting you= r time. From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: pls i need a vhdl code for a 16bit slicer Date: Sat, 5 Sep 2015 11:49:50 -0400 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 5 Sep 2015 15:48:03 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="17625"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188c+eOzCFDuEg39azBbTxW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> Cancel-Lock: sha1:uVyCwXW/w2zrHpiBwr0bWNPjPYs= Xref: mx02.eternal-september.org comp.lang.vhdl:8487 On 9/4/2015 4:47 PM, Aderemi wrote: > > > pls i need a vhdl code for a 16bit slicer I have code for a VHDL 16 bit dicer, but not for the slicer. -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: pls i need a vhdl code for a 16bit slicer Date: Sat, 5 Sep 2015 17:06:03 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 16 Message-ID: References: <12075ba7-4744-4642-adee-855640c87864@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8488 rickman wrote: > On 9/4/2015 4:47 PM, Aderemi wrote: >> pls i need a vhdl code for a 16bit slicer > I have code for a VHDL 16 bit dicer, but not for the slicer. And I suppose it came from Ronco? I am pretty sure they sell the slicer, too. https://en.wikipedia.org/wiki/Ronco (and who remembers the Bass-o-matic? -- glen From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.52.30.163 with SMTP id t3mr13725972vdh.14.1441553849512; Sun, 06 Sep 2015 08:37:29 -0700 (PDT) X-Received: by 10.50.41.34 with SMTP id c2mr154670igl.1.1441553849468; Sun, 06 Sep 2015 08:37:29 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no1170118qge.1!news-out.google.com!f6ni2823igi.0!nntp.google.com!kq10no1425592igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Sep 2015 08:37:28 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=79.177.48.161; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 79.177.48.161 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: use STD_LOGIC_UNSIGNED with NUMERIC_STD From: bknpk@hotmail.com Injection-Date: Sun, 06 Sep 2015 15:37:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8489 On Thursday, September 3, 2015 at 2:29:19 AM UTC+3, N. wrote: > Hello, >=20 > I'm trying to port a very old design that had formerly used the deprecate= d STD_LOGIC_ARITH library with the new NUMERIC_STD library.=20 >=20 > The old design has a substantial amount of unsigned additions of the foll= owing format :=20 >=20 > c_slv <=3D a_slv + b_slv; >=20 > or=20 >=20 > c_slv <=3D a_slv + 10; >=20 ... use ieee.STD_LOGIC_UNSIGNED."+"; ... learn_cnti <=3D=20 --load mem_do(43 downto 40) when fsm_ps(c_loc_read1) =3D '1' else --increment std_logic_vector(unsigned(learn_cntq) + "0001") when=20 fsm_ps(c_loc_ave0) =3D '1'=20 else learn_cntq; ... For more info see vhdl examples at http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html >=20 > I realize I should probably go through all of the code and recast it all = to "unsigned" to make it play nice with numeric_std, but was curious if it = was still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUM= ERIC_STD. As far as I can tell, it doesn't look like the overloaded functio= ns will conflict at all. >=20 >=20 > PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUM= ERIC_STD_UNSIGNED is out. >=20 > Thanks. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.158.84 with SMTP id h81mr17718174ioe.15.1441609197928; Sun, 06 Sep 2015 23:59:57 -0700 (PDT) X-Received: by 10.50.79.137 with SMTP id j9mr174981igx.15.1441609197906; Sun, 06 Sep 2015 23:59:57 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no1693891igb.0!news-out.google.com!nt1ni3282igb.0!nntp.google.com!kq10no1263033igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 6 Sep 2015 23:59:57 -0700 (PDT) In-Reply-To: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: <7c961a05-b447-4910-94b4-9f690a23571d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9fc04b7a-f8a7-4113-8051-a85d1dc68382@googlegroups.com> Subject: Re: Can we log internal signals from a testbench in VHDL? From: bknpk@hotmail.com Injection-Date: Mon, 07 Sep 2015 06:59:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8490 You can build your own. ... use STD.textio.all; use IEEE.STD_LOGIC_TEXTIO.all; ... write(my_line, string'("presState ")); write(my_line, string'(STATETYPE'image(presState))); write(my_line, string'(" at ")); write(my_line, now); writeline(output, my_line); For more details see http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_print_debug_tip.html To print instance path: 1.if(newByte = '1') then 2. write (my_line, string'("path ")); 3. write (my_line, clk'path_name);--short .... http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html On Friday, November 9, 2012 at 6:08:07 AM UTC+2, py wrote: > Hi, > > At the end of a test, I would like to collect some stat in the following manner: > > assert false report "Max counter is " & str(counter_value) severity note > > This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? I heard that for verilog, it is possible to reference internal signal like outer_layer.inner_layer.signal_name > > > Thanks From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.182.213.73 with SMTP id nq9mr8710795obc.33.1441646038885; Mon, 07 Sep 2015 10:13:58 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr196270igw.7.1441646038824; Mon, 07 Sep 2015 10:13:58 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no1471331igb.0!news-out.google.com!nt1ni3702igb.0!nntp.google.com!kq10no1960327igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 7 Sep 2015 10:13:58 -0700 (PDT) In-Reply-To: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> Subject: Re: PSL syntax help From: niv Injection-Date: Mon, 07 Sep 2015 17:13:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8491 Figured out I was using the Verilog syntax... [*2..5] should be [*2 to 5] for VHDL. (Doh!) However, I get assertion fails with: assert always (req -> next[*2 to 5](gnt)); -- compiles OK but gets assertion error or even with: assert always (req -> next gnt[*2 to 5]); Not sure which is the correct syntax for what I need to combine the 4 working assertions into a single one?? Any help most welcome. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.13.239.197 with SMTP id y188mr25784157ywe.0.1441732428562; Tue, 08 Sep 2015 10:13:48 -0700 (PDT) X-Received: by 10.50.111.43 with SMTP id if11mr243602igb.1.1441732428495; Tue, 08 Sep 2015 10:13:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no1651234qge.0!news-out.google.com!nt1ni4586igb.0!nntp.google.com!kq10no2470632igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Sep 2015 10:13:47 -0700 (PDT) In-Reply-To: <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.5.226.94; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu NNTP-Posting-Host: 86.5.226.94 References: <6f818d03-2cc1-41ad-bc18-65bb417b8af7@googlegroups.com> <0711915a-6221-4732-ac9a-f7566258f464@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: PSL syntax help From: niv Injection-Date: Tue, 08 Sep 2015 17:13:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8492 assert always (req -> next_a[2 to 5](gnt)); This does thejob. (Phew)! From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: ISCAS 95 Date: Sat, 12 Sep 2015 21:59:37 +0300 Organization: A noiseless patient Spider Lines: 2 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Sep 2015 18:57:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="30967"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Hb8asIXkV8B1iLSvqFN05KAH7QauVufg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:HPfofOjg/xd2CqnBhJlY9+3d7pw= Xref: mx02.eternal-september.org comp.lang.vhdl:8493 Do you know where I can download these benchmarks, preferably in RTL VHD? I would appreciate any other combinatorial benchmarks. From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.182.233.195 with SMTP id ty3mr33227826obc.44.1443096538290; Thu, 24 Sep 2015 05:08:58 -0700 (PDT) X-Received: by 10.50.134.169 with SMTP id pl9mr177706igb.13.1443096538269; Thu, 24 Sep 2015 05:08:58 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no9045435igb.0!news-out.google.com!n2ni10426igy.0!nntp.google.com!kq10no8580189igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 05:08:57 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Result is U From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 12:08:58 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8494 Hi, I have a question about the behavioral code of multiplier. I used two generate loops but after calculation, the output is Undesigned. Anyone can help me? The code is as followed: --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal a_temp_1:std_logic_vector(width-1 downto 0); signal a_temp_2:std_logic_vector(width-1 downto 0); signal cout_a:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal b_temp_1:std_logic_vector(width-1 downto 0); signal b_temp_2:std_logic_vector(width-1 downto 0); signal cout_b:std_logic_vector(width-1 downto 0); signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal y_ready:std_logic_vector(2*width-1 downto 0); signal cin:std_logic_vector(2*width downto 0); signal cout:std_logic_vector(2*width-1 downto 0); signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); begin --inverse calculation of a iteration_a1: for i in 0 to width-1 generate a_temp_1(i)<= not a(i); end generate iteration_a1; a_temp_2(0)<=a_temp_1(0) xor '1'; cout_a(0)<=a_temp_1(0) and '1'; iteration_a2: for i in 1 to width-1 generate a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); cout_a(i)<=a_temp_1(i) and cout_a(i-1); end generate iteration_a2; a_temp<=a when a(width-1)='0' else a_temp_2; --inverse calculation of b iteration_b1: for i in 0 to width-1 generate b_temp_1(i)<= not b(i); end generate iteration_b1; b_temp_2(0)<=b_temp_1(0) xor '1'; cout_b(0)<=b_temp_1(0) and '1'; iteration_b2: for i in 1 to width-1 generate b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); cout_b(i)<=b_temp_1(i) and cout_b(i-1); end generate iteration_b2; b_temp<=b when b(width-1)='0' else b_temp_2; mid_temp_a(width-1 downto 0)<=a_temp; iteration_out: for i in 0 to width-1 generate cin(0)<='0'; mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; mid_temp<=mid_temp_a when b(i)='1' else (others=>'0') when b(i)='0'; iteration_in: --y_temp is a while mid_temp is b for j in 0 to 2*width-1 generate y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); cin(j+1)<=cout(j); end generate iteration_in; y_temp<=y_ready1; end generate iteration_out; y<=y_ready; end architecture Behavioral; From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.13.222.196 with SMTP id h187mr913648ywe.0.1443117654215; Thu, 24 Sep 2015 11:00:54 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr38360igt.14.1443117654148; Thu, 24 Sep 2015 11:00:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no3963230qge.0!news-out.google.com!n2ni10681igy.0!nntp.google.com!kq10no9317957igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 11:00:53 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <219e2304-6fa4-4b07-a992-4c27f70cb8f2@googlegroups.com> Subject: VUnit, the Free and Open Source Unit Testing Framework for VHDL, Now Supports Active-HDL and Riviera-PRO From: Lars Asplund Injection-Date: Thu, 24 Sep 2015 18:00:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8495 Two weeks ago we got our partner licenses from Aldec and now we've released= a new VUnit version supporting both Active-HDL and Riviera-PRO (in additio= n to ModelSim and GHDL). You can find more information here https://www.lin= kedin.com/pulse/short-introduction-vunit-lars-asplund or go directly to htt= ps://github.com/LarsAsplund/vunit to download your copy or just do $ git clone https://github.com/LarsAsplund/vunit.git $ cd vunit $ python setup.py install to get started. /Lars From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.13.213.215 with SMTP id x206mr1062966ywd.7.1443119624318; Thu, 24 Sep 2015 11:33:44 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr381388igw.4.1443119624287; Thu, 24 Sep 2015 11:33:44 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no3977773qge.0!news-out.google.com!z4ni952ign.0!nntp.google.com!kq10no8915313igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 11:33:44 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Subject: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 18:33:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3803 X-Received-Body-CRC: 2194389024 Xref: mx02.eternal-september.org comp.lang.vhdl:8496 I have a problem , when I execute my code, the output is undesigned. Anyone can help me? My code is as followed --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal a_temp_1:std_logic_vector(width-1 downto 0); signal a_temp_2:std_logic_vector(width-1 downto 0); signal cout_a:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal b_temp_1:std_logic_vector(width-1 downto 0); signal b_temp_2:std_logic_vector(width-1 downto 0); signal cout_b:std_logic_vector(width-1 downto 0); signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal y_ready:std_logic_vector(2*width-1 downto 0); signal cin:std_logic_vector(2*width downto 0); signal cout:std_logic_vector(2*width-1 downto 0); signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); begin --inverse calculation of a iteration_a1: for i in 0 to width-1 generate a_temp_1(i)<= not a(i); end generate iteration_a1; a_temp_2(0)<=a_temp_1(0) xor '1'; cout_a(0)<=a_temp_1(0) and '1'; iteration_a2: for i in 1 to width-1 generate a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); cout_a(i)<=a_temp_1(i) and cout_a(i-1); end generate iteration_a2; a_temp<=a when a(width-1)='0' else a_temp_2; --inverse calculation of b iteration_b1: for i in 0 to width-1 generate b_temp_1(i)<= not b(i); end generate iteration_b1; b_temp_2(0)<=b_temp_1(0) xor '1'; cout_b(0)<=b_temp_1(0) and '1'; iteration_b2: for i in 1 to width-1 generate b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); cout_b(i)<=b_temp_1(i) and cout_b(i-1); end generate iteration_b2; b_temp<=b when b(width-1)='0' else b_temp_2; mid_temp_a(width-1 downto 0)<=a_temp; iteration_out: for i in 0 to width-1 generate cin(0)<='0'; mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; mid_temp<=mid_temp_a when b(i)='1' else (others=>'0') when b(i)='0'; iteration_in: --y_temp is a while mid_temp is b for j in 0 to 2*width-1 generate y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); cin(j+1)<=cout(j); end generate iteration_in; y_temp<=y_ready1; end generate iteration_out; y<=y_ready; end architecture Behavioral; From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Thu, 24 Sep 2015 16:50:33 -0400 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Sep 2015 20:48:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="18806"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193MeCU331Dr24BrsdhOlPS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Cancel-Lock: sha1:+Id2rnVBvKqvCSom3reJ0EOu9u8= Xref: mx02.eternal-september.org comp.lang.vhdl:8497 On 9/24/2015 2:33 PM, zhangth1991@gmail.com wrote: > I have a problem , when I execute my code, the output is undesigned. Of course your output is designed. You must be looking at the output wrong. > Anyone can help me? My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > > signal a_temp:std_logic_vector(width-1 downto 0); > signal a_temp_1:std_logic_vector(width-1 downto 0); > signal a_temp_2:std_logic_vector(width-1 downto 0); > signal cout_a:std_logic_vector(width-1 downto 0); > > signal b_temp:std_logic_vector(width-1 downto 0); > signal b_temp_1:std_logic_vector(width-1 downto 0); > signal b_temp_2:std_logic_vector(width-1 downto 0); > signal cout_b:std_logic_vector(width-1 downto 0); > signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal y_ready:std_logic_vector(2*width-1 downto 0); > signal cin:std_logic_vector(2*width downto 0); > signal cout:std_logic_vector(2*width-1 downto 0); > signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > > begin > --inverse calculation of a > iteration_a1: > for i in 0 to width-1 generate > a_temp_1(i)<= not a(i); > end generate iteration_a1; > a_temp_2(0)<=a_temp_1(0) xor '1'; > cout_a(0)<=a_temp_1(0) and '1'; > iteration_a2: > for i in 1 to width-1 generate > a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); > cout_a(i)<=a_temp_1(i) and cout_a(i-1); > end generate iteration_a2; > a_temp<=a when a(width-1)='0' else > a_temp_2; > --inverse calculation of b > iteration_b1: > for i in 0 to width-1 generate > b_temp_1(i)<= not b(i); > end generate iteration_b1; > b_temp_2(0)<=b_temp_1(0) xor '1'; > cout_b(0)<=b_temp_1(0) and '1'; > iteration_b2: > for i in 1 to width-1 generate > b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); > cout_b(i)<=b_temp_1(i) and cout_b(i-1); > end generate iteration_b2; > b_temp<=b when b(width-1)='0' else > b_temp_2; > mid_temp_a(width-1 downto 0)<=a_temp; > > iteration_out: > for i in 0 to width-1 generate > cin(0)<='0'; > mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; > mid_temp<=mid_temp_a when b(i)='1' else > (others=>'0') when b(i)='0'; > iteration_in: > --y_temp is a while mid_temp is b > for j in 0 to 2*width-1 generate > y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); > cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); > cin(j+1)<=cout(j); > end generate iteration_in; > y_temp<=y_ready1; > > end generate iteration_out; > y<=y_ready; > > > > > > > end architecture Behavioral; -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.66.100.233 with SMTP id fb9mr1571900pab.24.1443128375229; Thu, 24 Sep 2015 13:59:35 -0700 (PDT) X-Received: by 10.50.136.163 with SMTP id qb3mr393313igb.12.1443128375158; Thu, 24 Sep 2015 13:59:35 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no9443055igb.0!news-out.google.com!n2ni10802igy.0!nntp.google.com!kq10no9032420igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 13:59:34 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 24 Sep 2015 20:59:35 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1153 X-Received-Body-CRC: 404930816 Xref: mx02.eternal-september.org comp.lang.vhdl:8498 no, the output is U all the time From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Thu, 24 Sep 2015 17:37:56 -0400 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Sep 2015 21:36:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="30890"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ILM1QaOYLepB/YpkiWeWo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> Cancel-Lock: sha1:Pm2mQ/f/AOhS1tHdD51UrzLZhYk= Xref: mx02.eternal-september.org comp.lang.vhdl:8499 On 9/24/2015 4:59 PM, zhangth1991@gmail.com wrote: > no, the output is U all the time Have you traced it back through the logic? Where does the U originate? -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.13.230.214 with SMTP id p205mr3241863ywe.57.1443158472841; Thu, 24 Sep 2015 22:21:12 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr6253igw.4.1443158472771; Thu, 24 Sep 2015 22:21:12 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no4141936qge.0!news-out.google.com!n2ni11169igy.0!nntp.google.com!kq10no9269183igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Sep 2015 22:21:12 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Fri, 25 Sep 2015 05:21:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1366 X-Received-Body-CRC: 1160190088 Xref: mx02.eternal-september.org comp.lang.vhdl:8500 I think it is caused by the iteration_in, because before I use the inner iteration, the output is generated. Now the output is U after the first change of a and b From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!npeersf04.am4!fx34.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Multiplier using 1 bit full adder problem References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150924-1, 24/09/2015), Outbound message X-Antivirus-Status: Clean Lines: 96 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443169248 81.109.142.154 (Fri, 25 Sep 2015 08:20:48 UTC) NNTP-Posting-Date: Fri, 25 Sep 2015 08:20:48 UTC Organization: virginmedia.com Date: Fri, 25 Sep 2015 09:20:45 +0100 X-Received-Body-CRC: 937365260 X-Received-Bytes: 4293 Xref: mx02.eternal-september.org comp.lang.vhdl:8501 On 24/09/2015 19:33, zhangth1991@gmail.com wrote: > I have a problem , when I execute my code, the output is undesigned. Anyone can help me? My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > > signal a_temp:std_logic_vector(width-1 downto 0); > signal a_temp_1:std_logic_vector(width-1 downto 0); > signal a_temp_2:std_logic_vector(width-1 downto 0); > signal cout_a:std_logic_vector(width-1 downto 0); > > signal b_temp:std_logic_vector(width-1 downto 0); > signal b_temp_1:std_logic_vector(width-1 downto 0); > signal b_temp_2:std_logic_vector(width-1 downto 0); > signal cout_b:std_logic_vector(width-1 downto 0); > signal y_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal y_ready:std_logic_vector(2*width-1 downto 0); > signal cin:std_logic_vector(2*width downto 0); > signal cout:std_logic_vector(2*width-1 downto 0); > signal mid_temp_a:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > > begin > --inverse calculation of a > iteration_a1: > for i in 0 to width-1 generate > a_temp_1(i)<= not a(i); > end generate iteration_a1; > a_temp_2(0)<=a_temp_1(0) xor '1'; > cout_a(0)<=a_temp_1(0) and '1'; > iteration_a2: > for i in 1 to width-1 generate > a_temp_2(i)<=a_temp_1(i) xor cout_a(i-1); As a quick guess I would say you may be hitting the longest static prefix issue. Have a look at section 4.2.13 of the VHDL FAQ: https://tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html Good luck, Hans www.ht-lab.com > cout_a(i)<=a_temp_1(i) and cout_a(i-1); > end generate iteration_a2; > a_temp<=a when a(width-1)='0' else > a_temp_2; > --inverse calculation of b > iteration_b1: > for i in 0 to width-1 generate > b_temp_1(i)<= not b(i); > end generate iteration_b1; > b_temp_2(0)<=b_temp_1(0) xor '1'; > cout_b(0)<=b_temp_1(0) and '1'; > iteration_b2: > for i in 1 to width-1 generate > b_temp_2(i)<=b_temp_1(i) xor cout_b(i-1); > cout_b(i)<=b_temp_1(i) and cout_b(i-1); > end generate iteration_b2; > b_temp<=b when b(width-1)='0' else > b_temp_2; > mid_temp_a(width-1 downto 0)<=a_temp; > > iteration_out: > for i in 0 to width-1 generate > cin(0)<='0'; > mid_temp_a<=mid_temp_a(2*width-2 downto 0) & '0'; > mid_temp<=mid_temp_a when b(i)='1' else > (others=>'0') when b(i)='0'; > iteration_in: > --y_temp is a while mid_temp is b > for j in 0 to 2*width-1 generate > y_ready1(j)<=y_temp(j) xor mid_temp(j) xor cin(j); > cout(j)<=(y_temp(j) and mid_temp(j)) or (y_temp(j) and cin(j)) or (cin(j) and mid_temp(j)); > cin(j+1)<=cout(j); > end generate iteration_in; > y_temp<=y_ready1; > > end generate iteration_out; > y<=y_ready; > > end architecture Behavioral; > From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.107.167.134 with SMTP id q128mr4788228ioe.6.1443183116082; Fri, 25 Sep 2015 05:11:56 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr17110igw.7.1443183116015; Fri, 25 Sep 2015 05:11:56 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no9857521igb.0!news-out.google.com!n2ni11471igy.0!nntp.google.com!kq10no9561358igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 05:11:55 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Result is U From: Thomas Stanka Injection-Date: Fri, 25 Sep 2015 12:11:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8502 Am Donnerstag, 24. September 2015 14:09:02 UTC+2 schrieb zhang...@gmail.com: > Hi, > I have a question about the behavioral code of multiplier. I used two generate loops but after calculation, the output is Undesigned. Anyone can help me? The code is as followed: [..] > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); [..] > y<=y_ready; There is no statement that assigns a value to y_ready. I would debug this by having a look to all internal signals. That often helps identifying the signal that is root cause of 'U'. bye Thomas From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder problem Date: Fri, 25 Sep 2015 10:10:28 -0400 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 14:08:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="17378"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/o73Xdz696P+CQgnONPkWT" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> Cancel-Lock: sha1:31W3xTMlESKNh2SnAnoLoXnZ/wU= Xref: mx02.eternal-september.org comp.lang.vhdl:8503 On 9/25/2015 1:21 AM, zhangth1991@gmail.com wrote: > I think it is caused by the iteration_in, because before I use the inner iteration, the output is generated. Now the output is U after the first change of a and b To be honest, I've never tried debugging generated code, mainly because I seldom write generated code. Why are you writing generated code rather than much simpler straight VHDL? For example, instead of four lines of generated code iteration_a1: could just be... a_temp_1 <= not a; iteration_a2: could be... a_temp_2 <= a_temp_1 xor (cout_a(width-2 downto 0) & '1'); cout_a <= a_temp_1 and (cout_a(width-2 downto 0) & '1'); Isn't this much simpler? What is the source of information on how to construct your logic? Do you have equations or a verbal description of how it is supposed to work? -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.129.46.197 with SMTP id u188mr4734868ywu.22.1443191149212; Fri, 25 Sep 2015 07:25:49 -0700 (PDT) X-Received: by 10.50.8.42 with SMTP id o10mr27200iga.7.1443191149177; Fri, 25 Sep 2015 07:25:49 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no4324528qge.0!news-out.google.com!z4ni1766ign.0!nntp.google.com!kq10no9946790igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 07:25:48 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Subject: Question of ' From: fl Injection-Date: Fri, 25 Sep 2015 14:25:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8504 Hi, VHDL grammar is still not easy to me. I see this line on a forum: architecture lut of bit_count is subtype lutin is std_logic_vector (3 downto 0); subtype lutout is std_logic_vector (2 downto 0); type lut00 is array (natural range 0 to 15) of lutout; constant bitcount: lut00 := ( "000", "001", "001", "010", "011", "010", "010", "011", "001", "010", "010", "011", "010", "011", "011", "100" ); signal temp: std_logic_vector (2 downto 0); begin temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); .... it has an error: Illegal type conversion to lutin (operand type is not known). I know the correct answer is: temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) ); but I don't know the detail rule on understanding it. Online search ' gives predefined attribute. Obviously here is not an attribute. What function of ' is here? Thanks, From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.13.215.74 with SMTP id z71mr4995557ywd.26.1443193231331; Fri, 25 Sep 2015 08:00:31 -0700 (PDT) X-Received: by 10.50.79.193 with SMTP id l1mr31002igx.2.1443193231257; Fri, 25 Sep 2015 08:00:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feed.news.qwest.net!mpls-nntp-01.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!nntp.giganews.com!v79no4340755qge.0!news-out.google.com!z4ni1796ign.0!nntp.google.com!kq10no9976145igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 08:00:30 -0700 (PDT) In-Reply-To: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.36.208.72; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 217.36.208.72 References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e41e71e-50dc-4534-95cd-6bdff653d4a2@googlegroups.com> Subject: Re: Question of ' From: Jim Lewis Injection-Date: Fri, 25 Sep 2015 15:00:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: mx02.eternal-september.org comp.lang.vhdl:8505 > I know the correct answer is: > temp <= bitcount( TO_INTEGER ( unsigned (lutin'(a&b&c&d) ) ) ); > > > but I don't know the detail rule on understanding it. Online search ' gives > predefined attribute. Obviously here is not an attribute. What function of ' > is here? Here it is a type qualifier that identifies the type of the expression. If a,b,c,d are all std_ulogic or std_logic, then you could have simplified this to: temp <= bitcount( TO_INTEGER ( unsigned'(a&b&c&d) ) ); Jim From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.31.108.28 with SMTP id h28mr5062453vkc.4.1443194426259; Fri, 25 Sep 2015 08:20:26 -0700 (PDT) X-Received: by 10.50.22.7 with SMTP id z7mr32176ige.15.1443194426223; Fri, 25 Sep 2015 08:20:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no4350385qge.1!news-out.google.com!z4ni1807ign.0!nntp.google.com!kq10no9992632igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 08:20:25 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: std_ulogic_vector and std_logic_vector From: fl Injection-Date: Fri, 25 Sep 2015 15:20:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8506 Hi, I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of ABCD. If it is std_logic_vector, there are more cases to consider. I know general input would have type std_logic_vector. My question is whether there is a simple way to convert std_logic_vector to std_ulogic_vector? Thanks, library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Number_of_Ones is port ( --- mapped 3=a, 2=b, 1=c, 0=d abcd : in std_ulogic_vector(3 downto 0); -- mapped x=2, y=1, z=0 xyz : out std_ulogic_vector(2 downto 0); ); end entity; architecture any of Number_of_Ones is begin process (abcd) is begin case abcd of --ABCD|XYZ when "0000" => xyz <= "000"; when "0001" => xyz <= "001"; when "0010" => xyz <= "001"; when "0011" => xyz <= "010"; when "0100" => xyz <= "011"; when "0101" => xyz <= "010"; when "0110" => xyz <= "010"; when "0111" => xyz <= "011"; when "1000" => xyz <= "001"; when "1001" => xyz <= "010"; when "1010" => xyz <= "010"; when "1011" => xyz <= "011"; when "1100" => xyz <= "010"; when "1101" => xyz <= "011"; when "1110" => xyz <= "011"; when "1111" => xyz <= "100"; end case; end process; From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question of ' Date: Fri, 25 Sep 2015 11:50:26 -0400 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 15:48:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="8458"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18wjO7Pq35vXKFpWuQOVmV3" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> Cancel-Lock: sha1:PtoJNc+/4iiczOdRV9KPlPlKf2E= Xref: mx02.eternal-september.org comp.lang.vhdl:8507 On 9/25/2015 10:25 AM, fl wrote: > Hi, > > VHDL grammar is still not easy to me. I see this line on a forum: > > > architecture lut of bit_count is > subtype lutin is std_logic_vector (3 downto 0); > subtype lutout is std_logic_vector (2 downto 0); > type lut00 is array (natural range 0 to 15) of lutout; > constant bitcount: lut00 := ( > "000", "001", "001", "010", > "011", "010", "010", "011", > "001", "010", "010", "011", > "010", "011", "011", "100" > ); > > signal temp: std_logic_vector (2 downto 0); > begin > temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); Is "bitcount" supposed to actually be a bit count? It's not. bitcount(4) should be "001", no? -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Fri, 25 Sep 2015 11:58:02 -0400 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 15:56:06 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10232"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jlQhsZc93Tp/X0iFJClP5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:j6zymciTeD12uBfU9jCHiY/raTc= Xref: mx02.eternal-september.org comp.lang.vhdl:8508 On 9/25/2015 11:20 AM, fl wrote: > Hi, > I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of > ABCD. If it is std_logic_vector, there are more cases to consider. I believe std_ulogic_vector and std_logic_vector have the same value range. The difference is the result when signals are driven by multiple drivers. If you want to preclude the possibilities of inferring multiple drivers you can use std_ulogic_vector and errors will be flagged when multiple drivers are on the sane signal. With std_logic_vector the value goes to U or X, but no error is flagged in simulation. I'm not sure how synthesis handles multiple drivers on std_ulogic_vector signals. > I know general input would have type std_logic_vector. > > My question is whether there is a simple way to convert std_logic_vector to > std_ulogic_vector? Yeah.... std_logic_signal <= std_ulogic_signal; --- or --- xyz <= some expression of (std_logic'std_ulogic_signal); I believe these two logic types are completely interchangeable. > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity Number_of_Ones is > port ( > --- mapped 3=a, 2=b, 1=c, 0=d > abcd : in std_ulogic_vector(3 downto 0); > -- mapped x=2, y=1, z=0 > xyz : out std_ulogic_vector(2 downto 0); > ); > end entity; > > architecture any of Number_of_Ones is > begin > > process (abcd) is > begin > case abcd of > --ABCD|XYZ > when "0000" => xyz <= "000"; > when "0001" => xyz <= "001"; > when "0010" => xyz <= "001"; > when "0011" => xyz <= "010"; > when "0100" => xyz <= "011"; > when "0101" => xyz <= "010"; > when "0110" => xyz <= "010"; > when "0111" => xyz <= "011"; > when "1000" => xyz <= "001"; > when "1001" => xyz <= "010"; > when "1010" => xyz <= "010"; > when "1011" => xyz <= "011"; > when "1100" => xyz <= "010"; > when "1101" => xyz <= "011"; > when "1110" => xyz <= "011"; > when "1111" => xyz <= "100"; > end case; > end process; I think this also has the error for when "0100". -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.129.99.131 with SMTP id x125mr5974233ywb.42.1443205484794; Fri, 25 Sep 2015 11:24:44 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr49908igt.10.1443205484765; Fri, 25 Sep 2015 11:24:44 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no4430846qge.1!news-out.google.com!n2ni11749igy.0!nntp.google.com!kq10no9882567igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 11:24:44 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.245 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Subject: Re: std_ulogic_vector and std_logic_vector From: KJ Injection-Date: Fri, 25 Sep 2015 18:24:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 18 Xref: mx02.eternal-september.org comp.lang.vhdl:8509 On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote: > Hi, > I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of > ABCD. If it is std_logic_vector, there are more cases to consider. > That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector. > My question is whether there is a simple way to convert std_logic_vector to > std_ulogic_vector? > signal my_sulv: std_ulogic_vector(...); signal my_slv: std_logic_vector(...); ... my_sulv <= std_ulogic_vector(my_slv); my_slv <= std_logic_vector(my_sulv); Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Fri, 25 Sep 2015 17:18:15 -0400 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Sep 2015 21:16:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="21395"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nYCUZOrSw8J93VZG4JgHa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Cancel-Lock: sha1:uYsLVUtq4TpnvVaCTcf35j1Mc88= Xref: mx02.eternal-september.org comp.lang.vhdl:8510 On 9/25/2015 2:24 PM, KJ wrote: > On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote: >> Hi, >> I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of >> ABCD. If it is std_logic_vector, there are more cases to consider. >> > > That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector. > >> My question is whether there is a simple way to convert std_logic_vector to >> std_ulogic_vector? >> > > signal my_sulv: std_ulogic_vector(...); > signal my_slv: std_logic_vector(...); > .... > my_sulv <= std_ulogic_vector(my_slv); > my_slv <= std_logic_vector(my_sulv); Those would be conversion functions and I don't think they exist for those types. Those types are "closely related" and require no conversion or type specification to convert. In essence they can be mixed as if they were the same type. Am I wrong? -- Rick From newsfish@newsfish Tue Dec 29 16:43:57 2015 X-Received: by 10.66.236.41 with SMTP id ur9mr7871085pac.12.1443240671025; Fri, 25 Sep 2015 21:11:11 -0700 (PDT) X-Received: by 10.50.92.7 with SMTP id ci7mr70990igb.4.1443240670994; Fri, 25 Sep 2015 21:11:10 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no10220185igb.0!news-out.google.com!z4ni2330ign.0!nntp.google.com!kq10no10220182igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 25 Sep 2015 21:11:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:e811:23d2:8b8:b8f; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:e811:23d2:8b8:b8f References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: std_ulogic_vector and std_logic_vector From: KJ Injection-Date: Sat, 26 Sep 2015 04:11:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8511 On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: > Those would be conversion functions and I don't think they exist for=20 > those types. Those types are "closely related" and require no=20 > conversion or type specification to convert. In essence they can be=20 > mixed as if they were the same type. >=20 > Am I wrong? >=20 Like any good question, the answer is 'It depends'. For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wr= ong, the two are not closely related types. They are separate types so you= need a type conversion to go from one to the other. With VHDL-2008, you a= re correct that no type conversion is required. For std_logic and std_ulogic you never needed a conversion function because= std_logic is defined to be a subtype of std_ulogic. This is the way that = std_logic_vector should have been defined in the first place...VHDL-2008 c= orrected that (finally). Kevin Jennings From newsfish@newsfish Tue Dec 29 16:43:57 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Sat, 26 Sep 2015 00:27:11 -0400 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Sep 2015 04:25:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="87b10dc1a89c821d7d807dd85a2825be"; logging-data="29914"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19lHK6rzzRNQqPn+4UELzuC" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:yz0n5tansrZtHY6P7kHIElKRwpQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8512 On 9/26/2015 12:11 AM, KJ wrote: > On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: >> Those would be conversion functions and I don't think they exist for >> those types. Those types are "closely related" and require no >> conversion or type specification to convert. In essence they can be >> mixed as if they were the same type. >> >> Am I wrong? >> > > Like any good question, the answer is 'It depends'. > > For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wrong, the two are not closely related types. They are separate types so you need a type conversion to go from one to the other. With VHDL-2008, you are correct that no type conversion is required. > > For std_logic and std_ulogic you never needed a conversion function because std_logic is defined to be a subtype of std_ulogic. This is the way that std_logic_vector should have been defined in the first place...VHDL-2008 corrected that (finally). I'll have to take your word for it. I don't have any of my books with me and I'm too lazy to look this up on the Internet. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.13.223.129 with SMTP id i123mr13613492ywe.33.1443351484202; Sun, 27 Sep 2015 03:58:04 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr105907igw.7.1443351484174; Sun, 27 Sep 2015 03:58:04 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no5140546qge.0!news-out.google.com!z4ni3669ign.0!nntp.google.com!kq10no11381364igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Sep 2015 03:58:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Subject: Re: Question of ' From: fl Injection-Date: Sun, 27 Sep 2015 10:58:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2119 X-Received-Body-CRC: 41372844 Xref: mx02.eternal-september.org comp.lang.vhdl:8513 On Friday, September 25, 2015 at 11:50:31 AM UTC-4, rickman wrote: > On 9/25/2015 10:25 AM, fl wrote: > > Hi, > > > > VHDL grammar is still not easy to me. I see this line on a forum: > > > > > > architecture lut of bit_count is > > subtype lutin is std_logic_vector (3 downto 0); > > subtype lutout is std_logic_vector (2 downto 0); > > type lut00 is array (natural range 0 to 15) of lutout; > > constant bitcount: lut00 := ( > > "000", "001", "001", "010", > > "011", "010", "010", "011", > > "001", "010", "010", "011", > > "010", "011", "011", "100" > > ); > > > > signal temp: std_logic_vector (2 downto 0); > > begin > > temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); > > Is "bitcount" supposed to actually be a bit count? It's not. > bitcount(4) should be "001", no? > > -- > > Rick Rick: You are right. The original code on the table of bitcount(4) and other entries was wrong. Thanks, From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: std_ulogic_vector and std_logic_vector Date: Sun, 27 Sep 2015 14:37:54 -0400 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: <1dc77767-9670-4cdc-a48c-e2b13033cd9a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 18:36:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="14438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ixsn6X4pJak/NPLHn2Wpq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:GqV3ZfEQFqG/+I5imtUB5mk4ErU= Xref: mx02.eternal-september.org comp.lang.vhdl:8514 On 9/26/2015 12:27 AM, rickman wrote: > On 9/26/2015 12:11 AM, KJ wrote: >> On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote: >>> Those would be conversion functions and I don't think they exist for >>> those types. Those types are "closely related" and require no >>> conversion or type specification to convert. In essence they can be >>> mixed as if they were the same type. >>> >>> Am I wrong? >>> >> >> Like any good question, the answer is 'It depends'. >> >> For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you >> were wrong, the two are not closely related types. They are separate >> types so you need a type conversion to go from one to the other. With >> VHDL-2008, you are correct that no type conversion is required. >> >> For std_logic and std_ulogic you never needed a conversion function >> because std_logic is defined to be a subtype of std_ulogic. This is >> the way that std_logic_vector should have been defined in the first >> place...VHDL-2008 corrected that (finally). > > I'll have to take your word for it. I don't have any of my books with > me and I'm too lazy to look this up on the Internet. :) I finally got un-lazy and looked it up. The individual signals std_ulogic and std_logic do not require any sort of conversion. The _vector versions did. I seldom (ever actually) use std_ulogic so I didn't remember the distinction between the single signal and the vector signals. VHDL is complicated enough it is easy to forget details. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question of ' Date: Sun, 27 Sep 2015 14:38:38 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <4ff587ad-afc3-4eb0-93bd-90bebad69369@googlegroups.com> <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 18:36:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="14438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Pui7Wxa66TXXzWsK3+PRD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <6dfb986a-4a61-49ec-9cc0-1c6b18719955@googlegroups.com> Cancel-Lock: sha1:jO5Oegyf1/aCj+gRTf4vUKFqWMI= Xref: mx02.eternal-september.org comp.lang.vhdl:8515 On 9/27/2015 6:58 AM, fl wrote: > On Friday, September 25, 2015 at 11:50:31 AM UTC-4, rickman wrote: >> On 9/25/2015 10:25 AM, fl wrote: >>> Hi, >>> >>> VHDL grammar is still not easy to me. I see this line on a forum: >>> >>> >>> architecture lut of bit_count is >>> subtype lutin is std_logic_vector (3 downto 0); >>> subtype lutout is std_logic_vector (2 downto 0); >>> type lut00 is array (natural range 0 to 15) of lutout; >>> constant bitcount: lut00 := ( >>> "000", "001", "001", "010", >>> "011", "010", "010", "011", >>> "001", "010", "010", "011", >>> "010", "011", "011", "100" >>> ); >>> >>> signal temp: std_logic_vector (2 downto 0); >>> begin >>> temp <= bitcount( TO_INTEGER ( unsigned (lutin(a&b&c&d) ) ) ); >> >> Is "bitcount" supposed to actually be a bit count? It's not. >> bitcount(4) should be "001", no? >> >> -- >> >> Rick > > Rick: > You are right. The original code on the table of bitcount(4) and other > entries was wrong. Thanks, Hey, that's what code reviews are for. :) -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Review of Data Type Issues Date: Sun, 27 Sep 2015 15:08:32 -0400 Organization: A noiseless patient Spider Lines: 36 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Sep 2015 19:06:39 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22209"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19kMmqANY0wfVGSTe5MoEs5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:No7CJ/1X83L6W7fCztKLMHQsPEM= Xref: mx02.eternal-september.org comp.lang.vhdl:8516 I have trouble remembering the various ways of interchanging data types. I know there are three different methods that apply in different situations, but I have a hard time remembering them all because I don't code as often as I used to. 1) Conversions using functions Between unrelated types. Requires an explicit function. Example - Unsigned to Integer, to_integer(U) 2) Typecast Between related types (same base type, same index type if vector). Syntax looks like a function. Not needed for closely related types. Example - Unsigned to signed, signed('0' & X_uv) 3) Type qualifier Specifies type when unclear. String arrays can be a number of types, so require a qualifier to indicate the type. There can be multiple overloaded functions with the same input types but different return types, again a qualifier is required to resolve the issue. Example - Z_sv <= A_sv + signed'("1010") ; I think this lists the ways that types are converted or indicated. Just trying to refresh my memory. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.66.90.196 with SMTP id by4mr16792690pab.44.1443407088749; Sun, 27 Sep 2015 19:24:48 -0700 (PDT) X-Received: by 10.50.77.39 with SMTP id p7mr121905igw.7.1443407088678; Sun, 27 Sep 2015 19:24:48 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no12066138igb.0!news-out.google.com!n2ni14092igy.0!nntp.google.com!kq10no12066133igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Sep 2015 19:24:47 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about 'Actual expression is not globally static' From: fl Injection-Date: Mon, 28 Sep 2015 02:24:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8517 Hi, I remember that I see a code writing on part signal with 'not' logic as: instance_name : complexMul0 port map ( ar => not(ar), ai => ai, br => br, bi => bi, clk => CK, pr => pr, pi => pi); Today, when I write the above style and simulate with Modelsim, it gives error: (vcom-1436) Actual expression (prefix expression) of formal "ar" is not globally static. Could you help me on explain what 'globally static' is? What VHDL standard allow/dis-allow 'not' logic prefix? Thanks From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!xmission!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Question about 'Actual expression is not globally static' Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 28 Sep 2015 11:45:20 GMT Lines: 58 Message-ID: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: c8bf766b.news.astraweb.com X-Trace: DXC=kWk8NINX0A86fPZ:J:\J]3<:Wm\C]Q?P_PdAA< Xref: mx02.eternal-september.org comp.lang.vhdl:8518 On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote: > Hi, > > I remember that I see a code writing on part signal with 'not' logic as: > > > instance_name : complexMul0 > port map ( > ar => not(ar), > ai => ai, > br => br, > bi => bi, > clk => CK, > pr => pr, > pi => pi); > > > Today, when I write the above style and simulate with Modelsim, it gives > error: > > (vcom-1436) Actual expression (prefix expression) of formal "ar" is not > globally static. > > > > Could you help me on explain what 'globally static' is? > What VHDL standard allow/dis-allow 'not' logic prefix? Add quotes around the not like this instead: port map ( ar => "not"(ar), ai => ai, br => br, You are not allowed to use general expressions in a port map, however you are allowed to use function calls with at most one signal argument. This allows type conversions, etc. but not general purpose logic expressions of multiple signals. I'm not sure why they decided on this limitation. The "" quotes made a difference by turning an expression (which is illegal) into a function call (which is legal). Globally static roughly means that a name can be resolved at elaboration time. C.f. locally static, which roughly means that a name can be resolved at compilation time. If the compiler is saying that something isn't globally static, then it still can't work out what to do even after elaboration. I feel that Modelsim could have given a better error message in this case. Regards, Allan From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!81.171.118.62.MISMATCH!peer02.fr7!news.highwinds-media.com!post02.fr7!fx18.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Question about 'Actual expression is not globally static' References: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <5609284f$0$2852$c3e8da3$76491128@news.astraweb.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 150928-0, 28/09/2015), Outbound message X-Antivirus-Status: Clean Lines: 79 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443446545 81.109.142.154 (Mon, 28 Sep 2015 13:22:25 UTC) NNTP-Posting-Date: Mon, 28 Sep 2015 13:22:25 UTC Organization: virginmedia.com Date: Mon, 28 Sep 2015 14:22:25 +0100 X-Received-Body-CRC: 1165426853 X-Received-Bytes: 3329 Xref: mx02.eternal-september.org comp.lang.vhdl:8519 On 28/09/2015 12:45, Allan Herriman wrote: > On Sun, 27 Sep 2015 19:24:47 -0700, fl wrote: > >> Hi, >> >> I remember that I see a code writing on part signal with 'not' logic as: >> >> >> instance_name : complexMul0 >> port map ( >> ar => not(ar), >> ai => ai, >> br => br, >> bi => bi, >> clk => CK, >> pr => pr, >> pi => pi); >> >> >> Today, when I write the above style and simulate with Modelsim, it gives >> error: >> >> (vcom-1436) Actual expression (prefix expression) of formal "ar" is not >> globally static. >> >> >> >> Could you help me on explain what 'globally static' is? >> What VHDL standard allow/dis-allow 'not' logic prefix? > > > Add quotes around the not like this instead: > > > port map ( > ar => "not"(ar), > ai => ai, > br => br, > > > You are not allowed to use general expressions in a port map, however > you are allowed to use function calls with at most one signal argument. > This allows type conversions, etc. but not general purpose logic > expressions of multiple signals. I'm not sure why they decided on this > limitation. > > The "" quotes made a difference by turning an expression (which is > illegal) into a function call (which is legal). > > Globally static roughly means that a name can be resolved at elaboration > time. C.f. locally static, which roughly means that a name can be > resolved at compilation time. > If the compiler is saying that something isn't globally static, then it > still can't work out what to do even after elaboration. > > I feel that Modelsim could have given a better error message in this case. > Just use verror (cmd prompt or modelsim transcript) to get more info: D:\>verror 1436 vcom Message # 1436: VHDL 1993 through VHDL 2002 allowed an expression to be associated with a formal port in a port map as long as the expression was globally static and the port was of mode IN. VHDL 2008 now allows non-static expressions as well. Use the -2008 switch to vcom to enable this feature. [DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports] [DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] Regards, Hans www.ht-lab.com > Regards, > Allan > From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.66.252.6 with SMTP id zo6mr18192531pac.29.1443447677967; Mon, 28 Sep 2015 06:41:17 -0700 (PDT) X-Received: by 10.50.66.205 with SMTP id h13mr145264igt.10.1443447677891; Mon, 28 Sep 2015 06:41:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no12278394igb.0!news-out.google.com!z4ni4868ign.0!nntp.google.com!kq10no12278393igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 06:41:17 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: What differences are for type qualifier and type casting? From: fl Injection-Date: Mon, 28 Sep 2015 13:41:17 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8520 Hi, I see the following on a tutorial, but it is not clear about the difference= s=20 between type qualifier and type casting. How do I use either one from "1010" and B_slv? Thanks, =E2=97=8F VHDL type qualifier (type_name') is a mechanism that specifies th= e type of an operand or return value of a subprogram (or operator). Z_sv <=3D A_sv + signed'("1010") ;=20 =E2=97=8F Without ', it is type casting. Use type casting for: Z_sv <=3D A_sv + signed(B_slv) ;=20 From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.129.76.9 with SMTP id z9mr19013535ywa.35.1443457473215; Mon, 28 Sep 2015 09:24:33 -0700 (PDT) X-Received: by 10.50.111.138 with SMTP id ii10mr61457igb.0.1443457473160; Mon, 28 Sep 2015 09:24:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no5715762qge.1!news-out.google.com!n2ni14652igy.0!nntp.google.com!kq10no12670945igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 09:24:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What differences are for type qualifier and type casting? From: fl Injection-Date: Mon, 28 Sep 2015 16:24:33 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8521 On Monday, September 28, 2015 at 9:41:21 AM UTC-4, fl wrote: > Hi, >=20 > I see the following on a tutorial, but it is not clear about the differen= ces=20 > between type qualifier and type casting. >=20 > How do I use either one from "1010" and B_slv? >=20 > Thanks, >=20 >=20 > =E2=97=8F VHDL type qualifier (type_name') is a mechanism that specifies = the type > of an operand or return value of a subprogram (or operator). > Z_sv <=3D A_sv + signed'("1010") ;=20 >=20 > =E2=97=8F Without ', it is type casting. Use type casting for: > Z_sv <=3D A_sv + signed(B_slv) ; After read previous posts of KJ and Rick, I am clear about my question now.= Types are now and then confusing. From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.67.3.137 with SMTP id bw9mr19576180pad.4.1443458017907; Mon, 28 Sep 2015 09:33:37 -0700 (PDT) X-Received: by 10.50.112.4 with SMTP id im4mr148155igb.1.1443458017874; Mon, 28 Sep 2015 09:33:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no12425914igb.0!news-out.google.com!z4ni4979ign.0!nntp.google.com!kq10no12680954igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Sep 2015 09:33:37 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Subject: Why do conversion functions need to be self defined in a project? From: fl Injection-Date: Mon, 28 Sep 2015 16:33:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8522 Hi, I have a Matlab generated VHDL code project. It has such functions defined in the testbench package. I am just curious about why these looks frequent used functions need to write in such a project. It makes the test bench file very long, not friendly reading to me. Are there some similar functions out there accessible to me? Or, is there some reasons left to the designer to do by themselves? Thanks, -- Functions FUNCTION to_integer( x : IN std_logic) RETURN integer; FUNCTION to_hex( x : IN std_logic) RETURN string; FUNCTION to_hex( x : IN std_logic_vector) RETURN string; FUNCTION to_hex( x : IN bit_vector ) RETURN string; FUNCTION to_hex( x : IN signed ) RETURN string; FUNCTION to_hex( x : IN unsigned ) RETURN string; FUNCTION to_hex( x : IN real ) RETURN string; FUNCTION SLICE( x : IN bit_vector; slice : In Integer) RETURN std_logic_vector; From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What differences are for type qualifier and type casting? Date: Mon, 28 Sep 2015 13:59:40 -0400 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Sep 2015 17:57:45 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="13611"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18WwaryKL6Yf+/WFk292jkD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:iC8pDBTAziu1187qoV2J6bXrWAA= Xref: mx02.eternal-september.org comp.lang.vhdl:8523 On 9/28/2015 12:24 PM, fl wrote: > On Monday, September 28, 2015 at 9:41:21 AM UTC-4, fl wrote: >> Hi, >> >> I see the following on a tutorial, but it is not clear about the differences >> between type qualifier and type casting. >> >> How do I use either one from "1010" and B_slv? >> >> Thanks, >> >> >> â— VHDL type qualifier (type_name') is a mechanism that specifies the type >> of an operand or return value of a subprogram (or operator). >> Z_sv <= A_sv + signed'("1010") ; >> >> â— Without ', it is type casting. Use type casting for: >> Z_sv <= A_sv + signed(B_slv) ; > > After read previous posts of KJ and Rick, I am clear about my question now. Types are now and then confusing. Lol! That is like saying Godzilla was a rather large lizard! -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Tue, 29 Sep 2015 09:20:35 +0000 (UTC) Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 29 Sep 2015 09:20:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="15535"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/iRnFyN14R7xEYvwjTvBgU1sNjE6+7vMM=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:Th7vS7rZBTkf1UcfsNE8oe7E3qo= Xref: mx02.eternal-september.org comp.lang.vhdl:8524 On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: > Hi, > > I have a Matlab generated VHDL code project. It has such functions > defined in the testbench package. I am just curious about why these > looks frequent used functions need to write in such a project. It makes > the test bench file very long, not friendly reading to me. Put them in a utilities package so they don't clutter up the testbench. > Are there some similar functions out there accessible to me? Or, is > there some reasons left to the designer to do by themselves? There are libraries of functions to aid testing out there. www.osvvm.org supports constrained random verification https://github.com/LarsAsplund/vunit supports unit testing. Both of these have utilities to simplify reporting, which may cover your needs. However http://bitvis.no/resources/utility-library-download/ may be exactly what you are asking for. -- Brian From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.13.203.76 with SMTP id n73mr2646510ywd.15.1443541312055; Tue, 29 Sep 2015 08:41:52 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr239247igt.14.1443541312028; Tue, 29 Sep 2015 08:41:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!au2pb.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no6169784qge.0!news-out.google.com!z4ni5936ign.0!nntp.google.com!kq10no13637895igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 08:41:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Subject: Does if need else absolutely for synthesis to avoid latch? From: fl Injection-Date: Tue, 29 Sep 2015 15:41:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2250 X-Received-Body-CRC: 1478306846 Xref: mx02.eternal-september.org comp.lang.vhdl:8525 Hi, I remember that it is said that if must have an else to avoid latch in the synthesis process. I just begin working on a new, would-be large project. In order to do it gradually, I do a pure functional simulation first. The following code works for the simulation, but I don't find a way to add else for the if loop having '**' lines. The intention is to make the counter begins after an external signal 'start' changes to '1', which is expected the pulse width is just one clock cycle. When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but cnt /= x"00". The first cnt <= cnt+1 will run. Perhaps you expects have better idea to write this, even if my code works. I would rather to hear from you. Thanks, ........................... type START01 is range 0 to 1 ; signal start_var : START01 := 0; signal cnt : unsigned(7 downto 0) := (others => '0'); start_var <= start; p_start: process (clk, reset) begin if (clk'event and clk = '1') then if reset = '1' then cnt <= x"00"; elsif start_var = 0 then ** if cnt /= x"00" then cnt <= cnt + 1; ** end if; else cnt <= cnt + 1; end if; end if; end process; From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Does if need else absolutely for synthesis to avoid latch? Date: Tue, 29 Sep 2015 11:58:02 -0400 Organization: Alacron, Inc. Lines: 63 Message-ID: References: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 15:57:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="19033"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX199Lzb6lAmgpIPlEAmWb+YYWOb6734aECY=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Cancel-Lock: sha1:AdphoCmYH9lV/v/6aEg76U41FDE= Xref: mx02.eternal-september.org comp.lang.vhdl:8526 fl wrote: > Hi, > > I remember that it is said that if must have an else to avoid latch in the > synthesis process. I just begin working on a new, would-be large project. > In order to do it gradually, I do a pure functional simulation first. > The following code works for the simulation, but I don't find a way to add > else for the if loop having '**' lines. > > The intention is to make the counter begins after an external signal 'start' > changes to '1', which is expected the pulse width is just one clock cycle. > When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but > cnt /= x"00". The first cnt <= cnt+1 will run. > > > Perhaps you expects have better idea to write this, even if my code works. > I would rather to hear from you. > > Thanks, > > > ........................... > type START01 is range 0 to 1 ; > > signal start_var : START01 := 0; > signal cnt : unsigned(7 downto 0) := (others => '0'); > > start_var <= start; > p_start: process (clk, reset) > begin > if (clk'event and clk = '1') then > if reset = '1' then > cnt <= x"00"; > elsif start_var = 0 then > ** if cnt /= x"00" then > cnt <= cnt + 1; > ** end if; > else > cnt <= cnt + 1; > end if; > end if; > end process; > Latches are only created in a combinatorial process. Inside the if (clk`event ..., you are in a clocked process. So instead you will infer edge-triggered flip-flops. In this context there is no need to code an else for every if. It is assumed that the flip-flop will hold its current state if there is no else condition, and that's in fact what you want. Other than that, I would think the code more readable if you changed the order to look more like "if start is asserted then count up, else if count is not zero count up." The way you coded it does the same thing, but seems like it's backwards to the way one would normally think of it, i.e. you coded "if start is not asserted then count up only if count is not zero, otherwise count up." In the end, it's most likely you who will re-visit this code some time down the road and scratch your head trying to figure out what it does. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Tue, 29 Sep 2015 12:00:12 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 15:58:16 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="19377"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qUF2zxBv9kfxE2Sqa3Ppa" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:S27micn/ViJ85+jI45nlqPmkIB8= Xref: mx02.eternal-september.org comp.lang.vhdl:8527 On 9/29/2015 5:20 AM, Brian Drummond wrote: > On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: > >> Hi, >> >> I have a Matlab generated VHDL code project. It has such functions >> defined in the testbench package. I am just curious about why these >> looks frequent used functions need to write in such a project. It makes >> the test bench file very long, not friendly reading to me. > > Put them in a utilities package so they don't clutter up the testbench. > >> Are there some similar functions out there accessible to me? Or, is >> there some reasons left to the designer to do by themselves? > > There are libraries of functions to aid testing out there. > > www.osvvm.org supports constrained random verification > https://github.com/LarsAsplund/vunit supports unit testing. > > Both of these have utilities to simplify reporting, which may cover your > needs. > > However http://bitvis.no/resources/utility-library-download/ may be > exactly what you are asking for. I think the OP is using a utility to generate a test bench and it is adding the various functions which are *not* part of any of the conventional packages. So they stick them in the main file of the test bench. If he moves these functions to a package he will need to do the same work every time he generates the test bench again. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Does if need else absolutely for synthesis to avoid latch? Date: Tue, 29 Sep 2015 12:12:15 -0400 Organization: A noiseless patient Spider Lines: 58 Message-ID: References: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 16:10:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22350"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/VlLIbQo/4ZNzjLQkmcww1" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <0b3d523a-66e6-466f-bd54-214ac4edc910@googlegroups.com> Cancel-Lock: sha1:t7QZPXHnDdweAaZnpKGiyaT9I3c= Xref: mx02.eternal-september.org comp.lang.vhdl:8528 On 9/29/2015 11:41 AM, fl wrote: > Hi, > > I remember that it is said that if must have an else to avoid latch in the > synthesis process. I just begin working on a new, would-be large project. > In order to do it gradually, I do a pure functional simulation first. > The following code works for the simulation, but I don't find a way to add > else for the if loop having '**' lines. > > The intention is to make the counter begins after an external signal 'start' > changes to '1', which is expected the pulse width is just one clock cycle. > When 'start' is '1', the last cnt <= cnt+1 runs. Then, 'start' is '0', but > cnt /= x"00". The first cnt <= cnt+1 will run. > > > Perhaps you expects have better idea to write this, even if my code works. > I would rather to hear from you. > > Thanks, > > > ............................ > type START01 is range 0 to 1 ; > > signal start_var : START01 := 0; > signal cnt : unsigned(7 downto 0) := (others => '0'); > > start_var <= start; > p_start: process (clk, reset) > begin > if (clk'event and clk = '1') then > if reset = '1' then > cnt <= x"00"; > elsif start_var = 0 then > ** if cnt /= x"00" then > cnt <= cnt + 1; > ** end if; > else > cnt <= cnt + 1; > end if; > end if; > end process; The rule about latch generation only applies to code that is *not* within a clocked IF statement. The lack of the ELSE clause or an equivalent assignment implies that the previous value of the signal is retained. This infers a FF of some sort. In a clocked IF statement a clocked register is already inferred, so no harm. BTW, you should use the function rising_edge(clk) rather than the explicit term (clk'event and clk = '1'). The above code within the clocked IF statement will run on such transitions as 'H' to '1' and 'U' to '1'. Also it is just easier to read rising_edge(clk). Ditto falling_edge(clk). -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.31.178.196 with SMTP id b187mr83741vkf.3.1443560733885; Tue, 29 Sep 2015 14:05:33 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr18597igt.14.1443560733842; Tue, 29 Sep 2015 14:05:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no6302503qge.1!news-out.google.com!z4ni6202ign.0!nntp.google.com!kq10no13914860igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 14:05:32 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> Subject: Question about setting signal value From: fl Injection-Date: Tue, 29 Sep 2015 21:05:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8529 Hi, When I run a simulation VHDL code, there is a out of range fatal error. The signal source is from below code. corner0 is 111.5 while DINar_corner is 111.9. The division result should be below 1. Now the console output is: # ** Note: The value of 'corner0' is 1.119000e+002 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 # ** Note: The value of 'DINar_corner' is 1.115000e+002 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 # ** Note: The value of 'Cout' is -1.000000e+308 # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 I think that Cout should be the correct value after the process updates the signal value. But the other module which accespts Cout of below code, still sees Cout's value as -1.000000e+308. This results an out of range error. What is wrong in my code and signal value understanding? Thanks a lot to you. ............. p1: process (clk) variable tmp_XP, tmp_X : real; begin if (clk'event and clk = '1') then if reset = '1' then ar <= 0.0; ai <= 0.0; br <= 0.0; bi <= 0.0; else if cnt < x"02" then if cnt = x"00" then corner0 <= DINar_corner; elsif abs(corner0) < abs(DINar_corner) then corner0_q_real <= corner0/DINar_corner; Cout <= corner0_q_real; report "The value of 'corner0' is " & real'image(corner0); report "The value of 'DINar_corner' is " & real'image(DINar_corner); report "The value of 'Cout' is " & real'image(corner0_q_real); Sout <= 1; else corner0_q_real <= DINar_corner/corner0; Cout <= corner0_q_real; report "The value of 'Cout' is " & real'image(corner0_q_real); Sout <= 0; end if; else corner0_q_real <= DINar_corner/corner0; end if; From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.107.131.73 with SMTP id f70mr949243iod.18.1443563092531; Tue, 29 Sep 2015 14:44:52 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr275143igc.5.1443563092508; Tue, 29 Sep 2015 14:44:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no13939621igb.0!news-out.google.com!n2ni15887igy.0!nntp.google.com!kq10no13492478igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 14:44:51 -0700 (PDT) In-Reply-To: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Subject: Re: Question about setting signal value From: fl Injection-Date: Tue, 29 Sep 2015 21:44:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8530 On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: > Hi, > > When I run a simulation VHDL code, there is a out of range fatal error. The > signal source is from below code. corner0 is 111.5 while DINar_corner is > 111.9. The division result should be below 1. Now the console output is: > # ** Note: The value of 'corner0' is 1.119000e+002 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > # ** Note: The value of 'DINar_corner' is 1.115000e+002 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > # ** Note: The value of 'Cout' is -1.000000e+308 > # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > > I think that Cout should be the correct value after the process updates the > signal value. But the other module which accespts Cout of below code, still > sees Cout's value as -1.000000e+308. This results an out of range error. > > > What is wrong in my code and signal value understanding? > > > Thanks a lot to you. > > > > ............. > p1: process (clk) > variable tmp_XP, tmp_X : real; > begin > if (clk'event and clk = '1') then > if reset = '1' then > ar <= 0.0; ai <= 0.0; > br <= 0.0; bi <= 0.0; > else > if cnt < x"02" then > if cnt = x"00" then > corner0 <= DINar_corner; > elsif abs(corner0) < abs(DINar_corner) then > corner0_q_real <= corner0/DINar_corner; > Cout <= corner0_q_real; > report "The value of 'corner0' is " & real'image(corner0); > report "The value of 'DINar_corner' is " & real'image(DINar_corner); > report "The value of 'Cout' is " & real'image(corner0_q_real); > Sout <= 1; > else > corner0_q_real <= DINar_corner/corner0; > Cout <= corner0_q_real; > report "The value of 'Cout' is " & real'image(corner0_q_real); > Sout <= 0; > end if; > else > corner0_q_real <= DINar_corner/corner0; > end if; It is found that when I replace below one line to the two lines in previous post, it has no fatal error any more. I originally added one temporary signal for observation. It really delays one clock for the value. It was bug. Thanks, Cout <= -DINar_corner/corner0; From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about setting signal value Date: Tue, 29 Sep 2015 18:30:50 -0400 Organization: A noiseless patient Spider Lines: 75 Message-ID: References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Sep 2015 22:28:58 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="23219"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX192wqRXhG1cFYkeYg3AmtXh" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> Cancel-Lock: sha1:UBCxroi13Vxs3WEMReVCE0SfEK8= Xref: mx02.eternal-september.org comp.lang.vhdl:8531 On 9/29/2015 5:44 PM, fl wrote: > On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: >> Hi, >> >> When I run a simulation VHDL code, there is a out of range fatal error. The >> signal source is from below code. corner0 is 111.5 while DINar_corner is >> 111.9. The division result should be below 1. Now the console output is: >> # ** Note: The value of 'corner0' is 1.119000e+002 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> # ** Note: The value of 'DINar_corner' is 1.115000e+002 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> # ** Note: The value of 'Cout' is -1.000000e+308 >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >> >> I think that Cout should be the correct value after the process updates the >> signal value. But the other module which accespts Cout of below code, still >> sees Cout's value as -1.000000e+308. This results an out of range error. >> >> >> What is wrong in my code and signal value understanding? >> >> >> Thanks a lot to you. >> >> >> >> ............. >> p1: process (clk) >> variable tmp_XP, tmp_X : real; >> begin >> if (clk'event and clk = '1') then >> if reset = '1' then >> ar <= 0.0; ai <= 0.0; >> br <= 0.0; bi <= 0.0; >> else >> if cnt < x"02" then >> if cnt = x"00" then >> corner0 <= DINar_corner; >> elsif abs(corner0) < abs(DINar_corner) then >> corner0_q_real <= corner0/DINar_corner; >> Cout <= corner0_q_real; >> report "The value of 'corner0' is " & real'image(corner0); >> report "The value of 'DINar_corner' is " & real'image(DINar_corner); >> report "The value of 'Cout' is " & real'image(corner0_q_real); >> Sout <= 1; >> else >> corner0_q_real <= DINar_corner/corner0; >> Cout <= corner0_q_real; >> report "The value of 'Cout' is " & real'image(corner0_q_real); >> Sout <= 0; >> end if; >> else >> corner0_q_real <= DINar_corner/corner0; >> end if; > > It is found that when I replace below one line to the two lines in previous > post, it has no fatal error any more. I originally added one temporary > signal for observation. It really delays one clock for the value. It was > bug. > Thanks, > > Cout <= -DINar_corner/corner0; Yes, this statement inside the clocked conditional results in a 1 clock cycle delay, or actually more since it is in the ELSE clause while the rest of the code is in the THEN part of the IF cnt < x"02" statement. I think it would work fine if you made the Cout <= -DINar_corner/corner0; statement a concurrent statement outside of the process. Then it will be updated as soon as the values of DINar_corner and corner0 are updated. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.68.132.1 with SMTP id oq1mr757553pbb.12.1443571996580; Tue, 29 Sep 2015 17:13:16 -0700 (PDT) X-Received: by 10.50.176.200 with SMTP id ck8mr27084igc.3.1443571996537; Tue, 29 Sep 2015 17:13:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14021442igb.0!news-out.google.com!z4ni6359ign.0!nntp.google.com!kq10no14021433igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 17:13:15 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Subject: Re: Question about setting signal value From: fl Injection-Date: Wed, 30 Sep 2015 00:13:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8532 On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote: > On 9/29/2015 5:44 PM, fl wrote: > > On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: > >> Hi, > >> > >> When I run a simulation VHDL code, there is a out of range fatal error. The > >> signal source is from below code. corner0 is 111.5 while DINar_corner is > >> 111.9. The division result should be below 1. Now the console output is: > >> # ** Note: The value of 'corner0' is 1.119000e+002 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> # ** Note: The value of 'DINar_corner' is 1.115000e+002 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> # ** Note: The value of 'Cout' is -1.000000e+308 > >> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 > >> > >> I think that Cout should be the correct value after the process updates the > >> signal value. But the other module which accespts Cout of below code, still > >> sees Cout's value as -1.000000e+308. This results an out of range error. > >> > >> > >> What is wrong in my code and signal value understanding? > >> > >> > >> Thanks a lot to you. > >> > >> > >> > >> ............. > >> p1: process (clk) > >> variable tmp_XP, tmp_X : real; > >> begin > >> if (clk'event and clk = '1') then > >> if reset = '1' then > >> ar <= 0.0; ai <= 0.0; > >> br <= 0.0; bi <= 0.0; > >> else > >> if cnt < x"02" then > >> if cnt = x"00" then > >> corner0 <= DINar_corner; > >> elsif abs(corner0) < abs(DINar_corner) then > >> corner0_q_real <= corner0/DINar_corner; > >> Cout <= corner0_q_real; > >> report "The value of 'corner0' is " & real'image(corner0); > >> report "The value of 'DINar_corner' is " & real'image(DINar_corner); > >> report "The value of 'Cout' is " & real'image(corner0_q_real); > >> Sout <= 1; > >> else > >> corner0_q_real <= DINar_corner/corner0; > >> Cout <= corner0_q_real; > >> report "The value of 'Cout' is " & real'image(corner0_q_real); > >> Sout <= 0; > >> end if; > >> else > >> corner0_q_real <= DINar_corner/corner0; > >> end if; > > > > It is found that when I replace below one line to the two lines in previous > > post, it has no fatal error any more. I originally added one temporary > > signal for observation. It really delays one clock for the value. It was > > bug. > > Thanks, > > > > Cout <= -DINar_corner/corner0; > > Yes, this statement inside the clocked conditional results in a 1 clock > cycle delay, or actually more since it is in the ELSE clause while the > rest of the code is in the THEN part of the IF cnt < x"02" statement. > > I think it would work fine if you made the > Cout <= -DINar_corner/corner0; > statement a concurrent statement outside of the process. Then it will > be updated as soon as the values of DINar_corner and corner0 are updated. > > -- > > Rick Thanks. But there is another reciprocal case at the 'if' clause: corner0_q_real <= corner0/DINar_corner; which are conditioned on the two data absolute value (ABS) comparison. From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.182.106.228 with SMTP id gx4mr797636obb.34.1443572440249; Tue, 29 Sep 2015 17:20:40 -0700 (PDT) X-Received: by 10.50.112.4 with SMTP id im4mr27504igb.1.1443572440173; Tue, 29 Sep 2015 17:20:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no13559865igb.0!news-out.google.com!n2ni15991igy.0!nntp.google.com!kq10no13559859igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 17:20:39 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Subject: Could you explain this 'assert' description? From: fl Injection-Date: Wed, 30 Sep 2015 00:20:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8533 Hi, I learn 'assert' on this link: http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html I don't understand what this passage talks about: "If the message clause is ommited, a default message is output. The severity level and the name of the design unit containing the relevant assert statement may also be output" For this example line: assert not OVERFLOW) report "Accumulator overflowed" severity failure; "If the message clause is ommited" means remove "report "Accumulator overflowed" severity failure;"? What is your opinion on this? Thanks, From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about setting signal value Date: Tue, 29 Sep 2015 22:37:00 -0400 Organization: A noiseless patient Spider Lines: 101 Message-ID: References: <8634adec-cab7-4082-bee6-fb0940e70733@googlegroups.com> <8aefc0d0-fa40-46be-85d4-37568d7a38c9@googlegroups.com> <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 02:35:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="28234"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/F3njTo7mAKwfUTiTieC3y" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <35e118e4-6179-4d0e-a632-bef93d8ad40f@googlegroups.com> Cancel-Lock: sha1:g6BPMy36PjN2S3lXW7zpT8s9bS4= Xref: mx02.eternal-september.org comp.lang.vhdl:8534 On 9/29/2015 8:13 PM, fl wrote: > On Tuesday, September 29, 2015 at 6:31:01 PM UTC-4, rickman wrote: >> On 9/29/2015 5:44 PM, fl wrote: >>> On Tuesday, September 29, 2015 at 5:05:40 PM UTC-4, fl wrote: >>>> Hi, >>>> >>>> When I run a simulation VHDL code, there is a out of range fatal error. The >>>> signal source is from below code. corner0 is 111.5 while DINar_corner is >>>> 111.9. The division result should be below 1. Now the console output is: >>>> # ** Note: The value of 'corner0' is 1.119000e+002 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> # ** Note: The value of 'DINar_corner' is 1.115000e+002 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> # ** Note: The value of 'Cout' is -1.000000e+308 >>>> # Time: 30 ns Iteration: 3 Instance: /one_realmul0_tb/component1/component_corner1 >>>> >>>> I think that Cout should be the correct value after the process updates the >>>> signal value. But the other module which accespts Cout of below code, still >>>> sees Cout's value as -1.000000e+308. This results an out of range error. >>>> >>>> >>>> What is wrong in my code and signal value understanding? >>>> >>>> >>>> Thanks a lot to you. >>>> >>>> >>>> >>>> ............. >>>> p1: process (clk) >>>> variable tmp_XP, tmp_X : real; >>>> begin >>>> if (clk'event and clk = '1') then >>>> if reset = '1' then >>>> ar <= 0.0; ai <= 0.0; >>>> br <= 0.0; bi <= 0.0; >>>> else >>>> if cnt < x"02" then >>>> if cnt = x"00" then >>>> corner0 <= DINar_corner; >>>> elsif abs(corner0) < abs(DINar_corner) then >>>> corner0_q_real <= corner0/DINar_corner; >>>> Cout <= corner0_q_real; >>>> report "The value of 'corner0' is " & real'image(corner0); >>>> report "The value of 'DINar_corner' is " & real'image(DINar_corner); >>>> report "The value of 'Cout' is " & real'image(corner0_q_real); >>>> Sout <= 1; >>>> else >>>> corner0_q_real <= DINar_corner/corner0; >>>> Cout <= corner0_q_real; >>>> report "The value of 'Cout' is " & real'image(corner0_q_real); >>>> Sout <= 0; >>>> end if; >>>> else >>>> corner0_q_real <= DINar_corner/corner0; >>>> end if; >>> >>> It is found that when I replace below one line to the two lines in previous >>> post, it has no fatal error any more. I originally added one temporary >>> signal for observation. It really delays one clock for the value. It was >>> bug. >>> Thanks, >>> >>> Cout <= -DINar_corner/corner0; >> >> Yes, this statement inside the clocked conditional results in a 1 clock >> cycle delay, or actually more since it is in the ELSE clause while the >> rest of the code is in the THEN part of the IF cnt < x"02" statement. >> >> I think it would work fine if you made the >> Cout <= -DINar_corner/corner0; >> statement a concurrent statement outside of the process. Then it will >> be updated as soon as the values of DINar_corner and corner0 are updated. >> >> -- >> >> Rick > > Thanks. But there is another reciprocal case at the 'if' clause: > > corner0_q_real <= corner0/DINar_corner; > > which are conditioned on the two data absolute value (ABS) comparison. Ok then make it a when clause corner0_q_real <= corner0/DINar_corner when abs(corner0) < abs(DINar_corner) else DINar_corner/corner0; Or you can have two signals with one used in each part of the IF statement. The point is it needs to be combinatorial logic rather than sequential. Another way of doing it is to use a variable, but it can't be used outside the process unless you assign it to a signal and that largely defeats the purpose of using it to monitor the value. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Could you explain this 'assert' description? Date: Tue, 29 Sep 2015 22:40:33 -0400 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 02:38:42 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="28788"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+xieUA9rKlxtLunIt3rdB+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Cancel-Lock: sha1:IR7tgI2IRNLAdYvPRhXwCVm33+g= Xref: mx02.eternal-september.org comp.lang.vhdl:8535 On 9/29/2015 8:20 PM, fl wrote: > Hi, > > I learn 'assert' on this link: > > > > http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > > > For this example line: > > assert not OVERFLOW) report "Accumulator overflowed" severity failure; > > > "If the message clause is ommited" means remove "report "Accumulator > overflowed" severity failure;"? Yes, they are saying if you omit the report it will still print a default report with basic info like the line number, severity level and time. I don't know what is "required" by VHDL in this default report, but this is what I have seen simulators do. In fact, the default report is made even if you indicate a report. Your report is just added to the default. Try it, you'll see what your tool does. -- Rick From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.129.70.6 with SMTP id t6mr1669849ywa.5.1443588400430; Tue, 29 Sep 2015 21:46:40 -0700 (PDT) X-Received: by 10.50.79.136 with SMTP id j8mr292820igx.16.1443588400396; Tue, 29 Sep 2015 21:46:40 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no6394837qge.0!news-out.google.com!n2ni16168igy.0!nntp.google.com!kq10no13619104igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 29 Sep 2015 21:46:39 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.75.45; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.75.45 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Review of Data Type Issues From: Jim Lewis Injection-Date: Wed, 30 Sep 2015 04:46:40 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 3200 X-Received-Body-CRC: 644093104 Xref: mx02.eternal-september.org comp.lang.vhdl:8536 Some small clarifications: 1) Type Conversion Functions > > Between unrelated types. Requires an explicit function. > > Example - Unsigned to Integer, to_integer(U) > 2) Type Conversions (what many of us also call type casting) >From 1076-2008, Section 9.3.6, p 137 Explicit type conversions are allowed between closely related types. In particular, a type is closely related to itself. Other types are closely related only under the following conditions: -- Abstract numeric types -- Any abstract numeric type is closely related to any other abstract numeric type. -- Array types--Two array types are closely related if and only if the types have the same dimensionality and the element types are closely related\ No other types are closely related. > Example - Unsigned to signed, signed('0' & X_uv) > > 3) Type qualifier > > Specifies type when unclear. String arrays can be a number of types, so > require a qualifier to indicate the type. There can be multiple > overloaded functions with the same input types but different return > types, again a qualifier is required to resolve the issue. > > Example - Z_sv <= A_sv + signed'("1010") ; 4) Automatic Type Conversion: Two types convert automatically when both are subtypes of the same type. Combine this with every type is a subtype of itself, and you can conclude that two types will convert automatically when one is a subtype of the other. Hence, std_ulogic automatically converts to std_logic. Also in VHDL-2008, std_logic_vector is defined as: subtype std_logic_vector is {resolved} std_ulogic_vector ; Hence, in VHDL-2008, these two also convert automatically. This implies that in VHDL-2008 if you have an old package that includes overloading for both std_ulogic_vector and std_logic_vector, you need to remove one of them or it becomes ambiguous. > > I think this lists the ways that types are converted or indicated. > > Just trying to refresh my memory. The VHDL Tricks of the Trade (from which you borrowed examples) is still available at: http://synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Jim From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.107.163.80 with SMTP id m77mr3645312ioe.0.1443614055286; Wed, 30 Sep 2015 04:54:15 -0700 (PDT) X-Received: by 10.50.45.100 with SMTP id l4mr54274igm.9.1443614055215; Wed, 30 Sep 2015 04:54:15 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no14424360igb.0!news-out.google.com!z4ni6825ign.0!nntp.google.com!kq10no14424351igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 04:54:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Subject: What is one element of a signed array? From: fl Injection-Date: Wed, 30 Sep 2015 11:54:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8537 Hi, After a few progress on VHDL type conversion, I have new difficulties on the element access of an unsigned array. Please see the below example. How can I get the element of rs_SUM_RESULT ? I find this is wrong: bit0 <= rs_SUM_RESULT(1); Thanks for the kind replies. ................. signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); signal bit0 : bit; From newsfish@newsfish Tue Dec 29 16:43:58 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why do conversion functions need to be self defined in a project? Date: Wed, 30 Sep 2015 11:59:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <4cbc80be-939f-4b38-8b4c-0088ecdd04d0@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 30 Sep 2015 11:59:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="31264"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/obODJUw/AF7sKP5etZlWpywb5atMXfo4=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:nMfU7y2GvyfMTzMgfoyqdB3GJT4= Xref: mx02.eternal-september.org comp.lang.vhdl:8538 On Tue, 29 Sep 2015 12:00:12 -0400, rickman wrote: > On 9/29/2015 5:20 AM, Brian Drummond wrote: >> On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote: >> >>> Hi, >>> >>> I have a Matlab generated VHDL code project. It has such functions >>> defined in the testbench package. I am just curious about why these >>> looks frequent used functions need to write in such a project. It >>> makes the test bench file very long, not friendly reading to me. >> >> Put them in a utilities package so they don't clutter up the testbench. > I think the OP is using a utility to generate a test bench and it is > adding the various functions which are *not* part of any of the > conventional packages. So they stick them in the main file of the test > bench. If he moves these functions to a package he will need to do the > same work every time he generates the test bench again. Ah, then he has a Matlab problem rather than a VHDL problem. Hopefully someone else can help. -- Brian From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.13.224.132 with SMTP id j126mr2867894ywe.13.1443614716072; Wed, 30 Sep 2015 05:05:16 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr54909igb.15.1443614716042; Wed, 30 Sep 2015 05:05:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no6542986qge.0!news-out.google.com!z4ni6830ign.0!nntp.google.com!kq10no14435602igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 05:05:15 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Subject: Re: What is one element of a signed array? From: fl Injection-Date: Wed, 30 Sep 2015 12:05:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8539 On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > Hi, > > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. > > How can I get the element of rs_SUM_RESULT ? > > I find this is wrong: > bit0 <= rs_SUM_RESULT(1); > > > Thanks for the kind replies. > > ................. > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; Using to_bit seems to work in my previous post. But for convert rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different types and widths. What is your method? Thanks, type BYTE is array (0 to 7) of BIT; signal sig_byte : BYTE; signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.13.242.134 with SMTP id b128mr3235081ywf.7.1443617048775; Wed, 30 Sep 2015 05:44:08 -0700 (PDT) X-Received: by 10.50.65.66 with SMTP id v2mr57664igs.5.1443617048706; Wed, 30 Sep 2015 05:44:08 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!z77no6558467qge.1!news-out.google.com!n2ni16519igy.0!nntp.google.com!kq10no13912281igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 05:44:08 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Subject: Where does the XOR come to play? From: fl Injection-Date: Wed, 30 Sep 2015 12:44:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 16 Xref: mx02.eternal-september.org comp.lang.vhdl:8540 Hi, I am working on a LUT in a project. The input entries are signed. In order to same memory, only positive entries are considered in the LUT. Thus, negative input is first converted to positive data. Then, the result is converted back to negative. These input data is 2's complementary format. On the original paper, it had the following description. I am still new to FPGA. I am not clear about where and how to use 'XOR' in the process. Could you explain it to me? Thanks a lot. Further reduction in the memory size is achieved by storing only positive values in the LUT. The sign of the division result can be evaluated by an XOR gate. From newsfish@newsfish Tue Dec 29 16:43:58 2015 From: "Michael Kellett" Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: wed, 30 sep 2015 14:51:19 +0100 Message-ID: Content-Type: text/plain; charset="iso-8859-1" References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> X-Newsreader: UseNeXT 5.64 Organization: Welcome to Aviteo Ltd DE Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!feeder1.xsusenet.com!feeder.usenet.farm!94.232.116.13.MISMATCH!feed.xsnews.nl!border03.ams.xsnews.nl!feeder03.ams.xsnews.nl!abp002.ams.xsnews.nl!usenext.xennanews.com!not-for-mail Lines: 30 Injection-Date: Wed, 30 Sep 2015 15:51:34 +0200 Injection-Info: usenext.xennanews.com; mail-complaints-to="usenext@xennanews.com" Xref: mx02.eternal-september.org comp.lang.vhdl:8541 fl: > Hi, > > I am working on a LUT in a project. The input entries are signed. In order to > same memory, only positive entries are considered in the LUT. Thus, negative > input is first converted to positive data. Then, the result is converted back > to negative. These input data is 2's complementary format. > > On the original paper, it had the following description. I am still new to > FPGA. I am not clear about where and how to use 'XOR' in the process. > > Could you explain it to me? Thanks a lot. > > > > Further reduction in the memory size is achieved by storing only positive > values in the LUT. The sign of the division result can be evaluated by an XOR > gate. XORing the signs of the multiplier and multiplicand to get the sign of the answer ? MK From newsfish@newsfish Tue Dec 29 16:43:58 2015 X-Received: by 10.13.223.129 with SMTP id i123mr3873601ywe.33.1443629483719; Wed, 30 Sep 2015 09:11:23 -0700 (PDT) X-Received: by 10.50.147.100 with SMTP id tj4mr344215igb.2.1443629483682; Wed, 30 Sep 2015 09:11:23 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!z77no6640609qge.1!news-out.google.com!z4ni7007ign.0!nntp.google.com!kq10no14630996igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 09:11:22 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What is one element of a signed array? From: KJ Injection-Date: Wed, 30 Sep 2015 16:11:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 19 Xref: mx02.eternal-september.org comp.lang.vhdl:8542 On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > Hi, >=20 > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. >=20 > How can I get the element of rs_SUM_RESULT ? >=20 > I find this is wrong: > bit0 <=3D rs_SUM_RESULT(1); >=20 You haven't said what you're trying to do nor have you said in what way you= are finding something 'wrong'. I can guess that because you call the sign= al 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for what= ever reason you've selected bit 1 instead. bit0 <=3D rs_SUM_RESULT(0); Kevin From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: Wed, 30 Sep 2015 15:56:28 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 19:54:35 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="25131"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+E7VW/SheDnTWi246rjgjl" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> Cancel-Lock: sha1:FcnbJLzRy9hbCSnfsUGd9jTxAz4= Xref: mx02.eternal-september.org comp.lang.vhdl:8543 On 9/30/2015 8:44 AM, fl wrote: > Hi, > > I am working on a LUT in a project. The input entries are signed. In order to > same memory, only positive entries are considered in the LUT. Thus, negative > input is first converted to positive data. Then, the result is converted back > to negative. These input data is 2's complementary format. > > On the original paper, it had the following description. I am still new to > FPGA. I am not clear about where and how to use 'XOR' in the process. > > Could you explain it to me? Thanks a lot. > > > > Further reduction in the memory size is achieved by storing only positive > values in the LUT. The sign of the division result can be evaluated by an XOR > gate. Are you doing a division by LUT? What are the sizes of your input operands? The sign of the output will be the XOR of the sign of the two inputs to a division, just as Michael indicated for a multiplication. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Wed, 30 Sep 2015 16:01:05 -0400 Organization: A noiseless patient Spider Lines: 45 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Sep 2015 19:59:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="26420"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+D+7ZTLqlCLWjad92rIy9d" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: <92e4f30a-b191-4959-b64a-67e409261b77@googlegroups.com> Cancel-Lock: sha1:ry+V+eC4asuEhZHDP1nTcfRIw6U= Xref: mx02.eternal-september.org comp.lang.vhdl:8544 On 9/30/2015 8:05 AM, fl wrote: > On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: >> Hi, >> >> After a few progress on VHDL type conversion, I have new difficulties on >> the element access of an unsigned array. Please see the below example. >> >> How can I get the element of rs_SUM_RESULT ? >> >> I find this is wrong: >> bit0 <= rs_SUM_RESULT(1); >> >> >> Thanks for the kind replies. >> >> ................. >> signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); >> signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); >> signal bit0 : bit; > > Using to_bit seems to work in my previous post. But for convert > rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different > types and widths. What is your method? > Thanks, > > > > > type BYTE is array (0 to 7) of BIT; > signal sig_byte : BYTE; > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); This begs the question of why you need to use a bit type? They don't do anything the signed type won't do. I don't think there are any standard conversion routines for signed or unsigned to a bit vector. You will need to write one. It is just a function that takes a signed value as input and returns a bit vector with the same width. It will need a loop that assigns each bit one at a time using the conversion you found for the single bit. The input and output can be unconstrained which means it will work for any width of data. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Where does the XOR come to play? Date: Wed, 30 Sep 2015 21:20:30 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 25 Message-ID: References: <1c2c4bcb-7f18-4301-b9aa-43db6c43cdc5@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8545 fl wrote: > I am working on a LUT in a project. The input entries are signed. > In order to same memory, only positive entries are considered > in the LUT. Thus, negative input is first converted to positive data. > Then, the result is converted back to negative. > These input data is 2's complementary format. > On the original paper, it had the following description. > I am still new to FPGA. I am not clear about where and how > to use 'XOR' in the process. > Could you explain it to me? Thanks a lot. Sounds like you need a twos complement absolute value. If the input value is positive, it is fine. If negative, invert all the bits (with XOR) and add one. In the end, to convert back to twos complement, if the result should be negative invert the bits (XOR again) and add one. -- glen From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.129.57.9 with SMTP id g9mr5991153ywa.19.1443664555785; Wed, 30 Sep 2015 18:55:55 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr4051igb.15.1443664555759; Wed, 30 Sep 2015 18:55:55 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!v79no6833744qge.0!news-out.google.com!z4ni7410ign.0!nntp.google.com!kq10no15023293igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 30 Sep 2015 18:55:54 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.116.247; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.116.247 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: What is one element of a signed array? From: fl Injection-Date: Thu, 01 Oct 2015 01:55:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8546 On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote: > On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: > > Hi, > >=20 > > After a few progress on VHDL type conversion, I have new difficulties o= n > > the element access of an unsigned array. Please see the below example. > >=20 > > How can I get the element of rs_SUM_RESULT ? > >=20 > > I find this is wrong: > > bit0 <=3D rs_SUM_RESULT(1); > >=20 >=20 > You haven't said what you're trying to do nor have you said in what way y= ou are finding something 'wrong'. I can guess that because you call the si= gnal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for wh= atever reason you've selected bit 1 instead. >=20 > bit0 <=3D rs_SUM_RESULT(0); >=20 > Kevin Excuse me. I didn't say the question clearly.=20 My original intention was to convert array larger or smaller to BYTE. It was inspired from an online code. With rickman's new post, I know the=20 less important role of bit vector. The conversion is to use a for loop on= =20 bit level. That's all to my question. With several VHDL type coding projects, I feel it is clear and manageable after several tryings on it in the past. Thanks, you folks.=20 type BYTE is array (0 to 7) of BIT; signal sig_byte : BYTE; signal rs_SUM_RESULT : signed(4 downto 0) :=3D (others =3D> '0');=20 rs_SUM_RESULT From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Wed, 30 Sep 2015 23:40:16 -0400 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 03:38:26 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="17740"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kyvOkO56Ddj/hyG1AQmOw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:MrghEdnOVbK699LxEFSMuG+cM0E= Xref: mx02.eternal-september.org comp.lang.vhdl:8547 On 9/30/2015 9:55 PM, fl wrote: > On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote: >> On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote: >>> Hi, >>> >>> After a few progress on VHDL type conversion, I have new difficulties on >>> the element access of an unsigned array. Please see the below example. >>> >>> How can I get the element of rs_SUM_RESULT ? >>> >>> I find this is wrong: >>> bit0 <= rs_SUM_RESULT(1); >>> >> >> You haven't said what you're trying to do nor have you said in what way you are finding something 'wrong'. I can guess that because you call the signal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for whatever reason you've selected bit 1 instead. >> >> bit0 <= rs_SUM_RESULT(0); >> >> Kevin > > Excuse me. I didn't say the question clearly. > My original intention was to convert array larger or smaller to BYTE. > It was inspired from an online code. With rickman's new post, I know the > less important role of bit vector. The conversion is to use a for loop on > bit level. That's all to my question. With several VHDL type coding > projects, I feel it is clear and manageable after several tryings on it in > the past. Thanks, you folks. > > > > type BYTE is array (0 to 7) of BIT; > signal sig_byte : BYTE; > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > rs_SUM_RESULT Not sure if your post was cut off. I never use bits, so I am not so familiar with that data type, but it seems the std_logic_1164 library has conversion functions between bit or bit_vector and std_logic or std_logic_vector respectively. That would make a conversion with signed and unsigned trivial without using looping or making your own function. Are these problems homework for a class? If so, I think you are getting the right kind of advice to help you see the solution rather than just being given the answers. BTW, BYTE can be defined this way too... type BYTE is bit_vector (7 downto 0); This will work with all the conversion functions while I'm not sure if your BYTE declaration will. Like I said, I'm a bit rusty with this stuff. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.107.134.150 with SMTP id q22mr8183177ioi.31.1443698634283; Thu, 01 Oct 2015 04:23:54 -0700 (PDT) X-Received: by 10.50.66.144 with SMTP id f16mr22756igt.14.1443698634214; Thu, 01 Oct 2015 04:23:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no15218303igb.0!news-out.google.com!z4ni7795ign.0!nntp.google.com!kq10no15218293igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 04:23:53 -0700 (PDT) In-Reply-To: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1e3d47f7-8a4c-43a9-88be-5e0c95366367@googlegroups.com> Subject: Re: What is one element of a signed array? From: Thomas Stanka Injection-Date: Thu, 01 Oct 2015 11:23:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8548 Am Mittwoch, 30. September 2015 13:54:19 UTC+2 schrieb fl: [..] > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; This depends on _your_ definition of signed. All standardised definitions use (un)signed as vector of std_logic. so the code would work if bit0 is of type std_logic, should even work with std_ulogic. Else you need to convert the result of singedSignal(1) to bit before assigning to a bit value. From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.50.122.2 with SMTP id lo2mr2982671igb.2.1443710917228; Thu, 01 Oct 2015 07:48:37 -0700 (PDT) X-Received: by 10.50.4.70 with SMTP id i6mr41110igi.12.1443710917163; Thu, 01 Oct 2015 07:48:37 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no15313846igb.0!news-out.google.com!n2ni17574igy.0!nntp.google.com!kq10no15313838igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 07:48:36 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: <327cf532-4879-4f5e-b5aa-c39d5155d31b@googlegroups.com> <47dffef1-b29c-4450-9b12-eae352d83b50@googlegroups.com> <03072ae3-7e59-44a1-8ed5-21b3aeaa8bc3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Multiplier using 1 bit full adder problem From: zhangth1991@gmail.com Injection-Date: Thu, 01 Oct 2015 14:48:37 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1419 X-Received-Body-CRC: 115681467 Xref: mx02.eternal-september.org comp.lang.vhdl:8549 It is a vector multiplier which use a full adder. And we should judge if a or b is positive and negative to get correct answer. From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: What is one element of a signed array? Date: Thu, 1 Oct 2015 15:57:07 +0000 (UTC) Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <2b33ec3d-5688-4f01-a56a-4745866f53e3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 1 Oct 2015 15:57:07 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="18761"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19d8Nkd7xV22Rdh0wj5MYy3" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:YYhnN07/iEsv5EjnlWp+JDPv1zQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8550 On Wed, 30 Sep 2015 04:54:14 -0700, fl wrote: > Hi, > > After a few progress on VHDL type conversion, I have new difficulties on > the element access of an unsigned array. Please see the below example. > > How can I get the element of rs_SUM_RESULT ? > > I find this is wrong: > bit0 <= rs_SUM_RESULT(1); > > > Thanks for the kind replies. > > ................. > signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); > signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); > signal bit0 : bit; Assuming that you're using the signed/unsigned from ieee.numeric_std? std_logic. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.50.43.233 with SMTP id z9mr3542795igl.9.1443719070081; Thu, 01 Oct 2015 10:04:30 -0700 (PDT) X-Received: by 10.50.143.12 with SMTP id sa12mr15411igb.7.1443719070064; Thu, 01 Oct 2015 10:04:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14655995igb.0!news-out.google.com!z4ni8040ign.0!nntp.google.com!kq10no15372150igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 1 Oct 2015 10:04:29 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Multiplier using 1 bit full adder From: zhangth1991@gmail.com Injection-Date: Thu, 01 Oct 2015 17:04:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8551 I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? My code is as followed --multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Multiplier_VHDL is GENERIC (WIDTH:INTEGER); PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); end entity Multiplier_VHDL; architecture Behavioral of Multiplier_VHDL is signal a_temp:std_logic_vector(width-1 downto 0); signal b_temp:std_logic_vector(width-1 downto 0); signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0'); signal y_temp:std_logic_vector(2*width-1 downto 0); begin proc_multiplier1: process(a_temp,b_temp) begin a_temp<=a; b_temp<=b; calculation_out: for i in 0 to width-1 loop if b_temp(i)='1' then mid(width-1+i downto i)<=a_temp; end if; calculation_in: for j in 0 to 2*width-1 loop y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j); cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j)); end loop calculation_in; mid_temp<=y_temp; cout_mid<=(others=>'0'); mid<=(others=>'0'); end loop calculation_out; end process; y<=y_temp; end architecture Behavioral; There is a warning message Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Thu, 1 Oct 2015 13:38:26 -0400 Organization: A noiseless patient Spider Lines: 69 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 17:36:28 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="519"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ZkKLd6mDhwHt0hLgUraVb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:TMWweKa/mbdTf/axYWlaIJBhElQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8552 On 10/1/2015 1:04 PM, zhangth1991@gmail.com wrote: > I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? > > My code is as followed > --multiplier > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity Multiplier_VHDL is > GENERIC (WIDTH:INTEGER); > PORT(a:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > b:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); > y:OUT STD_LOGIC_VECTOR(2*WIDTH-1 DOWNTO 0)); > end entity Multiplier_VHDL; > > architecture Behavioral of Multiplier_VHDL is > signal a_temp:std_logic_vector(width-1 downto 0); > signal b_temp:std_logic_vector(width-1 downto 0); > signal mid:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal mid_temp:std_logic_vector(2*width-1 downto 0):=(others=>'0'); > signal cout_mid:std_logic_vector(2*width downto 0):=(others=>'0'); > signal y_temp:std_logic_vector(2*width-1 downto 0); > begin > proc_multiplier1: > process(a_temp,b_temp) > begin > a_temp<=a; > b_temp<=b; > calculation_out: > for i in 0 to width-1 loop > if b_temp(i)='1' then > mid(width-1+i downto i)<=a_temp; > end if; > calculation_in: > for j in 0 to 2*width-1 loop > y_temp(j)<=mid_temp(j) xor mid(j) xor cout_mid(j); > cout_mid(j+1)<=(mid_temp(j) and mid(j)) or (mid_temp(j) and cout_mid(j)) or (cout_mid(j) and mid(j)); > end loop calculation_in; > mid_temp<=y_temp; > cout_mid<=(others=>'0'); > mid<=(others=>'0'); > end loop calculation_out; > > end process; > > y<=y_temp; > > end architecture Behavioral; > > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf I don't know what this warning is about. Any chance you have two copies of the simulator running? I don't understand your code. I see one error. Your process sensitivity list includes two signals that are updated within the process. I think you meant to use a and b in the sensitivity list, no? You need to run your code in the simulator and explore the various signals to see if the code is doing what you need. Posting code here to look for some silly mistakes is ok, but no one is likely to debug your code for you. I'm not even sure how it is supposed to work. You seem to have a lot of extraneous signals for a simple multiplier. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Thu, 01 Oct 2015 14:28:16 -0400 Organization: Alacron, Inc. Lines: 21 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 1 Oct 2015 18:26:18 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="12021"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/A7elSeu5Vf7/egah6Bic5afVGRdTENVM=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:JAozhjvbdZGH09RP2iZO5ra8lCo= Xref: mx02.eternal-september.org comp.lang.vhdl:8553 zhangth1991@gmail.com wrote: > I have a problem to build a multiplier. But it seems something wrong with my code that the output did not update. Anyone can help me? > > My code is as followed [code snipped] > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf That warning is something I've run into a lot with ModelSim, especially older versions. It probably has nothing to do with your problems, as ModelSim will simply create a WLF file with some random name and use it instead of "vsim.wlf" I seem to recall this happens after you have run some number of different projects and not cleaned up the old vsim.wlf files. By the way, these files can get quite large and it is usually worth it to remove them when you are done with a project to reclaim the disk space. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.50.79.234 with SMTP id m10mr2649511igx.5.1443773259471; Fri, 02 Oct 2015 01:07:39 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr41030igg.16.1443773259392; Fri, 02 Oct 2015 01:07:39 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no14804901igb.0!news-out.google.com!n2ni18230igy.0!nntp.google.com!kq10no15615731igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Oct 2015 01:07:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.239.106.184; posting-account=0cly4QoAAACiQ1EaiVjiztUOIZacefwg NNTP-Posting-Host: 46.239.106.184 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Subject: Re: Multiplier using 1 bit full adder From: zhangth1991@gmail.com Injection-Date: Fri, 02 Oct 2015 08:07:39 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8554 The problem is I dont know why I cannot assign y<=y_temp when a and b change the value From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.roellig-ltd.de!open-news-network.org!cyclone01.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer01.am1!peering.am1!peer02.fr7!news.highwinds-media.com!post02.fr7!fx33.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: Multiplier using 1 bit full adder References: Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151001-2, 01/10/2015), Outbound message X-Antivirus-Status: Clean Lines: 31 Message-ID: <78rPx.23670$LT7.1399@fx33.am4> NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1443774083 81.109.142.154 (Fri, 02 Oct 2015 08:21:23 UTC) NNTP-Posting-Date: Fri, 02 Oct 2015 08:21:23 UTC Organization: virginmedia.com Date: Fri, 2 Oct 2015 09:21:19 +0100 X-Received-Body-CRC: 1773550843 X-Received-Bytes: 2341 Xref: mx02.eternal-september.org comp.lang.vhdl:8555 On 01/10/2015 18:04, zhangth1991@gmail.com wrote: .. > > There is a warning message > Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf > This happens when your simulation crashes, it sets a lock bit in the vsim.wlf file which prevents Modelsim from overwriting it (vsim.wlf is the default name). You can load the vsim.wlf file (vsim -view vsim.wlf) and see what lead to the crash (or get close to it). You need to delete the vsim.wlf file as Modelsim will continue to create new wlfxxxx files until the file is deleted, Hans www.ht-lab.com 02/10/2015 09:18 1,387 transcript 03/09/2015 20:21 49,152 vsim.wlf 03/11/2005 12:21 1,105 wave.do 04/09/2015 17:38 786,432 wlft1sddnc 06/09/2015 20:52 57,344 wlftgbhqzx 10/09/2015 11:35 540,672 wlftiqcymw 16/09/2015 15:17 57,344 wlftq4i743 09/09/2015 17:54 778,240 wlftq5mdd3 08/09/2015 17:44 49,152 wlftqe9ds1 05/09/2015 12:55 57,344 wlftr57znr 27/08/2015 13:59 work 16/11/2005 15:11 34 zoom.tcl 27 File(s) 2,949,498 bytes 4 Dir(s) 487,531,675,648 bytes free From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Fri, 02 Oct 2015 09:26:39 -0400 Organization: Alacron, Inc. Lines: 15 Message-ID: References: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 13:24:55 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="6214"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/NYSLb4TYLd9Xo+niZOFIxPLmwJlg+oZI=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Cancel-Lock: sha1:/XlJmE4K1O2T08hQmf39b7CMFOY= Xref: mx02.eternal-september.org comp.lang.vhdl:8556 zhangth1991@gmail.com wrote: > The problem is I dont know why I cannot assign y<=y_temp when a and b change the value For simulation, only items in the process sensitivity will "change the value." In your main process, you only have a_temp and b_temp in the sensitivity list. Since these are only assigned within the process, and the process needs them to change in order to actually run, then the process never triggers and all your outputs remain undefined. You need to have a and b in the sensitivity list to trigger the process. Also it is likely that you really wanted a_temp and b_temp to be variables rather than signals. -- Gabor From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.129.70.6 with SMTP id t6mr14178766ywa.5.1443797417632; Fri, 02 Oct 2015 07:50:17 -0700 (PDT) X-Received: by 10.50.28.19 with SMTP id x19mr63300igg.16.1443797417598; Fri, 02 Oct 2015 07:50:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!v79no7171920qge.0!news-out.google.com!n2ni18498igy.0!nntp.google.com!kq10no14907280igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 2 Oct 2015 07:50:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Subject: VHDL From: fwetie@googlemail.com Injection-Date: Fri, 02 Oct 2015 14:50:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 8955 X-Received-Body-CRC: 2066400661 Xref: mx02.eternal-september.org comp.lang.vhdl:8557 hello, please i am looking for someone who can help me to solve my pb. this is my code : Bonjour a tous, je cherche de l'aide pour mon projet sur VHDL: mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. voici mes codes: --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity Lane is port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; DATA_IN : IN std_logic; FPP_SEC_EN : IN std_logic; FPP_TURN_SEL : IN std_logic; FPP_CORE_SEL : IN std_logic; FPP_REGP_BYP : IN std_logic; FPP_SOURCE_SEL : IN std_logic; FPP_REGN_BYP : IN std_logic; FPP_PRI_EN : IN std_logic; Primary_Port : INOUT std_logic; Secondary_Port : INOUT std_logic; FPP_TO_CORE : OUT std_logic; DATA_OUT : OUT std_logic ); end Lane; architecture archLane of Lane is component Buf port ( A : IN std_logic; Y : OUT std_logic ); end component; component BufX port ( A : IN std_logic; en : in std_logic; Y : OUT std_logic ); end component; component Mux port ( Sel : IN std_logic; E : IN std_logic; F : IN std_logic; Z : OUT std_logic ); end component; component FlipFlopP port ( CLK : IN std_logic; D : IN std_logic; Q : OUT std_logic ); end component; component FlipFlopN port ( CLK : IN std_logic; D : IN std_logic; Q : OUT std_logic ); end component; signal Sec_buf_in_to_Mux6 : std_logic; signal Sel_BufX_in_to_Mux3 : std_logic; signal Sec_Pri_Buf_IN_TO_MUX6 :std_logic; signal Sec_Pri_BufY_IN_TO_MUX1 : std_logic; signal sig_from_Mux1_ff1_to_Mux3_ff3 : std_logic; signal sig_from_Mux1_to_FF1 : std_logic; signal sig_from_Mux5_to_FF2_Mux2 :std_logic; signal sig_from_FF2_to_Mux2 : std_logic; signal sig_from_Mux3_to_FF3 : std_logic; signal sig_from_Mux4_to_Mux5 : std_logic; signal FPP_TO_CORE_INT : std_logic; begin FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE Sec_Buf_In : Buf port map ( A => Secondary_Port, Y => Sec_buf_in_to_Mux6); Sec_BufX_Out : BufX port map ( A => Sel_BufX_in_to_Mux3, en => FPP_SEC_EN , Y => Secondary_Port); Pri_Buf_In : Buf port map ( A => Primary_Port, Y => Sec_Pri_Buf_IN_TO_MUX6); Pri_BufX_Out : BufX port map ( A => Sec_Pri_BufY_IN_TO_MUX1, en => FPP_PRI_EN, Y => Primary_Port); MUX1 : Mux port map ( E => Sig_from_Mux1_ff1_to_Mux3_ff3, F => sig_from_Mux1_to_FF1, Z => Sec_Pri_BufY_IN_TO_MUX1, Sel => FPP_REGN_BYP); MUX2 : Mux port map ( E => sig_from_Mux5_to_FF2_Mux2, F => sig_from_FF2_to_Mux2, Z => DATA_OUT, Sel => FPP_REGP_BYP ); MUX3 : Mux port map ( E => sig_from_Mux1_ff1_to_Mux3_ff3, F => sig_from_Mux3_to_FF3, Z => Sel_BufX_in_to_Mux3, Sel => FPP_REGN_BYP ); MUX4 : Mux port map ( E => DATA_IN, F => FPP_FROM_CORE, Z => sig_from_Mux4_to_Mux5, Sel => FPP_TURN_SEL ); MUX5 : Mux port map ( E => sig_from_Mux4_to_Mux5, F => FPP_TO_CORE_INT, Z => sig_from_Mux5_to_FF2_Mux2, Sel => FPP_CORE_SEL ); MUX6 : Mux port map ( E => Sec_buf_in_to_Mux6, F => Sec_pri_buf_in_to_Mux6, Z => FPP_TO_CORE_INT, Sel => FPP_SOURCE_SEL ); Flipflop1 : FlipFlopN port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3, D => sig_from_Mux1_to_FF1, CLK => FPP_CLK_IN ); Flipflop2 : FlipFlopP port map ( Q => sig_from_Mux5_to_FF2_Mux2, D => sig_from_FF2_to_Mux2, CLK => FPP_CLK_IN ); Flipflop3 : FlipFlopN port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3, D => sig_from_Mux3_to_FF3, CLK => FPP_CLK_IN ); end archLane; et mon testbench library ieee; use ieee.std_logic_1164.all; entity testPrimToSecCase1 is end testPrimToSecCase1; architecture archPrimToSecTest of testPrimToSecCase1 is component Lane Port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; DATA_IN : IN std_logic; FPP_SEC_EN : IN std_logic; FPP_TURN_SEL : IN std_logic; FPP_CORE_SEL : IN std_logic; FPP_REGP_BYP : IN std_logic; FPP_SOURCE_SEL : IN std_logic; FPP_REGN_BYP : IN std_logic; FPP_PRI_EN : IN std_logic; Primary_Port : INOUT std_logic; Secondary_Port : INOUT std_logic; DATA_OUT : OUT std_logic; FPP_TO_CORE : OUT std_logic ); end component; signal S_FPP_CLK_IN : std_logic; signal S_FPP_FROM_CORE : std_logic; signal S_DATA_IN : std_logic; signal S_FPP_SEC_EN : std_logic; signal S_FPP_TURN_SEL : std_logic; signal S_FPP_CORE_SEL : std_logic; signal S_FPP_REGP_BYP : std_logic; signal S_FPP_SOURCE_SEL : std_logic; signal S_FPP_REGN_BYP : std_logic; signal S_FPP_PRI_EN : std_logic; signal S_Primary_Port : std_logic; signal S_Secondary_Port : std_logic; signal s_FPP_TO_CORE_INT : std_logic; FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE begin U : Lane port map ( S_FPP_CLK_IN, S_FPP_FROM_CORE, S_DATA_IN, S_FPP_SEC_EN, S_FPP_TURN_SEL, S_FPP_CORE_SEL, S_FPP_REGP_BYP, S_FPP_SOURCE_SEL, S_FPP_REGN_BYP, S_FPP_PRI_EN, S_Primary_Port, S_Secondary_Port ); processClock : process begin S_FPP_CLK_IN <= '0'; wait for 10 ns; S_FPP_CLK_IN <= '1'; wait for 10 ns; end process processClock; Stimuli : process begin S_FPP_FROM_CORE <= '0'; S_DATA_IN <= '0'; S_FPP_SEC_EN <= '0'; S_FPP_TURN_SEL <= '0'; S_FPP_CORE_SEL <= '0'; S_FPP_REGP_BYP <= '0'; S_FPP_SOURCE_SEL <= '0'; S_FPP_REGN_BYP <= '0'; S_FPP_PRI_EN <= '0'; S_Primary_Port <= '0'; S_Secondary_Port <= '0'; wait until S_FPP_CLK_IN <= '1'; S_FPP_FROM_CORE <= '-'; S_DATA_IN <= '-'; S_FPP_SEC_EN <= '1'; S_FPP_TURN_SEL <= '-'; S_FPP_CORE_SEL <= '1'; S_FPP_REGP_BYP <= '0'; S_FPP_SOURCE_SEL <= '0'; S_FPP_REGN_BYP <= '0'; S_FPP_PRI_EN <= '0'; wait until S_FPP_CLK_IN <= '1'; S_Primary_Port <= '0'; wait until S_FPP_CLK_IN <= '1'; S_Secondary_Port <= '1'; wait until S_FPP_CLK_IN <= '1'; end process Stimuli; end archPrimToSecTest; i am looking for sombody to correct my testbench. thanks you for your help. Franck From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Fri, 02 Oct 2015 15:20:11 -0400 Organization: Alacron, Inc. Lines: 66 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 19:18:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="26755"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+3jtCFSZG0pfXXf2LcPEINEQce3TaIj78=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Cancel-Lock: sha1:mBVNf05T9wAoGt27Jza7tKGFswY= Xref: mx02.eternal-september.org comp.lang.vhdl:8558 fwetie@googlemail.com wrote: > hello, > please i am looking for someone who can help me to solve my pb. > this is my code : > > Bonjour a tous, > je cherche de l'aide pour mon projet sur VHDL: > mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > voici mes codes: > [snip] > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; > S_DATA_IN <= '0'; > S_FPP_SEC_EN <= '0'; > S_FPP_TURN_SEL <= '0'; > S_FPP_CORE_SEL <= '0'; > S_FPP_REGP_BYP <= '0'; > S_FPP_SOURCE_SEL <= '0'; > S_FPP_REGN_BYP <= '0'; > S_FPP_PRI_EN <= '0'; > S_Primary_Port <= '0'; > S_Secondary_Port <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; > S_DATA_IN <= '-'; > S_FPP_SEC_EN <= '1'; > S_FPP_TURN_SEL <= '-'; > S_FPP_CORE_SEL <= '1'; > S_FPP_REGP_BYP <= '0'; > S_FPP_SOURCE_SEL <= '0'; > S_FPP_REGN_BYP <= '0'; > S_FPP_PRI_EN <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '1'; > > S_Secondary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; > i am looking for sombody to correct my testbench. > thanks you for your help. > Franck Well, you didn't give much of a description of why the testbench does not function correctly, but my guess is that you wanted to wait for edges of the clock and not levels. Also it's unlikely that you want to wait for a clock signal to be "less than or equal to 1" even if you did want to check for a level. Probably something like wait until rising_edge (S_FPP_CLK_IN); -- Gabor From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Multiplier using 1 bit full adder Date: Fri, 2 Oct 2015 16:42:21 -0400 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4ab578b2-956a-41cb-8f2a-cfaf07b3480a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 2 Oct 2015 20:40:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="13053"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18A/Xe6tqekeY8n5zSvOPfU" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:HUGRhP9WsL+ZNcYxTB8A/OFTW7E= Xref: mx02.eternal-september.org comp.lang.vhdl:8559 On 10/2/2015 9:26 AM, GaborSzakacs wrote: > zhangth1991@gmail.com wrote: >> The problem is I dont know why I cannot assign y<=y_temp when a and b >> change the value > > For simulation, only items in the process sensitivity > will "change the value." In your main process, you > only have a_temp and b_temp in the sensitivity list. > Since these are only assigned within the process, and > the process needs them to change in order to actually > run, then the process never triggers and all your outputs > remain undefined. You need to have a and b in the sensitivity > list to trigger the process. Also it is likely that you really > wanted a_temp and b_temp to be variables rather than signals. I've already told him his sensitivity list is wrong. Maybe he didn't see my message. a_temp and b_temp really aren't needed. They are never reassigned, so they are just duplicates of a and b. He should just use a and b in the expressions instead of a_temp and b_temp. I'm not sure what he is doing with this code actually. He seems to be intending a bit serial adder, but rather than describing a shifter with a one bit adder, he is describing a standard parallel addition, one bit at a time, without a clock. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.182.29.40 with SMTP id g8mr16593319obh.27.1443861329993; Sat, 03 Oct 2015 01:35:29 -0700 (PDT) X-Received: by 10.50.45.100 with SMTP id l4mr12024igm.9.1443861329967; Sat, 03 Oct 2015 01:35:29 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no16047456igb.0!news-out.google.com!n2ni19199igy.0!nntp.google.com!kq10no15080436igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 3 Oct 2015 01:35:29 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=88.152.155.140; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 88.152.155.140 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Sat, 03 Oct 2015 08:35:29 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8560 Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > fwetie@googlemail.com wrote: > > hello, > > please i am looking for someone who can help me to solve my pb. > > this is my code : > > > > Bonjour a tous, > > je cherche de l'aide pour mon projet sur VHDL: > > mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > > voici mes codes: > > > > [snip] > > > Stimuli : process > > begin > > > > S_FPP_FROM_CORE <= '0'; > > S_DATA_IN <= '0'; > > S_FPP_SEC_EN <= '0'; > > S_FPP_TURN_SEL <= '0'; > > S_FPP_CORE_SEL <= '0'; > > S_FPP_REGP_BYP <= '0'; > > S_FPP_SOURCE_SEL <= '0'; > > S_FPP_REGN_BYP <= '0'; > > S_FPP_PRI_EN <= '0'; > > S_Primary_Port <= '0'; > > S_Secondary_Port <= '0'; > > > > wait until S_FPP_CLK_IN <= '1'; > > > > S_FPP_FROM_CORE <= '-'; > > S_DATA_IN <= '-'; > > S_FPP_SEC_EN <= '1'; > > S_FPP_TURN_SEL <= '-'; > > S_FPP_CORE_SEL <= '1'; > > S_FPP_REGP_BYP <= '0'; > > S_FPP_SOURCE_SEL <= '0'; > > S_FPP_REGN_BYP <= '0'; > > S_FPP_PRI_EN <= '0'; > > > > wait until S_FPP_CLK_IN <= '1'; > > > > S_Primary_Port <= '0'; > > wait until S_FPP_CLK_IN <= '1'; > > > > S_Secondary_Port <= '1'; > > wait until S_FPP_CLK_IN <= '1'; > > > > > > end process Stimuli; > > > > end archPrimToSecTest; > > i am looking for sombody to correct my testbench. > > thanks you for your help. > > Franck > > Well, you didn't give much of a description of why the testbench does > not function correctly, but my guess is that you wanted to wait for > edges of the clock and not levels. Also it's unlikely that you > want to wait for a clock signal to be "less than or equal to 1" > even if you did want to check for a level. Probably something like > > wait until rising_edge (S_FPP_CLK_IN); > > -- > Gabor danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response Franck From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Sat, 3 Oct 2015 06:29:48 -0400 Organization: A noiseless patient Spider Lines: 77 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 3 Oct 2015 10:27:47 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="22486"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+TXQCCuuD3zaa0lUxqxR+" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 In-Reply-To: Cancel-Lock: sha1:bNBX0NzYvqAg9m/KUkuSsjg8/HY= Xref: mx02.eternal-september.org comp.lang.vhdl:8561 On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >> fwetie@googlemail.com wrote: >>> hello, >>> please i am looking for someone who can help me to solve my pb. >>> this is my code : >>> >>> Bonjour a tous, >>> je cherche de l'aide pour mon projet sur VHDL: >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>> voici mes codes: >>> >> >> [snip] >> >>> Stimuli : process >>> begin >>> >>> S_FPP_FROM_CORE <= '0'; >>> S_DATA_IN <= '0'; >>> S_FPP_SEC_EN <= '0'; >>> S_FPP_TURN_SEL <= '0'; >>> S_FPP_CORE_SEL <= '0'; >>> S_FPP_REGP_BYP <= '0'; >>> S_FPP_SOURCE_SEL <= '0'; >>> S_FPP_REGN_BYP <= '0'; >>> S_FPP_PRI_EN <= '0'; >>> S_Primary_Port <= '0'; >>> S_Secondary_Port <= '0'; >>> >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_FPP_FROM_CORE <= '-'; >>> S_DATA_IN <= '-'; >>> S_FPP_SEC_EN <= '1'; >>> S_FPP_TURN_SEL <= '-'; >>> S_FPP_CORE_SEL <= '1'; >>> S_FPP_REGP_BYP <= '0'; >>> S_FPP_SOURCE_SEL <= '0'; >>> S_FPP_REGN_BYP <= '0'; >>> S_FPP_PRI_EN <= '0'; >>> >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_Primary_Port <= '0'; >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> S_Secondary_Port <= '1'; >>> wait until S_FPP_CLK_IN <= '1'; >>> >>> >>> end process Stimuli; >>> >>> end archPrimToSecTest; >>> i am looking for sombody to correct my testbench. >>> thanks you for your help. >>> Franck >> >> Well, you didn't give much of a description of why the testbench does >> not function correctly, but my guess is that you wanted to wait for >> edges of the clock and not levels. Also it's unlikely that you >> want to wait for a clock signal to be "less than or equal to 1" >> even if you did want to check for a level. Probably something like >> >> wait until rising_edge (S_FPP_CLK_IN); >> >> -- >> Gabor > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > Franck What do you see in your simulation? -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.67.24.39 with SMTP id if7mr5075694pad.24.1444052057354; Mon, 05 Oct 2015 06:34:17 -0700 (PDT) X-Received: by 10.50.4.70 with SMTP id i6mr90236igi.12.1444052057313; Mon, 05 Oct 2015 06:34:17 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no15650267igb.0!news-out.google.com!n2ni21275igy.0!nntp.google.com!kq10no16977223igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:34:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:34:17 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8562 Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > >> fwetie@googlemail.com wrote: > >>> hello, > >>> please i am looking for someone who can help me to solve my pb. > >>> this is my code : > >>> > >>> Bonjour a tous, > >>> je cherche de l'aide pour mon projet sur VHDL: > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > >>> voici mes codes: > >>> > >> > >> [snip] > >> > >>> Stimuli : process > >>> begin > >>> > >>> S_FPP_FROM_CORE <= '0'; > >>> S_DATA_IN <= '0'; > >>> S_FPP_SEC_EN <= '0'; > >>> S_FPP_TURN_SEL <= '0'; > >>> S_FPP_CORE_SEL <= '0'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> S_Primary_Port <= '0'; > >>> S_Secondary_Port <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_FPP_FROM_CORE <= '-'; > >>> S_DATA_IN <= '-'; > >>> S_FPP_SEC_EN <= '1'; > >>> S_FPP_TURN_SEL <= '-'; > >>> S_FPP_CORE_SEL <= '1'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Primary_Port <= '0'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Secondary_Port <= '1'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> > >>> end process Stimuli; > >>> > >>> end archPrimToSecTest; > >>> i am looking for sombody to correct my testbench. > >>> thanks you for your help. > >>> Franck > >> > >> Well, you didn't give much of a description of why the testbench does > >> not function correctly, but my guess is that you wanted to wait for > >> edges of the clock and not levels. Also it's unlikely that you > >> want to wait for a clock signal to be "less than or equal to 1" > >> even if you did want to check for a level. Probably something like > >> > >> wait until rising_edge (S_FPP_CLK_IN); > >> > >> -- > >> Gabor > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > Franck > > What do you see in your simulation? > > -- > > Rick hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. library ieee; use ieee.std_logic_1164.all; entity testPrimToSecCase1 is end testPrimToSecCase1; architecture archPrimToSecTest of testPrimToSecCase1 is component Lane Port ( FPP_CLK_IN : IN std_logic; FPP_FROM_CORE : IN std_logic; -- (j) DATA_IN : IN std_logic; -- (K) FPP_SEC_EN : IN std_logic; -- (b) FPP_TURN_SEL : IN std_logic; -- (c) FPP_CORE_SEL : IN std_logic; -- (d) FPP_REGP_BYP : IN std_logic; -- (e) FPP_SOURCE_SEL : IN std_logic; -- (f) FPP_REGN_BYP : IN std_logic; -- (g) FPP_PRI_EN : IN std_logic; -- (h) Primary_Port : INOUT std_logic; -- (i) Secondary_Port : INOUT std_logic; -- (a) DATA_OUT : OUT std_logic; FPP_TO_CORE : OUT std_logic ); end component; ----------------------- INPUT ------------------ signal S_FPP_CLK_IN : std_logic; signal S_FPP_FROM_CORE : std_logic; -- (j) signal S_DATA_IN : std_logic; -- (K) signal S_FPP_SEC_EN : std_logic; -- (b) signal S_FPP_TURN_SEL : std_logic; -- (c) signal S_FPP_CORE_SEL : std_logic; -- (d) signal S_FPP_REGP_BYP : std_logic; -- (e) signal S_FPP_SOURCE_SEL : std_logic; -- (f) signal S_FPP_REGN_BYP : std_logic; -- (g) signal S_FPP_PRI_EN : std_logic; -- (h) -------------- InOutput ------------------------ signal S_Primary_Port : std_logic; -- (i) signal S_Secondary_Port : std_logic; -- (a) ----------------- OUTPUT ----------------------- signal S_FPP_TO_CORE_INT : std_logic; signal S_DATA_OUT : std_logic; -- (k) --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE begin -- Komponent Instanzierung mit Verdrahtung U : Lane port map ( S_FPP_CLK_IN, S_FPP_FROM_CORE, -- j S_DATA_IN, -- k S_FPP_SEC_EN, -- b S_FPP_TURN_SEL, -- c S_FPP_CORE_SEL, -- d S_FPP_REGP_BYP, -- e S_FPP_SOURCE_SEL, -- f S_FPP_REGN_BYP, -- g S_FPP_PRI_EN, -- h S_Primary_Port, -- i S_Secondary_Port, -- a S_DATA_OUT, S_FPP_TO_CORE_INT ); processClock : process begin S_FPP_CLK_IN <= '0'; wait for 10 ns; S_FPP_CLK_IN <= '1'; wait for 10 ns; end process processClock; Stimuli : process begin S_FPP_FROM_CORE <= '0'; -- j S_DATA_IN <= '0'; -- k S_FPP_SEC_EN <= '0'; -- b S_FPP_TURN_SEL <= '0'; -- c S_FPP_CORE_SEL <= '0'; -- d S_FPP_REGP_BYP <= '0'; -- e S_FPP_SOURCE_SEL <= '0'; -- f S_FPP_REGN_BYP <= '0'; -- g S_FPP_PRI_EN <= '0'; -- h S_Primary_Port <= ''; -- i S_Secondary_Port <= '0'; -- a wait until S_FPP_CLK_IN <= '1'; S_FPP_FROM_CORE <= '-'; -- j S_DATA_IN <= '-'; -- k S_FPP_SEC_EN <= '1'; -- b S_FPP_TURN_SEL <= '-'; -- c S_FPP_CORE_SEL <= '1'; -- d S_FPP_REGP_BYP <= '0'; -- e S_FPP_SOURCE_SEL <= '0'; -- f S_FPP_REGN_BYP <= '0'; -- g S_FPP_PRI_EN <= '0'; -- h --wait until S_FPP_CLK_IN <= '1'; S_Primary_Port <= '0'; wait until S_FPP_CLK_IN <= '0'; S_Primary_Port <= '1'; wait until S_FPP_CLK_IN <= '1'; end process Stimuli; end archPrimToSecTest; From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.182.80.193 with SMTP id t1mr26693257obx.0.1444053243981; Mon, 05 Oct 2015 06:54:03 -0700 (PDT) X-Received: by 10.50.23.38 with SMTP id j6mr114173igf.15.1444053243946; Mon, 05 Oct 2015 06:54:03 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no15657040igb.0!news-out.google.com!n2ni21291igy.0!nntp.google.com!kq10no16985970igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:54:03 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:54:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8563 Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > >> fwetie@googlemail.com wrote: > >>> hello, > >>> please i am looking for someone who can help me to solve my pb. > >>> this is my code : > >>> > >>> Bonjour a tous, > >>> je cherche de l'aide pour mon projet sur VHDL: > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > >>> voici mes codes: > >>> > >> > >> [snip] > >> > >>> Stimuli : process > >>> begin > >>> > >>> S_FPP_FROM_CORE <= '0'; > >>> S_DATA_IN <= '0'; > >>> S_FPP_SEC_EN <= '0'; > >>> S_FPP_TURN_SEL <= '0'; > >>> S_FPP_CORE_SEL <= '0'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> S_Primary_Port <= '0'; > >>> S_Secondary_Port <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_FPP_FROM_CORE <= '-'; > >>> S_DATA_IN <= '-'; > >>> S_FPP_SEC_EN <= '1'; > >>> S_FPP_TURN_SEL <= '-'; > >>> S_FPP_CORE_SEL <= '1'; > >>> S_FPP_REGP_BYP <= '0'; > >>> S_FPP_SOURCE_SEL <= '0'; > >>> S_FPP_REGN_BYP <= '0'; > >>> S_FPP_PRI_EN <= '0'; > >>> > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Primary_Port <= '0'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> S_Secondary_Port <= '1'; > >>> wait until S_FPP_CLK_IN <= '1'; > >>> > >>> > >>> end process Stimuli; > >>> > >>> end archPrimToSecTest; > >>> i am looking for sombody to correct my testbench. > >>> thanks you for your help. > >>> Franck > >> > >> Well, you didn't give much of a description of why the testbench does > >> not function correctly, but my guess is that you wanted to wait for > >> edges of the clock and not levels. Also it's unlikely that you > >> want to wait for a clock signal to be "less than or equal to 1" > >> even if you did want to check for a level. Probably something like > >> > >> wait until rising_edge (S_FPP_CLK_IN); > >> > >> -- > >> Gabor > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > Franck > > What do you see in your simulation? > > -- > > Rick hello Rick how can i sent you the file. I try without success. From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.107.7.87 with SMTP id 84mr27775355ioh.9.1444053347155; Mon, 05 Oct 2015 06:55:47 -0700 (PDT) X-Received: by 10.50.143.4 with SMTP id sa4mr92179igb.15.1444053347118; Mon, 05 Oct 2015 06:55:47 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no15657599igb.0!news-out.google.com!z4ni11912ign.0!nntp.google.com!kq10no15657593igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 5 Oct 2015 06:55:46 -0700 (PDT) In-Reply-To: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=141.99.250.19; posting-account=4woS_QoAAAD_ZaYPvltumnRoUU-fqMkU NNTP-Posting-Host: 141.99.250.19 References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Subject: Re: VHDL From: fwetie@googlemail.com Injection-Date: Mon, 05 Oct 2015 13:55:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 228 Xref: mx02.eternal-september.org comp.lang.vhdl:8564 Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com: > Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: > > On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: > > > Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: > > >> fwetie@googlemail.com wrote: > > >>> hello, > > >>> please i am looking for someone who can help me to solve my pb. > > >>> this is my code : > > >>> > > >>> Bonjour a tous, > > >>> je cherche de l'aide pour mon projet sur VHDL: > > >>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. > > >>> voici mes codes: > > >>> > > >> > > >> [snip] > > >> > > >>> Stimuli : process > > >>> begin > > >>> > > >>> S_FPP_FROM_CORE <= '0'; > > >>> S_DATA_IN <= '0'; > > >>> S_FPP_SEC_EN <= '0'; > > >>> S_FPP_TURN_SEL <= '0'; > > >>> S_FPP_CORE_SEL <= '0'; > > >>> S_FPP_REGP_BYP <= '0'; > > >>> S_FPP_SOURCE_SEL <= '0'; > > >>> S_FPP_REGN_BYP <= '0'; > > >>> S_FPP_PRI_EN <= '0'; > > >>> S_Primary_Port <= '0'; > > >>> S_Secondary_Port <= '0'; > > >>> > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_FPP_FROM_CORE <= '-'; > > >>> S_DATA_IN <= '-'; > > >>> S_FPP_SEC_EN <= '1'; > > >>> S_FPP_TURN_SEL <= '-'; > > >>> S_FPP_CORE_SEL <= '1'; > > >>> S_FPP_REGP_BYP <= '0'; > > >>> S_FPP_SOURCE_SEL <= '0'; > > >>> S_FPP_REGN_BYP <= '0'; > > >>> S_FPP_PRI_EN <= '0'; > > >>> > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_Primary_Port <= '0'; > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> S_Secondary_Port <= '1'; > > >>> wait until S_FPP_CLK_IN <= '1'; > > >>> > > >>> > > >>> end process Stimuli; > > >>> > > >>> end archPrimToSecTest; > > >>> i am looking for sombody to correct my testbench. > > >>> thanks you for your help. > > >>> Franck > > >> > > >> Well, you didn't give much of a description of why the testbench does > > >> not function correctly, but my guess is that you wanted to wait for > > >> edges of the clock and not levels. Also it's unlikely that you > > >> want to wait for a clock signal to be "less than or equal to 1" > > >> even if you did want to check for a level. Probably something like > > >> > > >> wait until rising_edge (S_FPP_CLK_IN); > > >> > > >> -- > > >> Gabor > > > > > > danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response > > > Franck > > > > What do you see in your simulation? > > > > -- > > > > Rick > hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. > > library ieee; > use ieee.std_logic_1164.all; > > entity testPrimToSecCase1 is > end testPrimToSecCase1; > > architecture archPrimToSecTest of testPrimToSecCase1 is > > component Lane > Port ( > FPP_CLK_IN : IN std_logic; > > FPP_FROM_CORE : IN std_logic; -- (j) > > DATA_IN : IN std_logic; -- (K) > > FPP_SEC_EN : IN std_logic; -- (b) > > FPP_TURN_SEL : IN std_logic; -- (c) > > FPP_CORE_SEL : IN std_logic; -- (d) > > FPP_REGP_BYP : IN std_logic; -- (e) > > FPP_SOURCE_SEL : IN std_logic; -- (f) > > FPP_REGN_BYP : IN std_logic; -- (g) > > FPP_PRI_EN : IN std_logic; -- (h) > > Primary_Port : INOUT std_logic; -- (i) > > Secondary_Port : INOUT std_logic; -- (a) > > DATA_OUT : OUT std_logic; > > FPP_TO_CORE : OUT std_logic > ); > end component; > > ----------------------- INPUT ------------------ > signal S_FPP_CLK_IN : std_logic; > > signal S_FPP_FROM_CORE : std_logic; -- (j) > > signal S_DATA_IN : std_logic; -- (K) > > signal S_FPP_SEC_EN : std_logic; -- (b) > > signal S_FPP_TURN_SEL : std_logic; -- (c) > > signal S_FPP_CORE_SEL : std_logic; -- (d) > > signal S_FPP_REGP_BYP : std_logic; -- (e) > > signal S_FPP_SOURCE_SEL : std_logic; -- (f) > > signal S_FPP_REGN_BYP : std_logic; -- (g) > > signal S_FPP_PRI_EN : std_logic; -- (h) > > -------------- InOutput ------------------------ > signal S_Primary_Port : std_logic; -- (i) > > signal S_Secondary_Port : std_logic; -- (a) > > ----------------- OUTPUT ----------------------- > signal S_FPP_TO_CORE_INT : std_logic; > > signal S_DATA_OUT : std_logic; -- (k) > > --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE > > begin > > -- Komponent Instanzierung mit Verdrahtung > > U : Lane > port map ( > S_FPP_CLK_IN, > > S_FPP_FROM_CORE, -- j > S_DATA_IN, -- k > S_FPP_SEC_EN, -- b > S_FPP_TURN_SEL, -- c > S_FPP_CORE_SEL, -- d > S_FPP_REGP_BYP, -- e > S_FPP_SOURCE_SEL, -- f > S_FPP_REGN_BYP, -- g > S_FPP_PRI_EN, -- h > S_Primary_Port, -- i > S_Secondary_Port, -- a > S_DATA_OUT, > S_FPP_TO_CORE_INT > ); > > > processClock : process > begin > > S_FPP_CLK_IN <= '0'; > wait for 10 ns; > S_FPP_CLK_IN <= '1'; > wait for 10 ns; > > end process processClock; > > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; -- j > S_DATA_IN <= '0'; -- k > S_FPP_SEC_EN <= '0'; -- b > S_FPP_TURN_SEL <= '0'; -- c > S_FPP_CORE_SEL <= '0'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > S_Primary_Port <= ''; -- i > S_Secondary_Port <= '0'; -- a > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; -- j > S_DATA_IN <= '-'; -- k > S_FPP_SEC_EN <= '1'; -- b > S_FPP_TURN_SEL <= '-'; -- c > S_FPP_CORE_SEL <= '1'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > > --wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '0'; > > S_Primary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; is there anyway to sent you the file? From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Mon, 05 Oct 2015 10:36:20 -0400 Organization: Alacron, Inc. Lines: 245 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 5 Oct 2015 14:34:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="18979"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18zymqJDoa9BhrMkgkkZoWFiLoMyX1kc0A=" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> Cancel-Lock: sha1:A4q8iIzNZmLZa7NoOrme3V3I2bg= Xref: mx02.eternal-september.org comp.lang.vhdl:8565 fwetie@googlemail.com wrote: > Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: >> On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: >>> Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >>>> fwetie@googlemail.com wrote: >>>>> hello, >>>>> please i am looking for someone who can help me to solve my pb. >>>>> this is my code : >>>>> >>>>> Bonjour a tous, >>>>> je cherche de l'aide pour mon projet sur VHDL: >>>>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>>>> voici mes codes: >>>>> >>>> [snip] >>>> >>>>> Stimuli : process >>>>> begin >>>>> >>>>> S_FPP_FROM_CORE <= '0'; >>>>> S_DATA_IN <= '0'; >>>>> S_FPP_SEC_EN <= '0'; >>>>> S_FPP_TURN_SEL <= '0'; >>>>> S_FPP_CORE_SEL <= '0'; >>>>> S_FPP_REGP_BYP <= '0'; >>>>> S_FPP_SOURCE_SEL <= '0'; >>>>> S_FPP_REGN_BYP <= '0'; >>>>> S_FPP_PRI_EN <= '0'; >>>>> S_Primary_Port <= '0'; >>>>> S_Secondary_Port <= '0'; >>>>> >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_FPP_FROM_CORE <= '-'; >>>>> S_DATA_IN <= '-'; >>>>> S_FPP_SEC_EN <= '1'; >>>>> S_FPP_TURN_SEL <= '-'; >>>>> S_FPP_CORE_SEL <= '1'; >>>>> S_FPP_REGP_BYP <= '0'; >>>>> S_FPP_SOURCE_SEL <= '0'; >>>>> S_FPP_REGN_BYP <= '0'; >>>>> S_FPP_PRI_EN <= '0'; >>>>> >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_Primary_Port <= '0'; >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> S_Secondary_Port <= '1'; >>>>> wait until S_FPP_CLK_IN <= '1'; >>>>> >>>>> >>>>> end process Stimuli; >>>>> >>>>> end archPrimToSecTest; >>>>> i am looking for sombody to correct my testbench. >>>>> thanks you for your help. >>>>> Franck >>>> Well, you didn't give much of a description of why the testbench does >>>> not function correctly, but my guess is that you wanted to wait for >>>> edges of the clock and not levels. Also it's unlikely that you >>>> want to wait for a clock signal to be "less than or equal to 1" >>>> even if you did want to check for a level. Probably something like >>>> >>>> wait until rising_edge (S_FPP_CLK_IN); >>>> >>>> -- >>>> Gabor >>> danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response >>> Franck >> What do you see in your simulation? >> >> -- >> >> Rick > hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. > > library ieee; > use ieee.std_logic_1164.all; > > entity testPrimToSecCase1 is > end testPrimToSecCase1; > > architecture archPrimToSecTest of testPrimToSecCase1 is > > component Lane > Port ( > FPP_CLK_IN : IN std_logic; > > FPP_FROM_CORE : IN std_logic; -- (j) > > DATA_IN : IN std_logic; -- (K) > > FPP_SEC_EN : IN std_logic; -- (b) > > FPP_TURN_SEL : IN std_logic; -- (c) > > FPP_CORE_SEL : IN std_logic; -- (d) > > FPP_REGP_BYP : IN std_logic; -- (e) > > FPP_SOURCE_SEL : IN std_logic; -- (f) > > FPP_REGN_BYP : IN std_logic; -- (g) > > FPP_PRI_EN : IN std_logic; -- (h) > > Primary_Port : INOUT std_logic; -- (i) > > Secondary_Port : INOUT std_logic; -- (a) > > DATA_OUT : OUT std_logic; > > FPP_TO_CORE : OUT std_logic > ); > end component; > > ----------------------- INPUT ------------------ > signal S_FPP_CLK_IN : std_logic; > > signal S_FPP_FROM_CORE : std_logic; -- (j) > > signal S_DATA_IN : std_logic; -- (K) > > signal S_FPP_SEC_EN : std_logic; -- (b) > > signal S_FPP_TURN_SEL : std_logic; -- (c) > > signal S_FPP_CORE_SEL : std_logic; -- (d) > > signal S_FPP_REGP_BYP : std_logic; -- (e) > > signal S_FPP_SOURCE_SEL : std_logic; -- (f) > > signal S_FPP_REGN_BYP : std_logic; -- (g) > > signal S_FPP_PRI_EN : std_logic; -- (h) > > -------------- InOutput ------------------------ > signal S_Primary_Port : std_logic; -- (i) > > signal S_Secondary_Port : std_logic; -- (a) > > ----------------- OUTPUT ----------------------- > signal S_FPP_TO_CORE_INT : std_logic; > > signal S_DATA_OUT : std_logic; -- (k) > > --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE > > begin > > -- Komponent Instanzierung mit Verdrahtung > > U : Lane > port map ( > S_FPP_CLK_IN, > > S_FPP_FROM_CORE, -- j > S_DATA_IN, -- k > S_FPP_SEC_EN, -- b > S_FPP_TURN_SEL, -- c > S_FPP_CORE_SEL, -- d > S_FPP_REGP_BYP, -- e > S_FPP_SOURCE_SEL, -- f > S_FPP_REGN_BYP, -- g > S_FPP_PRI_EN, -- h > S_Primary_Port, -- i > S_Secondary_Port, -- a > S_DATA_OUT, > S_FPP_TO_CORE_INT > ); > > > processClock : process > begin > > S_FPP_CLK_IN <= '0'; > wait for 10 ns; > S_FPP_CLK_IN <= '1'; > wait for 10 ns; > > end process processClock; > > Stimuli : process > begin > > S_FPP_FROM_CORE <= '0'; -- j > S_DATA_IN <= '0'; -- k > S_FPP_SEC_EN <= '0'; -- b > S_FPP_TURN_SEL <= '0'; -- c > S_FPP_CORE_SEL <= '0'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > S_Primary_Port <= ''; -- i > S_Secondary_Port <= '0'; -- a > > wait until S_FPP_CLK_IN <= '1'; > > S_FPP_FROM_CORE <= '-'; -- j > S_DATA_IN <= '-'; -- k > S_FPP_SEC_EN <= '1'; -- b > S_FPP_TURN_SEL <= '-'; -- c > S_FPP_CORE_SEL <= '1'; -- d > S_FPP_REGP_BYP <= '0'; -- e > S_FPP_SOURCE_SEL <= '0'; -- f > S_FPP_REGN_BYP <= '0'; -- g > S_FPP_PRI_EN <= '0'; -- h > > --wait until S_FPP_CLK_IN <= '1'; > > S_Primary_Port <= '0'; > wait until S_FPP_CLK_IN <= '0'; > > S_Primary_Port <= '1'; > wait until S_FPP_CLK_IN <= '1'; > > > end process Stimuli; > > end archPrimToSecTest; You still have a problematic wait in your "Stimuli" process: wait until S_FPP_CLK_IN <= '1'; This literaly means "wait until S_FPP_CLK_IN is less than or equal to 1" and since the clock will only have values 0 or 1, it will always be true. Therefore the wait does not actually delay the next set of assignments until the clock is high, rather it happens immediately at time zero. Furthermore this sort of wait is problematic when you are trying to stimulate a clocked process and want to ensure that the stimulus happens a "delta" delay after the rising clock edge. You should really wait for an event. either: wait until S_FPP_CLK_IN'event and S_FPP_CLK_IN = '1'; or: wait until rising_edge (S_FPP_CLK_IN); -- Gabor From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.50.43.233 with SMTP id z9mr3074591igl.9.1444250670783; Wed, 07 Oct 2015 13:44:30 -0700 (PDT) X-Received: by 10.50.20.73 with SMTP id l9mr82144ige.2.1444250670719; Wed, 07 Oct 2015 13:44:30 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!kq10no18145261igb.0!news-out.google.com!n2ni23521igy.0!nntp.google.com!kq10no16459166igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 7 Oct 2015 13:44:29 -0700 (PDT) In-Reply-To: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=179.215.205.247; posting-account=HmYrCQoAAACjE_F53xA8_mML1hYdaSqp NNTP-Posting-Host: 179.215.205.247 References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Exponential code in VHDL From: maurolarrat@gmail.com Injection-Date: Wed, 07 Oct 2015 20:44:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8566 Em quarta-feira, 27 de julho de 2011 06:19:26 UTC-3, Zaid Al-Hilli escreveu: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Use Elliott function, also known as fast sigmoid function. It will solve your problem. From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Date: Wed, 7 Oct 2015 17:01:30 -0400 Organization: A noiseless patient Spider Lines: 239 Message-ID: References: <3e241485-a5bc-4f42-bdfd-2b97555bf41a@googlegroups.com> <15c93df1-1828-4232-b7da-435e34cfc6a4@googlegroups.com> <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 7 Oct 2015 20:59:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="7b80060806273f26e05ba36fc8912472"; logging-data="25273"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+LHfHJzCzcdiy7NZz9fql7" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <1c41abda-8fca-4d69-9af8-a3376b3c3ceb@googlegroups.com> Cancel-Lock: sha1:1H2Bd1fT1uel2Y7Mxc/fEjdY/4w= Xref: mx02.eternal-september.org comp.lang.vhdl:8567 On 10/5/2015 9:55 AM, fwetie@googlemail.com wrote: > Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com: >> Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman: >>> On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote: >>>> Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz: >>>>> fwetie@googlemail.com wrote: >>>>>> hello, >>>>>> please i am looking for someone who can help me to solve my pb. >>>>>> this is my code : >>>>>> >>>>>> Bonjour a tous, >>>>>> je cherche de l'aide pour mon projet sur VHDL: >>>>>> mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait. >>>>>> voici mes codes: >>>>>> >>>>> >>>>> [snip] >>>>> >>>>>> Stimuli : process >>>>>> begin >>>>>> >>>>>> S_FPP_FROM_CORE <= '0'; >>>>>> S_DATA_IN <= '0'; >>>>>> S_FPP_SEC_EN <= '0'; >>>>>> S_FPP_TURN_SEL <= '0'; >>>>>> S_FPP_CORE_SEL <= '0'; >>>>>> S_FPP_REGP_BYP <= '0'; >>>>>> S_FPP_SOURCE_SEL <= '0'; >>>>>> S_FPP_REGN_BYP <= '0'; >>>>>> S_FPP_PRI_EN <= '0'; >>>>>> S_Primary_Port <= '0'; >>>>>> S_Secondary_Port <= '0'; >>>>>> >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_FPP_FROM_CORE <= '-'; >>>>>> S_DATA_IN <= '-'; >>>>>> S_FPP_SEC_EN <= '1'; >>>>>> S_FPP_TURN_SEL <= '-'; >>>>>> S_FPP_CORE_SEL <= '1'; >>>>>> S_FPP_REGP_BYP <= '0'; >>>>>> S_FPP_SOURCE_SEL <= '0'; >>>>>> S_FPP_REGN_BYP <= '0'; >>>>>> S_FPP_PRI_EN <= '0'; >>>>>> >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_Primary_Port <= '0'; >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> S_Secondary_Port <= '1'; >>>>>> wait until S_FPP_CLK_IN <= '1'; >>>>>> >>>>>> >>>>>> end process Stimuli; >>>>>> >>>>>> end archPrimToSecTest; >>>>>> i am looking for sombody to correct my testbench. >>>>>> thanks you for your help. >>>>>> Franck >>>>> >>>>> Well, you didn't give much of a description of why the testbench does >>>>> not function correctly, but my guess is that you wanted to wait for >>>>> edges of the clock and not levels. Also it's unlikely that you >>>>> want to wait for a clock signal to be "less than or equal to 1" >>>>> even if you did want to check for a level. Probably something like >>>>> >>>>> wait until rising_edge (S_FPP_CLK_IN); >>>>> >>>>> -- >>>>> Gabor >>>> >>>> danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response >>>> Franck >>> >>> What do you see in your simulation? >>> >>> -- >>> >>> Rick >> hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving. >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity testPrimToSecCase1 is >> end testPrimToSecCase1; >> >> architecture archPrimToSecTest of testPrimToSecCase1 is >> >> component Lane >> Port ( >> FPP_CLK_IN : IN std_logic; >> >> FPP_FROM_CORE : IN std_logic; -- (j) >> >> DATA_IN : IN std_logic; -- (K) >> >> FPP_SEC_EN : IN std_logic; -- (b) >> >> FPP_TURN_SEL : IN std_logic; -- (c) >> >> FPP_CORE_SEL : IN std_logic; -- (d) >> >> FPP_REGP_BYP : IN std_logic; -- (e) >> >> FPP_SOURCE_SEL : IN std_logic; -- (f) >> >> FPP_REGN_BYP : IN std_logic; -- (g) >> >> FPP_PRI_EN : IN std_logic; -- (h) >> >> Primary_Port : INOUT std_logic; -- (i) >> >> Secondary_Port : INOUT std_logic; -- (a) >> >> DATA_OUT : OUT std_logic; >> >> FPP_TO_CORE : OUT std_logic >> ); >> end component; >> >> ----------------------- INPUT ------------------ >> signal S_FPP_CLK_IN : std_logic; >> >> signal S_FPP_FROM_CORE : std_logic; -- (j) >> >> signal S_DATA_IN : std_logic; -- (K) >> >> signal S_FPP_SEC_EN : std_logic; -- (b) >> >> signal S_FPP_TURN_SEL : std_logic; -- (c) >> >> signal S_FPP_CORE_SEL : std_logic; -- (d) >> >> signal S_FPP_REGP_BYP : std_logic; -- (e) >> >> signal S_FPP_SOURCE_SEL : std_logic; -- (f) >> >> signal S_FPP_REGN_BYP : std_logic; -- (g) >> >> signal S_FPP_PRI_EN : std_logic; -- (h) >> >> -------------- InOutput ------------------------ >> signal S_Primary_Port : std_logic; -- (i) >> >> signal S_Secondary_Port : std_logic; -- (a) >> >> ----------------- OUTPUT ----------------------- >> signal S_FPP_TO_CORE_INT : std_logic; >> >> signal S_DATA_OUT : std_logic; -- (k) >> >> --FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE >> >> begin >> >> -- Komponent Instanzierung mit Verdrahtung >> >> U : Lane >> port map ( >> S_FPP_CLK_IN, >> >> S_FPP_FROM_CORE, -- j >> S_DATA_IN, -- k >> S_FPP_SEC_EN, -- b >> S_FPP_TURN_SEL, -- c >> S_FPP_CORE_SEL, -- d >> S_FPP_REGP_BYP, -- e >> S_FPP_SOURCE_SEL, -- f >> S_FPP_REGN_BYP, -- g >> S_FPP_PRI_EN, -- h >> S_Primary_Port, -- i >> S_Secondary_Port, -- a >> S_DATA_OUT, >> S_FPP_TO_CORE_INT >> ); >> >> >> processClock : process >> begin >> >> S_FPP_CLK_IN <= '0'; >> wait for 10 ns; >> S_FPP_CLK_IN <= '1'; >> wait for 10 ns; >> >> end process processClock; >> >> Stimuli : process >> begin >> >> S_FPP_FROM_CORE <= '0'; -- j >> S_DATA_IN <= '0'; -- k >> S_FPP_SEC_EN <= '0'; -- b >> S_FPP_TURN_SEL <= '0'; -- c >> S_FPP_CORE_SEL <= '0'; -- d >> S_FPP_REGP_BYP <= '0'; -- e >> S_FPP_SOURCE_SEL <= '0'; -- f >> S_FPP_REGN_BYP <= '0'; -- g >> S_FPP_PRI_EN <= '0'; -- h >> S_Primary_Port <= ''; -- i >> S_Secondary_Port <= '0'; -- a >> >> wait until S_FPP_CLK_IN <= '1'; >> >> S_FPP_FROM_CORE <= '-'; -- j >> S_DATA_IN <= '-'; -- k >> S_FPP_SEC_EN <= '1'; -- b >> S_FPP_TURN_SEL <= '-'; -- c >> S_FPP_CORE_SEL <= '1'; -- d >> S_FPP_REGP_BYP <= '0'; -- e >> S_FPP_SOURCE_SEL <= '0'; -- f >> S_FPP_REGN_BYP <= '0'; -- g >> S_FPP_PRI_EN <= '0'; -- h >> >> --wait until S_FPP_CLK_IN <= '1'; >> >> S_Primary_Port <= '0'; >> wait until S_FPP_CLK_IN <= '0'; >> >> S_Primary_Port <= '1'; >> wait until S_FPP_CLK_IN <= '1'; >> >> >> end process Stimuli; >> >> end archPrimToSecTest; > > is there anyway to sent you the file? I don't want you to send me the file so I can debug your code. I want you to look at the simulation results and understand what you see. I will help you understand if you tell me what you don't understand or ask questions. -- Rick From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.66.249.100 with SMTP id yt4mr8188038pac.42.1444342935034; Thu, 08 Oct 2015 15:22:15 -0700 (PDT) X-Received: by 10.50.77.70 with SMTP id q6mr94814igw.4.1444342934991; Thu, 08 Oct 2015 15:22:14 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.glorb.com!kq10no18655451igb.0!news-out.google.com!z4ni15254ign.0!nntp.google.com!kq10no16811441igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 8 Oct 2015 15:22:14 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5abf3445-1212-4ec5-991c-645d31e4507b@googlegroups.com> Subject: Re: Exponential code in VHDL From: michael6866 Injection-Date: Thu, 08 Oct 2015 22:22:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8568 On Wednesday, October 7, 2015 at 4:44:34 PM UTC-4, mauro...@gmail.com wrote: > Em quarta-feira, 27 de julho de 2011 06:19:26 UTC-3, Zaid Al-Hilli escreveu: > > Hi all, > > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > > 8.5))); > > > > Would you please help me in that? > > > > Many thanks in advance... > > > > Zaid > > Use Elliott function, also known as fast sigmoid function. It will solve your problem. Why do you want to bring an ancient thread up... From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.140.150.206 with SMTP id 197mr25388065qhw.0.1444675760038; Mon, 12 Oct 2015 11:49:20 -0700 (PDT) X-Received: by 10.50.78.225 with SMTP id e1mr156835igx.0.1444675759963; Mon, 12 Oct 2015 11:49:19 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!newspeer1.nac.net!border2.nntp.dca1.giganews.com!nntp.giganews.com!z77no9202216qge.1!news-out.google.com!z4ni19067ign.0!nntp.google.com!kq10no20421473igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 12 Oct 2015 11:49:19 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=75.78.166.8; posting-account=1MLwSAoAAACZMvKd3RIo1qYTMmqjCBWr NNTP-Posting-Host: 75.78.166.8 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> Subject: Xilinx XC4VLX40-10FFG1148C - Available New From: mvarman@gmail.com Injection-Date: Mon, 12 Oct 2015 18:49:19 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 10 Xref: mx02.eternal-september.org comp.lang.vhdl:8569 I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND Please let me know whether anyone will by interested to buy this from me. Thanks Mahendra Varman From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.129.154.137 with SMTP id r131mr30680645ywg.0.1444769791217; Tue, 13 Oct 2015 13:56:31 -0700 (PDT) X-Received: by 10.50.164.201 with SMTP id ys9mr23724igb.13.1444769791140; Tue, 13 Oct 2015 13:56:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!z77no9437512qge.1!news-out.google.com!n2ni29327igy.0!nntp.google.com!kq10no20931082igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 13 Oct 2015 13:56:30 -0700 (PDT) In-Reply-To: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=117.198.93.234; posting-account=siWI1goAAADCu904SmsHiBYIWw1g2Ocr NNTP-Posting-Host: 117.198.93.234 References: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> Subject: Re: Xilinx XC4VLX40-10FFG1148C - Available New From: iamalien Injection-Date: Tue, 13 Oct 2015 20:56:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1605 X-Received-Body-CRC: 2210225640 Xref: mx02.eternal-september.org comp.lang.vhdl:8570 On Tuesday, October 13, 2015 at 12:19:25 AM UTC+5:30, mva...@gmail.com wrote: > I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. > The ICs are in original sealed envelope (not opened). > > Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND > > Please let me know whether anyone will by interested to buy this from > me. > > Thanks > > Mahendra Varman only ICs or is there a development board too? From newsfish@newsfish Tue Dec 29 16:43:59 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 16 Oct 2015 04:36:49 -0500 From: aadi Subject: creating program Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: fc54be3c-b935-4e6a-a6c9-a610175bed0c Message-ID: Date: Fri, 16 Oct 2015 04:36:49 -0500 Lines: 5 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-fcvZcbQlrEg+Vd3HjgJ4w1TIiMsmdr9NzmTytQJV0XPTPA7oYZIAl3TnQS96Mtfh+OS7Xe4827Ss7Ok!cuTHLAWvVjb0cAOSXGCZQgCVhNb89l4gY52yClU/3jO84PqtxR3/+SsXQohL0uBnnnZE15R4TVrz!Z8Q= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1121 Xref: mx02.eternal-september.org comp.lang.vhdl:8571 i have learned every aspect of VHDL but i still can't exersise it to make complex program. i need a code for data encryption standard and also for key generation. but i can't get a single way to do so plzz help me From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.182.241.10 with SMTP id we10mr12719883obc.24.1444991828353; Fri, 16 Oct 2015 03:37:08 -0700 (PDT) X-Received: by 10.50.43.195 with SMTP id y3mr82612igl.1.1444991828330; Fri, 16 Oct 2015 03:37:08 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22048410igb.0!news-out.google.com!z4ni22683ign.0!nntp.google.com!kq10no19028746igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 03:37:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:d9fa:c1c2:945e:ca59; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:d9fa:c1c2:945e:ca59 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: KJ Injection-Date: Fri, 16 Oct 2015 10:37:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8572 On Friday, October 16, 2015 at 5:36:53 AM UTC-4, aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me Stating what you say you 'need' and not showing what you've 'done' doesn't typically motivate anybody to help. Some suggestions: - Post some code for people to review and comment - Pay somebody to write the code for you - English may not be your first language, but 'plzz' is not even close to 'please'...it's closer to 'pizza'. Showing some bit of professionalism is often useful Kevin From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.182.126.228 with SMTP id nb4mr12072676obb.19.1444995261463; Fri, 16 Oct 2015 04:34:21 -0700 (PDT) X-Received: by 10.50.115.70 with SMTP id jm6mr87130igb.5.1444995261440; Fri, 16 Oct 2015 04:34:21 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19046399igb.0!news-out.google.com!z4ni22710ign.0!nntp.google.com!kq10no22071114igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 04:34:21 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Thomas Stanka Injection-Date: Fri, 16 Oct 2015 11:34:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8573 Am Freitag, 16. Oktober 2015 11:36:53 UTC+2 schrieb aadi: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me In general, it is agreed that writing a "Program" requires you to have Software and Compiler that generates a Program out of your Software. VHDL is mainly a hardware description language, I know no Compiler allowing you to generate a executeable out of VHDL, instead you will find several Simulators, that allow you to simulate the Code you wrote. If you have learned every aspect of VHDL this is nothing new for you, so your problem should be with the data encryption, not with HDL descripton itself, so you might ask in a group dealing with encyption standard. A VHDL code for DES can easily take some man-month work force. If you need easy way register by open cores and download the DES core from there. In this group you should provide specific questions in order to receive specific answers. regards Thomas From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.66.160.135 with SMTP id xk7mr14311386pab.28.1445022331638; Fri, 16 Oct 2015 12:05:31 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr161996igc.5.1445022331591; Fri, 16 Oct 2015 12:05:31 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22234302igb.0!news-out.google.com!n2ni32143igy.0!nntp.google.com!kq10no22234291igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 12:05:30 -0700 (PDT) In-Reply-To: <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=75.78.166.8; posting-account=1MLwSAoAAACZMvKd3RIo1qYTMmqjCBWr NNTP-Posting-Host: 75.78.166.8 References: <8c3d4880-38e6-41e4-9250-f8cfc78465ba@googlegroups.com> <86a7d6d1-77a9-494d-9148-7859493680ea@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Xilinx XC4VLX40-10FFG1148C - Available New From: mvarman@gmail.com Injection-Date: Fri, 16 Oct 2015 19:05:31 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8574 On Tuesday, October 13, 2015 at 3:56:37 PM UTC-5, iamalien wrote: > On Tuesday, October 13, 2015 at 12:19:25 AM UTC+5:30, mva...@gmail.com wrote: > > I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. > > The ICs are in original sealed envelope (not opened). > > > > Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND > > > > Please let me know whether anyone will by interested to buy this from > > me. > > > > Thanks > > > > Mahendra Varman > > only ICs or is there a development board too? Only ICs From newsfish@newsfish Tue Dec 29 16:43:59 2015 X-Received: by 10.68.165.5 with SMTP id yu5mr14211419pbb.1.1445023906236; Fri, 16 Oct 2015 12:31:46 -0700 (PDT) X-Received: by 10.50.131.164 with SMTP id on4mr166224igb.8.1445023906193; Fri, 16 Oct 2015 12:31:46 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no22244404igb.0!news-out.google.com!z4ni23052ign.0!nntp.google.com!kq10no19162949igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 12:31:45 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Subject: Strange 'X' values. From: Ilya Kalistru Injection-Date: Fri, 16 Oct 2015 19:31:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8575 Good day. I came across a strange behavior in my project and can't understand it. May= be you could explain it to me. I've reduced it to the point where it still persists. I've tried to ask on the xilinx forum but it looks like that that forum more engaged to help me avoid that proble= m then explain what is going on here... Here is the code entity test is Port ( Clock : in std_logic; Dev_Linked : in std_logic_vector(0 downto 0); R_CHCS : out std_logic_vector(1 downto 0):=3D"01" ); end entity test; architecture Behavioral of test is begin R_CHCS_proc : process (Clock) is begin if rising_edge(Clock) then for i in 0 to 0 loop R_CHCS(i * 2) <=3D '0'; end loop; end if; end process R_CHCS_proc; R_CHCS(1) <=3D Dev_Linked(0) when rising_edge(Clock); end Behavioral; On the first clock cycle R_CHCS becomes "X0". And I don't know why. On Xili= nx forum say that "Questa also gives the same output" and it's not a bug of= the simulator and it's because each process makes it's own driver for CHC= S and it gives 'X' value. But it doesn't make sense for me because if I rem= ove unnecessary loop in R_CHCS_proc this problem disappears, and it is noth= ing to do with processes. Maybe someone could explain this to me? From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.13.202.13 with SMTP id m13mr5780994ywd.57.1445032856084; Fri, 16 Oct 2015 15:00:56 -0700 (PDT) X-Received: by 10.50.131.164 with SMTP id on4mr183533igb.8.1445032856055; Fri, 16 Oct 2015 15:00:56 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!5no1600162qgg.0!news-out.google.com!z4ni23141ign.0!nntp.google.com!kq10no22295737igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 16 Oct 2015 15:00:55 -0700 (PDT) In-Reply-To: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.53.76.131; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 50.53.76.131 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> Subject: Re: Strange 'X' values. From: Jim Lewis Injection-Date: Fri, 16 Oct 2015 22:00:56 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8576 >From www.eda.org/comp.lang.vhdl/FAQ1.html: 4.2.13 Signal Drivers ... Further, VHDL needs to be able to statically (that is, during static elabo= ration) determine all drivers of a signal, in order to create a static netw= ork topology. A driver is created for the longest static prefix of each tar= get signal. During elaboration the compiler analyzes the target of each sig= nal assignment statement to determine the smallest portion of the signal th= at can be statically determined as being driven by the concurrent statement= . For example, the following model is erroneous, as both the process "p" an= d the concurrent signal assignment both drive "sig(3)", an unresolved signa= l. architecture behave of test is signal sig : bit_vector(0 TO 7); constant c : integer :=3D 3; begin p: process (sig) begin for i in 1 to 1 loop sig(i) <=3D '1'; -- signal assignment statement end loop; end process; sig(c) <=3D '1'; -- concurrent signal assignment driving -- "sig(3)" end behave;=20 In this example, the longest static prefix of the target of the assignment = statement "sig(i) <=3D '1'" is the entire signal "sig", since "sig" is a st= atic signal name and "i" is a loop constant and hence not static. Consequen= tly, "p" has a driver for the entire signal "sig", although actuality only = "sig(1)" will be driven by the process. Further, the longest static prefix = of the concurrent signal assignment is "sig(3)", since "c" is a statically = elaborated constant equal to 3. Hence, an error message should be generated= to the effect that several processes are driving "sig(3)". From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Fri, 16 Oct 2015 20:19:57 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 00:17:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="31484"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Jy7fRLJ/n6eNXqECLZI1G" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Cancel-Lock: sha1:wdz8U4SjYyfGbjqk/DqngPxgdCQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8577 On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > Good day. > I came across a strange behavior in my project and can't understand it. Maybe you could explain it to me. > I've reduced it to the point where it still persists. > I've tried to ask on the xilinx forum > but it looks like that that forum more engaged to help me avoid that problem then explain what is going on here... > Here is the code > > entity test is > Port ( > Clock : in std_logic; > Dev_Linked : in std_logic_vector(0 downto 0); > R_CHCS : out std_logic_vector(1 downto 0):="01" > ); > end entity test; > > architecture Behavioral of test is > begin > > R_CHCS_proc : process (Clock) is > begin > if rising_edge(Clock) then > for i in 0 to 0 loop > R_CHCS(i * 2) <= '0'; > end loop; > end if; > end process R_CHCS_proc; > > R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > end Behavioral; > > On the first clock cycle R_CHCS becomes "X0". And I don't know why. On Xilinx forum say that "Questa also gives the same output" and it's not a bug of the simulator and it's because each process makes it's own driver for CHCS and it gives 'X' value. But it doesn't make sense for me because if I remove unnecessary loop in R_CHCS_proc this problem disappears, and it is nothing to do with processes. > > Maybe someone could explain this to me? I think Jim gave you an explanation even if it is a bit hard to understand. VHDL has a lot of things like that. The basic rule is "don't do that". I can't say I see any reason why you would want to do that. Why not just include the assignment to bit 1 of R_CHCS in the same clocked process as the other assignment to R_CHCS? Rick -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sat, 17 Oct 2015 00:27:27 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 20 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8578 aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it > to make complex program. I started VHDL, and though I have never written a 'program' in it, I have designed some fairly complicated logic that actually works. I won't claim to undestand even half of VHDL, as they are adding to it faster than I can learn, and faster than the systems I use it with can keep up. (I had some years of verilog before, but only learned a small fraction of VHDL before I knew enough to start writing it.) > i need a code for data encryption standard and also for key generation. > but i can't get a single way to do so Do remember that VHDL is not a software programming language. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Sat, 17 Oct 2015 00:35:57 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 45 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8579 rickman wrote: > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >> I came across a strange behavior in my project and can't understand it. >> Maybe you could explain it to me. (snip) >> R_CHCS_proc : process (Clock) is >> begin >> if rising_edge(Clock) then >> for i in 0 to 0 loop >> R_CHCS(i * 2) <= '0'; >> end loop; >> end if; >> end process R_CHCS_proc; >> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); (snip) >> On the first clock cycle R_CHCS becomes "X0". (snip) > I think Jim gave you an explanation even if it is a bit hard to > understand. VHDL has a lot of things like that. The basic rule is > "don't do that". I can't say I see any reason why you would want to do > that. Why not just include the assignment to bit 1 of R_CHCS in the > same clocked process as the other assignment to R_CHCS? Yes. For each signal, use either the process form or the non-process (verilog calls it continuous assignment) form, but don't mix them. In verilog, you have to declare reg or wire, so you have to decide early which way you want to go. VHDL doesn't have that, but you still have to get it right. It might work if you put the second one in its own process, but it has to be in one. Also, I didn't know that you could use rising_edge(clock) outside of process, but then again, I never even thought to try it. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Fri, 16 Oct 2015 21:17:36 -0400 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 01:15:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="7641"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+P1LaHvFBz8REl566TUSno" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:TT6hBMbNWB4dRgXqzcjMpUOJshw= Xref: mx02.eternal-september.org comp.lang.vhdl:8580 On 10/16/2015 8:35 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >>> I came across a strange behavior in my project and can't understand it. >>> Maybe you could explain it to me. > > (snip) > >>> R_CHCS_proc : process (Clock) is >>> begin >>> if rising_edge(Clock) then >>> for i in 0 to 0 loop >>> R_CHCS(i * 2) <= '0'; >>> end loop; >>> end if; >>> end process R_CHCS_proc; > >>> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > (snip) > >>> On the first clock cycle R_CHCS becomes "X0". > > (snip) > >> I think Jim gave you an explanation even if it is a bit hard to >> understand. VHDL has a lot of things like that. The basic rule is >> "don't do that". I can't say I see any reason why you would want to do >> that. Why not just include the assignment to bit 1 of R_CHCS in the >> same clocked process as the other assignment to R_CHCS? > > Yes. For each signal, use either the process form or the non-process > (verilog calls it continuous assignment) form, but don't mix them. > > In verilog, you have to declare reg or wire, so you have to decide early > which way you want to go. VHDL doesn't have that, but you still have to > get it right. > > It might work if you put the second one in its own process, but it has > to be in one. > > Also, I didn't know that you could use rising_edge(clock) outside > of process, but then again, I never even thought to try it. I've seen this discussed, making a clocked process from a concurrent statement. But I've never tried it myself. I want to say I've read that it will work, but perhaps not in all tools. There is a synthesis VHDL spec if I am not mistaken and I bet this isn't in it. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Why VHDL? Date: Fri, 16 Oct 2015 21:24:16 -0400 Organization: A noiseless patient Spider Lines: 21 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 01:22:14 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="8713"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+oJpup/uyTGPpjaghoEvgH" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:mC2PGhaEyQQqV+Y9SY75LypuTBc= Xref: mx02.eternal-september.org comp.lang.vhdl:8581 comp.lang.verilog:4077 I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled by Glen's comment in the VHDL group that he learned Verilog first before using VHDL. Am I correct in assuming you used VHDL because a customer required it? I learned VHDL, although not well, then went to work for a comms company who used Verilog. I never went to school for Verilog and never really bought a book. So I don't feel comfortable using it even though I have coded in it. On the other hand, after many years of VHDL, I won't say I've ever gotten "comfortable" with it. I've just learned to live with it. Part of the reason I haven't switched to Verilog is that I've never found a good book for it. In fact when I have asked in the Verilog group I'm told there *isn't* one. Buy "good" I mean one that covers all the pitfalls well. At least with VHDL it tells you you've screwed up. I'm curious who here has learned both and why? Which do you prefer and why? -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 07:21:33 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 58 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8582 comp.lang.verilog:4078 In comp.lang.vhdl rickman wrote: > I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled > by Glen's comment in the VHDL group that he learned Verilog first before > using VHDL. Am I correct in assuming you used VHDL because a customer > required it? That is about right. > I learned VHDL, although not well, then went to work for a comms company > who used Verilog. I never went to school for Verilog and never really > bought a book. So I don't feel comfortable using it even though I have > coded in it. I started about 1993. I was told that C programmers usually like verilog, others I worked with were using it, so I did to. I bought both Thomas and Moorby's book, and the Sternhiem, Singh, Madhavan, and Trivedi book. There might not have been many books back then. Those two, and some Xilinx software to run designs through, and I started writing down logic designs pretty soon. I also did some simulations with Veriwell. Not so many years ago, I was working with an existing design that was done using a mix of schematic capture, VHDL, and AHDL (that is, Altera), and wrote mine in verilog. I had to be able to read the VHDL, but didn't need to write it. > On the other hand, after many years of VHDL, I won't say > I've ever gotten "comfortable" with it. I've just learned to live with > it. Part of the reason I haven't switched to Verilog is that I've never > found a good book for it. In fact when I have asked in the Verilog > group I'm told there *isn't* one. Buy "good" I mean one that covers all > the pitfalls well. At least with VHDL it tells you you've screwed up. Many useful verilog features are new to VHDL, some too new for the version of tools that I use. Even more, they are different for different FPGA chips with the same version of tools. (Specifically, Spartan 3 vs. Spartan 6.) Strange. > I'm curious who here has learned both and why? Which do you prefer and > why? Most verilog operators are similar to C operators, so that helps some. A few times, not so many, I have used & in VHDL when I meant AND. I still prefer verilog, but I figured out how to write most of the things I need from verilog into VHDL. Verilog style concatenations are still too new to VHDL. The result is a fair number of signals that are only needed to combine or separate signals to/from a vector. VHDL is a little wordier than I like, but it isn't so hard to live with. I will like it better when VHDL 2008 is supported, where I rarely complained about the features in verilog 95. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.50.62.49 with SMTP id v17mr8149530igr.1.1445075007345; Sat, 17 Oct 2015 02:43:27 -0700 (PDT) X-Received: by 10.50.124.69 with SMTP id mg5mr94183igb.10.1445075007289; Sat, 17 Oct 2015 02:43:27 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!feed.news.qwest.net!mpls-nntp-03.inet.qwest.net!216.166.98.85.MISMATCH!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!kq10no22525601igb.0!news-out.google.com!z4ni23657ign.0!nntp.google.com!kq10no19354314igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 02:43:26 -0700 (PDT) In-Reply-To: <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <46d2e97c-2e25-4d12-b4ff-d8a98cb91457@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d43de1f-dcea-4fa8-88be-cf583d30c3cf@googlegroups.com> Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 09:43:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 0 Xref: mx02.eternal-september.org comp.lang.vhdl:8583 Jim Lewis, thank you for your reply and a link to a good resource. From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.107.163.80 with SMTP id m77mr17831128ioe.0.1445075493415; Sat, 17 Oct 2015 02:51:33 -0700 (PDT) X-Received: by 10.50.164.167 with SMTP id yr7mr215690igb.2.1445075493399; Sat, 17 Oct 2015 02:51:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19356416igb.0!news-out.google.com!n2ni32733igy.0!nntp.google.com!kq10no22528783igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 02:51:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 09:51:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8584 On Saturday, October 17, 2015 at 3:20:03 AM UTC+3, rickman wrote: > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > > Good day. > > I came across a strange behavior in my project and can't understand it.= Maybe you could explain it to me. > > I've reduced it to the point where it still persists. > > I've tried to ask on the xilinx forum > > but it looks like that that forum more engaged to help me avoid that pr= oblem then explain what is going on here... > > Here is the code > > > > entity test is > > Port ( > > Clock : in std_logic; > > Dev_Linked : in std_logic_vector(0 downto 0); > > R_CHCS : out std_logic_vector(1 downto 0):=3D"01" > > ); > > end entity test; > > > > architecture Behavioral of test is > > begin > > > > R_CHCS_proc : process (Clock) is > > begin > > if rising_edge(Clock) then > > for i in 0 to 0 loop > > R_CHCS(i * 2) <=3D '0'; > > end loop; > > end if; > > end process R_CHCS_proc; > > > > R_CHCS(1) <=3D Dev_Linked(0) when rising_edge(Clock); > > > > end Behavioral; > > > > On the first clock cycle R_CHCS becomes "X0". And I don't know why. On = Xilinx forum say that "Questa also gives the same output" and it's not a bu= g of the simulator and it's because each process makes it's own driver for = CHCS and it gives 'X' value. But it doesn't make sense for me because if I= remove unnecessary loop in R_CHCS_proc this problem disappears, and it is = nothing to do with processes. > > > > Maybe someone could explain this to me? >=20 > I think Jim gave you an explanation even if it is a bit hard to=20 > understand. VHDL has a lot of things like that. The basic rule is=20 > "don't do that". I can't say I see any reason why you would want to do= =20 > that. Why not just include the assignment to bit 1 of R_CHCS in the=20 > same clocked process as the other assignment to R_CHCS? >=20 > Rick >=20 > --=20 >=20 > Rick I just came across this strange thing and I became curious what it is and w= hy. I just want to understand VHDL better. Originally it was written in a such way in attempt to separate different ma= tters in different processes to make code more readable and assign differen= t resets to this different matters. (there were a problems with huge fanout= of a reset signal and failed timings as a result). From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 09:58:43 +0000 (UTC) Organization: A noiseless patient Spider Lines: 19 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 17 Oct 2015 09:58:43 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="16691"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+mGF5Kj9rFX46ZmjCSy71+HfRXwrlPmlA=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:7zGKlMUwdNZpSGV6qlvZ3QHFNn8= Xref: mx02.eternal-september.org comp.lang.vhdl:8585 comp.lang.verilog:4080 On Sat, 17 Oct 2015 07:21:33 +0000, glen herrmannsfeldt wrote: > > VHDL is a little wordier than I like, but it isn't so hard to live with. > I will like it better when VHDL 2008 is supported, where I rarely > complained about the features in verilog 95. > > -- glen You may be pleased to know that ghdl at version 0.33 supports a lot more of VHDL-2008 than previously. Enough to run Jim's OSVVM suite. Its source release was last week. There aren't builds for all OS/ distributions yet, so some people will still have to build from source, or wait... https://sourceforge.net/projects/ghdl-updates/ -- Brian From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.107.37.206 with SMTP id l197mr2105344iol.17.1445076461903; Sat, 17 Oct 2015 03:07:41 -0700 (PDT) X-Received: by 10.50.43.195 with SMTP id y3mr216271igl.1.1445076461887; Sat, 17 Oct 2015 03:07:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no19360769igb.0!news-out.google.com!n2ni32733igy.0!nntp.google.com!kq10no22533610igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 17 Oct 2015 03:07:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sat, 17 Oct 2015 10:07:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8586 On Saturday, October 17, 2015 at 3:36:00 AM UTC+3, glen herrmannsfeldt wrote: > rickman wrote: > > On 10/16/2015 3:31 PM, Ilya Kalistru wrote: > >> I came across a strange behavior in my project and can't understand it. > >> Maybe you could explain it to me. > > (snip) > > >> R_CHCS_proc : process (Clock) is > >> begin > >> if rising_edge(Clock) then > >> for i in 0 to 0 loop > >> R_CHCS(i * 2) <= '0'; > >> end loop; > >> end if; > >> end process R_CHCS_proc; > > >> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); > > (snip) > > >> On the first clock cycle R_CHCS becomes "X0". > > (snip) > > > I think Jim gave you an explanation even if it is a bit hard to > > understand. VHDL has a lot of things like that. The basic rule is > > "don't do that". I can't say I see any reason why you would want to do > > that. Why not just include the assignment to bit 1 of R_CHCS in the > > same clocked process as the other assignment to R_CHCS? > > Yes. For each signal, use either the process form or the non-process > (verilog calls it continuous assignment) form, but don't mix them. > > In verilog, you have to declare reg or wire, so you have to decide early > which way you want to go. VHDL doesn't have that, but you still have to > get it right. > > It might work if you put the second one in its own process, but it has > to be in one. > > Also, I didn't know that you could use rising_edge(clock) outside > of process, but then again, I never even thought to try it. > > > -- glen Thank you for your advice. As for rising_edge(clock) outside of process, I met it somewhere and I found that it's good way to save few lines of code when you need something simple. Later I met this document http://www.synthworks.com/papers/VHDL_RTL_Synthesis_Standard_HDLCON_2002.pdf in which this way to make a register is also described. It works well with xilinx; I've been using it for several years. From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 11:02:52 -0400 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Oct 2015 15:00:48 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="03f127548f1143b691123e451e3cd25e"; logging-data="19141"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QWPO+AEdkns8bal721HQu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:MufWc2q4utA6AKNccf9yk9gQGUE= Xref: mx02.eternal-september.org comp.lang.vhdl:8587 comp.lang.verilog:4081 On 10/17/2015 3:21 AM, glen herrmannsfeldt wrote: > In comp.lang.vhdl rickman wrote: >> I'm not looking to start a VHDL vs. Verilog argument, but I was puzzled >> by Glen's comment in the VHDL group that he learned Verilog first before >> using VHDL. Am I correct in assuming you used VHDL because a customer >> required it? > > That is about right. > >> I learned VHDL, although not well, then went to work for a comms company >> who used Verilog. I never went to school for Verilog and never really >> bought a book. So I don't feel comfortable using it even though I have >> coded in it. > > I started about 1993. I was told that C programmers usually like > verilog, others I worked with were using it, so I did to. > > I bought both Thomas and Moorby's book, and the Sternhiem, Singh, > Madhavan, and Trivedi book. There might not have been many books > back then. Those two, and some Xilinx software to run designs > through, and I started writing down logic designs pretty soon. I will look into those references. My thing is I don't remember what I read as well as I used to. I'd like a book with the important stuff explicitly stated in a well organized manner so I can refer to it easily. Most importantly I want spelled out the various assumptions of Verilog code. I know there are things that are done with arithmetic that the user needs to understand. I found I could download the Thomas and Moorby book. The Doulos pages are often good, if not a great reference to return to. In this case I find the text runs off the screen without a scrollbar. To get it all on the page I have to shrink the text quite a bit. My old eyes don't like that. I wonder where that scrollbar has gotten to? > I also did some simulations with Veriwell. Is that more useful than the simulation tools from the FPGA vendors? >> On the other hand, after many years of VHDL, I won't say >> I've ever gotten "comfortable" with it. I've just learned to live with >> it. Part of the reason I haven't switched to Verilog is that I've never >> found a good book for it. In fact when I have asked in the Verilog >> group I'm told there *isn't* one. Buy "good" I mean one that covers all >> the pitfalls well. At least with VHDL it tells you you've screwed up. > > Many useful verilog features are new to VHDL, some too new for the > version of tools that I use. Even more, they are different for different > FPGA chips with the same version of tools. (Specifically, Spartan 3 vs. > Spartan 6.) Strange. By too new and "different" you mean some tools support some features which differ between the tools? So far I haven't found a VHDL 2008 feature I wanted to use that wasn't supported. It would be useful to have a chart of the features and the tools. With the restrictions on the tool licenses, I wonder if that would violate any by making and posting such a feature list? >> I'm curious who here has learned both and why? Which do you prefer and >> why? > > Most verilog operators are similar to C operators, so that helps some. > A few times, not so many, I have used & in VHDL when I meant AND. > > I still prefer verilog, but I figured out how to write most of the > things I need from verilog into VHDL. > > Verilog style concatenations are still too new to VHDL. The result is > a fair number of signals that are only needed to combine or separate > signals to/from a vector. I haven't found that. Have a ready example? > VHDL is a little wordier than I like, but it isn't so hard to live with. > I will like it better when VHDL 2008 is supported, where I rarely > complained about the features in verilog 95. I think calling VHDL "wordy" is like calling the Pope Catholic. I use it, but the typing is a PITA to the point I have regular expressions written in my boiler plate for converting between port declarations, instantiations and signal lists. Nicer would be an editor that could do much of that automatically... use a signal and the editor adds it to the signals list. Add a component instantiation and you just type the name and the full port map is added with "name => name" for each signal in the port list. I've touted the advantages of the strong typing used in VHDL, but I've never completely accepted that it is a big advantage. So I'm ready to give Verilog a try if I can find it less painful than all the typing I'd have to do to keep using VHDL. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Sat, 17 Oct 2015 19:10:47 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 29 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8588 comp.lang.verilog:4083 In comp.lang.vhdl rickman wrote: (snip) >> I also did some simulations with Veriwell. > Is that more useful than the simulation tools from the FPGA vendors? That was in the days before A and X had free versions. I was part of a discussion at FCCM 95 suggesting that companies should have free versions of the tools, and affordable (small) FPGAs. In my high school and college days, TTL chips were affordable enough to buy, design simple logic circuits and build them. A big reason for that was that enough were used in the computer industry to keep the economy of scale large, and prices low. I suspected in 1995 that as computers went more to VLSI, that TTL would go away. It seems that 20 years later, it is still fairly easy to get, and afford, TTL, but maybe not in 20 more years. (Though as I understand it, the usual undergrad digital logic course is now taught with simulation and no actual circuits.) If you just want a simple simulation, though, Veriwell is a fine choice. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Strange 'X' values. Date: Sun, 18 Oct 2015 02:00:02 -0400 Organization: A noiseless patient Spider Lines: 73 Message-ID: References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 18 Oct 2015 05:57:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="02e5de92ffe817d22ea5761a436dd6e8"; logging-data="23793"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Ya5GgPI72ts5ffjP5n6sE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> Cancel-Lock: sha1:qe+rXmxvR9dmfwyrAS0w03mIX+g= Xref: mx02.eternal-september.org comp.lang.vhdl:8589 On 10/17/2015 5:51 AM, Ilya Kalistru wrote: > On Saturday, October 17, 2015 at 3:20:03 AM UTC+3, rickman wrote: >> On 10/16/2015 3:31 PM, Ilya Kalistru wrote: >>> Good day. I came across a strange behavior in my project and >>> can't understand it. Maybe you could explain it to me. I've >>> reduced it to the point where it still persists. I've tried to >>> ask on the xilinx forum but it looks like that that forum more >>> engaged to help me avoid that problem then explain what is going >>> on here... Here is the code >>> >>> entity test is Port ( Clock : in std_logic; Dev_Linked : in >>> std_logic_vector(0 downto 0); R_CHCS : out std_logic_vector(1 >>> downto 0):="01" ); end entity test; >>> >>> architecture Behavioral of test is begin >>> >>> R_CHCS_proc : process (Clock) is begin if rising_edge(Clock) >>> then for i in 0 to 0 loop R_CHCS(i * 2) <= '0'; end loop; end >>> if; end process R_CHCS_proc; >>> >>> R_CHCS(1) <= Dev_Linked(0) when rising_edge(Clock); >>> >>> end Behavioral; >>> >>> On the first clock cycle R_CHCS becomes "X0". And I don't know >>> why. On Xilinx forum say that "Questa also gives the same output" >>> and it's not a bug of the simulator and it's because each process >>> makes it's own driver for CHCS and it gives 'X' value. But it >>> doesn't make sense for me because if I remove unnecessary loop in >>> R_CHCS_proc this problem disappears, and it is nothing to do with >>> processes. >>> >>> Maybe someone could explain this to me? >> >> I think Jim gave you an explanation even if it is a bit hard to >> understand. VHDL has a lot of things like that. The basic rule >> is "don't do that". I can't say I see any reason why you would >> want to do that. Why not just include the assignment to bit 1 of >> R_CHCS in the same clocked process as the other assignment to >> R_CHCS? >> >> Rick >> >> -- >> >> Rick > > I just came across this strange thing and I became curious what it is > and why. I just want to understand VHDL better. > > Originally it was written in a such way in attempt to separate > different matters in different processes to make code more readable > and assign different resets to this different matters. (there were a > problems with huge fanout of a reset signal and failed timings as a > result). I guess the question then is, if these two signals need to be differentiated, why are they separate bits in the same vector? Make them separate signals and you can express their assignments totally separately. The common reset signal often does not meet any timing spec. It is better to design your circuits so that the timing on the reset does not matter. Any sequential logic that must leave the reset state together should use a common synchronization signal controlling the exit from reset. This often results in much smaller nets since the reset exit requirement is usually a local one rather than global. If it is global, then you will need a common control with multiple output FFs as repeaters so the fan out of each copy is not so great. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.129.4.203 with SMTP id 194mr2070921ywe.33.1445156961351; Sun, 18 Oct 2015 01:29:21 -0700 (PDT) X-Received: by 10.50.13.38 with SMTP id e6mr266751igc.5.1445156961320; Sun, 18 Oct 2015 01:29:21 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!z77no10325180qge.1!news-out.google.com!n2ni33599igy.0!nntp.google.com!kq10no22904793igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 18 Oct 2015 01:29:20 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.188.121.67; posting-account=IBlIwwoAAADVasu4SEKAAkcNfZ1fhrbe NNTP-Posting-Host: 46.188.121.67 References: <07635e77-562b-44f6-8b0f-7d211cb10a20@googlegroups.com> <7b6230a9-a201-4434-bfda-caf958f21142@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Strange 'X' values. From: Ilya Kalistru Injection-Date: Sun, 18 Oct 2015 08:29:21 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8590 > I guess the question then is, if these two signals need to be=20 > differentiated, why are they separate bits in the same vector? Make=20 > them separate signals and you can express their assignments totally=20 > separately. I had similar thoughts just after reading of your comments to my post. R_C= HCS is a register which indicates states of a coprocessor for a CPU and dif= ferent bits of it have different meanings. So, in this case I should have d= ifferent signals for different indicators and then I should concatenate the= m in R_CHCS. I would have done that if it had been my code, but I am just t= rying to fix my colleague's code. > The common reset signal often does not meet any timing spec. It is=20 > better to design your circuits so that the timing on the reset does not= =20 > matter. Any sequential logic that must leave the reset state together=20 > should use a common synchronization signal controlling the exit from=20 > reset. This often results in much smaller nets since the reset exit=20 > requirement is usually a local one rather than global. If it is global,= =20 > then you will need a common control with multiple output FFs as=20 > repeaters so the fan out of each copy is not so great. it's exactly how I fixed this problem. > --=20 >=20 > Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.68.131.104 with SMTP id ol8mr24762796pbb.4.1445242096562; Mon, 19 Oct 2015 01:08:16 -0700 (PDT) X-Received: by 10.50.129.10 with SMTP id ns10mr145783igb.0.1445242096489; Mon, 19 Oct 2015 01:08:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no23316709igb.0!news-out.google.com!z4ni25521ign.0!nntp.google.com!kq10no23316706igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 01:08:16 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.168.206.17; posting-account=jGbtbQoAAADhdS75pUrt6RwP8xfugXhe NNTP-Posting-Host: 122.168.206.17 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Subject: C code for conversion instead of programming. From: Rajeev Varshney Injection-Date: Mon, 19 Oct 2015 08:08:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8591 Hello every1, I have a doubt about C code conversion. Can someone help me regard this. I am in RTL design. and I am getting some calls in that people ask , Howdo you use c? As programming or Conversion. Can someone please let me know about this. Or refer any document regard it. where is application for c code conversion for hdl. and any help regard this topic ..I am unable to understand, what actually they ask for. From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 10:16:42 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8592 Rajeev Varshney wrote: > I have a doubt about C code conversion. Can someone help me > regard this. I am in RTL design. and I am getting some calls in > that people ask , Howdo you use c? As programming or Conversion. > Can someone please let me know about this. > Or refer any document regard it. Personally, I don't recommend using C as an HDL, but it might depend on what you are doing. verilog uses the C operators, so it is fairly easy for C programmers who know about digital logic design to learn to write. The designs I work on are so different from what anyone would do in C, that I don't see using C. > where is application for c code conversion for hdl. and any > help regard this topic ..I am unable to understand, > what actually they ask for. What are you actually trying to do? That makes a big difference in how you should do it. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Mon, 19 Oct 2015 10:52:07 -0400 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Oct 2015 14:50:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79905ffb271791baaa8cf379f6c3d6ce"; logging-data="21882"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18GwRiQKnU/SwLLnr5FUM3H" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:+FDSkdqe65zKt/pJQxfwkftlgDc= Xref: mx02.eternal-september.org comp.lang.vhdl:8593 comp.lang.verilog:4085 On 10/17/2015 3:10 PM, glen herrmannsfeldt wrote: > In comp.lang.vhdl rickman wrote: > > (snip) > >>> I also did some simulations with Veriwell. > >> Is that more useful than the simulation tools from the FPGA vendors? > > That was in the days before A and X had free versions. > > I was part of a discussion at FCCM 95 suggesting that companies > should have free versions of the tools, and affordable (small) > FPGAs. Thank you on both those accounts. I have always felt FPGAs could be sold more like MCUs in many packages and with lots of variations of included I/O features. But the FPGA vendors still like their primary markets of comms where most of the need is for larger and faster devices. Unlike car companies where the money is made on the products for the average buyer, FPGAs are marketed to higher end buyers with extreme needs. I guess in general they do better selling to a few large customers rather than lots of small ones. Maybe the MCU market is just plain different in that regard with most of the profit coming from the many, many small quantity users across the board of device complexity. > In my high school and college days, TTL chips were affordable enough > to buy, design simple logic circuits and build them. A big reason > for that was that enough were used in the computer industry to keep > the economy of scale large, and prices low. > > I suspected in 1995 that as computers went more to VLSI, that TTL > would go away. It seems that 20 years later, it is still fairly > easy to get, and afford, TTL, but maybe not in 20 more years. Much TTL is getting harder to buy. There are still many basic functions available, but there used to be a wide assortment of specialized functions, many of which are no longer sold in any of the TTL/CMOS families. > (Though as I understand it, the usual undergrad digital logic course > is now taught with simulation and no actual circuits.) > > If you just want a simple simulation, though, Veriwell is a fine choice. I don't mind the vendor tools. Many years ago I had learned a bit of Modelsim and ordered the low end Lattice tools with Modelsim. At that point you still had to pay Lattice for a package with a simulator. A month later when they shipped, it came with the Aldec simulator which I knew nothing about. I had a COW and talked to half a dozen reps on the phone which got me nowhere. When I fired up the tool I found there was little difference and could use the tool pretty well so I cooled off and got to work. Heck, at that time Modelsim had a memory leak that would crash it every so often and this tool worked without crashing so I was actually better off. lol So I'm happy with the simulators from the vendors although I haven't used Xilinx tools in a while. I read a lot lately about their schizoid nature. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 10:58:04 -0400 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Oct 2015 14:56:00 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="79905ffb271791baaa8cf379f6c3d6ce"; logging-data="23612"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19JRkGHhFBFJZ+i8w7D0L5B" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Cancel-Lock: sha1:pcD0pOEU66SvWT5gFG4cDicynYg= Xref: mx02.eternal-september.org comp.lang.vhdl:8594 On 10/19/2015 4:08 AM, Rajeev Varshney wrote: > Hello every1, > I have a doubt about C code conversion. Can someone help me regard this. I am in RTL design. and I am getting some calls in that people ask , Howdo you use c? As programming or Conversion. > Can someone please let me know about this. Or refer any document regard it. > > > where is application for c code conversion for hdl. and any help regard this topic ..I am unable to understand, what actually they ask for. There are C to hardware compilers. But I think, like any HDL, for your code to be synthesizable it has to be written according to a style guide. Even in VHDL or Verilog, you can write code that will simulate, but won't be synthesizable. Much more so in C. Here is a like to a discussion of C tools for FPGAs. http://stackoverflow.com/questions/8988629/can-you-program-fpgas-in-c-like-languages This Wikipedia article has a list of potential tools. https://en.wikipedia.org/wiki/C_to_HDL -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Mon, 19 Oct 2015 22:25:47 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 22 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8595 rickman wrote: > On 10/19/2015 4:08 AM, Rajeev Varshney wrote: >> I have a doubt about C code conversion. Can someone help me >> regard this. I am in RTL design. and I am getting some calls >> in that people ask , Howdo you use c? >> As programming or Conversion. (snip) > There are C to hardware compilers. But I think, like any HDL, for your > code to be synthesizable it has to be written according to a style > guide. Even in VHDL or Verilog, you can write code that will simulate, > but won't be synthesizable. Much more so in C. I have thought that a tool that would compile a program to some intermediate code, and also generate logic for an efficient interpreter of that code, could be useful. That is, a soft processor optimized for the code at hand. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.50.62.68 with SMTP id w4mr1340471igr.13.1445313146964; Mon, 19 Oct 2015 20:52:26 -0700 (PDT) X-Received: by 10.50.131.162 with SMTP id on2mr24582igb.4.1445313146910; Mon, 19 Oct 2015 20:52:26 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no23782676igb.0!news-out.google.com!z4ni26261ign.0!nntp.google.com!kq10no23782667igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 20:52:26 -0700 (PDT) In-Reply-To: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=122.168.178.15; posting-account=jGbtbQoAAADhdS75pUrt6RwP8xfugXhe NNTP-Posting-Host: 122.168.178.15 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Subject: Re: C code for conversion instead of programming. From: Rajeev Varshney Injection-Date: Tue, 20 Oct 2015 03:52:26 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8596 Hello, Thanks you for your valueable suggestion..... After reading your responses, I have question that why people ask for c to hdl. Also last year I came to know some technology specialist that upcoming hardware will be based on clanguages. I s it related to something 7Series FPGA. From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.31.149.200 with SMTP id x191mr1279122vkd.14.1445322851676; Mon, 19 Oct 2015 23:34:11 -0700 (PDT) X-Received: by 10.50.30.102 with SMTP id r6mr404647igh.3.1445322851636; Mon, 19 Oct 2015 23:34:11 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!m48no356797qgd.0!news-out.google.com!n2ni35576igy.0!nntp.google.com!kq10no23826212igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 19 Oct 2015 23:34:10 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8c94c43f-6681-4088-a876-17692af9d843@googlegroups.com> Subject: Re: creating program From: bknpk@hotmail.com Injection-Date: Tue, 20 Oct 2015 06:34:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1708 X-Received-Body-CRC: 2972710380 Xref: mx02.eternal-september.org comp.lang.vhdl:8597 On Friday, October 16, 2015 at 12:36:53 PM UTC+3, aadi wrote: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > plzz help me You may want to see some examples. A simple UART project http://bknpk.ddns.net/my_web/MiscellaneousHW/UART/uart_tx_1.html A more complex design based on some free open IP stack. It also synthesized with Xilinx free XST and simulated with post NGD net-list. All is done with the free VHDL simulator GHDL http://bknpk.ddns.net/my_web/IP_STACK/start_1.html From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Tue, 20 Oct 2015 04:22:28 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 08:20:21 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="2576"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/R6vsLkmV3fvRHAGDgsfkx" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:8izYjPJdt57NgCb4JzL1bC8N400= Xref: mx02.eternal-september.org comp.lang.vhdl:8598 On 10/19/2015 6:25 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/19/2015 4:08 AM, Rajeev Varshney wrote: > >>> I have a doubt about C code conversion. Can someone help me >>> regard this. I am in RTL design. and I am getting some calls >>> in that people ask , Howdo you use c? >>> As programming or Conversion. > > (snip) > >> There are C to hardware compilers. But I think, like any HDL, for your >> code to be synthesizable it has to be written according to a style >> guide. Even in VHDL or Verilog, you can write code that will simulate, >> but won't be synthesizable. Much more so in C. > > I have thought that a tool that would compile a program to some > intermediate code, and also generate logic for an efficient > interpreter of that code, could be useful. > > That is, a soft processor optimized for the code at hand. Perhaps, but how much better than just buying an already optimized hard IP processor like an ARM or an x86 of some flavor? Sure soft processors have uses, but the work involved in designing such a tool to automatically produce machine code and a processor from C code would be a lot more than can be justified I'd bet, but who knows? It may just be the lack of a perceived market. Maybe this would be a good university research project? -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.182.181.3 with SMTP id ds3mr1838423obc.5.1445333509807; Tue, 20 Oct 2015 02:31:49 -0700 (PDT) X-Received: by 10.50.85.47 with SMTP id e15mr30267igz.9.1445333509786; Tue, 20 Oct 2015 02:31:49 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no20227616igb.0!news-out.google.com!n2ni35709igy.0!nntp.google.com!kq10no23895661igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 02:31:49 -0700 (PDT) In-Reply-To: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: C code for conversion instead of programming. From: Thomas Stanka Injection-Date: Tue, 20 Oct 2015 09:31:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8599 Am Dienstag, 20. Oktober 2015 05:52:30 UTC+2 schrieb Rajeev Varshney: > After reading your responses, I have question that why people ask for c t= o hdl. You should ask this to the person asking you. In general you might have a C based simulation model and like to easy excha= nge pure software with your design model written in C to verify the design = will behave like expected. In C you use usually cycle based simulation inst= ead of time based (ns,ps,..) simulation. Cycle based simulation ignores som= e effects but simulations run significant faster. Additionally there is no = simulator providing the same simulation speed, than any C-executeable.=20 On the contrary ask any specialist who likes to sell you C based hardware d= esign, how to scope with 10 clock domains that are asynchronous to each oth= er in C and how to access existing design IP written in Verilog.=20 bye Thomas From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Tue, 20 Oct 2015 09:49:42 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8600 rickman wrote: (snip on C as an HDL) (then I wrote) >> I have thought that a tool that would compile a program to some >> intermediate code, and also generate logic for an efficient >> interpreter of that code, could be useful. >> That is, a soft processor optimized for the code at hand. > Perhaps, but how much better than just buying an already optimized hard > IP processor like an ARM or an x86 of some flavor? Sure soft processors > have uses, but the work involved in designing such a tool to > automatically produce machine code and a processor from C code would be > a lot more than can be justified I'd bet, but who knows? It may just be > the lack of a perceived market. Maybe this would be a good university > research project? I haven't looked in detail how the usual soft processors work. It wouldn't seem so hard to compile the C, see which instructions the code actually used, then remove instructions from the soft processor that weren't used. That should be much less work than the synthesis tools themselves. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.107.159.132 with SMTP id i126mr3392909ioe.23.1445350373004; Tue, 20 Oct 2015 07:12:53 -0700 (PDT) X-Received: by 10.50.103.69 with SMTP id fu5mr71162igb.5.1445350372986; Tue, 20 Oct 2015 07:12:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24013354igb.0!news-out.google.com!n2ni35889igy.0!nntp.google.com!kq10no24013344igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 07:12:52 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Why does Modelsim insist so many bits for a multiplication? From: fl Injection-Date: Tue, 20 Oct 2015 14:12:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8601 Hi, I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter unsigned or signed number. When I try it with Modelsim, I find that it insists the result be 10-bit. Otherwise, it issues a warning. Could you explain what rule behind Modelsim to give such a warning? Thanks, ---------------- architecture behave of example_signed_unsigned is signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0'); signal rs_SUB_RESULT : signed(4 downto 0) := (others => '0'); signal ru_SUB_RESULT : unsigned(4 downto 0) := (others => '0'); signal rs_mpy_RESULT : signed(9 downto 0) := (others => '0'); signal ru_mpy_RESULT : unsigned(9 downto 0) := (others => '0'); begin -- Purpose: Add two numbers. Does both the signed and unsigned -- addition for demonstration. This process is synthesizable. p_SUM : process (i_clk, i_rst_l) begin if i_rst_l = '0' then -- asynchronous reset (active low) rs_SUM_RESULT <= (others => '0'); ru_SUM_RESULT <= (others => '0'); elsif rising_edge(i_clk) then ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b); rs_SUM_RESULT <= signed(i_a) + signed(i_b); end if; end process p_SUM; p_mpy0 : process (i_clk, i_rst_l) begin if i_rst_l = '0' then -- asynchronous reset (active low) rs_mpy_RESULT <= (others => '0'); ru_mpy_RESULT <= (others => '0'); elsif rising_edge(i_clk) then ru_mpy_RESULT <= unsigned(i_a) * unsigned(i_b); rs_mpy_RESULT <= signed(i_a) * signed(i_b); end if; end process p_mpy0; From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!bloom-beacon.mit.edu!bloom-beacon.mit.edu!panix!newsfeed-00.mathworks.com!news.mathworks.com!not-for-mail From: Tim McBrayer Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 10:38:08 -0400 Organization: The MathWorks, Inc. Lines: 23 Message-ID: References: NNTP-Posting-Host: tmcbraye-deb7-64.dhcp.mathworks.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: newscl01ah.mathworks.com 1445351888 16858 172.28.219.76 (20 Oct 2015 14:38:08 GMT) X-Complaints-To: news@mathworks.com NNTP-Posting-Date: Tue, 20 Oct 2015 14:38:08 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Icedove/24.5.0 In-Reply-To: Xref: mx02.eternal-september.org comp.lang.vhdl:8602 On 10/20/2015 10:12 AM, fl wrote: > Hi, > > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter > unsigned or signed number. When I try it with Modelsim, I find that it > insists the result be 10-bit. Otherwise, it issues a warning. Your 9-bit product assumption is the problem; 9 bits are not enough to store 5 bits * 5 bits at full precision. It requires 10 bits. Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 has range 0 to 31. Max value of multiplication: 31 * 31 = 961 Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 - 1 = 1023 Thus, 5 bits * 5 bits requires 10 bits for a full precision result. -- Tim McBrayer MathWorks From newsfish@newsfish Tue Dec 29 16:44:00 2015 X-Received: by 10.107.28.67 with SMTP id c64mr2321707ioc.1.1445356178348; Tue, 20 Oct 2015 08:49:38 -0700 (PDT) X-Received: by 10.50.57.17 with SMTP id e17mr63603igq.2.1445356178332; Tue, 20 Oct 2015 08:49:38 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24059364igb.0!news-out.google.com!n2ni35970igy.0!nntp.google.com!kq10no20340615igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 08:49:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Why does Modelsim insist so many bits for a multiplication? From: fl Injection-Date: Tue, 20 Oct 2015 15:49:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8603 On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: > On 10/20/2015 10:12 AM, fl wrote: > > Hi, > > > > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter > > unsigned or signed number. When I try it with Modelsim, I find that i= t > > insists the result be 10-bit. Otherwise, it issues a warning. >=20 >=20 > Your 9-bit product assumption is the problem; 9 bits are not enough to st= ore 5 bits * 5=20 > bits at full precision. It requires 10 bits. >=20 > Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 ha= s range 0 to 31. >=20 > Max value of multiplication: 31 * 31 =3D 961 >=20 > Max unsigned 9-bit value: 2^9 - 1 =3D 511 > Max unsigned 10-bit value: 2^10 - 1 =3D 1023 >=20 > Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > --=20 > Tim McBrayer > MathWorks Thanks. You said is correct for unsigned number multiplication. I just verify that it is correct for signed number multiplication. But the puzzling thing is that there are such examples on the web: Q15 multiplies Q15, the result is Q31. There is a sign extension bit. I always clip the= =20 MSB of the multiplication result, then often round to 16-bit.=20 Thanks for your article. Now I am puzzling on fixed point multiplication wh= en thinking about the multiplication product. First of all, Q.x format coul= d be signed, or unsigned number, is it right? After reading other online docs, I put it here to rephrase my question: Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to us= e (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it too. = So, the result has one redundant sign extension bit. When I write VHDL code= , Modelsim insists on using 10-bit result for two signed integers Q5.0 mult= iplies Q5.0. Why does it not consider sign extension bit? From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:11:40 +0000 (UTC) Organization: A noiseless patient Spider Lines: 67 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 16:11:40 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18r8ic31AivblicvGh6Cv+G" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:vr/JCbrdhVBUGRCP9PHF56Y/l+A= Xref: mx02.eternal-september.org comp.lang.vhdl:8604 On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: > On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: >> > Hi, >> > >> > I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >> > unsigned or signed number. When I try it with Modelsim, I find that >> > it insists the result be 10-bit. Otherwise, it issues a warning. >> >> >> Your 9-bit product assumption is the problem; 9 bits are not enough to >> store 5 bits * 5 bits at full precision. It requires 10 bits. >> >> Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 >> has range 0 to 31. >> >> Max value of multiplication: 31 * 31 = 961 >> >> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 >> - 1 = 1023 >> >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >> -- >> Tim McBrayer MathWorks > > Thanks. You said is correct for unsigned number multiplication. I just > verify that it is correct for signed number multiplication. But the > puzzling thing is that there are such examples on the web: Q15 > multiplies Q15, the result is Q31. There is a sign extension bit. I > always clip the MSB of the multiplication result, then often round to > 16-bit. > > Thanks for your article. Now I am puzzling on fixed point multiplication > when thinking about the multiplication product. First of all, Q.x format > could be signed, or unsigned number, is it right? > > After reading other online docs, I put it here to rephrase my question: > Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to > use (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it > too. So, the result has one redundant sign extension bit. When I write > VHDL code, Modelsim insists on using 10-bit result for two signed > integers Q5.0 multiplies Q5.0. Why does it not consider sign extension > bit? Because the "sign extension bit" is not redundant information in exactly one case. In your format -1 is represented 1.0000. 1.0000 * 1.0000 = -1 * -1 = 1 = 01.00000000. Also, this is why I loathe Q notation; no one ever quite follows what it means. Instead I use Ux.y and Sx.y. A signed number with a total of 5 bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value of -1) and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. When you multiply it's trivially simple to track the binary point; you add integer bits together and you add fractional bits together. S1.4 * S1.4 = S2.8, or to be completely explicit: S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:21:03 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 27 Message-ID: References: NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8605 Tim McBrayer wrote: > On 10/20/2015 10:12 AM, fl wrote: >> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >> unsigned or signed number. When I try it with Modelsim, I find that it >> insists the result be 10-bit. Otherwise, it issues a warning. > Your 9-bit product assumption is the problem; 9 bits are not enough > to store 5 bits * 5 bits at full precision. It requires 10 bits. > Take the simplest example, multiplying two unsigned 5-bit numbers. > 2^5 has range 0 to 31. > Max value of multiplication: 31 * 31 = 961 > Max unsigned 9-bit value: 2^9 - 1 = 511 > Max unsigned 10-bit value: 2^10 - 1 = 1023 > Thus, 5 bits * 5 bits requires 10 bits for a full precision result. But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. The real question is what VHDL says about it. The verilog rules for add are funny, and many get it wrong. -- glen From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: gtwrek@sonic.net (Mark Curry) Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:58:02 +0000 (UTC) Organization: Sonic.net, Inc. Lines: 37 Message-ID: References: Injection-Date: Tue, 20 Oct 2015 16:58:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="94f7a07384bb54987de3cb7c91340d9c"; logging-data="19757"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1898mYyiUxOeo30gYww8CQr" Originator: gtwrek@sonic.net (Mark Curry) X-Newsreader: trn 4.0-test76 (Apr 2, 2001) Cancel-Lock: sha1:eX6XBo4n+h528nmBniTn5Ke0/1Q= Xref: mx02.eternal-september.org comp.lang.vhdl:8606 In article , glen herrmannsfeldt wrote: >Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: > >>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>> unsigned or signed number. When I try it with Modelsim, I find that it >>> insists the result be 10-bit. Otherwise, it issues a warning. > >> Your 9-bit product assumption is the problem; 9 bits are not enough >> to store 5 bits * 5 bits at full precision. It requires 10 bits. > >> Take the simplest example, multiplying two unsigned 5-bit numbers. >> 2^5 has range 0 to 31. > >> Max value of multiplication: 31 * 31 = 961 > >> Max unsigned 9-bit value: 2^9 - 1 = 511 >> Max unsigned 10-bit value: 2^10 - 1 = 1023 > >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > >But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 bits for signed either. (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign bit at the output too. Or I'm missing your point? Regards, Mark From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:14:18 -0400 Organization: A noiseless patient Spider Lines: 74 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 20:12:12 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Li7dEhv+BrgJHFW3PYQJE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:S4OaaGiRNKMjVy1YOOxzMR3FvFY= Xref: mx02.eternal-september.org comp.lang.vhdl:8607 On 10/20/2015 12:11 PM, Rob Gaddi wrote: > On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: > >> On Tuesday, October 20, 2015 at 10:38:12 AM UTC-4, Tim McBrayer wrote: >>> On 10/20/2015 10:12 AM, fl wrote: >>>> Hi, >>>> >>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>>> unsigned or signed number. When I try it with Modelsim, I find that >>>> it insists the result be 10-bit. Otherwise, it issues a warning. >>> >>> >>> Your 9-bit product assumption is the problem; 9 bits are not enough to >>> store 5 bits * 5 bits at full precision. It requires 10 bits. >>> >>> Take the simplest example, multiplying two unsigned 5-bit numbers. 2^5 >>> has range 0 to 31. >>> >>> Max value of multiplication: 31 * 31 = 961 >>> >>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: 2^10 >>> - 1 = 1023 >>> >>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>> -- >>> Tim McBrayer MathWorks >> >> Thanks. You said is correct for unsigned number multiplication. I just >> verify that it is correct for signed number multiplication. But the >> puzzling thing is that there are such examples on the web: Q15 >> multiplies Q15, the result is Q31. There is a sign extension bit. I >> always clip the MSB of the multiplication result, then often round to >> 16-bit. >> >> Thanks for your article. Now I am puzzling on fixed point multiplication >> when thinking about the multiplication product. First of all, Q.x format >> could be signed, or unsigned number, is it right? >> >> After reading other online docs, I put it here to rephrase my question: >> Then, for signed numbers Q.a and Q.b, the product is Q.(a+b). Q.a has to >> use (a+1) bit to represent it. Q.b has to use (b+1) bit to represent it >> too. So, the result has one redundant sign extension bit. When I write >> VHDL code, Modelsim insists on using 10-bit result for two signed >> integers Q5.0 multiplies Q5.0. Why does it not consider sign extension >> bit? > > Because the "sign extension bit" is not redundant information in exactly > one case. In your format -1 is represented 1.0000. 1.0000 * 1.0000 = -1 > * -1 = 1 = 01.00000000. > > Also, this is why I loathe Q notation; no one ever quite follows what it > means. Instead I use Ux.y and Sx.y. A signed number with a total of 5 > bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value of -1) > and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. > > When you multiply it's trivially simple to track the binary point; you > add integer bits together and you add fractional bits together. S1.4 * > S1.4 = S2.8, or to be completely explicit: > > S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. Now I'm lost. 5 bit signed integers would be -16 to 15. Max range of the product would be from -16 * -16 yielding -256 which is a 9 bit signed number, no? My understanding is that you need 1 bit for the sign and n-1 bits for the significands (or whatever they are called). So the product will be able to eliminate one of the sign bits and use 2 * (n-1) + 1 or 2n - 1 bits total. Your notation of the product, S2.8 implies there is a larger range in the product than [-1,1), no? The product will be S1.8 I think. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:15:20 -0400 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 20 Oct 2015 20:13:13 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10369"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+r3I3P1iEE3nRI52CnVeRD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:0LbXBzVwx5qxzIzakXPm37ZGYXo= Xref: mx02.eternal-september.org comp.lang.vhdl:8608 On 10/20/2015 12:21 PM, glen herrmannsfeldt wrote: > Tim McBrayer wrote: >> On 10/20/2015 10:12 AM, fl wrote: > >>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>> unsigned or signed number. When I try it with Modelsim, I find that it >>> insists the result be 10-bit. Otherwise, it issues a warning. > >> Your 9-bit product assumption is the problem; 9 bits are not enough >> to store 5 bits * 5 bits at full precision. It requires 10 bits. > >> Take the simplest example, multiplying two unsigned 5-bit numbers. >> 2^5 has range 0 to 31. > >> Max value of multiplication: 31 * 31 = 961 > >> Max unsigned 9-bit value: 2^9 - 1 = 511 >> Max unsigned 10-bit value: 2^10 - 1 = 1023 > >> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. > > But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. > > The real question is what VHDL says about it. > > The verilog rules for add are funny, and many get it wrong. That is what I've read and why I'm looking for a book that explains this clearly before I commit to using Verilog. -- Rick From newsfish@newsfish Tue Dec 29 16:44:00 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 16:20:40 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:18:37 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="12002"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+tXTr+vQpUcMkbX2Yv2Imc" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:MChPlZIRxbN1Gkz8Gdn+DO4B8NU= Xref: mx02.eternal-september.org comp.lang.vhdl:8609 On 10/20/2015 12:58 PM, Mark Curry wrote: > In article , > glen herrmannsfeldt wrote: >> Tim McBrayer wrote: >>> On 10/20/2015 10:12 AM, fl wrote: >> >>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter >>>> unsigned or signed number. When I try it with Modelsim, I find that it >>>> insists the result be 10-bit. Otherwise, it issues a warning. >> >>> Your 9-bit product assumption is the problem; 9 bits are not enough >>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >> >>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>> 2^5 has range 0 to 31. >> >>> Max value of multiplication: 31 * 31 = 961 >> >>> Max unsigned 9-bit value: 2^9 - 1 = 511 >>> Max unsigned 10-bit value: 2^10 - 1 = 1023 >> >>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >> >> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. > > Glen - huh? The (max negative) * (max negative) case does NOT fit > in 9 bits for signed either. > > (-16)*(-16) = 256 = 'b01_0000_0000 > you need 10 bits - you need the sign bit at the output too. > > Or I'm missing your point? Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I remember that this is the defining case for multiplication and requires the full 2n bits... just as Rob said. If your data is for any reason limited to ±(2^(n-1)-1) then one less bit is needed for the product. Such is the case if an unsigned value was negated to produce the signed value. I don't get his product notation becoming S2.8 rather than S1.9 though. If the range of the result is [-1,1) there is still only one bit left of the binary point, or am I wrong about that too, lol? -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 20:32:53 +0000 (UTC) Organization: A noiseless patient Spider Lines: 38 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:32:53 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18RNmuFRq/4kYbE4MioqZDg" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:kSSnB3NiATUF5wsDlBFhd6AlFG8= Xref: mx02.eternal-september.org comp.lang.vhdl:8610 On Tue, 20 Oct 2015 16:14:18 -0400, rickman wrote: > On 10/20/2015 12:11 PM, Rob Gaddi wrote: >> On Tue, 20 Oct 2015 08:49:37 -0700, fl wrote: >> >> Also, this is why I loathe Q notation; no one ever quite follows what >> it means. Instead I use Ux.y and Sx.y. A signed number with a total >> of 5 bits and a range of [-1, 1) is S1.4. 1 integer bit (with a value >> of -1) and 4 fractional bits of values 1/2, 1/4, 1/8, and 1/16. >> >> When you multiply it's trivially simple to track the binary point; you >> add integer bits together and you add fractional bits together. S1.4 * >> S1.4 = S2.8, or to be completely explicit: >> >> S1.4 [-1,1) * S1.4 [-1,1) = S2.8 [-1,1]. > > Now I'm lost. 5 bit signed integers would be -16 to 15. Max range of > the product would be from -16 * -16 yielding -256 which is a 9 bit > signed number, no? My understanding is that you need 1 bit for the sign > and n-1 bits for the significands (or whatever they are called). So the > product will be able to eliminate one of the sign bits and use 2 * (n-1) > + 1 or 2n - 1 bits total. > Nope. -16 * -16 = +256. 01_0000_0000b if you're in 2's compliment and thus the MSB has a negative value. > Your notation of the product, S2.8 implies there is a larger range in > the product than [-1,1), no? The product will be S1.8 I think. There is a larger range in the product, it's [-1, 1]. The inclusion of +1 as a possibility is a righteous pain in the ass and requires you be willing to give up an entire bit to its existence if you can't preclude it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Tue, 20 Oct 2015 20:46:32 +0000 (UTC) Organization: A noiseless patient Spider Lines: 66 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 20 Oct 2015 20:46:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="0a3c9f09d5246ee6d0bbab9a3b7899b1"; logging-data="14940"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vDwMST037gBSF4/5dTqSj" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:LSGmI+PF/HjapYMtoQIM/kavxaY= Xref: mx02.eternal-september.org comp.lang.vhdl:8611 On Tue, 20 Oct 2015 16:20:40 -0400, rickman wrote: > On 10/20/2015 12:58 PM, Mark Curry wrote: >> In article , >> glen herrmannsfeldt wrote: >>> Tim McBrayer wrote: >>>> On 10/20/2015 10:12 AM, fl wrote: >>> >>>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no >>>>> matter >>>>> unsigned or signed number. When I try it with Modelsim, I find >>>>> that it insists the result be 10-bit. Otherwise, it issues a >>>>> warning. >>> >>>> Your 9-bit product assumption is the problem; 9 bits are not enough >>>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >>> >>>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>>> 2^5 has range 0 to 31. >>> >>>> Max value of multiplication: 31 * 31 = 961 >>> >>>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: >>>> 2^10 - 1 = 1023 >>> >>>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>> >>> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. >> >> Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 >> bits for signed either. >> >> (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign >> bit at the output too. >> >> Or I'm missing your point? > > Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I > remember that this is the defining case for multiplication and requires > the full 2n bits... just as Rob said. If your data is for any reason > limited to ±(2^(n-1)-1) then one less bit is needed for the product. > Such is the case if an unsigned value was negated to produce the signed > value. > > I don't get his product notation becoming S2.8 rather than S1.9 though. > If the range of the result is [-1,1) there is still only one bit left > of the binary point, or am I wrong about that too, lol? Nope. The LSB in S1.4 was 2^-4 = 1/16. The LSB of the product, therefore is 1/256, 2^-8. Likewise, as you pointed out, the representation of +1 is 01.0000_0000b, i.e. 2^0. The representation of -1 therefore is 11.0000_0000b, -(2^1) + 2^0 = -2 + 1 = -1. The total representable range is [-2,2), but if you get there from the product of two S1.4 numbers on [-1,1) then you've got a number that is S2.8 [-1,1]. So the number is, by virtue of what it actually represents, not capable of using the entire range representable by its format. That S/U notation, and actually carrying along explicit ranging information, is why I can write fixed-point code that is right the first time these days. God knows I didn't get any smarter, I just started using a notation that is so explicit and bloody stupid that it shouts your mistakes from the rafters. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.129.88.87 with SMTP id m84mr4997816ywb.0.1445382813429; Tue, 20 Oct 2015 16:13:33 -0700 (PDT) X-Received: by 10.50.85.47 with SMTP id e15mr137459igz.9.1445382813397; Tue, 20 Oct 2015 16:13:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c107no447168qgd.1!news-out.google.com!n2ni36247igy.0!nntp.google.com!kq10no20480223igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 16:13:32 -0700 (PDT) In-Reply-To: <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> <30f97eee-4d84-42e5-9c79-b57536ccb50c@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: C code for conversion instead of programming. From: michael6866 Injection-Date: Tue, 20 Oct 2015 23:13:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8612 On Monday, October 19, 2015 at 11:52:30 PM UTC-4, Rajeev Varshney wrote: > Hello, >=20 >=20 > Thanks you for your valueable suggestion..... > After reading your responses, I have question that why people ask for c t= o hdl. > Also last year I came to know some technology specialist that=20 > upcoming hardware will be based on clanguages. > I s it related to something 7Series FPGA. It's not necessary in C. Some other high level programming languages are po= ssible as well, for example SystemC (there is also a standardization effort= on the synthesizable subset going on). The reason to model in such kind of= languages is mainly 1) speed up simulation 2) start SoC verification early= . Now that you have the verified C model ready, it's normal to think why no= t convert it to HDL automatically.=20 High level synthesis is a trend. Eventually it will arrive just like how de= sign methodology evolved from gate level to RTL. Many large companies are t= rying that and some of them been benefited from HLS already (excuse me but = I cannot expose the names of the customers). If you're looking for more inf= ormation, you can keep an eye on 1) Stratus from Cadence, mainly focused on= SystemC 2) Catapult C from Calypto (now acquired by Mentor) By the way, the opposite direction also exists - that is to convert a synth= esizable HDL to C/C++ automatically. In that case the goal is merely speedu= p. One such example is ARM Cortex cores. They provide you cycle-accurate C+= + models which are derived from RTL (the process is largely done by compile= r tools from Synopsys) Michael From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.182.196.34 with SMTP id ij2mr887598obc.24.1445395132111; Tue, 20 Oct 2015 19:38:52 -0700 (PDT) X-Received: by 10.50.43.229 with SMTP id z5mr163353igl.8.1445395132092; Tue, 20 Oct 2015 19:38:52 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24317610igb.0!news-out.google.com!n2ni36406igy.0!nntp.google.com!kq10no24317600igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 19:38:51 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Question about std_logic variable compared with '0' From: fl Injection-Date: Wed, 21 Oct 2015 02:38:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8613 Hi, I never took a VHDL class, although I read a book for some time. Recently I have some progress. Some conceptual questions pop up occasionally. I find understanding these questions help me writing good code. 'in2sel' is the entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean? i.e. the comparing is on what category? Is it an integer subtype? Or something else? I don't find the solution after a web search. Hopefully someone gives me an interpretation or hint. Thanks, in2sel : IN std_logic; in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why does Modelsim insist so many bits for a multiplication? Date: Wed, 21 Oct 2015 00:24:40 -0400 Organization: A noiseless patient Spider Lines: 70 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Wed, 21 Oct 2015 04:22:32 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="28271"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1993XNavo394jUCumdcss8w" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:ftjTYw6iNriSS1LwO4VRRoegYcg= Xref: mx02.eternal-september.org comp.lang.vhdl:8614 On 10/20/2015 4:46 PM, Rob Gaddi wrote: > On Tue, 20 Oct 2015 16:20:40 -0400, rickman wrote: > >> On 10/20/2015 12:58 PM, Mark Curry wrote: >>> In article , >>> glen herrmannsfeldt wrote: >>>> Tim McBrayer wrote: >>>>> On 10/20/2015 10:12 AM, fl wrote: >>>> >>>>>> I know if 5-bit multiplies 5-bit, the result will be 9-bit, no >>>>>> matter >>>>>> unsigned or signed number. When I try it with Modelsim, I find >>>>>> that it insists the result be 10-bit. Otherwise, it issues a >>>>>> warning. >>>> >>>>> Your 9-bit product assumption is the problem; 9 bits are not enough >>>>> to store 5 bits * 5 bits at full precision. It requires 10 bits. >>>> >>>>> Take the simplest example, multiplying two unsigned 5-bit numbers. >>>>> 2^5 has range 0 to 31. >>>> >>>>> Max value of multiplication: 31 * 31 = 961 >>>> >>>>> Max unsigned 9-bit value: 2^9 - 1 = 511 Max unsigned 10-bit value: >>>>> 2^10 - 1 = 1023 >>>> >>>>> Thus, 5 bits * 5 bits requires 10 bits for a full precision result. >>>> >>>> But for signed, 15*15 fits in 9 bits, and (-16)*(-16) also fits. >>> >>> Glen - huh? The (max negative) * (max negative) case does NOT fit in 9 >>> bits for signed either. >>> >>> (-16)*(-16) = 256 = 'b01_0000_0000 you need 10 bits - you need the sign >>> bit at the output too. >>> >>> Or I'm missing your point? >> >> Opps, I was thinking 1_0000_0000 would be a negative value, duh. Now I >> remember that this is the defining case for multiplication and requires >> the full 2n bits... just as Rob said. If your data is for any reason >> limited to ±(2^(n-1)-1) then one less bit is needed for the product. >> Such is the case if an unsigned value was negated to produce the signed >> value. >> >> I don't get his product notation becoming S2.8 rather than S1.9 though. >> If the range of the result is [-1,1) there is still only one bit left >> of the binary point, or am I wrong about that too, lol? > > Nope. The LSB in S1.4 was 2^-4 = 1/16. The LSB of the product, > therefore is 1/256, 2^-8. Likewise, as you pointed out, the > representation of +1 is 01.0000_0000b, i.e. 2^0. The representation of > -1 therefore is 11.0000_0000b, -(2^1) + 2^0 = -2 + 1 = -1. The total > representable range is [-2,2), but if you get there from the product of > two S1.4 numbers on [-1,1) then you've got a number that is S2.8 [-1,1]. > So the number is, by virtue of what it actually represents, not capable > of using the entire range representable by its format. > > That S/U notation, and actually carrying along explicit ranging > information, is why I can write fixed-point code that is right the first > time these days. God knows I didn't get any smarter, I just started > using a notation that is so explicit and bloody stupid that it shouts > your mistakes from the rafters. Ok, thanks. This was a useful example. I guess I haven't actually used this sort of calculation before. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: C code for conversion instead of programming. Date: Wed, 21 Oct 2015 00:30:08 -0400 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <80d122c6-285b-40dd-a682-2f98f4afbd04@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 04:28:01 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="29526"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wv9R3YkRCW0x09AUI7r99" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:s5ggzZ9+B3KmVGM2j2EKI9qtXb4= Xref: mx02.eternal-september.org comp.lang.vhdl:8615 On 10/20/2015 5:49 AM, glen herrmannsfeldt wrote: > rickman wrote: > > (snip on C as an HDL) > (then I wrote) > >>> I have thought that a tool that would compile a program to some >>> intermediate code, and also generate logic for an efficient >>> interpreter of that code, could be useful. > >>> That is, a soft processor optimized for the code at hand. > >> Perhaps, but how much better than just buying an already optimized hard >> IP processor like an ARM or an x86 of some flavor? Sure soft processors >> have uses, but the work involved in designing such a tool to >> automatically produce machine code and a processor from C code would be >> a lot more than can be justified I'd bet, but who knows? It may just be >> the lack of a perceived market. Maybe this would be a good university >> research project? > > I haven't looked in detail how the usual soft processors work. > > It wouldn't seem so hard to compile the C, see which instructions > the code actually used, then remove instructions from the soft > processor that weren't used. That should be much less work than > the synthesis tools themselves. Removing instructions from a processor usually doesn't accomplish much unless it is a big ugly brute maybe. Most of the logic in soft processors is data path and instruction fetch rather than instruction decode. So unless removing instructions allow you to reduce some part of the data path it doesn't accomplish a lot. At least that has been my experience. But then most of my work has been with processors of my own design with some examination of a few RISC CPUs like MicroBlaze and LatticeMico32. My designs were all stack processors which were intended to minimize the logic used as a primary goal. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.129.134.129 with SMTP id w123mr5987618ywf.17.1445404922760; Tue, 20 Oct 2015 22:22:02 -0700 (PDT) X-Received: by 10.50.124.69 with SMTP id mg5mr422188igb.10.1445404922724; Tue, 20 Oct 2015 22:22:02 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!kq10no20534681igb.0!news-out.google.com!z4ni27311ign.0!nntp.google.com!kq10no24380093igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 20 Oct 2015 22:22:02 -0700 (PDT) In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.23.60.4; posting-account=KXGbogkAAACb7NKQto59OFEcUM-ADB_5 NNTP-Posting-Host: 185.23.60.4 References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Could you explain this 'assert' description? From: bknpk@hotmail.com Injection-Date: Wed, 21 Oct 2015 05:22:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 2472 X-Received-Body-CRC: 3257491668 Xref: mx02.eternal-september.org comp.lang.vhdl:8616 On Wednesday, September 30, 2015 at 3:20:42 AM UTC+3, fl wrote: > Hi, > > I learn 'assert' on this link: > > > > http://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > > > For this example line: > > assert not OVERFLOW) report "Accumulator overflowed" severity failure; > > > "If the message clause is ommited" means remove "report "Accumulator > overflowed" severity failure;"? > > > What is your opinion on this? > > Thanks, The assert statement of VHDL, can be used for simulation stop. This can be in a simple case like just a normal simulation end or a fatal error detection, by the verification test-bench. 2.If the simulation is let run after a fatal error occurs, the debug time may become longer in order to isolate the exact point of failure. While this is obvious, in some cases this rule is ignored. Typical example follows. 3.The simulation stop is done using the VHDL assert statement. examples are at http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_stop_on_error.html http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_test_ctrl_process.html From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about std_logic variable compared with '0' Date: Wed, 21 Oct 2015 01:26:37 -0400 Organization: A noiseless patient Spider Lines: 47 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 05:24:30 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="5169"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18SnYwtLG6aOp8Tt7Ev2E1P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:Jmdq6mh4Wk1KbOZilcXnKCEna3s= Xref: mx02.eternal-september.org comp.lang.vhdl:8617 On 10/20/2015 10:38 PM, fl wrote: > Hi, > > I never took a VHDL class, although I read a book for some time. Recently I > have some progress. Some conceptual questions pop up occasionally. I find > understanding these questions help me writing good code. 'in2sel' is the > entity input port. I am curious about ( in2sel > '0' ). I guess in2sel should > be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-determined > order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' mean? > i.e. the comparing is on what category? Is it an integer subtype? Or something > else? I don't find the solution after a web search. Hopefully someone gives > me an interpretation or hint. > > > Thanks, > > > in2sel : IN std_logic; > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; In VHDL the operator > is an arithmetic comparison. This sort of comparison is not defined for std_logic that I am aware of. If you mean comparisons such as arithmetic > for std_logic_vector (which would be "000" rather than '0') there are definitions of the > operation on this data type. You can assign the std_logic_vector to a signed or unsigned type defined in the NUMERIC_STD library. This will let you do the arithmetic comparison on the signed or unsigned value. Or you can use the new VHDL-2008 standard arithmetic package, IEEE.Numeric_Std_Unsigned. I have not used it myself, but I believe it defines unsigned arithmetic for std_logic_vector types. I see some mention of a similar library, IEEE.Numeric_Std_signed, but some pages say there is only the unsigned library. If you really want the std_logic type, you can convert the many values of std_logic to a 1 or 0 using to_01(). Then you can just use the equality comparison which *is* defined for std_logic as the returned value will be either a 1 or a 0 always. But this still may not be what you want if the input is a 'W', 'X', 'Z', '-' or 'U'. You can also define your own comparison or conversion operators. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.68.131.193 with SMTP id oo1mr6721470pbb.6.1445417694602; Wed, 21 Oct 2015 01:54:54 -0700 (PDT) X-Received: by 10.50.103.69 with SMTP id fu5mr187274igb.5.1445417694567; Wed, 21 Oct 2015 01:54:54 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no20599493igb.0!news-out.google.com!z4ni27442ign.0!nntp.google.com!kq10no20599489igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 01:54:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question about std_logic variable compared with '0' From: Thomas Stanka Injection-Date: Wed, 21 Oct 2015 08:54:54 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8618 Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. TYPE color IS (red, green, yellow); -- yellow>green>red There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.68.138.233 with SMTP id qt9mr6958711pbb.11.1445423236833; Wed, 21 Oct 2015 03:27:16 -0700 (PDT) X-Received: by 10.50.6.40 with SMTP id x8mr109590igx.0.1445423236802; Wed, 21 Oct 2015 03:27:16 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no24559125igb.0!news-out.google.com!z4ni27526ign.0!nntp.google.com!kq10no24559114igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 03:27:16 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.100.117.144; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo NNTP-Posting-Host: 50.100.117.144 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Question about std_logic variable compared with '0' From: fl Injection-Date: Wed, 21 Oct 2015 10:27:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8619 On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: > Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: > > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; > > Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. > > In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. > > TYPE color IS (red, green, yellow); -- yellow>green>red > > There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. The code in my original post is generated from Matlab. I rewrite it in a simplest VHDL module using it with a test bench. There is no compiling error either. This kind of module generally is inside of (called from) other module. With your replies, the comparison is on the enumerated type of std_logic, which is in the IEEE package. Can we think it has been determined i.e. a consistent result will always be got? Use to_01() should work, though a little extra code. It should have a simple way for such a situation. From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.66.144.164 with SMTP id sn4mr7905706pab.9.1445432648634; Wed, 21 Oct 2015 06:04:08 -0700 (PDT) X-Received: by 10.50.61.132 with SMTP id p4mr215506igr.1.1445432648599; Wed, 21 Oct 2015 06:04:08 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no20709110igb.0!news-out.google.com!z4ni27629ign.0!nntp.google.com!kq10no24663084igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 06:04:07 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 70.34.173.3 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <51ff883e-95c2-4ce7-8074-3233c1b4a648@googlegroups.com> Subject: Re: Question about std_logic variable compared with '0' From: KJ Injection-Date: Wed, 21 Oct 2015 13:04:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8620 On Tuesday, October 20, 2015 at 10:38:57 PM UTC-4, fl wrote: > 'in2sel' is the > entity input port. I am curious about ( in2sel > '0' ). I guess in2sel sh= ould > be resolved to '1' or '0' (Otherwise 'X' 'Z' 'H' etc. have some pre-deter= mined > order/priorities). Assume in2sel is resolved to '1'. What does '1' > '0' = mean? > i.e. the comparing is on what category? Is it an integer subtype? Or some= thing > else? I don't find the solution after a web search. Hopefully someone giv= es=20 > me an interpretation or hint. >=20 Since insel is type std_logic and std_logic is an enumeration type, the int= erpretation of > or < is whether the value is to the left or to the right = of the other value in the definition of the enumeration type list. The def= inition of std_ulogic is type STD_ULOGIC is ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance =20 'W', -- Weak Unknown 'L', -- Weak 0 =20 'H', -- Weak 1 =20 '-' -- Don't care ); Type std_logic is just the resolved subtype form of std_ulogic, so it will = have the same values as std_ulogic. The ordering of the literals that make= up the enumeration is from left to right so 'U' is to the left of 'X' (as = an example). An enumeration is considered 'greater' if it is to the right = of another so 'X' is considered to be greater than 'U' so the expression 'X= ' > 'U' returns the boolean value of True. Similarly, since '1' is to the = right of '0', an expression that boils down to '1' > '0' would result in th= e boolean value of True. In your case, you have "insel > '0'", so the foll= owing values for insel will all be true: '1', 'Z', 'W', 'L', 'H', '-'. There is no numeric interpretation of > or < going on here because the comp= arison is not between anything that has a numeric value. VHDL allows for e= numeration types to be defined and there are good use cases for where you w= ould like to evaluate to see if some signal is > or < some other signal or = constant that is also the same enumeration type. The code generated by Mat= lab would likely not be considered one of those 'good' use cases but rememb= er the Matlab program itself is a program, not a person. Probably a more c= learly written way to express that line of code would be the following. in2_im0 <=3D dmut_im WHEN ( in2sel =3D '1' ) ELSE dim_signed; Here the =3D is used rather than > and now suddenly there should be no conf= usion and yet =3D, > and < are all very familiar comparison operators. The= difference here is while it is easy to understand that =3D simply means th= e same, unless you what an enumeration type is, there may be confusion abou= t > or <. But that confusion probably does not exist if you ask yourself t= o compare strings so that they can be sorted (i.e. "def" > "abc"). Here yo= u're comparing strings and the 'greater' string would be sorted after the o= ther one. Now consider that strings are simply arrays of characters and VH= DL defines characters as an enumeration in package standard. type CHARACTER is ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,=20 BS, HT, LF, VT, FF, CR, SO, SI,=20 DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,=20 CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,=20 ... etc ... Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.182.215.226 with SMTP id ol2mr7804605obc.11.1445433055563; Wed, 21 Oct 2015 06:10:55 -0700 (PDT) X-Received: by 10.50.50.179 with SMTP id d19mr215486igo.7.1445433055543; Wed, 21 Oct 2015 06:10:55 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!news.ripco.com!news.glorb.com!kq10no24666377igb.0!news-out.google.com!z4ni27629ign.0!nntp.google.com!kq10no24666370igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 21 Oct 2015 06:10:55 -0700 (PDT) In-Reply-To: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=50.77.206.249; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 50.77.206.249 References: <0d729f2b-34c1-4d30-aebe-fac262284edb@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <27434335-4a96-473b-82e3-35cfc43fd58f@googlegroups.com> Subject: Re: Could you explain this 'assert' description? From: KJ Injection-Date: Wed, 21 Oct 2015 13:10:55 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8621 On Tuesday, September 29, 2015 at 8:20:42 PM UTC-4, fl wrote: > Hi, > > > I don't understand what this passage talks about: > > "If the message clause is ommited, a default message is output. The severity > level and the name of the design unit containing the relevant assert > statement may also be output" > The line of code in file D:/Projects/Test.vhd assert 1 < 0 severity ERROR; Will produce the following output in Modelsim # ** Error: Assertion violation. # Time: 0 ns Iteration: 0 Process: /tb_ulpi_link/line__252 File: D:/Projects/Test.vhd Kevin From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Why VHDL? Date: Wed, 21 Oct 2015 16:59:11 +0300 Organization: An impatient and LOUD arachnid Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="afd436d54299ec52d915a4a2551e1d6f"; logging-data="9936"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Ugod0itX+JJIu8yQl0G1y" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:lMJFGzZ8392+kOHb2I+qHm7wrIk= sha1:pQ3SxJFecdEAXJFNM8JSViIIMgA= Xref: mx02.eternal-september.org comp.lang.vhdl:8622 comp.lang.verilog:4087 rickman writes: > I'm curious who here has learned both and why? Which do you prefer > and why? I learned some VHDL in school then went to work at telecoms company. There the old school POTS and related stuff was done in Verilog and the new fangled cellular radio stuff was in VHDL. I don't really know why. I worked with the POTS stuff first and used mostly Verilog and then later moved to the radio stuff but as the project manager didn't want to learn VHDL everyone in my team used Verilog. By that time simulation and synthesis tools didn't care so it was no problem to do mixed language. After that job, which ended in 2002, it's been pretty exlusively VHDL for me. European thing I suppose. One IP company I consulted at even went so far as to have us write code in VHDL which they would then put through a Verilog converter before shipping to customers in Asia or somewhere who wanted Verilog. I don't really have a preference between either but... As a fresh graduate I liked the simplicity and freedom of Verilog (and C) and really didn't like the bewildering mess of types in VHDL and the required type conversions. Or the seeming need to write things in triplicate (entity, component, instance). Thankfully there's direct instantiation which eliminates the need for components and then the Emacs VHDL mode makes instantiating and declaring signals a snap. As I've gotten older I've come to like Python quite a lot and these days I really like strong typing and explicit type conversions. I also maintain some old code and now scoff at the use of std_arith to do arithmetic on std_logic_vectors. Now the way of thinking that goes like "anything, even binary literals to avoid having to call type conversions" just seems stupid. Then again, readability is in the eye of the beholder. I was just reminded of this the other week... Well, the state of support for VHDL 2008 is a constant annoyance. I work on Altera parts without access to a third party synthesis tool and Quartus hasn't progressed at all with VHDL 2008 support in the last five years or so while Modelsim and Questa (which I do have access to) have. I think Xilinx Vivado is about the same? So the smaller guys (Lattice and Microsemi) are maybe offering better tools now since they bundle Synplify. If they still do, haven't checked. From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question about std_logic variable compared with '0' Date: Wed, 21 Oct 2015 16:10:29 -0400 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 21 Oct 2015 20:08:22 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="6214"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18/7UjrTW5r5w1jqS9KSVmS" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:/xPxVNNkVTKomCxa7NyNKC3P1hM= Xref: mx02.eternal-september.org comp.lang.vhdl:8623 On 10/21/2015 6:27 AM, fl wrote: > On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: >> Am Mittwoch, 21. Oktober 2015 04:38:57 UTC+2 schrieb fl: >> >>> in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; >> >> Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. >> >> In fact std_ulogic is an enumerated type and has of course a order defined by the order you write it in the type definition. >> >> TYPE color IS (red, green, yellow); -- yellow>green>red >> >> There is also an order within std_ulogic. But I think is is not '1' > 'H' > '0' > 'L' and therefore you might experience some strange effects when simulating that line above with std_ulogic. > > The code in my original post is generated from Matlab. I rewrite it in a > simplest VHDL module using it with a test bench. There is no compiling error > either. This kind of module generally is inside of (called from) other > module. With your replies, the comparison is on the enumerated type of > std_logic, which is in the IEEE package. Can we think it has been determined > i.e. a consistent result will always be got? > > Use to_01() should work, though a little extra code. > > It should have a simple way for such a situation. If you are trying to work with synthesized code from Matlab, why do you care about the contents as long as it works? Or are you just trying to learn more about VHDL by studying this example (if a poor one). Clearly the code in2sel > '0' will work if they never allow the value of in2sel to be anything other than '1' or '0'. Even so, it is awkward code. It should have just been ins2sel = '1' instead. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.129.154.205 with SMTP id r196mr8557315ywg.48.1445500910950; Thu, 22 Oct 2015 01:01:50 -0700 (PDT) X-Received: by 10.50.33.73 with SMTP id p9mr249268igi.4.1445500910919; Thu, 22 Oct 2015 01:01:50 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!m48no789645qgd.0!news-out.google.com!z4ni28421ign.0!nntp.google.com!kq10no21087416igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 22 Oct 2015 01:01:50 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <080b9955-2b8b-45bd-b9b6-0417f400dfab@googlegroups.com> Subject: Re: Question about std_logic variable compared with '0' From: Thomas Stanka Injection-Date: Thu, 22 Oct 2015 08:01:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8624 Am Mittwoch, 21. Oktober 2015 12:27:20 UTC+2 schrieb fl: > On Wednesday, October 21, 2015 at 4:54:58 AM UTC-4, Thomas Stanka wrote: > > > in2_im0 <= dmut_im WHEN ( in2sel > '0' ) ELSE dim_signed; > > > > Writing this line is for me a clear selfnomination for the "Kick-me-my-name-is-McFly" award of today. > > The code in my original post is generated from Matlab. So kick it, its name is Matlab :). This code will most likely work well with some preconditions, but will not have the intended behavior when applying full range of std_logic => bad reuseability. Maybe Matlab will claim, that reuseability is not their business. As Rickman and KJ allready pointed out, the code would be functional and far better readable with using "=" for single bit compare function. On the plus side, you learned some new aspect of VHDL with this code line. bye Thomas From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 23 Oct 2015 02:48:36 -0500 From: aadi Subject: Re: creating program Newsgroups: comp.lang.vhdl X-UserIpAddress: X-InternalId: ecfba588-526b-4469-aa16-60624fb6f261 References: Message-ID: Date: Fri, 23 Oct 2015 02:48:36 -0500 Lines: 82 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-njYFrX3oTVC7vlyS1mFqTUhQDaX8PBpK5VH1MJhq0pf1C0ymzVi+UbdbWe15LOZIHdkxkD6XsoIvEKp!DRywJylL5o3xpKRTNk6x9Yup1lCKjjt7qlwSKqsBMgQYPkND4kQwYefqwr/Y/Ha3WMZLT1ge0m9d!7Gc= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4181 Xref: mx02.eternal-september.org comp.lang.vhdl:8625 Thanks Kevin for your comment. Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop. key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 10 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 11 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 12 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 13 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 14 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; when 15 => if (decipher = '1') then key_l(0 to 27) <= key_l(27) & key_l(0 to 26); key_r(0 to 27) <= key_r(27) & key_r(0 to 26); else key_l(0 to 27) <= key_l(1 to 27) & key_l(0); key_r(0 to 27) <= key_r(1 to 27) & key_r(0); end if; when others => end case; end if; end process Key; cntrl: process (clk, dirtn) variable count : integer range 0 to 15:=0; begin if (rising_edge(clk) and clk='1') then if decipher = '0' then if (dirtn='1') then count:= count+ 1; counter<=count; else if decipher = '1' then count:= count- 1; counter<=count; end if; end if; end if; end if; end process cntrl; end behavioural; From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Re: Why VHDL? Date: Tue, 27 Oct 2015 17:06:17 -0400 Organization: A noiseless patient Spider Lines: 89 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 27 Oct 2015 21:04:09 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="3887"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX190ROz50XWy0HBSSge8iPui" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:GHQ3JTq/8cYfKuogQvu0Vg3/aCI= Xref: mx02.eternal-september.org comp.lang.verilog:4099 comp.lang.vhdl:8626 On 10/27/2015 3:21 PM, Mark Curry wrote: > In article , rickman wrote: >> On 10/27/2015 12:26 PM, Mark Curry wrote: >>> In article , Anssi Saari wrote: >>>> Kevin Neilson writes: >>>> >>>>> I wish somebody would write a comprehensive guide to conversions in >>>>> VHDL. I had one once but lost it. >>>> >>>> There's the 2003 PDF by Jim Lewis of Synthworks titled "VHDL Math Tricks >>>> of the Trade" >>>> (http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf) which >>>> is pretty good. It covers both the old std_arith stuff and current >>>> numeric_std stuff. >>>> >>>> For a quick reference, there're lots of images floating around that >>>> cover the common conversions. Like this one: >>>> http://www.bitweenie.com/wp-content/uploads/2013/02/vhdl-type-conversions.png >>>> >>>>> Every time I write something in that infernal language I can't >>>>> remember how to convert unsigned into integer or whatever. Sometimes >>>>> it takes a double conversion. >>>> >>>> I dunno, it seems to me to_integer and to_unsigned are pretty easy to >>>> remember. >>> >>> Anssi - Thanks very much for the links. >>> >>> I think todays designers must be able to work with either VHDL or Verilog. >>> These language wars are over. >>> > > >> In my "book" anyone who discusses std_logic_arith is so far out of date >> they don't deserve serious respect. There literally is *no* reason to >> learn anything about std_logic_arith and its kin unless you are trying >> to maintain code so old the processes used to implement it are no longer >> around. >> >> The reasons to avoid std_logic_arith are many and well known. This is > > Noted - but as a verilog user, I don't know what those reasons are. > I do trust you, and other VHDL experts and will certainly follow > the suggestions. Like I said, I remembered there was a > strong suggestion to NOT use one of them. I'll try and > cement that in my head "don't use std_logic_arith"... To be honest, it has been so long that I don't remember all of the reasons. One that I recall is that with these packages you can't use signed and unsigned at the same time. These packages don't define new types, they define operators for SLV to implement signed or unsigned arithmetic. Adding both signed and unsigned packages gives you multiple operators for the same data types... which do you get? I know there are other issues with them as well, so they are best forgotten. In addition to numeric_std, there are new packages for signed and unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned). These new packages will have the same issue of not working together since they define the same operator on the same types, but otherwise will work ok. I just use signed and unsigned types from the std_numeric library. Life is good. >> the sort of info I'd like to have on Verilog. I understand there are >> default rules of how many thing operate in Verilog, but they are hard to >> find out about. That is what I would like in a Verilog book. > > As a verilog user, it's all obvious to me :) > Actually, if I had a suggestion, it just be Cliff's oldy but goody: > http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf > > It's still relevant today, IMHO. Not sure if this is what you're > looking for, but it's golden. > > Cliff's got many other great papers up on his website. I've seen some of this before. I was mostly referring to the issues of arithmetic. I believe Verilog has defaults for how the various details of bit growth etc are handled. If you aren't aware of what is happening you can have invisible trouble. In VHDL you have *very* visible trouble for nearly anything you do wrong. lol Crossposting to the VHDL group since this is as much about that as Verilog. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.107.47.219 with SMTP id v88mr29027816iov.25.1446023441540; Wed, 28 Oct 2015 02:10:41 -0700 (PDT) X-Received: by 10.50.8.68 with SMTP id p4mr35001iga.8.1446023441524; Wed, 28 Oct 2015 02:10:41 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!kq10no31135618igb.0!news-out.google.com!fs1ni785igb.0!nntp.google.com!kq10no31135615igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 02:10:41 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.156.155.14; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP NNTP-Posting-Host: 62.156.155.14 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Subject: Re: Why VHDL? From: Thomas Stanka Injection-Date: Wed, 28 Oct 2015 09:10:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8627 Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman: > On 10/27/2015 3:21 PM, Mark Curry wrote: > To be honest, it has been so long that I don't remember all of the=20 > reasons. =20 [..] > I know there are other issues with them as well, so they are best=20 > forgotten. The major issue with std_logic_arith and similar (std_logic_unsigned,...) i= s that they are NOT standardized. They are tool dependend (original from Sy= nopsys) and from LRM point of view illegal extensions to libray IEEE, as th= is library shall contain only standarized packages. If simulation and synthesis result for these packages differ, you have nobo= dy to complain about (beside the code autor, who dares to use non standard)= . > In addition to numeric_std, there are new packages for signed and=20 > unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned).=20 > These new packages will have the same issue of not working together=20 > since they define the same operator on the same types, but otherwise=20 > will work ok. I just use signed and unsigned types from the std_numeric= =20 > library. Life is good. Std_logic_unsigned and std_logic_signed are not "new packages" compared to = numeric_std, they are extensions from Synopsys for the std_logic_arith and= usually used in combination with arith with similar issues than arith alon= e.=20 regards, Thomas From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.31.148.206 with SMTP id w197mr38986731vkd.9.1446033993342; Wed, 28 Oct 2015 05:06:33 -0700 (PDT) X-Received: by 10.50.142.66 with SMTP id ru2mr57851igb.3.1446033993268; Wed, 28 Oct 2015 05:06:33 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!c107no2912759qgd.1!news-out.google.com!fs1ni883igb.0!nntp.google.com!i2no22141igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 05:06:32 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 80.113.175.178 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Wed, 28 Oct 2015 12:06:33 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1539 X-Received-Body-CRC: 3053702156 Xref: mx02.eternal-september.org comp.lang.vhdl:8628 Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: > i have learned every aspect of VHDL but i still can't exersise it to make complex program. It's VHDL, not C or Java. VHDL is a description, not a program. > i need a code for data encryption standard and also for key generation. but i can't get a single way to do so What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores. Igmar From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.13.248.68 with SMTP id i65mr25908346ywf.39.1446042250261; Wed, 28 Oct 2015 07:24:10 -0700 (PDT) X-Received: by 10.50.57.17 with SMTP id e17mr86189igq.2.1446042250178; Wed, 28 Oct 2015 07:24:10 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!us.feeder.erje.net!news.ripco.com!news.glorb.com!c107no2937693qgd.1!news-out.google.com!fs1ni1009igb.0!nntp.google.com!i2no83624igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 28 Oct 2015 07:24:09 -0700 (PDT) In-Reply-To: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.4.178.90; posting-account=kidwfQoAAAAfI20wQGXIy9JZVTNSnVqm NNTP-Posting-Host: 108.4.178.90 References: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <50c49191-139f-4b9f-96c4-6b429235ee1b@googlegroups.com> Subject: Re: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" From: elkniwt@gmail.com Injection-Date: Wed, 28 Oct 2015 14:24:10 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8629 On Friday, September 13, 2013 at 11:38:51 AM UTC-4, Christiano wrote: > If anyone has had this problem, just do this: > ghdl -a --ieee=synopsys x.vhd Thanks, this helped me out with some source over which I have no control. From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Wed, 28 Oct 2015 12:29:32 -0400 Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Oct 2015 16:27:23 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7631"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/lRE6lXqcLIEVE8ZHmMsIu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Cancel-Lock: sha1:dAhJj+sFj+f17lDvKvyzeS/aO6U= Xref: mx02.eternal-september.org comp.lang.vhdl:8630 On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: >> i have learned every aspect of VHDL but i still can't exersise it to make complex program. > > It's VHDL, not C or Java. VHDL is a description, not a program. That's not very fair. VHDL is used to describe hardware, but it is a perfectly good programming language too. That is how we use it for test benches. >> i need a code for data encryption standard and also for key generation. but i can't get a single way to do so > > What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores. > > > Igmar > -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: [GHDL] Solution to --> primary unit "std_logic_arith" not found in library "ieee" Date: Wed, 28 Oct 2015 12:33:38 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 28 Oct 2015 16:31:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="10154"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9Sb98L3oEX4ARymWM3HnD" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <227dcde5-9d5e-46bd-bce4-826f35c0dcf1@googlegroups.com> Cancel-Lock: sha1:nY6lx7dafpoaHIVF7BP6M97nSNk= Xref: mx02.eternal-september.org comp.lang.vhdl:8631 On 9/13/2013 11:38 AM, Christiano wrote: > If anyone has had this problem, just do this: > ghdl -a --ieee=synopsys x.vhd Better yet, use numeric_std rather than std_logic_arith. I did a little digging and found that because std_logic_arith was not a standard, each vendor produced their own, different, version. That is reason enough to not use it. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Wed, 28 Oct 2015 22:39:51 +0000 (UTC) Organization: Aioe.org NNTP Server Lines: 28 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> NNTP-Posting-Host: Uvpb42Ir6g+92oBc7q8CMg.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) X-Notice: Filtered by postfilter v. 0.8.2 Xref: mx02.eternal-september.org comp.lang.vhdl:8632 rickman wrote: > On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: (snip on VHDL and programs) >> It's VHDL, not C or Java. VHDL is a description, not a program. > That's not very fair. VHDL is used to describe hardware, but it is a > perfectly good programming language too. That is how we use it for test > benches. I think I also don't like the use of the word 'program' even in the case of test benches. To me, program has too much implication of sequential execution (even in the case of parallel programming) that I think some other word should be used. I might use design, which I think works in the case of hardware and test benches, which both need to be designed, if not described. Though test benches could also be described, even if they aren't hardware. (But the idea of a test bench comes from the days when they were hardware, even furniture.) -- glen From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why VHDL? Date: Thu, 29 Oct 2015 01:26:29 -0400 Organization: A noiseless patient Spider Lines: 39 Message-ID: References: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Oct 2015 05:24:19 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="31030"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GNpPLg9JghNum8m3dJUqW" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <9febdcc3-0775-43ab-8f40-8f84669c398e@googlegroups.com> Cancel-Lock: sha1:IpxXgbJ55r22Xl+PNxZpPI9Nxms= Xref: mx02.eternal-september.org comp.lang.vhdl:8633 On 10/28/2015 5:10 AM, Thomas Stanka wrote: > Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman: >> On 10/27/2015 3:21 PM, Mark Curry wrote: To be honest, it has been >> so long that I don't remember all of the reasons. > [..] >> I know there are other issues with them as well, so they are best >> forgotten. > > The major issue with std_logic_arith and similar > (std_logic_unsigned,...) is that they are NOT standardized. They are > tool dependend (original from Synopsys) and from LRM point of view > illegal extensions to libray IEEE, as this library shall contain only > standarized packages. If simulation and synthesis result for these > packages differ, you have nobody to complain about (beside the code > autor, who dares to use non standard). > >> In addition to numeric_std, there are new packages for signed and >> unsigned arithmetic on SLV, (std_logic_signed and >> std_logic_unsigned). These new packages will have the same issue of >> not working together since they define the same operator on the >> same types, but otherwise will work ok. I just use signed and >> unsigned types from the std_numeric library. Life is good. > > Std_logic_unsigned and std_logic_signed are not "new packages" > compared to numeric_std, they are extensions from Synopsys for the > std_logic_arith and usually used in combination with arith with > similar issues than arith alone. Yes, sorry, I got my names mixed up. I meant to say "numeric_std_unsigned and numeric_std_signed". I'm actually not sure how widely these are supported. I only find 1600 hits on a google search for numeric_std_unsigned and only about 100 for numeric_std_signed. But I find them both mentioned as part of VHDL-2008 at the Doulos site, so I figure they know what they are talking about... maybe. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.50.134.199 with SMTP id pm7mr6805687igb.0.1446121754704; Thu, 29 Oct 2015 05:29:14 -0700 (PDT) X-Received: by 10.50.67.179 with SMTP id o19mr58721igt.3.1446121754648; Thu, 29 Oct 2015 05:29:14 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no563895igv.0!news-out.google.com!z4ni39791ign.0!nntp.google.com!i2no389869igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 29 Oct 2015 05:29:14 -0700 (PDT) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=39.32.8.43; posting-account=272ktwoAAAA5_lGBEoh_tKUi3Dy5L9Ix NNTP-Posting-Host: 39.32.8.43 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Verilog programing query From: mahmedqureshi.maq@gmail.com Injection-Date: Thu, 29 Oct 2015 12:29:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8634 I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions. However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem? Thanks From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Verilog programing query Date: Thu, 29 Oct 2015 12:36:16 -0400 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 29 Oct 2015 16:34:05 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="7839"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/mgp78DxDLMas7JSF8kADw" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:7+VLVomG7u3jZPtHDQ31HzjGEzE= Xref: mx02.eternal-september.org comp.lang.vhdl:8635 On 10/29/2015 8:29 AM, mahmedqureshi.maq@gmail.com wrote: > I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions. > However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem? > Thanks I'm not sure why you are asking how to write Verilog code in a VHDL group. But to answer your question I suspect your professor wants you to use arrays to implement the register file. Then you simply need to initialize them to the instruction values. -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.107.136.19 with SMTP id k19mr11661951iod.5.1446297413849; Sat, 31 Oct 2015 06:16:53 -0700 (PDT) X-Received: by 10.50.33.73 with SMTP id p9mr59963igi.4.1446297413828; Sat, 31 Oct 2015 06:16:53 -0700 (PDT) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!i2no1659285igv.0!news-out.google.com!fs1ni3917igb.0!nntp.google.com!i2no1149318igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 31 Oct 2015 06:16:53 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Sat, 31 Oct 2015 13:16:53 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 14 X-Received-Bytes: 1906 X-Received-Body-CRC: 576785471 Xref: mx02.eternal-september.org comp.lang.vhdl:8636 Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman: > On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > > Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: > >> i have learned every aspect of VHDL but i still can't exersise it to make complex program. > > > > It's VHDL, not C or Java. VHDL is a description, not a program. > > That's not very fair. VHDL is used to describe hardware, but it is a > perfectly good programming language too. That is how we use it for test > benches. That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset. Igmar From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sun, 1 Nov 2015 02:19:30 -0500 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 1 Nov 2015 07:17:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c9f1f81c5b43c89873758a99614bbf4a"; logging-data="26980"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qxPnIzbbMlJA6OBX/cJDq" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:N/YYQKs0Lf9uLP7BcfJ2LV6onG8= Xref: mx02.eternal-september.org comp.lang.vhdl:8637 On 10/28/2015 6:39 PM, glen herrmannsfeldt wrote: > rickman wrote: >> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: > > (snip on VHDL and programs) > >>> It's VHDL, not C or Java. VHDL is a description, not a program. > >> That's not very fair. VHDL is used to describe hardware, but it is a >> perfectly good programming language too. That is how we use it for test >> benches. > > I think I also don't like the use of the word 'program' even in > the case of test benches. > > To me, program has too much implication of sequential execution > (even in the case of parallel programming) that I think some other > word should be used. > > I might use design, which I think works in the case of hardware > and test benches, which both need to be designed, if not described. > > Though test benches could also be described, even if they aren't > hardware. > > (But the idea of a test bench comes from the days when they were > hardware, even furniture.) I just call it "code". -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Sun, 1 Nov 2015 02:27:27 -0500 Organization: A noiseless patient Spider Lines: 40 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 1 Nov 2015 07:25:16 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="c9f1f81c5b43c89873758a99614bbf4a"; logging-data="28714"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+wvFg9zIB8VHkEj2FEX5Ew" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Cancel-Lock: sha1:8dwa5dE3rtq9++NeAmrvOD4WZt0= Xref: mx02.eternal-september.org comp.lang.vhdl:8638 On 10/31/2015 9:16 AM, Igmar Palsenberg wrote: > Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman: >> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote: >>> Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi: >>>> i have learned every aspect of VHDL but i still can't exersise it to make complex program. >>> >>> It's VHDL, not C or Java. VHDL is a description, not a program. >> >> That's not very fair. VHDL is used to describe hardware, but it is a >> perfectly good programming language too. That is how we use it for test >> benches. > > That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset. I think your distinction is pointless. You said "VHDL is a description, not a program" and I have you an example when this is not true. End of discussion for me. As to the "mindset", there was a software designer who wanted to code an FPGA in VHDL and came here asking for advice. We told him about how he needed to adjust his thinking to design hardware and not code software. I wrote to him personally to explain why this was important and came close to getting some consulting time with his firm. In the end his bosses had faith that he could do a good job and so he wrote the code himself, without any trouble. I learned that although I was a hardware person who was able to more easily think about the hardware I was designing as gates and register, this is *not* required, rather you *can* write VHDL as a sequential language as long as you understand the various processes were all in parallel. Parallel processes are not unique to hardware. The really funny part was that the guy talked his bosses into sending me a small check for the time I spent helping him while I insisted that was just the cost of marketing for me and it was not needed. Not very often I tell customers to *not* pay me. Lol -- Rick From newsfish@newsfish Tue Dec 29 16:44:01 2015 X-Received: by 10.107.12.88 with SMTP id w85mr21401308ioi.32.1446497924380; Mon, 02 Nov 2015 12:58:44 -0800 (PST) X-Received: by 10.50.8.68 with SMTP id p4mr247505iga.8.1446497924363; Mon, 02 Nov 2015 12:58:44 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no1801656igv.0!news-out.google.com!fs1ni6065igb.0!nntp.google.com!i2no1801645igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 2 Nov 2015 12:58:43 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Mon, 02 Nov 2015 20:58:44 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8639 Any coder worth his salt must know his/her compiler, be it C or VHDL. For HDLs, that typically means we need to know 2 different compilers (simulator and synthesis tools). Even in purely sequential languages, the best compilers optimize the object code for the processor's inherent parallel execution capabilities based on dependencies, the same as a VHDL synthesis tool does for sequential code in processes and subprograms. I agree that there are times (e.g. synchronization boundaries) where we need to code very close to the HW we need. But at other times, coding for behavior (think throughput and clock cycles of latency) rather than HW (think gates and registers), solves more problems (will the HW behave the way we want?) Otherwise, we leave 90% of the synthesis tool's capability on the table (we do its job for it by darn near coding a netlist). Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.13.223.72 with SMTP id i69mr26341467ywe.28.1446618203255; Tue, 03 Nov 2015 22:23:23 -0800 (PST) X-Received: by 10.50.77.70 with SMTP id q6mr461246igw.4.1446618203230; Tue, 03 Nov 2015 22:23:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!c107no4842152qgd.1!news-out.google.com!z4ni45809ign.0!nntp.google.com!i2no2745750igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Nov 2015 22:23:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=194.94.26.193; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K NNTP-Posting-Host: 194.94.26.193 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> Subject: Re: creating program From: goouse99@gmail.com Injection-Date: Wed, 04 Nov 2015 06:23:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 104 Xref: mx02.eternal-september.org comp.lang.vhdl:8640 Am Freitag, 23. Oktober 2015 09:48:40 UTC+2 schrieb aadi: > Thanks Kevin for your comment. > Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop. > > > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 10 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 11 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 12 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 13 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 14 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); > key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); > else > key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); > key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); > end if; > when 15 => > if (decipher = '1') then > key_l(0 to 27) <= key_l(27) & key_l(0 to 26); > key_r(0 to 27) <= key_r(27) & key_r(0 to 26); > else > key_l(0 to 27) <= key_l(1 to 27) & key_l(0); > key_r(0 to 27) <= key_r(1 to 27) & key_r(0); > end if; > when others => > end case; > end if; > > end process Key; > > cntrl: process (clk, dirtn) > variable count : integer range 0 to 15:=0; > begin > > if (rising_edge(clk) and clk='1') then > if decipher = '0' then > if (dirtn='1') then > count:= count+ 1; > counter<=count; > else > if decipher = '1' then > count:= count- 1; > counter<=count; > end if; > end if; > end if; > end if; > end process cntrl; > end behavioural; Hi, just some hint for the case selection: If you have a number of when branches with identical statements you can combine them into one branch: e.g.: when 10 to 14 => if (decipher = '1') then key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25); key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25); else key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1); key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1); end if; Nonsequential selection values can be grouped using an or symbol: like this: when 2 | 5 | 17 => -- do something look here for more details: http://vhdl.renerta.com/mobile/source/vhd00014.htm Have a nice synthesis Eilert From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.66.160.165 with SMTP id xl5mr5296813pab.33.1446620618718; Tue, 03 Nov 2015 23:03:38 -0800 (PST) X-Received: by 10.50.33.73 with SMTP id p9mr22143igi.4.1446620618647; Tue, 03 Nov 2015 23:03:38 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2752020igv.0!news-out.google.com!z4ni45867ign.0!nntp.google.com!i2no2752012igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 3 Nov 2015 23:03:38 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=46.101.18.209; posting-account=M-xIwgoAAABy7eXiPM8pdSh8Pv2NZhsR NNTP-Posting-Host: 46.101.18.209 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Low Cost FPGA Development Board: From: posedgegroup@gmail.com Injection-Date: Wed, 04 Nov 2015 07:03:38 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8641 Low Cost FPGA Development Board: Posedge-One FPGA Develop Board 3D view: http://posedge.ir/upload/posedgeOne3D.pdf features: - Xilinx Spartan6-LX9 - USB On-Board Programer (Full support with Xilinx softwares) - 4 Mb SRAM - USB 2.0 (Speed: 10 MB/s) - 64 Mbit Flash memory - 48 I/O - 24 MHz Oscillator Hardware guide: http://posedge.ir/posedgeone_hardware_guide/ From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.66.192.234 with SMTP id hj10mr1946993pac.28.1446654291759; Wed, 04 Nov 2015 08:24:51 -0800 (PST) X-Received: by 10.50.25.131 with SMTP id c3mr113486igg.6.1446654291724; Wed, 04 Nov 2015 08:24:51 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no4107381igv.0!news-out.google.com!z4ni46377ign.0!nntp.google.com!i2no4107370igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 4 Nov 2015 08:24:51 -0800 (PST) In-Reply-To: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <1163446a-15b6-41a4-845d-8bd141f7a5dd@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Wed, 04 Nov 2015 16:24:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8642 Excellent suggestion. You can define an integer subtype with the appropriate range (and a descriptive name) to use in the choice expression, or to select a slice of an array. I use an "_range" suffix on such subtype names. subtype active_range is integer range 10 to 14; ... when active_range => ... "downto" direction also works for case choice expressions. It must match the array index direction when used to index an array. subtype status_range is integer range 7 downto 0; ... status := data_word(status_range); ... You can also use such a subtype in a loop indexing scheme: for i in status_range loop ... Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.182.52.132 with SMTP id t4mr24581183obo.16.1447069847953; Mon, 09 Nov 2015 03:50:47 -0800 (PST) X-Received: by 10.50.6.40 with SMTP id x8mr487157igx.0.1447069847925; Mon, 09 Nov 2015 03:50:47 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no1092167igv.0!news-out.google.com!l1ni988igd.0!nntp.google.com!i2no1712511igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Nov 2015 03:50:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=jBunWwoAAADJaACRgWrdsgmliB-LzsaC NNTP-Posting-Host: 80.113.175.178 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: igmar.palsenberg@boostermedia.com Injection-Date: Mon, 09 Nov 2015 11:50:47 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8643 On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > I think your distinction is pointless. You said "VHDL is a description, > not a program" and I have you an example when this is not true. End of > discussion for me. Fine. That doesn't mean you're right. > As to the "mindset", there was a software designer who wanted to code an > FPGA in VHDL and came here asking for advice. We told him about how he > needed to adjust his thinking to design hardware and not code software. > I wrote to him personally to explain why this was important and came > close to getting some consulting time with his firm. In the end his > bosses had faith that he could do a good job and so he wrote the code > himself, without any trouble. It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc. With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype. > I learned that although I was a hardware person who was able to more > easily think about the hardware I was designing as gates and register, > this is *not* required, rather you *can* write VHDL as a sequential > language as long as you understand the various processes were all in > parallel. Parallel processes are not unique to hardware. I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc. Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story. Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.13.204.19 with SMTP id o19mr139528ywd.7.1447124667319; Mon, 09 Nov 2015 19:04:27 -0800 (PST) X-Received: by 10.50.225.70 with SMTP id ri6mr582771igc.9.1447124667289; Mon, 09 Nov 2015 19:04:27 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!f78no706096qge.1!news-out.google.com!l1ni1675igd.0!nntp.google.com!i2no2059320igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 9 Nov 2015 19:04:26 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Tue, 10 Nov 2015 03:04:27 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 4154 X-Received-Body-CRC: 404324227 Xref: mx02.eternal-september.org comp.lang.vhdl:8644 On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia.c= om wrote: > It's a whole different thing, assuming the end result ends up on a FPGA. = Software is sequenced, around datastructures. VHDL is not sequenced, and do= esn't have thing software has : Lock issues, memory alignment issues, etc.= =20 >=20 Really? You think a modern SW compiler doesn't tweak your sequence to take = advantage of the processor's capabilities. Whether it's SW or HW: coder, kn= ow thy compiler!=20 And who says data structures are exclusive to SW? Oh, you mean they aren't = available in Verilog? Use a better language! > With software, you attach a debugger, and you can step through. With VHDL= , it's not that simple. So yes, I call this a different mindset. If you thi= nk like a software programmer, you'll sooner or later end up with a non-wor= king, hard to debug prototype. So you don't use the debugger to set breakpoints and step through complex R= TL? I guess maybe not if you code too close to the edif. Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit de= sign experience) for 20+ years now. Have fewer problems than when I tried t= o code netlists, doing the synthesis tool's job for it. Sure it's not _exac= tly_ like SW, but many, many principles of SW development are highly applic= able to RTL. > I doubt that still works for a *very* large design. On software, the OS h= andes a lot for you. No cache flushes, no memory barriers, etc.=20 I would beg to differ. Very large designs are where SW approaches make the = most sense and benefit. The larger the design (and body of code), the harde= r it is to maintain if you don't think about it like SW. Cache flushes are not unique to SW. The OS is just more SW. So we need to w= rite a little more code to do that in RTL. >=20 > Can a programmer while VHDL code ? Sure. But there is a huge different be= tween good and "it works". Every monkey can write PHP code, but writing goo= d, maintainable code is a different story. Yes there is a difference between SW and HW, nobody is denying that. But I'= ve reviewed, maintained, and debugged too many RTL designs written too clos= e to the netlist level not to recognize the benefits of SW approach to RTL. You have to know where to pay attention to the HW (async clock boundaries a= re a big chunk). Then handle that close to the HW level, but encapsulate it= into a few reusable entities (like system calls to the OS in SW) and then = concentrate on the function, throughput and latency of the rest of the desi= gn. On a multi-person team, only one or two need to deal with the low level= stuff, the rest can design at a much higher level, where the behavior of t= he code is critical. Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Tue, 10 Nov 2015 03:15:11 -0500 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 Nov 2015 08:12:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10912"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Mmtoj6jA7qKY9atDqS/4P" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:Kf2okAETBJ2DWGDhHdBcw7Ij7h0= Xref: mx02.eternal-september.org comp.lang.vhdl:8645 On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: > On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > >> I think your distinction is pointless. You said "VHDL is a description, >> not a program" and I have you an example when this is not true. End of >> discussion for me. > > Fine. That doesn't mean you're right. ??? You don't make sense. I give you an example of VHDL that is a program as used everyday and you reject that??? >> As to the "mindset", there was a software designer who wanted to code an >> FPGA in VHDL and came here asking for advice. We told him about how he >> needed to adjust his thinking to design hardware and not code software. >> I wrote to him personally to explain why this was important and came >> close to getting some consulting time with his firm. In the end his >> bosses had faith that he could do a good job and so he wrote the code >> himself, without any trouble. > > It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc. I don't think you understand VHDL. VHDL has sequential code, that is what a process it. > With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype. Huh??? I use single stepping with VHDL at times. Normally it isn't that useful because there is so much parallelism, things tend to jump around as one process stops and another starts... same as software on a processor with interrupts or multitasking. >> I learned that although I was a hardware person who was able to more >> easily think about the hardware I was designing as gates and register, >> this is *not* required, rather you *can* write VHDL as a sequential >> language as long as you understand the various processes were all in >> parallel. Parallel processes are not unique to hardware. > > I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc. > > Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story. I'm not sure what you are going on about. You started by saying "VHDL is a description, not a program." Now you seem to be splitting all manner of hairs and calling programmers "monkeys". Why don't we agree to disagree? -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.31.147.149 with SMTP id v143mr1492775vkd.14.1447313801660; Wed, 11 Nov 2015 23:36:41 -0800 (PST) X-Received: by 10.50.3.41 with SMTP id 9mr844480igz.7.1447313801626; Wed, 11 Nov 2015 23:36:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no93366qge.1!news-out.google.com!l1ni1556igd.0!nntp.google.com!i2no660789igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Nov 2015 23:36:40 -0800 (PST) In-Reply-To: <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 07:36:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8646 Op dinsdag 10 november 2015 04:04:31 UTC+1 schreef Andy: > On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia= .com wrote: > > It's a whole different thing, assuming the end result ends up on a FPGA= . Software is sequenced, around datastructures. VHDL is not sequenced, and = doesn't have thing software has : Lock issues, memory alignment issues, etc= .=20 > >=20 > Really? You think a modern SW compiler doesn't tweak your sequence to tak= e advantage of the processor's capabilities. Whether it's SW or HW: coder, = know thy compiler!=20 Sure.=20 > And who says data structures are exclusive to SW? Oh, you mean they aren'= t > available in Verilog? Use a better language! Datastructures come at a price. In software the're cheap, in hardware the'r= e less cheap. I need to think harder in VHDL about the structure in general= . I find myself far less limited in software (which is also a potential pro= blem, if you ask me)=20 =20 > > With software, you attach a debugger, and you can step through. With VH= DL, it's not that simple. So yes, I call this a different mindset. If you t= hink like a software programmer, you'll sooner or later end up with a non-w= orking, hard to debug prototype. >=20 > So you don't use the debugger to set breakpoints and step through complex= RTL? I guess maybe not if you code too close to the edif. I did that on old Altera software. I failed at the latest version, still ne= ed to look into that. In IntelliJ, it just attach and it works (c). > Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit = design experience) for 20+ years now. Have fewer problems than when I tried= to code netlists, doing the synthesis tool's job for it. Sure it's not _ex= actly_ like SW, but many, many principles of SW development are highly appl= icable to RTL. True. I have 20+ in software, not in hardware. Getting up-to-speed on VHDL = again, which I last used at the university (that was 15 years ago). > > I doubt that still works for a *very* large design. On software, the OS= handes a lot for you. No cache flushes, no memory barriers, etc.=20 >=20 > I would beg to differ. Very large designs are where SW approaches make th= e most sense and benefit. The larger the design (and body of code), the har= der it is to maintain if you don't think about it like SW. In what sense ? Cutting it up in the right modules you mean ? I especially = found the VHDL variable vs signals confusing, and that fact that it looks s= equential, but isn't. > Cache flushes are not unique to SW. The OS is just more SW. So we need to= write a little more code to do that in RTL. I haven't reached that point yet :) > >=20 > > Can a programmer while VHDL code ? Sure. But there is a huge different = between good and "it works". Every monkey can write PHP code, but writing g= ood, maintainable code is a different story. >=20 > Yes there is a difference between SW and HW, nobody is denying that. But = I've reviewed, maintained, and debugged too many RTL designs written too cl= ose to the netlist level not to recognize the benefits of SW approach to RT= L. >=20 > You have to know where to pay attention to the HW (async clock boundaries= are a big chunk). Then handle that close to the HW level, but encapsulate = it into a few reusable entities (like system calls to the OS in SW) and the= n concentrate on the function, throughput and latency of the rest of the de= sign. On a multi-person team, only one or two need to deal with the low lev= el stuff, the rest can design at a much higher level, where the behavior of= the code is critical. I'm still struggling testing in VHDL. With software, I'm more confortable := Junit, gtest, mockito, pick one or combine them. That's getting harder in the modern async works : Akka for example is messa= ge based, high-parallel. I'm looking at vunit for VHDL at the moment, but it's still a bit confusing= : Waveform in, waveform out. With software it's value in, value out. Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.182.236.225 with SMTP id ux1mr11718126obc.2.1447314075698; Wed, 11 Nov 2015 23:41:15 -0800 (PST) X-Received: by 10.50.61.236 with SMTP id t12mr96682igr.8.1447314075677; Wed, 11 Nov 2015 23:41:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no662064igv.0!news-out.google.com!l1ni1581igd.0!nntp.google.com!i2no2069383igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 11 Nov 2015 23:41:14 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 07:41:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8647 Op dinsdag 10 november 2015 09:15:13 UTC+1 schreef rickman: > On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: > > On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: > > > >> I think your distinction is pointless. You said "VHDL is a descriptio= n, > >> not a program" and I have you an example when this is not true. End o= f > >> discussion for me. > > > > Fine. That doesn't mean you're right. >=20 > ??? You don't make sense. I give you an example of VHDL that is a=20 > program as used everyday and you reject that??? >=20 >=20 > >> As to the "mindset", there was a software designer who wanted to code = an > >> FPGA in VHDL and came here asking for advice. We told him about how h= e > >> needed to adjust his thinking to design hardware and not code software= . > >> I wrote to him personally to explain why this was important and cam= e > >> close to getting some consulting time with his firm. In the end his > >> bosses had faith that he could do a good job and so he wrote the code > >> himself, without any trouble. > > > > It's a whole different thing, assuming the end result ends up on a FPGA= . Software is sequenced, around datastructures. VHDL is not sequenced, and = doesn't have thing software has : Lock issues, memory alignment issues, etc= . >=20 > I don't think you understand VHDL. VHDL has sequential code, that is=20 > what a process it. But all of t hem run parallel. With software, it's the other way around. > > With software, you attach a debugger, and you can step through. With VH= DL, it's not that simple. So yes, I call this a different mindset. If you t= hink like a software programmer, you'll sooner or later end up with a non-w= orking, hard to debug prototype. >=20 > Huh??? I use single stepping with VHDL at times. Normally it isn't=20 > that useful because there is so much parallelism, things tend to jump=20 > around as one process stops and another starts... same as software on a= =20 > processor with interrupts or multitasking. That's also getting more common in software these days. Ever tried debuggin= g a 1M messages / second Akka application ? I've used Altera's Max Plus II, that only had waveforms. Hooking a real sim= ulator up with Quartus failed for me. I might try the Xilinx tools, see if = I have better luck with them. =20 > > Can a programmer while VHDL code ? Sure. But there is a huge different = between good and "it works". Every monkey can write PHP code, but writing g= ood, maintainable code is a different story. >=20 > I'm not sure what you are going on about. You started by saying "VHDL=20 > is a description, not a program." Now you seem to be splitting all=20 > manner of hairs and calling programmers "monkeys". I was trying to point out there is a difference between getting something t= o work, and actually understanding it. I failed at that :) Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 11:32:41 -0500 Organization: A noiseless patient Spider Lines: 125 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 16:30:24 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="8907"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18rh7baIp81tSRwCYHbXwhg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Cancel-Lock: sha1:zy8bWrF1vwQW2p21GNsx3zh3HcM= Xref: mx02.eternal-september.org comp.lang.vhdl:8648 On 11/12/2015 2:36 AM, Igmar Palsenberg wrote: > Op dinsdag 10 november 2015 04:04:31 UTC+1 schreef Andy: >> On Monday, November 9, 2015 at 5:50:51 AM UTC-6, >> igmar.pa...@boostermedia.com wrote: >>> It's a whole different thing, assuming the end result ends up on >>> a FPGA. Software is sequenced, around datastructures. VHDL is not >>> sequenced, and doesn't have thing software has : Lock issues, >>> memory alignment issues, etc. >>> >> Really? You think a modern SW compiler doesn't tweak your sequence >> to take advantage of the processor's capabilities. Whether it's SW >> or HW: coder, know thy compiler! > > Sure. > >> And who says data structures are exclusive to SW? Oh, you mean they >> aren't > available in Verilog? Use a better language! > > Datastructures come at a price. In software the're cheap, in hardware > the're less cheap. I need to think harder in VHDL about the structure > in general. I find myself far less limited in software (which is also > a potential problem, if you ask me) I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. >>> With software, you attach a debugger, and you can step through. >>> With VHDL, it's not that simple. So yes, I call this a different >>> mindset. If you think like a software programmer, you'll sooner >>> or later end up with a non-working, hard to debug prototype. >> >> So you don't use the debugger to set breakpoints and step through >> complex RTL? I guess maybe not if you code too close to the edif. > > I did that on old Altera software. I failed at the latest version, > still need to look into that. In IntelliJ, it just attach and it > works (c). > >> Been developing FPGAs in VHDL like SW (enlightened by digital HW >> circuit design experience) for 20+ years now. Have fewer problems >> than when I tried to code netlists, doing the synthesis tool's job >> for it. Sure it's not _exactly_ like SW, but many, many principles >> of SW development are highly applicable to RTL. > > True. I have 20+ in software, not in hardware. Getting up-to-speed on > VHDL again, which I last used at the university (that was 15 years > ago). Any questions or issues? I think the hard part of VHDL is the strong typing which is very similar to Ada and that is no longer hard to me so it's all easy other than dealing with my requirements for the problem. >>> I doubt that still works for a *very* large design. On software, >>> the OS handes a lot for you. No cache flushes, no memory >>> barriers, etc. >> >> I would beg to differ. Very large designs are where SW approaches >> make the most sense and benefit. The larger the design (and body of >> code), the harder it is to maintain if you don't think about it >> like SW. > > In what sense ? Cutting it up in the right modules you mean ? I > especially found the VHDL variable vs signals confusing, and that > fact that it looks sequential, but isn't. Any time you need to break a problem down to parallel tasks in software it gets *much* more difficult. In VHDL this is not so much an issue. The sequential part of VHDL (processes) are *exactly* like software when you use variables. Signals are only different in that they are not updated until the process stops. This is because of the fact that signals are intended to model hardware with delays. So all signal assignments are made with a delta delay as a minimum which is zero time (think infinitesimal in math) and so won't happen until the process ends. All statements in a process happen without time advancing, even delta time. >> Cache flushes are not unique to SW. The OS is just more SW. So we >> need to write a little more code to do that in RTL. > > I haven't reached that point yet :) > >>> >>> Can a programmer while VHDL code ? Sure. But there is a huge >>> different between good and "it works". Every monkey can write PHP >>> code, but writing good, maintainable code is a different story. >> >> Yes there is a difference between SW and HW, nobody is denying >> that. But I've reviewed, maintained, and debugged too many RTL >> designs written too close to the netlist level not to recognize the >> benefits of SW approach to RTL. >> >> You have to know where to pay attention to the HW (async clock >> boundaries are a big chunk). Then handle that close to the HW >> level, but encapsulate it into a few reusable entities (like system >> calls to the OS in SW) and then concentrate on the function, >> throughput and latency of the rest of the design. On a multi-person >> team, only one or two need to deal with the low level stuff, the >> rest can design at a much higher level, where the behavior of the >> code is critical. > > I'm still struggling testing in VHDL. With software, I'm more > confortable : Junit, gtest, mockito, pick one or combine them. That's > getting harder in the modern async works : Akka for example is > message based, high-parallel. I guess it has been awhile since I've done C development. I've never heard of these tools. Mostly my software is done in Forth. > I'm looking at vunit for VHDL at the moment, but it's still a bit > confusing : Waveform in, waveform out. With software it's value in, > value out. VHDL has built in testing tools. ASSERT statements are how I do it. There are other features provided by system Verilog that are even fancier I hear. Even so, it's not about waveforms really. Its about inputs and outputs. VHDL describes the inputs. VHDL verifies the outputs. Waveforms are for viewing by the user when you have a problem. -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 11:40:41 -0500 Organization: A noiseless patient Spider Lines: 88 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 16:38:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10852"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kh5XMLYe2PoEHWgPMnOzE" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Cancel-Lock: sha1:pjHa8RLsGEsJaGAt/Qt14bXfFnE= Xref: mx02.eternal-september.org comp.lang.vhdl:8649 On 11/12/2015 2:41 AM, Igmar Palsenberg wrote: > Op dinsdag 10 november 2015 09:15:13 UTC+1 schreef rickman: >> On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote: >>> On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote: >>> >>>> I think your distinction is pointless. You said "VHDL is a >>>> description, not a program" and I have you an example when this >>>> is not true. End of discussion for me. >>> >>> Fine. That doesn't mean you're right. >> >> ??? You don't make sense. I give you an example of VHDL that is >> a program as used everyday and you reject that??? >> >> >>>> As to the "mindset", there was a software designer who wanted >>>> to code an FPGA in VHDL and came here asking for advice. We >>>> told him about how he needed to adjust his thinking to design >>>> hardware and not code software. I wrote to him personally to >>>> explain why this was important and came close to getting some >>>> consulting time with his firm. In the end his bosses had faith >>>> that he could do a good job and so he wrote the code himself, >>>> without any trouble. >>> >>> It's a whole different thing, assuming the end result ends up on >>> a FPGA. Software is sequenced, around datastructures. VHDL is not >>> sequenced, and doesn't have thing software has : Lock issues, >>> memory alignment issues, etc. >> >> I don't think you understand VHDL. VHDL has sequential code, that >> is what a process it. > > But all of t hem run parallel. With software, it's the other way > around. Processes run in parallel in both VHDL and in software. In software your process may be *hugely* complex doing many, many things in each one. Partly that's because there is a huge overhead for setting up and managing each process in software. In VHDL a process has no overhead in the implementation. I'm not sure how complex process management is in simulation. I've not heard it is a problem though. The speed problems in simulation often come from the data structures. Integers are faster than std_logic, et. al. >>> With software, you attach a debugger, and you can step through. >>> With VHDL, it's not that simple. So yes, I call this a different >>> mindset. If you think like a software programmer, you'll sooner >>> or later end up with a non-working, hard to debug prototype. >> >> Huh??? I use single stepping with VHDL at times. Normally it >> isn't that useful because there is so much parallelism, things tend >> to jump around as one process stops and another starts... same as >> software on a processor with interrupts or multitasking. > > That's also getting more common in software these days. Ever tried > debugging a 1M messages / second Akka application ? > > I've used Altera's Max Plus II, that only had waveforms. Hooking a > real simulator up with Quartus failed for me. I might try the Xilinx > tools, see if I have better luck with them. I've worked with Max +II. Debugging in VHDL is built in. ASSERT is a great tool. Waveforms are for user exploration when a bug is found. >>> Can a programmer while VHDL code ? Sure. But there is a huge >>> different between good and "it works". Every monkey can write PHP >>> code, but writing good, maintainable code is a different story. >> >> I'm not sure what you are going on about. You started by saying >> "VHDL is a description, not a program." Now you seem to be >> splitting all manner of hairs and calling programmers "monkeys". > > I was trying to point out there is a difference between getting > something to work, and actually understanding it. I failed at that > :) I've seen that many times. I've even done it when required. Sometimes you don't have the time to "understand" something if you just need a simple fix. BTW, I can't write PHP code. I don't even know what it is, so obviously I'm not a monkey. ;) -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.50.136.199 with SMTP id qc7mr1162360igb.13.1447347648949; Thu, 12 Nov 2015 09:00:48 -0800 (PST) X-Received: by 10.50.78.164 with SMTP id c4mr159492igx.4.1447347648924; Thu, 12 Nov 2015 09:00:48 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no875098igv.0!news-out.google.com!l1ni2017igd.0!nntp.google.com!i2no875086igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 09:00:48 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 17:00:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8650 > Processes run in parallel in both VHDL and in software. That can only be done if : a) You have multiple cores / processors b) You have an OS that supports it If either of them are not met, it all runs sequential. > In software your > process may be *hugely* complex doing many, many things in each one. > Partly that's because there is a huge overhead for setting up and > managing each process in software. In VHDL a process has no overhead in > the implementation. I'm not sure how complex process management is in > simulation. I've not heard it is a problem though. The speed problems in > simulation often come from the data structures. Integers are faster than > std_logic, et. al. I don't expect that simulation runs at fullspeed. Similar tools in software usually also have an overhead. > > I've used Altera's Max Plus II, that only had waveforms. Hooking a > > real simulator up with Quartus failed for me. I might try the Xilinx > > tools, see if I have better luck with them. > > I've worked with Max +II. Debugging in VHDL is built in. ASSERT is a > great tool. Waveforms are for user exploration when a bug is found. Hmm.. I never saw it. On the other hand : That was 15 years ago. > > I was trying to point out there is a difference between getting > > something to work, and actually understanding it. I failed at that > > :) > > I've seen that many times. I've even done it when required. Sometimes > you don't have the time to "understand" something if you just need a > simple fix. I personally don't like that myself. > BTW, I can't write PHP code. I don't even know what it is, so obviously > I'm not a monkey. ;) Advise : Keep it that way :) Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.66.157.37 with SMTP id wj5mr14043441pab.30.1447348236824; Thu, 12 Nov 2015 09:10:36 -0800 (PST) X-Received: by 10.50.6.40 with SMTP id x8mr365540igx.0.1447348236760; Thu, 12 Nov 2015 09:10:36 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no878198igv.0!news-out.google.com!l1ni2025igd.0!nntp.google.com!i2no2222033igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 09:10:36 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=92.109.33.90; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 92.109.33.90 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Thu, 12 Nov 2015 17:10:36 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8651 > > Datastructures come at a price. In software the're cheap, in hardware > > the're less cheap. I need to think harder in VHDL about the structure > > in general. I find myself far less limited in software (which is also > > a potential problem, if you ask me) > > I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. Is that always synthesizable ? > >>> With software, you attach a debugger, and you can step through. > >>> With VHDL, it's not that simple. So yes, I call this a different > >>> mindset. If you think like a software programmer, you'll sooner > >>> or later end up with a non-working, hard to debug prototype. > >> > >> So you don't use the debugger to set breakpoints and step through > >> complex RTL? I guess maybe not if you code too close to the edif. > > > > I did that on old Altera software. I failed at the latest version, > > still need to look into that. In IntelliJ, it just attach and it > > works (c). > > > >> Been developing FPGAs in VHDL like SW (enlightened by digital HW > >> circuit design experience) for 20+ years now. Have fewer problems > >> than when I tried to code netlists, doing the synthesis tool's job > >> for it. Sure it's not _exactly_ like SW, but many, many principles > >> of SW development are highly applicable to RTL. > > > > True. I have 20+ in software, not in hardware. Getting up-to-speed on > > VHDL again, which I last used at the university (that was 15 years > > ago). > > Any questions or issues? I think the hard part of VHDL is the strong > typing which is very similar to Ada and that is no longer hard to me so > it's all easy other than dealing with my requirements for the problem. I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. > > In what sense ? Cutting it up in the right modules you mean ? I > > especially found the VHDL variable vs signals confusing, and that > > fact that it looks sequential, but isn't. > > Any time you need to break a problem down to parallel tasks in software > it gets *much* more difficult. In VHDL this is not so much an issue. > > The sequential part of VHDL (processes) are *exactly* like software when > you use variables. Signals are only different in that they are not > updated until the process stops. This is because of the fact that > signals are intended to model hardware with delays. So all signal > assignments are made with a delta delay as a minimum which is zero time > (think infinitesimal in math) and so won't happen until the process > ends. All statements in a process happen without time advancing, even > delta time. Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). > > I'm still struggling testing in VHDL. With software, I'm more > > confortable : Junit, gtest, mockito, pick one or combine them. That's > > getting harder in the modern async works : Akka for example is > > message based, high-parallel. > > I guess it has been awhile since I've done C development. I've never > heard of these tools. Mostly my software is done in Forth. I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > > I'm looking at vunit for VHDL at the moment, but it's still a bit > > confusing : Waveform in, waveform out. With software it's value in, > > value out. > > VHDL has built in testing tools. ASSERT statements are how I do it. > There are other features provided by system Verilog that are even > fancier I hear. Even so, it's not about waveforms really. Its about > inputs and outputs. VHDL describes the inputs. VHDL verifies the > outputs. Waveforms are for viewing by the user when you have a problem. Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : 1) Fetch instruction byte from PC and increase PC 2) Fetch operands from PC, and increase PC 3) Move operand to A register 4) Increase PC How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). I would say confirm each step, but I'm still working that out. Regards, Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 15:45:42 -0500 Organization: A noiseless patient Spider Lines: 122 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 20:43:26 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="9210"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18L+F3Z1/b1rgAi93IUm9Nj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:BdJvjoHQ4pS3p3mGejGnRT77mBg= Xref: mx02.eternal-september.org comp.lang.vhdl:8652 On 11/12/2015 12:10 PM, Igmar Palsenberg wrote: > >>> Datastructures come at a price. In software the're cheap, in hardware >>> the're less cheap. I need to think harder in VHDL about the structure >>> in general. I find myself far less limited in software (which is also >>> a potential problem, if you ask me) >> >> I use data structures often in hardware, RAM, FIFO, stacks, arrays, etc. > > Is that always synthesizable ? They are if you describe them with synthesizable code. There is nothing special about any of them that a compiler can't understand. It's all just logic. >>>>> With software, you attach a debugger, and you can step through. >>>>> With VHDL, it's not that simple. So yes, I call this a different >>>>> mindset. If you think like a software programmer, you'll sooner >>>>> or later end up with a non-working, hard to debug prototype. >>>> >>>> So you don't use the debugger to set breakpoints and step through >>>> complex RTL? I guess maybe not if you code too close to the edif. >>> >>> I did that on old Altera software. I failed at the latest version, >>> still need to look into that. In IntelliJ, it just attach and it >>> works (c). >>> >>>> Been developing FPGAs in VHDL like SW (enlightened by digital HW >>>> circuit design experience) for 20+ years now. Have fewer problems >>>> than when I tried to code netlists, doing the synthesis tool's job >>>> for it. Sure it's not _exactly_ like SW, but many, many principles >>>> of SW development are highly applicable to RTL. >>> >>> True. I have 20+ in software, not in hardware. Getting up-to-speed on >>> VHDL again, which I last used at the university (that was 15 years >>> ago). >> >> Any questions or issues? I think the hard part of VHDL is the strong >> typing which is very similar to Ada and that is no longer hard to me so >> it's all easy other than dealing with my requirements for the problem. > > I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. I like it in some cases, but until more recently it was a PITA to try to use as it requires a lot more typing. I am will to give Verilog a shot if I can find a good book. >>> In what sense ? Cutting it up in the right modules you mean ? I >>> especially found the VHDL variable vs signals confusing, and that >>> fact that it looks sequential, but isn't. >> >> Any time you need to break a problem down to parallel tasks in software >> it gets *much* more difficult. In VHDL this is not so much an issue. >> >> The sequential part of VHDL (processes) are *exactly* like software when >> you use variables. Signals are only different in that they are not >> updated until the process stops. This is because of the fact that >> signals are intended to model hardware with delays. So all signal >> assignments are made with a delta delay as a minimum which is zero time >> (think infinitesimal in math) and so won't happen until the process >> ends. All statements in a process happen without time advancing, even >> delta time. > > Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). Delta delays get around repeatability issues while Verilog can be a killer because of them. If you are single stepping to debug code you are most likely doing it wrong. That is a poor technique in nearly any language. >>> I'm still struggling testing in VHDL. With software, I'm more >>> confortable : Junit, gtest, mockito, pick one or combine them. That's >>> getting harder in the modern async works : Akka for example is >>> message based, high-parallel. >> >> I guess it has been awhile since I've done C development. I've never >> heard of these tools. Mostly my software is done in Forth. > > I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > >>> I'm looking at vunit for VHDL at the moment, but it's still a bit >>> confusing : Waveform in, waveform out. With software it's value in, >>> value out. >> >> VHDL has built in testing tools. ASSERT statements are how I do it. >> There are other features provided by system Verilog that are even >> fancier I hear. Even so, it's not about waveforms really. Its about >> inputs and outputs. VHDL describes the inputs. VHDL verifies the >> outputs. Waveforms are for viewing by the user when you have a problem. > > Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : > > 1) Fetch instruction byte from PC and increase PC > 2) Fetch operands from PC, and increase PC > 3) Move operand to A register > 4) Increase PC > > How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). > > I would say confirm each step, but I'm still working that out. Again, you only care about inputs and outputs. Make the opcode available at the last point in time it can be read by the timing spec or model the memory as its own function (which you then need to verify). I don't know that the timing of internal events is required other than clock cycle alignment. Even then it is hard to test internal features other than functionally. So execute the next instruction to read the A register and read it out. That also verifies the PC increment. Test it as you would a Z80 chip. I believe I have found ways to read internal signals of modules in VHDL. I think this is a simulator feature rather than a language feature though. Verilog supports this directly. What issues are you concerned about? -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Thu, 12 Nov 2015 15:51:17 -0500 Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <4c9608cf-c744-4b60-985f-b3dde4ba7c1a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 12 Nov 2015 20:49:00 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="10702"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+KOeas3/aXCnWdvXWluzlo" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:XHoHQxbpjN6dtcxInIFeMmnp1t4= Xref: mx02.eternal-september.org comp.lang.vhdl:8653 On 11/12/2015 12:00 PM, Igmar Palsenberg wrote: > >> Processes run in parallel in both VHDL and in software. > > That can only be done if : > > a) You have multiple cores / processors Neither VHDL nor single processors actually run processes in parallel. The processor is time multiplexed to run one process at a time. But I'm sure you know that. > b) You have an OS that supports it Yeah... so? > If either of them are not met, it all runs sequential. So??? Even with multiple processors multiprocessing has all the same issues. >> In software your process may be *hugely* complex doing many, many >> things in each one. Partly that's because there is a huge overhead >> for setting up and managing each process in software. In VHDL a >> process has no overhead in the implementation. I'm not sure how >> complex process management is in simulation. I've not heard it is a >> problem though. The speed problems in simulation often come from >> the data structures. Integers are faster than std_logic, et. al. > > I don't expect that simulation runs at fullspeed. Similar tools in > software usually also have an overhead. > >>> I've used Altera's Max Plus II, that only had waveforms. Hooking >>> a real simulator up with Quartus failed for me. I might try the >>> Xilinx tools, see if I have better luck with them. >> >> I've worked with Max +II. Debugging in VHDL is built in. ASSERT >> is a great tool. Waveforms are for user exploration when a bug is >> found. > > Hmm.. I never saw it. On the other hand : That was 15 years ago. ASSERT has been part of VHDL from the beginning. Read up on test benches. Simulating hardware by generating waveforms manually and looking at the outputs is a PITA. >>> I was trying to point out there is a difference between getting >>> something to work, and actually understanding it. I failed at >>> that :) >> >> I've seen that many times. I've even done it when required. >> Sometimes you don't have the time to "understand" something if you >> just need a simple fix. > > I personally don't like that myself. There are lots of things about work I don't like. But the job is to do the job, not make myself happy... well, not all the time. >> BTW, I can't write PHP code. I don't even know what it is, so >> obviously I'm not a monkey. ;) > > Advise : Keep it that way :) > > > Igmar > -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.107.135.150 with SMTP id r22mr16070729ioi.24.1447373176824; Thu, 12 Nov 2015 16:06:16 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr3938igq.3.1447373176778; Thu, 12 Nov 2015 16:06:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no2381325igv.0!news-out.google.com!f6ni520igq.0!nntp.google.com!i2no1094217igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 12 Nov 2015 16:06:16 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Fri, 13 Nov 2015 00:06:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8654 Data Structures (records, arrays, etc.) can be custom defined, and as long = as they boil down to synthesizable types (Boolean, integer, enumerated type= s, std_logic, etc.) it all synthesizes. But they can sure make passing data= around a lot easier.=20 I took a couple of Ada programming classes shortly after I started using VH= DL, and it helped a lot. Just like Ada, VHDL functions and procedures can b= e defined to perform common functionality (combinatorial) that can be calle= d sequentially, rather than using a separate entity/architecture that must = be concurrently instantiated and communicated with. Things like Hamming/ECC= encoding/decoding functions are much easier to use than entities to do the= same thing. These functions can be defined inside another subprogram, a pr= ocess, or inside an architecture or a package, depending on how widely they= need to be used. Use variables for data that does not need to leave the process. Then assign= signals with the variables to send to another process/entity. That works m= uch better in that the description is then purely sequential, just like SW.= You just have to make sure you don't put too much behavior in one cycle of= latency. And if the logic won't meet the clock period, then add a register (a clock = cycle of latency in the process behavior) before and/or after the subprogra= m call and enable retiming optimization.=20 Subprograms work really well with state machines, since you can call the su= bprogram right there in the state, rather than setup an interface to some o= ther entity or process. Just remember that VHDL subprograms have no static = variables, so if your procedure needs to remember something from one call t= o the next, it needs to be passed (an inout data structure parameter works = well here). Otherwise, if you declare a procedure in a process, anything de= clared beforehand in the same process is also visible inside the procedure.= And signals/ports that are visible to the process are visible inside the p= rocedure too! That can cut down a lot on how much you have to explicitly pa= ss in/out of a procedure with each call. This way, it is easy to describe a= n entire state machine, in one subprogram. The trick is, rather than thinking registers with so many gates between the= m, think in terms of clock cycles of latency (iterations of the clocked pro= cess's inherent "forever" loop). Try not to put too much serial work in any= one clock cycle. How much is too much depends on the device and the clock = rate. As far as testing, we use a continuous integration flow with Jenkins. Our t= estbenches are 100% self-checking (waveforms are for debugging only), and u= se constrained-random stimulus, while monitoring all DUT outputs for compar= ison in scoreboards with an untimed reference model. Coverage models for th= e stimulus ensure we cover what we need to cover in terms of functionality.= This can all be done in SystemVerilog using UVM, or in VHDL using OSVVM. W= e do not do unit level testing. We may use test versions of DUT entities to= make it easier to get to an internal entity's functionality, but we always= use the DUT interface to simplify the stimulus application (drivers) and r= esponse capture (monitors). The scoreboards hook up to the monitors, not th= e DUT, and to the reference model. Monitors can also verify interface proto= cols, without having to know anything about the stimulus or expected respon= se. Hope this helps, Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.13.194.197 with SMTP id e188mr27434908ywd.24.1447608589879; Sun, 15 Nov 2015 09:29:49 -0800 (PST) X-Received: by 10.50.112.201 with SMTP id is9mr225977igb.10.1447608589847; Sun, 15 Nov 2015 09:29:49 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3596394igv.0!news-out.google.com!f6ni3414igq.0!nntp.google.com!i2no3099872igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 09:29:48 -0800 (PST) In-Reply-To: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4251716a-cba9-43b3-863a-32348cbcb026@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Sun, 15 Nov 2015 17:29:49 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8655 @rickman > > I'm looking at vunit for VHDL at the moment, but it's still a bit > > confusing : Waveform in, waveform out. With software it's value in, > > value out. > > VHDL has built in testing tools. ASSERT statements are how I do it. VUnit doesn't replace the assert statement, it builds on top of it. So VUnit starts where plain VHDL test support stops. Regards, Lars From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.107.153.146 with SMTP id b140mr28307724ioe.30.1447613850572; Sun, 15 Nov 2015 10:57:30 -0800 (PST) X-Received: by 10.50.78.164 with SMTP id c4mr228773igx.4.1447613850555; Sun, 15 Nov 2015 10:57:30 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!i2no3634442igv.0!news-out.google.com!f6ni3478igq.0!nntp.google.com!i2no3156445igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 10:57:29 -0800 (PST) In-Reply-To: <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Lars Asplund Injection-Date: Sun, 15 Nov 2015 18:57:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 72 Xref: mx02.eternal-september.org comp.lang.vhdl:8656 @Andy =20 > As far as testing, we use a continuous integration flow with Jenkins. Our= testbenches are 100% self-checking (waveforms are for debugging only), and= use constrained-random stimulus, while monitoring all DUT outputs for comp= arison in scoreboards with an untimed reference model. Coverage models for = the stimulus ensure we cover what we need to cover in terms of functionalit= y. This can all be done in SystemVerilog using UVM, or in VHDL using OSVVM.= We do not do unit level testing. We may use test versions of DUT entities = to make it easier to get to an internal entity's functionality, but we alwa= ys use the DUT interface to simplify the stimulus application (drivers) and= response capture (monitors). The scoreboards hook up to the monitors, not = the DUT, and to the reference model. Monitors can also verify interface pro= tocols, without having to know anything about the stimulus or expected resp= onse. When I promote the use of VUnit it's usually very easy when people have a p= revious experience with unit testing tools for SW. They know what to expect= and they know that they want it. It seems to me that you may have such exp= erience but decided to do only top level testing anyway. That makes me a bi= t curious about the reasons. Are you working as a verification engineer, RT= L designer, or both? Anyway, it might be interesting for you to know that VUnit doesn't know wha= t a unit is, it doesn't care about your test strategy as long as your testb= enches are self-checking, and it has support for Jenkins integration. So if= you wrap your testbench in this library vunit_lib; context vunit_lib.vunit_context; entity tb_example is generic (runner_cfg : runner_cfg_t); end entity; architecture tb of tb_example is begin main : process begin test_runner_setup(runner, runner_cfg); -- Put whatever your "main process" is doing here test_runner_cleanup(runner); -- Simulation ends here end process; -- Put your DUT, scoreboards, monitors, reference models here end architecture; and create a python script (run.py) like this from vunit import VUnit vu =3D VUnit.from_argv() lib =3D vu.add_library("lib") lib.add_source_files("*.vhd") # Create as many libraries as needed and add source files to them vu.main() and do python run.py -x test_report.xml from the command line you will have something that (assuming you're using M= odelSim, Riviera-PRO, Active-HDL or GHDL) compiles your source files in dep= endency order based on what has been modified. The script then finds and ru= ns your testbench(es) and generates a test report on "Jenkins format" Regards, Lars From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.50.142.103 with SMTP id rv7mr5908583igb.2.1447658562889; Sun, 15 Nov 2015 23:22:42 -0800 (PST) X-Received: by 10.50.98.67 with SMTP id eg3mr27440igb.1.1447658562852; Sun, 15 Nov 2015 23:22:42 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3459540igv.0!news-out.google.com!l1ni5989igd.0!nntp.google.com!i2no3806216igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 15 Nov 2015 23:22:41 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=80.113.175.178; posting-account=pI0QRAoAAABFNFUT5mlsJOk3WoGZ0oO- NNTP-Posting-Host: 80.113.175.178 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Subject: Re: creating program From: Igmar Palsenberg Injection-Date: Mon, 16 Nov 2015 07:22:42 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8657 > > I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. > > I like it in some cases, but until more recently it was a PITA to try to > use as it requires a lot more typing. I am will to give Verilog a shot > if I can find a good book. In my experience, a good IDE can help. Sigasi helps a lot, it also has features that at least the Quartus editor doesn't have. > >>> In what sense ? Cutting it up in the right modules you mean ? I > >>> especially found the VHDL variable vs signals confusing, and that > >>> fact that it looks sequential, but isn't. > >> > >> Any time you need to break a problem down to parallel tasks in software > >> it gets *much* more difficult. In VHDL this is not so much an issue. > >> > >> The sequential part of VHDL (processes) are *exactly* like software when > >> you use variables. Signals are only different in that they are not > >> updated until the process stops. This is because of the fact that > >> signals are intended to model hardware with delays. So all signal > >> assignments are made with a delta delay as a minimum which is zero time > >> (think infinitesimal in math) and so won't happen until the process > >> ends. All statements in a process happen without time advancing, even > >> delta time. > > > > Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). > > Delta delays get around repeatability issues while Verilog can be a > killer because of them. If you are single stepping to debug code you > are most likely doing it wrong. That is a poor technique in nearly any > language. Personally, I use logging to a file a lot. And breakpoints on certain points, mainly in async code. > >>> I'm still struggling testing in VHDL. With software, I'm more > >>> confortable : Junit, gtest, mockito, pick one or combine them. That's > >>> getting harder in the modern async works : Akka for example is > >>> message based, high-parallel. > >> > >> I guess it has been awhile since I've done C development. I've never > >> heard of these tools. Mostly my software is done in Forth. > > > > I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. > > > >>> I'm looking at vunit for VHDL at the moment, but it's still a bit > >>> confusing : Waveform in, waveform out. With software it's value in, > >>> value out. > >> > >> VHDL has built in testing tools. ASSERT statements are how I do it. > >> There are other features provided by system Verilog that are even > >> fancier I hear. Even so, it's not about waveforms really. Its about > >> inputs and outputs. VHDL describes the inputs. VHDL verifies the > >> outputs. Waveforms are for viewing by the user when you have a problem. > > > > Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : > > > > 1) Fetch instruction byte from PC and increase PC > > 2) Fetch operands from PC, and increase PC > > 3) Move operand to A register > > 4) Increase PC > > > > How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). > > > > I would say confirm each step, but I'm still working that out. > > Again, you only care about inputs and outputs. Make the opcode > available at the last point in time it can be read by the timing spec or > model the memory as its own function (which you then need to verify). I > don't know that the timing of internal events is required other than > clock cycle alignment. Even then it is hard to test internal features > other than functionally. So execute the next instruction to read the A > register and read it out. That also verifies the PC increment. Test it > as you would a Z80 chip. I'll just start trying. The Z80 is pretty simple, that makes it a lot easier to get started with. Good exercise. > I believe I have found ways to read internal signals of modules in VHDL. > I think this is a simulator feature rather than a language feature > though. Verilog supports this directly. > > What issues are you concerned about? I normally test internals (in software, that is), since it will make determining what broke easier then just testing the public interfaces. I probably just need to get started, and not think about this to much. Igmar From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.eu.feeder.erje.net!weretis.net!feeder4.news.weretis.net!ecngs!testfeeder.ecngs.de!81.171.118.62.MISMATCH!peer02.fr7!news.highwinds-media.com!post02.fr7!fx41.am4.POSTED!not-for-mail X-Mozilla-News-Host: news://news.virginmedia.com:119 Reply-To: hans64@htminuslab.com Newsgroups: comp.lang.vhdl From: HT-Lab Subject: keywords versus language complexity User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151116-0, 16/11/2015), Outbound message X-Antivirus-Status: Clean Lines: 9 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1447671150 81.109.142.154 (Mon, 16 Nov 2015 10:52:30 UTC) NNTP-Posting-Date: Mon, 16 Nov 2015 10:52:30 UTC Organization: virginmedia.com Date: Mon, 16 Nov 2015 10:52:29 +0000 X-Received-Body-CRC: 3877743601 X-Received-Bytes: 1239 Xref: mx02.eternal-september.org comp.lang.vhdl:8658 For those who haven't seen this article (edacafe.com): http://www10.edacafe.com/blogs/realintent/2015/11/12/is-systemverilog-the-cobol-of-electronic-design/ Regarding the stackoverflow question, I counted 129 reserved words in VHDL (14 for PSL, excluded VHPI), which is not bad ;-) Hans www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.182.97.38 with SMTP id dx6mr31793189obb.29.1447682508109; Mon, 16 Nov 2015 06:01:48 -0800 (PST) X-Received: by 10.50.72.72 with SMTP id b8mr281210igv.2.1447682508049; Mon, 16 Nov 2015 06:01:48 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!i2no3683158igv.0!news-out.google.com!f6ni4266igq.0!nntp.google.com!i2no3954861igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 16 Nov 2015 06:01:47 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.158.74.19; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L NNTP-Posting-Host: 217.158.74.19 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: keywords versus language complexity From: Chris Higgs Injection-Date: Mon, 16 Nov 2015 14:01:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8659 Another proxy for complexity - language specification length: http://www.fivecomputers.com/language-specification-length.html From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone02.ams2.highwinds-media.com!voer-me.highwinds-media.com!peer02.am1!peering.am1!peer01.fr7!news.highwinds-media.com!post01.fr7!fx46.am4.POSTED!not-for-mail Reply-To: hans64@htminuslab.com Subject: Re: keywords versus language complexity References: Newsgroups: comp.lang.vhdl From: HT-Lab User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 151116-0, 16/11/2015), Outbound message X-Antivirus-Status: Clean Lines: 26 Message-ID: NNTP-Posting-Host: 81.109.142.154 X-Complaints-To: http://netreport.virginmedia.com X-Trace: 1447691491 81.109.142.154 (Mon, 16 Nov 2015 16:31:31 UTC) NNTP-Posting-Date: Mon, 16 Nov 2015 16:31:31 UTC Organization: virginmedia.com Date: Mon, 16 Nov 2015 16:31:30 +0000 X-Received-Body-CRC: 3128994999 X-Received-Bytes: 2199 Xref: mx02.eternal-september.org comp.lang.vhdl:8660 On 16/11/2015 14:01, Chris Higgs wrote: > Another proxy for complexity - language specification length: http://www.fivecomputers.com/language-specification-length.html > Hi Chris, Yes the LRM could also be a good indicator of language complexity. I just checked a draft 1076-2008 standard which comes in at 636 pages, however, if I take the VHPI part out (the largest section) and the BNF pages then we end up with about 290 pages of pure VHDL goodness. Which again is not bad compared to SV distilled 899 pages (according to your link). I actually mentioned the article as most of us don't realise the pain parser and tool developers have to go through to support all the esoteric feature mentioned in an LRM. SV is clearly a complex language and with the small user base you will pay through the nose for tools that fully support it. We are lucky to have Jim Lewis driving the next VHDL standard so I am sure VHDL will remain lean and mean (well at least in terms of RTL standards ;-) Regards, Hans. www.ht-lab.com From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: creating program Date: Mon, 16 Nov 2015 12:40:31 -0500 Organization: A noiseless patient Spider Lines: 99 Message-ID: References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 16 Nov 2015 17:38:10 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="dd8e7b5935e95133fd5dec46ea2fab06"; logging-data="23063"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19G9RsRJSRYKVtxxhI3JJSb" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> Cancel-Lock: sha1:cW6A2ModdL6kwyEcV6izF3cT5fw= Xref: mx02.eternal-september.org comp.lang.vhdl:8661 On 11/16/2015 2:22 AM, Igmar Palsenberg wrote: > >>> I'm used to languages with strong typing. I consider that a big plus myself, especially if you have a decent compiler that warns you when things look weird. >> >> I like it in some cases, but until more recently it was a PITA to try to >> use as it requires a lot more typing. I am will to give Verilog a shot >> if I can find a good book. > > In my experience, a good IDE can help. Sigasi helps a lot, it also has features that at least the Quartus editor doesn't have. I've heard a lot of good about Emacs in this regard. >>>>> In what sense ? Cutting it up in the right modules you mean ? I >>>>> especially found the VHDL variable vs signals confusing, and that >>>>> fact that it looks sequential, but isn't. >>>> >>>> Any time you need to break a problem down to parallel tasks in software >>>> it gets *much* more difficult. In VHDL this is not so much an issue. >>>> >>>> The sequential part of VHDL (processes) are *exactly* like software when >>>> you use variables. Signals are only different in that they are not >>>> updated until the process stops. This is because of the fact that >>>> signals are intended to model hardware with delays. So all signal >>>> assignments are made with a delta delay as a minimum which is zero time >>>> (think infinitesimal in math) and so won't happen until the process >>>> ends. All statements in a process happen without time advancing, even >>>> delta time. >>> >>> Clear. I find debugging programs with a large number of thread a huge PITA. Is something goes wrong, it's sometimes nearly impossible to trace, especially since debuggers change behaviour (read : timing). >> >> Delta delays get around repeatability issues while Verilog can be a >> killer because of them. If you are single stepping to debug code you >> are most likely doing it wrong. That is a poor technique in nearly any >> language. > > Personally, I use logging to a file a lot. And breakpoints on certain points, mainly in async code. That requires a lot of manual work. If you are trying to find a problem it can be useful. But for verification it is better to automate the process. >>>>> I'm still struggling testing in VHDL. With software, I'm more >>>>> confortable : Junit, gtest, mockito, pick one or combine them. That's >>>>> getting harder in the modern async works : Akka for example is >>>>> message based, high-parallel. >>>> >>>> I guess it has been awhile since I've done C development. I've never >>>> heard of these tools. Mostly my software is done in Forth. >>> >>> I've never done that. Only C, C++, Pascal, PHP, Java, Scala, Python and bash. >>> >>>>> I'm looking at vunit for VHDL at the moment, but it's still a bit >>>>> confusing : Waveform in, waveform out. With software it's value in, >>>>> value out. >>>> >>>> VHDL has built in testing tools. ASSERT statements are how I do it. >>>> There are other features provided by system Verilog that are even >>>> fancier I hear. Even so, it's not about waveforms really. Its about >>>> inputs and outputs. VHDL describes the inputs. VHDL verifies the >>>> outputs. Waveforms are for viewing by the user when you have a problem. >>> >>> Well, take for example the LD A, 0xFF Z80 instruction. That roughly does : >>> >>> 1) Fetch instruction byte from PC and increase PC >>> 2) Fetch operands from PC, and increase PC >>> 3) Move operand to A register >>> 4) Increase PC >>> >>> How do you test that ? You also want to test timing, since on a real Z80, this instruction takes a fixed amount of time (no pipeline, no cache, no prefetching, no nothing). >>> >>> I would say confirm each step, but I'm still working that out. >> >> Again, you only care about inputs and outputs. Make the opcode >> available at the last point in time it can be read by the timing spec or >> model the memory as its own function (which you then need to verify). I >> don't know that the timing of internal events is required other than >> clock cycle alignment. Even then it is hard to test internal features >> other than functionally. So execute the next instruction to read the A >> register and read it out. That also verifies the PC increment. Test it >> as you would a Z80 chip. > > I'll just start trying. The Z80 is pretty simple, that makes it a lot easier to get started with. Good exercise. > >> I believe I have found ways to read internal signals of modules in VHDL. >> I think this is a simulator feature rather than a language feature >> though. Verilog supports this directly. >> >> What issues are you concerned about? > > I normally test internals (in software, that is), since it will make determining what broke easier then just testing the public interfaces. > I probably just need to get started, and not think about this to much. Ok -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.129.96.134 with SMTP id u128mr13500779ywb.40.1448054854783; Fri, 20 Nov 2015 13:27:34 -0800 (PST) X-Received: by 10.50.97.38 with SMTP id dx6mr121134igb.9.1448054854743; Fri, 20 Nov 2015 13:27:34 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no1083761qgf.0!news-out.google.com!f6ni8529igq.0!nntp.google.com!i2no5531229igv.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 20 Nov 2015 13:27:33 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=86.140.203.78; posting-account=iESOMQoAAACXEEKUmGCCRrNO_51JL7Al NNTP-Posting-Host: 86.140.203.78 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <59d21b01-b6bc-43b4-bbc8-1e078f89927b@googlegroups.com> Subject: Re: creating program From: pault.eg@googlemail.com Injection-Date: Fri, 20 Nov 2015 21:27:34 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 5412 X-Received-Body-CRC: 1168188575 Xref: mx02.eternal-september.org comp.lang.vhdl:8662 On Sunday, November 15, 2015 at 6:57:33 PM UTC, Lars Asplund wrote: > @Andy > =20 > > As far as testing, we use a continuous integration flow with Jenkins. O= ur testbenches are 100% self-checking (waveforms are for debugging only), a= nd use constrained-random stimulus, while monitoring all DUT outputs for co= mparison in scoreboards with an untimed reference model. Coverage models fo= r the stimulus ensure we cover what we need to cover in terms of functional= ity. This can all be done in SystemVerilog using UVM, or in VHDL using OSVV= M. We do not do unit level testing. We may use test versions of DUT entitie= s to make it easier to get to an internal entity's functionality, but we al= ways use the DUT interface to simplify the stimulus application (drivers) a= nd response capture (monitors). The scoreboards hook up to the monitors, no= t the DUT, and to the reference model. Monitors can also verify interface p= rotocols, without having to know anything about the stimulus or expected re= sponse. >=20 > When I promote the use of VUnit it's usually very easy when people have a= previous experience with unit testing tools for SW. They know what to expe= ct and they know that they want it. It seems to me that you may have such e= xperience but decided to do only top level testing anyway. That makes me a = bit curious about the reasons. Are you working as a verification engineer, = RTL designer, or both? >=20 > Anyway, it might be interesting for you to know that VUnit doesn't know w= hat a unit is, it doesn't care about your test strategy as long as your tes= tbenches are self-checking, and it has support for Jenkins integration. So = if you wrap your testbench in this >=20 > library vunit_lib; > context vunit_lib.vunit_context; >=20 > entity tb_example is > generic (runner_cfg : runner_cfg_t); > end entity; >=20 > architecture tb of tb_example is > begin > main : process > begin > test_runner_setup(runner, runner_cfg); >=20 > -- Put whatever your "main process" is doing here >=20 > test_runner_cleanup(runner); -- Simulation ends here > end process; >=20 > -- Put your DUT, scoreboards, monitors, reference models here >=20 > end architecture; >=20 > and create a python script (run.py) like this >=20 > from vunit import VUnit > vu =3D VUnit.from_argv() > lib =3D vu.add_library("lib") > lib.add_source_files("*.vhd") >=20 > # Create as many libraries as needed and add source files to them >=20 > vu.main() >=20 > and do >=20 > python run.py -x test_report.xml >=20 > from the command line you will have something that (assuming you're using= ModelSim, Riviera-PRO, Active-HDL or GHDL) compiles your source files in d= ependency order based on what has been modified. The script then finds and = runs your testbench(es) and generates a test report on "Jenkins format" >=20 > Regards, >=20 > Lars Hmmm, I don't really do too much with this now, but there are echos in what= you are doing with what I was doing with this: http://www.p-code.org/ttask.html For automatic checking I was just logging to files with this: http://www.p-code.org/tbmsgs.html As you can see that's pretty basic, the VHDL code is here: http://www.p-code.org/tbmsgs.fossil/artifact/19271c770959048b There is also a verilog version of that if you root around. I see you are using vunit as a build tool as well as the testing framework.= I did that different, as I kept the build system separate. Well, as much a= s I could, because the build system scans log files and prints a summary if= it finds tbmsgs messages. But that can be easily changed with customized e= xtensions (see bottom of first link). From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.140.171.137 with SMTP id r131mr7656118qhr.5.1448308961482; Mon, 23 Nov 2015 12:02:41 -0800 (PST) X-Received: by 10.50.78.134 with SMTP id b6mr362912igx.4.1448308961449; Mon, 23 Nov 2015 12:02:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!b51no1681477qgf.0!news-out.google.com!f6ni11368igq.0!nntp.google.com!mv3no835575igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 12:02:40 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <1d388adb-6191-4981-81f6-1314a3e6f59e@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <81852379-c448-4f2d-8149-65266d494bc3@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Mon, 23 Nov 2015 20:02:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8663 On Sunday, November 15, 2015 at 12:57:33 PM UTC-6, Lars Asplund wrote: > @Andy > When I promote the use of VUnit it's usually very easy when people have a= previous experience with unit testing tools for SW. They know what to expe= ct and they know that they want it. It seems to me that you may have such e= xperience but decided to do only top level testing anyway. That makes me a = bit curious about the reasons. Are you working as a verification engineer, = RTL designer, or both? Mostly design, but some verification experience.=20 Perhaps I should say, we use unit level testing, but only at the top (desig= n) level! Under SW testing standards, we test using the production compiler= on representative production HW, or as close as practical. Simulation and = modeling are forms of analysis, not testing, strictly speaking.=20 Given that the simulator and synthesis, place & route tool are very differe= nt "compilers", and the simulation server bears no resemblance to the targe= t HW, the only way to perform testing is by using verification systems that= capture stimulus & DUT response from simulation(s), and then play that sti= mulus against the real programmed FPGA while comparing the FPGA's response = to the simulation response, using Aldec CTS for example. So, if we have to show, under a SW test approach, how all of our verificati= on coverage goals are met, on representative HW, then we have to attain tha= t coverage by stimulating the RTL at the top level during simulation. Then = we replay that stimulus to the programmed device, and show that the DUT res= ponse was the same as simulated. Note that the simulation showed the respon= se met requirements. Other than speeding up some simulations, there is no advantage for us in lo= wer level unit testing (directly stimulating/monitoring a lower level modul= e at its ports). We still have to test it via the top level (device) interf= ace. There are still some functional coverage items we cannot cover at the = hardware level, especially things that require "white box" verification, li= ke FSM illegal state recovery, internal memory EDAC, etc. Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.140.240.193 with SMTP id l184mr19549158qhc.4.1448309648654; Mon, 23 Nov 2015 12:14:08 -0800 (PST) X-Received: by 10.50.2.6 with SMTP id 6mr364522igq.5.1448309648615; Mon, 23 Nov 2015 12:14:08 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no1686814qgf.0!news-out.google.com!f6ni11381igq.0!nntp.google.com!mv3no1408925igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 12:14:08 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.31.106.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Mon, 23 Nov 2015 20:14:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Received-Bytes: 2581 X-Received-Body-CRC: 75580551 Xref: mx02.eternal-september.org comp.lang.vhdl:8664 On Monday, November 16, 2015 at 11:40:32 AM UTC-6, rickman wrote: > On 11/16/2015 2:22 AM, Igmar Palsenberg wrote: > > In my experience, a good IDE can help. Sigasi helps a lot, it also has = features that at least the Quartus editor doesn't have. >=20 > I've heard a lot of good about Emacs in this regard. >=20 Even the free version of Sigasi is incredibly useful, if you (and your empl= oyer) can tolerate the mandatory talk-back feature in the free version. And= the paid version has LOTS more features. IDE's that are truly language awa= re are extremely valuable.=20 For example, even in the free version, you can set Sigasi to fontify subpro= gram names differently than other text. If it cannot find a matching subpro= gram within scope, WITH MATCHING ARUMENT SIGNATURE, it won't fontify it, te= lling you immediately that you either misspelled it, or misused it with you= r arguments/types.=20 Andy From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.50.36.34 with SMTP id n2mr16307441igj.8.1448315649038; Mon, 23 Nov 2015 13:54:09 -0800 (PST) X-Received: by 10.50.79.233 with SMTP id m9mr82890igx.8.1448315648981; Mon, 23 Nov 2015 13:54:08 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no1499403igc.0!news-out.google.com!f6ni11442igq.0!nntp.google.com!mv3no1499393igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 23 Nov 2015 13:54:08 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.139.53.224; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 213.139.53.224 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: instruction set behavioural implementation From: kliga Injection-Date: Mon, 23 Nov 2015 21:54:08 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8665 I have an instruction set of 16 instructions each instruction has its own format, first 4 bits for the op code if opcode =0000 then add if opcode =0001 then sub i need to write vhdl code in xilinix (behavioral code) for this instruction set. please i need help. From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: instruction set behavioural implementation Date: Mon, 23 Nov 2015 17:10:52 -0500 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 23 Nov 2015 22:08:32 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="30877"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+UciXIi8XD4cLTieTfkMBj" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 In-Reply-To: Cancel-Lock: sha1:p+YzftCDwiPriEoVbw4f3UHzDa0= Xref: mx02.eternal-september.org comp.lang.vhdl:8666 On 11/23/2015 4:54 PM, kliga wrote: > I have an instruction set of 16 instructions > each instruction has its own format, first 4 bits for the op code > if opcode =0000 then add > if opcode =0001 then sub > > i need to write vhdl code in xilinix (behavioral code) for this instruction set. > > please i need help. What does your text book say? What logical units does your design have? Do you understand what a processor is supposed to do? Do you know how to code in VHDL? -- Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.129.136.68 with SMTP id y65mr29421855ywf.53.1448360650808; Tue, 24 Nov 2015 02:24:10 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr415822igb.5.1448360650775; Tue, 24 Nov 2015 02:24:10 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no1914350qge.1!news-out.google.com!f6ni11933igq.0!nntp.google.com!mv3no1248680igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 24 Nov 2015 02:24:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=87.78.98.142; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC NNTP-Posting-Host: 87.78.98.142 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8ac33f4a-c921-4637-8314-4a3b890cc8da@googlegroups.com> Subject: Re: instruction set behavioural implementation From: Nikolaos Kavvadias Injection-Date: Tue, 24 Nov 2015 10:24:10 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8667 Hi kliga=20 if you really mean it to use a behavioral model for your processor, you wil= l probably end-up with an ASMD/FSMD kind of design. You might consult my be= havioral model for MU0 (7-/8-instruction very-simple 16-bit processor) from= : https://github.com/nkkav/mu0/blob/master/rtl/vhdl/mu0_behav.vhd You will see the concept; introducing initial contents to memory, decoding = and execution of each behavior. The entire mu0 project is here: https://github.com/nkkav/mu0/ Best regards Nikolaos Kavvadias =CE=A4=CE=B7 =CE=94=CE=B5=CF=85=CF=84=CE=AD=CF=81=CE=B1, 23 =CE=9D=CE=BF=CE= =B5=CE=BC=CE=B2=CF=81=CE=AF=CE=BF=CF=85 2015 - 11:10:56 =CE=BC.=CE=BC. UTC+= 1, =CE=BF =CF=87=CF=81=CE=AE=CF=83=CF=84=CE=B7=CF=82 rickman =CE=AD=CE=B3= =CF=81=CE=B1=CF=88=CE=B5: > On 11/23/2015 4:54 PM, kliga wrote: > > I have an instruction set of 16 instructions > > each instruction has its own format, first 4 bits for the op code > > if opcode =3D0000 then add > > if opcode =3D0001 then sub > > > > i need to write vhdl code in xilinix (behavioral code) for this instruc= tion set. > > > > please i need help. >=20 > What does your text book say? What logical units does your design have?= =20 > Do you understand what a processor is supposed to do? Do you know how= =20 > to code in VHDL? >=20 > --=20 >=20 > Rick From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.129.83.85 with SMTP id h82mr40499385ywb.0.1448557343152; Thu, 26 Nov 2015 09:02:23 -0800 (PST) X-Received: by 10.50.79.233 with SMTP id m9mr66714igx.8.1448557343124; Thu, 26 Nov 2015 09:02:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!f78no3046898qge.1!news-out.google.com!f6ni13953igq.0!nntp.google.com!mv3no3293300igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 26 Nov 2015 09:02:22 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Thu, 26 Nov 2015 17:02:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 55 Xref: mx02.eternal-september.org comp.lang.vhdl:8668 @Andy Different standards have different opinions on unit testing and to what ext= ent unit test results can be used to prove correctness of a design. Even if= you're allowed to use them you might be required to motivate why the resul= ts gained from a test run in a non-product environment is valid for the rea= l thing as well. Anyway, the key value of unit testing isn't in building test coverage, it's= in the productivity and design quality boost. A fully automated unit test = methodology enables short code/test cycles such that a developer can test f= requently and start to test early. With early and continuous feedback it's = much easier to keep the work on track considering that most people produce = bugs, misinterpret requirements and make bad design decisions on a daily ba= sis. If you only test at the system level you can't test early and frequent= ly, partly because there is a delay before there is a system level to test = at all, partly because there is a delay before an already existing system i= s compatible with your new piece of code, and partly because system level t= esting is slower. There are number of problems with this and the significan= ce depends on project size=20 1. A bug discovered late might not affect you much if it's something as sim= ple as a faulty value of a constant. But if the bug reveals a design flaw t= here is a risk that you have had the time to add a considerable amount of c= ode based on that design and have to make significant changes. 2. A bug released to be integrated with other code before system testing ca= n take place can cause significant harm. We all know this but here are some= personal experiences. After you release your bug there is a delay before t= he code is used at all because not all teams are synchronized. When the cod= e is used and the bug starts to show people spend time debugging their own = code and there is delay before the bug report finds its way to your team. O= nce there it's often incomplete, information is missing to recreate and deb= ug the problem. Meanwhile team schedules are slipping and workarounds are a= dded to not stop progress. Once the root cause has been fixed and the worka= rounds can be removed it turns out that newly written code depends on these= workarounds so more work is needed before development can proceed smoothly= . Unfortunately, a workaround was part of a customer release and now they r= ely on it which becomes apparent when you make the next release. They are n= ot willing to take the consequences of removing that workaround on short no= tice so you end up supporting two different variants. At some point, often = much later, all dependencies on the workaround are gone. Someone finds the = FIXME in the code but the memory of why it was introduced is gone or in the= heads of people no longer available. Potentially dead code is bad practice= so it has to be investigated to decide if it can be removed or not. And so= on... In the same way that the lint support of Sigasi adds value by providing con= tinuous feedback based on static code analysis unit testing adds value by p= roviding continuous feedback based on dynamic code analysis. Testing at unit level also drives design. Creating test cases for the units= forces you to think about clear functional responsibilities for that unit.= This promotes strong cohesion of the unit and loose coupling to other unit= s which are signs of a good (readable and maintainable) design. /Lars From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.107.19.41 with SMTP id b41mr59817171ioj.5.1448911072225; Mon, 30 Nov 2015 11:17:52 -0800 (PST) X-Received: by 10.50.153.76 with SMTP id ve12mr78971igb.4.1448911072207; Mon, 30 Nov 2015 11:17:52 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no8311040igc.0!news-out.google.com!l1ni639igd.0!nntp.google.com!mv3no8311036igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 30 Nov 2015 11:17:51 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=213.139.53.195; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 213.139.53.195 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2d3eba50-4c0d-43ad-8af0-7dfc0148f78a@googlegroups.com> Subject: 16 bit risc processor in VHDL From: kliga Injection-Date: Mon, 30 Nov 2015 19:17:52 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8669 Hi, I need to write behavioral VHDL code for RISC instruction set that contains 8 instructions of each length is 16 bits. there are 3 types of instructions for these 8 instructions the 3 MSB of each instruction is for operation code. i am using xilinx ISE. this is sample of my code, i need your help library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity alu is generic ( MAXWIDTH : integer := 16; MAXDEPTH : integer := 12 ); end alu; architecture Behavioral of alu is -- CONSTANTS DECLARATION constant ADD : std_logic_vector(2 downto 0) := "000"; constant ADDI : std_logic_vector(2 downto 0) := "001"; constant NND : std_logic_vector(2 downto 0) := "010"; constant LUI : std_logic_vector(2 downto 0) := "011"; constant SW : std_logic_vector(2 downto 0) := "100"; constant LW : std_logic_vector(2 downto 0) := "101"; constant BEQ : std_logic_vector(2 downto 0) := "110"; constant JALR : std_logic_vector(2 downto 0) := "111"; -- SIGNALS DECLARATION signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3); signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6); signal regB : std_logic_vector(MAXWIDTH-7 downto MAXWIDTH-5); signal regC : std_logic_vector(MAXWIDTH-14 downto 0); signal imm7: std_logic_vector(MAXWIDTH-10 downto 0); signal imm10: std_logic_vector(MAXWIDTH-7 downto 0); signal pc_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal pc_next : std_logic_vector(MAXWIDTH-1 downto 0); signal ir_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal ir_next : std_logic_vector(MAXWIDTH-1 downto 0); signal acc_reg : std_logic_vector(MAXWIDTH-1 downto 0); signal acc_next : std_logic_vector(MAXWIDTH-1 downto 0); begin process ( pc_reg, pc_next, ir_reg, ir_next, acc_reg, acc_next ) variable opcode_v : std_logic_vector(2 downto 0); begin opcode <= ir_reg(MAXWIDTH-1 downto MAXWIDTH-3); regA <= ir_reg(MAXWIDTH-4 downto MAXWIDTH-6); regB <= ir_reg(MAXWIDTH-7 downto MAXWIDTH-5); regC <= ir_reg(MAXWIDTH-14 downto 0); imm7 <= ir_reg(MAXWIDTH-10 downto 0); imm10 <= ir_reg(MAXWIDTH-7 downto 0); opcode_v := opcode; case (opcode_v) is when ADD => regA <= regB + regC; when NND => regA <= regB nand regC; when others => pc_next <= pc_reg; end case; end process; end Behavioral From newsfish@newsfish Tue Dec 29 16:44:02 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: 16 bit risc processor in VHDL Date: Mon, 30 Nov 2015 20:26:04 -0000 (UTC) Organization: A noiseless patient Spider Lines: 23 Message-ID: References: <2d3eba50-4c0d-43ad-8af0-7dfc0148f78a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 30 Nov 2015 20:26:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="e1519d2450e35d4c7974a956276402c0"; logging-data="23296"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Vv32sN9AH0mVyD8ep2Z85" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:JvvhAOKtaSo1rnQwIFcnkkBPxDk= Xref: mx02.eternal-september.org comp.lang.vhdl:8670 On Mon, 30 Nov 2015 11:17:51 -0800, kliga wrote: > Hi, > I need to write behavioral VHDL code for RISC instruction set that > contains 8 instructions of each length is 16 bits. > there are 3 types of instructions for these 8 instructions the 3 MSB of > each instruction is for operation code. > i am using xilinx ISE. > > this is sample of my code, i need your help library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.numeric_std.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > If you're using numeric_std (which you should be) then you can't also use std_logic_arith and std_logic_unsigned (which have been the wrong answer for over 20 years now.) -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Tue Dec 29 16:44:02 2015 X-Received: by 10.98.0.204 with SMTP id 195mr4486293pfa.3.1449601824229; Tue, 08 Dec 2015 11:10:24 -0800 (PST) X-Received: by 10.50.57.100 with SMTP id h4mr538066igq.6.1449601824158; Tue, 08 Dec 2015 11:10:24 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!1.us.feeder.erje.net!xmission!news.glorb.com!mv3no10608199igc.0!news-out.google.com!f6ni17171igq.0!nntp.google.com!mv3no13486352igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Dec 2015 11:10:23 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=107.182.231.192; posting-account=f7L0LgoAAAA8JEaIfr01EpmKIY2GRrE2 NNTP-Posting-Host: 107.182.231.192 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Subject: Problem in ALUControl From: Muhammadreza Haghiri Injection-Date: Tue, 08 Dec 2015 19:10:24 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8671 I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v When I want to compile it, verilog says : ALUControl.v:4: syntax error ALUControl.v:4: error: Invalid variable list in port declaration. What's wrong in 4th line? From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.13.194.197 with SMTP id e188mr5345786ywd.24.1449613017661; Tue, 08 Dec 2015 14:16:57 -0800 (PST) X-Received: by 10.50.155.8 with SMTP id vs8mr169387igb.10.1449613017592; Tue, 08 Dec 2015 14:16:57 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!b51no7303244qgf.0!news-out.google.com!l1ni838igd.0!nntp.google.com!mv3no13557877igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 8 Dec 2015 14:16:57 -0800 (PST) In-Reply-To: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=207.47.14.74; posting-account=uuodZAoAAADTv7OvvFk6il3y1Zhg_eZG NNTP-Posting-Host: 207.47.14.74 References: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Problem in ALUControl From: Gunjan Injection-Date: Tue, 08 Dec 2015 22:16:57 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1600 X-Received-Body-CRC: 1539981173 Xref: mx02.eternal-september.org comp.lang.vhdl:8672 On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote: > I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v > > When I want to compile it, verilog says : > > ALUControl.v:4: syntax error > ALUControl.v:4: error: Invalid variable list in port declaration. > > What's wrong in 4th line? Your 4th line should be as follows output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size. From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: GaborSzakacs Newsgroups: comp.lang.vhdl Subject: Re: Problem in ALUControl Date: Tue, 08 Dec 2015 18:08:30 -0500 Organization: Alacron, Inc. Lines: 40 Message-ID: References: <0d31cfc2-7902-4fef-a23a-847bb3d9e3ce@googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 8 Dec 2015 23:06:23 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="11c31a3f903a6ec400cee060ef5819ee"; logging-data="11294"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19lmHWWxmQJtWGBSvCaYeOyuQM9X2Ik0j4=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.8.1.24) Gecko/20100228 Thunderbird/2.0.0.24 Mnenhy/0.7.6.666 In-Reply-To: Cancel-Lock: sha1:UYjiKe0nMobG/yz88qjM+MOHW+0= Xref: mx02.eternal-september.org comp.lang.vhdl:8673 Gunjan wrote: > On Tuesday, December 8, 2015 at 11:10:27 AM UTC-8, Muhammadreza Haghiri wrote: >> I wrote an ALUControl for MIPS ECE4680 : https://github.com/prp-e/ECE4680/blob/master/ALUControl.v >> >> When I want to compile it, verilog says : >> >> ALUControl.v:4: syntax error >> ALUControl.v:4: error: Invalid variable list in port declaration. >> >> What's wrong in 4th line? > > > Your 4th line should be as follows > > output reg [3:0] ALUCtl; //the reg keyword should be after output and not after the size. Some other notes: always case (FuncCode) 32: ALUCt1 <= 2; . . . This process has no sensitivity list, which will hang in simulation. In addition, all assignments are non-blocking. This makes no difference to synthesis, however it will probably cause simulation to crash due to memory usage for continuously scheduling the same assignments. At least that's been my experience with ModelSim. I'd suggest writing this like: always @* // Implied sensitivity list equivalent to always @ (FuncCode) case (FuncCode) 32: ALUCt1 = 2; // Blocking assignments are appropriate for combinatorial process . . . default: ALUCt1 = 7; endcase -- Gabor From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.66.145.193 with SMTP id sw1mr4558124pab.5.1449660341336; Wed, 09 Dec 2015 03:25:41 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr230114igh.4.1449660341298; Wed, 09 Dec 2015 03:25:41 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no13755308igc.0!news-out.google.com!f6ni17793igq.0!nntp.google.com!mv3no13755298igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Wed, 9 Dec 2015 03:25:40 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=134.94.233.214; posting-account=bGNCQgoAAAAsD7_lm_EVb4Tntq0BG1_k NNTP-Posting-Host: 134.94.233.214 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7af283d4-336f-4f5c-9c4d-fff4f99526e1@googlegroups.com> Subject: Error in converting code to VHDL From: Jamil Hayder Injection-Date: Wed, 09 Dec 2015 11:25:41 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8674 Hi, Can some one please help out.Thanks. I am trying to convert below code to VHDL using HDL Coder but getting error. The HDL Coder Block file is also attached .Please can you have a look on it and see whats the mistake in block diagram. x1=[1 2 3 4 5 6 7 8 9]; x2=[3 4 5 6 7 8 9 2 1]; n=length(x1); xc=zeros(2*n-1,1); for i=1:2*n-1 if(i>n) j1=1; k1=2*n-i; j2=i-n+1; k2=n; else j1=n-i+1; k1=n; j2=1; k2=i; end xc(i)=sum(conj(x1(j1:k1)).*x2(j2:k2)); end xc=flipud(xc); Error: Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D). Error due to multiple causes. Errors occurred during parsing of MATLAB function 'MATLAB Function'(#24) Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB Function/u' is a one dimensional vector with 1 elements. From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Error in converting code to VHDL Date: Wed, 9 Dec 2015 17:44:21 -0000 (UTC) Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <7af283d4-336f-4f5c-9c4d-fff4f99526e1@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Wed, 9 Dec 2015 17:44:21 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="28921"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/rUaQBTCJyLAj85Pkw4Pe1qqicdcC4MxY=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:cBUfRSRAne9RGV4V3shwgzcCt6I= Xref: mx02.eternal-september.org comp.lang.vhdl:8675 On Wed, 09 Dec 2015 03:25:40 -0800, Jamil Hayder wrote: > Hi, Can some one please help out.Thanks. I am trying to convert below > code to VHDL using HDL Coder but getting error. The HDL Coder Block file > is also attached .Please can you have a look on it and see whats the > mistake in block diagram. > > x1=[1 2 3 4 5 6 7 8 9]; > x2=[3 4 5 6 7 8 9 2 1]; etc > > Error: > > Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D). Since there is no "prc4" in the posted code I doubt that anyone is going to be able to help. However judging by the other message: > Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB > Function/u' is a one dimensional vector with 1 elements. it looks like something in the typeless mess of Matlab code is confusing HDL Coder. You may need to do some explicit type conversions somewhere to resolve the problem. -- Brian From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.31.169.141 with SMTP id s135mr16567351vke.11.1449866403266; Fri, 11 Dec 2015 12:40:03 -0800 (PST) X-Received: by 10.50.50.148 with SMTP id c20mr211808igo.9.1449866403230; Fri, 11 Dec 2015 12:40:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!f78no7875954qge.1!news-out.google.com!f6ni20050igq.0!nntp.google.com!mv3no14873390igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Dec 2015 12:40:02 -0800 (PST) In-Reply-To: <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.35.35.35 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: creating program From: Andy Injection-Date: Fri, 11 Dec 2015 20:40:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8676 On Thursday, November 26, 2015 at 11:02:27 AM UTC-6, Lars Asplund wrote: > @Andy >=20 > Different standards have different opinions on unit testing and to what e= xtent unit test results can be used to prove correctness of a design. Even = if you're allowed to use them you might be required to motivate why the res= ults gained from a test run in a non-product environment is valid for the r= eal thing as well. >=20 > If you only test at the system level you can't test early and frequently,= partly because there is a delay before there is a system level to test at = all, partly because there is a delay before an already existing system is c= ompatible with your new piece of code, and partly because system level test= ing is slower. There are number of problems with this and the significance = depends on project size=20 >=20 ... > /Lars Lars, Sorry it's been a while... First off, when I say "system level" I mean "FPGA level". With that in mind= ... We don't wait for the whole system to be anywhere near complete before we t= est. See Jim Lewis' paper "Accelerating Verification Through Pr= e-Use of System-Level Testbench Components". We use this approach to get un= its integrated into a partially implemented system & test early, with no wa= sted time developing unit level tests that won't need to be used again. The dificulty in unit level testing is the quantity of unique interfaces fo= r all the units, and all the monitors, drivers and often-unique transaction= s required for them. By developing the units in a sensible order to allow a= testbench with a system-level interface to exercise the functionality prov= ided by lower level units, we can test early and often with one TB <-> DUT = interface, drivers, monitors, etc. This approach also makes it easier to refine the system architecture for im= proved performance, utilization, functionality, etc. because our verificati= on is immune to changes in unit level interfaces that change with the archi= tecture. Andy From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.182.112.233 with SMTP id it9mr18113627obb.45.1449891855010; Fri, 11 Dec 2015 19:44:15 -0800 (PST) X-Received: by 10.50.78.232 with SMTP id e8mr238483igx.6.1449891854970; Fri, 11 Dec 2015 19:44:14 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no14977372igc.0!news-out.google.com!l1ni620igd.0!nntp.google.com!mv3no14977371igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 11 Dec 2015 19:44:14 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Subject: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 03:44:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8677 Hi, I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: clkd_div = DFF_R1 | DFF_F5 Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? Thanks, Michael From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 02:41:25 -0500 Organization: A noiseless patient Spider Lines: 34 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 07:38:54 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="16764"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX188xiTRfGinu+m5qEmoLMIZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> Cancel-Lock: sha1:q3jrGnAYoFd9sNj6E58tkiF8uLU= Xref: mx02.eternal-september.org comp.lang.vhdl:8678 On 12/11/2015 10:44 PM, michael6866 wrote: > Hi, > > I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > > 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > > I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > clkd_div = DFF_R1 | DFF_F5 > > Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? I haven't analyzed the algorithm in detail, but it sounds like they *are* attempting to approach a 50% duty cycle. ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will produce a pulse two clock cycles wide starting on the falling edge of cycle 5. That is 4.5 clock cycles from rising edge of the first pulse to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 are pulses that cover the transition of the other two inputs to those pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not too far from 50%. Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges of the pulses, but the duty cycle will only be 2/9 or 22.2%. -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.107.151.78 with SMTP id z75mr19885853iod.31.1449936303814; Sat, 12 Dec 2015 08:05:03 -0800 (PST) X-Received: by 10.50.28.20 with SMTP id x20mr271672igg.3.1449936303798; Sat, 12 Dec 2015 08:05:03 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no15187236igc.0!news-out.google.com!f6ni20857igq.0!nntp.google.com!mv3no11670833igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 08:05:02 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 16:05:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8679 On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: > On 12/11/2015 10:44 PM, michael6866 wrote: > > Hi, > > > > I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > > > > 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > > 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > > 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > > 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > > clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > > > > I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > > clkd_div = DFF_R1 | DFF_F5 > > > > Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? > > I haven't analyzed the algorithm in detail, but it sounds like they > *are* attempting to approach a 50% duty cycle. > > ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide > starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will > produce a pulse two clock cycles wide starting on the falling edge of > cycle 5. That is 4.5 clock cycles from rising edge of the first pulse > to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 > are pulses that cover the transition of the other two inputs to those > pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not > too far from 50%. > > Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges > of the pulses, but the duty cycle will only be 2/9 or 22.2%. > > -- > > Rick Hi Rick, Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? Michael From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 12:03:52 -0500 Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 17:01:20 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="b5ace21dac962f67a10de6fe9a7b4cc1"; logging-data="3581"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZeA7MFEuj9KFw5rmx6XJ4" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Cancel-Lock: sha1:FNj82xg55Z3oW48aaL5WaTiTLJI= Xref: mx02.eternal-september.org comp.lang.vhdl:8680 On 12/12/2015 11:05 AM, michael6866 wrote: > On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: >> On 12/11/2015 10:44 PM, michael6866 wrote: >>> Hi, >>> >>> I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: >>> >>> 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" >>> 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. >>> 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. >>> 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: >>> clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) >>> >>> I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: >>> clkd_div = DFF_R1 | DFF_F5 >>> >>> Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? >> >> I haven't analyzed the algorithm in detail, but it sounds like they >> *are* attempting to approach a 50% duty cycle. >> >> ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide >> starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will >> produce a pulse two clock cycles wide starting on the falling edge of >> cycle 5. That is 4.5 clock cycles from rising edge of the first pulse >> to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 >> are pulses that cover the transition of the other two inputs to those >> pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not >> too far from 50%. >> >> Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges >> of the pulses, but the duty cycle will only be 2/9 or 22.2%. >> >> -- >> >> Rick > > Hi Rick, > > Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? Oscillator outputs are never exactly 50%. Even on crystal oscillators and such the duty cycle is often specified to be in the range of 45/55 to 55/45. To get closer to 50% you can use a 2x rate and divide by 2 with a FF, but even that will have some skew due to the asymmetry of the drive. Getting close to a 50% duty cycle can matter to some circuits depending on how they are designed. If you can't get close to 50% then you need to use a circuit independent of duty cycle. You asked why that design was the way it was. I expect it was driving something where the duty cycle mattered. -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.129.0.212 with SMTP id 203mr15811249ywa.19.1449940152577; Sat, 12 Dec 2015 09:09:12 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr274988igq.3.1449940152547; Sat, 12 Dec 2015 09:09:12 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!enother.net!enother.net!peer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!g67no85400qgd.1!news-out.google.com!f6ni20912igq.0!nntp.google.com!mv3no15210100igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 09:09:11 -0800 (PST) In-Reply-To: <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: KJ Injection-Date: Sat, 12 Dec 2015 17:09:12 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 1692 X-Received-Body-CRC: 2418047743 Xref: mx02.eternal-september.org comp.lang.vhdl:8681 On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote: > But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? > Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Gabor Szakacs Newsgroups: comp.lang.vhdl Subject: Re: Question regarding a clock divider algorithm Date: Sat, 12 Dec 2015 12:23:57 -0500 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 12 Dec 2015 17:21:43 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9bd0ba8c53fd0f12dc2ce700b744f948"; logging-data="8108"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ZAuYj9Y6DJWbnnj/Nmf3x" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1270d936-204c-4de5-977e-5f4d06d64699@googlegroups.com> Cancel-Lock: sha1:4GqHzdc6omuHPY76pBZrM2GLhfI= Xref: mx02.eternal-september.org comp.lang.vhdl:8682 On 12/12/2015 12:09 PM, KJ wrote: > On Saturday, December 12, 2015 at 11:05:07 AM UTC-5, michael6866 wrote: >> But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? >> > Duty cycle is usually only important if the part receiving the signal has a minimum high or low pulse time requirement. Maybe you can meet the requirement with a 44% duty cycle, but not a 22% duty cycle as an example. > > Kevin Jennings > It's also important if you use both clock edges like for DDR interfaces. This 2/9 clock circuit is duty cyle dependent as well. Any input clock deviation from 50% introduces jitter on the output clocks, since the time from one edge to the next depends on opposite input clock edges. If you wanted to take the output of this circuit and use both edges, e.g. to multiply by 2/9 again, the output of that circuit will be jittery even given a 50% input clock and no asymmetry in the clock divider itself. -- Gabor From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.182.20.242 with SMTP id q18mr3389419obe.2.1449951074901; Sat, 12 Dec 2015 12:11:14 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr282125igb.5.1449951074882; Sat, 12 Dec 2015 12:11:14 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!peer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!mv3no11730227igc.0!news-out.google.com!f6ni21027igq.0!nntp.google.com!mv3no15277658igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 12 Dec 2015 12:11:13 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=76.118.141.107; posting-account=x6tNfQoAAADWboqzhMU6B7ctjLS1LjqB NNTP-Posting-Host: 76.118.141.107 References: <024f47de-d960-403b-8616-9569c73be90a@googlegroups.com> <5aa1eace-b010-4379-aa13-0cad94f450a2@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <46ac0d08-5859-43c4-8c11-68e2f24dbfcd@googlegroups.com> Subject: Re: Question regarding a clock divider algorithm From: michael6866 Injection-Date: Sat, 12 Dec 2015 20:11:14 +0000 Content-Type: text/plain; charset=ISO-8859-1 X-Received-Bytes: 4496 X-Received-Body-CRC: 260085835 Xref: mx02.eternal-september.org comp.lang.vhdl:8683 On Saturday, December 12, 2015 at 12:03:53 PM UTC-5, rickman wrote: > On 12/12/2015 11:05 AM, michael6866 wrote: > > On Saturday, December 12, 2015 at 2:41:26 AM UTC-5, rickman wrote: > >> On 12/11/2015 10:44 PM, michael6866 wrote: > >>> Hi, > >>> > >>> I'm reading a paper which talks about designing a 2/9 clock divider and it doesn't require 50% duty cycle. The author presents the following approach: > >>> > >>> 1. use a 9-bit shift registers (assuming bit [8] is MSB, bit [0] is LSB) which is left-rotated on every rising edge of the original clock clk. The initial value is "000000001" > >>> 2. On every *Rising* edge of clk, read the value of bit [1] into DFF_R1, bit [2] into DFF_R2 and bit [6] into DFF_R6 correspondingly. > >>> 3. On every *Falling* edge of clk, read the value of bit [1] into DFF_F1, bit [5] into DFF_F5 and bit[6] into DFF_F6. > >>> 4. The divided clock can be generated by feeding those 1-bit DFFs into a few OR gates: > >>> clk_div = ((DFF_R1|DFF_R2)|DFF_F1) | ((DFF_F5|DFF_F6)|DFF_R6) > >>> > >>> I understand the above solution works fine. What I don't understand is why it couldn't be as simple as: > >>> clkd_div = DFF_R1 | DFF_F5 > >>> > >>> Maybe I'm missing something obvious here, but could anyone tell why the original solution is better than the naive one in my mind? > >> > >> I haven't analyzed the algorithm in detail, but it sounds like they > >> *are* attempting to approach a 50% duty cycle. > >> > >> ((DFF_R1|DFF_R2)|DFF_F1) will produce a pulse two clock cycles wide > >> starting on the rising edge of cycle 1. ((DFF_F5|DFF_F6)|DFF_R6) will > >> produce a pulse two clock cycles wide starting on the falling edge of > >> cycle 5. That is 4.5 clock cycles from rising edge of the first pulse > >> to the rising edge of the second pulse. The signals DFF_F1 and DFF_R6 > >> are pulses that cover the transition of the other two inputs to those > >> pulses preventing a glitch. The duty cycle will be 4/9 or 44.4%, not > >> too far from 50%. > >> > >> Just using DFF_R1 and DFF_F5 will give 4.5 cycles between rising edges > >> of the pulses, but the duty cycle will only be 2/9 or 22.2%. > >> > >> -- > >> > >> Rick > > > > Hi Rick, > > > > Thanks for your reply. I can see the duty cycle is close to 50%. But comparing to the 22.2% duty cycle, what's the benefit of the 44.4% duty cycle (anyway it's not 50% duty cycle)? > > Oscillator outputs are never exactly 50%. Even on crystal oscillators > and such the duty cycle is often specified to be in the range of 45/55 > to 55/45. To get closer to 50% you can use a 2x rate and divide by 2 > with a FF, but even that will have some skew due to the asymmetry of the > drive. > > Getting close to a 50% duty cycle can matter to some circuits depending > on how they are designed. If you can't get close to 50% then you need > to use a circuit independent of duty cycle. > > You asked why that design was the way it was. I expect it was driving > something where the duty cycle mattered. > > -- > > Rick Thanks Rick (and Kevin and Gabor). The paper itself doesn't mention any other module it drives. It's only about the clock divider itself. But I think your explanation makes sense. Michael From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.31.160.210 with SMTP id j201mr44948097vke.1.1450384163222; Thu, 17 Dec 2015 12:29:23 -0800 (PST) X-Received: by 10.50.114.163 with SMTP id jh3mr147163igb.1.1450384163190; Thu, 17 Dec 2015 12:29:23 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!95no12273qgm.0!news-out.google.com!l1ni6409igd.0!nntp.google.com!mv3no17513272igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Dec 2015 12:29:22 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.234.122.12; posting-account=fU5vggoAAADRS9PxgZdxgAofsoUGMF84 NNTP-Posting-Host: 73.234.122.12 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Subject: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: disturbedspace1@gmail.com Injection-Date: Thu, 17 Dec 2015 20:29:23 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8684 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; If SHIFT_PB(3 Downto 0)="0000" THEN PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; ELSE PB_DEBOUNCED <= PREVIOUS; End if; end process; end a; From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Thu, 17 Dec 2015 21:04:34 -0500 Organization: A noiseless patient Spider Lines: 103 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 02:02:04 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="3603"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+G8UlUTGuGGmG+P92Vl0zy" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> Cancel-Lock: sha1:qjRCdDzWyPV+4NTyMeIjy5HIT7A= Xref: mx02.eternal-september.org comp.lang.vhdl:8685 On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > If SHIFT_PB(3 Downto 0)="0000" THEN > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > ELSE > PB_DEBOUNCED <= PREVIOUS; > End if; > end process; > end a; I rewrote the code to separate the state signals from the shift register. Otherwise I'm not sure what you want to see. Are you looking for some specific format for the FSM? There is no special format a state machine has to be coded in unless your professor insists. I didn't test any of this code. Oh, you should not use the STD_LOGIC_UNSIGNED library. It is not a standard and works differently with different vendors. Use the NUMERIC_STD library which *is* an IEEE standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND (clock_100Hz = '1'). Lastly, using a wait statement may work for synthesizable logic, but is not a great idea. Use a conditional and I expect your circuit could use a reset. This is a *very* standard form and is well supported. I did find your signal "PREVIOUS" is superfluous. It is always assigned the same value as PB_DEBOUNCED. Either you missed something in your algorithm or you added this thinking it would do something useful but never made it do that. If you want the code to be in the form of a case statement based on the state, you just need to make the conditionals specific to a state, but I don't see any value in that. Rick library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.NUMERIC_STD.all; ENTITY debounce IS PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for ~40ms. -- Debounce clock should be approximately 10ms process (clock_100Hz, Rst) begin if ('1' = Rst) then SHIFT_PB <= (others => '0'); elsif (rising_edge(clock_100Hz)) then SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; end if; end process; process (clock_100Hz, Rst) begin if ('1' = Rst) then PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; elsif (rising_edge(clock_100Hz)) then if (SHIFT_PB = (others => '0')) then PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; elsif (SHIFT_PB = (others => '1')) then PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; else PB_DEBOUNCED <= PREVIOUS; end if; end process; end a; -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.50.147.67 with SMTP id ti3mr323151igb.13.1450412702111; Thu, 17 Dec 2015 20:25:02 -0800 (PST) X-Received: by 10.50.57.100 with SMTP id h4mr6146igq.6.1450412702096; Thu, 17 Dec 2015 20:25:02 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no17631644igc.0!news-out.google.com!f6ni26233igq.0!nntp.google.com!mv3no17631633igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 17 Dec 2015 20:25:01 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=73.234.122.12; posting-account=fU5vggoAAADRS9PxgZdxgAofsoUGMF84 NNTP-Posting-Host: 73.234.122.12 References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) From: disturbedspace1@gmail.com Injection-Date: Fri, 18 Dec 2015 04:25:02 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8686 On Thursday, December 17, 2015 at 9:04:39 PM UTC-5, rickman wrote: > On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: > > library IEEE; > > use IEEE.STD_LOGIC_1164.all; > > use IEEE.STD_LOGIC_ARITH.all; > > use IEEE.STD_LOGIC_UNSIGNED.all; > > ENTITY debounce IS > > PORT(pb, clock_100Hz : IN STD_LOGIC; > > pb_debounced : OUT STD_LOGIC); > > END debounce; > > ARCHITECTURE a OF debounce IS > > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > > SIGNAL PREVIOUS : STD_LOGIC; > > BEGIN > > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > > -- Debounce clock should be approximately 10ms > > process > > begin > > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > > SHIFT_PB(3) <= NOT PB; > > If SHIFT_PB(3 Downto 0)="0000" THEN > > PB_DEBOUNCED <= '0'; > > PREVIOUS <= '0'; > > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > > PB_DEBOUNCED <= '1'; > > PREVIOUS <= '1'; > > ELSE > > PB_DEBOUNCED <= PREVIOUS; > > End if; > > end process; > > end a; > > I rewrote the code to separate the state signals from the shift > register. Otherwise I'm not sure what you want to see. Are you looking > for some specific format for the FSM? There is no special format a > state machine has to be coded in unless your professor insists. I > didn't test any of this code. Oh, you should not use the > STD_LOGIC_UNSIGNED library. It is not a standard and works differently > with different vendors. Use the NUMERIC_STD library which *is* an IEEE > standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND > (clock_100Hz = '1'). Lastly, using a wait statement may work for > synthesizable logic, but is not a great idea. Use a conditional and I > expect your circuit could use a reset. This is a *very* standard form > and is well supported. > > I did find your signal "PREVIOUS" is superfluous. It is always assigned > the same value as PB_DEBOUNCED. Either you missed something in your > algorithm or you added this thinking it would do something useful but > never made it do that. > > If you want the code to be in the form of a case statement based on the > state, you just need to make the conditionals specific to a state, but I > don't see any value in that. > > Rick > > > > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.NUMERIC_STD.all; > ENTITY debounce IS > PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for ~40ms. > -- Debounce clock should be approximately 10ms > process (clock_100Hz, Rst) > begin > if ('1' = Rst) then > SHIFT_PB <= (others => '0'); > elsif (rising_edge(clock_100Hz)) then > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > end if; > end process; > > process (clock_100Hz, Rst) > begin > if ('1' = Rst) then > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > elsif (rising_edge(clock_100Hz)) then > if (SHIFT_PB = (others => '0')) then > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > elsif (SHIFT_PB = (others => '1')) then > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > else > PB_DEBOUNCED <= PREVIOUS; > end if; > end process; > end a; > > -- > > Rick Thanks Rick for the response.. However I dont think thats what is the solution my professor is looking for. Copying the whole question as I got it. "A very common approach to making sense of the strangeness of the real world is not to rely on sensors to trigger events, as we did in question one, but to use an internal clock in the the design. The DEBOUNCE.vhd module from lab7 does that: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY debounce IS PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END debounce; ARCHITECTURE a OF debounce IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL PREVIOUS : STD_LOGIC; BEGIN -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. -- Debounce clock should be approximately 10ms process begin wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); SHIFT_PB(3) <= NOT PB; If SHIFT_PB(3 Downto 0)="0000" THEN PB_DEBOUNCED <= '0'; PREVIOUS <= '0'; ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN PB_DEBOUNCED <= '1'; PREVIOUS <= '1'; ELSE PB_DEBOUNCED <= PREVIOUS; End if; end process; end a; Express the architecture of this module as a Finite State Machine. There seem to be at least sixteen states, corresponding to the sixteen possible values of SHIFT_PB(3 downto 0)." From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Am looking for arcitecture of below code as a Finite State Machine (Urgent) Date: Fri, 18 Dec 2015 00:57:33 -0500 Organization: A noiseless patient Spider Lines: 154 Message-ID: References: <1cd38a17-4cb3-424d-99ac-8c957e9ccfdc@googlegroups.com> <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 05:55:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="22812"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Uy3iiA7xN1Sn7WCpPZh0q" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <87248515-1856-4c96-97e8-4d89a908fb6f@googlegroups.com> Cancel-Lock: sha1:gEGgGGqJ8rNueHujxvO4aOzVZd4= Xref: mx02.eternal-september.org comp.lang.vhdl:8687 On 12/17/2015 11:25 PM, disturbedspace1@gmail.com wrote: > On Thursday, December 17, 2015 at 9:04:39 PM UTC-5, rickman wrote: >> On 12/17/2015 3:29 PM, disturbedspace1@gmail.com wrote: >>> library IEEE; >>> use IEEE.STD_LOGIC_1164.all; >>> use IEEE.STD_LOGIC_ARITH.all; >>> use IEEE.STD_LOGIC_UNSIGNED.all; >>> ENTITY debounce IS >>> PORT(pb, clock_100Hz : IN STD_LOGIC; >>> pb_debounced : OUT STD_LOGIC); >>> END debounce; >>> ARCHITECTURE a OF debounce IS >>> SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); >>> SIGNAL PREVIOUS : STD_LOGIC; >>> BEGIN >>> -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. >>> -- Debounce clock should be approximately 10ms >>> process >>> begin >>> wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); >>> SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); >>> SHIFT_PB(3) <= NOT PB; >>> If SHIFT_PB(3 Downto 0)="0000" THEN >>> PB_DEBOUNCED <= '0'; >>> PREVIOUS <= '0'; >>> ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN >>> PB_DEBOUNCED <= '1'; >>> PREVIOUS <= '1'; >>> ELSE >>> PB_DEBOUNCED <= PREVIOUS; >>> End if; >>> end process; >>> end a; >> >> I rewrote the code to separate the state signals from the shift >> register. Otherwise I'm not sure what you want to see. Are you looking >> for some specific format for the FSM? There is no special format a >> state machine has to be coded in unless your professor insists. I >> didn't test any of this code. Oh, you should not use the >> STD_LOGIC_UNSIGNED library. It is not a standard and works differently >> with different vendors. Use the NUMERIC_STD library which *is* an IEEE >> standard. Also, use "rising_edge()" instead of (clock_100Hz'EVENT) AND >> (clock_100Hz = '1'). Lastly, using a wait statement may work for >> synthesizable logic, but is not a great idea. Use a conditional and I >> expect your circuit could use a reset. This is a *very* standard form >> and is well supported. >> >> I did find your signal "PREVIOUS" is superfluous. It is always assigned >> the same value as PB_DEBOUNCED. Either you missed something in your >> algorithm or you added this thinking it would do something useful but >> never made it do that. >> >> If you want the code to be in the form of a case statement based on the >> state, you just need to make the conditionals specific to a state, but I >> don't see any value in that. >> >> Rick >> >> >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.all; >> use IEEE.STD_LOGIC_ARITH.all; >> use IEEE.NUMERIC_STD.all; >> ENTITY debounce IS >> PORT(pb, clock_100Hz, Rst : IN STD_LOGIC; >> pb_debounced : OUT STD_LOGIC); >> END debounce; >> ARCHITECTURE a OF debounce IS >> SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); >> SIGNAL PREVIOUS : STD_LOGIC; >> BEGIN >> -- Debounce Button: Filters out mechanical switch bounce for ~40ms. >> -- Debounce clock should be approximately 10ms >> process (clock_100Hz, Rst) >> begin >> if ('1' = Rst) then >> SHIFT_PB <= (others => '0'); >> elsif (rising_edge(clock_100Hz)) then >> SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); >> SHIFT_PB(3) <= NOT PB; >> end if; >> end process; >> >> process (clock_100Hz, Rst) >> begin >> if ('1' = Rst) then >> PB_DEBOUNCED <= '0'; >> PREVIOUS <= '0'; >> elsif (rising_edge(clock_100Hz)) then >> if (SHIFT_PB = (others => '0')) then >> PB_DEBOUNCED <= '0'; >> PREVIOUS <= '0'; >> elsif (SHIFT_PB = (others => '1')) then >> PB_DEBOUNCED <= '1'; >> PREVIOUS <= '1'; >> else >> PB_DEBOUNCED <= PREVIOUS; >> end if; >> end process; >> end a; >> >> -- >> >> Rick > > > Thanks Rick for the response.. However I dont think thats what is the solution my professor is looking for. Copying the whole question as I got it. > > "A very common approach to making sense of the strangeness of the real world is not to rely on sensors to trigger events, as we did in question one, but to use an internal clock in the the design. The DEBOUNCE.vhd module from lab7 does that: > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_ARITH.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > ENTITY debounce IS > PORT(pb, clock_100Hz : IN STD_LOGIC; > pb_debounced : OUT STD_LOGIC); > END debounce; > ARCHITECTURE a OF debounce IS > SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); > SIGNAL PREVIOUS : STD_LOGIC; > BEGIN > -- Debounce Button: Filters out mechanical switch bounce for around 40Ms. > -- Debounce clock should be approximately 10ms > process > begin > wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1'); > SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1); > SHIFT_PB(3) <= NOT PB; > If SHIFT_PB(3 Downto 0)="0000" THEN > PB_DEBOUNCED <= '0'; > PREVIOUS <= '0'; > ELSIF SHIFT_PB(3 Downto 0) = "1111" THEN > PB_DEBOUNCED <= '1'; > PREVIOUS <= '1'; > ELSE > PB_DEBOUNCED <= PREVIOUS; > End if; > end process; > end a; > Express the architecture of this module as a Finite State Machine. There seem to be at least sixteen states, corresponding to the sixteen possible values of SHIFT_PB(3 downto 0)." I guess your professor wants you to do it with a case statement based on the 16 possible states of SHIFT_PB. I suggest you not bother with that since it is a pointless exercise. Rather you should point out all the bad programming mistakes he made in his code. I'm sure you will get extra credit for that. Really! Your professor sucks at VHDL coding!!! Tell him a professional said so. -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.182.33.74 with SMTP id p10mr5115506obi.34.1450476330639; Fri, 18 Dec 2015 14:05:30 -0800 (PST) X-Received: by 10.50.32.10 with SMTP id e10mr113869igi.2.1450476330580; Fri, 18 Dec 2015 14:05:30 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no13432102igc.0!news-out.google.com!l1ni7450igd.0!nntp.google.com!mv3no17971555igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Fri, 18 Dec 2015 14:05:30 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=212.34.11.119; posting-account=bEKMqAoAAABkm6h82MvoNJf2KpS09xnf NNTP-Posting-Host: 212.34.11.119 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Subject: basic computer sequential implementation in vhdl From: kliga Injection-Date: Fri, 18 Dec 2015 22:05:30 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8688 I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. i need your help how to start implementation? could you give me examples for source codes like this architecture From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: basic computer sequential implementation in vhdl Date: Fri, 18 Dec 2015 18:02:26 -0500 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 18 Dec 2015 22:59:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="29543"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19BAPCYbQez7HSEjz/RbbHg" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Cancel-Lock: sha1:tgqfWiP/ZWLc97XmUlwE39eRNBg= Xref: mx02.eternal-september.org comp.lang.vhdl:8689 On 12/18/2015 5:05 PM, kliga wrote: > I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. > i need your help how to start implementation? could you give me examples for source codes like this architecture There are tons and tons of CPU designs on the Internet. All you have to do is look around a little. If you have some specific questions please ask. But you can do your own searches, no? -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.98.86.89 with SMTP id k86mr15359191pfb.10.1450689531200; Mon, 21 Dec 2015 01:18:51 -0800 (PST) X-Received: by 10.50.43.168 with SMTP id x8mr245975igl.0.1450689531166; Mon, 21 Dec 2015 01:18:51 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no18958521igc.0!news-out.google.com!l1ni9944igd.0!nntp.google.com!mv3no13995471igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 21 Dec 2015 01:18:50 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=217.211.21.59; posting-account=DxWsGAoAAACYVll1bvqwgYKqnH_okVzK NNTP-Posting-Host: 217.211.21.59 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> Subject: Re: creating program From: Lars Asplund Injection-Date: Mon, 21 Dec 2015 09:18:51 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8690 >=20 > Lars, >=20 > Sorry it's been a while... >=20 > First off, when I say "system level" I mean "FPGA level". With that in mi= nd... >=20 > We don't wait for the whole system to be anywhere near complete before we= test. See Jim Lewis' paper "Accelerating Verification Through = Pre-Use of System-Level Testbench Components". We use this approach to get = units integrated into a partially implemented system & test early, with no = wasted time developing unit level tests that won't need to be used again. >=20 > The dificulty in unit level testing is the quantity of unique interfaces = for all the units, and all the monitors, drivers and often-unique transacti= ons required for them. By developing the units in a sensible order to allow= a testbench with a system-level interface to exercise the functionality pr= ovided by lower level units, we can test early and often with one TB <-> DU= T interface, drivers, monitors, etc. >=20 > This approach also makes it easier to refine the system architecture for = improved performance, utilization, functionality, etc. because our verifica= tion is immune to changes in unit level interfaces that change with the arc= hitecture. >=20 > Andy Hi Andy, Thanks for the link to Jim's paper. I've seen a very similar approach at a = company I was helping getting started with VUnit but I didn't know the orig= in. I think there's much to say about this but here is a short summary - The paper describes the "traditional" approach as a methodology testing t= he same things at all levels and once you have the top-level testbench you = throw away the testbenches at the unit (subblock in the paper) level which = is a waste. This is not an inherent property of multi-level testing but rat= her a result of bad practices. When unit testing I aim for full functional = coverage at the unit level, higher levels of testing is focused on verifyin= g integration issues that can't be tested at the lower levels. Since all te= stbenches add unique value you don't throw them away. - To people sceptical about unit testing I recommend starting with a unit t= esting framework and apply that on their current testbenches. It provides m= any features valuable at all levels of testing. Once you understand how it = works and how it removes various obstacles in testing you will hopefully se= e how unit testing becomes more available and less cumbersome. Once there y= ou can take advantage of the values unit testing provides, values that are = lost if you just do higher level testing or variants thereof like the one i= n the paper. - When adopting unit testing there is a degree of personal preferences and = project specific circumstances that affect how it is applied. However, I ha= ve never met any HW or SW developer that want to go back to where they were= before if they have been properly introduced to a good unit testing framew= ork. I've also seen a number of HW and SW teams making the transition and t= hey have all noticed a productivity and quality boost =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D DETAILS: - In the end we are all looking for improved productivity and there are a n= umber of ways in which we can achieve this. First we should maximize the wo= rk not done (avoid waste) and if it's something that must be done we should= look for ways to automate the work, speed it up, or make it simpler in som= e other way. Whatever methodology we use it should scale with design size a= nd complexity and respond well to change. The need for handling change whet= her it's in requirements, design or implementation is an inevitable part of= larger and more complex designs. We are simply not capable of figuring out= everything in advance but have to adapt as we move along. - A short code/test cycle helps us find our mistakes ASAP to avoid wasting = time heading in the wrong direction. But how short is short enough? Suppose= I'm developing a simple UART, 200 lines of code or so, let's say a day of = work. For that I have a handful of of test cases, maybe a little bit more: = sending and receiving a byte, several bytes, verifying reset conditions, sp= ecial cases like overflow. On average I will have a new test case/feature t= hat can be verified every hour. It's not unlikely that I will introduce a b= ug during an hour of coding and I have to test this eventually anyway so wh= y not do it immediately? - One thing that may prevent me taking this approach is too long simulation= times. The method proposed in the paper would on average contain half the = complete system worth of logic in addition to the unit being tested. That i= s significant in a larger system where the total amount of logic is much la= rger than that of a unit. - As you mention, all the interfaces you need to address can become a burde= n when you have one testbench for each unit. However, you're allowed to tak= e well-motivated short-cuts even if you're into unit testing, and people of= ten do. Given that the CPU interface in Jim's example doesn't affect your a= bility to observe and control the units behind it and it doesn't add signif= icant delays, it may save you time to test the CPU interface (CIF) + the ti= mer as a "unit", CIF+UART as a unit, and CIF+memory interface as a unit. To= verify integration of the full system I need a testbench with a few read/w= rites to make sure that decoding works and I don't have conflicts on the in= ternal bus. Same number of testbenches and unique interfaces to handle as i= n the paper but no superfluous logic and no abandon testbenches. - The reason that unit grouping like the one I explained can be motivated i= s that the "main" units in the paper sits right behind a "transparent" CPU = interface and they are largely independent. A larger and more complex desig= n would have more units, they would be more "embedded" and there would be m= ore dependencies. Figuring out how to control and observe the unit under te= st becomes harder from the system boundary. There may also be significant d= elays in the paths before the targeted unit becomes activated (=3D simulati= on time). If testing is hard and slow you won't do it as often (=3D longer = code/test cycles). Also, the amount of logic per I/O of a modern FPGA is ma= ny times higher than it was in 2003 when this paper was written. The observ= ability and controllability from the system interfaces are constantly getti= ng worse. - In general it's not possible to add units to a system in such an order th= at you can test them individually from the system boundary. This is the cas= e with the CPU interface logic in the examples which is partially tested wi= th manual inspection. An alternative would of course be to make that self-c= hecking and fully tested, that is develop a proper unit test. Another appro= ach would be to postpone testing (=3D longer code/test cycle) and wait unti= l you have more units in place. This is what I do when grouping the CPU int= erface with the timer. This problem will get worst with larger and more com= plex designs - Some other obstacles for the short code/test cycle that VUnit will remove - If you want frequent testing your testbenches must be self-checking. V= Unit provides a check package that improves over plain VHDL asserts (but yo= u can use assert as well) and a test runner to organize the test cases in y= our testbench - With many testbenches and test cases it has to be convenient to run the= m frequently or you won't. VUnit will automatically compile all your files = in dependency order, find and execute all your test cases (or a subset you = specify), and present the result. - VUnit can with a command line option split your test case simulations b= etween many threads/CPU cores which can run in the background while you con= tinue to work interactively with another instance of your simulator and the= next piece of code. If you can hide the simulation time altogether there's= no excuse for not running the tests. - If you run many simulations in parallel licensing may become an issue. = VUnit supports the free and open source GHDL simulator to remove that obsta= cle. Use whatever simulator you prefer for interactive work and let GHDL ha= ndle batch simulations. - Developing transactions may be cumbersome as you noted. VUnit has a pac= kage providing message passing combined with code generation for your trans= actions. - In a previous post I described how unit testing drives an architecture wi= th highly cohesive and loosely coupled units, that is a modular design. Suc= h a design is easier to maintain since changes tend to be more localized. M= ore localized changes means less interfaces changes and less rework of test= benches when making the type of optimizations you mention. One thing we cha= nged from the first generation of VUnit to where we are today is that our t= est cases are no longer procedures defined in a separate package since inte= rface changes means that you have to update the procedure declaration as we= ll. Instead our test cases are defined in the same scope as the unit instan= ce so that they have access to the interfaces directly. I guess you have si= milar problems when the test cases are defined in architectures of a separa= te test control entity. Again, remove obstacles whenever you can. From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Nicholas Collin Paul de Gloucester Newsgroups: comp.lang.vhdl Subject: Re: keywords versus language complexity Date: Tue, 22 Dec 2015 14:37:06 +0100 Organization: A noiseless patient Spider Lines: 31 Message-ID: References: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Injection-Info: mx02.eternal-september.org; posting-host="1b4315c307f3cc5ba77928d0bb2ed33c"; logging-data="26002"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18Kmn75rrdHGWslST4WsHCYZ9ewhbvJcYTmLi8sXvFUTg==" User-Agent: Alpine 2.11 (DEB 23 2013-08-11) In-Reply-To: Cancel-Lock: sha1:I3XYLDCj0MDVlPDSEcH8jhtC6uA= X-X-Sender: gloucester@Lydia.insomnia247.nl Xref: mx02.eternal-september.org comp.lang.vhdl:8691 HT-Lab submitted: |-----------------------------------------------------------------------------| |"[. . .] | |[. . .] if I | |take [out . . .] the BNF pages then we end up | |with about 290 pages of pure VHDL goodness. [. . .] | |[. . .] | | | |I actually mentioned the article as most of us don't realise the pain parser | |and tool developers have to go through to support all the esoteric feature | |mentioned in an LRM. [. . .] | |[. . .]" | |-----------------------------------------------------------------------------| Hi Hans, Without a BNF there is no parser. |-----------------------------------------------------------------------------| |"We are lucky to have Jim Lewis driving the next VHDL standard [. . .] | |[. . .] | | | |Regards, | |Hans. | | www.ht-lab.com " | |-----------------------------------------------------------------------------| True. Regards, Nicholas Collin Paul de Gloucester From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.129.130.135 with SMTP id s129mr22043271ywf.20.1450807876951; Tue, 22 Dec 2015 10:11:16 -0800 (PST) X-Received: by 10.50.57.84 with SMTP id g20mr414328igq.3.1450807876920; Tue, 22 Dec 2015 10:11:16 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!94no473194qgt.1!news-out.google.com!f6ni30620igq.0!nntp.google.com!mv3no14472552igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Tue, 22 Dec 2015 10:11:16 -0800 (PST) In-Reply-To: <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.91.171.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS NNTP-Posting-Host: 192.91.171.34 References: <5abed163-dd5d-4492-b359-3a03de07e63a@googlegroups.com> <0889a27f-bc49-4b9b-a988-e56382739170@googlegroups.com> <5712203b-4108-4a32-bd48-ae117f7ababf@googlegroups.com> <8ba97498-3d22-4ee0-a9cc-2bdcdc206eb6@googlegroups.com> <424591fa-62f4-40a2-a9d2-4797c0a897e7@googlegroups.com> <4e6ede6d-3470-4ff7-9b6e-98de5d5f8c0f@googlegroups.com> <6bfc26c7-f2c0-476c-8181-0a9ef0f3d9a7@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <88321b8a-514d-4c41-b1c7-b9ef6b411e37@googlegroups.com> Subject: Re: creating program From: Andy Injection-Date: Tue, 22 Dec 2015 18:11:16 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Lines: 41 Xref: mx02.eternal-september.org comp.lang.vhdl:8692 Lars, A fundamental aspect of SW test that is not possible in unit level "test" i= s that, by definition, sofware "test" must use the production compiler to p= roduce production object code, which is then run and tested on production-r= epresentative hardware. In reality, simulation is analysis, not test. In HDL, the production compiler is a synthesis, place & route tool (not a s= imulator!), and the production representative hardware/system is the target= FPGA. None of these are possible at the unit level. SPR does not SPR each = module, and "call" it multiple times. Each instance is separately SPR'd as = part of the system. Each instance is uniquely optimized per its environment= within the system). In order to perform testing for Programmable Logic, all stimulus/response m= ust be provided/captured at observable interfaces for the FPGA. RTL simulat= ion at the FPGA level can be used to verify and caputure the stimulus and r= esponse at the FPGA level, which can then be applied to a real FPGA, using = the real bit file (the "production" object code.) Even after that, we still have to run integration testing using real system= hardware to provide the stimulus/response to the FPGA, to verify that simu= lation models of those external components, were accurate models. Therefore, even if we wanted to avail ourselves of the virtues of unit leve= l testing, all coverage must still be achieved at the FPGA level, since tha= t is the only level at which the PL can be truly tested. Necessary exceptions to this include white-box testing at the RTL or gate l= evel. All that said, I agree with your statement about the virtues of loosely cou= pled modules, which are encouraged by unit level development and testing. T= here are other ways to encourage these virtues, including coding/design sta= ndards and reviews.=20 Just keep in mind that what is loosely coupled in the design is not always = loosely coupled in the FPGA after optimization, placement and routing, part= icularly if physical synthesis in employed. Andy From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.31.7.132 with SMTP id 126mr32643659vkh.3.1450989634708; Thu, 24 Dec 2015 12:40:34 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr646989igh.4.1450989634675; Thu, 24 Dec 2015 12:40:34 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!6no661752qgy.0!news-out.google.com!f6ni32698igq.0!nntp.google.com!mv3no15091120igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 12:40:33 -0800 (PST) In-Reply-To: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.162; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.162 References: <8890f2b9-dcd8-4c01-aced-4c7f5b5f7dda@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: basic computer sequential implementation in vhdl From: stchebel@gmail.com Injection-Date: Thu, 24 Dec 2015 20:40:34 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8693 W dniu pi=C4=85tek, 18 grudnia 2015 23:05:34 UTC+1 u=C5=BCytkownik kliga na= pisa=C5=82: > I am working now on implementing a 16 bit RISC CPU in VHDL, the instructi= on set consists of 8 instructions 16 bits each. > i need your help how to start implementation? could you give me examples = for source codes like this architecture case Instruction_Code is when "000" =3D> ......; -- here add your desired code=20 when "001" =3D> ......; . . when "111" =3D> ......; when others =3D> null; end case; From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.129.110.7 with SMTP id j7mr29797591ywc.26.1450990188159; Thu, 24 Dec 2015 12:49:48 -0800 (PST) X-Received: by 10.50.114.105 with SMTP id jf9mr647477igb.1.1450990188091; Thu, 24 Dec 2015 12:49:48 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!6no662563qgy.0!news-out.google.com!f6ni32695igq.0!nntp.google.com!mv3no20737348igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 12:49:47 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=185.53.155.162; posting-account=67yd9woAAAAHUu8VHyA7Js47M98NE3m3 NNTP-Posting-Host: 185.53.155.162 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Subject: Wide bus From: stchebel@gmail.com Injection-Date: Thu, 24 Dec 2015 20:49:48 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8694 Suppose I have an n-input simple OR gate. Result <= inp(0) or inp(1) or ...... or inp(n); Q: how to write the above code for generic n? From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wide bus Date: Thu, 24 Dec 2015 16:48:32 -0500 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 24 Dec 2015 21:45:59 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="208907d19447316176ab8c9b8a72ea24"; logging-data="8242"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18dwRFVNFXiP+8eG+DrQu/X" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Cancel-Lock: sha1:bxXkuf7oMxFZZj7q8oqGIfmVohE= Xref: mx02.eternal-september.org comp.lang.vhdl:8695 On 12/24/2015 3:49 PM, stchebel@gmail.com wrote: > Suppose I have an n-input simple OR gate. > > Result <= inp(0) or inp(1) or ...... or inp(n); > > Q: how to write the above code for generic n? I believe there is an existing operator in VHDL 2008 to take the or of each bit in a vector. If you can't find that use a for loop. -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.182.128.39 with SMTP id nl7mr35346251obb.13.1451002666295; Thu, 24 Dec 2015 16:17:46 -0800 (PST) X-Received: by 10.50.30.201 with SMTP id u9mr656572igh.4.1451002666233; Thu, 24 Dec 2015 16:17:46 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!2.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no20798624igc.0!news-out.google.com!l1ni1431igd.0!nntp.google.com!mv3no15126095igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Thu, 24 Dec 2015 16:17:45 -0800 (PST) In-Reply-To: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Wide bus From: KJ Injection-Date: Fri, 25 Dec 2015 00:17:46 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8696 On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com wrote: > Suppose I have an n-input simple OR gate. > > Result <= inp(0) or inp(1) or ...... or inp(n); > > Q: how to write the above code for generic n? The function you want is called 'or_reduce' commonly found in the 'reduce_pkg' package. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Literals UO"2C" = B"011_CCC"? Date: Fri, 25 Dec 2015 13:45:38 +0200 Organization: A noiseless patient Spider Lines: 3 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Dec 2015 11:43:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="10465"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/bHx+um7EQO+6nOSYiQ6saD5RKnYLlf7M=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:dlGJOfsA8HtrOsA13o6H33nmU1M= Xref: mx02.eternal-september.org comp.lang.vhdl:8697 LRM says that literally UO"2C" -- Equivalent to B"011_CCC" -- that is a copy and paste Octavian 2 has binary equivalent of 010 rather than 011, isn't it? From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Fri, 25 Dec 2015 18:43:33 +0200 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 25 Dec 2015 16:41:03 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2431"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18+M5fXP9o9eb03XKqg19e/Zx9lhd4n1AY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:kv6ksE4N5waDxggackYc+Aiq4C0= Xref: mx02.eternal-september.org comp.lang.vhdl:8698 I discovered it doing some parsing. I have also noticed that I cannot parse the bit string literals because bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " Please note that bit_value is enclosed into the quotes. bit_value ::= graphic_character { [ underline ] graphic_character } graphic_character ::= basic_graphic_character | lower_case_letter | other_special_character basic_graphic_character ::= upper_case_letter | digit | special_character | space_character where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ ` -- Please note that the first special character is exactly the quotation mark. Such definition makes the bit_string_literal closing literal a part of the literal itself and parser runs into the end of stream. How do you handle such cases? From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!nntp.club.cc.cmu.edu!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Wide bus Newsgroups: comp.lang.vhdl References: <1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com> User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 26 Dec 2015 09:22:42 GMT Lines: 20 Message-ID: <567e5c62$0$1525$c3e8da3$5496439d@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 6b340b3b.news.astraweb.com X-Trace: DXC=:@hY[S7h;8WD:=ciL5QPHRL?0kYOcDh@ZKF7Mk<5A6iU0WDN7dFMi;XHI6bY5_;LhYEBe]G`V^KXWJ4[iH6U\5J]2FUFZ3noJIP Xref: mx02.eternal-september.org comp.lang.vhdl:8699 On Thu, 24 Dec 2015 16:17:45 -0800, KJ wrote: > On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com > wrote: >> Suppose I have an n-input simple OR gate. >> >> Result <= inp(0) or inp(1) or ...... or inp(n); >> >> Q: how to write the above code for generic n? > > The function you want is called 'or_reduce' commonly found in the > 'reduce_pkg' package. > > Kevin Jennings or the ieee.std_logic_misc package. It's supported in all the tools I've tried (even ones from Xilinx). Regards, Allan From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 12:38:50 -0500 Organization: A noiseless patient Spider Lines: 30 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 17:36:17 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f3df5b8edec0e1f9d6c5ec6e1844be5b"; logging-data="1075"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18mAwFauOEWAnZVfZw65DKV" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:knxdR/BwHRxuUvb/sENRfUOQJPU= Xref: mx02.eternal-september.org comp.lang.vhdl:8700 On 12/25/2015 11:43 AM, valtih1978 wrote: > I discovered it doing some parsing. I have also noticed that I cannot > parse the bit string literals because > > bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " > > Please note that bit_value is enclosed into the quotes. > > bit_value ::= graphic_character { [ underline ] graphic_character } > graphic_character ::= basic_graphic_character | lower_case_letter | > other_special_character > basic_graphic_character ::= > upper_case_letter | digit | special_character | space_character > > where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ > ` -- Please note that the first special character is exactly the > quotation mark. Such definition makes the bit_string_literal closing > literal a part of the literal itself and parser runs into the end of > stream. How do you handle such cases? So you are trying to write a parser for VHDL? Obviously you scan the input text until you encounter another quote character. I know some languages allow quotes to be embedded in strings by using two quotes in a row, so the scanning is not so simple. You have to scan for a quote followed by a character that is not a quote. But I don't think VHDL does this. -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 20:28:42 +0200 Organization: A noiseless patient Spider Lines: 29 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 18:26:07 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="13696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19PellN4YYk0kqXz150szcQGfgTqrmYKhM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:hIo7S5tTbFU2dDf82qbcDHuccmA= Xref: mx02.eternal-september.org comp.lang.vhdl:8701 > So you are trying to write a parser for VHDL? Obviously you scan the > input text until you encounter another quote character. Obviously, I am doing quite the opposite thing. I follow the grammar rules instead of scanning for the second mark. I have failed exactly because not following this simplistic approach. Probably I am the only one on the planet who does not do that. >I know some > languages allow quotes to be embedded in strings by using two quotes in > a row, so the scanning is not so simple. You have to scan for a quote > followed by a character that is not a quote. But I don't think VHDL > does this. The duplication of quotation mark is stipulated in the `string_literal` chapter in LRM. It is also interesting how good this stipulation matches with the grammar rules, presented in parallel. Yet, I do not see such a remark in the `bit_string_literal` rule, discussed separately in the LRM. I looked into example parser, https://sourceforge.net/p/zamiacad/code/ci/master/tree/src/org/zamia/vhdl/vhdl2008/VHDL2008.jj. They simply throw the quotation mark out of the special character list and then add it separately as an alternative to graphic_character in the string_literal definition. But they do not supply " char in the bit string definition, which means that they do not support " in the bitstring literals. I am looking to know how it is supposed to be done and what does VHDL community does. From newsfish@newsfish Tue Dec 29 16:44:03 2015 X-Received: by 10.140.157.74 with SMTP id d71mr40622154qhd.13.1451163272976; Sat, 26 Dec 2015 12:54:32 -0800 (PST) X-Received: by 10.50.134.69 with SMTP id pi5mr738376igb.5.1451163272945; Sat, 26 Dec 2015 12:54:32 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!6no986330qgy.0!news-out.google.com!l1ni3302igd.0!nntp.google.com!mv3no15510446igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sat, 26 Dec 2015 12:54:31 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Sat, 26 Dec 2015 20:54:32 +0000 Content-Type: text/plain; charset=ISO-8859-1 Lines: 26 Xref: mx02.eternal-september.org comp.lang.vhdl:8702 On Friday, December 25, 2015 at 11:43:41 AM UTC-5, valtih1978 wrote: > I discovered it doing some parsing. I have also noticed that I cannot > parse the bit string literals because > > bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " > > Please note that bit_value is enclosed into the quotes. > > bit_value ::= graphic_character { [ underline ] graphic_character } > graphic_character ::= basic_graphic_character | lower_case_letter | > other_special_character > basic_graphic_character ::= > upper_case_letter | digit | special_character | space_character > > where special characters are " # & ' () * + , - . / : ; < = > ? @ [ ] _ > ` -- Please note that the first special character is exactly the > quotation mark. Such definition makes the bit_string_literal closing > literal a part of the literal itself and parser runs into the end of > stream. How do you handle such cases? The double quote that is to be included in the literal would have to be preceded by a backslash. Also note the definition of a string literal is: string_literal ::= " { graphic_character } " You would have the same issue here trying to insert a " into a string. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 17:26:23 -0500 Organization: A noiseless patient Spider Lines: 37 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 26 Dec 2015 22:23:49 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="f3df5b8edec0e1f9d6c5ec6e1844be5b"; logging-data="5126"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/I1IXZ7CB6zCsCQj8woaR5" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:+idOpboTEG9/bZ99v9Io8loDMM4= Xref: mx02.eternal-september.org comp.lang.vhdl:8703 On 12/26/2015 1:28 PM, valtih1978 wrote: >> So you are trying to write a parser for VHDL? Obviously you scan the >> input text until you encounter another quote character. > > Obviously, I am doing quite the opposite thing. I follow the grammar > rules instead of scanning for the second mark. I have failed exactly > because not following this simplistic approach. Probably I am the only > one on the planet who does not do that. > >> I know some >> languages allow quotes to be embedded in strings by using two quotes in >> a row, so the scanning is not so simple. You have to scan for a quote >> followed by a character that is not a quote. But I don't think VHDL >> does this. > > The duplication of quotation mark is stipulated in the `string_literal` > chapter in LRM. It is also interesting how good this stipulation matches > with the grammar rules, presented in parallel. Yet, I do not see such a > remark in the `bit_string_literal` rule, discussed separately in the LRM. > > I looked into example parser, > https://sourceforge.net/p/zamiacad/code/ci/master/tree/src/org/zamia/vhdl/vhdl2008/VHDL2008.jj. > They simply throw the quotation mark out of the special character list > and then add it separately as an alternative to graphic_character in the > string_literal definition. But they do not supply " char in the bit > string definition, which means that they do not support " in the > bitstring literals. > > I am looking to know how it is supposed to be done and what does VHDL > community does. I'm unclear. If you are following "all" the grammar rules, what exactly is your concern? -- Rick From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 02:59:18 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: <567F37E6.5090602@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="3696"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18DNobNsi7cC9G0GJfPlgr0kXs7lT1BIG4=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> Cancel-Lock: sha1:aWwP2yMzPRQz4m3Q+EUYM4RGtoQ= Xref: mx02.eternal-september.org comp.lang.vhdl:8704 > You would have the same issue here trying to insert a " into a string. Where did you read about that? > Also note the definition of a string literal is: > > string_literal ::= " { graphic_character } " > > You would have the same issue here trying to insert a " into a string. Yes, I reported that already to the rickman. I reported that I have discovered that LRM mandates user to duplicate the double quote marks in the VHDL source string literals to produce a single quotation in the running program. The Bible says so textually but LRM grammar productions seem to contradict the text. LRM does not even stipulate this issue in the bit_string_literal declaration at all. So I wonder, how did you know that \" must be used there instead of quotation duplication? Did you confuse user input with mine parser code, written in derivative of C? From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Physical unit ambiguities Date: Sun, 27 Dec 2015 03:07:53 +0200 Organization: A noiseless patient Spider Lines: 22 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 01:05:18 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="5151"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19leCtCat2SlelpMsW6fFPOL3bRPIcaJiI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 X-Mozilla-News-Host: news://news.eternal-september.org:119 Cancel-Lock: sha1:vc6HBarZBgQsV5nQRcRuRibPL50= Xref: mx02.eternal-september.org comp.lang.vhdl:8705 Another ambiguity comes from literal ::= numeric_literal | enumeration_literal | ... numeric_literal ::= physical_literal | ... physical_literal ::= [ abstract_literal ] name name ::= identifier | operator_symbol | character_literal | selected_name | indexed_name | slice_name | attribute_name enumeration_literal ::= identifier | ... For instance, you have a 'second' in the expression. Is it an enumeration or physical literal? The numerical quantity is optional in phys. literals, as we see. It seems that this is an incarnation of what I heard of "context-sensitivity" of VHDL? Does it mean that the parse tree is ambiguous until after the elaboration? Moreover, 'name' admits such fancy names as function invocation, attribute requests and such, which seems to be a nonsense for physical literal, e.g. 1 miles(3) should be valid according to the LRM grammar. Language designers could easily ban this "feature" by saying that physical units are specified by identifiers (aka simple names) rather than arbitrary names. Why does spec choose the general name production instead? From newsfish@newsfish Tue Dec 29 16:44:03 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sat, 26 Dec 2015 20:33:53 -0500 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 01:31:19 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="3e23f04fa29aea4a01d064c7ba7655fc"; logging-data="8338"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Yp2Dh79NQZENP4l602iMZ" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <567F37E6.5090602@not.email.me> Cancel-Lock: sha1:T/dgLSgf/5beXCURy6LLxvlYi+A= Xref: mx02.eternal-september.org comp.lang.vhdl:8706 On 12/26/2015 7:59 PM, valtih1978 wrote: >> You would have the same issue here trying to insert a " into a string. > > Where did you read about that? > > > Also note the definition of a string literal is: > > > > string_literal ::= " { graphic_character } " > > > > You would have the same issue here trying to insert a " into a string. > > Yes, I reported that already to the rickman. I reported that I have > discovered that LRM mandates user to duplicate the double quote marks in > the VHDL source string literals to produce a single quotation in the > running program. The Bible says so textually but LRM grammar productions > seem to contradict the text. LRM does not even stipulate this issue in > the bit_string_literal declaration at all. So I wonder, how did you know > that \" must be used there instead of quotation duplication? Did you > confuse user input with mine parser code, written in derivative of C? Except you showed BNF for "bit_string_literal" while the double quote only had meaning in the more literal "string_literal". Is the "string_literal" defined the same way? If your problem is in the "bit_string_literal" why are you trying to embed quotes in it? -- Rick From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 09:48:30 +0200 Organization: A noiseless patient Spider Lines: 25 Message-ID: <567F97CE.2060508@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="25723"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19pdL+KE35iWfDR24XSsGsZKOmtfMTtz2Y=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:Z+gkF+MYQw3N+9O4qKrev6EYCSA= Xref: mx02.eternal-september.org comp.lang.vhdl:8707 > Except you showed BNF for "bit_string_literal" while the double quote > only had meaning in the more literal "string_literal". Who says that any why does LRM say otherwise? I have demonstrated the grammar that says that all special characters, including the quotes, are allowed in the bit string literal, in the same way as they are included in the string literal. > Is the > "string_literal" defined the same way? You are responding under KJ's remark saying that the string literal string_literal ::= " { graphic_character } " is defined the same way. So, I do not understand this the question. > If your problem is in the > "bit_string_literal" why are you trying to embed quotes in it? Because I tried to implement the spec rather than my fantasies or to embed the quotes into the string. I think that if spec admits embedded quotes, they must be supported. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 11:09:32 -0500 Organization: A noiseless patient Spider Lines: 36 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 16:06:58 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="68639cc5c98aed50d7aac76c23cb1a02"; logging-data="23300"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX186sLPGKeZDtL6CPxN7kkOu" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <567F97CE.2060508@not.email.me> Cancel-Lock: sha1:S0zFNJfkuzGIuZ/AYq/97yms+HE= Xref: mx02.eternal-september.org comp.lang.vhdl:8708 On 12/27/2015 2:48 AM, valtih1978 wrote: > >> Except you showed BNF for "bit_string_literal" while the double quote >> only had meaning in the more literal "string_literal". > > Who says that any why does LRM say otherwise? I have demonstrated the > grammar that says that all special characters, including the quotes, are > allowed in the bit string literal, in the same way as they are included > in the string literal. > >> Is the >> "string_literal" defined the same way? > > You are responding under KJ's remark saying that the string literal > > string_literal ::= " { graphic_character } " > > is defined the same way. So, I do not understand this the question. > >> If your problem is in the >> "bit_string_literal" why are you trying to embed quotes in it? > > Because I tried to implement the spec rather than my fantasies or to > embed the quotes into the string. I think that if spec admits embedded > quotes, they must be supported. You mean you tried to implement the BNF which seems to not describe the language 100%. To think that a bit literal can contain every letter of the alphabet is a bit silly. They can't because a bit string literal only has meaning when it contains the few characters that are allowed. The VHDL spec is more than just the BNF lists. -- Rick From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 21:01:09 +0200 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 18:58:33 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="29157"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19qTFLYc35UJiczYW7ESS8hAGi3c2yeS6Y=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:z4p0Kj1HmWLHGwo2teDnqPNO7RM= Xref: mx02.eternal-september.org comp.lang.vhdl:8709 > You mean you tried to implement the BNF which seems to not describe the > language 100%.The VHDL spec is more than just the BNF lists. Yes, I tried. Yes, BNF is incomplete and water is liquid. But the problem that I address here is that BNF seems to contain a fatal error. Saying that I see it because it does not specify the language 100% is a little bit inappropriate, isn't it? It is like if instruction to go shopping would instruct you to kill youself at one point. You may defend the instruction saying that "it is incomplete" but this would make the situation even more ridiculous. And it does. > To think that a bit literal can contain every letter of > the alphabet is a bit silly. What if BNF admits every character? Have you ever looked at the appropriate lines I have copy pasted before starting to teach me? I do not need to learn the kid stuff. I have a concrete question and need to know where is the error concretely. > They can't because a bit string literal > only has meaning when it contains the few characters that are allowed. Any user-defined literal or identifier falls into this category. Everything that user defines must consist solely of few allowed characters. But, it is again as informative as "the water is wet" above. Simply saying "only permitted characters make sense" does not point us to which of the characters are permitted exactly, isn't it? Can you stop speaking misteriously with insinuations, and start telling exactly which characters are defined legit in LRM. I do not tolerate when people ignore my questions or draw them into 0-information, I hate intellectual pretense and not going to learn trivial, obvious things. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 14:16:57 -0500 Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 19:14:22 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="ebddd0a34a37eb1d7028213a8f3d0ba6"; logging-data="1794"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/E0mseH1KMwLFVSoCJJCnp" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:BM4zct5OC9iGUCXtm/KfMOA+VNA= Xref: mx02.eternal-september.org comp.lang.vhdl:8710 On 12/27/2015 2:01 PM, valtih1978 wrote: > >> You mean you tried to implement the BNF which seems to not describe the >> language 100%.The VHDL spec is more than just the BNF lists. > > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the > problem that I address here is that BNF seems to contain a fatal error. > Saying that I see it because it does not specify the language 100% is a > little bit inappropriate, isn't it? It is like if instruction to go > shopping would instruct you to kill youself at one point. You may defend > the instruction saying that "it is incomplete" but this would make the > situation even more ridiculous. And it does. > >> To think that a bit literal can contain every letter of >> the alphabet is a bit silly. > > What if BNF admits every character? Have you ever looked at the > appropriate lines I have copy pasted before starting to teach me? I do > not need to learn the kid stuff. I have a concrete question and need to > know where is the error concretely. > >> They can't because a bit string literal >> only has meaning when it contains the few characters that are allowed. > > Any user-defined literal or identifier falls into this category. > Everything that user defines must consist solely of few allowed > characters. But, it is again as informative as "the water is wet" above. > Simply saying "only permitted characters make sense" does not point us > to which of the characters are permitted exactly, isn't it? > > Can you stop speaking misteriously with insinuations, and start telling > exactly which characters are defined legit in LRM. I do not tolerate > when people ignore my questions or draw them into 0-information, I hate > intellectual pretense and not going to learn trivial, obvious things. I have no idea what you are complaining about. You have the VHDL spec, it clearly says you can embed the quote character in a string by using two in succession. What are you going on about? Either implement the language or give up. I don't know any other alternatives. I've already suggested that you need to ignore the BNF where it is wrong. Or is there a useful question in there somewhere that I missed? If you want, send me a copy of the version of the spec you are implementing and I'll take a look to show you where the various strings are fully explained. I believe I have PDFs of each version other than 2008. -- Rick From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Sun, 27 Dec 2015 14:26:41 -0500 Organization: A noiseless patient Spider Lines: 64 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Dec 2015 19:24:06 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="68639cc5c98aed50d7aac76c23cb1a02"; logging-data="5066"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/+tYBjncw4CRwtkLyV2BDm" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: Cancel-Lock: sha1:9C6bovq/3NCLImuNedXxVkqqCe4= Xref: mx02.eternal-september.org comp.lang.vhdl:8711 On 12/27/2015 2:01 PM, valtih1978 wrote: > >> You mean you tried to implement the BNF which seems to not describe the >> language 100%.The VHDL spec is more than just the BNF lists. > > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the > problem that I address here is that BNF seems to contain a fatal error. > Saying that I see it because it does not specify the language 100% is a > little bit inappropriate, isn't it? It is like if instruction to go > shopping would instruct you to kill youself at one point. You may defend > the instruction saying that "it is incomplete" but this would make the > situation even more ridiculous. And it does. > >> To think that a bit literal can contain every letter of >> the alphabet is a bit silly. > > What if BNF admits every character? Have you ever looked at the > appropriate lines I have copy pasted before starting to teach me? I do > not need to learn the kid stuff. I have a concrete question and need to > know where is the error concretely. > >> They can't because a bit string literal >> only has meaning when it contains the few characters that are allowed. > > Any user-defined literal or identifier falls into this category. > Everything that user defines must consist solely of few allowed > characters. But, it is again as informative as "the water is wet" above. > Simply saying "only permitted characters make sense" does not point us > to which of the characters are permitted exactly, isn't it? > > Can you stop speaking misteriously with insinuations, and start telling > exactly which characters are defined legit in LRM. I do not tolerate > when people ignore my questions or draw them into 0-information, I hate > intellectual pretense and not going to learn trivial, obvious things. Here are the appropriate sections from the 1993 standard... String Literals String literals are composed as a sequence of graphic characters (letters, digits, special characters) enclosed between two quotation marks (double quotes). They are usually used for warnings or reports which are displayed during simulation (Example 3). Bit string literals Bit string literals represent values of string literals that denote sequences of extended digits, range of which depends on the specified base. The base specifier determines the base of the digits: letter B used as a base specifier denotes binary digits (0 or 1), letter O - octal digits (0 to 7) and letter X - hexadecimal (digits 0 to 9 and letters A to F, case insensitive). Underlines can be used to increase readability and have no impact on the value. All values specified as bit string literals are converted into binary representation without underlines. Binary strings remain unchanged (only underlines are removed), each octal digit is converted into three bits and each hexadecimal into four bits (Example 4). What is not clear about that? -- Rick From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.50.70.42 with SMTP id j10mr44361425igu.9.1451266391698; Sun, 27 Dec 2015 17:33:11 -0800 (PST) X-Received: by 10.50.97.37 with SMTP id dx5mr491938igb.8.1451266391680; Sun, 27 Dec 2015 17:33:11 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!usenet.blueworldhosting.com!feeder01.blueworldhosting.com!news.glorb.com!mv3no21973484igc.0!news-out.google.com!f6ni35649igq.0!nntp.google.com!mv3no15757239igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 17:33:10 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Mon, 28 Dec 2015 01:33:11 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8712 On Sunday, December 27, 2015 at 2:01:13 PM UTC-5, valtih1978 wrote: > > You mean you tried to implement the BNF which seems to not describe the > > language 100%.The VHDL spec is more than just the BNF lists. >=20 > Yes, I tried. Yes, BNF is incomplete and water is liquid. But the=20 > problem that I address here is that BNF seems to contain a fatal error.= =20 There is more to the language specification than the BNF. In this particul= ar case, the following text is relevant (all from VHDL-2008) Section 15.8 (Bit String Literals): "A bit string literal has a value that= is a string literal" Section 15.7 (String literals): "If a quotation mark value is to be represe= nted in the sequence of character values, then a pair of adjacent quotation= marks shall be written at the corresponding place within the string litera= l. (This means that a string literal that includes two adjacent quotation m= arks is never interpreted as two adjacent string literals.)" There is an example which shows that """" (four consecutive quotation marks= ) is a string literal of length 1. In order for two consecutive quotation = marks to be allowed as a 'special_character', it would have to define the q= uotation mark character to be one of the special characters since you can't= have two of something until you at least have one. They could possibly ha= ve added a footnote to indicate that really the special character is "", bu= t they didn't. But they did explain how you get a " by using "". If you w= ant to fixate that the BNF has a 'fatal error', knock yourself out, but to = do that you have to ignore what was specifically explained in section 15.7 = regarding the quotation mark. If you'd like another example of a discrepancy between BNF and the text, he= re you go... Section 5.2.3.1 (General Integer types) "An implementation may restrict the bounds of the range constraint of integ= er types other than type universal_integer. However, an implementation shall allow the declaration o= f any integer type whose range is wholly contained within the bounds -21474= 83647 and +2147483647 inclusive." Section 9.3.2 Literals "numeric_literal ::=3D abstract_literal | physical_literal Numeric literals include literals of the abstract types universal_integer a= nd universal_real, as well as literals of physical types. Abstract literals= are defined in 15.5; physical literals are defined in 5.2.4.1." So, clearly -1 should be considered a numeric literal. But now look at the= BNF. abstract_literals are numeric_literals. Section 15.5.1: abstract_literal ::=3D decimal_literal Section 15.5.2: decimal_literal ::=3D integer [ . integer ] [ exponent ] integer ::=3D digit { [ underline ] digit } exponent ::=3D E [ + ] integer | E - integer Now, where is the minus sign in the BNF? It's not there. So while the sec= tion that defines integer literals specifically says that -2147483647 is a = literal, the BNF does not support this since there is no way to put in the = minus sign per the BNF. So these two sections of the specification conflic= t. To me, a reasonable interpretation to make is that since there is a con= flict with the specification itself, that there should be no flagging of an= error by a tool if source code adheres to the narrative but not the BNF. = The BNF is no more 'correct' than narrative (unless there is such a disclai= mer somewhere in the specification that says so). So the text -1 should be= interpreted as an integer literal. Not all folks agree and they think tha= t the BNF must trump narrative and think that they are making their tool ad= here 'closer' to the standard by using this interpretation when it is conve= nient...but they are ignoring something specifically called out in the stan= dard. Oh well. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.182.236.4 with SMTP id uq4mr47117875obc.3.1451269363668; Sun, 27 Dec 2015 18:22:43 -0800 (PST) X-Received: by 10.50.132.67 with SMTP id os3mr567975igb.7.1451269363648; Sun, 27 Dec 2015 18:22:43 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no21985990igc.0!news-out.google.com!l1ni4535igd.0!nntp.google.com!mv3no21985984igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 18:22:42 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:352c:4b9:87c4:c93a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:352c:4b9:87c4:c93a References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Subject: Re: Physical unit ambiguities From: KJ Injection-Date: Mon, 28 Dec 2015 02:22:43 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8713 On Saturday, December 26, 2015 at 8:07:55 PM UTC-5, valtih1978 wrote: > Another ambiguity comes from > > literal ::= numeric_literal | enumeration_literal | ... > numeric_literal ::= physical_literal | ... > physical_literal ::= [ abstract_literal ] name > name ::= identifier | operator_symbol | character_literal | > selected_name | indexed_name | slice_name | attribute_name > enumeration_literal ::= identifier | ... > According to VHDL-2000, 2002 and 2008 physical_literal ::= [ abstract_literal ] unit_name physical_literal is not defined as you have posted as physical_literal ::= [ abstract_literal ] name 'unit_name' is not further defined in the specifications, however 'unit name' is defined. Darn those inconsistent humans anyway. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.129.154.197 with SMTP id r188mr17734102ywg.40.1451282639027; Sun, 27 Dec 2015 22:03:59 -0800 (PST) X-Received: by 10.50.97.37 with SMTP id dx5mr502051igb.8.1451282638998; Sun, 27 Dec 2015 22:03:58 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!6no1198859qgy.0!news-out.google.com!l1ni4726igd.0!nntp.google.com!mv3no22040833igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Sun, 27 Dec 2015 22:03:58 -0800 (PST) In-Reply-To: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.236.158.124; posting-account=6KYi7AkAAAB4jzIGHfoC8dQPm6eaLKkM NNTP-Posting-Host: 125.236.158.124 References: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Physical unit ambiguities From: diogratia@gmail.com Injection-Date: Mon, 28 Dec 2015 06:03:59 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8714 On Monday, December 28, 2015 at 3:22:46 PM UTC+13, KJ wrote: > On Saturday, December 26, 2015 at 8:07:55 PM UTC-5, valtih1978 wrote: > > Another ambiguity comes from > >=20 > > literal ::=3D numeric_literal | enumeration_literal | ... > > numeric_literal ::=3D physical_literal | ... > > physical_literal ::=3D [ abstract_literal ] name > > name ::=3D identifier | operator_symbol | character_literal |=20 > > selected_name | indexed_name | slice_name | attribute_name > > enumeration_literal ::=3D identifier | ... > >=20 >=20 > According to VHDL-2000, 2002 and 2008 > physical_literal ::=3D [ abstract_literal ] unit_name >=20 > physical_literal is not defined as you have posted as > physical_literal ::=3D [ abstract_literal ] name >=20 > 'unit_name' is not further defined in the specifications, however 'unit n= ame' is defined. Darn those inconsistent humans anyway. The unit_ part of unit_name is shown in italics, which has meaning: IEEE Std 1076-2008 1.3.2 Syntactic description: g) If the name of any syntactic category starts with an italicized part, it= is equivalent to the category name without the italicized part. The italic= ized part is intended to convey some semantic information. For example, typ= e_name and subtype_name are both syntactically equivalent to name alone. -- You can while away some time reading up on syntactic predicates. You could also read 5.2.4 Physical types paragraph 5 for the semantic meani= ng here: Each unit declaration (either the primary unit declaration or a secondary u= nit declaration) defines a unit name. Unit names declared in secondary unit= declarations shall be directly or indirectly defined in terms of integral = multiples of the primary unit of the type declaration in which they appear.= The position numbers of unit names need not lie within the range specified= by the range constraint. -- Para 7: The abstract literal portion (if present) of a physical literal appearing i= n a secondary unit declaration shall be an integer literal. -- And para 9: There is a position number corresponding to each value of a physical type. = The position number of the value corresponding to a unit name is the number= of primary units represented by that unit name. The position number of the= value corresponding to a physical literal with an abstract literal part is= the largest integer that is not greater than the product of the value of t= he abstract literal and the position number of the accompanying unit name. -- Essentially that unit name has to be a declared primary or secondary unit n= ame, despite trying to abstract it to simply a name. You could note that a = unit name is guaranteed to be represented by not just any name, a simple na= me, 1.3.2: h) The term simple_name is used for any occurrence of an identifier that al= ready denotes some declared entity. -- Also see 8.2 Simple names, the first sentence of the first paragraph: A simple name for a named entity is either the identifier associated with t= he entity by its declaration or another identifier associated with the enti= ty by an alias declaration. -- And the following BNF: simple_name ::=3D identifier -- So there's a semantic restriction that limits unit_name to the simple name = (an identifier) of a declared unit. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 13:08:50 -0000 (UTC) Organization: A noiseless patient Spider Lines: 76 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Dec 2015 13:08:50 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="da745e888d4a5182b5fda6212bbb0a63"; logging-data="22038"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18XdNnrdsxUARnleMUNHe2XxRjmHQ34z98=" User-Agent: Pan/0.139 (Sexual Chocolate; GIT bf56508 git://git.gnome.org/pan2) Cancel-Lock: sha1:jfPsYBky/qxOm+OTWgxLunuT9Ys= Xref: mx02.eternal-september.org comp.lang.vhdl:8715 On Sun, 27 Dec 2015 17:33:10 -0800, KJ wrote: > If you'd like another example of a discrepancy between BNF and the text, > here you go... > Section 5.2.3.1 (General Integer types) > "An implementation may restrict the bounds of the range constraint of > integer types other than type universal_integer. However, an > implementation shall allow the declaration of any integer type whose > range is wholly contained within the bounds -2147483647 and +2147483647 > inclusive." The term "literal" does not appear here, nor is there any statement that every valid value is directly representable as a literal. ( More precisely, any such statement is not part of the quoted material. I haven't found one elsewhere either) > Section 9.3.2 Literals "numeric_literal ::= abstract_literal | > physical_literal Numeric literals include literals of the abstract types > universal_integer and universal_real, as well as literals of physical > types. Abstract literals are defined in 15.5; physical literals are > defined in 5.2.4.1." Nor does this state that the range of literals covers the entire range of values. > So, clearly -1 should be considered a numeric literal. I think that requires an inference that is not stated in the quoted passages above. > But now look at > the BNF. abstract_literals are numeric_literals. > > Section 15.5.1: abstract_literal ::= decimal_literal Section 15.5.2: > decimal_literal ::= integer [ . integer ] [ exponent ] > integer ::= digit { [ underline ] digit } exponent ::= E [ + ] > integer | E - integer > > Now, where is the minus sign in the BNF? It's not there. Which suggests an alternative inference : only the naturals are representable as literals; negative values are expressed as the result of a negation operator on a positive literal. > So while the > section that defines integer literals specifically says that -2147483647 > is a literal, Where exactly? > the BNF does not support this since there is no way to put > in the minus sign per the BNF. So these two sections of the > specification conflict. The conflict exists only if the former section of the specification actually exists, which is not established by the quoted material. > To me, a reasonable interpretation to make is > that since there is a conflict with the specification itself, that there > should be no flagging of an error by a tool if source code adheres to > the narrative but not the BNF. But in the absence of conflict, there is no need to deviate from the BNF. > So the text -1 should be interpreted as an > integer literal. Not all folks agree and they think that the BNF must > trump narrative The BNF unambiguously parses -1 as [unary operator][literal]. If you additionally allow negative literals, how do you resolve the resulting ambiguous parsing? Considering also that operators are overloadable on return type... -- Brian From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.182.181.100 with SMTP id dv4mr48922935obc.47.1451313253666; Mon, 28 Dec 2015 06:34:13 -0800 (PST) X-Received: by 10.50.108.20 with SMTP id hg20mr830387igb.5.1451313253640; Mon, 28 Dec 2015 06:34:13 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no15889491igc.0!news-out.google.com!f6ni36253igq.0!nntp.google.com!mv3no22220957igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 06:34:13 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:352c:4b9:87c4:c93a; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:352c:4b9:87c4:c93a References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <5ebe89ed-617f-4cf5-a701-f1581e38b02f@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Mon, 28 Dec 2015 14:34:13 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8716 On Monday, December 28, 2015 at 8:11:29 AM UTC-5, Brian Drummond wrote: > On Sun, 27 Dec 2015 17:33:10 -0800, KJ wrote: >=20 > > If you'd like another example of a discrepancy between BNF and the text= , > > here you go... > > Section 5.2.3.1 (General Integer types) > > "An implementation may restrict the bounds of the range constraint of > > integer types other than type universal_integer. However, an > > implementation shall allow the declaration of any integer type whose > > range is wholly contained within the bounds -2147483647 and +2147483647 > > inclusive." >=20 > The term "literal" does not appear here, > More precisely, any such statement is not part of the quoted material. I= =20 > haven't found one elsewhere either) >=20 You didn't look too hard. I see you chose to write this before you read th= e next paragraph that I wrote or the section that I referenced in the speci= fication. Maybe you'll read it this time. section 5.2.3.1 (Integer types general) "Integer literals are the literals of an anonymous predefined type that is = called universal_integer in this standard. Other integer types have no lite= rals. However, for each integer type there exists an implicit conversion th= at converts a value of type universal_integer into the corresponding value = (if any) of the integer type (see 9.3.6)." > > Section 9.3.2 Literals "numeric_literal ::=3D abstract_literal | > > physical_literal Numeric literals include literals of the abstract type= s > > universal_integer and universal_real, as well as literals of physical > > types. Abstract literals are defined in 15.5; physical literals are > > defined in 5.2.4.1." >=20 > Nor does this state that the range of literals covers the entire range of= =20 > values. >=20 You've gone off the deep end now. The sections I've cited do establish the= range. > > So, clearly -1 should be considered a numeric literal. =20 >=20 > I think that requires an inference that is not stated in the quoted=20 > passages above. >=20 Then you're part of the small group that accepts: 1. "Integer literals are the literals of an anonymous predefined type that = is called universal_integer" (5.2.3.1) 2. "Numeric literals include literals of the abstract types universal_integ= er" (9.3.2) 3. "integer type whose range is wholly contained within the bounds -2147483= 647 and +2147483647 inclusive." (5.2.3.1) 4. "...may restrict the bounds of the range constraint of integer types oth= er than type universal_integer" 5.2.3.1 But do not think that -1 is a numeric literal. > >=20 > > Now, where is the minus sign in the BNF? It's not there. =20 >=20 > Which suggests an alternative inference : only the naturals are=20 > representable as literals; negative values are expressed as the result of= =20 > a negation operator on a positive literal. Which contradicts the previously cited section 5.2.3.1 "integer type whose = range is wholly contained within the bounds -2147483647 and +2147483647 inc= lusive." > > the BNF does not support this since there is no way to put > > in the minus sign per the BNF. So these two sections of the > > specification conflict.=20 >=20 > The conflict exists only if the former section of the specification=20 > actually exists, which is not established by the quoted material. >=20 It is established, you don't accept it. There is a difference. Or if you'= d prefer, I don't accept the position that you've put forth and you do not = accept mine. >=20 > The BNF unambiguously parses -1 as [unary operator][literal]. If you=20 > additionally allow negative literals, how do you resolve the resulting=20 > ambiguous parsing?=20 >=20 Correcting the problem is not my job, I'm simply pointing out the discrepan= cy. As you already know, the discrepancy has also been pointed out to the = proper authorities who decline official comment as representatives of the V= HDL standard. The narrative of the specification establishes that negative numbers are nu= meric literals. The BNF does not. If there is something in the language s= pecification that says the narrative can be ignored in case of a conflict w= ith the BNF, then you would do well to quote that rather than trundling dow= n the path you're on. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.182.142.8 with SMTP id rs8mr25000773obb.33.1451330284791; Mon, 28 Dec 2015 11:18:04 -0800 (PST) X-Received: by 10.50.36.3 with SMTP id m3mr856392igj.0.1451330284729; Mon, 28 Dec 2015 11:18:04 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!1.eu.feeder.erje.net!feeder.erje.net!2.us.feeder.erje.net!news.glorb.com!mv3no22341376igc.0!news-out.google.com!l1ni5330igd.0!nntp.google.com!mv3no22341365igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 11:18:04 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=98.176.234.81; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs NNTP-Posting-Host: 98.176.234.81 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Subject: Re: Literals UO"2C" = B"011_CCC"? From: Jim Lewis Injection-Date: Mon, 28 Dec 2015 19:18:04 +0000 Content-Type: text/plain; charset=ISO-8859-1 Xref: mx02.eternal-september.org comp.lang.vhdl:8717 The LRM is the conjunction of the BNF rules and the text. If a rule is concisely and accurately specified in the BNF, then there is no additional text. OTOH, some of the BNF is more general and the text provides further constraints. Perhaps you can download one of the free simulators and test out the cases you are concerned about. IE, how other simulators handle " in a string. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 22:46:32 +0200 Organization: A noiseless patient Spider Lines: 85 Message-ID: <56819FA8.90204@not.email.me> References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="4367"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193UY8/29vPgYe8oOemwjaKE+JtwYYTH44=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:RtgkkmBNcamJOq5rUZocGJteKUA= Xref: mx02.eternal-september.org comp.lang.vhdl:8718 On 28.12.2015 3:33, KJ wrote: > There is more to the language specification than the BNF. In this > particular case, the following text is relevant (all from VHDL-2008) > Section 15.7 (String literals): "If a quotation mark value is to > be represented in the sequence of character values, then a pair > of adjacent quotation marks shall be written at the corresponding > place within the string literal. (This means that a string literal > that includes two adjacent quotation marks is never interpreted as > two adjacent string literals.)" > There is an example which shows that """" (four consecutive quotation > marks) is a string literal of length 1. Yes, I know. We have established this already. > Section 15.8 (Bit String Literals): "A bit string literal has a > value that is a string literal" I have overlooked it indeed. But, think a little. What does it mean? IMO, it addresses the output of the conversion. The bit string literal is a function that takes integers in various bases and produces binary strings. It produces string literals. Binary vectors are nothing more than just string literals. There is a bit_string_literal form which allows you to avoid specifying every single bit (which is a pain even for short 8-bit words) in the more compact form, like 16"FFFFFFFF" instead of 32 ones. The bit string literal supports special characters for don't care-like bit strings. The standard just says that characters besides digits and "ABCDF" are copy-pasted into the output string literal. So, 16"F-" is translated into "1111----". The result is string_literal. This way, standard admits double quotes, if you place them instead of don't care '-' sign. Now, what does the fact that value is the same as quadrupled '"' character tell to us? What should the input bit_string_literal look like? Does LRM stipulate this case? Is it ok? And what should poor compiler do? To revise, string_literal ::= " { graphic_character } " bit_string_literal ::= [ integer ] base_specifier " [ bit_value ] " bit_value ::= graphic_character { [ underline ] graphic_character } graphic_character :: == something including quotation mark if user enters "" for every " in the parsed string_literal, what should be the input for bit_string_literal to achieve the same result? > If you'd like another example of a discrepancy between BNF and the text, here you go... > Section 5.2.3.1 (General Integer types) > "An implementation may restrict the bounds of the range constraint of integer types other than type > universal_integer. However, an implementation shall allow the declaration of any integer type whose range is wholly contained within the bounds -2147483647 and +2147483647 inclusive." > > Section 9.3.2 Literals > "numeric_literal ::= abstract_literal | physical_literal > Numeric literals include literals of the abstract types universal_integer and universal_real, as well as literals of physical types. Abstract literals are defined in 15.5; physical literals are defined in 5.2.4.1." > > So, clearly -1 should be considered a numeric literal. But now look at the BNF. abstract_literals are numeric_literals. > > Section 15.5.1: abstract_literal ::= decimal_literal > Section 15.5.2: decimal_literal ::= integer [ . integer ] [ exponent ] > integer ::= digit { [ underline ] digit } > exponent ::= E [ + ] integer | E - integer > > Now, where is the minus sign in the BNF? It's not there. So while the section that defines integer literals specifically says that -2147483647 is a literal, the BNF does not support this since there is no way to put in the minus sign per thre 'closer' to the standard by using this interpretation when it me, a reasonable interpretation to make is that since there is a conflict with the specification itself, that there should be no flagging of an error by a tool if source code adheres to the narrative but not the BNF. The BNF is no more 'correct' than narrative (unless there is such a disclaimer somewhere in the specification that says so). So the text -1 should be interpreted as an integer literal. Not all folks agree and they think that the BNF must trump narrative and think that they are making their tool adhere 'closer' to the standard by using this interpretation when it is convenient...but they are ignoring something specifically called out in the standard. Oh well. Uou say that narrative admits the negative integers whereas there is no way to enter them in BNF. You call it a contradiction but I do not see any problem here. You simply allocate internal variable of Int type for every literal that you keep in your tool and do not use the negative part of it. You will get negatives by applying the "-" operation to the literal, as Brain pointed out. It is fine. The user writes -100 and it is parsed as operation followed by literal. The code is parsed, elaboreated and smoothly processed further by the back end. It is not efficient but it is not stopper. Where is the conflict, where is the problem? I do not think that you can treat it equally with the issues that I have raised. The double quote and physical unit is simply unparsable. Yestuday, I have discovered one more conflict of this kind. function_call ::= name [(args)] How do you distinguish it from a simple identifier if arguments are not specified? From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Physical unit ambiguities Date: Mon, 28 Dec 2015 23:03:48 +0200 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <62ee3b9c-9ebd-4f7f-a33b-e73fb0f6ee8d@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Dec 2015 21:01:14 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="4eaed61cc34cf27306084f6070dcb276"; logging-data="8793"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ytq6p7nhVka+Hfbm9vZxbLusFtza8FNA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:Tzu6VMw4CSclP41SxB9hAq23p/I= Xref: mx02.eternal-september.org comp.lang.vhdl:8719 Ok, in such a complex way you seem to simply say that there is no chance that any other than simple name succeeds for the unit literal. This makes sense. Thanks. It seems that parser can reduce the physical_literal to physical_literal ::= [num] simple_name No, wait. I guess they have "abstracted" it to the more general name to enable extended names! In 2008 you can refer units in the other modules. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Mon, 28 Dec 2015 16:13:42 -0500 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Dec 2015 21:11:09 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="37ae68441c80f157b8b51f72be5b18c2"; logging-data="11211"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/M9qOVKl0wF7GXM+HknzwF" User-Agent: Mozilla/5.0 (Windows NT 6.2; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 In-Reply-To: <56819FA8.90204@not.email.me> Cancel-Lock: sha1:mOCvFn4rvq/TFeEZOKr6ZihbhuI= Xref: mx02.eternal-september.org comp.lang.vhdl:8720 On 12/28/2015 3:46 PM, valtih1978 wrote: > > How do you distinguish it from a simple identifier if arguments are not > specified? Context. It is not at all unusual for interpretation to depend on context. -- Rick From newsfish@newsfish Tue Dec 29 16:44:04 2015 X-Received: by 10.66.102.8 with SMTP id fk8mr49933600pab.40.1451358855785; Mon, 28 Dec 2015 19:14:15 -0800 (PST) X-Received: by 10.50.25.196 with SMTP id e4mr219696igg.8.1451358855754; Mon, 28 Dec 2015 19:14:15 -0800 (PST) Path: eternal-september.org!mx02.eternal-september.org!feeder.eternal-september.org!news.glorb.com!mv3no22502499igc.0!news-out.google.com!l1ni5694igd.0!nntp.google.com!mv3no22502498igc.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.vhdl Date: Mon, 28 Dec 2015 19:14:14 -0800 (PST) In-Reply-To: <56819FA8.90204@not.email.me> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2602:306:3b8f:3240:2046:4996:5ef9:af68; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd NNTP-Posting-Host: 2602:306:3b8f:3240:2046:4996:5ef9:af68 References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: Subject: Re: Literals UO"2C" = B"011_CCC"? From: KJ Injection-Date: Tue, 29 Dec 2015 03:14:15 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: mx02.eternal-september.org comp.lang.vhdl:8721 On Monday, December 28, 2015 at 3:46:36 PM UTC-5, valtih1978 wrote: > On 28.12.2015 3:33, KJ wrote: > > Section 15.8 (Bit String Literals): "A bit string literal has a > > value that is a string literal" >=20 > I have overlooked it indeed. >=20 Now, what does the fact that value is the same as quadrupled '"' > character tell to us? What should the input bit_string_literal look like? >=20 Section 15.8, says "For a character in the simplified value that is not int= erpreted as an extended digit, each character in the replacement sequence i= s the same as the character replaced." So if you run across a " or a "" in the input, it should be copied over as-= is into the output unchanged. > Does LRM stipulate this case? Is it ok? And what should poor compiler do? >=20 Since a " would end up not being a legal bit value when you're all done con= verting and an error is going to be flagged anyway, I would think a compile= r could stop and flag the error at that point. > Uou say that narrative admits the negative integers whereas there is no= =20 > way to enter them in BNF. You call it a contradiction but I do not see=20 > any problem here. You simply allocate internal variable of Int type for= =20 > every literal that you keep in your tool and do not use the negative=20 > part of it. You will get negatives by applying the "-" operation to the= =20 > literal, as Brain pointed out. It is fine. No it's not. There are instances where it mattered. One particular tool t= ook a declaration that had a negative number where a numeric literal was ex= pected and complained saying that it was not a numeric_literal. I don't want to hijack this thread to go into that issue any further. My o= nly point in bringing it up here is that since the LRM is produced by human= beings, it is not out of the question that the BNF does not comply with th= e narrative but that does not imply that the narrative is wrong. Unless sp= ecifically disclaimed, the whole document is on equal footing. >=20 > I do not think that you can treat it equally with the issues that I have= =20 > raised. Right, only things that you bring up are important. Gotcha. > The double quote and physical unit is simply unparsable.=20 Well, other tools I assume are able to parse it, although I admit I haven't= bothered to try to insert a " into a bit string to see what happens. I'm = only giving my take on why the "" appears to be the way to include the " an= d that the LRM does specify this (in my opinion, maybe not yours) > Yestuday, I have discovered one more conflict of this kind. >=20 > function_call ::=3D name [(args)] >=20 > How do you distinguish it from a simple identifier if arguments are not= =20 > specified? In your example, 'name' will be the name of the function that has already b= een defined previously in the source code as a function with no arguments. = The vocabulary keeps expanding as source code is processed. It starts wit= h only the keywords, then adds on everything else that gets declared. Not = sure why you see any issue here. Kevin Jennings From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Tue, 29 Dec 2015 11:09:30 +0200 Organization: A noiseless patient Spider Lines: 83 Message-ID: References: <48f16b17-80ce-4551-8e05-e69bccd4a799@googlegroups.com> <567F37E6.5090602@not.email.me> <567F97CE.2060508@not.email.me> <56819FA8.90204@not.email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 29 Dec 2015 09:06:55 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="907"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19PScKewGP7+796MlworTGE+PJ+n03cOKI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: Cancel-Lock: sha1:7tKR5rqE7Oalgl9FS29oYBrtBhI= Xref: mx02.eternal-september.org comp.lang.vhdl:8722 >> Now, what does the fact that value is the same as quadrupled '"' >> character tell to us? What should the input bit_string_literal look like? > Section 15.8, says "For a character in the simplified value that is not > interpreted as an extended digit, each character in the replacement sequence > is the same as the character replaced." > So if you run across a " or a "" in the input, it should be copied over as-is > into the output unchanged. And now my question again: what should user input look like? I can copy over '-' to get "----" in the resulting string literal value. What should user enter to get '"' instead of '-'? Saying 'copy, as-is' means that user should enter single "-mark in the bit vector literal instead of -mark, right? Or what? Meantime you say that they need to be duplicated to circumvent the BNF grammar. > Since a " would end up not being a legal bit value when you're all done > converting and an error is going to be flagged anyway, I would think > a compiler could stop and flag the error at that point. I have heard that several times already and never received the answer "why illegal". Who says 'illegal'? Why '-' is legal but '"' is illegal? Should I constrain legal bit string values to those used in bit or std_logic? My impression always was that user can define its own logic values and use whatever characters are legal in the enumeration. Why is '"' illegal? Is my convincing wrong? Moreover, you say that bit vector has the same values as string_literal. Does it mean that '"' is illegal in the string_literal? >> I do not think that you can treat it equally with the issues that I have >> raised. > > Right, only things that you bring up are important. Gotcha. First, this is a fascism. It is a fascism to say that "we are right because these are we". Secondly, this is your position. You say LRM creates a problem because your tool had a bug. But it is not, as we explained. Third, you say that this is mine position, despite I discuss the LRM rather than a bug in your tool. I have explained why there is no problem with negatives. You should point to a flaw in my logic rather than say that I must buy whatever you say or I am a unconscious bastard. >> The double quote and physical unit is simply unparsable. > Well, other tools I assume are able to parse it, although I admit I > haven't bothered to try to insert a " into a bit string to see what > happens. I have even looked in source code of such a tool. Why am I still here? > >> Yestuday, I have discovered one more conflict of this kind. >> >> function_call ::= name [(args)] >> >> How do you distinguish it from a simple identifier if arguments are not >> specified? > > In your example, 'name' will be the name of the function that has > already been defined previously in the source code as a function with > no arguments. The vocabulary keeps expanding as source code is processed. > It starts with only the keywords, then adds on everything else that gets > declared. Not sure why you see any issue here. Because "vocabulary" is the collection of scopes that you get during elaboration, which seems to be a step supposed to happen after the parse has finished. Meantime, VHDL seems to be context-sensitive language and cannot parse without elaborating immediately. That is to parse a(b), your parser must beware that a is a type or a function to choose a corresponding grammar production, whether it should be a type conversion or array indexing or function call. There should be elaborated model to tell you that. At the same time, LRM presents material as if elaboration is a thrid step following 1) parsing and 2) analysis. All tools that I have used perpetuate this approach when propose you to select the top level for elaboration after parsing completed. The dilemma "to combine elaboration with parsing or elaborate afterwards" leaves me very puzzled. Your hints suggest that I must combine the two. From newsfish@newsfish Tue Dec 29 16:44:04 2015 Path: eternal-september.org!mx02.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Literals UO"2C" = B"011_CCC"? Date: Tue, 29 Dec 2015 11:15:21 +0200 Organization: A noiseless patient Spider Lines: 18 Message-ID: <56824F29.7090403@not.email.me> References: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="355305ea6318fa0c6ba1ac3390909d2c"; logging-data="2013"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/nI02iZfzAK8lyUuhCuNyJYNwQxVAKHCA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-Reply-To: <4096a666-a77b-4a2c-98ec-fdeaa2f15ec3@googlegroups.com> Cancel-Lock: sha1:iOtXdKIeKLLhazpVIZUnTsuGLsg= Xref: mx02.eternal-september.org comp.lang.vhdl:8723 On 28.12.2015 21:18, Jim Lewis wrote: > The LRM is the conjunction of the BNF rules and the text. If a rule is > concisely and accurately specified in the BNF, then there is no additional text. > OTOH, some of the BNF is more general and the text provides further constraints. That was my impression. Thanks for explicating it. The problem is that I started this thread because I could not find the additional text on bis vector literals with embedded quote marks. Ok? > Perhaps you can download one of the free simulators and test out the cases you > are concerned about. IE, how other simulators handle " in a string. I have even looked into the source code of the tool. I am not convinced however that one implementation should be used as ultimate specification when LRM is unclear. Why cannot people at compl.lang.vhdl simply provide the missing narrative or point to the existing one?