From newsfish@newsfish Fri Feb 3 13:07:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Can one declare more than one signal on one line? From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 10:25:15 +0100 Message-ID: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:VrLHdifAoeUYoMcWw5q+84rfqiY= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 27 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=>e;7WNg^51kbJlfT[;@_ShYSB=nbEKnkkOoZn^kHoPehZEVG4aK_]RP;@H2onO>`Ol[NBH>dn2bR\d`N4HieUKKVCA=Sbn X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4279 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Can one write, e.g. in an architecture environment, == signal a, b, c: integer range 0 to 10 == ? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- The greatest good you can do for another is not just share your riches, but reveal to him his own. (Benjamin Disraeli) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOh3sACgkQM0LLzLt8MhwBeQCdG6OQUJ9WEQ0qWiK1Tc7xWcmi nDIAmgKXt0pKcvlopEda63aZwlLD17wq =ztLG -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:07:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.ag!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Quadruple assignment From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 11:45:56 +0100 Message-ID: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:F1BAwLimkS2Z4YUwZH4fXdIjJhI= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 31 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=k>Fk__F:2X31@QH[VaTAe9YSB=nbEKnk;71459NG41K_]RP;@H2o>O>`Ol[NBH>4Qae0d3VLJe71T;O>;oY7Q3 X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4280 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, Say you define == signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0; == where MAX_VALUE is a constant. My ghdl compiler will be okay with this statement, but what is its result? I would like to define sig1, sig2, sig3 and sig4 to be, initially, 0. But does that actually achieve what I want? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Men are more moral than they think, and far more immoral than they can imagine. (Sigmund Freud) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOmmMACgkQM0LLzLt8MhwCsgCeL5Wyg61PIBrvIrfWdgo3DWwg Ks8An2MDR1ZI1eg94AnABFWHDWlAIQX4 =kd8P -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:07:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Mon, 1 Nov 2010 05:09:38 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 86.111.223.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288613378 14813 127.0.0.1 (1 Nov 2010 12:09:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 12:09:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=86.111.223.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 06j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4281 On Nov 1, 10:45=A0am, Merciadri Luca wrote: > =3D=3D > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE :=3D 0; > =3D=3D > > where MAX_VALUE is a constant. My ghdl compiler will be okay with this > statement, but what is its result? Each of your four signals has the same subtype (0 to MAX_VALUE). The explicit initialization ":=3D0" is redundant, because any VHDL variable or signal is initialized to the left-most value in its value set; in your case that value is 0 anyway. All four signals will have 0 as their initialization value. Note that the initial value is associated with the subtype part of the declaration. It is not attached to each individual data object; it applies to all four of them. > But does that actually achieve what I want? Only you can answer that :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:07:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? Date: Mon, 1 Nov 2010 05:13:21 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288613601 16682 127.0.0.1 (1 Nov 2010 12:13:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 12:13:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.1 (15829) 14j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4282 On Nov 1, 9:25=A0am, Merciadri Luca wrote: > Can one write, e.g. in an architecture environment, > > =3D=3D > signal a, b, c: integer range 0 to 10 > =3D=3D > ? Yes, but wouldn't it be kinder to your readers and reviewers if you write subtype my_range is integer range 0 to 10; signal a : my_range; signal b : my_range; signal c : my_range; ? -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:07:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:30:00 +0100 Message-ID: <877hgxdvdz.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:Ych3XHKvqkCyv6roteiYfSKAwNE= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 44 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=Kj1HJd3TdOGSi^`20K04QCYSB=nbEKnkK71459NG4AK_]RP;@H2oNO>`Ol[NBH>DKMXJ_dg^BhGFJHF`K]idDH X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4283 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jonathan Bromley writes: > On Nov 1, 10:45 am, Merciadri Luca wrote: > >> == >> signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE := 0; >> == >> >> where MAX_VALUE is a constant. My ghdl compiler will be okay with this >> statement, but what is its result? > > Each of your four signals has the same subtype > (0 to MAX_VALUE). The explicit initialization ":=0" > is redundant, because any VHDL variable or signal is > initialized to the left-most value in its value set; > in your case that value is 0 anyway. All four > signals will have 0 as their initialization value. > > Note that the initial value is associated with > the subtype part of the declaration. It is not > attached to each individual data object; it > applies to all four of them. > >> But does that actually achieve what I want? Thanks. I did not know it! :-) - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- In matters of style, swim with the current; in matters of principle, stand like a rock. (Thomas Jefferson) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwNgACgkQM0LLzLt8MhxJwACeKXQNuw9b/r6HNoEuvLaCpStI NRAAn3Qn6Csb4hEWtME0lXKaXPrQik/m =gThP -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:07:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:33:26 +0100 Message-ID: <8739rldv89.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:uOE0BQPdu466euSqSzd6UQGjCWE= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 38 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=4P=9m4l=a\cb>:U6jKdTQlYSB=nbEKnkk71459NG4aK_]RP;@H2onO>`Ol[NBH>dKMXJ_dg^BhgFJHF`K]idDh X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4284 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jonathan Bromley writes: > On Nov 1, 9:25 am, Merciadri Luca wrote: > >> Can one write, e.g. in an architecture environment, >> >> == >> signal a, b, c: integer range 0 to 10 >> == >> ? > > Yes, but wouldn't it be kinder to your readers > and reviewers if you write > > subtype my_range is integer range 0 to 10; > signal a : my_range; > signal b : my_range; > signal c : my_range; Yes, exactly. Thanks for the tip. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- When making your choices in life, do not forget to live. (Samuel Johnson) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwaYACgkQM0LLzLt8MhwGDwCfZW9qH/2HdGWjfCihl7jd4zCb cpEAnjlzeuw53rvYk/g6aXFOW3T4kYgd =mM/K -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:07:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Two different `architecture' implementations? From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 14:38:53 +0100 Message-ID: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:E9LitQSyytBS2dmP8bYDr9So8Yo= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 54 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=1>iDM1J[mF_0Sc_VCmP]hZYSB=nbEKnk[71459NG4QK_]RP;@H2o^O>`Ol[NBH>TKMXJ_dg^BhWFJHF`K]idDX X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4285 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I generally write == architecture my_arch of my_stuff is - -- signal, etc., declarations begin process - -- var declarations begin - -- code end process; end my_arch; == but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden designs PTY., LTD., consultant), that he did it this way: == architecture my_arch of my_stuff is - -- signal, etc., declarations begin process is begin end process; end architecture my_arch; == There are two main differences between our approaches. The first is that he uses the `is' keyword after `process'. The second is that he writes `architecture' before the architecture's name, in the closing line of the architecture my_arch. Is there a reason to prefer one of the approaches to the other? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm =Qs9G -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:07:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t35g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Mon, 1 Nov 2010 06:49:17 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <907eb12b-b53d-4125-9737-aa376cbfa017@t35g2000yqj.googlegroups.com> References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288619359 1936 127.0.0.1 (1 Nov 2010 13:49:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 13:49:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000yqj.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4286 Both are optional. I prefer adding "is" after a process statement (after the sensitivity clause, if present), simply because it makes it read more like the other vhdl items that have their own declarative regions. I also prefer adding the "architecture" keyword after the end statement, before the name of the architecture, because most "end" statements have a keyword with them identifying what type of structure is being ended (end if, end loop, etc.) But it really boils down to personal preference. I don't mind a little extra typing for syntactic consistency. Andy From newsfish@newsfish Fri Feb 3 13:07:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!goblin1!goblin.stu.neva.ru!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Can one declare more than one signal on one line? Date: Mon, 1 Nov 2010 07:00:33 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <18b5f159-9132-4b64-921c-deecda782703@t13g2000yqm.googlegroups.com> References: <87mxptv1j8.fsf@merciadriluca-station.MERCIADRILUCA> <255c421a-632c-49ae-b854-b27a4b224569@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288620033 7946 127.0.0.1 (1 Nov 2010 14:00:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 1 Nov 2010 14:00:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4287 On Nov 1, 7:13=A0am, Jonathan Bromley wrote: > On Nov 1, 9:25=A0am, Merciadri Luca wrote: > > > Can one write, e.g. in an architecture environment, > > > =3D=3D > > signal a, b, c: integer range 0 to 10 > > =3D=3D > > ? > > Yes, but wouldn't it be kinder to your readers > and reviewers if you write > > subtype my_range is integer range 0 to 10; > signal a : my_range; > signal b : my_range; > signal c : my_range; > > ? > -- > Jonathan Bromley Kindness to readers/reviewers is often not quite so simple. If each signal declaration were followed by a comment about what the signal was for (as I often do), I would whole-heartedly agree with separate declarations. If I'm trying to get the point across that all three are the same type, that is communicated most effectively if they are declared in the same statement. Of course, that does not mean that I would declare all of my std_logic (or boolean) signals with one statement either. For example, I very rarely use a dual-process (combinatorial & clocked) representation, but when I do, I prefer to declare the combinatorial and register signals in the same statement (with an end- of-line comment that defines the data held by both, the names will identify which is the reg). Andy From newsfish@newsfish Fri Feb 3 13:07:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!news.net.uni-c.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> <907eb12b-b53d-4125-9737-aa376cbfa017@t35g2000yqj.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Mon, 01 Nov 2010 15:57:17 +0100 Message-ID: <87wroxum5u.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:UzEENIk6t86YWwK93Hhe7ZKVJTw= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 36 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=Q`G4QK_]RP;@H2o^O>`Ol[NBH>T^T9NAEJJNBSRR\U@^P4?eP X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4288 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Andy writes: > Both are optional. I prefer adding "is" after a process statement > (after the sensitivity clause, if present), simply because it makes it > read more like the other vhdl items that have their own declarative > regions. > > I also prefer adding the "architecture" keyword after the end > statement, before the name of the architecture, because most "end" > statements have a keyword with them identifying what type of structure > is being ended (end if, end loop, etc.) I agree with you on both points. > But it really boils down to personal preference. I don't mind a little > extra typing for syntactic consistency. You're right. I just thought there was some subtle difference on another point of view than aesthetic considerations, but apparently not. Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Luck is what happens when preparation meets opportunity. (Lucius Annaeus Seneca) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzO1UwACgkQM0LLzLt8MhyazACfX8Qv9HfOhZJ1za2a0vOaMPhS VGwAnAon0L2ixNe9C0Qvn6Kt8ZyKBEdt =hTgf -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l17g2000yqe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Mon, 1 Nov 2010 23:16:30 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288678590 32600 127.0.0.1 (2 Nov 2010 06:16:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 06:16:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l17g2000yqe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4289 On 1 Nov., 14:38, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I generally write > > == > architecture my_arch of my_stuff is > - -- signal, etc., declarations > begin > process > - -- var declarations > begin > - -- code > end process; > end my_arch; > == > > but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden > designs PTY., LTD., consultant), that he did it this way: > > == > architecture my_arch of my_stuff is > - -- signal, etc., declarations > begin > process is > begin > end process; > end architecture my_arch; > == > > There are two main differences between our approaches. The first is > that he uses the `is' keyword after `process'. The second is that he > writes `architecture' before the architecture's name, in the closing > line of the architecture my_arch. > > Is there a reason to prefer one of the approaches to the other? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln) > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld > JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm > =Qs9G > -----END PGP SIGNATURE----- Hi Merciadri. every few years the VHDL standard gets reworked. Beginning with first release in 1987, then came 1993 which should now be accepted by all tools. 2002 was next and most of the changes should be available in the tools. 2008 is the latest change but the tools just started to adopt the new stuff. In your simulator there may be a compile switch to select the allowed standard (e.g. modelsims vcom: -87 -93-2002). While both of your code examples will pass vcom with the -93 or -2002 option, I suspect that the second example will fail with the -87 option enabled. Just give it a try. Have a nice simulation Eilert From newsfish@newsfish Fri Feb 3 13:08:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: April Andy Newsgroups: comp.lang.vhdl Subject: Boracay Weather Forecast Date: Tue, 2 Nov 2010 00:39:50 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <8f83eabe-2b49-441c-85b7-acb0a60d5ae5@s4g2000yql.googlegroups.com> NNTP-Posting-Host: 122.144.115.238 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288683590 11439 127.0.0.1 (2 Nov 2010 07:39:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 07:39:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=122.144.115.238; posting-account=Lh1MHAoAAAAJRapwydaEfYdCvKe3AE53 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.1.15) Gecko/20101026 Firefox/3.5.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4290 I'd like to know what's the perfect time to visit the Philippines? I'd like to go to Boracay and wonder where I can get the best and accurate Boracay Weather Forecast in the Philippines? I'd like to visit Boracay island and enjoy all sorts of activities in the day within the island, such as day sports,Paraw, Paragliding, sunbathing, island hopping and so much more. You can go partying until the wee hours of the morning, immerse in the local talents of fire dancers, or better yet enjoy the warm ocean breeze while sipping pi=F1a colada by the seashore. So better visit the Island when The Weather is good. For more information, visit http://www.BoracayWeather.com From newsfish@newsfish Fri Feb 3 13:08:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Declaration hides port port_name / Port port_name hidden by declaration in architecture From: Merciadri Luca Organization: ULg Date: Tue, 02 Nov 2010 12:41:13 +0100 Message-ID: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:ea7nE0X3BJh1VVgUh/VNA8auXWg= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 26 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=YMn12QG4aK_]RP;@H2onO>`Ol[NBH>dfSJQkLI]17dY31n6hZd6Oj X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4291 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, When copiling a .vhd that I wrote these days, I get no errors with GHDL, but warnings such as `Declaration hides port port_name' and `Port port_name hidden by declaration in architecture.' Any idea of what it could be caused by? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Remember, no one can make you feel inferior, without your consent. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 =8Qmi -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!p1g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Declaration hides port port_name / Port port_name hidden by declaration in architecture Date: Tue, 2 Nov 2010 06:29:03 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288704543 6363 127.0.0.1 (2 Nov 2010 13:29:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 13:29:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p1g2000yqm.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4292 On Nov 2, 6:41=A0am, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > When copiling a .vhd that I wrote these days, I get no errors with > GHDL, but warnings such as `Declaration hides port port_name' and > `Port port_name hidden by declaration in architecture.' > > Any idea of what it could be caused by? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > Remember, no one can make you feel inferior, without your consent. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p > 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 > =3D8Qmi > -----END PGP SIGNATURE----- You have probably declared a signal in the architecture with the same name as a port on the entity. Thus you have no way to access the port from within the architecture. Andy From newsfish@newsfish Fri Feb 3 13:08:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Tue, 2 Nov 2010 10:36:33 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 188.28.190.41 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288719393 11623 127.0.0.1 (2 Nov 2010 17:36:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 17:36:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=188.28.190.41; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4293 On Oct 22, 4:33=A0pm, Paul Uiterlinden wrote: > jacko wrote: > > Don't be afraid to apparently duplicate a lot of code. This refers to > > say having 2 copies of a case statement with differing when clauses > > based on some outer state of the machine being coded. It does not > > consume many extra resources, and can lead to a better data flow. > > What do yo mean with "apparently duplicate a lot of code"? If it really > means copying and pasting a lot of code, I would object. It will result i= n > hard to mantain code. I thoroughly dislike copy-and-paste code. case A when a =3D> case B when b =3D> case B In this example the case B structure is repeated/duplicated. Although it may seem like a good idea to combine the case B into one case and then test case A internally, often the process structure suggest one way as better, case is better than if most of the time because it will warn more than if. Real vs. apparent, copy case delete assignments, put new in context assignments. best hardware performance is often achieved with not with the most beautiful simple code, but with the necessary code to dataflow the signals to pass through a minimal of logic and placing all logic before the flip flop. Look up 'Moore State Machine' which is preferred to a Mealey machine in synchronous design. Cheers Jacko From newsfish@newsfish Fri Feb 3 13:08:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: Merciadri Luca Newsgroups: comp.lang.vhdl Subject: Re: Two different `architecture' implementations? Date: Tue, 2 Nov 2010 13:21:10 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: <87y69dcgeq.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 85.26.2.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288729270 3653 127.0.0.1 (2 Nov 2010 20:21:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 2 Nov 2010 20:21:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=85.26.2.239; posting-account=V6LrigoAAACudvZ0KlT32AF1BSfjssFY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.0.19) Gecko/2010072023 Firefox/3.0.6 (Debian-3.0.6-3),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4294 On Nov 2, 7:16=A0am, backhus wrote: > On 1 Nov., 14:38, Merciadri Luca > wrote: > > > > > -----BEGIN PGP SIGNED MESSAGE----- > > Hash: SHA1 > > > Hi, > > > I generally write > > > =3D=3D > > architecture my_arch of my_stuff is > > - -- signal, etc., declarations > > begin > > process > > - -- var declarations > > begin > > - -- code > > end process; > > end my_arch; > > =3D=3D > > > but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden > > designs PTY., LTD., consultant), that he did it this way: > > > =3D=3D > > architecture my_arch of my_stuff is > > - -- signal, etc., declarations > > begin > > process is > > begin > > end process; > > end architecture my_arch; > > =3D=3D > > > There are two main differences between our approaches. The first is > > that he uses the `is' keyword after `process'. The second is that he > > writes `architecture' before the architecture's name, in the closing > > line of the architecture my_arch. > > > Is there a reason to prefer one of the approaches to the other? > > > Thanks. > > - -- > > Merciadri Luca > > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > > - -- > > > You can fool all of the people some of the time, some of the people all= of the time, but you can't fool all of the people all of the time. (Abraha= m Lincoln) > > -----BEGIN PGP SIGNATURE----- > > Version: GnuPG v1.4.9 (GNU/Linux) > > Comment: Processed by Mailcrypt 3.5.8 > > > iEYEARECAAYFAkzOwuwACgkQM0LLzLt8MhxR6ACfYQjriXTSFL//tixAmPpq8Nld > > JM0AoJ8C3yx/nc11jJi6vcM7tnSw5Agm > > =3DQs9G > > -----END PGP SIGNATURE----- > > Hi Merciadri. > every few years the VHDL standard gets reworked. > Beginning with first release in 1987, then came 1993 which should now > be accepted by all tools. > 2002 was next and most of the changes should be available in the > tools. > 2008 is the latest change but the tools just started to adopt the new > stuff. > > In your simulator there may be a compile switch to select the allowed > standard (e.g. modelsims vcom: -87 -93-2002). > While both of your code examples will pass vcom with the -93 or -2002 > option, > I suspect that the second example will fail with the -87 option > enabled. > > Just give it a try. > Have a nice simulation > =A0 Eilert Thanks for pointing this out. From newsfish@newsfish Fri Feb 3 13:08:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Declaration hides port port_name / Port port_name hidden by declaration in architecture References: <874oc0gdgm.fsf@merciadriluca-station.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Tue, 02 Nov 2010 21:23:53 +0100 Message-ID: <87aalrjwyu.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:IZ83Gfh06B3wbZUAhkTW5J5SPQQ= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 53 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=5G41K_]RP;@H2o>O>`Ol[NBH>4oGK4^hS99d>:c@X[;\3KR6 X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4295 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Andy writes: > On Nov 2, 6:41 am, Merciadri Luca > wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Hi, >> >> When copiling a .vhd that I wrote these days, I get no errors with >> GHDL, but warnings such as `Declaration hides port port_name' and >> `Port port_name hidden by declaration in architecture.' >> >> Any idea of what it could be caused by? >> >> Thanks. >> - -- >> Merciadri Luca >> Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ >> - -- >> >> Remember, no one can make you feel inferior, without your consent. >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.9 (GNU/Linux) >> Comment: Processed by Mailcrypt 3.5.8 >> >> iEYEARECAAYFAkzP+NkACgkQM0LLzLt8MhwergCgpxHce968uKHS36nnqCMUnY5p >> 5JkAnigx13WO2FsE9eUP8Agkm8Vkuav4 >> =8Qmi >> -----END PGP SIGNATURE----- > > You have probably declared a signal in the architecture with the same > name as a port on the entity. Thus you have no way to access the port > from within the architecture. Exactly. Thanks! - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- God is a comedian playing to an audience too afraid to laugh. (Voltaire) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzQc1kACgkQM0LLzLt8MhyHPgCeLPBh8u6c+v0GRm0z7A0lWHLW GrcAn2IKdzGp5VGnXmTD8bsBjVFFU0uA =Yx7q -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Tue, 02 Nov 2010 16:05:51 -0700 Lines: 24 Message-ID: <8jbjq4F97uU1@mid.individual.net> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vLZSnFG9z6UrU9gdIgpZ8QofA1JflCh5yYjAOUz1ZIiPq/QTaN Cancel-Lock: sha1:EYMFnzjUEoYntOX7xE9udNGNmHQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4296 On 11/2/2010 10:36 AM, jacko wrote: > > case A > when a => case B > when b => case B > > In this example the case B structure is repeated/duplicated. I agree that duplicating a case expression is sometimes easier to read than a long elsif. > Look up > 'Moore State Machine' which is preferred to a Mealey machine in > synchronous design. If you mean that a design with output registers is usually preferred to one without, I agree. Or if you mean that pipelining for timing closure involves some trial and error, I agree. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 03 Nov 2010 16:07:15 +0000 Organization: TRW Conekt Lines: 26 Message-ID: References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 85cuRHZ/wmulknvZ2gkzrwvl4PRAqMZWQZFsrXjnqgo4xRGi8= Cancel-Lock: sha1:8skjLd8baQh73nt/ANKvCH7JYss= sha1:7DSQkXPoTpC6GUJP5xZae2werq0= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4298 Mike Treseler writes: > On 11/2/2010 10:36 AM, jacko wrote: >> >> case A >> when a => case B >> when b => case B >> >> In this example the case B structure is repeated/duplicated. > > > I agree that duplicating a case expression is sometimes > easier to read than a long elsif. > But for ease of maintenance, I'd tend to move the duplicated content to a subprogram and call it from both cases, rather than copy/paste. Too easy to forget to update both sides when something changes. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:08:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 03 Nov 2010 11:39:37 -0700 Lines: 25 Message-ID: <8jdoisFebpU1@mid.individual.net> References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 7mHveXqD4G6Mb389FD/zQQb3UkportvY/AmJj4GfJ6/Avt24uU Cancel-Lock: sha1:BEPf5GGVQ1WUfkmSCsabPIBbxUk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4299 >> On 11/2/2010 10:36 AM, jacko wrote: >>> case A >>> when a => case B >>> when b => case B >>> >>> In this example the case B structure is repeated/duplicated. Mike Treseler wrote: >> I agree that duplicating a case expression is sometimes >> easier to read than a long elsif. On 11/3/2010 9:07 AM, Martin Thompson wrote: > But for ease of maintenance, I'd tend to move the duplicated content > to a subprogram and call it from both cases, rather than copy/paste. > Too easy to forget to update both sides when something changes. Good point. -- Mike Treseler ____________________________ case A_v is when a => my_fn(B); when b => my_fn(B); when c => my_fn(Z); end case; From newsfish@newsfish Fri Feb 3 13:08:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!fh19g2000vbb.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Best advice for FPGA/VHDL beginner? Date: Wed, 3 Nov 2010 12:10:18 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <5a22238a-2396-4666-88e0-a39671b6c750@o23g2000prh.googlegroups.com> <6ac49a79-28ff-4256-9e7d-74eaa4ebe838@e14g2000yqe.googlegroups.com> <4cc1bce7$0$81485$e4fe514c@news.xs4all.nl> <8fa68fac-eb80-40d6-9c1a-665a5af3b9a7@y23g2000yqd.googlegroups.com> <8jbjq4F97uU1@mid.individual.net> NNTP-Posting-Host: 188.28.123.144 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288811418 16853 127.0.0.1 (3 Nov 2010 19:10:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 3 Nov 2010 19:10:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fh19g2000vbb.googlegroups.com; posting-host=188.28.123.144; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.6.30 Version/10.63,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4300 On Nov 2, 11:05=A0pm, Mike Treseler wrote: > On 11/2/2010 10:36 AM, jacko wrote: > > > > > case A > > =A0 =A0when a =3D> =A0case B > > =A0 =A0when b =3D> =A0case B > > > In this example the case B structure is repeated/duplicated. > > I agree that duplicating a case expression is sometimes > easier to read than a long elsif. > > > Look up > > 'Moore State Machine' which is preferred to a Mealey machine in > > synchronous design. Another example was duplicating a register for to separate uses of the content. While increasing fan in, it can reduce fan out, which is preferred for a low fan in signal set anyhow when it has a high fan out. This fan balancing can be useful. Some tools can do this balancing automatically, but sometimes the differing content of register possibility can be used to good effect. Some tools automatically throw logic to the other side of the flip flop to balance logic complexity between flops. > If you mean that a design with output registers > is usually preferred to one without, I agree. Yes, design with registered output. Registered input is also a good idea... It does let full clock speed of device be used, but with external memory say, it needs an extra clock state in the state machine. > Or if you mean that pipelining for timing closure > involves some trial and error, I agree. Yes this relates to the above, I had a case where some logic on the inputs before the first register, and the delay cycle was not acceptable, so the auto logic movement was used to good effect. In the X3 I may explicitly do this adjustment by using a variable combinational of register output instead of an if then selecting register input. It's that annoying feeling of SRAM access delay PLUS some logic delay, before the clock, and expressing this to the tool. This is preferable to a 20% speed penalty as the critical path is elsewhere. The splitting fan of the inputs, can cause a bit of a headache as you decide on the fast input register meaning, as there is likely to only be one per input.... Cheers Jacko http://nibz.googlecode.com From newsfish@newsfish Fri Feb 3 13:08:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: boolean operations on "integer" in VHDL'93 Date: Thu, 04 Nov 2010 12:28:31 +0100 Organization: Aioe.org NNTP Server Lines: 14 Message-ID: NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4301 Hello, I really miss the "or", "and", "xor", "not", "shr", "shl" etc. operators in the "integer" type. To my knowledge, they are available only for the types like std_(u)logic(_vector) but they are... slow. I would like to do some quick behavioural stuff and I'm ready to code some extensions to my favorite simulator (GHDL) but I wonder if anyone knows an existing solution. Any hint ? Did I miss something ? yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Feb 3 13:08:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 04 Nov 2010 15:28:33 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Thu, 04 Nov 2010 20:37:54 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 17 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-JAzLiGW1d5hQjW/eKWwvOxKNOSTfNIZCOXCD9Dvr2U0z5Sz/74bpYoPpzPH4XksSTYKJ5vkHq69HTYw!EZRdJIUMhkfV+bH2FpMtWHuhk/B5ETEKLUjNkWl56AoZleiRZLt7BuauITmo5MLe6lxoIXg4icMX!O+A= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1688 Xref: feeder.eternal-september.org comp.lang.vhdl:4302 On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >Hello, > >I really miss the "or", "and", "xor", "not", "shr", "shl" etc. >operators in the "integer" type. To my knowledge, they are available >only for the types like std_(u)logic(_vector) but they are... slow. >I would like to do some quick behavioural stuff and >I'm ready to code some extensions to my favorite simulator >(GHDL) but I wonder if anyone knows an existing solution. > >Any hint ? Did I miss something ? bit_vector should be less heavyweight than std_logic_vector. - Brian From newsfish@newsfish Fri Feb 3 13:08:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: Matt Longbrake Newsgroups: comp.lang.vhdl Subject: Generate statement with varying signal width Date: Thu, 4 Nov 2010 14:19:31 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 134.131.125.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288905572 17274 127.0.0.1 (4 Nov 2010 21:19:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Nov 2010 21:19:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=134.131.125.49; posting-account=MSTlZgoAAAD_zHgCSsJ-fGgs0cHA71At User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11 GTB7.1 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4303 Is there any way to use a signal from a previous generate loop iteration in a later iteration? As an example, say you were building a variable length adder chain. The output of each adder is one bit wider than the previous adder. The inelegant solution would be to create an array of std_logic_vector where the width of each vector is as wide as the widest needed. These vectors are just selected based on the loop index. The problem with this is that you get all kinds of unused signal warnings when you synthesize. As an alternative approach, you could use the declarative region of the generate loop to create a signal of the appropriate width for the current iteration. Then, if you could somehow access that signal from the next iteration you could have variable width signals and avoid a bunch of warnings. Is something like this possible? From newsfish@newsfish Fri Feb 3 13:08:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed2-b.proxad.net!nnrp4-1.free.fr!not-for-mail Date: Thu, 04 Nov 2010 23:13:47 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 15 Message-ID: <4cd3301c$0$10046$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 04 Nov 2010 23:13:48 MET NNTP-Posting-Host: 82.246.229.10 X-Trace: 1288908828 news-3.free.fr 10046 82.246.229.10:52064 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4304 Le 04/11/2010 12:28, whygee a crit : > Hello, > > I really miss the "or", "and", "xor", "not", "shr", "shl" etc. > operators in the "integer" type. To my knowledge, they are available > only for the types like std_(u)logic(_vector) but they are... slow. > I would like to do some quick behavioural stuff and > I'm ready to code some extensions to my favorite simulator > (GHDL) but I wonder if anyone knows an existing solution. > > Any hint ? Did I miss something ? That's strong typing for you... Nicolas From newsfish@newsfish Fri Feb 3 13:08:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g26g2000vba.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: combinatorial process not simulating correctly Date: Thu, 4 Nov 2010 16:33:34 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288913615 24820 127.0.0.1 (4 Nov 2010 23:33:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 4 Nov 2010 23:33:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g26g2000vba.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13083 comp.lang.vhdl:4305 Hi, I coded a combinatorial process. However when simulated in Modelsim, the output does not change when my input which is in the process sensitivity list changes.the output remains constant and takes into account only the initial value of my input. when i add a clk to my sensitivity list, i get the expected output. However my process should be combinatorial! there is nothing wrong with my SIMPLE combinatorial process. any help please?? I used ISE synthesiser tool to synthesise my programs . CHEERS From newsfish@newsfish Fri Feb 3 13:08:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed-00.mathworks.com!newsfeed2.dallas1.level3.net!news.level3.com!bos-service1.raytheon.com!bos-service2b.ext.ray.com.POSTED!53ab2750!not-for-mail Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly From: Ian Shef References: Message-ID: User-Agent: Xnews/06.08.25 Lines: 28 Date: Fri, 05 Nov 2010 00:35:23 GMT NNTP-Posting-Host: 147.24.143.70 X-Complaints-To: news@ext.ray.com X-Trace: bos-service2b.ext.ray.com 1288917323 147.24.143.70 (Fri, 05 Nov 2010 00:35:23 UTC) NNTP-Posting-Date: Fri, 05 Nov 2010 00:35:23 UTC Organization: Raytheon Company Xref: feeder.eternal-september.org comp.arch.fpga:13084 comp.lang.vhdl:4306 Angus wrote in news:cc605b18-e83d-4ffd-82a9- 6b13ac150ee8@g26g2000vba.googlegroups.com: > Hi, > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes.the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . > > CHEERS > My crystal ball is broken today, and my extra-sensory perception doesn't seem to reach to your location. :-) Please provide your code. All of it. Pasted, not re-typed. I read your posting in comp.arch.fpga, but I am going to guess (since you didn't provide much information) that because you also posted to comp.lang.vhdl then your code is probably VHDL. Maybe it is not as SIMPLE and as combinatorial as you think. Thanks! From newsfish@newsfish Fri Feb 3 13:08:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:38:59 +0000 (UTC) Organization: A noiseless patient Spider Lines: 25 Message-ID: References: Injection-Date: Fri, 5 Nov 2010 00:38:59 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="27891"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NCndu2ILyCZ7WY1KhuYzJ" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:XjZr8PfAmxJ86VyHX1aUbIrpUms= Xref: feeder.eternal-september.org comp.arch.fpga:13085 comp.lang.vhdl:4307 In comp.arch.fpga Angus wrote: > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes. That seems to mean that it isn't combinatorial. > the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. It shouldn't have a clock, so how can you add one? OK, if you add to the sensitivity list and the output changes when that new signal changes, then it seems that the input is not in the sensitivity list. Could it be spelled wrong, so that it looks like it is in the list? > However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . -- glen From newsfish@newsfish Fri Feb 3 13:08:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!multikabel.net!newsfeed20.multikabel.net!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!n32g2000prc.googlegroups.com!not-for-mail From: Amal Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Thu, 4 Nov 2010 17:44:02 -0700 (PDT) Organization: http://groups.google.com Lines: 45 Message-ID: References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 119.194.48.102 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288917843 5787 127.0.0.1 (5 Nov 2010 00:44:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 00:44:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000prc.googlegroups.com; posting-host=119.194.48.102; posting-account=aaW8HAkAAABqrMdJYSf-acWh2T9ofAYm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.11 (KHTML, like Gecko) Chrome/9.0.570.0 Safari/534.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4308 On Nov 4, 5:19=A0pm, Matt Longbrake wrote: > Is there any way to use a signal from a previous generate loop > iteration in a later iteration? =A0As an example, say you were building > a variable length adder chain. =A0The output of each adder is one bit > wider than the previous adder. =A0The inelegant solution would be to > create an array of std_logic_vector where the width of each vector is > as wide as the widest needed. =A0These vectors are just selected based > on the loop index. =A0The problem with this is that you get all kinds of > unused signal warnings when you synthesize. > > As an alternative approach, you could use the declarative region of > the generate loop to create a signal of the appropriate width for the > current iteration. =A0Then, if you could somehow access that signal from > the next iteration you could have variable width signals and avoid a > bunch of warnings. =A0Is something like this possible? There are a number of things you can do. You can declare signals outside the generate block and make an assignment based on generate index: signal a : std_logic_vector(7 downto 0); signal b : std_logic; g_test: for i in 0 to 7 generate if ( i =3D 0 ) then b <=3D a(i); end if end generate : g_test The other option you are looking for is possible by declaring signals within the generate for: g_test: for i in 0 to 7 generate signal x : std_logic_vector(i+2 downto 0); x(i+2 downto 0) <=3D whatever; end generate : g_test In this case, you will have 8 x's defined as: x(2:0), x(3:0), ... x(9:0). But only accessible within the generate block. Cheers, -- Amal From newsfish@newsfish Fri Feb 3 13:08:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 05:30:12 +0100 Organization: Aioe.org NNTP Server Lines: 21 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4309 Hi ! Brian Drummond wrote: > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >> Any hint ? Did I miss something ? > bit_vector should be less heavyweight than std_logic_vector. sure but i want to use integers :-/ > - Brian Nicolas Matringe wrote : > That's strong typing for you... it's not a problem of typing, i can create new functions, however I see nowhere an explanation of these missing operations. why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) and not on integer, as in any other language ? > Nicolas yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Feb 3 13:08:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f33g2000yqh.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:21:22 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288941682 21033 127.0.0.1 (5 Nov 2010 07:21:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:21:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000yqh.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13090 comp.lang.vhdl:4310 all right here you go (I read there was A problem with MODELSIM in simulating combinatorial processes): SIGNAL DATA1 : Data_t:=(7,3,2); SIGNAL DATA2 : Data_t :=(9,5,1); PROCESS (SEL) BEGIN -- CASE SEL IS WHEN "00" =>temp<=DATA1; WHEN "01" =>temp<=DATA2; WHEN OTHERS =>NULL; END CASE; Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1), 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); END PROCESS; when i change SEL in my testbench, Data does not change. I had to embed my CASE within a clk edge detection to see the changes on modelsim CHEERS From newsfish@newsfish Fri Feb 3 13:08:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!t13g2000yqm.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:24:42 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <82821ba5-b77f-4059-9ea4-62c311d1d9c8@t13g2000yqm.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288941882 19983 127.0.0.1 (5 Nov 2010 07:24:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:24:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000yqm.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13091 comp.lang.vhdl:4311 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS i forgot to add SIGNAL temp : Data_t ; From newsfish@newsfish Fri Feb 3 13:08:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f33g2000yqh.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 00:24:46 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <95c5cdc7-2603-4c91-a54b-e145df0afd56@f33g2000yqh.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288941886 19994 127.0.0.1 (5 Nov 2010 07:24:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:24:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000yqh.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4312 On 5 Nov., 05:30, whygee wrote: > Hi ! > > Brian Drummond wrote: > > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: > >> Any hint ? Did I miss something ? > > bit_vector should be less heavyweight than std_logic_vector. > > sure but i want to use integers :-/ > > =A0> - Brian > > Nicolas Matringe wrote : > =A0> That's strong typing for you... > it's not a problem of typing, i can create new functions, > however I see nowhere an explanation of these missing operations. > why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) > and not on integer, as in any other language ? > > =A0> Nicolas > yg > --http://ygdes.com/http://yasep.org Hi, maybe it's because integers were not intended to be used for your logic data. They are made for array indexing and loop counting stuff, where the need for logic functions is neglectible. If you want to do convenient algorithmic stuff with VHDL use numeric_std types signed and unsigned. While the std_logic types need more computing time in your simulator, the advantage is that they are not limited to 32 bit max. width. You may not need this in your current project, but maybe somewhen. Have a nice simulation Eilert From newsfish@newsfish Fri Feb 3 13:08:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e14g2000yqe.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:27:59 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288942079 21701 127.0.0.1 (5 Nov 2010 07:27:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:27:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqe.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13092 comp.lang.vhdl:4313 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS obviously,my case statement has 4 conditions, that';s why SEL is of 2 bits. i simplified the code in order not to distract you from the real problem. From newsfish@newsfish Fri Feb 3 13:08:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!b25g2000vbz.googlegroups.com!not-for-mail From: "maurizio.tranchero" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 00:39:53 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <1cf54872-86f1-4bea-9ef3-d853e3bc3a8d@b25g2000vbz.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 217.140.96.21 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288942793 27652 127.0.0.1 (5 Nov 2010 07:39:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 07:39:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b25g2000vbz.googlegroups.com; posting-host=217.140.96.21; posting-account=uO6v-goAAABkLf6DVKtE8Z5Ly72qnjLn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.1.1) Gecko/20090715 Firefox/3.5.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13093 comp.lang.vhdl:4314 On Nov 5, 8:27=A0am, Angus wrote: > On Nov 5, 7:21=A0am, Angus wrote: > > > > > all right here you go (I read there was A problem with MODELSIM in > > simulating combinatorial processes): > > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > > PROCESS (SEL) > > BEGIN > > -- > > =A0 =A0 =A0 =A0 =A0CASE SEL IS > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > > =A0 =A0 =A0 =A0 END CASE; > > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC= _VECTOR(temp(1), > > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > > END PROCESS; > > when i change SEL in my testbench, Data does not change. I had to > > embed my CASE within a clk edge detection to see the changes on > > modelsim Your process isn't fully combinatorial: a process in order to be combinatorial has to contain in its sensitivity list ALL the inputs that can affect the output. In your case you only have the multiplexer selector in the sensitivity list, while the DATA1 and DATA2 are not included. Try to add them and it will work. Ciao! maurizio From newsfish@newsfish Fri Feb 3 13:08:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!optima2.xanadu-bbs.net!news.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 5 Nov 2010 01:30:49 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <639b89a6-5417-4264-bd1b-1c93c9d48525@r14g2000yqa.googlegroups.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288945849 21862 127.0.0.1 (5 Nov 2010 08:30:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:30:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4315 =A0The inelegant solution would be to > create an array of std_logic_vector where the width of each vector is > as wide as the widest needed. =A0 Very inelegent, because unsigned/signed types are what you should be using if you're doing arithmatic, not std_logic_vector. But otherwise, you cannot access signals out of scope (as you were suggesting with the 2nd paragraph). Personally, Id probably just convert them to integers and back to unsigned/signed at the end (if I really need to - why not just keep it an integer?) and then let the synthesiser chose the correct bit length. From newsfish@newsfish Fri Feb 3 13:08:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 01:32:14 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288946047 23604 127.0.0.1 (5 Nov 2010 08:34:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:34:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4316 On Nov 4, 11:28=A0am, whygee wrote: > Hello, > > I really miss the "or", "and", "xor", "not", "shr", "shl" etc. > operators in the "integer" type. To my knowledge, they are available > only for the types like std_(u)logic(_vector) but they are... slow. > I would like to do some quick behavioural stuff and > I'm ready to code some extensions to my favorite simulator > (GHDL) but I wonder if anyone knows an existing solution. > > Any hint ? Did I miss something ? > > yg > --http://ygdes.com/http://yasep.org Use signed/unsigned instead? you can do arithmatic and boolean with them. From newsfish@newsfish Fri Feb 3 13:08:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 01:34:32 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288946072 28624 127.0.0.1 (5 Nov 2010 08:34:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 08:34:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13095 comp.lang.vhdl:4317 On Nov 5, 7:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS As maurizio has pointed out, if you add DATA1 and DATA2 to the sensitivity list it will work. But one word of warning - this code will create latches, which is probably not what you want to do. From newsfish@newsfish Fri Feb 3 13:08:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 03:56:29 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 09:05:53 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 53 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-EeHo01ijOqkJ/AULeWqM3UXU/atnjLG+KGaBjNp6b/MAe9MzdcnHPwGbwfkyeYoGuTahHkXwJfQojpq!2hzsk9wUsl4wwPePbswxKAG7iwQRwS8Mm7+6TiOujdJ5m558ydfP1nBjYKpXp5Zt9YEX0TCtzLJD!1wIf X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3160 Xref: feeder.eternal-september.org comp.lang.vhdl:4318 On Fri, 05 Nov 2010 05:30:12 +0100, whygee wrote: >Hi ! > >Brian Drummond wrote: >> On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >>> Any hint ? Did I miss something ? >> bit_vector should be less heavyweight than std_logic_vector. >sure but i want to use integers :-/ > > > - Brian > >Nicolas Matringe wrote : > > That's strong typing for you... >it's not a problem of typing, i can create new functions, >however I see nowhere an explanation of these missing operations. >why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) >and not on integer, as in any other language ? Not "any" other language. Mainly C and its followers, which tend to trade a superficial convenience for a thousand subtle ways to screw yourself. These operations are not "missing" in VHDL's integer types; they were never part of Integer at any time in the history of mathematics, and there is no rational reason for them to be now. They basically crept into C's "int" via some late 1960's assembly language, and we have been paying the price in software "quality" ever since. If you need to "AND" two quantities, you can be pretty close to certain that they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, maybe. Control signals, possibly. Oh and while I'm still coffee-deprived, adding two positive integers will NEVER EVER result in a negative integer. Integers don't, and can't, overflow. >From which we can see that C doesn't actually have ANY integer data types at all - merely a bit-vector type, misleadingly labelled "int", on which they allow instructions that occasionally resemble addition, etc. (Pedantically, modulo-n addition). Oh, and "unsigned char", as if there was ever such a thing as a signed character. (If you think this is a little OTT, just count the number of "integer overflow" bugs reported in a project like Firefox. And weep.) - Brian From newsfish@newsfish Fri Feb 3 13:08:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.142.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 04:02:11 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 05 Nov 2010 09:11:35 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <88i7d65se7oasvf313gt6u631jo9ppamjq@4ax.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 20 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-pxwVdSL9EhPmkTp0ZcmDG6y4ktfoSKFOQhx5c3JCZc3E466HwKORWCDsngkwaK38Y8zblfqQztZb/l3!hM7eS35JvOGBr6cy+AGAW4AiUbC25MI3XaCRCsnPjxYSIevXWHqnm/awXjdSx+55Om/FYu895NKy!jVEW X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1975 Xref: feeder.eternal-september.org comp.lang.vhdl:4319 On Thu, 4 Nov 2010 14:19:31 -0700 (PDT), Matt Longbrake wrote: >Is there any way to use a signal from a previous generate loop >iteration in a later iteration? As an example, say you were building >a variable length adder chain. The output of each adder is one bit >wider than the previous adder. You may be able to do this by nesting two generate statements, using the outer one's loop variable as the inner one's control parameter. I would be wary of encountering synthesis bugs, and check the results unusually carefully. Alternatively, realise that synthesis warnings are merely warnings, not errors, and can safely be ignored if you understand and expect them. Synthesis tools will do an excellent job of trimming fixed-width adders down to the size required. - Brian From newsfish@newsfish Fri Feb 3 13:08:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 10:20:58 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 49 Message-ID: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b271b4f9.news.skynet.be X-Trace: 1288948858 news.skynet.be 14248 91.177.173.208:40769 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4320 Brian Drummond wrote: > Not "any" other language. > > Mainly C and its followers, which tend to trade a superficial convenience for a > thousand subtle ways to screw yourself. > > These operations are not "missing" in VHDL's integer types; they were never part > of Integer at any time in the history of mathematics, and there is no rational > reason for them to be now. > > They basically crept into C's "int" via some late 1960's assembly language, and > we have been paying the price in software "quality" ever since. > > If you need to "AND" two quantities, you can be pretty close to certain that > they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, > maybe. Control signals, possibly. > > Oh and while I'm still coffee-deprived, adding two positive integers will NEVER > EVER result in a negative integer. Integers don't, and can't, overflow. > > From which we can see that C doesn't actually have ANY integer data types at all > - merely a bit-vector type, misleadingly labelled "int", on which they allow > instructions that occasionally resemble addition, etc. (Pedantically, modulo-n > addition). > > Oh, and "unsigned char", as if there was ever such a thing as a signed > character. All true, but I think it is also possible to do it right and that the result is very useful, especially for hardware designers. I think a language like Python does it right. Integers are true integers, but through the boolean operators you have access to the underlying 2's complement representation if desired. What I do in MyHDL with the intbv type, is to add an indexing and slicing interface to such integers. The result is indeed a "dual mode" type. But for arithmetic, it doesn't have any of the confusion of signed/unsigned. I believe this is exactly what hardware designers need in practice. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Fri, 5 Nov 2010 03:04:56 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288951496 5876 127.0.0.1 (5 Nov 2010 10:04:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 10:04:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4321 On Nov 1, 8:09=A0am, Jonathan Bromley wrote: > On Nov 1, 10:45=A0am, Merciadri Luca wrote: > > > =3D=3D > > signal sig1, sig2, sig3, sig4: natural range 0 to MAX_VALUE :=3D 0; > > =3D=3D > > > where MAX_VALUE is a constant. My ghdl compiler will be okay with this > > statement, but what is its result? > > Each of your four signals has the same subtype > (0 to MAX_VALUE). =A0The explicit initialization ":=3D0" > is redundant, because any VHDL variable or signal is > initialized to the left-most value in its value set; > in your case that value is 0 anyway. =A0All four > signals will have 0 as their initialization value. > > Note that the initial value is associated with > the subtype part of the declaration. =A0It is not > attached to each individual data object; it > applies to all four of them. > > > But does that actually achieve what I want? > > Only you can answer that :-) > -- > Jonathan Bromley That may be true for simulation, but for synthesis the initialization is often used for the initial value set during configuration. If the explicit assignment is omitted, will the synthesis tool match the simulation? Rick From newsfish@newsfish Fri Feb 3 13:08:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.tornevall.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!q18g2000vbm.googlegroups.com!not-for-mail From: "maurizio.tranchero" Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 03:17:55 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 217.140.96.21 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288952275 12408 127.0.0.1 (5 Nov 2010 10:17:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 10:17:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbm.googlegroups.com; posting-host=217.140.96.21; posting-account=uO6v-goAAABkLf6DVKtE8Z5Ly72qnjLn User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.1.1) Gecko/20090715 Firefox/3.5.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13096 comp.lang.vhdl:4322 > As maurizio has pointed out, if you add DATA1 and DATA2 to the > sensitivity list it will work. > But one word of warning - this code will create latches, which is > probably not what you want to do. Yes, Tricky, I forgot the latches...sorry for that Angus, each time in an HDL statement you leave a default behavior that simply keeps the previous value of a signal (when others => null, actually does this) you will introduce a latch element. A small advice, when you are developing HW, never forget that you are not writing software, but describing HW. Try to ask yourself "how this behavior can result in gates?" you will reduce a lot the number of unwanted behavior. Good luck! maurizio From newsfish@newsfish Fri Feb 3 13:08:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 05 Nov 2010 10:22:37 +0000 Organization: TRW Conekt Lines: 64 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 1SzUQU3P5cG7f0UawlHtMQjKImwnsZq2fu5TFRiRDfQM+4A3w= Cancel-Lock: sha1:Ik1vIWqQFpPoHhwmU5xmf35QuYc= sha1:KHYgeeFKg77XpFZYjmkIizMaKmI= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.arch.fpga:13097 comp.lang.vhdl:4323 Angus writes: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=(7,3,2); > SIGNAL DATA2 : Data_t :=(9,5,1); > > PROCESS (SEL) Do you not want DATA1 and DATA2 in here? Are you trying to latch your result *only* when SEL changes (and not when the data changes)? > BEGIN > -- > CASE SEL IS > WHEN "00" =>temp<=DATA1; > WHEN "01" =>temp<=DATA2; > WHEN OTHERS =>NULL; Here you've scheduled a transaction on temp to happen at the end of the process. > END CASE; > > > Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); Here you are using temp, but it hasn't updated yet as the process hasn't suspended. To get this to update the way you seem to want you need to use a variable for temp. That updates immediately. BTW, you're using conv_std_logic_vector, which means you must have used ieee.std_logic_arith - don't do that, use ieee.numeric_std. Some other threads on this: https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/389677dd60f7b91c/af0ec67dda4ee7ba?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith&pli=1#af0ec67dda4ee7ba https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffd35914d/83cc0f19350fc392?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith#83cc0f19350fc392 http://www.alteraforum.com/forum/showthread.php?t=20925 And some notes I made after writing about it on newsgroups once too often: http://www.parallelpoints.com/node/3 > END PROCESS; > when i change SEL in my testbench, Data does not change. Are you sure you're not just seeing it change on the *next* change of sel? > I had to > embed my CASE within a clk edge detection to see the changes on > modelsim Well, that's probably a good plan anyway, as I doubt the description above is remotely synthesisable... That should also show a pipelined behaviour though (where data changes one extra tick after sel changes). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:08:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 04:24:31 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288956271 14652 127.0.0.1 (5 Nov 2010 11:24:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 11:24:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4324 On Nov 5, 5:20=A0am, Jan Decaluwe wrote: > Brian Drummond wrote: > > Not "any" other language. > > > Mainly C and its followers, which tend to trade a superficial convenien= ce for a > > thousand subtle ways to screw yourself. > > > These operations are not "missing" in VHDL's integer types; they were n= ever part > > of Integer at any time in the history of mathematics, and there is no r= ational > > reason for them to be now. > > > They basically crept into C's "int" via some late 1960's assembly langu= age, and > > we have been paying the price in software "quality" ever since. > > > If you need to "AND" two quantities, you can be pretty close to certain= that > > they are, fundamentally, not integers. Instructions, perhaps. Sets of b= its, > > maybe. Control signals, possibly. > > > Oh and while I'm still =A0coffee-deprived, adding two positive integers= will NEVER > > EVER result in a negative integer. Integers don't, and can't, overflow. > > > From which we can see that C doesn't actually have ANY integer data typ= es at all > > - merely a bit-vector type, misleadingly labelled "int", on which they = allow > > instructions that occasionally resemble addition, etc. (Pedantically, m= odulo-n > > addition). > > > Oh, and "unsigned char", as if there was ever such a thing as a signed > > character. > > All true, but I think it is also possible to do it right and that > the result is very useful, especially for hardware designers. > > I think a language like Python does it right. Integers are true integers, > but through the boolean operators you have access to the underlying > 2's complement representation if desired. But that is the problem. Who says an integer is implemented as a 2's complement binary signal array? > What I do in MyHDL with the intbv type, is to add an indexing and slicing > interface to such integers. The result is indeed a "dual mode" type. But > for arithmetic, it doesn't have any of the confusion of signed/unsigned. > I believe this is exactly what hardware designers need in practice. So MyHDL assumes a specific implementation of integers in the hardware? If the OP wants to treat integers as an array of a binary data type, then he needs to write the functions to do that. He will either need to convert the integers to an array of binary values and perform the logic operation on those, or he can use looping constructs to isolate the individual bits of the integer and operate on those. The problem is not that it can't be done, the OP simply doesn't know how to write a function to do this. He is thinking at a very simple level expecting there to be logic operators on integers for him to use. He needs to consider how logic operators could be implemented on integers. Rick From newsfish@newsfish Fri Feb 3 13:08:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 15:09:27 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 47 Message-ID: <4cd41017$0$14253$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: f514c5e8.news.skynet.be X-Trace: 1288966167 news.skynet.be 14253 91.177.173.208:52422 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4325 rickman wrote: > On Nov 5, 5:20 am, Jan Decaluwe wrote: >> >> I think a language like Python does it right. Integers are true integers, >> but through the boolean operators you have access to the underlying >> 2's complement representation if desired. > > But that is the problem. Who says an integer is implemented as a 2's > complement binary signal array? The Python Language LRM of course. It's not an axioma. Other definitions and languages are perfectly feasible, although less practical probably. >> What I do in MyHDL with the intbv type, is to add an indexing and slicing >> interface to such integers. The result is indeed a "dual mode" type. But >> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >> I believe this is exactly what hardware designers need in practice. > > So MyHDL assumes a specific implementation of integers in the > hardware? The intbv type is an integer-like type with a defined bit-vector representation. Much like Verilog's signed and unsigned regs, with the big difference that integer arithmetic works as it should. At the same time, it's more "abstract" than VHDL's integer - no arbitrary 32 bit limit. Intbv's can be used as integers without ever referring to their bit vector representation. They can also be used as bit vectors without ever referring to their integer interpretation, for example to represent integers in different ways in hardware. However, it is equally possible to mix the 2 interpretations as needed. Let's be honest, that happens all the time in practical hardware design. I have a lot of sympathy for purity, but I find your call to it a litte surprizing. I thought you were in the process of moving from VHDL to Verilog for practical reasons :-) ? Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!42g2000prt.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 07:55:29 -0700 (PDT) Organization: http://groups.google.com Lines: 59 Message-ID: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> NNTP-Posting-Host: 173.13.214.113 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288968929 9462 127.0.0.1 (5 Nov 2010 14:55:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 14:55:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 42g2000prt.googlegroups.com; posting-host=173.13.214.113; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4326 On Nov 5, 10:09=A0am, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 5:20 am, Jan Decaluwe wrote: > > >> I think a language like Python does it right. Integers are true intege= rs, > >> but through the boolean operators you have access to the underlying > >> 2's complement representation if desired. > > > But that is the problem. =A0Who says an integer is implemented as a 2's > > complement binary signal array? > > The Python Language LRM of course. It's not an axioma. Other definitions > and languages are perfectly feasible, although less practical probably. That's great, but not useful for hardware design is it? > >> What I do in MyHDL with the intbv type, is to add an indexing and slic= ing > >> interface to such integers. The result is indeed a "dual mode" type. B= ut > >> for arithmetic, it doesn't have any of the confusion of signed/unsigne= d. > >> I believe this is exactly what hardware designers need in practice. > > > So MyHDL assumes a specific implementation of integers in the > > hardware? > > The intbv type is an integer-like type with a defined bit-vector > representation. Much like Verilog's signed and unsigned regs, with > the big difference that integer arithmetic works as it should. > At the same time, it's more "abstract" than VHDL's integer - no > arbitrary 32 bit limit. > > Intbv's can be used as integers without ever referring to their > bit vector representation. They can also be used as bit vectors > without ever referring to their integer interpretation, for example > to represent integers in different ways in hardware. However, it > is equally possible to mix the 2 interpretations as needed. Let's > be honest, that happens all the time in practical hardware design. > > I have a lot of sympathy for purity, but I find your call to it > a litte surprizing. I thought you were in the process of moving > from VHDL to Verilog for practical reasons :-) ? I won't say the intent was "for practical reasons". It is more that I want to find out for myself what is good and bad about Verilog and possibly be more compatible with customers. I don't have a need for "purity" and I don't think I said that. HDLs are designed to be implementation independent unless you want to specify an implementation. Integers in VHDL are not intended to specify implementation, while signed and unsigned are. Is being implementation independent the same as being "pure"? Besides, I explained how integers can be treated as bit vectors with two choices. You just need to define your own functions for it. Rick From newsfish@newsfish Fri Feb 3 13:08:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.ett.com.ua!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!f8g2000yqn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 5 Nov 2010 08:13:02 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288969982 18880 127.0.0.1 (5 Nov 2010 15:13:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 15:13:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f8g2000yqn.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4327 On Nov 5, 2:09=A0pm, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 5:20 am, Jan Decaluwe wrote: > > >> I think a language like Python does it right. Integers are true intege= rs, > >> but through the boolean operators you have access to the underlying > >> 2's complement representation if desired. > > > But that is the problem. =A0Who says an integer is implemented as a 2's > > complement binary signal array? > > The Python Language LRM of course. It's not an axioma. Other definitions > and languages are perfectly feasible, although less practical probably. > > >> What I do in MyHDL with the intbv type, is to add an indexing and slic= ing > >> interface to such integers. The result is indeed a "dual mode" type. B= ut > >> for arithmetic, it doesn't have any of the confusion of signed/unsigne= d. > >> I believe this is exactly what hardware designers need in practice. > > > So MyHDL assumes a specific implementation of integers in the > > hardware? > > The intbv type is an integer-like type with a defined bit-vector > representation. Much like Verilog's signed and unsigned regs, with > the big difference that integer arithmetic works as it should. > At the same time, it's more "abstract" than VHDL's integer - no > arbitrary 32 bit limit. > > Intbv's can be used as integers without ever referring to their > bit vector representation. They can also be used as bit vectors > without ever referring to their integer interpretation, for example > to represent integers in different ways in hardware. However, it > is equally possible to mix the 2 interpretations as needed. Let's > be honest, that happens all the time in practical hardware design. > > I have a lot of sympathy for purity, but I find your call to it > a litte surprizing. I thought you were in the process of moving > from VHDL to Verilog for practical reasons :-) ? > > Jan > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0 Python as a HDL:http://www.myhdl.org > =A0 =A0 VHDL development, the modern way:http://www.sigasi.com > =A0 =A0 Analog design automation:http://www.mephisto-da.com > =A0 =A0 World-class digital design:http://www.easics.com Can you explain to me why you should use intbv over signed/unsigned? From newsfish@newsfish Fri Feb 3 13:08:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!not-for-mail From: whygee Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 05 Nov 2010 15:34:39 +0100 Organization: Aioe.org NNTP Server Lines: 121 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: U/0exTfd1WylvXzoYV2Z0A.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) Xref: feeder.eternal-september.org comp.lang.vhdl:4328 Hi everybody ! It's nice to see some activity here :-) To Tricky and Eilert : Yes of course I know numeric_std (signed and unsigned) enough to see what it is good for and to know it does not address my need. Currently I'm not looking at synthesisable code but behavioural description. I want to avoid SystemC and similar oddities, why would I need them when I have GHDL ? :-) And when the behaviour is right, i translate to std_ulogic. rickman wrote: > On Nov 5, 5:20 am, Jan Decaluwe wrote: >> Brian Drummond wrote: >>> Not "any" other language. >>> Mainly C and its followers, which tend to trade a superficial convenience for a >>> thousand subtle ways to screw yourself. CRAY screwed with floating point, but despite the high costs, it sold well. Hint : it was FAST. Yet I know the reluctantly accepted IEEE758, the same way they accepted 2-s complement after the CDC line which was 1s complement. I don't want to screw with arithmetics or standards. I just see that I spend too much time coding and simulating individual bits when the simulator's CPU can do a much simpler and faster work. I'll sort all the initialisation and other usual issues of my models later (during the transition to std_ulogic) but i don't think there will be much to care about because i use to code defensivly and forward-looking. >>> These operations are not "missing" in VHDL's integer types; they were never part >>> of Integer at any time in the history of mathematics, and there is no rational >>> reason for them to be now. I'm not doing mathematics, i'm doing digital electronics and I look at what does the job fastest :-) Don't worry : std_ulogic is not going to be thrown away, or else, how will i synthesise my code ? >>> They basically crept into C's "int" via some late 1960's assembly language, and >>> we have been paying the price in software "quality" ever since. >>> If you need to "AND" two quantities, you can be pretty close to certain that >>> they are, fundamentally, not integers. Instructions, perhaps. Sets of bits, >>> maybe. Control signals, possibly. yes, so what ? data is data. >>> Oh and while I'm still coffee-deprived, adding two positive integers will NEVER >>> EVER result in a negative integer. Integers don't, and can't, overflow. >>> From which we can see that C doesn't actually have ANY integer data types at all >>> - merely a bit-vector type, misleadingly labelled "int", on which they allow >>> instructions that occasionally resemble addition, etc. (Pedantically, modulo-n >>> addition). i agree. On the other side, how many times did you see in VHDL "x / 2**y " that makes a stupid bit shift using a divide (slow) and an exponential ? (super slow) ? >>> Oh, and "unsigned char", as if there was ever such a thing as a signed >>> character. haha :-) >> All true, but I think it is also possible to do it right and that >> the result is very useful, especially for hardware designers. more precisely : designers who know HW and SW well. I often hear the argument : "don't do X because it is potentially dangerous". Fine, I know the dangers and I take appropriate precautions. C integers are a bitch but I know them for a while now so I can code defensively and efficiently. >> I think a language like Python does it right. Integers are true integers, >> but through the boolean operators you have access to the underlying >> 2's complement representation if desired. > > But that is the problem. Who says an integer is implemented as a 2's > complement binary signal array? it's a convenient compromise, it is adopted by ... all the new computer architectures since the 1980's that i know. Now if you prefer 1's complement, it's not my problem :-) >> What I do in MyHDL with the intbv type, is to add an indexing and slicing >> interface to such integers. The result is indeed a "dual mode" type. But >> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >> I believe this is exactly what hardware designers need in practice. > > So MyHDL assumes a specific implementation of integers in the > hardware? > > If the OP wants to treat integers as an array of a binary data type, > then he needs to write the functions to do that. > He will either need > to convert the integers to an array of binary values and perform the > logic operation on those, or he can use looping constructs to isolate > the individual bits of the integer and operate on those. There are 3 ways : - as you wrote : plain slow (use of std_ulogic is faster) - modify the compiler : that's a long-term goal - VHPIDIRECT : what i'll do first :-) it only works with GHDL (maybe Aldec) but it's easy and fast to write and it's a first step to defining the behaviour of the boolean extension before the compiler is modified. > The problem is not that it can't be done, the OP simply doesn't know > how to write a function to do this. Rick, I thought you knew me better :-/ > He is thinking at a very simple > level expecting there to be logic operators on integers for him to > use. He needs to consider how logic operators could be implemented on > integers. give me 48h (well 2h are enough) and i'll show you a few tricks :-) Did I say that I have added a graphic framebuffer interface to GHDL, or I wrote code that reads the computer's environment variables ? OK it's only for GHDL but it works great and once you understand the guts, it's easy :-) Talk to you all soon, > Rick yg -- http://ygdes.com / http://yasep.org From newsfish@newsfish Fri Feb 3 13:08:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.wiretrip.org!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 17:40:50 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> In-Reply-To: <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 12 Message-ID: <4cd43391$0$14248$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 3e96c8a7.news.skynet.be X-Trace: 1288975249 news.skynet.be 14248 91.177.173.208:60651 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4329 Tricky wrote: > Can you explain to me why you should use intbv over signed/unsigned? Because it makes integer arithmetic work like God intended it :-) -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!tudelft.nl!txtfeed1.tudelft.nl!newsfeed.kpn.net!pfeed08.wxs.nl!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 18:44:54 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> In-Reply-To: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 73 Message-ID: <4cd44295$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: ca4d4994.news.skynet.be X-Trace: 1288979093 news.skynet.be 14247 91.177.173.208:33441 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4330 rickman wrote: > On Nov 5, 10:09 am, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>> I think a language like Python does it right. Integers are true integers, >>>> but through the boolean operators you have access to the underlying >>>> 2's complement representation if desired. >>> But that is the problem. Who says an integer is implemented as a 2's >>> complement binary signal array? >> The Python Language LRM of course. It's not an axioma. Other definitions >> and languages are perfectly feasible, although less practical probably. > > That's great, but not useful for hardware design is it? I don't see what you are referring to here. It can't be Python/MyHDL's actual choice, because that is the same as VHDL/Verilog for signed, and probably any VHDL synthesis tool for integer. >>>> What I do in MyHDL with the intbv type, is to add an indexing and slicing >>>> interface to such integers. The result is indeed a "dual mode" type. But >>>> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >>>> I believe this is exactly what hardware designers need in practice. >>> So MyHDL assumes a specific implementation of integers in the >>> hardware? >> The intbv type is an integer-like type with a defined bit-vector >> representation. Much like Verilog's signed and unsigned regs, with >> the big difference that integer arithmetic works as it should. >> At the same time, it's more "abstract" than VHDL's integer - no >> arbitrary 32 bit limit. >> >> Intbv's can be used as integers without ever referring to their >> bit vector representation. They can also be used as bit vectors >> without ever referring to their integer interpretation, for example >> to represent integers in different ways in hardware. However, it >> is equally possible to mix the 2 interpretations as needed. Let's >> be honest, that happens all the time in practical hardware design. >> >> I have a lot of sympathy for purity, but I find your call to it >> a litte surprizing. I thought you were in the process of moving >> from VHDL to Verilog for practical reasons :-) ? > > I won't say the intent was "for practical reasons". It is more that I > want to find out for myself what is good and bad about Verilog and > possibly be more compatible with customers. I don't have a need for > "purity" and I don't think I said that. Agreed, you complained about the consequences of VHDL's strong typing system. But that's what I intended to refer to also. > HDLs are designed to be > implementation independent unless you want to specify an > implementation. Integers in VHDL are not intended to specify > implementation, while signed and unsigned are. Is being > implementation independent the same as being "pure"? That's what I mean, yes: strong typing and abstract types without an implied representation, such as VHDL's boolean, enum and integer. I'm personally all for it, > Besides, I explained how integers can be treated as bit vectors with > two choices. You just need to define your own functions for it. Note that would have to make choice how to represent integers in those function. I wonder what that choice would be :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t7g2000vbj.googlegroups.com!not-for-mail From: Matt Longbrake Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Fri, 5 Nov 2010 11:11:51 -0700 (PDT) Organization: http://groups.google.com Lines: 68 Message-ID: <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> NNTP-Posting-Host: 134.131.125.50 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1288980712 19956 127.0.0.1 (5 Nov 2010 18:11:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 18:11:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t7g2000vbj.googlegroups.com; posting-host=134.131.125.50; posting-account=MSTlZgoAAAD_zHgCSsJ-fGgs0cHA71At User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.11) Gecko/20101012 Firefox/3.6.11 GTB7.1 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4331 > There are a number of things you can do. =A0You can declare signals > outside the generate block and make an assignment based on generate > index: > > =A0 signal a : std_logic_vector(7 downto 0); > =A0 signal b : std_logic; > > =A0 g_test: for i in 0 to 7 generate > =A0 =A0 if ( i =3D 0 ) then > =A0 =A0 =A0 b <=3D a(i); > =A0 =A0 end if > =A0 end generate : g_test > > The other option you are looking for is possible by declaring signals > within the generate for: > > =A0 g_test: for i in 0 to 7 generate > =A0 =A0 signal x : std_logic_vector(i+2 downto 0); > > =A0 =A0 x(i+2 downto 0) <=3D whatever; > > =A0 end generate : g_test > > In this case, you will have 8 x's defined as: x(2:0), x(3:0), ... > x(9:0). =A0But only accessible within the generate block. > > Cheers, > -- Amal Here's an example of what I meant with option 1 (probably not syntactically correct): type input_array is array(0 to 3) of signed(3 downto 0); signal inputs : input_array; type sum_array is array(0 to 4) of signed(7 downto 0); signal sums : sum_array; signal input : signed(3 downto 0); signal output : signed(7 downto 0); sums(0)(3 downto 0) <=3D inputs(0); output <=3D sums(4); abc: for i in 0 to 3 generate adder: adder2 generic map( width =3D> i+4) port map( A =3D> resize(inputs(i+1), i+4), B =3D> sums(i), S =3D> sums(i+1)(i+4 downto 0)); end generate; I wrote that off the cuff, but the point is that the width of the adder is easily adjusted by the generate statement, but I can't see any way to adjust the size of the signals feeding them. The above solution works, but you get unused signal warnings. > Alternatively, realise that synthesis warnings are merely warnings, not e= rrors, > and can safely be ignored if you understand and expect them. Synthesis to= ols > will do an excellent job of trimming fixed-width adders down to the size > required. I try to reduce the warnings as much as possible so that they actually have some meaning when they happen, maybe I'm being to optimistic. I just know that if I see a list of 1000 warnings, most of which can be ignored, it's hard to find the one that's actually something that needs fixing. From newsfish@newsfish Fri Feb 3 13:08:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 05 Nov 2010 19:23:04 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> In-Reply-To: <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 74 Message-ID: <4cd44b87$0$14255$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 11bc70aa.news.skynet.be X-Trace: 1288981383 news.skynet.be 14255 91.177.173.208:59175 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4332 rickman wrote: > On Nov 5, 10:09 am, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>> I think a language like Python does it right. Integers are true integers, >>>> but through the boolean operators you have access to the underlying >>>> 2's complement representation if desired. >>> But that is the problem. Who says an integer is implemented as a 2's >>> complement binary signal array? >> The Python Language LRM of course. It's not an axioma. Other definitions >> and languages are perfectly feasible, although less practical probably. > > That's great, but not useful for hardware design is it? I don't see what you are referring to here. It can't be Python/MyHDL's actual choice, because that is the same as VHDL/Verilog for signed, and probably any VHDL synthesis tool for integer. >>>> What I do in MyHDL with the intbv type, is to add an indexing and slicing >>>> interface to such integers. The result is indeed a "dual mode" type. But >>>> for arithmetic, it doesn't have any of the confusion of signed/unsigned. >>>> I believe this is exactly what hardware designers need in practice. >>> So MyHDL assumes a specific implementation of integers in the >>> hardware? >> The intbv type is an integer-like type with a defined bit-vector >> representation. Much like Verilog's signed and unsigned regs, with >> the big difference that integer arithmetic works as it should. >> At the same time, it's more "abstract" than VHDL's integer - no >> arbitrary 32 bit limit. >> >> Intbv's can be used as integers without ever referring to their >> bit vector representation. They can also be used as bit vectors >> without ever referring to their integer interpretation, for example >> to represent integers in different ways in hardware. However, it >> is equally possible to mix the 2 interpretations as needed. Let's >> be honest, that happens all the time in practical hardware design. >> >> I have a lot of sympathy for purity, but I find your call to it >> a litte surprizing. I thought you were in the process of moving >> from VHDL to Verilog for practical reasons :-) ? > > I won't say the intent was "for practical reasons". It is more that I > want to find out for myself what is good and bad about Verilog and > possibly be more compatible with customers. I don't have a need for > "purity" and I don't think I said that. Agreed, you complained about the consequences of VHDL's strong typing system. But that's what I intended to refer to also. > HDLs are designed to be > implementation independent unless you want to specify an > implementation. Integers in VHDL are not intended to specify > implementation, while signed and unsigned are. Is being > implementation independent the same as being "pure"? That's what I mean, yes: strong typing and abstract types without an implied representation, such as VHDL's boolean, enum and integer. I'm personally all for it in general, but not for the case of integer. Sometimes practicality beats purity. > Besides, I explained how integers can be treated as bit vectors with > two choices. You just need to define your own functions for it. Note that you would have to make a choice how to represent integers in those functions. I wonder what that choice would be :-) Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g25g2000yqn.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 14:35:24 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <0331399d-df23-49de-9ead-cf0628d0aabe@g25g2000yqn.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> <1cf54872-86f1-4bea-9ef3-d853e3bc3a8d@b25g2000vbz.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288992924 1554 127.0.0.1 (5 Nov 2010 21:35:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 21:35:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g25g2000yqn.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13104 comp.lang.vhdl:4333 > > Your process isn't fully combinatorial: a process in order to be > combinatorial > has to contain in its sensitivity list ALL the inputs that can affect > the output. > In your case you only have the multiplexer selector in the sensitivity > list, > while the DATA1 and DATA2 are not included. Try to add them and it > will > work. > > Ciao! > maurizio- Hide quoted text - > > - Show quoted text - Maurizio, Data1 and Data2 are constant. I think they don't have to be in the sensitivity list. I have fixed the problem as explained in my post below From newsfish@newsfish Fri Feb 3 13:08:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c20g2000yqj.googlegroups.com!not-for-mail From: Angus Newsgroups: comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 5 Nov 2010 14:39:38 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <05599483-6a4d-4414-96cb-61f78025ce58@c20g2000yqj.googlegroups.com> References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 82.20.238.68 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1288993178 3628 127.0.0.1 (5 Nov 2010 21:39:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Nov 2010 21:39:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000yqj.googlegroups.com; posting-host=82.20.238.68; posting-account=zev-HgoAAAAJ3gB3jazolLF4vwFW9Fpu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.2; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4334 Many thanks Martin. I had to use Variables and not Signals as you suggested and this fixed my error. should we then generalise that in combinatorial processes, variables should be used instead of signals in the intermediate assignments? From newsfish@newsfish Fri Feb 3 13:08:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!diablo2.news.osn.de!news.osn.de!diablo2.news.osn.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 05 Nov 2010 17:42:21 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Fri, 05 Nov 2010 22:51:45 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> <05599483-6a4d-4414-96cb-61f78025ce58@c20g2000yqj.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 13 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-RJWZj0HkoUd0PpHpOV3TImejNq7fK3BeAOMgryvq4TpBAPr48s//lmdtTSZQcq1EXywfBQXQqU1ZUCc!pt6vbCiuf7s81M4rUzsWwrWHHSgSF55VkAMudBEUQH7YniqGk7jJVleyfyvxzioX4bMM6fN4UXNI!zShN X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1866 Xref: feeder.eternal-september.org comp.lang.vhdl:4335 On Fri, 5 Nov 2010 14:39:38 -0700 (PDT), Angus wrote: >Many thanks Martin. I had to use Variables and not Signals as you >suggested and this fixed my error. should we then generalise that in >combinatorial processes, variables should be used instead of signals >in the intermediate assignments? Not necessarily. You could also have solved the problem by adding "temp" to the sensitivity list, since it appears on the RHS of a statement within the process. - Brian From newsfish@newsfish Fri Feb 3 13:08:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Element update within records Date: Fri, 05 Nov 2010 23:58:49 +0100 Organization: T-Online Lines: 30 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1288997930 00 n14699 Db0sChY1LpQVSilV 101105 22:58:50 X-Complaints-To: usenet-abuse@t-online.de X-ID: ZYUAMsZFreE6sjmUSQWqgiteFr0iDutnTwTXq2Dhw1GNkA8gbBFngU User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4336 Hi, I have a problem which I would like to optimize for simulation speed. I have a signal "a", which is a record with many different elements and element types. Now I would like to substitue single elements within this record asynchronously. Currently I do the following: process(a, b, c) is begin out <= a; out.record_element_x <= b; out.record_element_y <= c; end process; "out" is of the same type as "a", so I first copy all record elements and then overwrite the ones I would like to substitute. Like that I don't have to copy each record element individually. The problem is that "b" and "c" might be asynchronously calculated as well, which means the process can be triggered several times per rising clock edge, slowing down the simulation (copying "a" to "out" seems quite time consuming). Is there a better solution for this problem, which prevents me from copying "a" to "out" a couple of times per clock? Of course, the solution should be synthesizable. Thanks, Matthias From newsfish@newsfish Fri Feb 3 13:08:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!tudelft.nl!txtfeed1.tudelft.nl!feed.xsnews.nl!border-1.ams.xsnews.nl!193.201.147.77.MISMATCH!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 06 Nov 2010 03:44:12 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 08:53:37 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 34 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-GyZQfOhbSDWUIOit9Tv64ysUW+gTC3TNuqHskvBxUfSuZm0YFcjPS3rmAmYK2qArMM0LkcZExNRZuvG!TBdUfl/urd186TSsgDGiLIetRlz2wB0Z0+QmouDyHhRJTVXdNZaNrE99hsp4N8qhV1QxnlFclksT!65Da X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2153 Xref: feeder.eternal-september.org comp.lang.vhdl:4337 On Fri, 05 Nov 2010 23:58:49 +0100, Matthias Alles wrote: >Hi, > >I have a problem which I would like to optimize for simulation speed. I >have a signal "a", which is a record with many different elements and >element types. >out <= a; > >out.record_element_x <= b; >out.record_element_y <= c; >"out" is of the same type as "a", so I first copy all record elements >and then overwrite the ones I would like to substitute. Like that I >don't have to copy each record element individually. The problem is that >"b" and "c" might be asynchronously calculated as well, which means the >process can be triggered several times per rising clock edge, slowing >down the simulation (copying "a" to "out" seems quite time consuming). Write a simple function returning that record type, accepting arguments a,b,c. A sketch: function combine(a: in : b,c : in std_logic) return is variable temp : := a; begin temp.x := b; return temp; end combine; - Brian From newsfish@newsfish Fri Feb 3 13:08:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 09:09:13 +0000 Organization: A noiseless patient Spider Lines: 29 Message-ID: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="17207"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19DSBoL0Onggf0pvn0P/3lvMoQgxbgNenc=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:+qNGvaxWLPZhroTQ9c2kPb5kP6I= Xref: feeder.eternal-september.org comp.lang.vhdl:4338 On Sat, 06 Nov 2010 08:53:37 +0000, Brian Drummond wrote: >function combine(a: in : b,c : in std_logic) return is >variable temp : := a; >begin > temp.x := b; > return temp; >end combine; Right, but I don't think that solves the OP's problem, which was to try to avoid the performance hit of repeated copying of a large record when his process is repeatedly triggered in successive deltas. Indeed, your function potentially causes THREE copy operations: - one to put the actual argument value into the formal "a" - one to copy "a" to "temp" - one to copy "temp" to the return target although any half-decent compiler will collapse those on to only one or two, I imagine. The real solution is to avoid retriggering of the process, which is best done by NOT writing a combinational process with multiple signals in its sensitivity list. Matthias, is there any way you could fold the record processing into your clocked process, so you know it's executed only once per cycle? -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:08:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Generate statement with varying signal width Date: Sat, 06 Nov 2010 09:53:03 +0000 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <98e84b45-2cad-44c0-8831-cd72d388a25e@c20g2000yqj.googlegroups.com> <1d6ce218-34fc-41b5-845e-a9754bfee291@t7g2000vbj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="25240"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/a4tt5SVq/urMWOfh7RKVoOoK830/oFAg=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:5O0CnepxaPZaFJL15hObb0EvpUI= Xref: feeder.eternal-september.org comp.lang.vhdl:4339 On Fri, 5 Nov 2010 11:11:51 -0700 (PDT), Matt Longbrake wrote: >I try to reduce the warnings as much as possible so that they actually >have some meaning when they happen Sounds good. I am not sure whether you got a clear response about whether you can reference one generate block's signals from within another; the answer is "no" (except by using VHDL-2008 cross-scope references or whatever they're called). The pragmatic solution is definitely to use interconnect vectors of sufficient width. To remove the warnings, consider driving unused bits of those vectors with a common value that preserves the arithmetic meaning (typically zero-pad or sign-extend the MSBs). Synthesis will strip out the common or constant logic. You may get some note-level messages about that too, but that happens all the time and there's not a lot we can do about it. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:08:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!37g2000prx.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 6 Nov 2010 09:52:01 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289062322 27057 127.0.0.1 (6 Nov 2010 16:52:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Nov 2010 16:52:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 37g2000prx.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4340 On Nov 5, 6:58=A0pm, Matthias Alles wrote: > > Is there a better solution for this problem, which prevents me from > copying "a" to "out" a couple of times per clock? Of course, the > solution should be synthesizable. > Yes, either use multiple concurrent assignment statements... out.record_element_a <=3D a.a; -- Copy out.record_element_b <=3D a.b; -- Copy out.record_element_x <=3D b; out.record_element_y <=3D c; Or, a single assignment out <=3D ( record_element_a =3D> a.a, -- Copy record_element_b =3D> a.b, -- Copy record_element_x =3D> b; record_element_y =3D> c ); The second method has the advantage that if you add/remove record elements, the assignment to 'out' will fail when you compile it, forcing you to explicitly fix it at that time (that's a good thing). The first method of independent assignments would compile correctly without complaint (which can be nice), but might not represent what you intend to do. The second method is usually better. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:08:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Sat, 06 Nov 2010 15:14:44 -0700 Lines: 13 Message-ID: <8jm2a4F28bU1@mid.individual.net> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 4KaCS0+41hs8+IJ/nZczMQtyrs5K/NHt2I/SCu1YZDrKLQjPJb Cancel-Lock: sha1:AGOhvLanRw5Q1vpMwyfg38X+vmo= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4341 On 11/5/2010 3:04 AM, rickman wrote: > That may be true for simulation, but for synthesis the initialization > is often used for the initial value set during configuration. If the > explicit assignment is omitted, will the synthesis tool match the > simulation? I would consider it unsafe to count on value of an internal register between power up configuration and system reset, for any target device. So I guess I see no reason to simulate it. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 06 Nov 2010 18:41:09 -0500 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sat, 06 Nov 2010 23:50:35 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 64 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-HRha4TXM531VXJUeX20McCas2V/JpSVY6DoUR+23AYlh9hjyg722fWw5zFsBu/s3DYOEeFvFOD3BBPE!V6biTY9Qci5h0QxXJr3hTIxaIRUuRGZfdp6Sh4klYf2pldXFcp8wEmm3WRYgFr4Z0BIQHjXhXCnK!nv2l X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3972 Xref: feeder.eternal-september.org comp.lang.vhdl:4342 On Sat, 06 Nov 2010 09:09:13 +0000, Jonathan Bromley wrote: >On Sat, 06 Nov 2010 08:53:37 +0000, Brian Drummond wrote: > >>function combine(a: in : b,c : in std_logic) return is >>variable temp : := a; >>begin >> temp.x := b; >> return temp; >>end combine; > >Right, but I don't think that solves the OP's problem, which >was to try to avoid the performance hit of repeated copying >of a large record when his process is repeatedly triggered >in successive deltas. Indeed, your function potentially >causes THREE copy operations: >- one to put the actual argument value into the formal "a" >- one to copy "a" to "temp" >- one to copy "temp" to the return target >although any half-decent compiler will collapse those >on to only one or two, I imagine. Could be. I thought the slowness he found was when copying a to out, i.e. when a potentially tricky resolution took place. This solution should at least reduce the number of assignments to "out" to one. Which - I would guess - would give most of the benefit of whatever the optimum approach is. Confession time; I haven't spent an afternoon benchmarking different approaches with a few million iterations each, so I could be wrong here. --- Is it just me that pays (almost) no attention to simulation efficiency? It seems to me that my thinking time dwarfs sim runtime anyway. And corrupting the design for more "efficient" simulation seems to be a move in the wrong direction - away from efficient use of my time - to me. Am I so far out on a limb? I try to get the heavy lifting done by fairly well focussed test cases rather than by distorting the most natural (to me) - and therefore most likely to be bug-free - design approach in the cause of pandering to simulators. Even when I run a long simulation (e.g. error mapping a 32-bit floating point square root) testing every one of 16 million mantissa values only took an hour or two, with no concession to fast simulation coding. (About 200 of them had error just over 0.5LSB so it wasn't 100% P754 compliant). Of course by that stage I'm not interactively debugging, but if I were, after lunch, I could focus on the specific values that were giving trouble. The only time simulation speed REALLY bugs me is when vendors insist on supplying only a gate-level representation of their core (and sometimes even their testbench - I'm not kidding here!!! *cough* Xilinx PCI express ) - that is too large to run on their basic pay-for simulator! Then I restrict the simulation to a few basic reads and writes, and drop in a higher level interface (approximating the PCIe core's local bus) for the real system-level simulations. - Brian From newsfish@newsfish Fri Feb 3 13:08:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: combinatorial process not simulating correctly Date: Sat, 6 Nov 2010 19:24:29 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: References: <76c33f7f-69a3-451d-bb89-f1450a235930@f33g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.157.42.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289096670 871 127.0.0.1 (7 Nov 2010 02:24:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 7 Nov 2010 02:24:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=68.157.42.151; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13112 comp.lang.vhdl:4343 On Nov 5, 3:21=A0am, Angus wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS ---------------------------------------------------------------------------= -------- items to the right of <=3D are typically in the sensitivity list DATA1, DATA2, temp, SEL You may have to play around with the vector notation in the sensitivity list. You forgot temp From newsfish@newsfish Fri Feb 3 13:08:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u25g2000pra.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Sun, 7 Nov 2010 01:25:03 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <6fcb0328-61a0-4e6b-b484-35ebd0e8b9bf@u25g2000pra.googlegroups.com> References: NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289118304 25824 127.0.0.1 (7 Nov 2010 08:25:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 7 Nov 2010 08:25:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u25g2000pra.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4344 I had a similar situation on a project where I noticed an assignment to a signal record significantly increased sim runtime. My solution was to keep the record as a variable inside a process. It appeared to be the assignment to the signal that caused the simulation slow down. If I was debugging I would assign the variable to a signal to see what was going on. If the record has to be a signal then you can reduce the number of members or size of the members of the record can also help. So you could try splitting the record if some elements get 'touched' more that others. Darrin On Nov 6, 9:58=A0am, Matthias Alles wrote: > Hi, > > I have a problem which I would like to optimize for simulation speed. I > have a signal "a", which is a record with many different elements and > element types. Now I would like to substitue single elements within this > record asynchronously. Currently I do the following: > > process(a, b, c) is > begin > > out <=3D a; > > out.record_element_x <=3D b; > out.record_element_y <=3D c; > > end process; > > "out" is of the same type as "a", so I first copy all record elements > and then overwrite the ones I would like to substitute. Like that I > don't have to copy each record element individually. The problem is that > "b" and "c" might be asynchronously calculated as well, which means the > process can be triggered several times per rising clock edge, slowing > down the simulation (copying "a" to "out" seems quite time consuming). > > Is there a better solution for this problem, which prevents me from > copying "a" to "out" a couple of times per clock? Of course, the > solution should be synthesizable. > > Thanks, > Matthias From newsfish@newsfish Fri Feb 3 13:08:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!f16g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Mon, 8 Nov 2010 08:53:43 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289235223 419 127.0.0.1 (8 Nov 2010 16:53:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 16:53:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f16g2000prj.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4345 On Nov 6, 5:14=A0pm, Mike Treseler wrote: > On 11/5/2010 3:04 AM, rickman wrote: > > > That may be true for simulation, but for synthesis the initialization > > is often used for the initial value set during configuration. =A0If the > > explicit assignment is omitted, will the synthesis tool match the > > simulation? > > I would consider it unsafe to count on value of an internal register > between power up configuration and system reset, for any target device. > So I guess I see no reason to simulate it. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler I'm not sure what your point is. Are you saying that you don't make use of the built in global reset function? That value matches the configuration reset value. Of course if you use logic to generate your own system reset you can set it to whatever you want independent of the configuration value. But that is out of context to what Jonathan was saying which is what I was replying to. Rick From newsfish@newsfish Fri Feb 3 13:08:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u11g2000prn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 09:57:05 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289239025 2885 127.0.0.1 (8 Nov 2010 17:57:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 17:57:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u11g2000prn.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4346 The VHDL standard has already adopted an assumed two's complement numeric representation for vectors (numeric_std, numeric_std_unsigned, ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement representation for integes as well?! The primary problem with vhdl vector based arithmetic (numeric_*) is that it rolls over (not to signed, but what's the difference, an unsigned rollover is still inaccurate). Take two unsigned, add them together, and you can get a result that is less than either of the operands. The closest vhdl vector arithmetic comes to true integer arithmetic accuracy is the fixed point package types, with zero fractional bits declared. Fixed point operators automatically pad the result size to account for accuracy in all cases, except one: a ufixed minus a ufixed is still a ufixed (but actually bigger by one bit! go figure) rather than an sfixed. With the almost universal need to resize sfixed/ufixed results to fit in an assigned signal/variable, the conversion from sfixed to ufixed could easily be handled in the resize function anyway. Or better yet, allow assignment operators to be overloaded so that they can do the resizing automatically. Hey, I can dream, can't I? Andy From newsfish@newsfish Fri Feb 3 13:08:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!g28g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 10:53:02 -0800 (PST) Organization: http://groups.google.com Lines: 54 Message-ID: <4ff4f712-4b04-4414-a712-b277acb6cc31@g28g2000pra.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 98.232.140.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289242382 32083 127.0.0.1 (8 Nov 2010 18:53:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 18:53:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g28g2000pra.googlegroups.com; posting-host=98.232.140.93; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4347 > The VHDL standard has already adopted an assumed two's complement > numeric representation for vectors (numeric_std, numeric_std_unsigned, > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > representation for integes as well?! It certainly would be worth while to entertain enhancements to integers in the next revision of VHDL - I have heard others issues in addition to this one. See my separate post about study group formation. The first baby step toward the next standard - but it is important to attend and voice an opinion on the issues mentioned. > The closest vhdl vector arithmetic comes to true integer arithmetic > accuracy is the fixed point package types, with zero fractional bits > declared. Fixed point operators automatically pad the result size to > account for accuracy in all cases, except one: a ufixed minus a ufixed > is still a ufixed (but actually bigger by one bit! go figure) rather > than an sfixed. With the almost universal need to resize sfixed/ufixed > results to fit in an assigned signal/variable, the conversion from > sfixed to ufixed could easily be handled in the resize function > anyway. I think both have issues. For example: signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto 0) ; signal Y_ufixed11 : ufixed(10 downto 0) ; Y_ufixed11 <= A_ufixed8 + B_ufixed8 + C_ufixed8 + D_ufixed8 ; results in a different size than: signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto 0) ; signal Y_ufixed10 : ufixed(9 downto 0) ; Y_ufixed10 <= (A_ufixed8 + B_ufixed8) + (C_ufixed8 + D_ufixed8) ; > Or better yet, allow assignment operators to be overloaded so that > they can do the resizing automatically. It would be an interesting proposal. If it gets approved, are you interested in writing it? Can you formulate something that chooses between modulo math (like unsigned/signed) or full precision arith (like ufixed/sfixed)? If you blow the doors open and allow anything, I would think that is bad. If you add more saftey such as enforcement of ranges for ufixed/sfixed (so that more than size is enforced) then it would be exciting. Best, Jim From newsfish@newsfish Fri Feb 3 13:08:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m20g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: VHDL Study Group Meeting Notice Date: Mon, 8 Nov 2010 10:57:08 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: <8d1b4c0e-204e-43de-8adc-d3ad5cf058e8@m20g2000prc.googlegroups.com> NNTP-Posting-Host: 98.232.140.93 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289242629 1601 127.0.0.1 (8 Nov 2010 18:57:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Nov 2010 18:57:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000prc.googlegroups.com; posting-host=98.232.140.93; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4348 Hi, In preparation for the next revision of VHDL, the DASC (parent of the 1076 - VHDL) has given us permission to form a study group with the purpose of writing the PAR (project authorization request). Meeting is scheduled for Wednesday Dec 1 at 8 am Pacific. Dial in details will be announced later. Please enroll in the VASG email reflector at (see bottom of page under participation) http://www.eda.org/vasg/ This meeting is open to all who have a vested interest in VHDL. Please participate. While I expect most of the PAR to be easy for all, we do have one item that will come up. One item that will come up is whether to organize the VHDL working group as an individual (as it has been) or corporate based working group. Anyone with a vested interest in VHDL can participate (attend meetings, be on the working group email reflector, and attain voting rights) in an individual based working group. In a corporate based working group, to be an observer (attend meetings or be on the reflector) will cost a company between $1250 and $5500 (depending on corporate revenue). To be a voting member, one must be an advanced corporate member at a cost of $3500 to $10000. Unfortunately none of this money goes to the working group, instead it goes to fund IEEE Standards Association (which is a separate organization from IEEE). Any funding needed by the working group will be a separate assessment. Please attend and weigh in on this issue as this will effect the working group. Best Regards, Jim Lewis P.S. If you think you are already on the VHDL-200X reflector, and did not get this already, your email is bouncing (Mike T). -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ From newsfish@newsfish Fri Feb 3 13:08:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!26g2000yqv.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Mon, 8 Nov 2010 16:13:02 -0800 (PST) Organization: http://groups.google.com Lines: 80 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289261582 13944 127.0.0.1 (9 Nov 2010 00:13:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Nov 2010 00:13:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 26g2000yqv.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4349 On Nov 5, 1:23=A0pm, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 10:09 am, Jan Decaluwe wrote: > >> rickman wrote: > >>> On Nov 5, 5:20 am, Jan Decaluwe wrote: > >>>> I think a language like Python does it right. Integers are true inte= gers, > >>>> but through the boolean operators you have access to the underlying > >>>> 2's complement representation if desired. > >>> But that is the problem. =A0Who says an integer is implemented as a 2= 's > >>> complement binary signal array? > >> The Python Language LRM of course. It's not an axioma. Other definitio= ns > >> and languages are perfectly feasible, although less practical probably= . > > > That's great, but not useful for hardware design is it? > > I don't see what you are referring to here. It can't be Python/MyHDL's > actual choice, because that is the same as VHDL/Verilog for signed, and > probably any VHDL synthesis tool for integer. I think I have no idea what you are saying with this. What Python does with integers has no bearing on what VHDL does. So what is your point about mentioning Python? > >> I have a lot of sympathy for purity, but I find your call to it > >> a litte surprizing. I thought you were in the process of moving > >> from VHDL to Verilog for practical reasons :-) ? > > > I won't say the intent was "for practical reasons". =A0It is more that = I > > want to find out for myself what is good and bad about Verilog and > > possibly be more compatible with customers. =A0I don't have a need for > > "purity" and I don't think I said that. > > Agreed, you complained about the consequences of VHDL's strong > typing system. But that's what I intended to refer to also. Again, I have no idea why you are bringing this up. How does it pertain to the discussion? > > HDLs are designed to be > > implementation independent unless you want to specify an > > implementation. =A0Integers in VHDL are not intended to specify > > implementation, while signed and unsigned are. =A0Is being > > implementation independent the same as being "pure"? > > That's what I mean, yes: strong typing and abstract types without > an implied representation, such as VHDL's boolean, enum and > integer. I'm personally all for it in general, but not for the > case of integer. Sometimes practicality beats purity. Ok, you have stated your preference, but you have not given any basis for it. In general a given type does not have an representation implied so that it can be implemented in the manner that suits the application the best. Although 2's complement is pretty universal, it is not the only way to use integers. Do you think it is worth eliminating the use of integers for any other representation by specifying one representation in the standard? I guess I know the answer to that one. But you can see where this is a problem for some usage that others may want, no? Besides, the OP can do what he wants and perform bit wise operations on integers. He just has to write a few functions to do that. > > Besides, I explained how integers can be treated as bit vectors with > > two choices. =A0You just need to define your own functions for it. > > Note that you would have to make a choice how to represent integers > in those functions. I wonder what that choice would be :-) That is up to the author to suit their application. I can see where they would choose to use 2's complement or unsigned possibly. It depends on how they intend to use it in the application. Rick From newsfish@newsfish Fri Feb 3 13:08:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!194.134.4.91.MISMATCH!news2.euro.net!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 09 Nov 2010 10:06:48 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 85 Message-ID: <4cd90f28$0$14261$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: ee99856e.news.skynet.be X-Trace: 1289293608 news.skynet.be 14261 91.177.109.178:44493 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4350 rickman wrote: > On Nov 5, 1:23 pm, Jan Decaluwe wrote: >> rickman wrote: >>> On Nov 5, 10:09 am, Jan Decaluwe wrote: >>>> rickman wrote: >>>>> On Nov 5, 5:20 am, Jan Decaluwe wrote: >>>>>> I think a language like Python does it right. Integers are true integers, >>>>>> but through the boolean operators you have access to the underlying >>>>>> 2's complement representation if desired. >>>>> But that is the problem. Who says an integer is implemented as a 2's >>>>> complement binary signal array? >>>> The Python Language LRM of course. It's not an axioma. Other definitions >>>> and languages are perfectly feasible, although less practical probably. >>> That's great, but not useful for hardware design is it? >> I don't see what you are referring to here. It can't be Python/MyHDL's >> actual choice, because that is the same as VHDL/Verilog for signed, and >> probably any VHDL synthesis tool for integer. > > I think I have no idea what you are saying with this. What Python > does with integers has no bearing on what VHDL does. So what is your > point about mentioning Python? I try to convince people to take a good look at Python/MyHDL integers and possibly consider to do it similarly in a future VHDL standard. >>>> I have a lot of sympathy for purity, but I find your call to it >>>> a litte surprizing. I thought you were in the process of moving >>>> from VHDL to Verilog for practical reasons :-) ? >>> I won't say the intent was "for practical reasons". It is more that I >>> want to find out for myself what is good and bad about Verilog and >>> possibly be more compatible with customers. I don't have a need for >>> "purity" and I don't think I said that. >> Agreed, you complained about the consequences of VHDL's strong >> typing system. But that's what I intended to refer to also. > > Again, I have no idea why you are bringing this up. How does it > pertain to the discussion? The ideas I'm proposing would solve many of the VHDL usability issues that we are all struggling with, including the OP and you as I understood it, when you announced that you'd rather switch (to Verilog) than fight (with VHDL). >>> HDLs are designed to be >>> implementation independent unless you want to specify an >>> implementation. Integers in VHDL are not intended to specify >>> implementation, while signed and unsigned are. Is being >>> implementation independent the same as being "pure"? >> That's what I mean, yes: strong typing and abstract types without >> an implied representation, such as VHDL's boolean, enum and >> integer. I'm personally all for it in general, but not for the >> case of integer. Sometimes practicality beats purity. > > Ok, you have stated your preference, but you have not given any basis > for it. In general a given type does not have an representation > implied so that it can be implemented in the manner that suits the > application the best. Although 2's complement is pretty universal, it > is not the only way to use integers. Do you think it is worth > eliminating the use of integers for any other representation by > specifying one representation in the standard? I guess I know the > answer to that one. But you can see where this is a problem for some > usage that others may want, no? No, I don't think there is a problem. Imagine an integer type with an "accessible" 2's complement representation. A synthesis tool only has to honour that when the representation is actually "accessed" in the code, something which is easy for a tool to detect. Otherwise, it could implement it with any optimized representation it chooses. The latter case is equivalent to the current situation, with an "inaccessible" representation. In other words, this would be a backwards compatible enhancement. If you need full control over representation, you'd have to do it like today: use bit vectors with dedicated logic, and interprete the bit vector values as numbers yourself. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!news.weisnix.org!newsfeed.ision.net!newsfeed2.easynews.net!ision!newsfeed3.dallas1.level3.net!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!w38g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Tue, 9 Nov 2010 05:53:02 -0800 (PST) Organization: http://groups.google.com Lines: 85 Message-ID: <7d5fc000-c5de-4d28-8958-997e371ef953@w38g2000pri.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <04da2dda-de18-4ea4-a7bc-21f1c067974a@42g2000prt.googlegroups.com> <4cd44b87$0$14255$ba620e4c@news.skynet.be> <4cd90f28$0$14261$ba620e4c@news.skynet.be> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289310783 8851 127.0.0.1 (9 Nov 2010 13:53:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 9 Nov 2010 13:53:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w38g2000pri.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4351 On Nov 9, 4:06=A0am, Jan Decaluwe wrote: > rickman wrote: > > On Nov 5, 1:23 pm, Jan Decaluwe wrote: > >> I don't see what you are referring to here. It can't be Python/MyHDL's > >> actual choice, because that is the same as VHDL/Verilog for signed, an= d > >> probably any VHDL synthesis tool for integer. > > > I think I have no idea what you are saying with this. =A0What Python > > does with integers has no bearing on what VHDL does. =A0So what is your > > point about mentioning Python? > > I try to convince people to take a good look at Python/MyHDL integers > and possibly consider to do it similarly in a future VHDL standard. > > >> Agreed, you complained about the consequences of VHDL's strong > >> typing system. But that's what I intended to refer to also. > > > Again, I have no idea why you are bringing this up. =A0How does it > > pertain to the discussion? > > The ideas I'm proposing would solve many of the VHDL usability > issues that we are all struggling with, including the OP and > you as I understood it, when you announced that you'd rather > switch (to Verilog) than fight (with VHDL). I don't see where it would solve the problems I have seen unless it allows the use of integers to replace all data types... I tried using Boolean for some control signals as this simplifies expressions in conditionals. But in simulation Boolean signals are displayed as a value like an integer which is a PITA. A std_logic signal is displayed as a line with two levels and is very easy to see rather than having to read a value which can be off the display. > >> That's what I mean, yes: strong typing and abstract types without > >> an implied representation, such as VHDL's boolean, enum and > >> integer. I'm personally all for it in general, but not for the > >> case of integer. Sometimes practicality beats purity. > > > Ok, you have stated your preference, but you have not given any basis ccc> > for it. =A0In general a given type does not have an representation > > implied so that it can be implemented in the manner that suits the > > application the best. =A0Although 2's complement is pretty universal, i= t > > is not the only way to use integers. =A0Do you think it is worth > > eliminating the use of integers for any other representation by > > specifying one representation in the standard? =A0I guess I know the > > answer to that one. =A0But you can see where this is a problem for some > > usage that others may want, no? > > No, I don't think there is a problem. > > Imagine an integer type with an "accessible" 2's complement representatio= n. > A synthesis tool only has to honour that when the representation is > actually "accessed" in the code, something which is easy for a tool to > detect. Otherwise, it could implement it with any optimized representatio= n it > chooses. The latter case is equivalent to the current situation, with an > "inaccessible" representation. In other words, this would be a backwards > compatible enhancement. > > If you need full control over representation, you'd have to do it like > today: use bit vectors with dedicated logic, and interprete the bit > vector values as numbers yourself. I don't need control over the representation of integers. But my tool vendor may need that. The synthesis tool is designed for the target. If it works better to represent integers as signed magnitude then the synthesis tool can do that without my involvement or knowledge. How would you allow a synthesis tool to optimize for a given target implementation if the representation is fixed? By requiring the tool to work one way when the bit representation is accessed and a different way when it is not sounds like a complexity that could cause problems for users. Maybe that is not really important. I know it is an issue in the software world, but in FPGAs and ASICs I can't think of an example where the number representation is anything other than 2's complement. But I don't see it helping with any problems unless you can replace all data types with integers. Rick From newsfish@newsfish Fri Feb 3 13:08:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Tue, 09 Nov 2010 10:13:38 -0800 Lines: 17 Message-ID: <8jthagFdreU1@mid.individual.net> References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net ya2DfFT/CpwnP/YGPxqaKA2XG5bezqBdSM2/rtdvr35C7Ux9Is Cancel-Lock: sha1:LpytZb9Uc3nTqoPSTTLNf9PNbFA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4352 On 11/8/2010 8:53 AM, rickman wrote: > I'm not sure what your point is. Are you saying that you don't make > use of the built in global reset function? I use Altera parts, and the internal "reset" logic is fixed. Pins go to Z and flops go to 0. > Of course if you use logic to generate > your own system reset you can set it to whatever you want independent > of the configuration value. This is what I have have always done. Otherwise, the only way to force a "reset" is to reload the configuration. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.unit0.net!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:08:57 +0100 Organization: T-Online Lines: 27 Message-ID: References: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289336938 00 n18220 D0GECmhvJ4fFRyx 101109 21:08:58 X-Complaints-To: usenet-abuse@t-online.de X-ID: GhujB-ZbYezPVbZIl2cOOkRLM+7VRLuvy8VMaamEmE9lHsj1BIAxk5 User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <790f9874-09d4-44c6-9ae4-54719761953b@37g2000prx.googlegroups.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4353 I tried both approaches, and both result in a significant simulation speed-up. > out.record_element_a <= a.a; -- Copy > out.record_element_b <= a.b; -- Copy > out.record_element_x <= b; > out.record_element_y <= c; > > Or, a single assignment > out <= > ( > record_element_a => a.a, -- Copy > record_element_b => a.b, -- Copy > record_element_x => b; > record_element_y => c > ); The first approach is slower than the second one. With some other improvements I gained 15% speed-up with multiple concurrent assignments and 30% speed-up with a single assignment. So I'm using a single assignment now. The code is still readable, but the problem remains that the copied signals are written in every delta-cycle in which the signals b or c change. Thus, I also tried to make sure that b and c are calculated at the same delta. Thanks, Matthias From newsfish@newsfish Fri Feb 3 13:08:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:13:40 +0100 Organization: T-Online Lines: 14 Message-ID: References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289337220 00 n18220 08GECmhvv4m7png 101109 21:13:40 X-Complaints-To: usenet-abuse@t-online.de X-ID: VsVUt8Za8eGEPTjM2tLx0b6tm-YejmgGWphamqqDidTMvloI3X1Ak4 User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4354 > The real solution is to avoid retriggering of the process, > which is best done by NOT writing a combinational process > with multiple signals in its sensitivity list. > > Matthias, is there any way you could fold the record > processing into your clocked process, so you know it's > executed only once per cycle? Unfortunately not, but I reduced the number of deltas in which the process (or now concurrent assignment, see other post) is triggered. Matthias From newsfish@newsfish Fri Feb 3 13:08:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsmm00.sul.t-online.de!t-online.de!news.t-online.com!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Element update within records Date: Tue, 09 Nov 2010 22:27:42 +0100 Organization: T-Online Lines: 42 Message-ID: References: <8d6ad69n78dcb5lmfnu2tihbkpo2vcq6ib@4ax.com> <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.t-online.com 1289338067 03 n11093 bGXECfQ64zJoEA4 101109 21:27:47 X-Complaints-To: usenet-abuse@t-online.de X-ID: XpaCy+ZTreljwCoNdkqYVAafRsd9CCB5fx3uhzq4z4KZpvYQhDLV8I User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: <0tobd659o75utqkagdn8d51t5eujaldvd3@4ax.com> X-Enigmail-Version: 1.0.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4355 > Is it just me that pays (almost) no attention to simulation efficiency? > It seems to me that my thinking time dwarfs sim runtime anyway. > And corrupting the design for more "efficient" simulation seems to be a move in > the wrong direction - away from efficient use of my time - to me. Am I so far > out on a limb? Usually I don't care that much either. But think of regression tests that you might want to perform after fixing a bug. Those can be quite time consuming, since you usually perform them for every single change you make on a design. In this particular case, spending one hour in profiling the VHDL code can easily save me many many hours of simulation time later on. Matthias > I try to get the heavy lifting done by fairly well focussed test cases rather > than by distorting the most natural (to me) - and therefore most likely to be > bug-free - design approach in the cause of pandering to simulators. > > Even when I run a long simulation (e.g. error mapping a 32-bit floating point > square root) testing every one of 16 million mantissa values only took an hour > or two, with no concession to fast simulation coding. (About 200 of them had > error just over 0.5LSB so it wasn't 100% P754 compliant). > > Of course by that stage I'm not interactively debugging, but if I were, after > lunch, I could focus on the specific values that were giving trouble. > > The only time simulation speed REALLY bugs me is when vendors insist on > supplying only a gate-level representation of their core (and sometimes even > their testbench - I'm not kidding here!!! *cough* Xilinx PCI express ) - that > is too large to run on their basic pay-for simulator! > > Then I restrict the simulation to a few basic reads and writes, and drop in a > higher level interface (approximating the PCIe core's local bus) for the real > system-level simulations. > > - Brian > From newsfish@newsfish Fri Feb 3 13:08:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o29g2000vbi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Quadruple assignment Date: Wed, 10 Nov 2010 04:49:52 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: References: <8762whfhjv.fsf@merciadriluca-station.MERCIADRILUCA> <8ef78aab-b987-48f0-82bb-1af513c2e729@d8g2000yqf.googlegroups.com> <489d0d5d-ef9d-41a5-9e97-90bbaed59898@c20g2000yqj.googlegroups.com> <8jm2a4F28bU1@mid.individual.net> <685a748b-8d1f-429c-aa75-db66774a1987@f16g2000prj.googlegroups.com> <8jthagFdreU1@mid.individual.net> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289393392 13917 127.0.0.1 (10 Nov 2010 12:49:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 12:49:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o29g2000vbi.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4358 On Nov 9, 1:13=A0pm, Mike Treseler wrote: > On 11/8/2010 8:53 AM, rickman wrote: > > > I'm not sure what your point is. =A0Are you saying that you don't make > > use of the built in global reset function? > > I use Altera parts, and the internal "reset" logic is fixed. > Pins go to Z and flops go to 0. I thought they had dropped that long ago. I have used some pretty old Altera parts and what they do to provide a preset condition is to reset the FF and treat the signal as a low true. Otherwise there are things you couldn't do properly. > > Of course if you use logic to generate > > your own system reset you can set it to whatever you want independent > > of the configuration value. > > This is what I have have always done. > Otherwise, the only way to force a "reset" > is to reload the configuration. I am pretty sure Altera parts have the exact same functionality of a system reset that the Xilinx and Lattice parts do, but it has been years since I have used their tools. One of us needs to check the docs... I'll do that when I get some time. Rick From newsfish@newsfish Fri Feb 3 13:08:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Damian Drewulski Newsgroups: comp.lang.vhdl Subject: matrix generation Date: Wed, 10 Nov 2010 06:57:45 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: <173668ec-83ec-4c17-8e96-fb856140c058@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 94.75.66.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289401066 15139 127.0.0.1 (10 Nov 2010 14:57:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 14:57:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=94.75.66.49; posting-account=a2FzzAoAAAAo1ltX21u5iIbdaYjK0AHF User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; pl; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4359 Hi there, i have some problem. I need to get sorting net. 40 comparators in 81 line. First i declared matrix: type wire is array (0 to 81) of std_logic_vector (7 downto 0); type connections is array (0 to 81) of wire; Then i'm trying to generate a net of comparators. component comparator port( clk : in std_logic; rst : in std_logic; A_in : in std_logic_vector (7 downto 0); B_in : in std_logic_vector (7 downto 0); A_out : out std_logic_vector (7 downto 0); B_out : out std_logic_vector (7 downto 0) ); end component; sorting_net : for i in 0 to 40 generate ins: for j in (0 to 81) generate comparatorx : comparator port map(clk, rst, connections(i*2) of wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j +1), connections(i*2 + 1) of wire (j+1)); end generate; end generate; And after that i get few errors. I use quartus. Anyone could help me? best wishes, Damian From newsfish@newsfish Fri Feb 3 13:08:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!s5g2000yqm.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: XST - configuration - VHDL Date: Wed, 10 Nov 2010 08:53:16 -0800 (PST) Organization: http://groups.google.com Lines: 47 Message-ID: NNTP-Posting-Host: 194.25.252.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289407996 18106 127.0.0.1 (10 Nov 2010 16:53:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 16:53:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s5g2000yqm.googlegroups.com; posting-host=194.25.252.189; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-Via: 1.1 S04921 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13142 comp.lang.vhdl:4360 Dear all, In my current project I have an entity for which I which arhitecture to use on a VHDL file where I instantiate the entity, like following configuration code: -- Embedded configuration -- Select control architecture to use for all : Ctrl2D use entity work.Ctrl2D(rtl_small); Within the VHDL file where Ctrl2D is defined, I have different configurations, namely rtl_tiny and rtl_small. Within each of those, are processes which have variables whose length depend on some constants (KA, KB), like: process_out : process (in_a, in_b) variable var : std_logic_vector (KA-KB-1 downto 0) := (others => '0'); begin I should select which architecture to use in the configuration (rtl_tiny or rtl_small) depending on a given a given set of values KA and KB. For a set of values KA and KB that works fine with rtl_small and having rtl_small selected in the configuration, XST, when parsing, gives me warnign and error messages: Entity compiled. WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null range: -33 downto 0 ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of concat operation is different than size of the target. Entity (Architecture ) compiled. But those lines (157 and 214) are within the architecture rtl_tiny, not rtl_small. I was confident that by selecting the right architecture in the configuration I was completely bypassing everything related to non- desired architectures, but it seems like I was wrong. How can I direct XST to ignore the code of the non-interesting architectures, and parse and synthesize only the one that I selected in the configuration? Thanks a lot in advance, JaaC From newsfish@newsfish Fri Feb 3 13:08:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.glorb.com!news2.glorb.com!postnews.google.com!k30g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Wed, 10 Nov 2010 09:50:05 -0800 (PST) Organization: http://groups.google.com Lines: 84 Message-ID: <93aa53bb-5df3-4ae4-92d9-00d0c09e7a71@k30g2000vbn.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <4ff4f712-4b04-4414-a712-b277acb6cc31@g28g2000pra.googlegroups.com> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289411405 17208 127.0.0.1 (10 Nov 2010 17:50:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 17:50:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k30g2000vbn.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4362 On Nov 8, 12:53=A0pm, JimLewis wrote: > > The closest vhdl vector arithmetic comes to true integer arithmetic > > accuracy is the fixed point package types, with zero fractional bits > > declared. Fixed point operators automatically pad the result size to > > account for accuracy in all cases, except one: a ufixed minus a ufixed > > is still a ufixed (but actually bigger by one bit! go figure) rather > > than an sfixed. With the almost universal need to resize sfixed/ufixed > > results to fit in an assigned signal/variable, the conversion from > > sfixed to ufixed could easily be handled in the resize function > > anyway. > > I think both have issues. =A0For example: > signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto > 0) ; > signal Y_ufixed11 : ufixed(10 downto 0) ; > Y_ufixed11 <=3D A_ufixed8 + B_ufixed8 + C_ufixed8 + D_ufixed8 ; > > results in a different size than: > signal A_ufixed8, B_ufixed8, C_ufixed8, D_ufixed8 : ufixed(7 downto > 0) ; > signal Y_ufixed10 : ufixed(9 downto 0) ; > Y_ufixed10 <=3D (A_ufixed8 + B_ufixed8) + (C_ufixed8 + D_ufixed8) ; If you used y_ufixed10 <=3D resize(expr, y_ufixed10); it wouldn't make any difference, no matter which form of the expression you used. I find it very seldom that you do not have to use a resize function prior to an assignment with the fixed point packages, which is why overloading the assignment operator to include the resize functionality makes a lot of sense. Again, this would work very similarly to the way integer expressions and assignments work, but without the limitations of size in integer. > > > Or better yet, allow assignment operators to be overloaded so that > > they can do the resizing automatically. > > It would be an interesting proposal. If it gets approved, are you > interested in writing it? =A0 I don't have any compiler writing experience, so defining the syntax to use for overloading an assignment operator, and limiting its use to cases that are reasonable to implement would be beyond me. But I am certainly willing to help where I can (defining what we want to be able to do). > Can you formulate something that > chooses between modulo math (like unsigned/signed) or full precision > arith > (like ufixed/sfixed)? =A0If you blow the doors open and allow anything, > I > would think that is bad. =A0If you add more saftey such as =A0enforcement > of > ranges for ufixed/sfixed (so that more than size is enforced) then it > would > be exciting. Allowing blanket overloading of assignment operators would necessarily "blow the doors off". Perhaps restricting overloaded assignment operators to be defined in the same declarative region as the type to which they assign would help, especially in the case of the standard packages (users could not re-overload the assignment operators outside the package). An overloaded assignment operator for vectors, unlike a standard operator, would have to be able to know what the target range is, which is not currently possible for a function in vhdl. So it would have to be handled more like a procedure with an in and out argument, unless we developed some whole new syntax. It would not be the assignment operator which would define modulo (roll-over) math vs full-precision. That is controlled by the type, and those operators that are defined for the type. The assignment operator could define behavior like truncate, saturate, round, etc. when assigning a larger vector into a smaller one. On the other hand, we would not need overloaded assignment operators (and all of their potential pitfalls blowing doors off) if we had an arbitrarily sized type of integer, including fixed point capability and bit-wise logical operations defined. Then there would be no overloaded assignment operators and all their potential pitfalls to deal with. Andy From newsfish@newsfish Fri Feb 3 13:08:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!fh19g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:16:18 -0800 (PST) Organization: http://groups.google.com Lines: 66 Message-ID: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289412978 22458 127.0.0.1 (10 Nov 2010 18:16:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:16:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fh19g2000vbb.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13144 comp.lang.vhdl:4363 On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona wrote: > Dear all, > > In my current project I have an entity for which I which arhitecture > to use on a VHDL file where I instantiate the entity, like following > configuration code: > > -- Embedded configuration > -- Select control architecture to use > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > Within the VHDL file where Ctrl2D is defined, I have different > configurations, namely rtl_tiny and rtl_small. Within each of those, > are processes which have variables whose length depend on some > constants (KA, KB), like: > > process_out : process (in_a, in_b) > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (other= s =3D> > '0'); > =A0 begin > > I should select which architecture to use in the configuration > (rtl_tiny or rtl_small) depending on a given a given set of values KA > and KB. For a set of values KA and KB that works fine with rtl_small > and having rtl_small selected in the configuration, XST, when parsing, > gives me warnign and error messages: > > Entity compiled. > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > range: -33 downto 0 > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > concat operation is different than size of the target. > Entity (Architecture ) compiled. > > But those lines (157 and 214) are within the architecture rtl_tiny, > not rtl_small. > > I was confident that by selecting the right architecture in the > configuration I was completely bypassing everything related to non- > desired architectures, but it seems like I was wrong. > > How can I direct XST to ignore the code of the non-interesting > architectures, and parse and synthesize only the one that I selected > in the configuration? > > Thanks a lot in advance, > > JaaC Unlike simulation tools, synthesis tools combine the analysis and elaboration phases into one. This is probably leading to your problem. Leaving something out in a configuration is not quite like conditionally compiling it. Everything gets analyzed (if it is in a file that is being analyzed), whether it is chosen at elaboration or not. Some simulators have options for compiling (analyzing) only certain types of units (packages, package bodies, entities, architectures, etc.) and ignoring others in the same file. I have not seen that in a synthesis tool. Other than fixing the problem with the mismatched size (if even possible), I would suggest moving the two architectures into separate files, and only including the appropriate file in the project. Andy From newsfish@newsfish Fri Feb 3 13:08:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tramontana.escomposlinux.org!cagarruta.escomposlinux.org!escomposlinux.org!news.antakira.com!weretis.net!feeder4.news.weretis.net!news.musoftware.de!wum.musoftware.de!news.weisnix.org!newsfeed.ision.net!newsfeed2.easynews.net!ision!newsfeed3.dallas1.level3.net!newsfeed2.dallas1.level3.net!news.level3.com!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:50:34 -0800 (PST) Organization: http://groups.google.com Lines: 91 Message-ID: References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> NNTP-Posting-Host: 62.143.30.164 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415035 7638 127.0.0.1 (10 Nov 2010 18:50:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:50:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=62.143.30.164; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13145 comp.lang.vhdl:4364 On 10 Nov., 19:16, Andy wrote: > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > wrote: > > Dear all, > > > In my current project I have an entity for which I which arhitecture > > to use on a VHDL file where I instantiate the entity, like following > > configuration code: > > > -- Embedded configuration > > -- Select control architecture to use > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > Within the VHDL file where Ctrl2D is defined, I have different > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > are processes which have variables whose length depend on some > > constants (KA, KB), like: > > > process_out : process (in_a, in_b) > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (oth= ers =3D> > > '0'); > > =A0 begin > > > I should select which architecture to use in the configuration > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > and KB. For a set of values KA and KB that works fine with rtl_small > > and having rtl_small selected in the configuration, XST, when parsing, > > gives me warnign and error messages: > > > Entity compiled. > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > range: -33 downto 0 > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > concat operation is different than size of the target. > > Entity (Architecture ) compiled. > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > not rtl_small. > > > I was confident that by selecting the right architecture in the > > configuration I was completely bypassing everything related to non- > > desired architectures, but it seems like I was wrong. > > > How can I direct XST to ignore the code of the non-interesting > > architectures, and parse and synthesize only the one that I selected > > in the configuration? > > > Thanks a lot in advance, > > > JaaC > > Unlike simulation tools, synthesis tools combine the analysis and > elaboration phases into one. This is probably leading to your problem. > Leaving something out in a configuration is not quite like > conditionally compiling it. Everything gets analyzed (if it is in a > file that is being analyzed), whether it is chosen at elaboration or > not. Some simulators have options for compiling (analyzing) only > certain types of units (packages, package bodies, entities, > architectures, etc.) and ignoring others in the same file. I have not > seen that in a synthesis tool. > > Other than fixing the problem with the mismatched size (if even > possible), I would suggest moving the two architectures into separate > files, and only including the appropriate file in the project. > > Andy Hi Andy, Thanks for your reply, I found the solution however: adding pragmas: architecture struct of Stack2D is signal dat_2ext : buf2dwrd; signal rd_2ext : std_logic; signal dat_2slv : buf2dwrd; signal wr_2slv : std_logic; -- pragma synthesis on for all : Ctrl2D use entity work.Ctrl2D(rtl_small); -- pragma synthesis off begin The commented pragmas did the job. Regards. From newsfish@newsfish Fri Feb 3 13:08:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 10:54:55 -0800 (PST) Organization: http://groups.google.com Lines: 109 Message-ID: <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> NNTP-Posting-Host: 62.143.30.164 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415295 9942 127.0.0.1 (10 Nov 2010 18:54:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 18:54:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=62.143.30.164; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; de; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13146 comp.lang.vhdl:4365 On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona wrote: > On 10 Nov., 19:16, Andy wrote: > > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > wrote: > > > Dear all, > > > > In my current project I have an entity for which I which arhitecture > > > to use on a VHDL file where I instantiate the entity, like following > > > configuration code: > > > > -- Embedded configuration > > > -- Select control architecture to use > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > configurations, namely rtl_tiny and rtl_small. Within each of those, > > > are processes which have variables whose length depend on some > > > constants (KA, KB), like: > > > > process_out : process (in_a, in_b) > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D (o= thers =3D> > > > '0'); > > > =A0 begin > > > > I should select which architecture to use in the configuration > > > (rtl_tiny or rtl_small) depending on a given a given set of values KA > > > and KB. For a set of values KA and KB that works fine with rtl_small > > > and having rtl_small selected in the configuration, XST, when parsing= , > > > gives me warnign and error messages: > > > > Entity compiled. > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > range: -33 downto 0 > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > concat operation is different than size of the target. > > > Entity (Architecture ) compiled. > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > not rtl_small. > > > > I was confident that by selecting the right architecture in the > > > configuration I was completely bypassing everything related to non- > > > desired architectures, but it seems like I was wrong. > > > > How can I direct XST to ignore the code of the non-interesting > > > architectures, and parse and synthesize only the one that I selected > > > in the configuration? > > > > Thanks a lot in advance, > > > > JaaC > > > Unlike simulation tools, synthesis tools combine the analysis and > > elaboration phases into one. This is probably leading to your problem. > > Leaving something out in a configuration is not quite like > > conditionally compiling it. Everything gets analyzed (if it is in a > > file that is being analyzed), whether it is chosen at elaboration or > > not. Some simulators have options for compiling (analyzing) only > > certain types of units (packages, package bodies, entities, > > architectures, etc.) and ignoring others in the same file. I have not > > seen that in a synthesis tool. > > > Other than fixing the problem with the mismatched size (if even > > possible), I would suggest moving the two architectures into separate > > files, and only including the appropriate file in the project. > > > Andy > > Hi Andy, > > Thanks for your reply, I found the solution however: adding pragmas: > > architecture struct of Stack2D is > > =A0 signal dat_2ext : buf2dwrd; > =A0 signal rd_2ext =A0: std_logic; > =A0 signal dat_2slv : buf2dwrd; > =A0 signal wr_2slv =A0: std_logic; > > =A0 -- pragma synthesis on > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > =A0 -- pragma synthesis off > > begin > > The commented pragmas did the job. > > Regards. Dear all, By the way, is there a way to make a conditional selection of architecture to use, something in the lines of: for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) else use entity work.Ctrl2D(architecture_b); ??? Or is there an alternative approach? Thanks lot in advance. JaaC From newsfish@newsfish Fri Feb 3 13:08:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gandalf.srv.welterde.de!news.unit0.net!news.glorb.com!news2.glorb.com!postnews.google.com!k3g2000vbp.googlegroups.com!not-for-mail From: Kevin Thibedeau Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Wed, 10 Nov 2010 11:00:14 -0800 (PST) Organization: http://groups.google.com Lines: 35 Message-ID: <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> NNTP-Posting-Host: 173.85.161.91 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289415614 12838 127.0.0.1 (10 Nov 2010 19:00:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 10 Nov 2010 19:00:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000vbp.googlegroups.com; posting-host=173.85.161.91; posting-account=WHzLMgoAAABnFPi2ZJ1UFqg0jT69I-kr User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4366 On Nov 4, 11:30=A0pm, whygee wrote: > Hi ! > > Brian Drummond wrote: > > On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: > >> Any hint ? Did I miss something ? > > bit_vector should be less heavyweight than std_logic_vector. > > sure but i want to use integers :-/ > > =A0> - Brian > > Nicolas Matringe wrote : > =A0> That's strong typing for you... > it's not a problem of typing, i can create new functions, > however I see nowhere an explanation of these missing operations. > why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) > and not on integer, as in any other language ? > > =A0> Nicolas > yg > --http://ygdes.com/http://yasep.org The reason is because this is an artifact carried over from Ada-83. In Ada and VHDL, integers are always considered to be signed even if the range is restricted to positive numbers. There is no universal way to handle boolean operations on signed numbers so it was decided to leave out implicit boolean operators in Ada. This was remedied in Ada-95 with the addition of modular types. They are restricted to unsigned integers and *do* have implicit boolean operators. As their name suggests, modular types also wraparound on overflow and underflow without throwing an exception. It would be interesting to consider adding them to a future revision to VHDL for those who want an efficient alternative to the array types. From newsfish@newsfish Fri Feb 3 13:08:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!newsfeed01.sul.t-online.de!t-online.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Wed, 10 Nov 2010 13:34:08 -0800 Lines: 54 Message-ID: <8k0hecF277U1@mid.individual.net> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net dWZzVs+RNsOF7iSaEeYZ5w3wOQzhqcFYMrke6M8ybXT2Sa0dC0 Cancel-Lock: sha1:jr0Ug82ZSw0UVhDKv9LtL+pYAiE= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> Xref: feeder.eternal-september.org comp.arch.fpga:13147 comp.lang.vhdl:4367 On 11/10/2010 10:54 AM, Jaime Andrs Aranguren Cardona wrote: >> architecture struct of Stack2D is >> >> signal dat_2ext : buf2dwrd; >> signal rd_2ext : std_logic; >> signal dat_2slv : buf2dwrd; >> signal wr_2slv : std_logic; >> >> -- pragma synthesis on >> for all : Ctrl2D use entity work.Ctrl2D(rtl_small); >> -- pragma synthesis off >> >> begin >> >> The commented pragmas did the job. Maybe. Were both architectures in the synthesis file list? If so which one was first? I use a similar trick to insert debug code into synthesis sources: -- synthesis translate off spy: process (strobe_s) is begin -- process watch if falling_edge(strobe_s) then report("data = ", work.my_pkg.std2hexstr(my_ctr)); end if; end process spy; -- synthesis translate on > By the way, is there a way to make a conditional selection of > architecture to use, something in the lines of: > > for all : Ctrl2D if A = 0 use entity work.Ctrl2D(architecture_a) else > use entity work.Ctrl2D(architecture_b); ??? Not that I know of for synthesis, where I must declare one top entity and file list. There is no notion of vhdl libraries or configurations. > Or is there an alternative approach? I could generate one direct instance or another based on a packaged constant value, but I find this confusing. If the architecture differences are much less the spare fpga resources, I might combine both modes and select using a mode register or a jumper. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r14g2000yqa.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: matrix generation Date: Thu, 11 Nov 2010 00:45:01 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <12e7ed74-0e4d-4ac0-b9be-6e85d5d2ef77@r14g2000yqa.googlegroups.com> References: <173668ec-83ec-4c17-8e96-fb856140c058@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289465101 20439 127.0.0.1 (11 Nov 2010 08:45:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 08:45:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r14g2000yqa.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4368 On Nov 10, 2:57=A0pm, Damian Drewulski wrote: > Hi there, > i have some problem. I need to get sorting net. 40 comparators in 81 > line. > > First i declared matrix: > > =A0 =A0 =A0 =A0 type wire is array (0 to 81) of std_logic_vector (7 downt= o 0); > =A0 =A0 =A0 =A0 type connections is array (0 to 81) of wire; > > Then i'm trying to generate a net of comparators. > > component comparator > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 clk : in std_logic; > =A0 =A0 =A0 =A0 rst : in std_logic; > > =A0 =A0A_in : in std_logic_vector (7 downto 0); > =A0 =A0 =A0 =A0 B_in : in std_logic_vector (7 downto 0); > > =A0 =A0 =A0 =A0 A_out : out std_logic_vector (7 downto 0); > =A0 =A0 =A0 =A0 B_out : out std_logic_vector (7 downto 0) > ); > end component; > > sorting_net : for i in 0 to 40 generate > =A0 =A0 =A0 =A0 ins: for j in (0 to 81) generate > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 comparatorx : comparator port map(clk, rs= t, connections(i*2) of > wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j > +1), connections(i*2 + 1) of wire (j+1)); > =A0 =A0 =A0 =A0 end generate; > end generate; > > And after that i get few errors. I use quartus. > Anyone could help me? > > best wishes, > Damian You have to connect the IO of the instantiation to signals or IO, you cannot connect them to types. You need to declare a signal of type "connections" and connect everything to that. From newsfish@newsfish Fri Feb 3 13:08:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 11 Nov 2010 15:52:54 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> In-Reply-To: <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 56 Message-ID: <4cdc0343$0$14262$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 4c593229.news.skynet.be X-Trace: 1289487171 news.skynet.be 14262 91.177.233.223:58145 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4369 Kevin Thibedeau wrote: > On Nov 4, 11:30 pm, whygee wrote: >> Hi ! >> >> Brian Drummond wrote: >>> On Thu, 04 Nov 2010 12:28:31 +0100, whygee wrote: >>>> Any hint ? Did I miss something ? >>> bit_vector should be less heavyweight than std_logic_vector. >> sure but i want to use integers :-/ >> >> > - Brian >> >> Nicolas Matringe wrote : >> > That's strong typing for you... >> it's not a problem of typing, i can create new functions, >> however I see nowhere an explanation of these missing operations. >> why do AND/OR/XOR work on bit(_vector) and std_(u)logic(vector) >> and not on integer, as in any other language ? >> >> > Nicolas >> yg >> --http://ygdes.com/http://yasep.org > > The reason is because this is an artifact carried over from Ada-83. In > Ada and VHDL, integers are always considered to be signed even if the > range is restricted to positive numbers. There is no universal way to > handle boolean operations on signed numbers so it was decided to leave > out implicit boolean operators in Ada. > > This was remedied in Ada-95 with the addition of modular types. They > are restricted to unsigned integers and *do* have implicit boolean > operators. As their name suggests, modular types also wraparound on > overflow and underflow without throwing an exception. It would be > interesting to consider adding them to a future revision to VHDL for > those who want an efficient alternative to the array types. Fascinating stuff - thanks for this info. Restricting the bit view to the "unsigned" domain makes a lot of sense (talking from my own language design experience). During a quick survey I found that part of the rationale behind modular types was "easier interaction with hardware". Interesting, isn't it? It seems that a lot of the groundwork that would turn VHDL into the "easy" HDL is readily available. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!x4g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Thu, 11 Nov 2010 09:03:19 -0800 (PST) Organization: http://groups.google.com Lines: 142 Message-ID: <2b0654d8-ade1-4d10-a4f5-b864964ea1ad@x4g2000pre.googlegroups.com> References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289495000 22647 127.0.0.1 (11 Nov 2010 17:03:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 17:03:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x4g2000pre.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13153 comp.lang.vhdl:4370 On Nov 10, 12:54=A0pm, Jaime Andr=E9s Aranguren Cardona wrote: > On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona > > > > > > wrote: > > On 10 Nov., 19:16, Andy wrote: > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > wrote: > > > > Dear all, > > > > > In my current project I have an entity for which I which arhitectur= e > > > > to use on a VHDL file where I instantiate the entity, like followin= g > > > > configuration code: > > > > > -- Embedded configuration > > > > -- Select control architecture to use > > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > > configurations, namely rtl_tiny and rtl_small. Within each of those= , > > > > are processes which have variables whose length depend on some > > > > constants (KA, KB), like: > > > > > process_out : process (in_a, in_b) > > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:=3D = (others =3D> > > > > '0'); > > > > =A0 begin > > > > > I should select which architecture to use in the configuration > > > > (rtl_tiny or rtl_small) depending on a given a given set of values = KA > > > > and KB. For a set of values KA and KB that works fine with rtl_smal= l > > > > and having rtl_small selected in the configuration, XST, when parsi= ng, > > > > gives me warnign and error messages: > > > > > Entity compiled. > > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > > range: -33 downto 0 > > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > > concat operation is different than size of the target. > > > > Entity (Architecture ) compiled. > > > > > But those lines (157 and 214) are within the architecture rtl_tiny, > > > > not rtl_small. > > > > > I was confident that by selecting the right architecture in the > > > > configuration I was completely bypassing everything related to non- > > > > desired architectures, but it seems like I was wrong. > > > > > How can I direct XST to ignore the code of the non-interesting > > > > architectures, and parse and synthesize only the one that I selecte= d > > > > in the configuration? > > > > > Thanks a lot in advance, > > > > > JaaC > > > > Unlike simulation tools, synthesis tools combine the analysis and > > > elaboration phases into one. This is probably leading to your problem= . > > > Leaving something out in a configuration is not quite like > > > conditionally compiling it. Everything gets analyzed (if it is in a > > > file that is being analyzed), whether it is chosen at elaboration or > > > not. Some simulators have options for compiling (analyzing) only > > > certain types of units (packages, package bodies, entities, > > > architectures, etc.) and ignoring others in the same file. I have not > > > seen that in a synthesis tool. > > > > Other than fixing the problem with the mismatched size (if even > > > possible), I would suggest moving the two architectures into separate > > > files, and only including the appropriate file in the project. > > > > Andy > > > Hi Andy, > > > Thanks for your reply, I found the solution however: adding pragmas: > > > architecture struct of Stack2D is > > > =A0 signal dat_2ext : buf2dwrd; > > =A0 signal rd_2ext =A0: std_logic; > > =A0 signal dat_2slv : buf2dwrd; > > =A0 signal wr_2slv =A0: std_logic; > > > =A0 -- pragma synthesis on > > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > =A0 -- pragma synthesis off > > > begin > > > The commented pragmas did the job. > > > Regards. > > Dear all, > > By the way, is there a way to make a conditional selection of > architecture to use, something in the lines of: > > for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) =A0els= e > use entity work.Ctrl2D(architecture_b); =A0 ??? > > Or is there an alternative approach? > > Thanks lot in advance. > > JaaC- Hide quoted text - > > - Show quoted text - The only way to do that is with an if-generate on the instantiation, not the configuration. In fact, since the '93 standard, you can directly instantiate an entity and its architecture: if a =3D 0 generate u1: entity work.entity_name(architecture_name)... end generate; if a /=3D 0 generate u1: entity work.entity_name(alternative_architecture_name) ... end generate; You don't even need to mess with a configuration! Andy From newsfish@newsfish Fri Feb 3 13:08:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!r21g2000pri.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 09:14:23 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289495663 7723 127.0.0.1 (11 Nov 2010 17:14:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 17:14:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r21g2000pri.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4371 I have only been programming full-time in VHDL for a little over a year so I tend to be skeptical at my ability to come up with suggestions that would enhance the language. So before I go through any process to make any official request I'd like to get some feedback here on a few ideas that I've felt would improve the VHDL experience. 1. 'SCOPE' or 'CONTEXT' - a keyword to define a scope. An example usage follows: CountDown : CONTEXT VARIABLE Counter : UNSIGNED( 15 DOWNTO 0 ) := x"FFFF"; BEGIN Counter := Counter - 1; END CONTEXT CountDown; Counter := Counter - 1; -- Error: Counter is not defined here. This is a trivial example, but the idea is as follows. Many variables are used only a few times and in a small section. By having the variable declaration close to where it's used it makes the code more readable as the programmer does not need to search through the file for the definition. Originally the idea was to simply allow the BEGIN keyword to be used in IF statements, but the syntax would be very odd with respect to how it would look if you used ELSE statements. This is broader. I would suggest CONTEXT be allowed both within a process body and outside of it for the benefit of concurrent statements. This models one of the uses of the curly brackets in C++. 2. Often times signals are used only within a single process because the semantics are ideal if you don't want changes to take effect until the next clock cycle. For example, all of my state machines, even if they're only defined within a process, are signals. Similar to the above reasoning of keeping variable declarations close to where they're used, I'd like to see the SIGNAL keyword be legal to use wherever you can use VARIABLE. I realize simulators require more CPU resources to simulate signals than variables and so some people try to discourage their use, but for those of us who use them often I feel this would help readability. 3. This is less well thought out than the two above and comes more in the shape of a problem than a solution. VHDL's ability for static elaboration is amazing in comparison to many other languages (i.e. C+ +). However, consider the following type. Imagine that I wanted to implement a LFSR that cycles every N increments. Can this be coded in VHDL 2008? I.E., can I have something like the following: TYPE lfsr5 IS lfsr( period => 5 ); ... VARIABLE state : lfsr5 := lfsr5'POS(0); ... CASE state IS WHEN lfsr5'POS(0) => ... WHEN lfsr5'POS(1) => ... ... WHEN lfsr5'POS(4) => ... END CASE; state := state + 1; I don't see how to do anything quite like that at the moment. The values of POS(0) through POS(1) for an LFSR depend on the period so they would need to be generated during elaboration. I wouldn't mind a custom attribute other than POS to be used, I just don't see how to do this as a generic variable. If I'm mistaken please let me know. From newsfish@newsfish Fri Feb 3 13:08:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!postnews.google.com!y2g2000prf.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 10:17:15 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289499435 10134 127.0.0.1 (11 Nov 2010 18:17:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 18:17:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y2g2000prf.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4372 It seems like what you want for #1 is to be able to use the block statement as a sequential statement. It would be just as valuable, and syntactically simpler, to allow declarative regions within control statements (if, case, loop, etc.; anything with an "end" should be able to have a declarative region). An existing solution to #2 is to wrap your process with a block statement that declares the signals that are "local" to the process. This can also be used to declare signals (and types) that are used to communicate only between two processes (e.g. a clocked and combo process pair) by putting both processes in the same block. Opinions vary, but the semantics of signal assignment/update rarely lead to a "more readable" description within a process. I prefer the semantics of variables because it "reads" like it executes. There is no hidden "oh, this doesn't actually change until the process suspends" garbage. I have no comment on #3. Andy From newsfish@newsfish Fri Feb 3 13:08:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a9g2000pro.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 11:53:59 -0800 (PST) Organization: http://groups.google.com Lines: 69 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289505239 14887 127.0.0.1 (11 Nov 2010 19:53:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 19:53:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a9g2000pro.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4373 On Nov 11, 1:17=A0pm, Andy wrote: > It seems like what you want for #1 is to be able to use the block > statement as a sequential statement. It would be just as valuable, and > syntactically simpler, to allow declarative regions within control > statements (if, case, loop, etc.; anything with an "end" should be > able to have a declarative region). > > An existing solution to #2 is to wrap your process with a block > statement that declares the signals that are "local" to the process. > This can also be used to declare signals (and types) that are used to > communicate only between two processes (e.g. a clocked and combo > process pair) by putting both processes in the same block. > > Opinions vary, but the semantics of signal assignment/update rarely > lead to a "more readable" description within a process. I prefer the > semantics of variables because it "reads" like it executes. There is > no hidden "oh, this doesn't actually change until the process > suspends" garbage. > > I have no comment on #3. > > Andy Thanks - very informative. Yes, I suppose I am simply looking for a sequential version of block. As I said, my original suggestion was going to be to allow the use of BEGIN within control statements, but the following usage bothered me: IF Condition THEN VARIABLE LocalValue : LocalType :=3D LocalInitialization; BEGIN DoSomething; ELSE DoSomethingElse; END IF; Is LocalValue defined in both branches of the if statement? We'd want it to be so, yes, but I could see how it might possibly lead to occasional (and/or newbie) confusion. The other issue was that if the BEGIN syntax is used as above it would lead to the BEGIN keyword being optional in some locations and mandatory in others (unless the definitions of many other keywords). Although I will admit that there are many times I've wanted to not write BEGIN (i.e. functions/procedures/processes where I have no variables...), there does tend to be inertia to such wide-scale changes, even if they don't break previous code. As for the comment on #2, this certainly does most of what I want, and a bit more. That said, when I use a signal purely inside a process it's not as clean, but it'll certainly help make my code at least a little more readable, especially in the clocked/combo pair example you cited. Often times I find myself write code "backwards" though when I use variables instead of signals. I.E., if I have the following schedule of tasks to accomplish, each taking 1 clock cycle, and depending on each other: A < B < C, that is C depends on the result of B depends on the result of A, if their results are output as variables I tend to write the code: C B A This is (to me) more opaque to read. But different developers will do things differently, and as long as people are using signals the way I use them, it would be nice to be able to declare them closer to where they're used. From newsfish@newsfish Fri Feb 3 13:08:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!o11g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Thu, 11 Nov 2010 13:33:56 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 173.13.214.113 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289511236 2208 127.0.0.1 (11 Nov 2010 21:33:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 21:33:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000prf.googlegroups.com; posting-host=173.13.214.113; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4374 On Nov 8, 12:57 pm, Andy wrote: > The VHDL standard has already adopted an assumed two's complement > numeric representation for vectors (numeric_std, numeric_std_unsigned, > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > representation for integes as well?! Your statement is not exactly correct. "vectors" are not 2's complement. numeric_std is 2's complement. SLV is still not arithmetic at all. That is the difference. If you wanted to add a 2's complement integer type as a new type then that would be backwards compatible by not changing the standard integer type. The new type could be defined in something like integer_numeric_std or maybe added to numeric_std. > The primary problem with vhdl vector based arithmetic (numeric_*) is > that it rolls over (not to signed, but what's the difference, an > unsigned rollover is still inaccurate). Take two unsigned, add them > together, and you can get a result that is less than either of the > operands. What you call "inaccurate" is a result of limited range of the representation. What would you have the implementation do when the "overflow" occurs? I can see three choices: roll over treating the limited range as modulo arithmetic (minimum logic), saturate at the max and min of the range (more logic and still "inaccurate") or just not perform the operation (also more logic and who knows what "inaccurate" really means in this case). Both can/should throw an error if the operation is actually doing arithmetic. But it is often that a counter is intended to roll over. For those I have to use an explicit modulo operator. > The closest vhdl vector arithmetic comes to true integer arithmetic > accuracy is the fixed point package types, with zero fractional bits > declared. Fixed point operators automatically pad the result size to > account for accuracy in all cases, except one: a ufixed minus a ufixed > is still a ufixed (but actually bigger by one bit! go figure) rather > than an sfixed. With the almost universal need to resize sfixed/ufixed > results to fit in an assigned signal/variable, the conversion from > sfixed to ufixed could easily be handled in the resize function > anyway. > > Or better yet, allow assignment operators to be overloaded so that > they can do the resizing automatically. > > Hey, I can dream, can't I? I believe overloading operators has been suggested for the next go around on the VHDL spec. I have no idea if this would create any problems. Rick From newsfish@newsfish Fri Feb 3 13:08:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z22g2000pri.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Programmable Logic at StackExchange Date: Thu, 11 Nov 2010 15:43:05 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289518986 26444 127.0.0.1 (11 Nov 2010 23:43:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 23:43:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z22g2000pri.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4375 Someone recently added a Programmable Logic Stack on Stack Exchange, and it needs more followers to get official status. As most VHDL developers can attest, getting information can be difficult, and these stack sites (the original is StackOverflow.com) are immensely useful. The site can be found here: http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design Someone tried to start a VHDL stack but it was too specific and was pruned. From newsfish@newsfish Fri Feb 3 13:08:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r31g2000prg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 15:50:22 -0800 (PST) Organization: http://groups.google.com Lines: 67 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289519423 8779 127.0.0.1 (11 Nov 2010 23:50:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Nov 2010 23:50:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r31g2000prg.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4376 On Nov 11, 1:53=A0pm, Jonathan Ross wrote: > > Thanks - very informative. Yes, I suppose I am simply looking for a > sequential version of block. As I said, my original suggestion was > going to be to allow the use of BEGIN within control statements, but > the following usage bothered me: > > IF Condition THEN > =A0 =A0VARIABLE LocalValue : LocalType :=3D LocalInitialization; > BEGIN > =A0 =A0DoSomething; > ELSE > =A0 =A0DoSomethingElse; > END IF; > > Is LocalValue defined in both branches of the if statement? We'd want > it to be so, yes, but I could see how it might possibly lead to > occasional (and/or newbie) confusion. > Every other place BEGIN is used in VHDL, its context continues until the corresponding END. I could easily agree with a change that made BEGIN keywords optional if there were no declarative region needed, for all cases, including process, architecture, etc. "IS" is already optional after PROCESS (...). > Often times I find myself write code "backwards" though when I use > variables instead of signals. I.E., if I have the following schedule > of tasks to accomplish, each taking 1 clock cycle, and depending on > each other: A < B < C, that is C depends on the result of B depends on > the result of A, if their results are output as variables I tend to > write the code: > > C > B > A > > This is (to me) more opaque to read. That's part of the unintuitiveness of signals: a <=3D b; b <=3D c; has exactly the same results as: b <=3D c; a <=3D b; This is not intuitive. The difference in behavior between sequential signal assignments and concurrent signal assignments is muddied because the order of statements does not matter in either case, which leads to lots of confusion with newbies. A sequential signal assignment is not quite sequential, but not quite concurrent either. With variables, the assignment executes entirely in the order it is written, and as expected, the different orders have different results. Having to "reverse the order" is no different whether you are writing code for compilation and execution on a processor, or on an FPGA/ASIC. Andy From newsfish@newsfish Fri Feb 3 13:08:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!r21g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Thu, 11 Nov 2010 18:03:21 -0800 (PST) Organization: http://groups.google.com Lines: 81 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289527401 5757 127.0.0.1 (12 Nov 2010 02:03:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 02:03:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r21g2000pri.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4377 On Nov 11, 6:50=A0pm, Andy wrote: > On Nov 11, 1:53=A0pm, Jonathan Ross > wrote: > > > > > > > Thanks - very informative. Yes, I suppose I am simply looking for a > > sequential version of block. As I said, my original suggestion was > > going to be to allow the use of BEGIN within control statements, but > > the following usage bothered me: > > > IF Condition THEN > > =A0 =A0VARIABLE LocalValue : LocalType :=3D LocalInitialization; > > BEGIN > > =A0 =A0DoSomething; > > ELSE > > =A0 =A0DoSomethingElse; > > END IF; > > > Is LocalValue defined in both branches of the if statement? We'd want > > it to be so, yes, but I could see how it might possibly lead to > > occasional (and/or newbie) confusion. > > Every other place BEGIN is used in VHDL, its context continues until > the corresponding END. > > I could easily agree with a change that made BEGIN keywords optional > if there were no declarative region needed, for all cases, including > process, architecture, etc. =A0"IS" is already optional after PROCESS > (...). > > > Often times I find myself write code "backwards" though when I use > > variables instead of signals. I.E., if I have the following schedule > > of tasks to accomplish, each taking 1 clock cycle, and depending on > > each other: A < B < C, that is C depends on the result of B depends on > > the result of A, if their results are output as variables I tend to > > write the code: > > > C > > B > > A > > > This is (to me) more opaque to read. > > That's part of the unintuitiveness of signals: > > a <=3D b; > b <=3D c; > > has exactly the same results as: > > b <=3D c; > a <=3D b; > > This is not intuitive. > > The difference in behavior between sequential signal assignments and > concurrent signal assignments is muddied because the order of > statements does not matter in either case, which leads to lots of > confusion with newbies. A sequential signal assignment is not quite > sequential, but not quite concurrent either. > > With variables, the assignment executes entirely in the order it is > written, and as expected, the different orders have different results. > > Having to "reverse the order" is no different whether you are writing > code for compilation and execution on a processor, or on an FPGA/ASIC. When you say "unintuitive" you mean you have learned how software works and had to relearn how hardware works. HDL is the way it is because it is describing hardware. Trying to treat HDL like software may result in a working design, but has great potential to cause problems. Yes, if you already know how procedural languages work, you will have to forget that or at least not think HDL is similar. I know that is what I had to do. Rick From newsfish@newsfish Fri Feb 3 13:08:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 09:13:38 +0000 Organization: TRW Conekt Lines: 40 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 9vXdUszZ2hLRuWwQfrdkTwImBEZgmfME9HuuaXioO841MLmfc= Cancel-Lock: sha1:6VaojYq7eM+UX3n+7tfOzk5W7OM= sha1:sqEuWBAl1iaUCT7/vwcDMAtus+U= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4378 Jan Decaluwe writes: > Kevin Thibedeau wrote: >> Ada and VHDL, integers are always considered to be signed even if the >> range is restricted to positive numbers. There is no universal way to >> handle boolean operations on signed numbers so it was decided to leave >> out implicit boolean operators in Ada. >> >> This was remedied in Ada-95 with the addition of modular types. They >> are restricted to unsigned integers and *do* have implicit boolean >> operators. As their name suggests, modular types also wraparound on >> overflow and underflow without throwing an exception. It would be >> interesting to consider adding them to a future revision to VHDL for >> those who want an efficient alternative to the array types. > > Fascinating stuff - thanks for this info. > > Restricting the bit view to the "unsigned" domain makes a lot > of sense (talking from my own language design experience). > > During a quick survey I found that part of the rationale > behind modular types was "easier interaction with hardware". > Interesting, isn't it? > > It seems that a lot of the groundwork that would turn VHDL > into the "easy" HDL is readily available. > Maybe we should just quit VHDL and start synthesising Ada directly (with only half-a-smiley ;) Maybe call it SystemAda :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:08:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Fri, 12 Nov 2010 09:19:34 +0000 Organization: TRW Conekt Lines: 21 Message-ID: References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net gb0ZfD4FNU4p3l6XjkHGkghMnOkPMGfRfGXubudzRvkM9avAU= Cancel-Lock: sha1:NIQIIiPKpun3zIig8Qlr9DH16KE= sha1:RdS2SnkXO6i9CFFPmmd91HlQaBk= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4379 Andy writes: > It seems like what you want for #1 is to be able to use the block > statement as a sequential statement. It would be just as valuable, and > syntactically simpler, to allow declarative regions within control > statements (if, case, loop, etc.; anything with an "end" should be > able to have a declarative region). Which is the C99 and C++ way (dunno if that's in its favour or not :) Personally, I'd like it. I think the "if blah then variable.... begin... else... end;" proposal made downthread could work well. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:08:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 12 Nov 2010 05:43:20 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 11:52:54 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 64 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-1qeYFktKYLl893TrvOJL47HUlFZ7hL8ztIhOnJsyNnr+kqhCbihqpqnwVT1JWecg9CeKhNdH6bYJiKW!hA/I+xfRG30yS3xk+eMCV3sR68iBuFjwvQ3rJwBycFiydVpLTDkhdsu0rruyzaApWPJDNlqgdfNd!iuUL X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3983 Xref: feeder.eternal-september.org comp.lang.vhdl:4380 On Fri, 12 Nov 2010 09:13:38 +0000, Martin Thompson wrote: >Jan Decaluwe writes: > >> Kevin Thibedeau wrote: ... >>> This was remedied in Ada-95 with the addition of modular types. They >>> are restricted to unsigned integers and *do* have implicit boolean >>> operators. As their name suggests, modular types also wraparound on >>> overflow and underflow without throwing an exception. It would be >>> interesting to consider adding them to a future revision to VHDL for >>> those who want an efficient alternative to the array types. >> >> Fascinating stuff - thanks for this info. >> >> Restricting the bit view to the "unsigned" domain makes a lot >> of sense (talking from my own language design experience). >> >> During a quick survey I found that part of the rationale >> behind modular types was "easier interaction with hardware". >> Interesting, isn't it? >> >> It seems that a lot of the groundwork that would turn VHDL >> into the "easy" HDL is readily available. >> > >Maybe we should just quit VHDL and start synthesising Ada directly >(with only half-a-smiley ;) > >Maybe call it SystemAda :) I believe that would make a lot more sense as a starting point than C or C++. I am playing with Ada, and finding it very nice indeed. Ada-95 and now 2005 add a rational type of object oriented programing, maintaining good type safety even in a complex class hierarchy. If VHDL is to acquire classes, I hope they will be along the same lines. As well as adding the modular types, Ada has fixed point types (you specify range and precision) which could make DSP a breeze. I suspect the original VHDL committee chose about the right subset of Ada as a starting point in the 1980s, but now a larger subset could be useful - fixed point types for example. Since then there has been parallel (usually divergent) evolution, but VHDL-2008 got conditional- (and case?) -expressions before Ada (they are due in Ada-2012). But if we're going down the SystemAda route, we need a synthesisable subset - no heap allocation, limits on recursion, etc. It'll look a lot like the SPARK subset - with which, using annotations in the form of Ada comments - your design can be proved formally correct. There would seem to be a lot of commonality between restructuring logic for formal proof, and restructuring it for synthesis - and certainly there are a lot of similar limitations. If the prover fails to terminate, that probably implies infinite hardware, etc... So, I'm going with SystemSPARK, and using Ada for my testbenches! - Brian From newsfish@newsfish Fri Feb 3 13:08:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 06:38:15 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289572695 29860 127.0.0.1 (12 Nov 2010 14:38:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 14:38:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4381 On Nov 11, 3:33 pm, rickman wrote: > On Nov 8, 12:57 pm, Andy wrote: > > > The VHDL standard has already adopted an assumed two's complement > > numeric representation for vectors (numeric_std, numeric_std_unsigned, > > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > > representation for integes as well?! > > Your statement is not exactly correct. "vectors" are not 2's > complement. numeric_std is 2's complement. SLV is still not > arithmetic at all. That is the difference. I beg to differ. The new numeric_std_unsigned package assigns an arithmetic interpretation to std_logic_vector, just like std_logic_arith did. Also, by using the conversion unsigned(my_slv) you are already implying that the unconverted slv has the same bit representation as unsigned, which is arithmetic. The tool is not allowed to convert/move bits around in that conversion, so the new interpretation is in effect placed on the old slv as well. > > > The primary problem with vhdl vector based arithmetic (numeric_*) is > > that it rolls over (not to signed, but what's the difference, an > > unsigned rollover is still inaccurate). Take two unsigned, add them > > together, and you can get a result that is less than either of the > > operands. > > What you call "inaccurate" is a result of limited range of the > representation. What would you have the implementation do when the > "overflow" occurs? I can see three choices: roll over treating the > limited range as modulo arithmetic (minimum logic), saturate at the > max and min of the range (more logic and still "inaccurate") or just > not perform the operation (also more logic and who knows what > "inaccurate" really means in this case). Both can/should throw an > error if the operation is actually doing arithmetic. But it is often > that a counter is intended to roll over. For those I have to use an > explicit modulo operator. > If I tell the simulator or synthesis tool to add one to a value, the new value better be larger than the old value, by exactly one, or it should die trying (with an informative error message in the case of a simulator). It should not silently assume that something else will be good enough. Same goes for subtraction. If I need it do do something besides adding or subtracting, then I will tell it what I want it to do (either by resize() or mod, etc.) Integer and sfixed/ufixed do this correctly, with the exception of subtracting ufixed values. > > > Or better yet, allow assignment operators to be overloaded so that > > they can do the resizing automatically. > > > Hey, I can dream, can't I? > > I believe overloading operators has been suggested for the next go > around on the VHDL spec. I have no idea if this would create any > problems. > > Rick I think limiting overloaded assignment operators to re-sizing the same type (between the expression and the target) would be pretty safe, but it also would not handle the signed/unsigned issue. But because integer and natural are the same base type, it can also handle signed/ unsigned conversions (with bounds checking). Those are different base types in VHDL. So maybe we limit the actions of overloaded assignment operators to converting "closely related" types and resizing to this relatively safe. If it works out, maybe we can extend overloaded assignments to other areas, but I'd rather take baby steps and not break anything, than take too big a step and cause bigger, unforseen problems. Andy From newsfish@newsfish Fri Feb 3 13:08:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 12 Nov 2010 16:09:06 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> In-Reply-To: <9a9qd617fmqieb034t378lg7d7cjm9mml0@4ax.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 77 Message-ID: <4cdd5892$0$14252$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 84a31462.news.skynet.be X-Trace: 1289574546 news.skynet.be 14252 91.177.142.122:32880 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4382 Brian Drummond wrote: > On Fri, 12 Nov 2010 09:13:38 +0000, Martin Thompson > wrote: > >> Jan Decaluwe writes: >> >>> Kevin Thibedeau wrote: > ... > >>>> This was remedied in Ada-95 with the addition of modular types. They >>>> are restricted to unsigned integers and *do* have implicit boolean >>>> operators. As their name suggests, modular types also wraparound on >>>> overflow and underflow without throwing an exception. It would be >>>> interesting to consider adding them to a future revision to VHDL for >>>> those who want an efficient alternative to the array types. >>> Fascinating stuff - thanks for this info. >>> >>> Restricting the bit view to the "unsigned" domain makes a lot >>> of sense (talking from my own language design experience). >>> >>> During a quick survey I found that part of the rationale >>> behind modular types was "easier interaction with hardware". >>> Interesting, isn't it? >>> >>> It seems that a lot of the groundwork that would turn VHDL >>> into the "easy" HDL is readily available. >>> >> Maybe we should just quit VHDL and start synthesising Ada directly >> (with only half-a-smiley ;) >> >> Maybe call it SystemAda :) > > I believe that would make a lot more sense as a starting point than C or C++. > > I am playing with Ada, and finding it very nice indeed. > > Ada-95 and now 2005 add a rational type of object oriented programing, > maintaining good type safety even in a complex class hierarchy. If VHDL is to > acquire classes, I hope they will be along the same lines. > > As well as adding the modular types, Ada has fixed point types (you specify > range and precision) which could make DSP a breeze. > > I suspect the original VHDL committee chose about the right subset of Ada as a > starting point in the 1980s, but now a larger subset could be useful - fixed > point types for example. > > Since then there has been parallel (usually divergent) evolution, but VHDL-2008 > got conditional- (and case?) -expressions before Ada (they are due in Ada-2012). > > But if we're going down the SystemAda route, we need a synthesisable subset To get started, we would need to define/implement an RTL semantics subset. The language has built-in concurrency support, so no problem there. An RTL-style signal would probably be easy. The remaining problem is a model for sensitivity, and then a simulation engine could be written ... > heap allocation, limits on recursion, etc. It'll look a lot like the SPARK > subset - with which, using annotations in the form of Ada comments - your design > can be proved formally correct. > > There would seem to be a lot of commonality between restructuring logic for > formal proof, and restructuring it for synthesis - and certainly there are a lot > of similar limitations. If the prover fails to terminate, that probably implies > infinite hardware, etc... > > So, I'm going with SystemSPARK, and using Ada for my testbenches! > > - Brian -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!o11g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 07:58:38 -0800 (PST) Organization: http://groups.google.com Lines: 109 Message-ID: <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289577518 26646 127.0.0.1 (12 Nov 2010 15:58:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 15:58:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000prf.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4383 On Nov 12, 9:38=A0am, Andy wrote: > On Nov 11, 3:33 pm, rickman wrote: > > > On Nov 8, 12:57 pm, Andy wrote: > > > > The VHDL standard has already adopted an assumed two's complement > > > numeric representation for vectors (numeric_std, numeric_std_unsigned= , > > > ufixed/sfixed, etc.) Why can we not adopt an assumed two's complement > > > representation for integes as well?! > > > Your statement is not exactly correct. =A0"vectors" are not 2's > > complement. =A0numeric_std is 2's complement. =A0SLV is still not > > arithmetic at all. =A0That is the difference. > > I beg to differ. The new numeric_std_unsigned package assigns an > arithmetic interpretation to std_logic_vector, just like > std_logic_arith did. > > Also, by using the conversion unsigned(my_slv) you are already > implying that the unconverted slv has the same bit representation as > unsigned, which is arithmetic. The tool is not allowed to convert/move > bits around in that conversion, so the new interpretation is in effect > placed on the old slv as well. Yes, if the designer wants to consider SLV as a 2's complement vector, there is nothing in the language to prevent that. But there is nothing in the language to promote it either. Anyone is free to create their own libraries or to use standard ones to add capabilities to the language. That is what is going on in both numeric_std_unsigned and in numeric_std. The utility of these data types is being extended as the designer wishes. It is not a default part of the language. > > > The primary problem with vhdl vector based arithmetic (numeric_*) is > > > that it rolls over (not to signed, but what's the difference, an > > > unsigned rollover is still inaccurate). Take two unsigned, add them > > > together, and you can get a result that is less than either of the > > > operands. > > > What you call "inaccurate" is a result of limited range of the > > representation. =A0What would you have the implementation do when the > > "overflow" occurs? =A0I can see three choices: roll over treating the > > limited range as modulo arithmetic (minimum logic), saturate at the > > max and min of the range (more logic and still "inaccurate") or just > > not perform the operation (also more logic and who knows what > > "inaccurate" really means in this case). =A0Both can/should throw an > > error if the operation is actually doing arithmetic. =A0But it is often > > that a counter is intended to roll over. =A0For those I have to use an > > explicit modulo operator. > > If I tell the simulator or synthesis tool to add one to a value, the > new value better be larger than the old value, by exactly one, or it > should die trying (with an informative error message in the case of a > simulator). It should not silently assume that something else will be > good enough. Same goes for subtraction. If I need it do do something > besides adding or subtracting, then I will tell it what I want it to > do (either by resize() or mod, etc.) > > Integer and sfixed/ufixed do this correctly, with the exception of > subtracting ufixed values. How do you expect a synthesis tool to handle this requirement? If you write VHDL code to increment a counter, what do you expect the hardware to do when the counter reaches the max value? Are you saying you expect the synthesis tool to throw an error if the designer does not indicate explicitly what will happen with an IF statement or a MOD operator? What does the synthesis tool do with integers in the case of a counter that can overflow? signal a : integer range 0 to 15; -- clocked process wrapper... a <=3D a + 1; What hardware should this produce? Or how should I write this for a 4 bit counter? How exactly should the synthesis tool "die trying"? > > > Or better yet, allow assignment operators to be overloaded so that > > > they can do the resizing automatically. > > > > Hey, I can dream, can't I? > > > I believe overloading operators has been suggested for the next go > > around on the VHDL spec. =A0I have no idea if this would create any > > problems. > > > Rick > > I think limiting overloaded assignment operators to re-sizing the same > type (between the expression and the target) would be pretty safe, but > it also would not handle the signed/unsigned issue. But because > integer and natural are the same base type, it can also handle signed/ > unsigned conversions (with bounds checking). Those are different base > types in VHDL. > > So maybe we limit the actions of overloaded assignment operators to > converting "closely related" types and resizing to this relatively > safe. If it works out, maybe we can extend overloaded assignments to > other areas, but I'd rather take baby steps and not break anything, > than take too big a step and cause bigger, unforseen problems. I have no idea what is safe and what is not. But us talking about it won't solve anything. Rick From newsfish@newsfish Fri Feb 3 13:08:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!n32g2000prc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 11:46:16 -0800 (PST) Organization: http://groups.google.com Lines: 70 Message-ID: <55049319-4709-4af5-8987-17194ca0de88@n32g2000prc.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289591177 4349 127.0.0.1 (12 Nov 2010 19:46:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 19:46:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000prc.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4384 On Nov 12, 9:58=A0am, rickman wrote: > Yes, if the designer wants to consider SLV as a 2's complement vector, > there is nothing in the language to prevent that. =A0But there is > nothing in the language to promote it either. =A0Anyone is free to > create their own libraries or to use standard ones to add capabilities > to the language. =A0That is what is going on in both > numeric_std_unsigned and in numeric_std. =A0The utility of these data > types is being extended as the designer wishes. =A0It is not a default > part of the language. > The standard ("default part of the") language now includes the packages. And by allowing the unsigned(my_slv) conversion, which does not include any reforming of the elements within my_slv, and my_slv =3D 10 (via numeric_std_unsigned), the language is ensuring that the numeric interpretation is extended to slv. Whether you choose to access that interpretation or not, the representation must be consistent with the numeric interpretation. > How do you expect a synthesis tool to handle this requirement? =A0If you > write VHDL code to increment a counter, what do you expect the > hardware to do when the counter reaches the max value? =A0Are you saying > you expect the synthesis tool to throw an error if the designer does > not indicate explicitly what will happen with an IF statement or a MOD > operator? > > What does the synthesis tool do with integers in the case of a counter > that can overflow? > > signal a : integer range 0 to 15; > -- clocked process wrapper... > =A0 a <=3D a + 1; > > What hardware should this produce? =A0Or how should I write this for a 4 > bit counter? =A0How exactly should the synthesis tool "die trying"? Your description did not legally tell the synthesis tool what to do when a is 15, since storing the result of 15 + 1 in a would be illegal (and in fact impossible in a four bit storage register). Therefore, the synthesis tool is free to do anything it wants in that case. So, one way to look at what really happens in synthesis is this: signal a : integer range 0 to 15; -- clocked process wrapper... if a + 1 > 15 then -- implied by the range of a a <=3D "don't care"; -- because assigning 16 to a is illegal anyway else a <=3D a + 1; end if; Lucky for us, it turns out that the most efficient implementation of the above is to simply truncate the result of 15 + 1, which is a roll over, or modulo counter. I would prefer that it at least give me a warning that it was doing this, but in reality, it could do anything it wants, because I did not tell it what to do. To keep simulation and synthesis on the same page, a better way to write it in the first place would be: signal a : integer range 0 to 15; -- clocked process wrapper... a <=3D (a + 1) mod 16; This way, you are explicitly, legally telling the synthesis tool (and the simulator) what you want to do when a is 15. Andy From newsfish@newsfish Fri Feb 3 13:08:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!y2g2000prf.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: VHDL Feature Suggestions Date: Fri, 12 Nov 2010 11:54:58 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <80085633-1739-4b6a-8230-1127083cbbb8@y2g2000prf.googlegroups.com> References: <9a6ddc89-bf85-4988-a3f7-ffdb026de5bc@r21g2000pri.googlegroups.com> NNTP-Posting-Host: 66.80.67.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289591698 9410 127.0.0.1 (12 Nov 2010 19:54:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 12 Nov 2010 19:54:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y2g2000prf.googlegroups.com; posting-host=66.80.67.189; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4385 Jonathan, Now once you have written about what you want, if you would like to make an official feature request to the VHDL working group, you can submit an enhancement request at: http://www.eda.org/vasg/ Look on the left hand side of the page for enhancement & bug request Best, Jim From newsfish@newsfish Fri Feb 3 13:08:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news.musoftware.de!wum.musoftware.de!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 12 Nov 2010 17:10:43 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 23:11:13 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 23 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-fmKNFvR8DJUFEeEqqDTTqqPUkxKHtq4SoX1EZmXkySBjo2dl2nhr/GWkFqhcWJDwLA09OM6xFyhfbLW!wuLYvdHYHNlD2SDUBi4i5iPq3520PqWYKE1SfvY2/B810Xr0qWa78gkcXKop12Jmrl6z0jQrt8cM!a16z X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2549 Xref: feeder.eternal-september.org comp.lang.vhdl:4386 On Fri, 12 Nov 2010 06:38:15 -0800 (PST), Andy wrote: >On Nov 11, 3:33 pm, rickman wrote: >> On Nov 8, 12:57 pm, Andy wrote: >So maybe we limit the actions of overloaded assignment operators to >converting "closely related" types and resizing to this relatively >safe. If it works out, maybe we can extend overloaded assignments to >other areas, but I'd rather take baby steps and not break anything, >than take too big a step and cause bigger, unforseen problems. Before you go too far with overloaded assignment operators, you have to face another issue : assignment is not an operator! And changing that in VHDL would probably be difficult (for a mild understatement). For better or worse, it's a 50-year old design decision in, clearly not just VHDL, but back through Ada, and right back to Algol-60. I don't see it happening. - Brian From newsfish@newsfish Fri Feb 3 13:08:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!i32g2000pri.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 17:39:54 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <9f0c07cc-1717-489c-9f94-bd4558a74ce1@i32g2000pri.googlegroups.com> References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289612394 2322 127.0.0.1 (13 Nov 2010 01:39:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 01:39:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i32g2000pri.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4387 On Nov 12, 6:11=A0pm, Brian Drummond wrote: > > Before you go too far with overloaded assignment operators, > you have to face another issue : > > assignment is not an operator! > > And changing that in VHDL would probably be difficult (for a mild > understatement). For better or worse, it's a 50-year old design decision = in, > clearly not just VHDL, but back through Ada, and right back to Algol-60. > > I don't see it happening. > Rather than overloading the assignment operator, my suggestion to the (*1) VHDL pubas (two years ago) is to add a method to allow a function to get access to the attributes associated with whatever the result of the function will be assigned to. Adds to the language without breaking anything existing and accomplishes the same goal. Kevin Jennings (*1) bug #240 https://bugzilla.mentor.com/show_bug.cgi?id=3D240 From newsfish@newsfish Fri Feb 3 13:08:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n10g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Fri, 12 Nov 2010 18:35:06 -0800 (PST) Organization: http://groups.google.com Lines: 84 Message-ID: <0bc6ee0b-cca8-4c42-8883-dc924de813f9@n10g2000prj.googlegroups.com> References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <697ddd4a-527f-45f1-a8a6-7dcf5c1440be@o11g2000prf.googlegroups.com> <55049319-4709-4af5-8987-17194ca0de88@n32g2000prc.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289615706 2554 127.0.0.1 (13 Nov 2010 02:35:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 02:35:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000prj.googlegroups.com; posting-host=71.176.145.26; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4388 On Nov 12, 2:46 pm, Andy wrote: > On Nov 12, 9:58 am, rickman wrote: > > > Yes, if the designer wants to consider SLV as a 2's complement vector, > > there is nothing in the language to prevent that. But there is > > nothing in the language to promote it either. Anyone is free to > > create their own libraries or to use standard ones to add capabilities > > to the language. That is what is going on in both > > numeric_std_unsigned and in numeric_std. The utility of these data > > types is being extended as the designer wishes. It is not a default > > part of the language. > > The standard ("default part of the") language now includes the > packages. And by allowing the unsigned(my_slv) conversion, which does > not include any reforming of the elements within my_slv, and my_slv = > 10 (via numeric_std_unsigned), the language is ensuring that the > numeric interpretation is extended to slv. Whether you choose to > access that interpretation or not, the representation must be > consistent with the numeric interpretation. > > > > > How do you expect a synthesis tool to handle this requirement? If you > > write VHDL code to increment a counter, what do you expect the > > hardware to do when the counter reaches the max value? Are you saying > > you expect the synthesis tool to throw an error if the designer does > > not indicate explicitly what will happen with an IF statement or a MOD > > operator? > > > What does the synthesis tool do with integers in the case of a counter > > that can overflow? > > > signal a : integer range 0 to 15; > > -- clocked process wrapper... > > a <= a + 1; > > > What hardware should this produce? Or how should I write this for a 4 > > bit counter? How exactly should the synthesis tool "die trying"? > > Your description did not legally tell the synthesis tool what to do > when a is 15, since storing the result of 15 + 1 in a would be illegal > (and in fact impossible in a four bit storage register). Therefore, > the synthesis tool is free to do anything it wants in that case. > > So, one way to look at what really happens in synthesis is this: > > signal a : integer range 0 to 15; > -- clocked process wrapper... > if a + 1 > 15 then -- implied by the range of a > a <= "don't care"; -- because assigning 16 to a is illegal anyway > else > a <= a + 1; > end if; > > Lucky for us, it turns out that the most efficient implementation of > the above is to simply truncate the result of 15 + 1, which is a roll > over, or modulo counter. > > I would prefer that it at least give me a warning that it was doing > this, but in reality, it could do anything it wants, because I did not > tell it what to do. > > To keep simulation and synthesis on the same page, a better way to > write it in the first place would be: > > signal a : integer range 0 to 15; > -- clocked process wrapper... > a <= (a + 1) mod 16; > > This way, you are explicitly, legally telling the synthesis tool (and > the simulator) what you want to do when a is 15. > > Andy As it turns out, that is exactly what I do because the simulation doesn't work without it. It also solves your synthesis problem. There are any number of things that a synthesis tool assumes if you don't tell it. They think they are doing you a favor. But then these are the same sorts of things that people complain about when using VHDL. That is what VHDL is all about, telling the tools exactly what you want rather than using default. Rick From newsfish@newsfish Fri Feb 3 13:08:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!feeder.news-service.com!xlned.com!feeder5.xlned.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 13 Nov 2010 09:02:08 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20100411) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 References: <4cd3cc7a$0$14248$ba620e4c@news.skynet.be> <4cd41017$0$14253$ba620e4c@news.skynet.be> <72d100fc-9f58-4bba-a703-7cd03cea4e29@f8g2000yqn.googlegroups.com> <4cd43391$0$14248$ba620e4c@news.skynet.be> <200da958-8f62-4918-9af2-447ef1b22709@u11g2000prn.googlegroups.com> <462b3d59-2569-4628-9dfc-46b16b32f25d@o23g2000prh.googlegroups.com> <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> In-Reply-To: <70ird6dmu8f19mg74sce0ecgvgkioq21cd@4ax.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 42 Message-ID: <4cde4600$0$14250$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 490d6e16.news.skynet.be X-Trace: 1289635328 news.skynet.be 14250 91.177.142.122:38598 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4389 Brian Drummond wrote: > On Fri, 12 Nov 2010 06:38:15 -0800 (PST), Andy wrote: > >> On Nov 11, 3:33 pm, rickman wrote: >>> On Nov 8, 12:57 pm, Andy wrote: > >> So maybe we limit the actions of overloaded assignment operators to >> converting "closely related" types and resizing to this relatively >> safe. If it works out, maybe we can extend overloaded assignments to >> other areas, but I'd rather take baby steps and not break anything, >> than take too big a step and cause bigger, unforseen problems. > > Before you go too far with overloaded assignment operators, > you have to face another issue : > > assignment is not an operator! > > And changing that in VHDL would probably be difficult (for a mild > understatement). For better or worse, it's a 50-year old design decision in, > clearly not just VHDL, but back through Ada, and right back to Algol-60. > > I don't see it happening. Moreover, these proposals invariably seem to be inspired by types that force us to deal with the representation to get arithmetic right. For some reason, we seem to think that we are better at that than synthesis tools. The opposite is true of course. For integer arithmetic, a more usable integer type would address the issues in a much better way. I don't know about fixed point, but probably the Ada example can be enlightening. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:08:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j33g2000vbb.googlegroups.com!not-for-mail From: "Niv (KP)" Newsgroups: comp.lang.vhdl Subject: Custom views in ModelSim Date: Sat, 13 Nov 2010 03:51:40 -0800 (PST) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 81.110.164.109 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289649100 1378 127.0.0.1 (13 Nov 2010 11:51:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Nov 2010 11:51:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j33g2000vbb.googlegroups.com; posting-host=81.110.164.109; posting-account=gstOigoAAADV9pmzZL58qQ436SKV3SBu User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4390 I've read somewhere that custom data views can be built using Tcl to view data selected in the wave window in a different format. E.g. display a clock as hrs, mins & secs as a digital clock type display. Can anyone point me to where I can find outhow todo this please? From newsfish@newsfish Fri Feb 3 13:08:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Custom views in ModelSim Date: Sat, 13 Nov 2010 17:30:13 +0000 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6153"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IOUMBnOU7V/HSP1cxCyGZR71hvA8EjRA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:a5qUjorhlWKKb/TxORSqV+RvNjk= Xref: feeder.eternal-september.org comp.lang.vhdl:4391 On Sat, 13 Nov 2010 03:51:40 -0800 (PST), "Niv (KP)" wrote: >I've read somewhere that custom data views can be built using Tcl to >view data selected in the wave window in a different format. >E.g. display a clock as hrs, mins & secs as a digital clock type >display. >Can anyone point me to where I can find outhow todo this please? You could start with http://www.doulos.com/knowhow/tcltk/examples/constellation/ However, it's not been updated since I wrote it quite a while ago, so it's entirely possible that the bits have rotted a little, in the way that they do when tool vendors make major revisions of their GUIs. Must try it myself, just to see if it still works :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:08:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p7g2000prb.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.lang.vhdl Subject: Re: Programmable Logic at StackExchange Date: Sun, 14 Nov 2010 15:03:00 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1289775780 31437 127.0.0.1 (14 Nov 2010 23:03:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Nov 2010 23:03:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p7g2000prb.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4392 On Nov 11, 11:43 pm, Jonathan Ross wrote: > Someone recently added a Programmable Logic Stack on Stack Exchange, That was me. I'm glad it's getting a bit more attention, so it can become a live site eventually. A couple of months ago I made a pitch to comp.arch.fpga (which I follow regularly): http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/e4526299628848b7/ I explain there why I think the SE framework, even if imperfect, is the best option for a vendor-agnostic, "owner-less" (sort of) community support site. My post to CAF stopped short of what the SE "Area51" is, so I'll mention it here. The proposal needs at least 60 followers and 5 on- and off-topic questions, each. To count, each of those 10 questions needs to have at least 20 on- or off-topic votes (and 4 times as many on/off-topic as off/on-topic votes). Practically this means that many more than 60 followers are needed. If you choose to support this proposal, then please register, click "follow" on the proposal page, and then vote on the questions. Also, feel free to suggest your own questions. When these conditions are met, the proposal graduates to the "commitment" stage, where people are expected to commit to participate in the discussion of the would-be SE site. With enough committers (with sufficient accumulated SE "karma") the site goes "beta" for a while, and then becomes an "official" SE site if there is enough activity. cheers, saar. http://www.saardrimer.com From newsfish@newsfish Fri Feb 3 13:08:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!t35g2000yqj.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?= Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: XST - configuration - VHDL Date: Mon, 15 Nov 2010 06:38:21 -0800 (PST) Organization: http://groups.google.com Lines: 160 Message-ID: References: <0d61ad47-fd44-4171-bdf5-d0c65520119c@fh19g2000vbb.googlegroups.com> <57111d11-2b30-4806-bc1d-2f3d409b0cc6@v20g2000yqb.googlegroups.com> <2b0654d8-ade1-4d10-a4f5-b864964ea1ad@x4g2000pre.googlegroups.com> NNTP-Posting-Host: 194.25.252.189 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1289831901 31893 127.0.0.1 (15 Nov 2010 14:38:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Nov 2010 14:38:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000yqj.googlegroups.com; posting-host=194.25.252.189; posting-account=LGrEZwgAAABRklkiVht6PcemOxu89csI User-Agent: G2/1.0 X-HTTP-Via: 1.1 S04921 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13205 comp.lang.vhdl:4393 On 11 Nov., 18:03, Andy wrote: > On Nov 10, 12:54=A0pm, Jaime Andr=E9s Aranguren Cardona > > > > > > wrote: > > On 10 Nov., 19:50, Jaime Andr=E9s Aranguren Cardona > > > wrote: > > > On 10 Nov., 19:16, Andy wrote: > > > > > On Nov 10, 10:53=A0am, Jaime Andr=E9s Aranguren Cardona > > > > > wrote: > > > > > Dear all, > > > > > > In my current project I have an entity for which I which arhitect= ure > > > > > to use on a VHDL file where I instantiate the entity, like follow= ing > > > > > configuration code: > > > > > > -- Embedded configuration > > > > > -- Select control architecture to use > > > > > for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > > > > Within the VHDL file where Ctrl2D is defined, I have different > > > > > configurations, namely rtl_tiny and rtl_small. Within each of tho= se, > > > > > are processes which have variables whose length depend on some > > > > > constants (KA, KB), like: > > > > > > process_out : process (in_a, in_b) > > > > > =A0 =A0 variable var : std_logic_vector (KA-KB-1 downto 0) =A0:= =3D (others =3D> > > > > > '0'); > > > > > =A0 begin > > > > > > I should select which architecture to use in the configuration > > > > > (rtl_tiny or rtl_small) depending on a given a given set of value= s KA > > > > > and KB. For a set of values KA and KB that works fine with rtl_sm= all > > > > > and having rtl_small selected in the configuration, XST, when par= sing, > > > > > gives me warnign and error messages: > > > > > > Entity compiled. > > > > > WARNING:HDLParsers:3350 - "D:/Projects/Ctrl2D.vhd" Line 157. Null > > > > > range: -33 downto 0 > > > > > ERROR:HDLParsers:804 - "D:/Projects/Ctrl2D.vhd" Line 214. Size of > > > > > concat operation is different than size of the target. > > > > > Entity (Architecture ) compiled. > > > > > > But those lines (157 and 214) are within the architecture rtl_tin= y, > > > > > not rtl_small. > > > > > > I was confident that by selecting the right architecture in the > > > > > configuration I was completely bypassing everything related to no= n- > > > > > desired architectures, but it seems like I was wrong. > > > > > > How can I direct XST to ignore the code of the non-interesting > > > > > architectures, and parse and synthesize only the one that I selec= ted > > > > > in the configuration? > > > > > > Thanks a lot in advance, > > > > > > JaaC > > > > > Unlike simulation tools, synthesis tools combine the analysis and > > > > elaboration phases into one. This is probably leading to your probl= em. > > > > Leaving something out in a configuration is not quite like > > > > conditionally compiling it. Everything gets analyzed (if it is in a > > > > file that is being analyzed), whether it is chosen at elaboration o= r > > > > not. Some simulators have options for compiling (analyzing) only > > > > certain types of units (packages, package bodies, entities, > > > > architectures, etc.) and ignoring others in the same file. I have n= ot > > > > seen that in a synthesis tool. > > > > > Other than fixing the problem with the mismatched size (if even > > > > possible), I would suggest moving the two architectures into separa= te > > > > files, and only including the appropriate file in the project. > > > > > Andy > > > > Hi Andy, > > > > Thanks for your reply, I found the solution however: adding pragmas: > > > > architecture struct of Stack2D is > > > > =A0 signal dat_2ext : buf2dwrd; > > > =A0 signal rd_2ext =A0: std_logic; > > > =A0 signal dat_2slv : buf2dwrd; > > > =A0 signal wr_2slv =A0: std_logic; > > > > =A0 -- pragma synthesis on > > > =A0 for all : Ctrl2D use entity work.Ctrl2D(rtl_small); > > > =A0 -- pragma synthesis off > > > > begin > > > > The commented pragmas did the job. > > > > Regards. > > > Dear all, > > > By the way, is there a way to make a conditional selection of > > architecture to use, something in the lines of: > > > for all : Ctrl2D if A =3D 0 use entity work.Ctrl2D(architecture_a) =A0e= lse > > use entity work.Ctrl2D(architecture_b); =A0 ??? > > > Or is there an alternative approach? > > > Thanks lot in advance. > > > JaaC- Hide quoted text - > > > - Show quoted text - > > The only way to do that is with an if-generate on the instantiation, > not the configuration. > > In fact, since the '93 standard, you can directly instantiate an > entity and its architecture: > > if a =3D 0 generate > u1: entity work.entity_name(architecture_name)... > end generate; > > if a /=3D 0 generate > u1: entity work.entity_name(alternative_architecture_name) ... > end generate; > > You don't even need to mess with a configuration! > > Andy- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - Dear all, Thanks for the feedback. Andy's suggestion seems to be very in the direction I was heading for, thanks a lot. Kindest regards, JaaC From newsfish@newsfish Fri Feb 3 13:08:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Colin Paul Gloster Newsgroups: comp.lang.vhdl Subject: Re: boolean operations on "integer" in VHDL'93 Date: Tue, 16 Nov 2010 19:40:19 +0000 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <6b66d6dkhelejkkbkss3j3ji0kpk53tkch@4ax.com> <16f11021-0b2b-4340-8cfb-a03fd936ac84@k3g2000vbp.googlegroups.com> <4cdc0343$0$14262$ba620e4c@news.skynet.be> Reply-To: Colin Paul Gloster Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="17925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/5HFR0CTXNQaC/YSJTuF13ugUuUGp0CGnnovCiznWCqQ==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: Cancel-Lock: sha1:CHQijTAIES3gP3tSH0S6oW3t+9o= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4394 Martin Thompson sent on November 12th, 2010: |------------------------------------------------------------------| |"[..] | | | |Maybe we should just quit VHDL and start synthesising Ada directly| |[..]" | |------------------------------------------------------------------| People have claimed to have synthesized Ada to hardware. |--------------------------------------------------------------------| |"Maybe call it SystemAda :)" | |--------------------------------------------------------------------| There was an article by Zainalabedin Navabi and others in "Ada Letters" entitled "System level hardware design and simulation with SystemAda" in 2009. It seems to me that they were trying to get an easy publication instead of doing real work. They and the editor showed unknowingly in the article that they did not know what they were discussing. Yours sincerely, Paul Colin Gloster From newsfish@newsfish Fri Feb 3 13:08:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Pin numbers assignment From: Merciadri Luca Organization: ULg Date: Thu, 18 Nov 2010 13:03:49 +0100 Message-ID: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:Y5T6bAKTRT14UDSo0+JcEx2XAro= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 39 NNTP-Posting-Host: 139.165.242.29 X-Trace: news.sunsite.dk DXC=lH]Co=P`_:8jd^7_dR6Ih5YSB=nbEKnk;OoZn^kHoPe8ZEVG41K_]RP;@H2o>Ff7K8NJeTc1TN6Wl7j iEYEARECAAYFAkzlFiUACgkQM0LLzLt8MhzkfgCfZvxK09E4kSF2TmtZJ4OG/Vjc LmEAn1/BfmjFjae2oE7UIqZPLmctfG/e =4xSL -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Buzzer From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 00:18:12 +0100 Message-ID: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:DYVI5S8C5xUzMB35B8ohvuvERUQ= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 37 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=oH8D2k\VJUX5dE91CT5^XYYSB=nbEKnk[=Wf0P_7c\ZVZEVG4QK_]RP;@H2o^O>`Ol[NBH>TX0\Po9^jJaQdkh3GE4Wn]Q X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4397 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I've got a buzzer which is basically an output of my entity. Say this is buzzer BUZ: out std_logic. Then, I want to put BUZ to 1 for just some very small amount of time. I then tried == BUZ <= '1'; BUZ <= '0' after 500 ns; == but it is apparently not appreciated from my compiler's point of view, which complains about tristate problems, etc. Is there a simple solution to it? Thanks. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- If you want to judge a man's character, give him power. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzltDQACgkQM0LLzLt8Mhxw0wCgpniL+PeT7FMkbEXnSHQmMhiQ jVEAnRS31MQHeCe++BSxwGBPZ1/CRTUB =fMgN -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!c39g2000yqi.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment Date: Thu, 18 Nov 2010 19:18:33 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <8a05ab91-79aa-45dc-ac19-e1529340296b@c39g2000yqi.googlegroups.com> References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290136713 21003 127.0.0.1 (19 Nov 2010 03:18:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 03:18:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c39g2000yqi.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4398 On Nov 18, 7:03=A0am, Merciadri Luca wrote: > attribute pin_numbers of sorter: entity is > "CLK:1 BTN_on:2 LED_size:14"; > However, ispLEVER gives me `Reference to unknown attribute definition > pin_numbers'. What am I doing wrong? > Before you can use an attribute, first you must define what that attribute is in the first place. The attribute 'pin_numbers' is not a pre-defined VHDL language attribute, it is a user defined attribute...so you as the user need to define it. In your case, the following statement is needed prior to your use of the attribute statement that you have above. attribute pin_numbers: STRING; It is also likely that there is some Lattice specific library that has this attribute definition included that you could get access to with a 'use' statement. use work.xxx.all; -- Where xxx is the name of the Lattice lib Lastly, although you may have no intention of ever porting your design to any other device, it is generally not a good idea to embed pin definitions in the source code. If you DO end up moving to a different device (maybe from QFP to BGA as an example, or a bigger part) then those pin definitions in the source code are useless...and in the way now because they are in the source code. Using attributes is also tool dependent (if you move the code from say Lattice to Altera, Xilinx, etc.) and the tools that you use will usually give you an easier way to enter the pin info. Since you will need to archive the synthesis tool files anyway there is no reason that the pin number information can't be kept there also. You will likely have other constraints archived there such as timing constraints so there is no reason why pin number constraints can't be there also. Think of it this way, the VHDL you write is intended to define a logic description. A logic description does not inherently require any specific technology implementation. So any design constraints that are dependent on the underlying technology should generally be stored with whatever tool it is that allows one to implement the logic description in that technology. Use that as your criteria for deciding whether or not to define a constraint in the VHDL source code or elsewhere. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:08:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Buzzer Date: Thu, 18 Nov 2010 19:27:24 -0800 (PST) Organization: http://groups.google.com Lines: 62 Message-ID: References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290137245 17539 127.0.0.1 (19 Nov 2010 03:27:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 03:27:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4399 On Nov 18, 6:18=A0pm, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I've got a buzzer which is basically an output of my entity. Say this > is buzzer BUZ: out std_logic. > > Then, I want to put BUZ to 1 for just some very small amount of > time. I then tried > > =3D=3D > BUZ <=3D '1'; > BUZ <=3D '0' after 500 ns; > =3D=3D > > but it is apparently not appreciated from my compiler's point of view, > which complains about tristate problems, etc. > If you're simply trying to simulate this (but I don't think you are), then the solution is to put the statements into a process process(BUZ) begin BUZ <=3D '1' after 1 ns; -- Must want it to be there for *some* time BUZ <=3D '0' after 500 ns; end process; But since you say the complaint is about tristate problems, then I suspect the complaining compiler is a sysnthesis tool which means that you have a few problems: 1. You can't have more than one process or more than one concurrent statement driving any signal (almost without exception). 2. The main exception is I/O pins of the device which generally have tristate control. But you haven't specified any tri-state control. 3. 'after xxx ns' is not synthesizable in today's typical logic devices since those devinces don't have delay lines. This may change in the future, but as of now, there are no delay lines so there is no way to synthesize 'after 500 ns' so it will be ignored. Kevin Jennings > Is there a simple solution to it? > > Thanks. > > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > If you want to judge a man's character, give him power. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzltDQACgkQM0LLzLt8Mhxw0wCgpniL+PeT7FMkbEXnSHQmMhiQ > jVEAnRS31MQHeCe++BSxwGBPZ1/CRTUB > =3DfMgN > -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!news.glorb.com!news2.glorb.com!postnews.google.com!f9g2000vbf.googlegroups.com!not-for-mail From: dgreig Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment Date: Fri, 19 Nov 2010 01:32:50 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> NNTP-Posting-Host: 84.19.254.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290159171 22482 127.0.0.1 (19 Nov 2010 09:32:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 09:32:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f9g2000vbf.googlegroups.com; posting-host=84.19.254.82; posting-account=jWYCGAoAAACtdbpYfrlZ1GVzvYP1FIDc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4401 On Nov 18, 1:03=A0pm, Merciadri Luca wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Hi, > > I'm using an entity `sorter', that I define using > > =3D=3D > entity sorter is > port( > =A0 =A0 =A0 =A0 CLK: in std_logic; > =A0 =A0 =A0 =A0 BTN_on: in std_logic; > =A0 =A0 =A0 =A0 LED_size: out std_logic; > ); > > attribute pin_numbers of sorter: entity is > "CLK:1 BTN_on:2 LED_size:14"; > > end sorter; > =3D=3D > > However, ispLEVER gives me `Reference to unknown attribute definition > pin_numbers'. What am I doing wrong? > > Thanks. > - -- > Merciadri Luca > Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/ > - -- > > If you fake it, you can't make it. > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.9 (GNU/Linux) > Comment: Processed by Mailcrypt 3.5.8 > > iEYEARECAAYFAkzlFiUACgkQM0LLzLt8MhzkfgCfZvxK09E4kSF2TmtZJ4OG/Vjc > LmEAn1/BfmjFjae2oE7UIqZPLmctfG/e > =3D4xSL > -----END PGP SIGNATURE----- Try the predefined '93 "chip_pin". The synthesis tool may or may not support it however. I hate to admit knowing this one.. DG From newsfish@newsfish Fri Feb 3 13:08:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i17g2000vbq.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Delaying signal assignment Date: Fri, 19 Nov 2010 02:38:36 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290163116 21814 127.0.0.1 (19 Nov 2010 10:38:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 10:38:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i17g2000vbq.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4402 How can I delay a signal in the following manner ? signal clk : std_logic; signal sig : std_logic; process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; Now I want "sig" to be High for 50us, after that it should be assigned the value of clk. The following approach does not work: sig <= '1', clk after 50 us; Cheers, hssig From newsfish@newsfish Fri Feb 3 13:08:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Buzzer Date: Fri, 19 Nov 2010 07:12:55 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <501b7dfe-6682-42bd-aa19-f365e130e325@j25g2000yqa.googlegroups.com> References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290179575 2760 127.0.0.1 (19 Nov 2010 15:12:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:12:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4403 To be more specific on #3, you will need a clock signal, and a circuit that counts out the number of clock cycles needed to keep the signal on. You will need much longer than 500 ns for a human to hear a buzzer. Try something on the order of 100 ms or more. Andy From newsfish@newsfish Fri Feb 3 13:08:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Fri, 19 Nov 2010 07:25:49 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290180349 20597 127.0.0.1 (19 Nov 2010 15:25:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:25:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4404 On Nov 19, 4:38=A0am, hssig wrote: > How can I delay a signal in the following manner ? > > signal clk : std_logic; > signal sig : std_logic; > > process > begin > =A0 =A0clk <=3D '1'; wait for 10 ns; > =A0 =A0clk <=3D '0'; wait for 10 ns; > end process; > > Now I want "sig" to be High for 50us, after that it should be assigned > the value of clk. > > The following approach does not work: > sig <=3D '1', clk after 50 us; > > Cheers, hssig signal enable : boolean :=3D false; signal clk : std_logic :=3D '0'; signal sig : std_logic :=3D '1'; enable <=3D true after 50 us; clk <=3D not clk after 10 ns; sig <=3D clk when enable, else '1'; Andy From newsfish@newsfish Fri Feb 3 13:08:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!d8g2000yqf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Fri, 19 Nov 2010 07:54:05 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <176dcd2e-05ce-4ec9-97ff-44968eabf5b9@d8g2000yqf.googlegroups.com> References: NNTP-Posting-Host: 69.255.126.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290182045 24198 127.0.0.1 (19 Nov 2010 15:54:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 19 Nov 2010 15:54:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d8g2000yqf.googlegroups.com; posting-host=69.255.126.158; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4405 On Nov 19, 5:38=A0am, hssig wrote: > How can I delay a signal in the following manner ? > > signal clk : std_logic; > signal sig : std_logic; > > process > begin > =A0 =A0clk <=3D '1'; wait for 10 ns; > =A0 =A0clk <=3D '0'; wait for 10 ns; > end process; > > Now I want "sig" to be High for 50us, after that it should be assigned > the value of clk. > > The following approach does not work: > sig <=3D '1', clk after 50 us; > > Cheers, hssig 50us <=3D '1', '0' after 50 us; sig <=3D clk or 50us; Isn't that easy? Don't make things too hard by thinking about them too much... Rick From newsfish@newsfish Fri Feb 3 13:08:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nuzba.szn.dk!news.szn.dk!pnx.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Pin numbers assignment References: <87r5ei96u2.fsf@merciadriluca-eee.MERCIADRILUCA> <8a05ab91-79aa-45dc-ac19-e1529340296b@c39g2000yqi.googlegroups.com> From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 20:08:15 +0100 Message-ID: <87hbfdp1wg.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:+nQWbe8PixkZNsd5j/SkznDO3/A= MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Lines: 69 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=PETUXC[NbcGB^D;0lZCOUDYSB=nbEKnkK3LlDMZ4XbVIZEVG4AK_]RP;@H2oNO>`Ol[NBH>DVH8HSaRLafM]ES=S;40D?B X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4406 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 KJ writes: > On Nov 18, 7:03 am, Merciadri Luca > wrote: > >> attribute pin_numbers of sorter: entity is >> "CLK:1 BTN_on:2 LED_size:14"; > >> However, ispLEVER gives me `Reference to unknown attribute definition >> pin_numbers'. What am I doing wrong? >> > > Before you can use an attribute, first you must define what that > attribute is in the first place. The attribute 'pin_numbers' is not a > pre-defined VHDL language attribute, it is a user defined > attribute...so you as the user need to define it. In your case, the > following statement is needed prior to your use of the attribute > statement that you have above. > > attribute pin_numbers: STRING; > > It is also likely that there is some Lattice specific library that has > this attribute definition included that you could get access to with a > 'use' statement. > > use work.xxx.all; -- Where xxx is the name of the Lattice lib > > Lastly, although you may have no intention of ever porting your design > to any other device, it is generally not a good idea to embed pin > definitions in the source code. If you DO end up moving to a > different device (maybe from QFP to BGA as an example, or a bigger > part) then those pin definitions in the source code are useless...and > in the way now because they are in the source code. Using attributes > is also tool dependent (if you move the code from say Lattice to > Altera, Xilinx, etc.) and the tools that you use will usually give you > an easier way to enter the pin info. Since you will need to archive > the synthesis tool files anyway there is no reason that the pin number > information can't be kept there also. You will likely have other > constraints archived there such as timing constraints so there is no > reason why pin number constraints can't be there also. > > Think of it this way, the VHDL you write is intended to define a logic > description. A logic description does not inherently require any > specific technology implementation. So any design constraints that > are dependent on the underlying technology should generally be stored > with whatever tool it is that allows one to implement the logic > description in that technology. Use that as your criteria for > deciding whether or not to define a constraint in the VHDL source code > or elsewhere. Thanks for your answers. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- Give a man a fish and you feed him for a day; teach a man to fish and you feed him for a lifetime. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzmyx8ACgkQM0LLzLt8MhyMlQCfRN5kB/3wXgO+yt93aLVvLNas R5UAn2Er2OSaljdy9iu0GvXP1El2RSKu =igyf -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!nuzba.szn.dk!news.szn.dk!pnx.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Newsgroups: comp.lang.vhdl Subject: Re: Buzzer References: <87pqu2usp7.fsf@merciadriluca-station.MERCIADRILUCA> From: Merciadri Luca Organization: ULg Date: Fri, 19 Nov 2010 20:08:24 +0100 Message-ID: <87d3q1p1w7.fsf@merciadriluca-station.MERCIADRILUCA> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.2 (gnu/linux) Cancel-Lock: sha1:tz8thdwv2AhyLOfCc/Z2NgeT74U= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 39 NNTP-Posting-Host: 85.26.2.239 X-Trace: news.sunsite.dk DXC=PETUXC[NbcW0Sc_VCmP]hZYSB=nbEKnk[3LlDMZ4XbVYZEVG4QK_]RP;@H2o^O>`Ol[NBH>TVH8HSaRLaf]]ES=S;40D?R X-Complaints-To: staff@sunsite.dk Xref: feeder.eternal-september.org comp.lang.vhdl:4407 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Merciadri Luca writes: > Hi, > > I've got a buzzer which is basically an output of my entity. Say this > is buzzer BUZ: out std_logic. > > Then, I want to put BUZ to 1 for just some very small amount of > time. I then tried > > == > BUZ <= '1'; > BUZ <= '0' after 500 ns; > == > > but it is apparently not appreciated from my compiler's point of view, > which complains about tristate problems, etc. > > Is there a simple solution to it? > > Thanks. Thanks all. - -- Merciadri Luca See http://www.student.montefiore.ulg.ac.be/~merciadri/ - -- If it's worth doing, it's worth over-doing. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Processed by Mailcrypt 3.5.8 iEYEARECAAYFAkzmyygACgkQM0LLzLt8MhyTrACgi7XWHu46WShb6RDnbFnMfxnQ E9QAn28KM4/qcIkIq8sWcDFT/pKHOy2p =eD7k -----END PGP SIGNATURE----- From newsfish@newsfish Fri Feb 3 13:08:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q14g2000yqe.googlegroups.com!not-for-mail From: Analog_Guy Newsgroups: comp.lang.vhdl Subject: Multiple Reset Inputs Date: Fri, 19 Nov 2010 23:09:30 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 24.150.100.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290236971 16912 127.0.0.1 (20 Nov 2010 07:09:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Nov 2010 07:09:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q14g2000yqe.googlegroups.com; posting-host=24.150.100.145; posting-account=UWE3jQkAAABcpV79MLIdWDGzI1XYb0Ot User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-us) AppleWebKit/533.18.1 (KHTML, like Gecko) Version/5.0.2 Safari/533.18.5,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4408 I generally implement resets with asynchronous assertion and synchronous de-assertion. With a single reset, this is simple. However, what happens if there are multiple reset inputs but I only want one internal reset? I was always under the impression that one should not have any combinational logic in the asynchronous reset path, as it could lead to static hazards (and reset glitches). So, how do you combine two resets into one without using combinational logic somewhere? I was thinking of two scenarios: 1. AND the two resets coming into the FPGA, and connect to the asynchronous reset of a synchronizer. The output of the synchronizer is the single internal reset. 2. Individually synchronize the two resets coming into the FPGA (note that each reset input feeds the asynchronous reset of the synchronizer). AND the output of each of the synchronizers and feed this single signal into the asynchronous reset of a final flip-flop. The output of this flip-flop is the single internal reset. In both cases we achieve asynchronous assertion and synchronous de- assertion ... however, in both cases there is combinational logic in the asynchronous reset path. Any suggestions how these multiple resets should be combined? From newsfish@newsfish Fri Feb 3 13:08:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j25g2000yqa.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Sat, 20 Nov 2010 11:08:54 -0800 (PST) Organization: http://groups.google.com Lines: 51 Message-ID: <50dff447-aa6d-46ef-955d-551e5ca08ced@j25g2000yqa.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290280134 31303 127.0.0.1 (20 Nov 2010 19:08:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 20 Nov 2010 19:08:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j25g2000yqa.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4409 On Nov 20, 2:09=A0am, Analog_Guy wrote: > I was always under the impression that one should not have any > combinational logic in the asynchronous reset path, as it could lead > to static hazards (and reset glitches). =A0 That would be the situation if you're trying to *avoid* resetting something because of a transient condition. An example would be if you're supposed to reset something when you've decoded a particular processor address. Simple combinatorial logic then might inadvertantly generate a reset pulse that is not wanted because of transient conditions on the address bus, propagation delays through logic paths, etc. > So, how do you combine two > resets into one without using combinational logic somewhere? > By or-ing them together. > I was thinking of two scenarios: > 1. AND the two resets coming into the FPGA, and connect to the > asynchronous reset of a synchronizer. =A0The output of the synchronizer > is the single internal reset. I think you mean 'or', not 'and'. But other than that, what you've described would be correct. > 2. Individually synchronize the two resets coming into the FPGA (note > that each reset input feeds the asynchronous reset of the > synchronizer). =A0AND the output of each of the synchronizers and feed > this single signal into the asynchronous reset of a final flip-flop. > The output of this flip-flop is the single internal reset. > Again, except for saying 'and' rather than 'or', what you've descirved would work here also. It would consume more resources, but it would work, no better, no worse than #1. > In both cases we achieve asynchronous assertion and synchronous de- > assertion ... however, in both cases there is combinational logic in > the asynchronous reset path. > But that combinatorial logic that you're talking about is not a problem because in this situation you're not trying to prevent a false logic reset from happening. It's good to question things one has 'always done' every now and then to refresh yourself on fundamentally why you do such things. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:08:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: Dave Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Sun, 21 Nov 2010 03:00:27 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: References: NNTP-Posting-Host: 91.84.86.43 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290337227 20870 127.0.0.1 (21 Nov 2010 11:00:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 21 Nov 2010 11:00:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=91.84.86.43; posting-account=yEeedQoAAAAW-TdoIYHIZrGsurykmF2S User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10_5_8; en-us) AppleWebKit/533.19.4 (KHTML, like Gecko) Version/5.0.3 Safari/533.19.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4410 On 19 Nov, 10:38, hssig wrote: > The following approach does not work: > sig <= '1', clk after 50 us; Try:- sig <= transport '1', clk after 50 us; (this instructs the simulator to model sig as a transmission line) From newsfish@newsfish Fri Feb 3 13:08:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!v20g2000yqb.googlegroups.com!not-for-mail From: makeuptest Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Procedures and Registers Date: Sun, 21 Nov 2010 19:34:19 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290396859 4376 127.0.0.1 (22 Nov 2010 03:34:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 03:34:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v20g2000yqb.googlegroups.com; posting-host=71.176.145.26; posting-account=X05sxgoAAADHzx4d_Xru0yHmZ5OQFj6h User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4411 comp.arch.fpga:13297 I was writing some code and decided to make it a procedure to put in a library. I have written functions many times, but not a procedure. This was a routine for some registers and counters internal to the procedure and so required a clock and reset. I couldn't figure out how to wirte it so that it would be inside a clocked process, so I added the clock and reset to the inputs and put the clocking code within the procedure. That was all well and good. But when I tried to test it, none of the internal variables that should have created registers were being remembered. I ran a simulation and the variables were getting reset initially, but on the next entry to the procedure they were back to being undefined. Do I have a basic misunderstanding about how procedures operate? I haven't found a good reference to explain enough to figure out what I am doing wrong. Greg From newsfish@newsfish Fri Feb 3 13:08:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Sun, 21 Nov 2010 21:00:49 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290402049 26978 127.0.0.1 (22 Nov 2010 05:00:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 05:00:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4412 comp.arch.fpga:13299 On Nov 21, 10:34=A0pm, makeuptest wrote: > > That was all well and good. =A0But when I tried to test it, none of the > internal variables that should have created registers were being > remembered. =A0I ran a simulation and the variables were getting reset > initially, but on the next entry to the procedure they were back to > being undefined. > Procedures do not inherently 'remember' the values of internal variables or signals as you would have in a process. Instead you must make the signal available on the interface of the procedure and hook up a real signal to that port. This generally means that you must actually add two signals to the interface of the procedure: one is an 'input' to the procedure which represents the current state of the signal; the other is an 'output' of the procedure which represent the next state of the signal. > Do I have a basic misunderstanding about how procedures operate? Yes...you can't hide signals within a procedure. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:08:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news.glorb.com!postnews.google.com!s16g2000yqc.googlegroups.com!not-for-mail From: makeuptest Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Mon, 22 Nov 2010 14:27:34 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> NNTP-Posting-Host: 71.176.145.26 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1290464854 15806 127.0.0.1 (22 Nov 2010 22:27:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 22 Nov 2010 22:27:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s16g2000yqc.googlegroups.com; posting-host=71.176.145.26; posting-account=X05sxgoAAADHzx4d_Xru0yHmZ5OQFj6h User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4413 comp.arch.fpga:13312 On Nov 22, 12:00=A0am, KJ wrote: > On Nov 21, 10:34=A0pm, makeuptest wrote: > > > > > That was all well and good. =A0But when I tried to test it, none of the > > internal variables that should have created registers were being > > remembered. =A0I ran a simulation and the variables were getting reset > > initially, but on the next entry to the procedure they were back to > > being undefined. > > Procedures do not inherently 'remember' the values of internal > variables or signals as you would have in a process. =A0Instead you must > make the signal available on the interface of the procedure and hook > up a real signal to that port. > > This generally means that you must actually add two signals to the > interface of the procedure: =A0one is an 'input' to the procedure which > represents the current state of the signal; the other is an 'output' > of the procedure which represent the next state of the signal. > > > Do I have a basic misunderstanding about how procedures operate? > > Yes...you can't hide signals within a procedure. > > Kevin Jennings Yes, I finally found a reference that says variables won't retain their values between invocations in a procedure. I guess that is different from a process, but now that I think about it, that only makes sense. In order to have a register created, the process would have to pass the value out and back in. Thanks From newsfish@newsfish Fri Feb 3 13:08:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Procedures and Registers Date: Mon, 22 Nov 2010 23:17:35 -0800 Lines: 11 Message-ID: <8l184fF1f2U1@mid.individual.net> References: <2a131ec1-db7e-42af-9ef2-a6bd784096ba@v20g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net JHfqs4AS7aThtMLvpLwU2gDsqIiKYIOAhqJdeP8yY9cfeDtXJd Cancel-Lock: sha1:6Y6Xh/dxb79nJbWrReJq2ejmX2M= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4414 comp.arch.fpga:13319 On 11/22/2010 2:27 PM, makeuptest wrote: > In order to have a register created, the process would > have to pass the value out and back in. > For example, see the procedure "retime" here: http://mysite.ncnetwork.net/reszotzl/rise_count.vhd -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!noc.nerim.net!nerim.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!k38g2000vbc.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Delaying signal assignment Date: Tue, 23 Nov 2010 02:45:55 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1290509155 7184 127.0.0.1 (23 Nov 2010 10:45:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 23 Nov 2010 10:45:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k38g2000vbc.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4415 >Don't make things too hard by thinking about them >too much... True point. Thank you for your suggestions. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:08:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u3g2000vbj.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Purpose of a string variable in a FSM process Date: Mon, 29 Nov 2010 05:01:51 -0800 (PST) Organization: http://groups.google.com Lines: 55 Message-ID: NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291035711 16398 127.0.0.1 (29 Nov 2010 13:01:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Nov 2010 13:01:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbj.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.41 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4418 Hello, I am working with Xilinx tools and have troubles understanding the purpose of a string variable init_fsm_name in the FSM process posted below (snipped). The code below was generated by Xilinx Core Generator. I guess it must be related to simulation, but simulation tools can already extract the name from the FSM state init_state_r. I would be grateful for shedding a light regarding this question. [code] process (pma_reset_done_i, init_fsm_wait_lock_check, lock_r, pcs_reset_done_i, wait_pcs_done_i, pcs_error_r1,wait_ready_done_i, pcs_error_count_done_i,init_state_r) variable init_fsm_name : string(1 to 25); begin case init_state_r is when C_RESET => init_next_state_r <= C_PMA_RESET; init_fsm_name := ExtendString("C_RESET", 25); when C_PMA_RESET => if (pma_reset_done_i = '1') then init_next_state_r <= C_WAIT_LOCK; else init_next_state_r <= C_PMA_RESET; end if; init_fsm_name := ExtendString("C_PMA_RESET", 25); when C_WAIT_LOCK => if(init_fsm_wait_lock_check = '1') then init_next_state_r <= C_PCS_RESET; else init_next_state_r <= C_WAIT_LOCK; end if; init_fsm_name := ExtendString("C_WAIT_LOCK", 25); -- some cases removed when others => init_next_state_r <= C_RESET; init_fsm_name := ExtendString("C_RESET", 25); end case; end process; [/code] From newsfish@newsfish Fri Feb 3 13:08:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Synthesis Only Date: Mon, 29 Nov 2010 12:52:45 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291063965 22306 127.0.0.1 (29 Nov 2010 20:52:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 29 Nov 2010 20:52:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_4; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4419 I'm trying to work around a bug in iSim where types with the enum_encoding attribute set such that they're one-hot encoded gives different results than in synthesis - essentially there's an off-by- one error in this case in the simulation for initialization. I've informed Xilinx, though the person handling the webcase seemed quite uninterested and so I have little faith it'll be fixed any time soon. I'm having trouble coming up with an acceptable work around. Take the following example: PROCESS( CLK ) TYPE TestType IS ( A, B, C ); ATTRIBUTE enum_encoding : string; ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; VARIABLE Test : TestType := A; BEGIN ... END PROCESS; XST results in Test having an initial value of A, and in iSim the initial value is B (if I had assigned B, XST would use B, and iSim would use C). The only way I've found to work around this is to use a function as follows: FUNCTION KludgeInit RETURN TestType IS VARIABLE IsSynth : BOOLEAN := TRUE; BEGIN -- pragma synthesis_off IsSynth := FALSE; -- pragma synthesis_on IF IsSynth THEN RETURN B; ELSE RETURN A; END IF; END KludgeInit; Of course, TestType must be declared B, A, C - there's no way to get at the first item in the list due to the error (using the last item causes iSim to crash.) This is horrific. Is there no way for me to disable enum_encoding entirely during simulation? Is there nothing like: -- pragma simulation_off ... -- pragma simulation_on From newsfish@newsfish Fri Feb 3 13:08:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!p11g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Mon, 29 Nov 2010 22:15:41 -0800 (PST) Organization: http://groups.google.com Lines: 62 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291097741 23184 127.0.0.1 (30 Nov 2010 06:15:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 06:15:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000vbn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4420 On Nov 29, 3:52=A0pm, Jonathan Ross wrote: > I'm trying to work around a bug in iSim where types with the > enum_encoding attribute set such that they're one-hot encoded gives > different results than in synthesis - essentially there's an off-by- > one error in this case in the simulation for initialization. Just noting here that simulation doesn't give a hoot about the enum_encoding attributes. > I've > informed Xilinx, though the person handling the webcase seemed quite > uninterested and so I have little faith it'll be fixed any time soon. > I'm having trouble coming up with an acceptable work around. Take the > following example: > > PROCESS( CLK ) > =A0 =A0 TYPE TestType IS ( A, B, C ); > =A0 =A0 ATTRIBUTE enum_encoding : string; > =A0 =A0 ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; > =A0 =A0 VARIABLE Test : TestType :=3D A; > BEGIN > =A0 =A0... > END PROCESS; > > XST results in Test having an initial value of A, This is correct... > and in iSim the > initial value is B A few possibilities come to mine: - iSim may be wrong - You've missed a synthesis warning/note that said something to the effect that the encoding of Test is not the same as what you've put into the 'enum_encoding' attribute. - It could be that you're misinterpreting which nodes are which. Presumably 'Test' gets synthesized as actual signals Test(2-0), so when you say "100" for 'A', is Test(2) =3D '1' or is Test(0)? How do you know this to be true? Check the synthesis notes for confirmation. - From your snippet, one can't tell if Test will result in flops or not. If they are not the outputs of flip flops, then 'Test' might get combined with other combinatorial logic in your design but still get assigned the name 'Test' and you're interpreting that node to be the same thing as listed in your source code. Assign an output signal of the top level of the design to 'Test' and see what really pops out. > > This is horrific. Is there no way for me to disable enum_encoding > entirely during simulation? Is there nothing like: > > -- pragma simulation_off > ... > -- pragma simulation_on Any time you try to make simulation different from synthesis you're starting down a bad path. The likely cause is probably listed above. Peruse the synthesis warnings, make 'Test' temporarily be an output of the design if you have to in order to debug and trudge forward. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:08:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Purpose of a string variable in a FSM process Date: Tue, 30 Nov 2010 08:41:12 -0800 Lines: 28 Message-ID: <8lknp7Fg7tU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net MpzK8IHdFivEILtoDHhioQyh0LwlkE97X1sJ/86GQUXAKsKSvs Cancel-Lock: sha1:dzQdd+FBwi3mb4rmJRMN9Bc+ugQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4422 On 11/29/2010 5:01 AM, a s wrote: > I am working with Xilinx tools and have troubles understanding the > purpose of a string variable init_fsm_name in the FSM process posted below > The code below was generated by Xilinx Core Generator. > I guess it must be related to simulation, but simulation tools can > already extract the name from the FSM state init_state_r. > I would be grateful for shedding a light regarding this question. If I write my own synthesis code, I can use the same vhdl or verilog code directly for synthesis or as a simulation model. If I use a vendor core, no such vhdl source is provided. Vendor core generators collect parameter strings from me to generate a vendor-specific netlist for synthesis and a vhdl (or verilog) simulation model based on my entered parameters. Note that my synthesis input is a collection of strings, not code. Your code example is probably part of such a simulation model. I don't spend any time analyzing such code because: 1. It is not safe to touch it because I don't have the core source, and 2. If provides little useful information on how equivalent synthesis code might be written. If I were a fpga vendor, I might want my generated models to work well enough to test the core without revealing the design to the user. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:08:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!u3g2000vbj.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Tue, 30 Nov 2010 10:41:59 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: <6c324eaa-475e-40fb-a0a4-69f0efffe63a@u3g2000vbj.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> NNTP-Posting-Host: 188.28.151.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291142519 1351 127.0.0.1 (30 Nov 2010 18:41:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 18:41:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbj.googlegroups.com; posting-host=188.28.151.15; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4423 remember the two flip flop rule one for async to sync, and one to leave one propergation interval for what? seems almost silly! maybe its a feedback reset reduction fan out technique. From newsfish@newsfish Fri Feb 3 13:08:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!c17g2000prm.googlegroups.com!not-for-mail From: Swapnajit Newsgroups: comp.lang.verilog,comp.lang.vhdl Subject: Do you have a separate Verification team? Date: Tue, 30 Nov 2010 12:11:32 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 12.35.78.5 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291147893 25187 127.0.0.1 (30 Nov 2010 20:11:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 30 Nov 2010 20:11:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c17g2000prm.googlegroups.com; posting-host=12.35.78.5; posting-account=bDLsBQkAAAB3tCuLYhxyPevTa4ZY2yB2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1; .NET CLR 3.0.04506.30; OfficeLiveConnector.1.3; OfficeLivePatch.0.0; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:2696 comp.lang.vhdl:4424 Request for participation: I started an online poll on this basic question as it is fundamental to verification management. Your participation is requested. Here is the link: polls.linkedin.com/p/111235/fmnat Thanks. From newsfish@newsfish Fri Feb 3 13:08:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!29g2000yqq.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Re: Purpose of a string variable in a FSM process Date: Tue, 30 Nov 2010 23:21:18 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: <4bbe0455-c90f-43b9-abea-e845ee410f72@29g2000yqq.googlegroups.com> References: <8lknp7Fg7tU1@mid.individual.net> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291188078 22854 127.0.0.1 (1 Dec 2010 07:21:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 07:21:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000yqq.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.41 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4425 On Nov 30, 5:41=A0pm, Mike Treseler wrote: > On 11/29/2010 5:01 AM, a s wrote: > > > I am working with Xilinx tools and have troubles understanding the > > purpose of a string variable init_fsm_name in the FSM process posted be= low > > The code below was generated by Xilinx Core Generator. > > I guess it must be related to simulation, but simulation tools can > > already extract the name from the FSM state init_state_r. > > I would be grateful for shedding a light regarding this question. > > If I write my own synthesis code, I can use the same vhdl or verilog > code directly for synthesis or as a simulation model. If I use a vendor > core, no such vhdl source is provided. Vendor core generators collect > parameter strings from me to generate a vendor-specific netlist for > synthesis and a vhdl (or verilog) simulation model based on my entered > parameters. > Note that my synthesis input is a collection of strings, not code. > > Your code example is probably part of such a simulation model. > I don't spend any time analyzing such code because: > 1. It is not safe to touch it because I don't have the core source, and > 2. If provides little useful information on how equivalent synthesis > code might be written. > > If I were a fpga vendor, I might want my generated models to > work well enough to test the core without revealing the design > to the user. Mike, thanks for the input. I completely agree that one should not modify the code generated with a "wizard". I am just trying to understand the purpose of that code as I am still learning VHDL. BTW, the code sample is taken from the code which is responsible for initialization of RocketIO in Virtex4, but I have seen similar constructs in other Xilinx "wizard" generated code. From newsfish@newsfish Fri Feb 3 13:08:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!a17g2000yql.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: CONFUSED WITH NUMBERS Date: Wed, 1 Dec 2010 08:27:20 -0800 (PST) Organization: http://groups.google.com Lines: 13 Message-ID: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> NNTP-Posting-Host: 93.173.6.39 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291220841 14327 127.0.0.1 (1 Dec 2010 16:27:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 16:27:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a17g2000yql.googlegroups.com; posting-host=93.173.6.39; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4426 Hi all Numbers confuse me in VHDL . For example when a in port receives data from an Analog To Digital converter that represents fractions numbers smaller then one like +0.54 or - 0.33 . In that case how do I define that in port I gues i will use the NUMERIC_STD package . Please clarift the subject for me and all newbees to VHDL . Thanks EC From newsfish@newsfish Fri Feb 3 13:08:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 01 Dec 2010 11:42:24 -0600 Date: Wed, 01 Dec 2010 09:42:25 -0800 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> In-Reply-To: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> Lines: 75 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-JNAH7WKnoazRKULmCtVKkIHXVURq1sypc6jKo4JZE+Nybhj5tlk0zsPhJ4q63j7jT7KBMsgM7Jf0lzE!k3hbShl+HVdSsfUcM1kvgXRl5Qnzu+gLlWaNDG1D+Q/iQVMQ5yFiUU1+Gn06iNfPTs8TNZ2W08nx!Bg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4932 Xref: feeder.eternal-september.org comp.lang.vhdl:4427 On 12/1/2010 8:27 AM, TheRightInfo wrote: > Hi all > Numbers confuse me in VHDL . > For example when a in port receives data from an Analog To Digital > converter that represents fractions numbers smaller then > one like +0.54 or - 0.33 . > > In that case how do I define that in port I gues i will use the > NUMERIC_STD package . > > Please clarift the subject for me and all newbees to VHDL . > > Thanks > EC A port connected to an analog to digital converter receives bits. 1's and 0's. Sometimes parallel, sometimes serially, sometimes a combination of the two. And, as it's connected to external hardware, you'll have the best luck doing that connection using std_logic and std_logic_vector. Now you've got bits, and it's your job to come up with an interpretation of them. Typically, you'd represent that as either a SIGNED or an UNSIGNED, based on whether the ADC is bipolar or unipolar. It's possible that the ADC is bipolar (SIGNED) but outputs it's information not in two's compliment but in what's known as offset binary (0 = -fullscale, '1' followed by all '0's = 0, all '1' = +fullscale), in which case you'd want to invert the MSB in order to have a normal, two's compliment SIGNED number. You could also use the native integer type for this instead of a NUMERIC_STD, in which case you'd want to use a bounded one, i.e. x : integer range 0 to 4095. This will simulate ever so marginally faster, simplify some tasks, and complicate some others. So now you've got an entity. That entity's job is to look on one side like an interface full of std_logic* types to talk to the physical ADC, and on the other to be one of the NUMERIC_STD types along with whatever control signals the rest of your design needs. The left side talks to the physical layer, the right side provides semi-abstracted data. Designing the contents of that entity required you to become fairly familiar with the data sheet of the specific ADC in question, but you now get to leave the knowledge of the specific interface details inside that box, flush your brain cache, bring that entity in as a component of your larger design, and concentrate on what you wish to do with the data rather than how you got it. Whether you've chosen to work with NUMERIC_STD types or integers, you're now holding data that you've declared to represent integer numbers. These numbers map linearly onto the voltage applied at the input of the ADC. For instance, a 12-bit unipolar ADC with a 4.096V input range. In this case, you've got one of the following: x : unsigned(11 downto 0); x : integer range 0 to 4095; In either case, 1 LSB (least significant bit) corresponds to 1 mV on the input. Keeping track of this is your responsibility, the tools have no help to offer you. So it's your job to know that 10 (16#00A#) means 10 mV. This is where comments are your friend. If the numbers only matter to you relative to full scale, the fundamental relationship is, in this case, value = x / 4096. Notice that, as x can never exceed 4095, you now have a fractional value between 0 and 0.99976. This, once again, has to be kept track of by you. It's theoretically possible to use the VHDL2008 fixed point package for this instead; practically the tool support for doing so is pretty abysmal and you'll most likely just get yourself in trouble. Thus concludes the answer to your question. Now, in exchange for this lesson, please turn on the damn spell check for whatever method it is you're using to throw questions out to the Internet. It's like reading a train crash in a blender. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:08:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS Date: Wed, 1 Dec 2010 09:53:41 -0800 (PST) Organization: http://groups.google.com Lines: 81 Message-ID: <4cdd5f67-1f3d-4430-bee6-6f374fd6a271@30g2000yql.googlegroups.com> References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> NNTP-Posting-Host: 93.172.170.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291226021 31925 127.0.0.1 (1 Dec 2010 17:53:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Dec 2010 17:53:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=93.172.170.107; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4428 On Dec 1, 7:42=A0pm, Rob Gaddi wrote: > On 12/1/2010 8:27 AM, TheRightInfo wrote: > > > Hi all > > Numbers confuse me in VHDL . > > For example when a in port receives data from an Analog To Digital > > converter that represents fractions numbers smaller then > > one like +0.54 or - 0.33 . > > > In that case how do I define that in port I gues i will use the > > NUMERIC_STD package . > > > Please clarift the subject for me and all newbees to VHDL . > > > Thanks > > EC > > A port connected to an analog to digital converter receives bits. =A01's > and 0's. =A0Sometimes parallel, sometimes serially, sometimes a > combination of the two. =A0And, as it's connected to external hardware, > you'll have the best luck doing that connection using std_logic and > std_logic_vector. > > Now you've got bits, and it's your job to come up with an interpretation > of them. =A0Typically, you'd represent that as either a SIGNED or an > UNSIGNED, based on whether the ADC is bipolar or unipolar. =A0It's > possible that the ADC is bipolar (SIGNED) but outputs it's information > not in two's compliment but in what's known as offset binary (0 =3D > -fullscale, '1' followed by all '0's =3D 0, all '1' =3D +fullscale), in > which case you'd want to invert the MSB in order to have a normal, two's > compliment SIGNED number. =A0You could also use the native integer type > for this instead of a NUMERIC_STD, in which case you'd want to use a > bounded one, i.e. x : integer range 0 to 4095. =A0This will simulate ever > so marginally faster, simplify some tasks, and complicate some others. > > So now you've got an entity. =A0That entity's job is to look on one side > like an interface full of std_logic* types to talk to the physical ADC, > and on the other to be one of the NUMERIC_STD types along with whatever > control signals the rest of your design needs. =A0The left side talks to > the physical layer, the right side provides semi-abstracted data. > > Designing the contents of that entity required you to become fairly > familiar with the data sheet of the specific ADC in question, but you > now get to leave the knowledge of the specific interface details inside > that box, flush your brain cache, bring that entity in as a component of > your larger design, and concentrate on what you wish to do with the data > rather than how you got it. > > Whether you've chosen to work with NUMERIC_STD types or integers, you're > now holding data that you've declared to represent integer numbers. > These numbers map linearly onto the voltage applied at the input of the > ADC. =A0For instance, a 12-bit unipolar ADC with a 4.096V input range. = =A0In > this case, you've got one of the following: > =A0 =A0 =A0 =A0 x : unsigned(11 downto 0); > =A0 =A0 =A0 =A0 x : integer range 0 to 4095; > > In either case, 1 LSB (least significant bit) corresponds to 1 mV on the > input. =A0Keeping track of this is your responsibility, the tools have no > help to offer you. =A0So it's your job to know that 10 (16#00A#) means 10 > mV. =A0This is where comments are your friend. > > If the numbers only matter to you relative to full scale, the > fundamental relationship is, in this case, value =3D x / 4096. =A0Notice > that, as x can never exceed 4095, you now have a fractional value > between 0 and 0.99976. =A0This, once again, has to be kept track of by > you. =A0It's theoretically possible to use the VHDL2008 fixed point > package for this instead; practically the tool support for doing so is > pretty abysmal and you'll most likely just get yourself in trouble. > > Thus concludes the answer to your question. =A0Now, in exchange for this > lesson, please turn on the damn spell check for whatever method it is > you're using to throw questions out to the Internet. =A0It's like reading > a train crash in a blender. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Many Many Thanks EC From newsfish@newsfish Fri Feb 3 13:08:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Multiple Reset Inputs Date: Thu, 2 Dec 2010 10:59:58 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <5595c317-30c2-46d5-9836-f905fe1c6315@r29g2000yqj.googlegroups.com> References: <0e38a6e9-a14f-4a00-a01c-6dd6e92c5545@q14g2000yqe.googlegroups.com> <6c324eaa-475e-40fb-a0a4-69f0efffe63a@u3g2000vbj.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291316398 20918 127.0.0.1 (2 Dec 2010 18:59:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Dec 2010 18:59:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4429 On Nov 30, 12:41=A0pm, jacko wrote: > remember the two flip flop rule one for async to sync, and one to > leave one propergation interval for what? seems almost silly! maybe > its a feedback reset reduction fan out technique. The 2nd flop is to reject a potential metastable pulse from the 1st synchronizing flop. It is not necessary if the destination is another flop on the same or related clock, and you have sufficiently extra timing margin to get there (a few extra nanoseconds will buy an eon in MTBF in most FPGAs). Andy From newsfish@newsfish Fri Feb 3 13:08:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j29g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: CONFUSED WITH NUMBERS Date: Thu, 2 Dec 2010 11:06:34 -0800 (PST) Organization: http://groups.google.com Lines: 110 Message-ID: <1f34187c-f118-4a9e-8582-464b755aeecb@j29g2000yqm.googlegroups.com> References: <5a83737c-8d23-435d-abe6-4a68f6772253@a17g2000yql.googlegroups.com> <7uKdnZJO9OedFGvRnZ2dnUVZ_uidnZ2d@lmi.net> <4cdd5f67-1f3d-4430-bee6-6f374fd6a271@30g2000yql.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291316794 25201 127.0.0.1 (2 Dec 2010 19:06:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 2 Dec 2010 19:06:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j29g2000yqm.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4430 On Dec 1, 11:53=A0am, TheRightInfo wrote: > On Dec 1, 7:42=A0pm, Rob Gaddi wrote: > > > > > > > On 12/1/2010 8:27 AM, TheRightInfo wrote: > > > > Hi all > > > Numbers confuse me in VHDL . > > > For example when a in port receives data from an Analog To Digital > > > converter that represents fractions numbers smaller then > > > one like +0.54 or - 0.33 . > > > > In that case how do I define that in port I gues i will use the > > > NUMERIC_STD package . > > > > Please clarift the subject for me and all newbees to VHDL . > > > > Thanks > > > EC > > > A port connected to an analog to digital converter receives bits. =A01'= s > > and 0's. =A0Sometimes parallel, sometimes serially, sometimes a > > combination of the two. =A0And, as it's connected to external hardware, > > you'll have the best luck doing that connection using std_logic and > > std_logic_vector. > > > Now you've got bits, and it's your job to come up with an interpretatio= n > > of them. =A0Typically, you'd represent that as either a SIGNED or an > > UNSIGNED, based on whether the ADC is bipolar or unipolar. =A0It's > > possible that the ADC is bipolar (SIGNED) but outputs it's information > > not in two's compliment but in what's known as offset binary (0 =3D > > -fullscale, '1' followed by all '0's =3D 0, all '1' =3D +fullscale), in > > which case you'd want to invert the MSB in order to have a normal, two'= s > > compliment SIGNED number. =A0You could also use the native integer type > > for this instead of a NUMERIC_STD, in which case you'd want to use a > > bounded one, i.e. x : integer range 0 to 4095. =A0This will simulate ev= er > > so marginally faster, simplify some tasks, and complicate some others. > > > So now you've got an entity. =A0That entity's job is to look on one sid= e > > like an interface full of std_logic* types to talk to the physical ADC, > > and on the other to be one of the NUMERIC_STD types along with whatever > > control signals the rest of your design needs. =A0The left side talks t= o > > the physical layer, the right side provides semi-abstracted data. > > > Designing the contents of that entity required you to become fairly > > familiar with the data sheet of the specific ADC in question, but you > > now get to leave the knowledge of the specific interface details inside > > that box, flush your brain cache, bring that entity in as a component o= f > > your larger design, and concentrate on what you wish to do with the dat= a > > rather than how you got it. > > > Whether you've chosen to work with NUMERIC_STD types or integers, you'r= e > > now holding data that you've declared to represent integer numbers. > > These numbers map linearly onto the voltage applied at the input of the > > ADC. =A0For instance, a 12-bit unipolar ADC with a 4.096V input range. = =A0In > > this case, you've got one of the following: > > =A0 =A0 =A0 =A0 x : unsigned(11 downto 0); > > =A0 =A0 =A0 =A0 x : integer range 0 to 4095; > > > In either case, 1 LSB (least significant bit) corresponds to 1 mV on th= e > > input. =A0Keeping track of this is your responsibility, the tools have = no > > help to offer you. =A0So it's your job to know that 10 (16#00A#) means = 10 > > mV. =A0This is where comments are your friend. > > > If the numbers only matter to you relative to full scale, the > > fundamental relationship is, in this case, value =3D x / 4096. =A0Notic= e > > that, as x can never exceed 4095, you now have a fractional value > > between 0 and 0.99976. =A0This, once again, has to be kept track of by > > you. =A0It's theoretically possible to use the VHDL2008 fixed point > > package for this instead; practically the tool support for doing so is > > pretty abysmal and you'll most likely just get yourself in trouble. > > > Thus concludes the answer to your question. =A0Now, in exchange for thi= s > > lesson, please turn on the damn spell check for whatever method it is > > you're using to throw questions out to the Internet. =A0It's like readi= ng > > a train crash in a blender. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order > > Many Many Thanks > EC- Hide quoted text - > > - Show quoted text - You should take a look at the new fixed point VHDL packages, for doing fixed point (integer and fractional) arithmetic in synthesizable vhdl. Andy From newsfish@newsfish Fri Feb 3 13:08:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!22g2000prx.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: FPGA project structure definition Date: Fri, 3 Dec 2010 04:32:42 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291379563 17937 127.0.0.1 (3 Dec 2010 12:32:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 3 Dec 2010 12:32:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 22g2000prx.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13522 comp.lang.verilog:2703 comp.lang.vhdl:4431 I've written up an (informal) draft proposal for an FPGA project structure that could be easily extended as the project grows and is version control friendly. I'd be grateful for any type of feedback... http://www.saardrimer.com/fpgaproj/ cheers, saar. From newsfish@newsfish Fri Feb 3 13:08:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!v19g2000yqa.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Sat, 4 Dec 2010 10:05:00 -0800 (PST) Organization: http://groups.google.com Lines: 79 Message-ID: <8f170397-081e-4631-a211-c422d46f7dea@v19g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291485900 4768 127.0.0.1 (4 Dec 2010 18:05:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 18:05:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqa.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13547 comp.lang.verilog:2705 comp.lang.vhdl:4432 On Dec 3, 7:32=A0am, saar drimer wrote: > I've written up an (informal) draft proposal for an FPGA project > structure that could be easily extended as the project grows and is > version control friendly. I'd be grateful for any type of feedback... > > =A0http://www.saardrimer.com/fpgaproj/ > > cheers, > saar. First some minuta. The figures aren't labeled, so it's hard to target comments for one. The first figure, "The 'flow'", doesn't have a "Build Scripts" as a source file type. I realize you had planned to make a distinction between scripts and source, but our build scripts are checked into our repository under the Philosophy that any checkout should be buildable as is, and we consider them part of our source. Also, testbenches should make mention of Unit Testing in hardware - it's automated and should be part of a mature build cycle. Scoping/ Tapping on the other hand is part of the development process so doesn't necessarily need to be mentioned here. I was in the study phase of implementing an SCons Builder/Scanner for XST/VHDL for my build cycles. Requiring that VHDL files share the entity name would make scanning dramatically easier; as I control our own internal standards I'll make this a requirement, along with configurations and components as well. You might consider requiring that source files fall under a directory with the same name as the library they're in. For example, if the entity Foo was part of library work, and Bar was part of library play, the directory structure look like so: ../Project/sources/hdl/work/Foo.vhd ../Project/sources/hdl/play/Bar.vhd We don't do any Verilog development so I'm not sure how the concept of a library is handled there. Another issue we have is that a lot of our sub-components should be accessible by some engineers, but not all engineers. By writing SCons SConstruct and SConscript files and using BuildBot, the idea was that an engineer could check in their sub-project and the server would initialize a build over the whole project while keeping components isolated to their respective developers. That is - our organizational issue is as follows: each component should have two levels of access - one public for declaration, one private for specification; if a team was designing an Ethernet controller we'd want the entity, component, configurations, behavioral simulations, and packages that define the types needed to interface with it to be available to everyone, while we'd want the implementation structure hidden. This would require a public/private fork of the directory structure under mercurial to accomplish, i.e. ../Project/public/source/hdl/work/Foo.vhd ../Project/private/source/hdl/work/Bar.vhd Then there would be a mercurial repository at Project, and public and private would be sub-repositories. Further, since mercurial allows pre and post hooks for all commands, the plan was to preempt any push to a stable repository on the server with an initiation of Unit Tests across the entire project (sub and sup modules...) that must be passed before it can successfully be pushed. The issue is that some modules will be used in multiple projects. We have yet to figure out the optimal method of doing this. I.E. Project1/submodules/Project3/... Project2/submodules/Project3/... Project3/... Pushes to Project3 should automatically initiate unit testing for Project1 and Project2. I have no clue how to do this effectively and efficiently. Overall though, I like the proposal. If I can make it fit my need for public/private portions of submodules I'll definitely use it. Thanks. ~Jonathan Ross From newsfish@newsfish Fri Feb 3 13:08:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sat, 4 Dec 2010 10:57:51 -0800 (PST) Organization: http://groups.google.com Lines: 82 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291489071 2575 127.0.0.1 (4 Dec 2010 18:57:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 18:57:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4433 On Nov 30, 1:15=A0am, KJ wrote: > On Nov 29, 3:52=A0pm, Jonathan Ross > wrote: > > > I'm trying to work around a bug in iSim where types with the > > enum_encoding attribute set such that they're one-hot encoded gives > > different results than in synthesis - essentially there's an off-by- > > one error in this case in the simulation for initialization. > > Just noting here that simulation doesn't give a hoot about the > enum_encoding attributes. > > > > > > > > > > > I've > > informed Xilinx, though the person handling the webcase seemed quite > > uninterested and so I have little faith it'll be fixed any time soon. > > I'm having trouble coming up with an acceptable work around. Take the > > following example: > > > PROCESS( CLK ) > > =A0 =A0 TYPE TestType IS ( A, B, C ); > > =A0 =A0 ATTRIBUTE enum_encoding : string; > > =A0 =A0 ATTRIBUTE enum_encoding OF TestType : TYPE IS "100 010 001"; > > =A0 =A0 VARIABLE Test : TestType :=3D A; > > BEGIN > > =A0 =A0... > > END PROCESS; > > > XST results in Test having an initial value of A, > > This is correct... > > > and in iSim the > > initial value is B > > A few possibilities come to mine: > - iSim may be wrong > - You've missed a synthesis warning/note that said something to the > effect that the encoding of Test is not the same as what you've put > into the 'enum_encoding' attribute. > - It could be that you're misinterpreting which nodes are which. > Presumably 'Test' gets synthesized as actual signals Test(2-0), so > when you say "100" for 'A', is Test(2) =3D '1' or is Test(0)? =A0How do > you know this to be true? =A0Check the synthesis notes for confirmation. > - From your snippet, one can't tell if Test will result in flops or > not. =A0If they are not the outputs of flip flops, then 'Test' might get > combined with other combinatorial logic in your design but still get > assigned the name 'Test' and you're interpreting that node to be the > same thing as listed in your source code. =A0Assign an output signal of > the top level of the design to 'Test' and see what really pops out. > > > > > This is horrific. Is there no way for me to disable enum_encoding > > entirely during simulation? Is there nothing like: > > > -- pragma simulation_off > > ... > > -- pragma simulation_on > > Any time you try to make simulation different from synthesis you're > starting down a bad path. =A0The likely cause is probably listed above. > Peruse the synthesis warnings, make 'Test' temporarily be an output of > the design if you have to in order to debug and trudge forward. > > Kevin Jennings There was no warning. It's a highly repeatable issue. It probably went undiscovered because it doesn't occur if you set a value during reset - only if you initialize a value. The workaround we finally came up with was to use a function to produce a one-hot encoding for the string argument of enum_encoding. When it doesn't detect simulation it produces a binary encoding instead. From newsfish@newsfish Fri Feb 3 13:08:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!l32g2000yqc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Concurrent Logic Timing Date: Sat, 4 Dec 2010 14:32:53 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291501973 22282 127.0.0.1 (4 Dec 2010 22:32:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 4 Dec 2010 22:32:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l32g2000yqc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4434 comp.arch.fpga:13551 I suppose this is something that you need to expect, but I just have never come across this before. I have some concurrent logic equations using integers where one input common to two assignments changes and because one gets updated before the other, one is set to a value that is outside the range of the integer and flags an error in simulation. C <= B - A * stuff; D <= A + C; -- A changes and puts D outside of its range until C is updated In the real world, this is not really an issue since all sorts of intermediate states are expected when doing arithmetic. But VHDL doesn't seem to accommodate this well. The only way I can think of to fix this, without changing the logic, is to do these calculations inside a combinatorial process using variables. Then I can control the sequence of updates explicitly. The only other thing I can think is to assign A to A' and use A' in place of A in the assignment for D. That may still allow an error, but if A'' is used, then there will be two delta delays in D assignment path. However, if C grows because A has shrunk, then that could cause the same sort of out of bounds error on D. Is there another way make this work that isn't so cumbersome? Rick From newsfish@newsfish Fri Feb 3 13:08:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 23:29:44 +0000 (UTC) Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> Injection-Date: Sat, 4 Dec 2010 23:29:44 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="30122"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/fdpEjHS4AFSfCeehgqV7i" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:ndTzA/eMX3waBinu0mmL9tQOoXI= Xref: feeder.eternal-september.org comp.lang.vhdl:4435 comp.arch.fpga:13552 In comp.arch.fpga rickman wrote: > I suppose this is something that you need to expect, but I just have > never come across this before. I have some concurrent logic equations > using integers where one input common to two assignments changes and > because one gets updated before the other, one is set to a value that > is outside the range of the integer and flags an error in > simulation. > C <= B - A * stuff; > D <= A + C; -- A changes and puts D outside of its range until C is > updated > In the real world, this is not really an issue since all sorts of > intermediate states are expected when doing arithmetic. But VHDL > doesn't seem to accommodate this well. I don't think verilog has this problem, but it might just be because I would do it with reg [32] and not integer. I think you can do something similar to reg [32] in VHDL, and likely avoid the problem. (snip) -- glen From newsfish@newsfish Fri Feb 3 13:08:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: VHDL Automated Testing Date: Sat, 4 Dec 2010 16:09:17 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291507757 20309 127.0.0.1 (5 Dec 2010 00:09:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 00:09:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4436 I'm trying to implement an automated testing hardness for a VHDL project. We compile and link with vhpcomp and fuse respectively. 1. The program generated will only run under xtclsh - is there any way to get it to run in bash? 2. The following code generates the following output: PROCESS BEGIN REPORT "Hello World!" SEVERITY NOTE; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY NOTE; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY WARNING; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY ERROR; ASSERT 1 = 1 REPORT "1 = 1" SEVERITY FAILURE; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY NOTE; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY WARNING; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY ERROR; ASSERT 1 = 2 REPORT "1 = 2" SEVERITY FAILURE; WAIT; END PROCESS; ISim> run Simulator is doing circuit initialization process. at 0 ps: Note: Hello World! (/vhdlunit/). at 0 ps: Note: 1 = 2 (/vhdlunit/). at 0 ps, Instance /vhdlunit/ : Warning: 1 = 2 at 0 ps: Error: 1 = 2 ** Failure:1 = 2 User(VHDL) Code Called Simulation Stop In process VHDLUNIT.vhd:10 INFO: Simulator is stopped. ISim> The program doesn't exit even on failure, so there's no error code for my harness to use. Also, besides reporting or asserting with severity failure, I can't figure out how to get it to stop. How to I control my return code? 3. GHDL seems better designed for this use, but we've seen discrepancies between iSim and XST so we're worried they'd be even worse with a tool not made by Xilinx. To be fair though, most of the issues have been iSim issues more than they've been XST issues, so if GHDL works well it might work better than XST. Thanks. From newsfish@newsfish Fri Feb 3 13:09:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!i18g2000yqn.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 17:05:54 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291511154 20733 127.0.0.1 (5 Dec 2010 01:05:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 01:05:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000yqn.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4437 comp.arch.fpga:13553 On Dec 4, 5:32=A0pm, rickman wrote: > I suppose this is something that you need to expect, but I just have > never come across this before. =A0I have some concurrent logic equations > using integers where one input common to two assignments changes and > because one gets updated before the other, one is set to a value that > is outside the range of the integer and flags an error in > simulation. > > C <=3D B - A * stuff; > D <=3D A + C; =A0-- A changes and puts D outside of its range until C is > updated > > In the real world, this is not really an issue since all sorts of > intermediate states are expected when doing arithmetic. =A0But VHDL > doesn't seem to accommodate this well. =A0The only way I can think of to > fix this, without changing the logic, is to do these calculations > inside a combinatorial process using variables. =A0Then I can control > the sequence of updates explicitly. > > The only other thing I can think is to assign A to A' and use A' in > place of A in the assignment for D. =A0That may still allow an error, > but if A'' is used, then there will be two delta delays in D > assignment path. =A0However, if C grows because A has shrunk, then that > could cause the same sort of out of bounds error on D. > > Is there another way make this work that isn't so cumbersome? > > Rick Try using either the SIGNED or UNSIGNED type instead of integer. From newsfish@newsfish Fri Feb 3 13:09:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sat, 4 Dec 2010 18:58:52 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291517932 19204 127.0.0.1 (5 Dec 2010 02:58:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 02:58:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4438 On Dec 4, 1:57=A0pm, Jonathan Ross wrote: > > There was no warning. It's a highly repeatable issue. It probably went > undiscovered because it doesn't occur if you set a value during reset > - only if you initialize a value. > The only place you should ever consider using an initial value is in the shift register that synchronizes an external reset signal to a clock. You shouldn't use initial values anywhere else. You likely have no control over when the clock starts up relative to the design coming alive which means you have no way of guaranteeing setup/hold times are met on that very first clock cycle. That's why you should always design in an explicit reset...and why you found that it 'works' for you when you do that. > The workaround we finally came up with was to use a function to > produce a one-hot encoding for the string argument of enum_encoding. > When it doesn't detect simulation it produces a binary encoding > instead. When you have the solution and found that it works (i.e. using an explicit reset) then why would you even consider a workaround? As I mentioned before, any time you try to make simulation different from synthesis you're starting down a bad path. That bad path will end up biting you in the rear eventually if you continue to follow it. KJ From newsfish@newsfish Fri Feb 3 13:09:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!216.196.98.144.MISMATCH!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!j18g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Sat, 4 Dec 2010 19:55:34 -0800 (PST) Organization: http://groups.google.com Lines: 54 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291521335 13396 127.0.0.1 (5 Dec 2010 03:55:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 03:55:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4439 comp.arch.fpga:13554 On Dec 4, 8:05=A0pm, Jonathan Ross wrote: > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > I suppose this is something that you need to expect, but I just have > > never come across this before. =A0I have some concurrent logic equation= s > > using integers where one input common to two assignments changes and > > because one gets updated before the other, one is set to a value that > > is outside the range of the integer and flags an error in > > simulation. > > > C <=3D B - A * stuff; > > D <=3D A + C; =A0-- A changes and puts D outside of its range until C i= s > > updated > > > In the real world, this is not really an issue since all sorts of > > intermediate states are expected when doing arithmetic. =A0But VHDL > > doesn't seem to accommodate this well. =A0The only way I can think of t= o > > fix this, without changing the logic, is to do these calculations > > inside a combinatorial process using variables. =A0Then I can control > > the sequence of updates explicitly. > > > The only other thing I can think is to assign A to A' and use A' in > > place of A in the assignment for D. =A0That may still allow an error, > > but if A'' is used, then there will be two delta delays in D > > assignment path. =A0However, if C grows because A has shrunk, then that > > could cause the same sort of out of bounds error on D. > > > Is there another way make this work that isn't so cumbersome? > > > Rick > > Try using either the SIGNED or UNSIGNED type instead of integer. I see what the two of you are saying. By using integer it will be tested for range bounds. std_logic_vector types don't get that level of analysis. The range testing is useful when it is done properly. By properly, I mean so that it is checking the logic, not your skill at eliminating glitches in combinatorial logic... For the short term I put it in a combinatorial process. The other thing that would have been pretty easy would be to combine the two into one assignment. The first assignment was just an intermediate to facilitate debugging. I guess I'm just surprised that I've never been bitten by this before. Rick From newsfish@newsfish Fri Feb 3 13:09:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!ircam.fr!freenix!exabot.com!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp9-1.free.fr!not-for-mail Date: Sun, 05 Dec 2010 14:55:45 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.12) Gecko/20101027 Thunderbird/3.1.6 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> In-Reply-To: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 45 Message-ID: <4cfb99de$0$7523$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 05 Dec 2010 14:55:42 MET NNTP-Posting-Host: 82.246.229.10 X-Trace: 1291557342 news-3.free.fr 7523 82.246.229.10:52831 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4440 Le 05/12/2010 01:09, Jonathan Ross a crit : > [...] > 2. The following code generates the following output: > > PROCESS > BEGIN > REPORT "Hello World!" SEVERITY NOTE; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY NOTE; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY WARNING; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY ERROR; > ASSERT 1 = 1 REPORT "1 = 1" SEVERITY FAILURE; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY NOTE; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY WARNING; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY ERROR; > ASSERT 1 = 2 REPORT "1 = 2" SEVERITY FAILURE; > WAIT; > END PROCESS; > > ISim> run > Simulator is doing circuit initialization process. > at 0 ps: Note: Hello World! (/vhdlunit/). > at 0 ps: Note: 1 = 2 (/vhdlunit/). > at 0 ps, Instance /vhdlunit/ : Warning: 1 = 2 > at 0 ps: Error: 1 = 2 > > ** Failure:1 = 2 > User(VHDL) Code Called Simulation Stop > In process VHDLUNIT.vhd:10 > > INFO: Simulator is stopped. > ISim> > > The program doesn't exit even on failure, so there's no error code for > my harness to use. Also, besides reporting or asserting with severity > failure, I can't figure out how to get it to stop. How to I control my > return code? Hi It looks like the simulator DID exit after the failure. Try to put something that the simulator would execute if it didn't exit and see what happens, instead of exiting (or not) on the last instruction. Nicolas From newsfish@newsfish Fri Feb 3 13:09:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 10:07:57 -0800 (PST) Organization: http://groups.google.com Lines: 61 Message-ID: <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291572477 23595 127.0.0.1 (5 Dec 2010 18:07:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:07:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4441 On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > [...] > > > > > > > > > > > 2. The following code generates the following output: > > > =A0 =A0 =A0PROCESS > > =A0 =A0 =A0BEGIN > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > =A0 =A0 =A0 =A0 =A0WAIT; > > =A0 =A0 =A0END PROCESS; > > > ISim> =A0run > > Simulator is doing circuit initialization process. > > at 0 ps: Note: Hello World! (/vhdlunit/). > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > at 0 ps: Error: 1 =3D 2 > > > ** Failure:1 =3D 2 > > User(VHDL) Code Called Simulation Stop > > In process VHDLUNIT.vhd:10 > > > INFO: Simulator is stopped. > > ISim> > > > The program doesn't exit even on failure, so there's no error code for > > my harness to use. Also, besides reporting or asserting with severity > > failure, I can't figure out how to get it to stop. How to I control my > > return code? > > Hi > It looks like the simulator DID exit after the failure. > Try to put something that the simulator would execute if it didn't exit > and see what happens, instead of exiting (or not) on the last instruction= . > > Nicolas Actually, the simulator is still on. The iSim> prompt means it didn't exit to the Xilinx TCL shell, which has a %> or so prompt. That said, it does STOP at the failure. I need it to exit so I can get an exit code to tell me whether it failed or not by the launching application/ script. From newsfish@newsfish Fri Feb 3 13:09:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!c39g2000yqi.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 10:24:43 -0800 (PST) Organization: http://groups.google.com Lines: 47 Message-ID: <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 74.72.162.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291573483 682 127.0.0.1 (5 Dec 2010 18:24:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:24:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c39g2000yqi.googlegroups.com; posting-host=74.72.162.230; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4442 On Dec 4, 9:58=A0pm, KJ wrote: > On Dec 4, 1:57=A0pm, Jonathan Ross > wrote: > > > > > There was no warning. It's a highly repeatable issue. It probably went > > undiscovered because it doesn't occur if you set a value during reset > > - only if you initialize a value. > > The only place you should ever consider using an initial value is in > the shift register that synchronizes an external reset signal to a > clock. =A0You shouldn't use initial values anywhere else. =A0You likely > have no control over when the clock starts up relative to the design > coming alive which means you have no way of guaranteeing setup/hold > times are met on that very first clock cycle. =A0That's why you should > always design in an explicit reset...and why you found that it 'works' > for you when you do that. > > > The workaround we finally came up with was to use a function to > > produce a one-hot encoding for the string argument of enum_encoding. > > When it doesn't detect simulation it produces a binary encoding > > instead. > > When you have the solution and found that it works (i.e. using an > explicit reset) then why would you even consider a workaround? > > As I mentioned before, any time you try to make simulation different > from synthesis you're starting down a bad path. =A0That bad path will > end up biting you in the rear eventually if you continue to follow it. > > KJ We tend to use a lot of initial values and have never had trouble with them in hardware - only in simulation (due to the off-by-one error). I see what you're saying, though either the Xilinx tools or board must be compensating for it or I'd expect we'd have been bitten by it by now (we've been doing this for a long time and never seen an issue). We use initial values instead of reset whenever there's no harm running the process during RESET with the hope of shortening logic paths. That said, you're right. I'm now deeply worried we've been getting lucky. Does anyone know about this in detail? We use Virtex-6 chips and we've been doing our initial development on the ML605 board from Xilinx. Are we going to have a catastrophic failure when we move to our production board? From newsfish@newsfish Fri Feb 3 13:09:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!h22g2000vbr.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Sun, 5 Dec 2010 10:36:28 -0800 (PST) Organization: http://groups.google.com Lines: 69 Message-ID: References: NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291574189 7703 127.0.0.1 (5 Dec 2010 18:36:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:36:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h22g2000vbr.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13561 comp.lang.verilog:2706 comp.lang.vhdl:4443 Great, thanks for sharing. I have set up an FPGA project organization which ended up quite similar to yours. The build dir is introducing (to me) a new level which seems to be a good idea, we used sim, synt, par dirs in paralell to the src, doc etc. We don't have the products dir, instead products (of specific revisions) are manually archived on a separate archive server. Also our constraint files have been lying in the synt ans par dirs, but I like the Idea of just removing the entire build dir to do a clean. However I also kind of like to do "cd synt; make" (or "make -C synt") to get the synthesis done. So I need to keep at least the makefile when doing a clean. Often the project has several "products" built from the same sources, e.g. a "board_test" bit file for production tests, and possibly some bit file to develop or debug a specific part or function of the board. Further down the road you may end up with having to support different FPGAs (i.e different speed grades/ sizes). Another aspect is when using the project as a submodule, you may want to be able to publish several variants (16/32, master/slave, etc.) All this made us come up with the concept of a "component" of a module (for the lack of a better word (component is probably the most overloaded word in HW design)). In our system a module may have several components, e.g. "board_test", "ddr_debug", "small_fpga" etc. During build: Usually there are many warnings in the log files of quite different severity. An approach I have taken is to view the log file as the primary goal in the makefile (for both sim, synt and par). Or actually a filtered log file obtained by running a (bash) script using "grep -v" to remove "known and accepted" warnings. Nothing should be left after the filter has worked on the file. The filter also does some simple statistics such as reporting the number of warnings filtered out etc. The filter is setup with a specific "component" control file that lists all acceptable warnings. This control file is also an excellent place to document why specific warnings are acceptable. So e.g. the (synt result) .edi file is obtained as a side effect of wanting a filtered synthesis log file. The filter can have make fail if wished (we currently don't do that). So the directories we have at the module level is src/ synt/ sim/ par/ doc/ submodule_1/ and design/ "make -C src" will compile (for simulation) all src code including any generated "macros" from the fpga vendor "make -C sim" will run a set of batchmode simulations generating filtered log files which can be inspected. "make -C synt my_comp" will synt the component my_comp (or actaully aim to generate my_comp's filtered log file) "make -C par my_comp" will {build; map; par; trace} my_comp by [again] aim for a filtered log file. "make all" in the module top will do all four steps above. Finally in design/ we keep all build scripts and makefiles and a file to setup the environment, i.e. paths to all tools used. In that way we also check in which tools and their versions that were used for a given project at a given time. One thing I have noted is that implementing "make help" in each directory has made the system much more user friendly. -- Pontus From newsfish@newsfish Fri Feb 3 13:09:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!e20g2000vbx.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 10:41:47 -0800 (PST) Organization: http://groups.google.com Lines: 72 Message-ID: <4568ed0c-4e6d-4868-a468-a806616e2a79@e20g2000vbx.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291574507 6628 127.0.0.1 (5 Dec 2010 18:41:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 18:41:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbx.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4444 On Dec 5, 7:07=A0pm, Jonathan Ross wrote: > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > [...] > > > > 2. The following code generates the following output: > > > > =A0 =A0 =A0PROCESS > > > =A0 =A0 =A0BEGIN > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > =A0 =A0 =A0END PROCESS; > > > > ISim> =A0run > > > Simulator is doing circuit initialization process. > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > at 0 ps: Error: 1 =3D 2 > > > > ** Failure:1 =3D 2 > > > User(VHDL) Code Called Simulation Stop > > > In process VHDLUNIT.vhd:10 > > > > INFO: Simulator is stopped. > > > ISim> > > > > The program doesn't exit even on failure, so there's no error code fo= r > > > my harness to use. Also, besides reporting or asserting with severity > > > failure, I can't figure out how to get it to stop. How to I control m= y > > > return code? > > > Hi > > It looks like the simulator DID exit after the failure. > > Try to put something that the simulator would execute if it didn't exit > > and see what happens, instead of exiting (or not) on the last instructi= on. > > > Nicolas > > Actually, the simulator is still on. The iSim> prompt means it didn't > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > it does STOP at the failure. I need it to exit so I can get an exit > code to tell me whether it failed or not by the launching application/ > script. Instead of just doing "run" I do "run; exit" which does what you want, at least for modelsim/riviera. The simulation will stop at "failure" (configurable, you can stop at warning if you wish). Simulation will also stop when there are no more scheduled events, so by stopping your clock you will stop the sim. HTH -- Pontus From newsfish@newsfish Fri Feb 3 13:09:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 11:01:45 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291575705 18041 127.0.0.1 (5 Dec 2010 19:01:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:01:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4445 On Dec 5, 1:07=A0pm, Jonathan Ross wrote: > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > [...] > > > > 2. The following code generates the following output: > > > > =A0 =A0 =A0PROCESS > > > =A0 =A0 =A0BEGIN > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE; > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > =A0 =A0 =A0END PROCESS; > > > > ISim> =A0run > > > Simulator is doing circuit initialization process. > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > at 0 ps: Error: 1 =3D 2 > > > > ** Failure:1 =3D 2 > > > User(VHDL) Code Called Simulation Stop > > > In process VHDLUNIT.vhd:10 > > > > INFO: Simulator is stopped. > > > ISim> > > > > The program doesn't exit even on failure, so there's no error code fo= r > > > my harness to use. Also, besides reporting or asserting with severity > > > failure, I can't figure out how to get it to stop. How to I control m= y > > > return code? > > > Hi > > It looks like the simulator DID exit after the failure. > > Try to put something that the simulator would execute if it didn't exit > > and see what happens, instead of exiting (or not) on the last instructi= on. > > > Nicolas > > Actually, the simulator is still on. The iSim> prompt means it didn't > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > it does STOP at the failure. I need it to exit so I can get an exit > code to tell me whether it failed or not by the launching application/ > script. As Pontus says, you can use a command in ISim to exit the program after it ends the simulation run. But that doesn't tell your program why it exited. Is there a simulation result available at the ISim command line that could be used as an exit condition for the program? Rick From newsfish@newsfish Fri Feb 3 13:09:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z20g2000pra.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 11:12:22 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291576342 24184 127.0.0.1 (5 Dec 2010 19:12:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:12:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z20g2000pra.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4446 On Dec 5, 1:24=A0pm, Jonathan Ross wrote: > On Dec 4, 9:58=A0pm, KJ wrote: > > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > wrote: > > > > There was no warning. It's a highly repeatable issue. It probably wen= t > > > undiscovered because it doesn't occur if you set a value during reset > > > - only if you initialize a value. > > > The only place you should ever consider using an initial value is in > > the shift register that synchronizes an external reset signal to a > > clock. =A0You shouldn't use initial values anywhere else. =A0You likely > > have no control over when the clock starts up relative to the design > > coming alive which means you have no way of guaranteeing setup/hold > > times are met on that very first clock cycle. =A0That's why you should > > always design in an explicit reset...and why you found that it 'works' > > for you when you do that. > > > > The workaround we finally came up with was to use a function to > > > produce a one-hot encoding for the string argument of enum_encoding. > > > When it doesn't detect simulation it produces a binary encoding > > > instead. > > > When you have the solution and found that it works (i.e. using an > > explicit reset) then why would you even consider a workaround? > > > As I mentioned before, any time you try to make simulation different > > from synthesis you're starting down a bad path. =A0That bad path will > > end up biting you in the rear eventually if you continue to follow it. > > > KJ > > We tend to use a lot of initial values and have never had trouble with > them in hardware - only in simulation (due to the off-by-one error). I > see what you're saying, though either the Xilinx tools or board must > be compensating for it or I'd expect we'd have been bitten by it by > now (we've been doing this for a long time and never seen an issue). > We use initial values instead of reset whenever there's no harm > running the process during RESET with the hope of shortening logic > paths. > > That said, you're right. I'm now deeply worried we've been getting > lucky. Does anyone know about this in detail? We use Virtex-6 chips > and we've been doing our initial development on the ML605 board from > Xilinx. Are we going to have a catastrophic failure when we move to > our production board? I'm not clear on what your reset concept is. It used to be that the tools did not use initializations in synthesis. I believe now that many of them do. The values used in the initialization is imposed on registers coming out of configuration and if the GSR is connected externally, this will give the same result. Check with your synthesis vendor to find out if initialization is supported. However... The issue with using GSR is not asserting it, but removing it. The GSR path is slow and if your clock is running and any clock enables are asserted different registers are released at different clock cycles than others. This can result in state machines ending up in invalid states, counters at wrong initial counts, etc. In essence, your synchronous logic is out of sync! There are many ways to deal with this. Often various parts of the design will do nothing until some condition enables them. These parts don't need to be changed unless there is a way they can be enabled when GSR is released. If any parts of the design need to be held in reset and released on the same clock cycle, then you need a sync reset on those portions. You can do this on a section by section basis so that you don't have one sync reset driving the entire design. Or you can use one common sync reset to the entire design which will most likely be replicated anyway. But this should be coded as a sync reset, not an async reset. Rick From newsfish@newsfish Fri Feb 3 13:09:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j9g2000vbl.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 11:57:44 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291579064 22309 127.0.0.1 (5 Dec 2010 19:57:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 19:57:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000vbl.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4447 On Dec 5, 2:01=A0pm, rickman wrote: > On Dec 5, 1:07=A0pm, Jonathan Ross > wrote: > > > > > > > > > > > On Dec 5, 8:55=A0am, Nicolas Matringe wrote: > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > > [...] > > > > > 2. The following code generates the following output: > > > > > =A0 =A0 =A0PROCESS > > > > =A0 =A0 =A0BEGIN > > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNING= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILURE= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNING= ; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR; > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILURE= ; > > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > > =A0 =A0 =A0END PROCESS; > > > > > ISim> =A0run > > > > Simulator is doing circuit initialization process. > > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > > at 0 ps: Error: 1 =3D 2 > > > > > ** Failure:1 =3D 2 > > > > User(VHDL) Code Called Simulation Stop > > > > In process VHDLUNIT.vhd:10 > > > > > INFO: Simulator is stopped. > > > > ISim> > > > > > The program doesn't exit even on failure, so there's no error code = for > > > > my harness to use. Also, besides reporting or asserting with severi= ty > > > > failure, I can't figure out how to get it to stop. How to I control= my > > > > return code? > > > > Hi > > > It looks like the simulator DID exit after the failure. > > > Try to put something that the simulator would execute if it didn't ex= it > > > and see what happens, instead of exiting (or not) on the last instruc= tion. > > > > Nicolas > > > Actually, the simulator is still on. The iSim> prompt means it didn't > > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > > it does STOP at the failure. I need it to exit so I can get an exit > > code to tell me whether it failed or not by the launching application/ > > script. > > As Pontus says, you can use a command in ISim to exit the program > after it ends the simulation run. =A0But that doesn't tell your program > why it exited. =A0Is there a simulation result available at the ISim > command line that could be used as an exit condition for the > program? > > Rick I'm not quite following - perhaps because I'm not sure what's meant by "simulation result." Is there some object that iSim is aware of or can be made aware of, or is this terminology colloquial? I'm open to making any changes needed - in fact I won't be using ASSERT for this (I'm going to follow the xUnit pattern and make my results openly available at vhdlunit.org). From newsfish@newsfish Fri Feb 3 13:09:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!z17g2000prz.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 12:22:19 -0800 (PST) Organization: http://groups.google.com Lines: 99 Message-ID: <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291580539 4049 127.0.0.1 (5 Dec 2010 20:22:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 20:22:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000prz.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4448 On Dec 5, 2:12=A0pm, rickman wrote: > On Dec 5, 1:24=A0pm, Jonathan Ross > wrote: > > > > > > > > > > > On Dec 4, 9:58=A0pm, KJ wrote: > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > > wrote: > > > > > There was no warning. It's a highly repeatable issue. It probably w= ent > > > > undiscovered because it doesn't occur if you set a value during res= et > > > > - only if you initialize a value. > > > > The only place you should ever consider using an initial value is in > > > the shift register that synchronizes an external reset signal to a > > > clock. =A0You shouldn't use initial values anywhere else. =A0You like= ly > > > have no control over when the clock starts up relative to the design > > > coming alive which means you have no way of guaranteeing setup/hold > > > times are met on that very first clock cycle. =A0That's why you shoul= d > > > always design in an explicit reset...and why you found that it 'works= ' > > > for you when you do that. > > > > > The workaround we finally came up with was to use a function to > > > > produce a one-hot encoding for the string argument of enum_encoding= . > > > > When it doesn't detect simulation it produces a binary encoding > > > > instead. > > > > When you have the solution and found that it works (i.e. using an > > > explicit reset) then why would you even consider a workaround? > > > > As I mentioned before, any time you try to make simulation different > > > from synthesis you're starting down a bad path. =A0That bad path will > > > end up biting you in the rear eventually if you continue to follow it= . > > > > KJ > > > We tend to use a lot of initial values and have never had trouble with > > them in hardware - only in simulation (due to the off-by-one error). I > > see what you're saying, though either the Xilinx tools or board must > > be compensating for it or I'd expect we'd have been bitten by it by > > now (we've been doing this for a long time and never seen an issue). > > We use initial values instead of reset whenever there's no harm > > running the process during RESET with the hope of shortening logic > > paths. > > > That said, you're right. I'm now deeply worried we've been getting > > lucky. Does anyone know about this in detail? We use Virtex-6 chips > > and we've been doing our initial development on the ML605 board from > > Xilinx. Are we going to have a catastrophic failure when we move to > > our production board? > > I'm not clear on what your reset concept is. =A0It used to be that the > tools did not use initializations in synthesis. =A0I believe now that > many of them do. =A0The values used in the initialization is imposed on > registers coming out of configuration and if the GSR is connected > externally, this will give the same result. =A0Check with your synthesis > vendor to find out if initialization is supported. =A0However... > > The issue with using GSR is not asserting it, but removing it. =A0The > GSR path is slow and if your clock is running and any clock enables > are asserted different registers are released at different clock > cycles than others. =A0This can result in state machines ending up in > invalid states, counters at wrong initial counts, etc. =A0In essence, > your synchronous logic is out of sync! > > There are many ways to deal with this. =A0Often various parts of the > design will do nothing until some condition enables them. =A0These parts > don't need to be changed unless there is a way they can be enabled > when GSR is released. =A0If any parts of the design need to be held in > reset and released on the same clock cycle, then you need a sync reset > on those portions. =A0You can do this on a section by section basis so > that you don't have one sync reset driving the entire design. =A0Or you > can use one common sync reset to the entire design which will most > likely be replicated anyway. =A0But this should be coded as a sync > reset, not an async reset. > > Rick I found the following post: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-and-Virtex-6-confi= guration-and-GSR/m-p/98892/highlight/true#M7728 All of our state machines have either no reset logic (purely initialized) or synchronous reset logic, so it sounds like we're safe. From newsfish@newsfish Fri Feb 3 13:09:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sun, 5 Dec 2010 14:46:44 -0800 (PST) Organization: http://groups.google.com Lines: 101 Message-ID: References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291589204 22887 127.0.0.1 (5 Dec 2010 22:46:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 22:46:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4449 On Dec 5, 2:57=A0pm, Jonathan Ross wrote: > On Dec 5, 2:01=A0pm, rickman wrote: > > > > > On Dec 5, 1:07=A0pm, Jonathan Ross > > wrote: > > > > On Dec 5, 8:55=A0am, Nicolas Matringe wrot= e: > > > > > Le 05/12/2010 01:09, Jonathan Ross a =E9crit : > > > > > [...] > > > > > > 2. The following code generates the following output: > > > > > > =A0 =A0 =A0PROCESS > > > > > =A0 =A0 =A0BEGIN > > > > > =A0 =A0 =A0 =A0 =A0REPORT "Hello World!" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY WARNI= NG; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY ERROR= ; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 1 REPORT "1 =3D 1" SEVERITY FAILU= RE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY NOTE; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY WARNI= NG; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY ERROR= ; > > > > > =A0 =A0 =A0 =A0 =A0ASSERT 1 =3D 2 REPORT "1 =3D 2" SEVERITY FAILU= RE; > > > > > =A0 =A0 =A0 =A0 =A0WAIT; > > > > > =A0 =A0 =A0END PROCESS; > > > > > > ISim> =A0run > > > > > Simulator is doing circuit initialization process. > > > > > at 0 ps: Note: Hello World! (/vhdlunit/). > > > > > at 0 ps: Note: 1 =3D 2 (/vhdlunit/). > > > > > at 0 ps, Instance /vhdlunit/ : Warning: 1 =3D 2 > > > > > at 0 ps: Error: 1 =3D 2 > > > > > > ** Failure:1 =3D 2 > > > > > User(VHDL) Code Called Simulation Stop > > > > > In process VHDLUNIT.vhd:10 > > > > > > INFO: Simulator is stopped. > > > > > ISim> > > > > > > The program doesn't exit even on failure, so there's no error cod= e for > > > > > my harness to use. Also, besides reporting or asserting with seve= rity > > > > > failure, I can't figure out how to get it to stop. How to I contr= ol my > > > > > return code? > > > > > Hi > > > > It looks like the simulator DID exit after the failure. > > > > Try to put something that the simulator would execute if it didn't = exit > > > > and see what happens, instead of exiting (or not) on the last instr= uction. > > > > > Nicolas > > > > Actually, the simulator is still on. The iSim> prompt means it didn't > > > exit to the Xilinx TCL shell, which has a %> or so prompt. That said, > > > it does STOP at the failure. I need it to exit so I can get an exit > > > code to tell me whether it failed or not by the launching application= / > > > script. > > > As Pontus says, you can use a command in ISim to exit the program > > after it ends the simulation run. =A0But that doesn't tell your program > > why it exited. =A0Is there a simulation result available at the ISim > > command line that could be used as an exit condition for the > > program? > > > Rick > > I'm not quite following - perhaps because I'm not sure what's meant by > "simulation result." Is there some object that iSim is aware of or can > be made aware of, or is this terminology colloquial? I'm open to > making any changes needed - in fact I won't be using ASSERT for this > (I'm going to follow the xUnit pattern and make my results openly > available at vhdlunit.org). That's why I'm asking the question, I don't know either. If there is a way to use command line functions to determine the result of the simulation... and there is a way to make ISim return an exit code on exiting, then you can make this work the way I think you want to do it. But I don't know if ISim will do either of those things. Would it be easier to have ISim save the log to a file and then read the log to get a result? Rick From newsfish@newsfish Fri Feb 3 13:09:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!u25g2000pra.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 14:49:56 -0800 (PST) Organization: http://groups.google.com Lines: 117 Message-ID: References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291589396 24517 127.0.0.1 (5 Dec 2010 22:49:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 22:49:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u25g2000pra.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4450 On Dec 5, 3:22=A0pm, Jonathan Ross wrote: > On Dec 5, 2:12=A0pm, rickman wrote: > > > > > On Dec 5, 1:24=A0pm, Jonathan Ross > > wrote: > > > > On Dec 4, 9:58=A0pm, KJ wrote: > > > > > On Dec 4, 1:57=A0pm, Jonathan Ross > > > > wrote: > > > > > > There was no warning. It's a highly repeatable issue. It probably= went > > > > > undiscovered because it doesn't occur if you set a value during r= eset > > > > > - only if you initialize a value. > > > > > The only place you should ever consider using an initial value is i= n > > > > the shift register that synchronizes an external reset signal to a > > > > clock. =A0You shouldn't use initial values anywhere else. =A0You li= kely > > > > have no control over when the clock starts up relative to the desig= n > > > > coming alive which means you have no way of guaranteeing setup/hold > > > > times are met on that very first clock cycle. =A0That's why you sho= uld > > > > always design in an explicit reset...and why you found that it 'wor= ks' > > > > for you when you do that. > > > > > > The workaround we finally came up with was to use a function to > > > > > produce a one-hot encoding for the string argument of enum_encodi= ng. > > > > > When it doesn't detect simulation it produces a binary encoding > > > > > instead. > > > > > When you have the solution and found that it works (i.e. using an > > > > explicit reset) then why would you even consider a workaround? > > > > > As I mentioned before, any time you try to make simulation differen= t > > > > from synthesis you're starting down a bad path. =A0That bad path wi= ll > > > > end up biting you in the rear eventually if you continue to follow = it. > > > > > KJ > > > > We tend to use a lot of initial values and have never had trouble wit= h > > > them in hardware - only in simulation (due to the off-by-one error). = I > > > see what you're saying, though either the Xilinx tools or board must > > > be compensating for it or I'd expect we'd have been bitten by it by > > > now (we've been doing this for a long time and never seen an issue). > > > We use initial values instead of reset whenever there's no harm > > > running the process during RESET with the hope of shortening logic > > > paths. > > > > That said, you're right. I'm now deeply worried we've been getting > > > lucky. Does anyone know about this in detail? We use Virtex-6 chips > > > and we've been doing our initial development on the ML605 board from > > > Xilinx. Are we going to have a catastrophic failure when we move to > > > our production board? > > > I'm not clear on what your reset concept is. =A0It used to be that the > > tools did not use initializations in synthesis. =A0I believe now that > > many of them do. =A0The values used in the initialization is imposed on > > registers coming out of configuration and if the GSR is connected > > externally, this will give the same result. =A0Check with your synthesi= s > > vendor to find out if initialization is supported. =A0However... > > > The issue with using GSR is not asserting it, but removing it. =A0The > > GSR path is slow and if your clock is running and any clock enables > > are asserted different registers are released at different clock > > cycles than others. =A0This can result in state machines ending up in > > invalid states, counters at wrong initial counts, etc. =A0In essence, > > your synchronous logic is out of sync! > > > There are many ways to deal with this. =A0Often various parts of the > > design will do nothing until some condition enables them. =A0These part= s > > don't need to be changed unless there is a way they can be enabled > > when GSR is released. =A0If any parts of the design need to be held in > > reset and released on the same clock cycle, then you need a sync reset > > on those portions. =A0You can do this on a section by section basis so > > that you don't have one sync reset driving the entire design. =A0Or you > > can use one common sync reset to the entire design which will most > > likely be replicated anyway. =A0But this should be coded as a sync > > reset, not an async reset. > > > Rick > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FPGA= s/Virtex-5-and-Virtex-6... > > All of our state machines have either no reset logic (purely > initialized) or synchronous reset logic, so it sounds like we're safe. Do you know if the initialized machines are init the way you want? I don't depend on init values to set my GSR state... BTW, if you think using init values somehow gets you around the GSR problem, you don't understand what I am saying. If the init values are used for synthesis, then they are used to set the GSR behavior of the registers. You then have to deal with how the register comes out of reset. Are you using an external reset of any kind? Is that the sync reset? If so, how do you activate the GSR reset for the rest of the chip? Rick From newsfish@newsfish Fri Feb 3 13:09:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 15:44:20 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291592660 19454 127.0.0.1 (5 Dec 2010 23:44:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 5 Dec 2010 23:44:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4451 On Dec 5, 3:22 pm, Jonathan Ross wrote: > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-and-Virtex-6... > > All of our state machines have either no reset logic (purely > initialized) or synchronous reset logic, so it sounds like we're safe. > I'm not seeing how you think you're safe if you have synchronous logic that depends only on initial values. The issue is not whether or not the initial values get loaded, but how the transition from configuration to user mode with a running clock happens and whether it occurs at a time which violates a setup or hold time requirement. Any flop that is part of a feedback path (such as state machines or counters) are candidates for problems; any flop that is not part of a feedback (such as a synchronizer or delay) will not be a problem. Having said that, the odds of seeing such a failure might also be rather slim since configuration generally happens only once per power cycle. So, yes you are getting lucky, but you're also not in a high probability of failure situation. Still, good design practice generally dictactes that you should not rely on initial values for two reasons: - Potential timing issues at end of configuration as just discussed - No way to have the design recover from any unusual situation without cycling power Kevin Jennings From newsfish@newsfish Fri Feb 3 13:09:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 06 Dec 2010 02:18:29 +0100 Lines: 39 Message-ID: <8m2rv5F1gdU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 52vyDVbxASav88J7u2o+UgPZohTialh9EF8MKN0yj+4xJKQLkA Cancel-Lock: sha1:X3fyOocXuN92DlBvXoXSN3nHNzM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:13564 comp.lang.verilog:2708 comp.lang.vhdl:4452 On 12/3/2010 1:32 PM, saar drimer wrote: > I've written up an (informal) draft proposal for an FPGA project > structure that could be easily extended as the project grows and is > version control friendly. I'd be grateful for any type of feedback... > > http://www.saardrimer.com/fpgaproj/ > > cheers, > saar. First of all I'd like to point out that your proposal looks consistent and in some aspects very elegant. I like the idea of having a common structured approach everyone understands and follows rigorously and methodically, in order to promote reuse and modular design. On the contrary I believe the effort becomes huge when you need to deal with FPGA vendors, since every one is pushing their own product and through their own Integrated Development Environment they tie down the designers to their own structure. As already posted, I also like the idea of cleaning a build in one go, but I think that a constraint file is pretty much different from an hdl file and collecting them under /source will make a lot of confusion, especially when you are interested in developing rtl while some other people are interested in adding constraints for the implementation. Dividing the dir tree in processes has the big advantage that even though you are the only one designer, you make your project flowing, in several reiterations, with the processes. Once you are happy with the simulation and the rtl you would move into synthesis and so on (with a good chance you need to come back to your rtl). In the end I believe that having a structure, regardless the type, is the most important thing, since nothing can be more confusing than having no organization. I sometimes stare for minutes at the list of directory names my group is creating and believe that no matter what structure you want to propose their capability to screw it up is greatly above any imagination (I still remember my very first vhdl project soon moved from directory /test to directory /final and then /reallyfinal and then /reallyfinal2...). From newsfish@newsfish Fri Feb 3 13:09:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!j18g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 18:27:38 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: <0094b499-679c-4468-a751-4c201d91fbc4@j18g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291602458 16432 127.0.0.1 (6 Dec 2010 02:27:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 02:27:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j18g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4453 On Dec 5, 6:44=A0pm, KJ wrote: > On Dec 5, 3:22 pm, Jonathan Ross > wrote: > > > > > I found the following post:http://forums.xilinx.com/t5/Virtex-Family-FP= GAs/Virtex-5-and-Virtex-6... > > > All of our state machines have either no reset logic (purely > > initialized) or synchronous reset logic, so it sounds like we're safe. > > I'm not seeing how you think you're safe if you have synchronous logic > that depends only on initial values. =A0The issue is not whether or not > the initial values get loaded, but how the transition from > configuration to user mode with a running clock happens and whether it > occurs at a time which violates a setup or hold time requirement. > > Any flop that is part of a feedback path (such as state machines or > counters) are candidates for problems; any flop that is not part of a > feedback (such as a synchronizer or delay) will not be a problem. > > Having said that, the odds of seeing such a failure might also be > rather slim since =A0configuration generally happens only once per power > cycle. =A0So, yes you are getting lucky, but you're also not in a high > probability of failure situation. =A0Still, good design practice > generally dictactes that you should not rely on initial values for two > reasons: > - Potential timing issues at end of configuration as just discussed > - No way to have the design recover from any unusual situation without > cycling power Depending on initial states does not require a power cycle. Most, if not all FPGAs can be reloaded by asserting a pin, often called PRGM or something similar. Otherwise I agree with you. Rick From newsfish@newsfish Fri Feb 3 13:09:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis Only Date: Sun, 5 Dec 2010 21:18:14 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <31f5420d-2455-488f-9e99-e2c9f021be2f@f20g2000prn.googlegroups.com> References: <3d8c2b8c-bd22-477e-a3b1-f1880ffd972d@29g2000prb.googlegroups.com> <25a543a7-328b-4515-b850-572f076ec2df@c13g2000prc.googlegroups.com> <9718277a-ae74-4b5f-8644-a25125c536de@c39g2000yqi.googlegroups.com> <60e6c5c1-2ed6-4f47-aa73-2f400b325e45@z17g2000prz.googlegroups.com> <971ace01-56e8-4122-85da-ba591aa175b5@f20g2000prn.googlegroups.com> <0094b499-679c-4468-a751-4c201d91fbc4@j18g2000prn.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291612694 17360 127.0.0.1 (6 Dec 2010 05:18:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 05:18:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4454 On Dec 5, 9:27=A0pm, rickman wrote: > Depending on initial states does not require a power cycle. =A0Most, if > not all FPGAs can be reloaded by asserting a pin, often called PRGM or > something similar. =A0Otherwise I agree with you. > > Rick You're right, I thought of that too soon after clicking on 'Send'. KJ From newsfish@newsfish Fri Feb 3 13:09:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v19g2000yqa.googlegroups.com!not-for-mail From: Kolja Sulimma Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 02:09:10 -0800 (PST) Organization: http://groups.google.com Lines: 63 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 87.155.69.23 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291630150 28217 127.0.0.1 (6 Dec 2010 10:09:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 10:09:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v19g2000yqa.googlegroups.com; posting-host=87.155.69.23; posting-account=GgLtCgoAAAD1eGcaDvWVJ6l90w-YMYMc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.10) Gecko/20100914 Firefox/3.6.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4455 comp.arch.fpga:13567 On 5 Dez., 04:55, rickman wrote: > On Dec 4, 8:05=A0pm, Jonathan Ross > wrote: > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > I suppose this is something that you need to expect, but I just have > > > never come across this before. =A0I have some concurrent logic equati= ons > > > using integers where one input common to two assignments changes and > > > because one gets updated before the other, one is set to a value that > > > is outside the range of the integer and flags an error in > > > simulation. > > > > C <=3D B - A * stuff; > > > D <=3D A + C; =A0-- A changes and puts D outside of its range until C= is > > > updated > > > > In the real world, this is not really an issue since all sorts of > > > intermediate states are expected when doing arithmetic. =A0But VHDL > > > doesn't seem to accommodate this well. =A0The only way I can think of= to > > > fix this, without changing the logic, is to do these calculations > > > inside a combinatorial process using variables. =A0Then I can control > > > the sequence of updates explicitly. > > > > The only other thing I can think is to assign A to A' and use A' in > > > place of A in the assignment for D. =A0That may still allow an error, > > > but if A'' is used, then there will be two delta delays in D > > > assignment path. =A0However, if C grows because A has shrunk, then th= at > > > could cause the same sort of out of bounds error on D. > > > > Is there another way make this work that isn't so cumbersome? > > > > Rick > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > I see what the two of you are saying. =A0By using integer it will be > tested for range bounds. =A0std_logic_vector types don't get that level > of analysis. =A0The range testing is useful when it is done properly. > By properly, I mean so that it is checking the logic, not your skill > at eliminating glitches in combinatorial logic... Use signed or unsigned from the numeric_std package and perform the range check yourself at times when you know the intermediate states have settled: if rising_edge(clk) then assert c >=3D lower_bound and c <=3D upper_bound report "C out of range"; end if; I believe that virtually all HDL-Designers should use a lot more assertions than they do. (Myself included.) Kolja From newsfish@newsfish Fri Feb 3 13:09:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m20g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 05:57:33 -0800 (PST) Organization: http://groups.google.com Lines: 75 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291643853 30138 127.0.0.1 (6 Dec 2010 13:57:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 13:57:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000prc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4456 comp.arch.fpga:13575 On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > On 5 Dez., 04:55, rickman wrote: > > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > wrote: > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > I suppose this is something that you need to expect, but I just hav= e > > > > never come across this before. =A0I have some concurrent logic equa= tions > > > > using integers where one input common to two assignments changes an= d > > > > because one gets updated before the other, one is set to a value th= at > > > > is outside the range of the integer and flags an error in > > > > simulation. > > > > > C <=3D B - A * stuff; > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range until= C is > > > > updated > > > > > In the real world, this is not really an issue since all sorts of > > > > intermediate states are expected when doing arithmetic. =A0But VHDL > > > > doesn't seem to accommodate this well. =A0The only way I can think = of to > > > > fix this, without changing the logic, is to do these calculations > > > > inside a combinatorial process using variables. =A0Then I can contr= ol > > > > the sequence of updates explicitly. > > > > > The only other thing I can think is to assign A to A' and use A' in > > > > place of A in the assignment for D. =A0That may still allow an erro= r, > > > > but if A'' is used, then there will be two delta delays in D > > > > assignment path. =A0However, if C grows because A has shrunk, then = that > > > > could cause the same sort of out of bounds error on D. > > > > > Is there another way make this work that isn't so cumbersome? > > > > > Rick > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > I see what the two of you are saying. =A0By using integer it will be > > tested for range bounds. =A0std_logic_vector types don't get that level > > of analysis. =A0The range testing is useful when it is done properly. > > By properly, I mean so that it is checking the logic, not your skill > > at eliminating glitches in combinatorial logic... > > Use signed or unsigned from the numeric_std package and perform the > range check yourself > at times when you know the intermediate states have settled: > > if rising_edge(clk) then > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > range"; > end if; > > I believe that virtually all HDL-Designers should use a lot more > assertions than they do. > (Myself included.) > > Kolja That's an interesting approach. I'm not accustomed to using assertions in my synthesizable code, but there is certainly no reason not to. Rick From newsfish@newsfish Fri Feb 3 13:09:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!matrix.darkstorm.co.uk!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!z9g2000yqz.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 06:30:03 -0800 (PST) Organization: http://groups.google.com Lines: 98 Message-ID: <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> NNTP-Posting-Host: 68.18.17.161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291645803 16647 127.0.0.1 (6 Dec 2010 14:30:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 14:30:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z9g2000yqz.googlegroups.com; posting-host=68.18.17.161; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4457 comp.arch.fpga:13579 On Dec 6, 8:57=A0am, rickman wrote: > On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > > > > > > > On 5 Dez., 04:55, rickman wrote: > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > > wrote: > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > > I suppose this is something that you need to expect, but I just h= ave > > > > > never come across this before. =A0I have some concurrent logic eq= uations > > > > > using integers where one input common to two assignments changes = and > > > > > because one gets updated before the other, one is set to a value = that > > > > > is outside the range of the integer and flags an error in > > > > > simulation. > > > > > > C <=3D B - A * stuff; > > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range unt= il C is > > > > > updated > > > > > > In the real world, this is not really an issue since all sorts of > > > > > intermediate states are expected when doing arithmetic. =A0But VH= DL > > > > > doesn't seem to accommodate this well. =A0The only way I can thin= k of to > > > > > fix this, without changing the logic, is to do these calculations > > > > > inside a combinatorial process using variables. =A0Then I can con= trol > > > > > the sequence of updates explicitly. > > > > > > The only other thing I can think is to assign A to A' and use A' = in > > > > > place of A in the assignment for D. =A0That may still allow an er= ror, > > > > > but if A'' is used, then there will be two delta delays in D > > > > > assignment path. =A0However, if C grows because A has shrunk, the= n that > > > > > could cause the same sort of out of bounds error on D. > > > > > > Is there another way make this work that isn't so cumbersome? > > > > > > Rick > > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > > I see what the two of you are saying. =A0By using integer it will be > > > tested for range bounds. =A0std_logic_vector types don't get that lev= el > > > of analysis. =A0The range testing is useful when it is done properly. > > > By properly, I mean so that it is checking the logic, not your skill > > > at eliminating glitches in combinatorial logic... > > > Use signed or unsigned from the numeric_std package and perform the > > range check yourself > > at times when you know the intermediate states have settled: > > > if rising_edge(clk) then > > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > > range"; > > end if; > > > I believe that virtually all HDL-Designers should use a lot more > > assertions than they do. > > (Myself included.) > > > Kolja > > That's an interesting approach. =A0I'm not accustomed to using > assertions in my synthesizable code, but there is certainly no reason > not to. > > Rick- Hide quoted text - > > - Show Iquoted text - I have not tried it, but what is below may do what you want also. signal G_sv : signed(10 downto 0); signal Signed_int : integer range -128 to 127; -- specified valid range here ................. if rising_edge(clk) then Signed_int <=3D TO_INTEGER(G_sv); end if; From newsfish@newsfish Fri Feb 3 13:09:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!o23g2000prh.googlegroups.com!not-for-mail From: Newman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 06:38:20 -0800 (PST) Organization: http://groups.google.com Lines: 107 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 68.18.17.161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291646329 21791 127.0.0.1 (6 Dec 2010 14:38:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 14:38:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o23g2000prh.googlegroups.com; posting-host=68.18.17.161; posting-account=hX5ozgoAAACr_wYCLO-8IUzNPDjrZ91p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; HPNTDF; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4458 comp.arch.fpga:13580 On Dec 6, 9:30=A0am, Newman wrote: > On Dec 6, 8:57=A0am, rickman wrote: > > > > > > > On Dec 6, 5:09=A0am, Kolja Sulimma wrote: > > > > On 5 Dez., 04:55, rickman wrote: > > > > > On Dec 4, 8:05=A0pm, Jonathan Ross > > > > wrote: > > > > > > On Dec 4, 5:32=A0pm, rickman wrote: > > > > > > > I suppose this is something that you need to expect, but I just= have > > > > > > never come across this before. =A0I have some concurrent logic = equations > > > > > > using integers where one input common to two assignments change= s and > > > > > > because one gets updated before the other, one is set to a valu= e that > > > > > > is outside the range of the integer and flags an error in > > > > > > simulation. > > > > > > > C <=3D B - A * stuff; > > > > > > D <=3D A + C; =A0-- A changes and puts D outside of its range u= ntil C is > > > > > > updated > > > > > > > In the real world, this is not really an issue since all sorts = of > > > > > > intermediate states are expected when doing arithmetic. =A0But = VHDL > > > > > > doesn't seem to accommodate this well. =A0The only way I can th= ink of to > > > > > > fix this, without changing the logic, is to do these calculatio= ns > > > > > > inside a combinatorial process using variables. =A0Then I can c= ontrol > > > > > > the sequence of updates explicitly. > > > > > > > The only other thing I can think is to assign A to A' and use A= ' in > > > > > > place of A in the assignment for D. =A0That may still allow an = error, > > > > > > but if A'' is used, then there will be two delta delays in D > > > > > > assignment path. =A0However, if C grows because A has shrunk, t= hen that > > > > > > could cause the same sort of out of bounds error on D. > > > > > > > Is there another way make this work that isn't so cumbersome? > > > > > > > Rick > > > > > > Try using either the SIGNED or UNSIGNED type instead of integer. > > > > > I see what the two of you are saying. =A0By using integer it will b= e > > > > tested for range bounds. =A0std_logic_vector types don't get that l= evel > > > > of analysis. =A0The range testing is useful when it is done properl= y. > > > > By properly, I mean so that it is checking the logic, not your skil= l > > > > at eliminating glitches in combinatorial logic... > > > > Use signed or unsigned from the numeric_std package and perform the > > > range check yourself > > > at times when you know the intermediate states have settled: > > > > if rising_edge(clk) then > > > =A0 assert c >=3D lower_bound and c <=3D upper_bound report "C out of > > > range"; > > > end if; > > > > I believe that virtually all HDL-Designers should use a lot more > > > assertions than they do. > > > (Myself included.) > > > > Kolja > > > That's an interesting approach. =A0I'm not accustomed to using > > assertions in my synthesizable code, but there is certainly no reason > > not to. > > > Rick- Hide quoted text - > > > - Show Iquoted text - > > I have not tried it, but what is below may do what you want also. > > signal G_sv =A0 =A0 =A0 =A0 =A0 =A0 : signed(10 downto 0); > signal Signed_int =A0 : integer range -128 to 127; =A0 -- specified valid > range here > ................. > > if rising_edge(clk) then > =A0 Signed_int <=3D =A0 TO_INTEGER(G_sv); > end if;- Hide quoted text - > > - Show quoted text - I might have wrongly assumed that the combinatorial result was going to be eventually registered. Oops! From newsfish@newsfish Fri Feb 3 13:09:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j29g2000yqm.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Mon, 6 Dec 2010 09:14:20 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291655661 10789 127.0.0.1 (6 Dec 2010 17:14:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 17:14:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j29g2000yqm.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4459 On Dec 5, 2:46=A0pm, rickman wrote: > > Would it be easier to have ISim save the log to a file and then read > the log to get a result? > > Rick Do what Rick says. Create a log file. At the very least, have the word PASS or FAIL appear in the log file. Eventually you will want to have something in your log file to tell you why and when the failure was detected. Hint: Assertions are your friend. RK From newsfish@newsfish Fri Feb 3 13:09:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!k14g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 10:00:23 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291658424 5046 127.0.0.1 (6 Dec 2010 18:00:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:00:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k14g2000pre.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4460 comp.arch.fpga:13589 I think I would use a function for the intermediate calculation, and then call the function in both concurrent assignment statements per the original implementation. Integers give you the benefits of bounds checking in simulation (even below the 2^n granularity if desired), and a big improvement in simulation performance, especially if integers are widely used in the design (instead of vectors). Andy From newsfish@newsfish Fri Feb 3 13:09:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!feeder4.news.weretis.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!a28g2000prb.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 10:25:38 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291659938 19774 127.0.0.1 (6 Dec 2010 18:25:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:25:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a28g2000prb.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13590 comp.lang.verilog:2709 comp.lang.vhdl:4461 Thank you Jonathan, Pontus and Alessandro for your comments and suggestions -- I will consider them for the next revision of the document. On Dec 6, 1:18=A0am, Alessandro Basili wrote: > In the end I believe that having a structure, regardless the type, is > the most important thing, since nothing can be more confusing than > having no organization. That's the main point, yes. The primary motivation for writing this specification was to provide a starting point for engineers, together with the reasoning behind the choices that I have made. Obviously, there's no way for a single structure definition to fit everyone's needs. I do think, though, that within the rigid rules of this proposal, there's enough flexibility for customization without loss of most benefits. Further comments and suggestions are welcome! cheers, saar. From newsfish@newsfish Fri Feb 3 13:09:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 10:50:39 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 216.127.159.67 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291661439 5928 127.0.0.1 (6 Dec 2010 18:50:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 18:50:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=216.127.159.67; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4462 comp.arch.fpga:13591 On Dec 6, 1:00=A0pm, Andy wrote: > I think I would use a function for the intermediate calculation, and > then call the function in both concurrent assignment statements per > the original implementation. > > Integers give you the benefits of bounds checking in simulation (even > below the 2^n granularity if desired), and a big improvement in > simulation performance, especially if integers are widely used in the > design (instead of vectors). > > Andy I know everyone says that integers run faster, but is this a significant effect? Has it been measured or at least verified on current simulators? Rick From newsfish@newsfish Fri Feb 3 13:09:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!y19g2000prb.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 12:46:54 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291668414 4135 127.0.0.1 (6 Dec 2010 20:46:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 20:46:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y19g2000prb.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13594 comp.lang.verilog:2710 comp.lang.vhdl:4463 On 6 d=E9c, 13:25, saar drimer wrote: > Thank you Jonathan, Pontus and Alessandro for your comments and > suggestions -- I will consider them for the next revision of the > document. > > On Dec 6, 1:18=A0am, Alessandro Basili > wrote: > > > In the end I believe that having a structure, regardless the type, is > > the most important thing, since nothing can be more confusing than > > having no organization. > > That's the main point, yes. The primary motivation for writing this > specification was to provide a starting point for engineers, together > with the reasoning behind the choices that I have made. Obviously, > there's no way for a single structure definition to fit everyone's > needs. I do think, though, that within the rigid rules of this > proposal, there's enough flexibility for customization without loss of > most benefits. > > Further comments and suggestions are welcome! > > cheers, > saar. I was just wondering, with your project structure, where would vendor- specific cores would fit in? Let's say I use core generator to generate a FIR filter. Coregen generates a .xco file along with .ngc, .mif .vhd (for simulation), etc. Where would you put it in your structure and what files would you add to your version control. Technically, you only need the .xco file, and maybe the .coef file the regenerate your core. However, if you have a lot of cores, it might take a lot of time to regenerate the missing core files. From newsfish@newsfish Fri Feb 3 13:09:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n2g2000pre.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 13:46:34 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <0d80e6ec-227c-4db9-958a-7fe9cadf7139@n2g2000pre.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> NNTP-Posting-Host: 86.7.19.9 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291671994 10425 127.0.0.1 (6 Dec 2010 21:46:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 21:46:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n2g2000pre.googlegroups.com; posting-host=86.7.19.9; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.04 (lucid) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13598 comp.lang.verilog:2711 comp.lang.vhdl:4464 > I was just wondering, with your project structure, where would vendor- > specific cores would fit in? Let's say I use core generator to > generate a FIR filter. Coregen generates a .xco file along > with .ngc, .mif .vhd (for simulation), etc. Where would you put it in > your structure and what files would you add to your version control. > Technically, you only need the .xco file, and maybe the .coef file the > regenerate your core. However, if you have a lot of cores, it might > take a lot of time to regenerate the missing core files. Some of this is already covered in the document; see the "build environment" section. This is the Makefile bit (I've noted that I'm inconsistent with "/source" and "/sources", and will fix it in the next revision): CGP = fifo # Generate black boxes # (Unfortunately, CoreGen will generate the core where the .cgp and # .xco files are, NOT from where it is invoked. There is no output # path directive either. Hack is to copy the source files first) %.v %.cgp: cp ../sources/blackbox/$(CGP).cgp $(SYN)/$(CGP).cgp cp ../sources/blackbox/$(CGP).xco $(SYN)/$(CGP).xco cd $(SYN) && coregen -p $(CGP).cgp -b $(CGP).xco bbox: $(SYN)/$(CGP).v $(SYN)/$(CGP).cgp I'm suggesting that the required source files (in this case, .xco and .cgp) be put in version control at "/sources/blackbox" (for a single core). An FIR filter and FIFO source files could sit in "/ sources/blackbox/fir_filter", and "/sources/blackbox/fifo", respectively. "blackbox" isn't special -- they could similarly be placed in "/sources/fir_filter", and "/sources/fifo", and the Makefile changed accordingly. Another valid option is to consider these cores as submodules with a build of their own, though I decided not to do that because these modules typically aren't significant enough to justify it. Generated files (.vhd/.v, .ngc, etc.) are placed in "/build/synthesis/ /", for example. The Makefile should know when to regenerate the required files if they are missing. Indeed, generating the .ngc files take a long time, so "/build/synthesis//" shouldn't be deleted too often... this can also be set up by the Makefile (i.e., selective clean of the various generated directories, as I have it in the example Makefile in the document for "syn" and "imp"). cheers, saar. From newsfish@newsfish Fri Feb 3 13:09:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.unit0.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!k11g2000vbf.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl Subject: Re: FPGA project structure definition Date: Mon, 6 Dec 2010 14:31:10 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: <611bf397-eb75-429c-9738-c1397e23b0d9@k11g2000vbf.googlegroups.com> References: <8m2rv5F1gdU1@mid.individual.net> <994b31b0-6f53-4bca-beb5-2065e7e5aee7@a28g2000prb.googlegroups.com> <0d80e6ec-227c-4db9-958a-7fe9cadf7139@n2g2000pre.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291674670 32051 127.0.0.1 (6 Dec 2010 22:31:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 22:31:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k11g2000vbf.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13601 comp.lang.verilog:2712 comp.lang.vhdl:4465 Considering that you may want to use a module as a submodule, parent modules will need to be able to find your submodule's generated macros (black-boxes) for their build (sim/synt/par). If you start copying files within a submodule you will not succeed cleaning it (from a parent modules view), or you need to clean the copies as well. Which one should the parent use? The original, or the copy? I found that, as long as I know where the submodule's generated items are stored, I could, for simulation, use a configuration to override paths using generics [vhdl]. For par (ngdbuild) use -sd to point out the macro. Synthesis treats it as a blackbox but I guess timing to/from the blackbox could/should be possible? In the cleaning process I excluded removing any macros (since they are quite time consuming to regenerate), however the build process still requires the macro-control-file (e.g. .xco) to be older than the macro-result-file (e.g. .mif, .ngc etc.). -- Pontus From newsfish@newsfish Fri Feb 3 13:09:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r40g2000prh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl,comp.arch.fpga Subject: Re: Concurrent Logic Timing Date: Mon, 6 Dec 2010 14:43:18 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <15b96527-d885-46dc-88a5-2d67409def46@r40g2000prh.googlegroups.com> References: <163bc849-a426-45ba-aef3-d5b5b712db25@l32g2000yqc.googlegroups.com> <19e8adab-f06f-4413-98ae-42f95c3a6edc@z9g2000yqz.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291675398 10527 127.0.0.1 (6 Dec 2010 22:43:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 6 Dec 2010 22:43:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r40g2000prh.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4466 comp.arch.fpga:13603 On Dec 6, 12:50=A0pm, rickman wrote: > On Dec 6, 1:00=A0pm, Andy wrote: > > > I think I would use a function for the intermediate calculation, and > > then call the function in both concurrent assignment statements per > > the original implementation. > > > Integers give you the benefits of bounds checking in simulation (even > > below the 2^n granularity if desired), and a big improvement in > > simulation performance, especially if integers are widely used in the > > design (instead of vectors). > > > Andy > > I know everyone says that integers run faster, but is this a > significant effect? =A0Has it been measured or at least verified on > current simulators? > > Rick A few years back, I had a design for a small FPGA with several modules on a common bus. I started out with unsigned(4 downto 0) for the address, and each module decoded its own address (each was given a generic for address and size). Then I changed only that address to a natural with equivalent range. Just that one change sped up my RTL simulation from over 2.5 hours down to less than 1 hour. I considered it very significant... Andy From newsfish@newsfish Fri Feb 3 13:09:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Tue, 07 Dec 2010 14:09:41 +0100 Lines: 35 Message-ID: <8m6q0lFdgiU1@mid.individual.net> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <4cfb99de$0$7523$426a74cc@news.free.fr> <66b27ed2-17ad-4976-a6a9-1a093ffea61b@c13g2000prc.googlegroups.com> <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /L/QUrL5u1dD0DSIH9nfmgm1gBwOw1NLA3heJNmVfGscxHH7vw Cancel-Lock: sha1:sXUWcDbTLylaOVlo8WJDpZ5JaXs= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <5cd8fed2-42ff-426d-bbd4-774329a79702@j29g2000yqm.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4467 On 12/6/2010 6:14 PM, d_s_klein wrote: > On Dec 5, 2:46 pm, rickman wrote: >> >> Would it be easier to have ISim save the log to a file and then read >> the log to get a result? >> >> Rick > > Do what Rick says. > > Create a log file. At the very least, have the word PASS or FAIL > appear in the log file. > > Eventually you will want to have something in your log file to tell > you why and when the failure was detected. > > Hint: Assertions are your friend. > > RK Maybe I haven't quite well understood the topic, but you maybe interested in this thread: http://www.velocityreviews.com/forums/t57165-how-to-stop-simulation-in-vhdl.html One of the first replies from Mike Treseler point to a broken link which you may check here: http://mysite.ncnetwork.net/reszotzl/ It gives a very good approach to testbench and once there are no scheduled transitions any longer (through done_s signal) the simulation should stop automatically. Hope that helps, Al From newsfish@newsfish Fri Feb 3 13:09:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y19g2000prb.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Using integers for counters in synthesis Date: Tue, 7 Dec 2010 17:25:40 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291771541 31238 127.0.0.1 (8 Dec 2010 01:25:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 01:25:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y19g2000prb.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4468 Hi everyone, I have a simple question. Assuming we have this process : MY_PROCESS : process(CLK) variable cnt : natural range 0 to 255; begin if rising_edge(CLK) then output_signal <= '0'; if (srst = '1') then cnt := 0; else if (cnt = 100) then output_signal <= '1'; end if; cnt := cnt + 1; end if; end if; end process; In simulation, I will get an error at the rising edge of CLK when cnt is 255. However, what happens in synthesis? Will the synthesizer add logic to prevent cnt from wrapping aroung ? Or will it simply implement the "usual" wraparound behavior? Is it synthesizer specific? Best regards. Benjamin From newsfish@newsfish Fri Feb 3 13:09:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin.stu.neva.ru!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 00:57:48 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291798668 16217 127.0.0.1 (8 Dec 2010 08:57:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 08:57:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4469 On Dec 8, 1:25=A0am, Benjamin Couillard wrote: > Hi everyone, > > I have a simple question. Assuming we have this process : > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 output_signal <=3D '0'; > =A0 =A0 if (srst =3D '1') then > =A0 =A0 =A0 cnt :=3D 0; > =A0 =A0else > =A0 =A0 if (cnt =3D 100) then > =A0 =A0 =A0 =A0output_signal <=3D '1'; > =A0 =A0end if; > =A0 =A0cnt :=3D cnt + 1; > =A0 =A0end if; > =A0 end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? > > Best regards. > > Benjamin >From my experience, counters like this will just wrap in synthesis. The error you get is more to do with the VHDL type system rather than how it works on hardware. It is one danger of the VHDL types, but it might just be safer to stick with an Unsigned type in your code. Personally, If I want wrapping behaviour I use and unsigned, but if I always reset at a specific number, Ill use an integer. From newsfish@newsfish Fri Feb 3 13:09:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 08 Dec 2010 14:28:39 +0000 Organization: TRW Conekt Lines: 65 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net VV2EIBqXTLJ6RR97mtpJlwTEhYT9/U1MOOo0aQkqNhunxpaJ4= Cancel-Lock: sha1:D3laQNeyXQdwIc3q1q7rrQU37bQ= sha1:n9tPikeuFolDr8n4UFuS/yS98x8= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4470 Benjamin Couillard writes: > Hi everyone, > > I have a simple question. Assuming we have this process : > > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > if rising_edge(CLK) then > output_signal <= '0'; > if (srst = '1') then > cnt := 0; > else > if (cnt = 100) then > output_signal <= '1'; > end if; > cnt := cnt + 1; > end if; > end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. Quite right too, you're trying to push 256 into that variable and you've said "it can't happen" when you defined the range. > However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? In theory it's completely undefined - you've told the synthesiser that that variable can't be bigger than 255, so if you try and make it so, the synthesiser is probably within its rights to generate logic that shorts the power supplies and makes magic smoke issue forth from your FPGA :) In reality, no synthesiser I know of would implement this as anything other than an 8 bit counter which wraps around. HOWEVER... in order to keep your simulation matching your synthesis (which IMHO you must do), you should either: 1) Use an unsigned vector, for which wraparound behaviour is the defined behaviour on overflow. 2) Put some explicit code in to handle the overflow - the synthesiser will spot that it is unneeded in your case, and implement the same as it would've before. As an aside - if you find yourself using a different maximum for cnt (say 200 for example), and you don't do option 2) you'll likely find the synthesiser generating an 8 bit wraparound counter which will still count up to 255, making your sim and synth completely different... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Wed, 08 Dec 2010 16:47:38 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 79 Message-ID: <4cffa89a$0$14258$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 6677cd28.news.skynet.be X-Trace: 1291823258 news.skynet.be 14258 91.177.212.228:58239 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4471 Martin Thompson wrote: > Benjamin Couillard writes: > >> Hi everyone, >> >> I have a simple question. Assuming we have this process : >> >> >> MY_PROCESS : process(CLK) >> variable cnt : natural range 0 to 255; >> begin >> if rising_edge(CLK) then >> output_signal <= '0'; >> if (srst = '1') then >> cnt := 0; >> else >> if (cnt = 100) then >> output_signal <= '1'; >> end if; >> cnt := cnt + 1; >> end if; >> end if; >> end process; >> >> In simulation, I will get an error at the rising edge of CLK when cnt >> is 255. > > Quite right too, you're trying to push 256 into that variable and > you've said "it can't happen" when you defined the range. > >> However, what happens in synthesis? Will the synthesizer add >> logic to prevent cnt from wrapping aroung ? Or will it simply >> implement the "usual" wraparound behavior? Is it synthesizer >> specific? > > In theory it's completely undefined - you've told the synthesiser that > that variable can't be bigger than 255, so if you try and make it so, > the synthesiser is probably within its rights to generate logic that > shorts the power supplies and makes magic smoke issue forth from your > FPGA :) > > In reality, no synthesiser I know of would implement this as anything > other than an 8 bit counter which wraps around. > > HOWEVER... in order to keep your simulation matching your synthesis > (which IMHO you must do), you should either: > > 1) Use an unsigned vector, for which wraparound behaviour is the > defined behaviour on overflow. > > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. I agree that you have to fix your code like that, but not for any synthesis-related reason - simply because it is wrong. The run-time bound error proves that your there is a mismatch between the model and the design intent. You would have to fix the code regardless of whether the code is synthesisable or not. > As an aside - if you find yourself using a different maximum for cnt > (say 200 for example), and you don't do option 2) you'll likely find the > synthesiser generating an 8 bit wraparound counter which will still > count up to 255, making your sim and synth completely different... Again, I find this a very dangerous way of putting it. Now newbies may think that they should avoid integers because of sim/synth mismatches, which simply do not exist. It is meaningless to talk about mismatches beyond a simulation error. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: spacewire project on opencores.org Date: Wed, 08 Dec 2010 20:10:51 +0100 Lines: 68 Message-ID: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net xBQcxxZK/74unjF3eZBr+gduyTnNoYCvxRghw8aC+o7jXisvJJ Cancel-Lock: sha1:R3tRYDHX5pfWJjDYbRXzrVXn8t4= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 Xref: feeder.eternal-september.org comp.arch.fpga:13635 comp.lang.vhdl:4472 comp.lang.verilog:2714 Hi everyone, after some struggles I have eventually found the time to revive an old project on opencores which hasn't been updated since a while: a spacewire link and router. I have just been assigned as co-maintainer since the original one seems not available since a while. I intend to bring back the status of the project to "planning", since I would like to discuss again the structure of the project, starting from the specification documentation and the overall design structure. I'd like to stress that I am not a spacewire expert, but I have been working on a "modified" version of it that is in use in the AMS-02 experiment (http://ams.cern.ch) which is ready to be launched next year on the International Space Station. At the moment I would like to share my motivation, hoping to find some feedback and some interest. The purpose of the spacewire standard is (citation from the ECSS‐E‐ST‐50‐12C): - to facilitate the construction of high‐performance on‐board data‐handling systems; - to help reduce system integration costs; - to promote compatibility between data‐handling equipment and subsystems; - to encourage reuse of data‐handling equipment across several different missions. In this respect a handful of firms have grown to provide SoC know-how and system integration capabilities to "serve" space exploration and space science. ESA for example is promoting R&D in order to improve european space industry sector. Even though I do understand the commercial impact of this approach, I still believe that we can do much more through an open platform, improving the quality of the solutions and allowing for a greater spectrum of products. In my limited experience I have been working on two space experiments (pamela.roma2.infn.it and ams.cern.ch) and witnessed other four at least (ALTEA, GLAST-FERMI, LAZIO-SiRAD, AGILE). A great deal of development was focused on the onboard data-handling systems, with ad-hoc interfaces and non-standard solutions. We had the possibility to adopt spacewire, but the "closed" solutions provided by the industry is rather counter productive in an open environment like the one of the academic collaborations we have (costs are rather high and liability is often unclear). This is where open IP cores may come in action and empower low-budget experiments to build reliable and reusable systems cutting the development costs and enabling them to focus on science. The industry itself may benefit from this approach, since a good licensing policy (like the LGPL) may foster interests and wide spread the usage (hence enhancing the reliability) of these IP cores. A more reliable and widely used standard gives a tremendous boost to our space related dreams and even though it's just a piece of wire, I believe it still build bridges worldwide. Any feedback is appreciated. Al p.s.: this post will be on opencores.org forum as well. -- Alessandro Basili CERN, PH/UGC Electronic Engineer From newsfish@newsfish Fri Feb 3 13:09:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 12:42:42 -0800 (PST) Organization: http://groups.google.com Lines: 56 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291840962 2696 127.0.0.1 (8 Dec 2010 20:42:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 20:42:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4473 On Dec 7, 6:25=A0pm, Benjamin Couillard wrote: > Hi everyone, > > I have a simple question. Assuming we have this process : > > MY_PROCESS : process(CLK) > variable cnt : natural range 0 to 255; > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 output_signal <=3D '0'; > =A0 =A0 if (srst =3D '1') then > =A0 =A0 =A0 cnt :=3D 0; > =A0 =A0else > =A0 =A0 if (cnt =3D 100) then > =A0 =A0 =A0 =A0output_signal <=3D '1'; > =A0 =A0end if; > =A0 =A0cnt :=3D cnt + 1; > =A0 =A0end if; > =A0 end if; > end process; > > In simulation, I will get an error at the rising edge of CLK when cnt > is 255. However, what happens in synthesis? Will the synthesizer add > logic to prevent cnt from wrapping aroung ? Or will it simply > implement the "usual" wraparound behavior? Is it synthesizer > specific? > > Best regards. > > Benjamin Put a modulo 256 on the counter: count : process (clk) is variable cnt : natural range 0 to 255; begin if (srst =3D '1') then cnt :=3D 0; outreg <=3D '0'; elsif rising_edge(clk) then if (cnt =3D 100) then outreg <=3D '1'; else outreg <=3D '0'; end if; cnt :=3D (cnt + 1) mod 256; end if; end process count; The synthesis tool will recognize that the modulo is just there to prevent overflow in simulation and it gets optimized away in the hardware. -a From newsfish@newsfish Fri Feb 3 13:09:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o9g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Wed, 8 Dec 2010 15:40:05 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <964571ef-a8be-4e49-b6f3-f4a031732a75@o9g2000pre.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291851605 389 127.0.0.1 (8 Dec 2010 23:40:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Dec 2010 23:40:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000pre.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4474 On Dec 8, 8:28=A0am, Martin Thompson wrote: > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. That depends on what code you put in there to "handle the overflow"... If your resulting code will not allow an overflow of the assignment, then you are removing the ambiguity caused by the illegal condition of an overflow. Absent the ambiguity, the synthesis tool will then be bound to replicate the resulting behavior, which may or may not be the same as before. A minor point: "the overflow" occurs only upon the assignment, not on the increment. It is perfectly legal to add 1 to cnt when cnt is 255 (the result is 256). What is not legal is to take that result and try to store it back into cnt! For example, (cnt + 1 > 255) is perfectly legal and meaningful with cnt: natural range 0 to 255. With cnt: unsigned (7 downto 0), it is also legal, but meaningless and will always evaluate as false. Using (cnt + 1 > 255) or (cnt - 1 < 0) as a conditional is an excellent way to efficiently detect a roll-over (by accessing the carry/borrow bit), but it only works for integer subtypes, not signed/unsigned. Andy From newsfish@newsfish Fri Feb 3 13:09:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s9g2000vby.googlegroups.com!not-for-mail From: Sebastien Bourdeauducq Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Thu, 9 Dec 2010 02:36:07 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> References: <8ma3hpF3caU1@mid.individual.net> NNTP-Posting-Host: 92.225.33.98 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1291890968 26534 127.0.0.1 (9 Dec 2010 10:36:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Dec 2010 10:36:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000vby.googlegroups.com; posting-host=92.225.33.98; posting-account=8e6pLwoAAACvu9UuLn7G--_8cF5NYx8j User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101027 Fedora/3.6.12-1.fc14 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13644 comp.lang.vhdl:4475 comp.lang.verilog:2716 On 8 d=E9c, 20:10, Alessandro Basili wrote: > after some struggles I have eventually found the time to revive an old > project on opencores which hasn't been updated since a while: I would not bother. Why not simply use GRLIB's code? http://www.gaisler.com/cms/index.php?option=3Dcom_content&task=3Dview&id=3D= 357&Itemid=3D82 While GRLIB also has some of the problems that plague most Opencores designs (namely, slowness and resource utilization through the roof), at least the cores work, are supported and are well documented. S. From newsfish@newsfish Fri Feb 3 13:09:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Thu, 09 Dec 2010 15:40:22 +0000 Organization: TRW Conekt Lines: 64 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <4cffa89a$0$14258$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net da3m/8yy0HLxFZHh9hM76wmFmonjlFo7eqTGGoTjZIzhBfBVw= Cancel-Lock: sha1:xMFtDkrll2qmnR2Ml01RgjUkuSc= sha1:DjfmncixDPDWz+Nt43MDxBjzqLU= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4476 Jan Decaluwe writes: > Martin Thompson wrote: >> HOWEVER... in order to keep your simulation matching your synthesis >> (which IMHO you must do), you should either: >> >> 1) Use an unsigned vector, for which wraparound behaviour is the >> defined behaviour on overflow. >> >> 2) Put some explicit code in to handle the overflow - the synthesiser >> will spot that it is unneeded in your case, and implement the same as >> it would've before. > > I agree that you have to fix your code like that, but not for any > synthesis-related reason - simply because it is wrong. The run-time > bound error proves that your there is a mismatch between the model > and the design intent. Yes - I didn't mean to imply it was for a synthesis-related issue. The question asked what would happen - I answered. Then followed up with: >> HOWEVER... in order to keep your simulation matching your synthesis >> (which IMHO you must do), you should either: the implication of "you must do" was intended to be "it's wrong without it" - but I can see it might not be strong enough. Or maybe I should've written "to keep your simulation matching your design intent". > You would have to fix the code regardless > of whether the code is synthesisable or not. > Well, yes, if the simulation is dying like that, something is wrong. I read the question (accurately or not!) to be more "it'll die in sim, but I reckon it'll be alright in the real hardware, do I need to bother with it?" - to which I was trying to say "YES!" > >> As an aside - if you find yourself using a different maximum for cnt >> (say 200 for example), and you don't do option 2) you'll likely find the >> synthesiser generating an 8 bit wraparound counter which will still >> count up to 255, making your sim and synth completely different... > > Again, I find this a very dangerous way of putting it. Now newbies > may think that they should avoid integers because of sim/synth > mismatches, which simply do not exist. Well, that certainly wasn't my intent, sorry! > It is meaningless to talk about mismatches beyond a simulation > error. Yes - assuming your simulation is good enough to show the error. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Thu, 09 Dec 2010 16:41:57 +0100 Lines: 30 Message-ID: <8mcbm2F5foU1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net uBd6bqOpBbGwdwq/emJs7A3TbFQLosmBNX6fUavDdyfW0LsIW3 Cancel-Lock: sha1:Z6ySQ/u2ouFxOYY03WGqmIYR5xw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <2b2d89db-837d-404a-8c8d-1234e069c1cb@s9g2000vby.googlegroups.com> Xref: feeder.eternal-september.org comp.arch.fpga:13648 comp.lang.vhdl:4477 comp.lang.verilog:2717 On 12/9/2010 11:36 AM, Sebastien Bourdeauducq wrote: > On 8 dc, 20:10, Alessandro Basili wrote: >> after some struggles I have eventually found the time to revive an old >> project on opencores which hasn't been updated since a while: > > I would not bother. Why not simply use GRLIB's code? > http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=357&Itemid=82 > While GRLIB also has some of the problems that plague most Opencores > designs (namely, slowness and resource utilization through the roof), > at least the cores work, are supported and are well documented. > > S. I believe you are referring to the gpl package and not to the copyrighted version. I don't quite believe you would have so much support (at least from them) unless you get the proprietary one and secondly the GRLIB promotes the AMBA bus as SoC, which is a rather complex bus compared to the Wishbone. IMHO GRLIB is a great effort to provide a fully integrated system on chip (either FPGA or ASIC) that I do not dare to achieve (or compete against). On the contrary my intent is to have a simple enough IP Core which can be easily integrated and reused in order to promote the protocol. But I do appreciate your comment and I will consider the possibility to publish only the spacewire part out of the whole library, maybe stripping off the amba interface, even though I need to evaluate the licensing issue. Al From newsfish@newsfish Fri Feb 3 13:09:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Thu, 09 Dec 2010 15:42:19 +0000 Organization: TRW Conekt Lines: 32 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <964571ef-a8be-4e49-b6f3-f4a031732a75@o9g2000pre.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net hvrGXpKpXMP2HDOQ5u18JQIWHq8unE6ZdRd5dm1REd2o++Djs= Cancel-Lock: sha1:j5SdB/igIWnckirD/T0OS6zcNRY= sha1:a9bly7p2+5/9528fp4W1LpEb3RA= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4478 Andy writes: > On Dec 8, 8:28am, Martin Thompson wrote: >> 2) Put some explicit code in to handle the overflow - the synthesiser >> will spot that it is unneeded in your case, and implement the same as >> it would've before. > > That depends on what code you put in there to "handle the overflow"... > OK, yes - assuming the code you put in there makes it wrap around to zero (which is what I meant by "in your case") > If your resulting code will not allow an overflow of the assignment, > then you are removing the ambiguity caused by the illegal condition of > an overflow. Absent the ambiguity, the synthesis tool will then be > bound to replicate the resulting behavior, which may or may not be the > same as before. > Yes, if you make it saturate for example, the synthesiser (of course) will add logic to replicate your saturation requirement. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p38g2000vbn.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Fri, 10 Dec 2010 06:57:43 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <8ma3hpF3caU1@mid.individual.net> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1291993063 29419 127.0.0.1 (10 Dec 2010 14:57:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 14:57:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p38g2000vbn.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:13667 comp.lang.vhdl:4479 comp.lang.verilog:2718 On 8 Dez., 20:10, Alessandro Basili wrote: > after some struggles I have eventually found the time to revive an old > project on opencores which hasn't been updated since a while: > > a spacewire link and router. > [..] > > Any feedback is appreciated. I think spacewire is not the best example for open cores (At least unless you manage to get ESA as co-supporter which is unlikely as ESA has allready spacewire cores). Open cores tend to have a lack in documentation and verification, which is a no-go for developing space electronics. Even if you target on public science projects it is very likely that you need to ensure the "space-readiness" in many aspects for a core before you can use it. For spacewire interface I consider the effort to proof the quality of a core clearly exceeding the effort for writting the core for your own. Are you firm with developing according to ECSS-Q 60 02? I would expect a core development to be complaint to this before using it without further quality checking in case of the core not beeing provided from ESA for a ESA project. In case of detailed questions you may also conntact me by sending an email. You should change the receive-address to thomas @domain_from_email when replying. best regards Thomas From newsfish@newsfish Fri Feb 3 13:09:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!postnews.google.com!v23g2000vbi.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 13:13:14 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> NNTP-Posting-Host: 83.188.231.12 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292015594 3792 127.0.0.1 (10 Dec 2010 21:13:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 21:13:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v23g2000vbi.googlegroups.com; posting-host=83.188.231.12; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4480 Consider the following system: inp_clk -- Input clock to FPGA (Xilinx Spartan 3A DSP) -- directly routed to DCM -- PERIOD constraint attached to it -- Frequency: 125 MHz clk_25 -- CLKDV_OUT from DCM -- Frequency: 25 MHz clk_28 -- CLKFX_OUT from DCM -- Frequency: inp_clk*7/31 MHz clk_250k -- Output from a VHDL-module that divides the clk_25 with 100 -- Frequency: 250 kHz CTRL_PROC : process (clk_250k) begin if rising_edge(clk_250k) then if reset =3D '1' then reg1 <=3D '0'; else if byte_received =3D '1' then if data_in =3D =9310101010=94 then reg1 <=3D '1'; else reg1 <=3D '0'; end if; end if; end if; end if; end process; CNT_PROC : process (clk_28) begin if rising_edge(clk_28) then if reset =3D '1' then cnt <=3D (others =3D> =910=92); else if reg1 =3D '1' then cnt <=3D cnt + 1; else cnt <=3D cnt - 1; end if; end if; end if; end process; reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it is crossing clock domains. Do I need to worry about that in the above situation and apply some asynchronous clock domain techniques? I=92m asking since the two clocks actually are related to each other. So, main question: When are two clock domains actually considered asynchronous? Some related questions. How does ISE/XST handle the situation? As I understand the Xilinx software automatically derives a new PERIOD for each of the DCM output clocks and determines the clock relationships between the output clock domains. There will probably be moments where the edges of the two clocks are so close that the timing won=92t be met. Do I need to insert a FALSE PATH constraint in this case? And, last question, should I put the clk_250k on a global clock path? Regards Beppe From newsfish@newsfish Fri Feb 3 13:09:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o4g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 14:28:13 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292020093 11120 127.0.0.1 (10 Dec 2010 22:28:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Dec 2010 22:28:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000yqd.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4481 On Dec 10, 4:13=A0pm, Beppe wrote: > Consider the following system: > > inp_clk =A0 -- Input clock to FPGA (Xilinx Spartan 3A DSP) > =A0 =A0 =A0 =A0 =A0 -- directly routed to DCM > =A0 =A0 =A0 =A0 =A0 -- PERIOD constraint attached to it > =A0 =A0 =A0 =A0 =A0 -- Frequency: 125 MHz > > clk_25 =A0 =A0-- CLKDV_OUT from DCM > =A0 =A0 =A0 =A0 =A0 -- Frequency: 25 MHz > > clk_28 =A0 =A0-- CLKFX_OUT from DCM > =A0 =A0 =A0 =A0 =A0 -- Frequency: inp_clk*7/31 MHz > > clk_250k =A0 -- Output from a VHDL-module that divides the clk_25 with > 100 clk_250k will be a problem in an FPGA. In an FPGA environment, you basically almos never want to generate a clock with logic. Even when it comes out of a flip flop you're most likely doomed. > =A0 =A0 =A0 =A0 =A0 -- Frequency: 250 kHz > > CTRL_PROC : process (clk_250k) > begin > =A0if rising_edge(clk_250k) then Yep...doomed > =A0 end if; > =A0end if; > end process; > > CNT_PROC : process (clk_28) > begin > =A0if rising_edge(clk_28) then > =A0 if reset =3D '1' then > =A0 =A0cnt <=3D (others =3D> =910=92); > =A0 else > =A0 =A0if reg1 =3D '1' then > =A0 =A0 cnt <=3D cnt + 1; > =A0 =A0else > =A0 =A0 cnt <=3D cnt - 1; > =A0 =A0end if; > =A0 end if; > =A0end if; > end process; > > reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it > is crossing clock domains. Do I need to worry about that in the above > situation and apply some asynchronous clock domain techniques? Yes and no. - Since you created two clocks, then yes you should treat them as if they are unrelated. - What you should do is generate a clock enable for rather than a clock for the 250k. Then both processes are running in the same clock domain...no clock crossings at all. Instead of this... process(clk_250k) begin if rising_edge(clk_250k) then ... end if; end process; Do this... process(clk) begin if rising_edge(clk) then if (clkenable_250k) then ... end if; end if; end process; Where clkenable_250k is generated by your VHDL code to be exactly one clock cycle in your 0 to 99 counter. > > And, last question, should I put the clk_250k on a global clock path? > No...because you should be getting rid of it as a clock and using it as a clock enable instead. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:09:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Are HDLs Misguided? Date: Fri, 10 Dec 2010 20:25:58 -0800 (PST) Organization: http://groups.google.com Lines: 44 Message-ID: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 76.100.125.243 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292041558 6417 127.0.0.1 (11 Dec 2010 04:25:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 04:25:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=76.100.125.243; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4482 Sometimes I wonder if HDLs are really the right way to go. I mainly use VHDL which we all know is a pig in many ways with its verbosity and arcane type conversion gyrations. But what bothers me most of all is that I have to learn how to tell the tools in their "language" how to construct the efficient logic I can picture in my mind. By "language" I don't mean the HDL language, but actually the specifics of a given inference tool. What I mean is, if I want a down counter that uses the carry out to give me an "end of count" flag, why can't I get that in a simple and clear manner? It seems like every time I want to design a circuit I have to experiment with the exact style to get the logic I want and it often is a real PITA to make that happen. For example, I wanted a down counter that would end at 1 instead of 0 for the convenience of the user. To allow a full 2^N range, I thought it could start at zero and run for the entire range by wrapping around to 2^N-1. I had coded the circuit using a natural range 0 to (2^N)-1. I did the subtraction as a simple assignment foo <= foo -1; I fully expected that even if it were flagged as an error in simulation to load a 0 and let it count "down" to (2^N)-1, it would work in the real world since I stop the down counter when it gets to 1, not zero. Loading a zero in an N bit counter would work just fine wrapping around. But to make the simulation the same as the real hardware I expected to get, I thought adding some simple code to handle the wrap around might be good. So the assignment was done modulo 2^N. But the synthesis size blew up to nearly double the size without the "mod" function added, mostly additional adders! I didn't have time to explore what caused this so I just left out the modulo operation and will live with what I get for the case of loading a zero starting value. I guess what I am trying to say is I would like to be able to specify detailed logic rather than generically coding the function and letting a tool try to figure out how to implement it. This should be possible without the issues of instantiating logic (vendor specific, clumsy, hard to read...). In an ideal design world, shouldn't it be pretty easy to infer logic and to actually know what logic to expect? Rick From newsfish@newsfish Fri Feb 3 13:09:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z19g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 10 Dec 2010 20:44:33 -0800 (PST) Organization: http://groups.google.com Lines: 120 Message-ID: <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> NNTP-Posting-Host: 76.100.125.243 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292042673 15819 127.0.0.1 (11 Dec 2010 04:44:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 04:44:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000yqb.googlegroups.com; posting-host=76.100.125.243; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4483 I can't say I totally agree with the doom and gloom predictions of KJ... On Dec 10, 5:28 pm, KJ wrote: > On Dec 10, 4:13 pm, Beppe wrote: > > > Consider the following system: > > > inp_clk -- Input clock to FPGA (Xilinx Spartan 3A DSP) > > -- directly routed to DCM > > -- PERIOD constraint attached to it > > -- Frequency: 125 MHz > > > clk_25 -- CLKDV_OUT from DCM > > -- Frequency: 25 MHz > > > clk_28 -- CLKFX_OUT from DCM > > -- Frequency: inp_clk*7/31 MHz > > > clk_250k -- Output from a VHDL-module that divides the clk_25 with > > 100 > > clk_250k will be a problem in an FPGA. In an FPGA environment, you > basically almos never want to generate a clock with logic. Even when > it comes out of a flip flop you're most likely doomed. I agree that generating a clock from a counter is not a good idea. But it is not a fatal flaw if handled correctly. But you are better off using a clock enable unless there is a reason. > > -- Frequency: 250 kHz > > > CTRL_PROC : process (clk_250k) > > begin > > if rising_edge(clk_250k) then > > Yep...doomed Isn't that a bit dramatic? If the tools properly recognize this signal as a clock and routes it on a clock spline, and you treat it as a separate clock with no clear timing relation to the clock it is generated from, then there shouldn't be any problem. Actually, I have seen the tools not use a clock spline and they seem to handle it correctly, recognizing it as a clock but routing it on the local interconnect. > > end if; > > end if; > > end process; > > > CNT_PROC : process (clk_28) > > begin > > if rising_edge(clk_28) then > > if reset =3D '1' then > > cnt <=3D (others =3D> =910=92); > > else > > if reg1 =3D '1' then > > cnt <=3D cnt + 1; > > else > > cnt <=3D cnt - 1; > > end if; > > end if; > > end if; > > end process; > > > reg1 is assigned a value in CTRL_PROC and read in CNT_PROC and thus it > > is crossing clock domains. Do I need to worry about that in the above > > situation and apply some asynchronous clock domain techniques? > > Yes and no. > - Since you created two clocks, then yes you should treat them as if > they are unrelated. > - What you should do is generate a clock enable for rather than a > clock for the 250k. Then both processes are running in the same clock > domain...no clock crossings at all. > > Instead of this... > process(clk_250k) > begin > if rising_edge(clk_250k) then > ... > end if; > end process; > > Do this... > process(clk) > begin > if rising_edge(clk) then > if (clkenable_250k) then > ... > end if; > end if; > end process; > > Where clkenable_250k is generated by your VHDL code to be exactly one > clock cycle in your 0 to 99 counter. > > > > > And, last question, should I put the clk_250k on a global clock path? > > No...because you should be getting rid of it as a clock and using it > as a clock enable instead. I don't think you can easily put a signal on a global clock line. If the tools recognize it as a clock, because it drives the clock input of a FF, it will consider if it needs to use a global clock line to control skew. If so it will use one. If not it won't. There are times when you don't want to use an enable. A design I did generates a clock enable to control some circuitry. But the input and output of the data signals need to be done on the actual clock edges to optimize the setup and hold times of the external signals. So the data input and output are run through a FF clocked by the clock I am generating and then I deal with the data timing as required. Rick From newsfish@newsfish Fri Feb 3 13:09:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: process vs instance Date: Fri, 10 Dec 2010 22:40:16 -0800 Lines: 58 Message-ID: <4D031CD0.2070208@gmail.com> References: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net fdigJyMlKz9awAEpnwqKMQExZ7MiiCwCukM77t9xgCdwshk3Ql Cancel-Lock: sha1:VpnHtKbBCsHcMjFx3107WAqR7bM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <8ma3hpF3caU1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4484 On Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote: > Dear Mr. Treseler, > few years ago I followed quite closely the comp.arch.fpga and comp.lang.vhdl > groups and I was fascinated by your template project especially the > testbench style, that I adopted since then. ... > Talking about your template, how do you see multiple component instantiation > and port mapping, as opposed to your procedural template? My top entity is a collection of direct instances of single process entities with port maps. I use the Quartus rtl viewer to draw a block diagram from my functional code. I use a template to simplify the synthesis of variables. > I believe that component instantiation offers a black-box view pretty much > like a schematic entry and it's easy to me to follow, while I don't have > that picture through your procedural template. Am I missing something? I agree at the top level. I like to see the wired view, but I let quartus draw it for me. I also click on on one of the top blocks on the rtl viewer to verify the structural view of my procedural entity. > Do you think a single process, as opposed to many of them, will simplify the > datapath and allow for better maintainance of the code? I instance single process entities at the top level. I prefer to connect large boxes at the port map level to connecting processes at the architecture level. > What is the gain of having variables as opposed to signals? I can write functional/procedural code for synthesis using standard vhdl source code. > I am very used > to signals since I always though that the way values are assigned to a > signal follow pretty much what happens on hardware, while for a variable > there is an abstraction that I am not accustomed to. I am very used to writing, siming and tracing code descriptions with immediate assignments, and letting synthesis sort out the LUTs and flops using my template. > I hope I haven't bother you too much with my questions. > Best regards, > > Al Not a bother in the least. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:09:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder7.xlned.com!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 11 Dec 2010 14:53:40 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 65 Message-ID: <4d038263$0$14246$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b1451aab.news.skynet.be X-Trace: 1292075619 news.skynet.be 14246 91.177.205.212:59992 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4485 rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. > > What I mean is, if I want a down counter that uses the carry out to > give me an "end of count" flag, why can't I get that in a simple and > clear manner? It seems like every time I want to design a circuit I > have to experiment with the exact style to get the logic I want and it > often is a real PITA to make that happen. > > For example, I wanted a down counter that would end at 1 instead of 0 > for the convenience of the user. To allow a full 2^N range, I thought > it could start at zero and run for the entire range by wrapping around > to 2^N-1. I had coded the circuit using a natural range 0 to > (2^N)-1. I did the subtraction as a simple assignment > > foo <= foo -1; > > I fully expected that even if it were flagged as an error in > simulation to load a 0 and let it count "down" to (2^N)-1, it would > work in the real world since I stop the down counter when it gets to > 1, not zero. Loading a zero in an N bit counter would work just fine > wrapping around. > > But to make the simulation the same as the real hardware I expected to > get, I thought adding some simple code to handle the wrap around might > be good. So the assignment was done modulo 2^N. But the synthesis > size blew up to nearly double the size without the "mod" function > added, mostly additional adders! I didn't have time to explore what > caused this so I just left out the modulo operation and will live with > what I get for the case of loading a zero starting value. Ok. So you didn't have time to explore the issue, but you have all the time in world to write a lengthy post spreading FUD and jumping to all kinds of Big Conclusions? There, as is commonly known, no reason why modulo a power of 2 (hint) would generate additional hardware, and there is overwhelming evidence that decent synthesis tools do this just right. Therefore, if you think you see this, the proper reaction is to be very intruigued and switch to fanatic bug-hunting mode. Do that please (or trick others into doing it for you). Chances are that we will not here about the issue again. All the rest is a waste of everybody's time. > I guess what I am trying to say is I would like to be able to specify > detailed logic rather than generically coding the function and letting > a tool try to figure out how to implement it. This should be possible > without the issues of instantiating logic (vendor specific, clumsy, > hard to read...). In an ideal design world, shouldn't it be pretty > easy to infer logic and to actually know what logic to expect? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin2!goblin.stu.neva.ru!news.karotte.org!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 11 Dec 2010 10:20:17 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Sat, 11 Dec 2010 16:21:24 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <1k87g6pgurrcujr2hnhjl8pb6q5see2jj5@4ax.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 45 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-GSNjZRqf6evFBIDgh/5Eq6IkdmYnGd+XCcK7HlTo2fVEbY97uVFA8QaN42TuxzwPywtM47fs855h09v!zarDXlLP+4bU9NPt4YlXl0+bdZRogvW18MIfhU9qb1RirFjC7xqgk3gX6+CVgTtult7PMkjEqhab!BxM= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2542 Xref: feeder.eternal-september.org comp.lang.vhdl:4486 On Tue, 7 Dec 2010 17:25:40 -0800 (PST), Benjamin Couillard wrote: >Hi everyone, > >I have a simple question. Assuming we have this process : > > >MY_PROCESS : process(CLK) >variable cnt : natural range 0 to 255; >begin > if rising_edge(CLK) then > output_signal <= '0'; > if (srst = '1') then > cnt := 0; > else > if (cnt = 100) then > output_signal <= '1'; > end if; > cnt := cnt + 1; > end if; > end if; >end process; > >In simulation, I will get an error at the rising edge of CLK when cnt >is 255. As you should. Wrapping round is always an error in integer arithmetic. (Relying on that error is ... IMO, not best practice) If you want wrapround from 255 to 0, you want a modular type - as others point out, numeric_std.unsigned meets your needs. Or you could make the wrapround explicit using the "mod" operator. This is more flexible since the "mod" value can be something other than 256. >However, what happens in synthesis? Anything at all, since you have presumably fixed the error during simulation ;-) Conventionally, synthesis tools will treat the error condition as a "don't care" and implement the smallest (or fastest) logic they can ... which may even be exactly what you wanted. Or not... - Brian From newsfish@newsfish Fri Feb 3 13:09:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m37g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 08:29:50 -0800 (PST) Organization: http://groups.google.com Lines: 65 Message-ID: <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292084990 3473 127.0.0.1 (11 Dec 2010 16:29:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 16:29:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m37g2000vbn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4487 On Dec 10, 11:44=A0pm, rickman wrote: > I can't say I totally agree with the doom and gloom predictions of > KJ... > > clk_250k will be a problem in an FPGA. =A0In an FPGA environment, you > > basically almos never want to generate a clock with logic. =A0Even when > > it comes out of a flip flop you're most likely doomed. > > I agree that generating a clock from a counter is not a good idea. > But it is not a fatal flaw if handled correctly. =A0 The only way to 'handle it correctly' will be to treat it as an independent clock domain and design in clock domain crossing logic. Without that, you'll be running into hold time issues with any signal originating from the high speed clock domain that enters the generated clock domain. You can't do anything about those issues except re- route, cross your fingers and hope. Yes you can hand hold a design and get it to work, but before you do so there should be a compelling reason to do so. No such reason was posted. > > > CTRL_PROC : process (clk_250k) > > > begin > > > =A0if rising_edge(clk_250k) then > > > Yep...doomed > > Isn't that a bit dramatic? =A0 No. I would characterize the OP's odds of success as 'low'. At best, he would find that he is never able to get the design working right out of the shoot, abandon the approach and will end up with more knowledge. That would be a good outcome. At worst, the design would be going into production when there starts to become a growing pile of boards that seem to have a 'temperature sensitivity' or 'date code issue'. What is your definition of 'doomed'? >If the tools properly recognize this > signal as a clock and routes it on a clock spline, and you treat it as > a separate clock with no clear timing relation to the clock it is > generated from, But the OP clearly doesn't know this if you read the post. > > There are times when you don't want to use an enable. =A0A design I did > generates a clock enable to control some circuitry. =A0But the input and > output of the data signals need to be done on the actual clock edges > to optimize the setup and hold times of the external signals. =A0So the > data input and output are run through a FF clocked by the clock I am > generating and then I deal with the data timing as required. > But in those situations, you don't have any logic being implemented in the clock domain crossing as was in the OP. In the posted code, the signals reset, byte_received and data_in probably originate in some other domain and are crossing; reg1, as noted by the OP definitely does come from a foreign clock domain and is not treated properly. The clock domain crossing looks like this... Synced_To_Clock_Signal <=3D Synced_To_Other_Clock_Signal when rising_edge(Clock); Kevin Jennings From newsfish@newsfish Fri Feb 3 13:09:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!border1.nntp.ams2.giganews.com!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 11 Dec 2010 10:43:39 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sat, 11 Dec 2010 16:44:46 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 44 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-deJum5YTwWOHmAr2P5K7+r30UAm12RCnH79DJpoi+rmHrr5FaK/wdCV6IdcV4xCMQ1ivb0fyHMEcXlX!ha9xzeUibLjHhV8GOiKnL2vuuRlH2ULz8lU58nvwUhtd/8r/s0QDL/1dBio6vznWrMe4C5wTMKfd!/18= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3139 Xref: feeder.eternal-september.org comp.lang.vhdl:4488 On Fri, 10 Dec 2010 20:25:58 -0800 (PST), rickman wrote: >Sometimes I wonder if HDLs are really the right way to go. I mainly >use VHDL which we all know is a pig in many ways with its verbosity >and arcane type conversion gyrations. I usually find that the gyrations are a hint to step back and see what aspect of the design I have missed... I end up needing a few, but YMMV. > But what bothers me most of all >is that I have to learn how to tell the tools in their "language" how >to construct the efficient logic I can picture in my mind. By >"language" I don't mean the HDL language, but actually the specifics >of a given inference tool. > >What I mean is, if I want a down counter that uses the carry out to >give me an "end of count" flag, why can't I get that in a simple and >clear manner? Here the issue appears to be how to get at the carry out of a counter... the syntax of integer arithmetic doesn't provide an easy way to do that by default, in any language I know (other than assembler for pre-RISC CPUs, with their flag registers). It seems to me that you have two choices ... (1) implement an n-bit counter, and augment it in some way to recreate the carry out (unfortunately you are fighting the synthesis tool in the process) (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and trust the synthesis tool to eliminate the excess flip-flop at the optimisation stage... I am willing to guess the second approach would be simpler. Even if the obvious optimisation doesn't happen (and I bet it does) it's worth asking if your design is sensitive to the cost of that FF. Can you boil down what you are trying to do (and doesn't work) into a test case? > In an ideal design world, shouldn't it be pretty >easy to infer logic and to actually know what logic to expect? I would say so. And I'm still hoping to live to see it! - Brian From newsfish@newsfish Fri Feb 3 13:09:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 12:43:12 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> NNTP-Posting-Host: 83.188.245.33 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292100195 5473 127.0.0.1 (11 Dec 2010 20:43:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 20:43:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=83.188.245.33; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4489 Thanks for the answers. An enable won=92t solve the problem of crossing clock domains. With an enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC would still be clocked by clk_28. clk_28 =3D 35/31*clk_25. I=92m aware of the problem with logic generated clocks, but I hope that Rick is right here. Putting the clock on a low skew global clock net should be enough to ensure that hold and setup times are met. Actually, when synthesizing the design, XST infers a BUFG on the clk_250k, as you predicted Rick, and the design seems to be working fine in hardware although I haven=92t made any extensive tests yet. I was first thinking that it would be okay to put the clk_250k on a non-dedicated clock net because of its low frequency, but the frequency doesn=92t matter here if I=92m right when rethinking it. The output of a flip-flop (as a result of the flip-flop being clocked by a clock edge) could be propagating to the next flip-flop before the same clock edge clocks the next flip-flop and thus leading to a hold time violation no matter the frequency. Right? On a side note, a solution for clocks with excessive skew (on non- global clock nets) should be to alternate between positive and negative clock edges on every other register. That would cut the performance by half, but if it=92s applied on low frequency clocks it doesn=92t really matter. Is this a no, no technique or would I be fine using it? As for the original question I guess I could simply find the minimum distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is what ISE/XST should do if I understand the documentation correctly). That time would be the =93new=94 timing constraint. If it=92s impossible to meet this new timing I need to use asynchronous clock domain techniques, otherwise it would be just fine. > In the posted code, the > signals reset, byte_received and data_in probably originate in some > other domain and are crossing; reg1, as noted by the OP definitely > does come from a foreign clock domain and is not treated properly. data_in and byte_received are registers clocked by clk_250k and originate from a MIDI UART. The clk_250k frequency is eight times the 31.25 kbaud rate of the MIDI interface and used to retrieve the asynchronous serial MIDI data. Beppe From newsfish@newsfish Fri Feb 3 13:09:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: process vs instance Date: Sat, 11 Dec 2010 22:13:26 +0100 Lines: 80 Message-ID: <8mi7rkFue0U1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> <4D031CD0.2070208@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 43OlmDpPQbTr9OvVGCiMKwQ4+x4tZAcgFU9t2AMKsgUG64gY+g Cancel-Lock: sha1:e4N4O8yXrYabNgb37o6Oc3nX1QA= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <4D031CD0.2070208@gmail.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4490 On 12/11/2010 7:40 AM, Mike Treseler wrote: > On Fri, Dec 10, 2010 at 4:42 PM, alessandro basili wrote: > > Dear Mr. Treseler, > > few years ago I followed quite closely the comp.arch.fpga and > comp.lang.vhdl > > groups and I was fascinated by your template project especially the > > testbench style, that I adopted since then. > ... > > Talking about your template, how do you see multiple component > instantiation > > and port mapping, as opposed to your procedural template? > > > My top entity is a collection of direct > instances of single process entities with port maps. Understood. Indeed one of my biggest problem is where to put the boundaries of a component to allow for reusability. But I got your point of having top levels (which may as well be part of a bigger project) populated only by components instantiation through port mapping, while hiding the logic as much as possible. > I use the Quartus rtl viewer to draw a block diagram > from my functional code. Do you know of any open-source software capable of doing that? > > > I believe that component instantiation offers a black-box view pretty > much > > like a schematic entry and it's easy to me to follow, while I don't have > > that picture through your procedural template. Am I missing something? > > I agree at the top level. > I like to see the wired view, but I let quartus draw it for me. > I also click on on one of the top blocks on the rtl viewer > to verify the structural view of my procedural entity. > Actually this is the hardest part for me. If I see pretty well the single flops and gates in a multi-process and concurrent assignments style, I lack the overall structure view and most of the time I need to draw down (what I call "paper simulation") the datapath. Indeed your template collects all the flops and the assignments in one single tidy place. procedure template_v_rst is -- My default. begin -- a_rst is logically equivalent if reset = '1' then -- Assumes synched trailing edge reset pulse init_regs; -- reg_v := init_c; Variables only, ports below. elsif rising_edge(clock) then update_regs; -- reg_v := f(reg_v);Variables only, ports below. end if; -- Synchronous init optional (state_v = idle_c) update_ports; -- will infer port wires ok for reset and clock end procedure template_v_rst; -- out_port <= reg_v; ports only, -- no signals which is only saying that a reset will initialize all the registers and the clock will update them all, instead of doing this for every single flop/register/counter in the architecture. > > What is the gain of having variables as opposed to signals? > > I can write functional/procedural code for synthesis > using standard vhdl source code. > Apologize but I didn't get your answer. What do you mean with functional/procedural code? and what is standard vhdl? Is there a non-standard vhdl? > > I hope I haven't bother you too much with my questions. > > Best regards, > > > > Al > > Not a bother in the least. > > -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:09:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: jacko Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sat, 11 Dec 2010 13:21:57 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <733eea6c-b8b0-4809-9073-5e6910ac9aca@f20g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 188.28.106.60 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292102517 30991 127.0.0.1 (11 Dec 2010 21:21:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 21:21:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=188.28.106.60; posting-account=kZanLQoAAABvNhBbAlX1SsCxeprjdiHJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; InfoPath.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4491 On 11 Dec, 04:25, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. =A0But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. I find the tools wierd sometimes, but they have their own style for logic minimization. Like I only considered doubling the memory size by having two routines to do 2 hi bits of jump, and then use bytes instead of 16 bit words. Strange but it also makes the hardware smaller!! I have also been considering using preseting special values in the cycle before a general load, instead of an if/else in the same cycle. I also think the hardest part is specifying to the sythesis tool, how external memory supplies a result after an access delay, and how to make this delay relative to the synthesized fmax., not just in ns. Cheers Jacko From newsfish@newsfish Fri Feb 3 13:09:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: process vs instance Date: Sat, 11 Dec 2010 14:53:19 -0800 Lines: 99 Message-ID: <4D0400DF.6050507@gmail.com> References: <8ma3hpF3caU1@mid.individual.net> <4D031CD0.2070208@gmail.com> <8mi7rkFue0U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net gfP35MmZWq9MZ4V2b8v75gSz+1HyUyKAqChRWDQqqTCFLzJQb+ Cancel-Lock: sha1:3uQJHZi1PCNwClKr2M0lyjuUMYc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <8mi7rkFue0U1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4492 On 12/11/2010 1:13 PM, Alessandro Basili wrote: >> > Talking about your template, how do you see multiple component >> instantiation >> > and port mapping, as opposed to your procedural template? >> My top entity is a collection of direct >> instances of single process entities with port maps. > > Understood. Indeed one of my biggest problem is where to put the > boundaries of a component to allow for reusability. But I got your point > of having top levels (which may as well be part of a bigger project) > populated only by components instantiation through port mapping, while > hiding the logic as much as possible. That's it. Note that direct instances do not require a component declaration. >> I use the Quartus rtl viewer to draw a block diagram >> from my functional code. > Do you know of any open-source software capable of doing that? No, but the free version of quartus/modelsim has it. That is a good starting point for a trial design. >> > I believe that component instantiation offers a black-box view pretty >> much >> > like a schematic entry and it's easy to me to follow, while I don't >> have >> > that picture through your procedural template. Am I missing something? >> I agree at the top level. >> I like to see the wired view, but I let quartus draw it for me. >> I also click on on one of the top blocks on the rtl viewer >> to verify the structural view of my procedural entity. > Actually this is the hardest part for me. If I see pretty well the > single flops and gates in a multi-process and concurrent assignments > style, I lack the overall structure view and most of the time I need to > draw down (what I call "paper simulation") the datapath. Imagine a vhdl description of the muxes and registers in this schematic of a register stack: http://mysite.ncnetwork.net/reszotzl/stack.pdf Now compare that description to the 13 lines of code in the update_regs procedure here: http://mysite.ncnetwork.net/reszotzl/stack.vhd > Indeed your template collects all the flops and the assignments in one > single tidy place. Yes. That's the idea. > procedure template_v_rst is -- My default. > begin -- a_rst is logically equivalent > if reset = '1' then -- Assumes synched trailing edge reset pulse > init_regs; -- reg_v := init_c; Variables only, ports below. > elsif rising_edge(clock) then > update_regs; -- reg_v := f(reg_v);Variables only, ports below. > end if; -- Synchronous init optional (state_v = idle_c) > update_ports; -- will infer port wires ok for reset and clock > end procedure template_v_rst; -- out_port <= reg_v; ports only, > -- no signals > > which is only saying that a reset will initialize all the registers and > the clock will update them all, instead of doing this for every single > flop/register/counter in the architecture. Yes, I still have to write the 3 procedures and run a sim to check them, but note that the stack code is working on an abstract array of 32 bit registers. >> > What is the gain of having variables as opposed to signals? >> >> I can write functional/procedural code for synthesis >> using standard vhdl source code. >> > > Apologize but I didn't get your answer. What do you mean with > functional/procedural code? Code using variables, functions and procedures for hardware synthesis. > Is there a > non-standard vhdl? There are functional languages based on c or python that can *generate* vhdl code. That is different than just using vhdl source code to do the same thing. Good luck. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:09:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!k3g2000vbp.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sat, 11 Dec 2010 14:57:27 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <0c238b88-4be4-49bb-8aba-d82ba72af2b1@k3g2000vbp.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 83.188.245.33 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292108248 12319 127.0.0.1 (11 Dec 2010 22:57:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Dec 2010 22:57:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000vbp.googlegroups.com; posting-host=83.188.245.33; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4493 > (Hm, exactly this is > what ISE/XST should do if I understand the documentation correctly). And it does. Another good reason for using clock enables in this particular case (and probably in other cases as well) and not the derived clock is that XST sees the relationship between clk_25 and clk_28 when a source register is clocked by the first and the destination register is clocked by the second. A test (not with the exact processes above) reveals this. Timing report: Slack: -5.319ns (requirement =96 (data path - clock path skew + uncertainty)) Source: test_cnt_1 (FF) Destination: led_2 (FF) Requirement: 1.140ns Data Path Delay: 6.059ns (Levels of Logic =3D 10) (Component delays alone exceeds constraint) Clock Path Skew: -0.400ns (1.832 - 2.232) Source Clock: clk_25 rising at 1169000.000ns Destination Clock: clk_28 rising at 1169001.140ns Clock Uncertainty: 0.000ns So, the minimum distance is 1.140 ns and that=92s the new requirement, which of course is not met. /B From newsfish@newsfish Fri Feb 3 13:09:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p38g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Sun, 12 Dec 2010 00:31:19 -0800 (PST) Organization: http://groups.google.com Lines: 76 Message-ID: <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292142679 31976 127.0.0.1 (12 Dec 2010 08:31:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 08:31:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p38g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4494 On Dec 8, 9:28=A0am, Martin Thompson wrote: > Benjamin Couillard writes: > > Hi everyone, > > > I have a simple question. Assuming we have this process : > > > MY_PROCESS : process(CLK) > > variable cnt : natural range 0 to 255; > > begin > > =A0 =A0if rising_edge(CLK) then > > =A0 =A0 output_signal <=3D '0'; > > =A0 =A0 if (srst =3D '1') then > > =A0 =A0 =A0 cnt :=3D 0; > > =A0 =A0else > > =A0 =A0 if (cnt =3D 100) then > > =A0 =A0 =A0 =A0output_signal <=3D '1'; > > =A0 =A0end if; > > =A0 =A0cnt :=3D cnt + 1; > > =A0 =A0end if; > > =A0 end if; > > end process; > > > In simulation, I will get an error at the rising edge of CLK when cnt > > is 255. > > Quite right too, you're trying to push 256 into that variable and > you've said "it can't happen" when you defined the range. =A0 > > > However, what happens in synthesis? Will the synthesizer add > > logic to prevent cnt from wrapping aroung ? Or will it simply > > implement the "usual" wraparound behavior? Is it synthesizer > > specific? > > In theory it's completely undefined - you've told the synthesiser that > that variable can't be bigger than 255, so if you try and make it so, > the synthesiser is probably within its rights to generate logic that > shorts the power supplies and makes magic smoke issue forth from your > FPGA :) > > In reality, no synthesiser I know of would implement this as anything > other than an 8 bit counter which wraps around. > > HOWEVER... in order to keep your simulation matching your synthesis > (which IMHO you must do), you should either: > > 1) Use an unsigned vector, for which wraparound behaviour is the > defined behaviour on overflow. > > 2) Put some explicit code in to handle the overflow - the synthesiser > will spot that it is unneeded in your case, and implement the same as > it would've before. > > As an aside - if you find yourself using a different maximum for cnt > (say 200 for example), and you don't do option 2) you'll likely find the > synthesiser generating an 8 bit wraparound counter which will still > count up to 255, making your sim and synth completely different... How exactly would my simulation be different from synthesis if I used a max of 200 for a counter? If my simulation tries to increment the counter past 200 it stops! That would not be an issue of different results, that would be my simulation failing to complete! If my usage of the counter never pushes it past 200, then the simulation and synth match. I think people are making far too big of an issue about this. An HDL is supposed to be describing hardware, hence the name HDL. If you take the position that the simulation and synthesis should always match 10% you can never design anything real. If I have a counter that is only needed for values of 200 or less and I don't care what happens when the value is over 200, then case 2 is perfectly ok. The OP has not responded, but I think he is just asking what the synthesizer does. I don't think his issue is about what the "correct" thing to do is. Rick From newsfish@newsfish Fri Feb 3 13:09:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s4g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sun, 12 Dec 2010 01:15:31 -0800 (PST) Organization: http://groups.google.com Lines: 86 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292145331 23151 127.0.0.1 (12 Dec 2010 09:15:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:15:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s4g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4495 On Dec 11, 11:44=A0am, Brian Drummond wrote: > On Fri, 10 Dec 2010 20:25:58 -0800 (PST), rickman wrot= e: > >Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > >use VHDL which we all know is a pig in many ways with its verbosity > >and arcane type conversion gyrations. > > I usually find that the gyrations are a hint to step back and see what as= pect of > the design I have missed... I end up needing a few, but YMMV. > > > But what bothers me most of all > >is that I have to learn how to tell the tools in their "language" how > >to construct the efficient logic I can picture in my mind. By > >"language" I don't mean the HDL language, but actually the specifics > >of a given inference tool. > > >What I mean is, if I want a down counter that uses the carry out to > >give me an "end of count" flag, why can't I get that in a simple and > >clear manner? =A0 > > Here the issue appears to be how to get at the carry out of a counter... > the syntax of integer arithmetic doesn't provide an easy way to do that b= y > default, in any language I know (other than assembler for pre-RISC CPUs, = with > their flag registers). Well, no, I'm not trying to force the tool to generate a carry out since I am not using it for anything. I just want a simple counter and logic to make it detect a final count value of 1. I am pretty sure I would have gotten that from my original code. But I also want the counter to roll over to zero at the max value of the counter which will give me a max count range of 2**N by specifying a value of 0 in the limit register. To use the carry out for the final count detection I would have to require the user to program M-1 rather than programming M or 0 for max M. > It seems to me that you have two choices ... > (1) implement an n-bit counter, and augment it in some way to recreate th= e carry > out (unfortunately you are fighting the synthesis tool in the process) > > (2) implement an n+1 bit counter, with the excess bit assigned to the car= ry, and > trust the synthesis tool to eliminate the excess flip-flop at the optimis= ation > stage... > > I am willing to guess the second approach would be simpler. Even if the o= bvious > optimisation doesn't happen (and I bet it does) it's worth asking if your= design > is sensitive to the cost of that FF. > > Can you boil down what you are trying to do (and doesn't work) into a tes= t case? Jan doesn't get what I am saying. I'm not that worried about the particulars of this case. I am just lamenting that everything I do in an HDL is about describing the behavior of the logic and not actually describing the logic itself. I am an old school hardware designer. I cut my teeth on logic in TO packages, hand soldering the wire leads. I still think in terms of the hardware, not the software to describe the hardware. Many of my designs need to be efficient in terms of hardware used and so I have to waste time learning how to get what I want from the tools. Sometimes I just get tired of having to work around the tools rather than with them. > > In an ideal design world, shouldn't it be pretty > >easy to infer logic and to actually know what logic to expect? > > I would say so. And I'm still hoping to live to see it! I'm not sure I will still be working then if it ever happens. As hardware becomes more and more cost efficient, I think there is less incentive to make the tools hardware efficient. I guess speed that will always be important and minimal hardware is usually the fastest. But that's not the case when the tools are doing the optimization. I recently reduced my LUT count 20% by changing the optimization from speed to area. Rick From newsfish@newsfish Fri Feb 3 13:09:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m11g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Sun, 12 Dec 2010 01:19:09 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <5de904da-a2c3-4dc9-9633-dde231b88cf9@m11g2000vbs.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <733eea6c-b8b0-4809-9073-5e6910ac9aca@f20g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292145550 17441 127.0.0.1 (12 Dec 2010 09:19:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:19:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m11g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4496 On Dec 11, 4:21=A0pm, jacko wrote: > I also think the hardest part is specifying to the sythesis tool, how > external memory supplies a result after an access delay, and how to > make this delay relative to the synthesized fmax., not just in ns. I'm not sure what you are trying to do, but you should be able to specify a delay in terms of your target fmax. Just define a set of constants that calculate the values you want. I assume you mean a delay value to use in simulation such as a <=3D b after x ns? Rick From newsfish@newsfish Fri Feb 3 13:09:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i18g2000yqn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 01:28:39 -0800 (PST) Organization: http://groups.google.com Lines: 87 Message-ID: <8f1566a6-4f98-4f8e-94bb-05c6f0dacea2@i18g2000yqn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292146119 29777 127.0.0.1 (12 Dec 2010 09:28:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 09:28:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000yqn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4497 On Dec 11, 11:29=A0am, KJ wrote: > On Dec 10, 11:44=A0pm, rickman wrote: > > > I can't say I totally agree with the doom and gloom predictions of > > KJ... > > > clk_250k will be a problem in an FPGA. =A0In an FPGA environment, you > > > basically almos never want to generate a clock with logic. =A0Even wh= en > > > it comes out of a flip flop you're most likely doomed. > > > I agree that generating a clock from a counter is not a good idea. > > But it is not a fatal flaw if handled correctly. =A0 > > The only way to 'handle it correctly' will be to treat it as an > independent clock domain and design in clock domain crossing logic. > Without that, you'll be running into hold time issues with any signal > originating from the high speed clock domain that enters the generated > clock domain. =A0You can't do anything about those issues except re- > route, cross your fingers and hope. =A0Yes you can hand hold a design > and get it to work, but before you do so there should be a compelling > reason to do so. =A0No such reason was posted. I expect there are tons of facts involve that he didn't post. Why not assume the guy has a brain in his head and discuss the issue without being extreme about it? > > > > CTRL_PROC : process (clk_250k) > > > > begin > > > > =A0if rising_edge(clk_250k) then > > > > Yep...doomed > > > Isn't that a bit dramatic? =A0 > > No. =A0I would characterize the OP's odds of success as 'low'. =A0At best= , > he would find that he is never able to get the design working right > out of the shoot, abandon the approach and will end up with more > knowledge. =A0That would be a good outcome. =A0At worst, the design would > be going into production when there starts to become a growing pile of > boards that seem to have a 'temperature sensitivity' or 'date code > issue'. > > What is your definition of 'doomed'? > > >If the tools properly recognize this > > signal as a clock and routes it on a clock spline, and you treat it as > > a separate clock with no clear timing relation to the clock it is > > generated from, > > But the OP clearly doesn't know this if you read the post. I think you are missing the point. The OP is asking the question. Of course he doesn't "know" for sure that he has to treat the new clock as an independent clock, otherwise he wouldn't be asking the question. But clearly he is aware of the issues involved. So yes, "doomed" is being overly dramatic. > > There are times when you don't want to use an enable. =A0A design I did > > generates a clock enable to control some circuitry. =A0But the input an= d > > output of the data signals need to be done on the actual clock edges > > to optimize the setup and hold times of the external signals. =A0So the > > data input and output are run through a FF clocked by the clock I am > > generating and then I deal with the data timing as required. > > But in those situations, you don't have any logic being implemented in > the clock domain crossing as was in the OP. =A0In the posted code, the > signals reset, byte_received and data_in probably originate in some > other domain and are crossing; reg1, as noted by the OP definitely > does come from a foreign clock domain and is not treated properly. > > The clock domain crossing looks like this... > > Synced_To_Clock_Signal <=3D Synced_To_Other_Clock_Signal when > rising_edge(Clock); > > Kevin Jennings Yes, the OP is asking if he needs to add that sort of code. The answer is "yes". No need to say his design is "doomed" or otherwise be dramatic about it. If the guy didn't have a clue, he wouldn't have asked the question. Rick From newsfish@newsfish Fri Feb 3 13:09:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 02:01:13 -0800 (PST) Organization: http://groups.google.com Lines: 113 Message-ID: <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292148074 14857 127.0.0.1 (12 Dec 2010 10:01:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 10:01:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4498 On Dec 11, 3:43 pm, Beppe wrote: > Thanks for the answers. > > An enable won=92t solve the problem of crossing clock domains. With an > enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC > would still be clocked by clk_28. clk_28 =3D 35/31*clk_25. > > I=92m aware of the problem with logic generated clocks, but I hope that > Rick is right here. Putting the clock on a low skew global clock net > should be enough to ensure that hold and setup times are met. > Actually, when synthesizing the design, XST infers a BUFG on the > clk_250k, as you predicted Rick, and the design seems to be working > fine in hardware although I haven=92t made any extensive tests yet. Don't count on the fact that the design works on your lab bench as proof that it works in any real sense! You can never prove a design works by testing it!!! You can only use test to prove that a design doesn't work. To prove that it works requires that you test all possible conditions and that's not really possible much less practical. > I was first thinking that it would be okay to put the clk_250k on a > non-dedicated clock net because of its low frequency, but the > frequency doesn=92t matter here if I=92m right when rethinking it. The > output of a flip-flop (as a result of the flip-flop being clocked by a > clock edge) could be propagating to the next flip-flop before the same > clock edge clocks the next flip-flop and thus leading to a hold time > violation no matter the frequency. Right? > > On a side note, a solution for clocks with excessive skew (on non- > global clock nets) should be to alternate between positive and > negative clock edges on every other register. That would cut the > performance by half, but if it=92s applied on low frequency clocks it > doesn=92t really matter. Is this a no, no technique or would I be fine > using it? Yes, I think you understand the issue here. I've never considered using a low speed clock in this manner, but I expect it would work ok as long as you account for ***ALL*** possible logic paths. For example, if you have any sort of counter, you would need to use two sets of FFs in the feedback loop, one positive edge triggered and one negative edge triggered. Otherwise clock skew can cause one output to change before another bit that depends on the first is clocked. As you say, clock skew causes hold time problems. > As for the original question I guess I could simply find the minimum > distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is > what ISE/XST should do if I understand the documentation correctly). > That time would be the =93new=94 timing constraint. If it=92s impossible = to > meet this new timing I need to use asynchronous clock domain > techniques, otherwise it would be just fine. I'm not sure what you are getting at. If the clocks are not simply related, I'm not sure you can assume there is any useful relationship between their timing. To generate the 28 MHz clock the 125 MHz input clock is multiplied up to 825 before being divided down to 28.xxx. How would you expect the tools to consider the timing relationship between two clocks divided down from an 825 MHz (~1.2 ns period) clock? > > In the posted code, the > > signals reset, byte_received and data_in probably originate in some > > other domain and are crossing; reg1, as noted by the OP definitely > > does come from a foreign clock domain and is not treated properly. > > data_in and byte_received are registers clocked by clk_250k and > originate from a MIDI UART. The clk_250k frequency is eight times the > 31.25 kbaud rate of the MIDI interface and used to retrieve the > asynchronous serial MIDI data. I recently discussed a multiple clock design with my customer. He said he had more than 50 clocks in this design and wanted details on how I deal with syncing multiple clock domains. I explained that I do all my work in one clock domain and use a particular logic circuit to transport clocks, enables and data into that one domain. I solve the synchronization problem once at the interface and never have to worry about it again. That logic uses two processes, one in each clock domain. If the FROM domain uses a clock enable, the data is registered in the FROM domain. Data is normally also registered in the TO domain but it depends on the rates. Clocks and/or clock enables run through a simple circuit that deals with metastability and provides a clock enable in the new domain that suits the situation. The circuit is just three FFs, one in the FROM clock domain and two in the TO clock domain. The FROM domain FF and one of the TO domain FFs have the data inputs and outputs connected in a feedback loop with one inverter in the loop. If syncing a clock the FROM domain FF has no enable. If syncing a clock enable, that enable is used on the FROM domain FF. The TO domain FF in the feedback loop feeds the second FF for metastability minimization. Every FROM domain clock edge or clock enable causes the feedback loop to toggle state. An XOR gate on the output of the two TO FFs gives you a clock enable in the TO domain. The FROM domain clock can be faster than the TO domain clock as long as the FROM clock enable is less frequent than half the TO domain clock rate. It may even be possible to have an enable rate up to the TO domain clock rate, but I won't swear to that unless I analyzed this carefully. This is a lot simpler to think about looking at a diagram. Maybe I need to write this up. I didn't think of this circuit myself. A co- worker told me about it and it was given to him by his brother I think. It is very versatile and is the only circuit I use for clock domain crossing with varying data registers depending on the particulars. My customer found this to work for him with his 50+ clocks. Rick From newsfish@newsfish Fri Feb 3 13:09:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 12 Dec 2010 13:42:20 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 59 Message-ID: <4d04c32c$0$14250$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 03b0f900.news.skynet.be X-Trace: 1292157740 news.skynet.be 14250 91.177.205.212:49433 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4500 rickman wrote: > > Jan doesn't get what I am saying. I'm not that worried about the > particulars of this case. I am just lamenting that everything I do in > an HDL is about describing the behavior of the logic and not actually > describing the logic itself. I am an old school hardware designer. I > cut my teeth on logic in TO packages, hand soldering the wire leads. > I still think in terms of the hardware, not the software to describe > the hardware. Many of my designs need to be efficient in terms of > hardware used and so I have to waste time learning how to get what I > want from the tools. Sometimes I just get tired of having to work > around the tools rather than with them. Ok, let's talk about the overall message then. I remember an article from the early days were some guy "proved" that HDL-based design would never otherthrow schematic entry, because it is obviously better to describe what something *is* than what it *does*. All ideas come back, also the bad ones :-) HDL-based design was adopted by old school hardware designers, for lack of other ones. They must have been extremely skeptical. How did it happen? Synopsys took manually optimized designs from expert designers and showed that Design Compiler consistently made them both smaller and faster, and permitted trade-off optimizations between the two. The better result was obviously *not* like the original designer imagined it. The truth is that HDL-based design works better in all respects than handcrafted logic. It is a no-compromises-required technology, which is very rare. Look no further than this newsgroup for active designers who understand this very well. Their designs must probably be as efficient as yours. Yet they use coding styles that are much more abstract, and they are certainly not concerned about the where the last mux or carry-out goes. In other words, when you make claims about ineffiencies and requirements to fight tools all the time, you better come up with some very strong examples - the evidence is against you. What do you give us? A vague problem with an example of a modulo operation on a decrementer. Instead of posting the code and resolve the issue immediately, you give some verbose description in prose so that we now all can start the guessing game. The example has a critical problem, but you don't know what it is and you refuse to track it down. Yet you still refer to it to back up your claims. If that is your standard, why should I take any of your claims seriously? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 12 Dec 2010 19:05:09 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 29 Message-ID: <4d050ed4$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 3cef954e.news.skynet.be X-Trace: 1292177108 news.skynet.be 14247 91.177.205.212:55974 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4501 rickman wrote: > Jan doesn't get what I am saying. I'm not that worried about the > particulars of this case. I'm sorry to bother you with this again, but I am actually worried. >From your description, I tried to reproduce your problem, to no avail. With or without modulo, it doesn't make the slightest difference. (Quartus Linux web edition v.10.0). Perhaps you stumbled on some problematic use case that we definitely should know about. After all, HDL-based design is not about specifying an exact gate level implementation, but about understanding which patterns work well. Perhaps you stumbled upon a pattern that doesn't and that we should avoid. Please post your code. Let's not spoil an opportunity to advance the state of the art. Of course, you may have good reasons not to post your code, for example because you found a bug in the mean time. Perhaps you did modulo 2^N-1 instead of 2*N, just to mention a mistake that I once made. Let us know, so that we can stop worrying. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin2!goblin.stu.neva.ru!xlned.com!feeder1.xlned.com!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 21:37:16 +0100 Lines: 116 Message-ID: <8mkq3rFo01U1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net b6OlAfcN3tEeikVDCUPMNgYFX+kDCFak+Ki85D6R8fa/9PF+JU Cancel-Lock: sha1:/9niAbA8UIbdnru7PtYHL7vwKB0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4502 On 12/12/2010 11:01 AM, rickman wrote: > On Dec 11, 3:43 pm, Beppe wrote: >> Thanks for the answers. [snip] > > Don't count on the fact that the design works on your lab bench as > proof that it works in any real sense! You can never prove a design > works by testing it!!! You can only use test to prove that a design > doesn't work. To prove that it works requires that you test all > possible conditions and that's not really possible much less > practical. > I am sorry but I disagree with you on this point. There are "good practices" that help a lot in guaranteeing the quality of your project. I believe that coding is just part of the story. Having the possibility to test the design by a different team from the designers one will make a huge difference. To do that a very precise (not necessarily detailed) documentation is of course mandatory, since the verification team should not go in the rtl details, or even the timing constraints and place & route details of the project (the concept behind the design will also benefit of a well structured documentation). This is why there are standardized procedures, for avionics, space applications, military applications (to mention some of them), which go beyond the vhdl and define a work flow that should be as much independent as possible from the individual skills of the designers team. And also limiting the focus only on the coding side, there are a lot of dos and don'ts that should be followed thoroughly. Here for instance a good article on common hdl mistakes (and IMHO misconceptions): http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > >> I was first thinking that it would be okay to put the clk_250k on a >> non-dedicated clock net because of its low frequency, but the >> frequency doesnt matter here if Im right when rethinking it. The >> output of a flip-flop (as a result of the flip-flop being clocked by a >> clock edge) could be propagating to the next flip-flop before the same >> clock edge clocks the next flip-flop and thus leading to a hold time >> violation no matter the frequency. Right? >> >> On a side note, a solution for clocks with excessive skew (on non- >> global clock nets) should be to alternate between positive and >> negative clock edges on every other register. That would cut the >> performance by half, but if its applied on low frequency clocks it >> doesnt really matter. Is this a no, no technique or would I be fine >> using it? Why do you need to go in such a complicated pathway when you don't need to? It has been already suggested a very easy and robust solution that will avoid any of the problems you mentioned: On 12/10/2010 11:28 PM, KJ wrote: > - What you should do is generate a clock enable for rather than a > clock for the 250k. Then both processes are running in the same clock > domain...no clock crossings at all. > In my opinion the use of both rising and falling edges should have a stronger motivation (like to minimize the peak current during clock transitions in large SoC). > >> As for the original question I guess I could simply find the minimum >> distance between a clk_28 edge and a clk_25 edge (Hm, exactly this is >> what ISE/XST should do if I understand the documentation correctly). >> That time would be the new timing constraint. If its impossible to >> meet this new timing I need to use asynchronous clock domain >> techniques, otherwise it would be just fine. > Even though your solution may work, that doesn't mean it is the right one. I would recommend going through a clock domain crossing technique as already suggested. Again, following "good practices" not only help us having better chances our systems work, it also (and more important) helps spreading the use of them with invaluable returns to the whole community. > I'm not sure what you are getting at. If the clocks are not simply > related, I'm not sure you can assume there is any useful relationship > between their timing. To generate the 28 MHz clock the 125 MHz input > clock is multiplied up to 825 before being divided down to 28.xxx. > How would you expect the tools to consider the timing relationship > between two clocks divided down from an 825 MHz (~1.2 ns period) > clock? > > >>> In the posted code, the >>> signals reset, byte_received and data_in probably originate in some >>> other domain and are crossing; reg1, as noted by the OP definitely >>> does come from a foreign clock domain and is not treated properly. >> >> data_in and byte_received are registers clocked by clk_250k and >> originate from a MIDI UART. The clk_250k frequency is eight times the >> 31.25 kbaud rate of the MIDI interface and used to retrieve the >> asynchronous serial MIDI data. That is data_in and byte_received are from a different clock domain and they should by resync'ed to be used in the clk_25 domain. > > I recently discussed a multiple clock design with my customer. He > said he had more than 50 clocks in this design and wanted details on > how I deal with syncing multiple clock domains. I explained that I do > all my work in one clock domain and use a particular logic circuit to > transport clocks, enables and data into that one domain. I solve the > synchronization problem once at the interface and never have to worry > about it again. > I would recommend an alternative to the 50 clocks domains, instead. Al From newsfish@newsfish Fri Feb 3 13:09:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!fu15g2000vbb.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 13:17:18 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> NNTP-Posting-Host: 83.185.113.81 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292188638 20892 127.0.0.1 (12 Dec 2010 21:17:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 21:17:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fu15g2000vbb.googlegroups.com; posting-host=83.185.113.81; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4503 > Don't count on the fact that the design works on your lab bench as > proof that it works in any real sense! You can never prove a design > works by testing it!!! You can only use test to prove that a design > doesn't work. To prove that it works requires that you test all > possible conditions and that's not really possible much less > practical. Of course you=92re right. =93It=92s working in hardware=94 was more of a hi= nt that it might not be totally doomed. > How would you expect the tools to consider the timing relationship > between two clocks divided down from an 825 MHz (~1.2 ns period) > clock? Maybe I wasn=92t clear enough, but the two clocks are related by a known fraction. They are both derived from the 125 MHz input clock. clk_28 =3D 125*7/31 and clk_25 =3D 125/5 and hence clk_28 =3D 35/31*clk_25. And I expect the tools to consider the timing relationship because the ISE/ XST/DCM documentation states that the software derives a new PERIOD for each of the DCM output clocks and determines the clock relationships between the output clock domains. And that is also what the timing report in my previous post reflects. > I solve the synchronization problem once at the interface > and never have to worry about it again. Seems like a good idea. > This is a lot simpler to think about looking at a diagram. Maybe I > need to write this up. Please do that! I lost you somewhere in between the domains..., but I would very much like to see how you solve the clock domain crossing. /B From newsfish@newsfish Fri Feb 3 13:09:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i17g2000vbq.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Sun, 12 Dec 2010 13:45:45 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> NNTP-Posting-Host: 83.185.113.81 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292190345 3554 127.0.0.1 (12 Dec 2010 21:45:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 12 Dec 2010 21:45:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i17g2000vbq.googlegroups.com; posting-host=83.185.113.81; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4504 > Why do you need to go in such a complicated pathway when you don't need > to? It has been already suggested a very easy and robust solution that > will avoid any of the problems you mentioned: > On 12/10/2010 11:28 PM, KJ wrote: > > - What you should do is generate a clock enable for rather than a > > clock for the 250k. Then both processes are running in the same clock > > domain...no clock crossings at all. I don=92t intend to. As I said it was just a side note. And as I also have said, that solution doesn=92t help since I still need to cross domains. With an enable the CTRL_PROC would be clocked by clk_25, but the CNT_PROC would still be clocked by clk_28. > That is data_in and byte_received are from a different clock domain and > they should by resync'ed to be used in the clk_25 domain. If you read the original post you will notice that the clk_25 domain isn=92t used in either of the two processes. data_in and byte_received are read in the CTRL_PROC, which is clocked by clk_250k and thus they don't cross domains and they don=92t need to be resynchronized. At least not in the given example. /B From newsfish@newsfish Fri Feb 3 13:09:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 00:20:42 +0100 Lines: 33 Message-ID: <8ml3mcFgg9U1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net C5pBy5PFH61uh4XUmhpc+wosL/kV8UYM0MOHX5VitHcWufX9Dz Cancel-Lock: sha1:koXmPfxMob7pyPARTvO7XrFw4d8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4505 On 12/12/2010 10:45 PM, Beppe wrote: >> Why do you need to go in such a complicated pathway when you don't need >> to? It has been already suggested a very easy and robust solution that >> will avoid any of the problems you mentioned: >> On 12/10/2010 11:28 PM, KJ wrote: >> > - What you should do is generate a clock enable for rather than a >> > clock for the 250k. Then both processes are running in the same clock >> > domain...no clock crossings at all. > > I dont intend to. As I said it was just a side note. And as I also > have said, that solution doesnt help since I still need to cross > domains. With an enable the CTRL_PROC would be clocked by clk_25, but > the CNT_PROC would still be clocked by clk_28. > That is the reason why you need to resync. >> That is data_in and byte_received are from a different clock domain and >> they should by resync'ed to be used in the clk_25 domain. > > If you read the original post you will notice that the clk_25 domain > isnt used in either of the two processes. data_in and byte_received > are read in the CTRL_PROC, which is clocked by clk_250k and thus they > don't cross domains and they dont need to be resynchronized. At least > not in the given example. > My fault, indeed it seems to me you do not need the clk_250k at all and can have data_in and byte_received directly in clk_25 domain (800 pulses per bit). > /B From newsfish@newsfish Fri Feb 3 13:09:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 00:23:30 +0100 Lines: 26 Message-ID: <8ml3riFgg9U2@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 4tq8qmqG2snB7i3mIHl4+gsc/Sg+sOxbcM6VsQQDrjxRl6X4pr Cancel-Lock: sha1:A/42fpNlS7L/0TxLMvG/P/XcEDw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4506 On 12/11/2010 5:25 AM, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. [snip] > I guess what I am trying to say is I would like to be able to specify > detailed logic rather than generically coding the function and letting > a tool try to figure out how to implement it. This should be possible > without the issues of instantiating logic (vendor specific, clumsy, > hard to read...). In an ideal design world, shouldn't it be pretty > easy to infer logic and to actually know what logic to expect? > IMHO using HDL as if we are using a schematic entry is rather limiting and does not provide any high level abstraction which is rather powerful in terms of description, implementation and maintainance of the code. I found the following readings very inspiring: http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm and http://mysite.ncnetwork.net/reszotzl/uart.vhd Al > Rick From newsfish@newsfish Fri Feb 3 13:09:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 02:05:19 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292234719 8390 127.0.0.1 (13 Dec 2010 10:05:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 10:05:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4508 > > I don t intend to. As I said it was just a side note. And as I also > > have said, that solution doesn t help since I still need to cross > > domains. With an enable the CTRL_PROC would be clocked by clk_25, but > > the CNT_PROC would still be clocked by clk_28. > > That is the reason why you need to resync. Exactly. And the reason why an enable doesn't help. However, an enable will get rid of the logic generated clk_250k although I haven't been convinced why it's so bad with a logic generated clock even when it is put on the low skew global clock line. > >> That is data_in and byte_received are from a different clock domain and > >> they should by resync'ed to be used in the clk_25 domain. > > > If you read the original post you will notice that the clk_25 domain > > isn t used in either of the two processes. data_in and byte_received > > are read in the CTRL_PROC, which is clocked by clk_250k and thus they > > don't cross domains and they don t need to be resynchronized. At least > > not in the given example. > > My fault, indeed it seems to me you do not need the clk_250k at all and > can have data_in and byte_received directly in clk_25 domain (800 pulses > per bit). That's right. So in any case I need to use a clock domain crossing technique unless I rewrite the MIDI UART and clock it with the clk_28. /B From newsfish@newsfish Fri Feb 3 13:09:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 04:48:00 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <1acc8c8f-bbc5-45dd-8e86-49b15abb5d76@30g2000yql.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292244480 18897 127.0.0.1 (13 Dec 2010 12:48:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 12:48:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4509 On Dec 13, 5:05=A0am, Beppe wrote: > > > That is the reason why you need to resync. > > Exactly. And the reason why an enable doesn't help. However, an enable > will get rid of the logic generated clk_250k although I haven't been > convinced why it's so bad with a logic generated clock even when it is > put on the low skew global clock line. > Because of the potential for hold time problems on a signal coming from the high speed clock domain into the generated clock domain. The low skew that you are talking about is between different flops clocked by that same clock. It does not address the skew between the two clock domains. The timing analysis will report it...but it won't fix it. While this is true of all timing problems, the solution to this particular timing problem is to add delays into the data path so that the minimum data delay is still faster than the clock (plus setup). Then ask yourself, how do you insert delays into an FPGA design? Do you want to be adding this delay potentially every time you re-route the design for some reason? Plus, when you get right down to it, it will likely take exactly the same amount of logic to generate the lower speed clock as it would to generate the clock enable...so ask yourself, other than more work and potential headaches what do you expect to get by using a generated clock? Kevin Jennings From newsfish@newsfish Fri Feb 3 13:09:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.unit0.net!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!n32g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Mon, 13 Dec 2010 06:40:11 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: <1909591f-171b-47bb-8233-793106dff97c@n32g2000pre.googlegroups.com> References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <1k87g6pgurrcujr2hnhjl8pb6q5see2jj5@4ax.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292251211 13572 127.0.0.1 (13 Dec 2010 14:40:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 14:40:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000pre.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4510 On Dec 11, 10:21=A0am, Brian Drummond wrote: > If you want wrapround from 255 to 0, you want a modular type - as others = point > out, numeric_std.unsigned meets your needs. > > Or you could make the wrapround explicit using the "mod" operator. > This is more flexible since the "mod" value can be something other than 2= 56. Most synthesis tools will not accept a modulo or divide operation by a non-integer power of two. For other values, you have to use a conditional to test for the pending overflow and take appropriate actions to prevent it. Andy From newsfish@newsfish Fri Feb 3 13:09:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Mon, 13 Dec 2010 15:23:08 +0000 Organization: TRW Conekt Lines: 46 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net Y3Yqi8FAkffqNjjFyL+eFQyUz1/SUWZywRFH1mgtswJBt4M5o= Cancel-Lock: sha1:gI0a5NMZ7fXY2KWj/03y0Uwk8z8= sha1:e/P1plEtF+1ru9ECQW9opehUEJo= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4511 rickman writes: > How exactly would my simulation be different from synthesis if I used > a max of 200 for a counter? If my simulation tries to increment the > counter past 200 it stops! That would not be an issue of different > results, that would be my simulation failing to complete! If my usage > of the counter never pushes it past 200, then the simulation and synth > match. OK, yes, I think I expressed myself badly :) I was trying to talk about unexpected behaviour, and confused the issue by talking about mismatches. As I said to Jan, if the simulation doesn't test far enough, one might get different behaviour to what one (might) expect (however innaccurate that expectation may be). > I think people are making far too big of an issue about this. An HDL > is supposed to be describing hardware, hence the name HDL. If you > take the position that the simulation and synthesis should always > match 10% you can never design anything real. ^^^ I assume you mean 100% there? > If I have a counter that is only needed for values of 200 or less > and I don't care what happens when the value is over 200, then case > 2 is perfectly ok. Quite so, I never intended to say anything other. > > The OP has not responded, but I think he is just asking what the > synthesizer does. I don't think his issue is about what the "correct" > thing to do is. > On re-reading the OP with that in mind, I agree. Sorry for any confusion caused! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Mon, 13 Dec 2010 16:35:57 +0100 Lines: 62 Message-ID: <8mmsqvF12mU1@mid.individual.net> References: <8ma3hpF3caU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9LS9uv89g/IalggIlnPPnwZGJr0tZDvyqhDB8HvhVTe+3AN++9 Cancel-Lock: sha1:de5sRBOj2tR6Ztou27S03wUqHK8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:13692 comp.lang.vhdl:4512 comp.lang.verilog:2720 On 12/10/2010 3:57 PM, Thomas Stanka wrote: [snip] > Open cores tend to have a lack in documentation and verification, > which is a no-go for developing space electronics. There are documented results of projects that attracted space applications (http://opencores.org/newsletter,2010,09,#n5), proving that there is a certain interest in the open approach. > Even if you target on public science projects it is very likely that > you need to ensure the "space-readiness" in many aspects for a core > before you can use it. > The aim of the project is not to provide a "ready-to-use" solution, but to spread the use of spacewire protocol. The end-user is of course responsible for the entire process, but it can be foreseen a test campaign which will validate the IP on certain technologies (after all I am working at CERN and there are a lot of test-beams facilities here!). I just want to mention that on an FPGA based application the choice of the FPGA may guarantee certain level of radiation hardness, while specific design techniques may improve the level of hardness even further (TMR, data-scrubbing, EDAC.). > For spacewire interface I consider the effort to proof the quality of > a core clearly exceeding the effort for writting the core for your > own. > Indeed, nevertheless there are a good amount of projects which are neither proofing the quality of their cores, nor applying any standard protocol throughout their systems. > Are you firm with developing according to ECSS-Q 60 02? I would expect > a core development to be complaint to this before using it without > further quality checking in case of the core not beeing provided from > ESA for a ESA project. > Even though I believe that Space Agencies around the world are politically and technically bond to follow standardization processes based mostly on lessons learned, I also believe that a lot of industries and research institutes are buried under the burden of those standards where a good chunk of their budget goes. I am not advocating a deviation from the standards, on the contrary I believe that protocols (as can-bus, mil-std-1553, spi, I2C...) are key components of a reliable system and any effort should be made to make them popular. > In case of detailed questions you may also conntact me by sending an > email. You should change the receive-address to thomas > @domain_from_email when replying. > > best regards Thomas Al p.s.: I am just an enthusiast designer, willing to improve my skills and to share my knowledge. From newsfish@newsfish Fri Feb 3 13:09:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!35g2000prb.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 09:06:38 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292259998 6101 127.0.0.1 (13 Dec 2010 17:06:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 17:06:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 35g2000prb.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4513 On Dec 10, 8:25=A0pm, rickman wrote: > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > use VHDL which we all know is a pig in many ways with its verbosity > and arcane type conversion gyrations. =A0But what bothers me most of all > is that I have to learn how to tell the tools in their "language" how > to construct the efficient logic I can picture in my mind. By > "language" I don't mean the HDL language, but actually the specifics > of a given inference tool. > > Rick Back in the 8086 days, I had to do the same thing with compilers. I spent a fair amount of time learning how the code generation phase worked so I could get the tools to work properly. I remember a "brand- name" 'C' compiler very carefully generating code to keep the loop control variable in the CX register, then at the end of the loop moving CX to AX and adding minus-one. (For those that don't program 86's in assembly, the CX register is a special purpose register for the 'LOOP' instruction.) Now that processors are real fast, and memory is very cheap, I don't worry so much about efficient code. I would draw a parallel to the frustrations you are having with HDLs. Another parallel I would draw is that when I wanted 'very fast tight code' I would code certain modules in assembly, and link them with 'C' routines. When the synthesizer just won't get it right, I draw it a picture. (Which is one advantage the Acme-Brand tool has over the Brand-X tool) Yeah, it's not portable, and it isn't "right". But I'm getting product out the door. RK. From newsfish@newsfish Fri Feb 3 13:09:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!f21g2000prn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 09:31:30 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292261490 7269 127.0.0.1 (13 Dec 2010 17:31:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 17:31:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f21g2000prn.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4514 On Dec 11, 10:44=A0am, Brian Drummond wrote: > >What I mean is, if I want a down counter that uses the carry out to > >give me an "end of count" flag, why can't I get that in a simple and > >clear manner? =A0 > > Here the issue appears to be how to get at the carry out of a counter... > the syntax of integer arithmetic doesn't provide an easy way to do that b= y > default, in any language I know (other than assembler for pre-RISC CPUs, = with > their flag registers). > > It seems to me that you have two choices ... > (1) implement an n-bit counter, and augment it in some way to recreate th= e carry > out (unfortunately you are fighting the synthesis tool in the process) > > (2) implement an n+1 bit counter, with the excess bit assigned to the car= ry, and > trust the synthesis tool to eliminate the excess flip-flop at the optimis= ation > stage... > > I am willing to guess the second approach would be simpler. I have found the 1st approach far simpler, by using a natural subtype for the counter. Then (count - 1 < 0) is the carry out for a down counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit up counter. No fighting required. Andy From newsfish@newsfish Fri Feb 3 13:09:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!news.tele.dk!feed118.news.tele.dk!postnews.google.com!29g2000prb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 10:19:59 -0800 (PST) Organization: http://groups.google.com Lines: 45 Message-ID: <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292264400 12680 127.0.0.1 (13 Dec 2010 18:20:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 18:20:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 29g2000prb.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4515 On Dec 12, 3:15=A0am, rickman wrote: > I'm not that worried about the > particulars of this case. =A0I am just lamenting that everything I do in > an HDL is about describing the behavior of the logic and not actually > describing the logic itself. =A0I am an old school hardware designer. =A0= I > cut my teeth on logic in TO packages, hand soldering the wire leads. > I still think in terms of the hardware, not the software to describe > the hardware. =A0Many of my designs need to be efficient in terms of > hardware used and so I have to waste time learning how to get what I > want from the tools. =A0Sometimes I just get tired of having to work > around the tools rather than with them. I seem to recall a similar argument when assemblers gave way to higher level language compilers... This change in digital hardware design is not unlike the change from one-man furniture shops to furniture factories. The craftsmen of the one-man shops painstakingly treated every detail as critical to their product: a chair. And the result was an exquisite piece of furniture, albeit at a very high price, and very low volume (unless you hired a lot of one man shops at the same time). Circuit designers are no different (being one myself, dating back to those "I can do that function in one less part" days gone by). But the target has changed. We no longer need a chair, we need a stadium full of them. And we need the elevators, climate control, fire suppression, lighting, and all the other support systems, to go along with them. Perhaps we should take a step back, and look at what we really need (hint: a place for a lot of people to watch an event, while seated most of the time). Now I can optimize my stadium to recognize that all of my seats don't need to be finely crafted pieces of furniture. But I don't know that until I focus on the requirements: "What must my project do?" So, instead of finding a way to describe the project as a collection of specific chairs, elevators and fire extinguishers, we need to describe it as a set of desired behaviors, and then, through some process (hopefully semi-automated), convert that description into an optimized design for the stadium. Could the craftsman and his tools have done that? What do you want from the tools, a collection of exquisitely crafted chairs, or an efficient stadium? Andy From newsfish@newsfish Fri Feb 3 13:09:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!15g2000vbz.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 10:34:13 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <429cad50-bfa9-42be-85b6-8bef28e19c77@i17g2000vbq.googlegroups.com> <8ml3mcFgg9U1@mid.individual.net> <0bd4f1b3-da2e-4020-9b6e-d7ce39de752f@o14g2000yqe.googlegroups.com> <1acc8c8f-bbc5-45dd-8e86-49b15abb5d76@30g2000yql.googlegroups.com> NNTP-Posting-Host: 90.130.237.152 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292265253 20700 127.0.0.1 (13 Dec 2010 18:34:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Dec 2010 18:34:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 15g2000vbz.googlegroups.com; posting-host=90.130.237.152; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.215 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4516 > Because of the potential for hold time problems on a signal coming > from the high speed clock domain into the generated clock domain. But if there=92s no data coming from the high speed clock domain into the generated clock domain I don=92t see the problem. That is actually the case in the given example. The clock domain crossing is between clk_250k and clk_28 not between clk_250k and clk_25. > Then ask yourself, how do you insert delays into an FPGA design? Clocking on both positive and negative clock edge...! Ok, I won=92t do that I will use enables. > what do you expect to get by using a generated clock? Lower power consumption? /B From newsfish@newsfish Fri Feb 3 13:09:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 13 Dec 2010 16:43:09 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 22:44:19 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 31 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-V0eVJ02ziUG3BFUoIuad4BzbjqgrXy3NGyJHsUIu1tRgsxfc1yPHAhsNhlQ37gzEbxwPeXYpnLTOHgN!ggpJibO3Jz5JqpSWzzRoZKS06GGmF+2VgEQ8wN07FYPT/7JGjREEqbyajId7UK+Kou67hQc/dRpP!lpg= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2577 Xref: feeder.eternal-september.org comp.lang.vhdl:4517 On Mon, 13 Dec 2010 09:31:30 -0800 (PST), Andy wrote: >On Dec 11, 10:44am, Brian Drummond >wrote: >> Here the issue appears to be how to get at the carry out of a counter... >> It seems to me that you have two choices ... >> (1) implement an n-bit counter, and augment it in some way to recreate the carry >> out (unfortunately you are fighting the synthesis tool in the process) >> >> (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and >> trust the synthesis tool to eliminate the excess flip-flop at the optimisation >> stage... >> >> I am willing to guess the second approach would be simpler. > >I have found the 1st approach far simpler, by using a natural subtype >for the counter. Then (count - 1 < 0) is the carry out for a down >counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit >up counter. No fighting required. In which case it is the expression (count - 1) or (count + 1) which must be n+1 bits; then perhaps its size (and its type - integer - for count-1) need not be explicitly expressed. I believe some synthesis tools used to generate rather large elaborations of this expression (inc/decrement, then comparator), hence fighting - but perhaps none do so any longer. - Brian From newsfish@newsfish Fri Feb 3 13:09:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z19g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 19:56:25 -0800 (PST) Organization: http://groups.google.com Lines: 106 Message-ID: <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292298985 26001 127.0.0.1 (14 Dec 2010 03:56:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 03:56:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4518 On Dec 12, 3:37 pm, Alessandro Basili wrote: > On 12/12/2010 11:01 AM, rickman wrote: > > > On Dec 11, 3:43 pm, Beppe wrote: > >> Thanks for the answers. > [snip] > > > Don't count on the fact that the design works on your lab bench as > > proof that it works in any real sense! You can never prove a design > > works by testing it!!! You can only use test to prove that a design > > doesn't work. To prove that it works requires that you test all > > possible conditions and that's not really possible much less > > practical. > > I am sorry but I disagree with you on this point. There are "good > practices" that help a lot in guaranteeing the quality of your project. I never said testing isn't useful. I said that testing can't assure that something works unless you test every possible condition and that is not possible in an absolute sense. Besides, you snipped the OP's comment I was responding to... "the design seems to be working fine in hardware although I haven=92t made any extensive tests yet." The problem we are discussing is ***exactly*** the sort of thing you may not find in testing. The way the OP has constructed the circuit it may work in 99.99% of the systems he builds. Or it may work 99.99% of the time in all of the systems. But testing can't validate timing since you can't control all of the variables. The only thing testing can really do is to verify that your design meets your requirements... if your requirements are testable! I've been trained in quality process development and after seeing it in action, I realize that much of it is not a better than intelligent thinking. Just like many of the tools provided in engineering, this is one that seems to provide benefit when used by the "masses" rather than by the skilled. > I believe that coding is just part of the story. Having the possibility > to test the design by a different team from the designers one will make > a huge difference. "a huge difference"... I understand there are lots of ways to improve testing, but that doesn't change the fundamental limitation of testing. > To do that a very precise (not necessarily detailed) > documentation is of course mandatory, since the verification team should > not go in the rtl details, or even the timing constraints and place & > route details of the project (the concept behind the design will also > benefit of a well structured documentation). > > This is why there are standardized procedures, for avionics, space > applications, military applications (to mention some of them), which go > beyond the vhdl and define a work flow that should be as much > independent as possible from the individual skills of the designers team. > > And also limiting the focus only on the coding side, there are a lot of > dos and don'ts that should be followed thoroughly. > Here for instance a good article on common hdl mistakes (and IMHO > misconceptions): > > http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF I'm not sure what to say about this article. It is actually a bit shallow in my opinion. But it also contains errors! Much of it is really just the opinion of the author. > Even though your solution may work, that doesn't mean it is the right > one. I would recommend going through a clock domain crossing technique > as already suggested. > Again, following "good practices" not only help us having better chances > our systems work, it also (and more important) helps spreading the use > of them with invaluable returns to the whole community. I think that terms like "good practices" are some of the least useful concepts I've ever seen. First, where are "good practices" defined? Without a clear, detailed definition of the term, it doesn't communicate anything. Usually it is used to mean "what I do". It may be defined within a company, in some limited ways it may be defined within a sector. But in general this is a term that has little meaning as used by most people. This is much like recommending to design "carefully". I can't say how many times I have seen that word used in engineering without actually saying anything. > > I recently discussed a multiple clock design with my customer. He > > said he had more than 50 clocks in this design and wanted details on > > how I deal with syncing multiple clock domains. I explained that I do > > all my work in one clock domain and use a particular logic circuit to > > transport clocks, enables and data into that one domain. I solve the > > synchronization problem once at the interface and never have to worry > > about it again. > > I would recommend an alternative to the 50 clocks domains, instead. What alternative would that be??? Is that different than the solution I recommended? Rick From newsfish@newsfish Fri Feb 3 13:09:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Mon, 13 Dec 2010 20:25:05 -0800 (PST) Organization: http://groups.google.com Lines: 83 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292300705 8513 127.0.0.1 (14 Dec 2010 04:25:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 04:25:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4519 On Dec 12, 4:17=A0pm, Beppe wrote: > > Don't count on the fact that the design works on your lab bench as > > proof that it works in any real sense! =A0You can never prove a design > > works by testing it!!! =A0You can only use test to prove that a design > > doesn't work. =A0To prove that it works requires that you test all > > possible conditions and that's not really possible much less > > practical. > > Of course you=92re right. =93It=92s working in hardware=94 was more of a = hint > that it might not be totally doomed. > > > How would you expect the tools to consider the timing relationship > > between two clocks divided down from an 825 MHz (~1.2 ns period) > > clock? > > Maybe I wasn=92t clear enough, but the two clocks are related by a known > fraction. They are both derived from the 125 MHz input clock. clk_28 =3D > 125*7/31 and clk_25 =3D 125/5 and hence clk_28 =3D 35/31*clk_25. And I > expect the tools to consider the timing relationship because the ISE/ > XST/DCM documentation states that the software derives a new PERIOD > for each of the DCM output clocks and determines the clock > relationships between the output clock domains. And that is also what > the timing report in my previous post reflects. > > > I solve the synchronization problem once at the interface > > and never have to worry about it again. > > Seems like a good idea. > > > This is a lot simpler to think about looking at a diagram. =A0Maybe I > > need to write this up. > > Please do that! I lost you somewhere in between the domains..., but I > would very much like to see how you solve the clock domain crossing. I don't have time to draw a diagram, but here is some code. I've had to edit out a lot of support circuitry which is not related, I hope I didn't screw this up. Scfg_Sync : process (SysClk, SysRst) begin if (SysRst =3D '1') then Scfg_SysClk <=3D '0'; elsif (falling_edge(SysClk)) then if (Clk_en =3D '1') then Scfg_SysClk <=3D not Scfg_StbLatch; -- Sync across clock domains end if; end if; end process Scfg_Sync; -- Control register interface -- Clock interface and synchronize to system clock CntrlReg : process (Scfg_Str, IF_EN) begin if (IF_EN =3D '1') then Scfg_StbLatch <=3D '0'; Scfg_StbLatch_D <=3D '0'; elsif (rising_edge(Scfg_Str)) then Scfg_StbLatch <=3D Scfg_SysClk; -- Sync across clock domains Scfg_StbLatch_D <=3D Scfg_StbLatch; end if; end process CntrlReg; Scfg_clk_en <=3D Scfg_StbLatch xor Scfg_StbLatch_D; Every time the clock enable in the SysClk domain is asserted, the loop signal Scfg_SysClk toggles generating an edge which is detected by the concurrent statement at the end. That logic can also be registered to help with metastability issues since Scfg_StbLatch will go metastable. To convey the clock SysClk to the other domain, just remove the if (Clk_en =3D '1') and let every rising edge send an transition to the other domain. The Scfg_Str domain has to be clocked at least as fast as the edge rate of Scfg_SysClk for an enable or twice as fast for a clock. Getting data across just requires that the data be held stable until it is clocked into the receiving domain. Sometimes this does not require an interface register at all depending on the particulars of the interface timing, etc. Rick From newsfish@newsfish Fri Feb 3 13:09:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 20:40:33 -0800 Organization: solani.org Lines: 36 Message-ID: <20101213204033.7c01f784@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292301634 32540 eJwFwQkBwDAIA0BLFEho5TAe/xJ2B+NhhRN0LFbwzuBWvrgfbCuaKeGuJpkhs60ZltShq/YPEq4Qyg== (14 Dec 2010 04:40:34 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Tue, 14 Dec 2010 04:40:34 +0000 (UTC) X-User-ID: eJwNw4kNwDAIBLCVCP+NQ4HsP0JjySZ+vEPdXO3aHQiI+aVCHOGsXbRR7XxDiMq3krZxU/EDCqEQ4Q== X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:terNPMwX1t3Vnqytxc/RQWbg7BA= X-NNTP-Posting-Host: eJwFwYEBwCAIA7CX7KAV3qmT/08wYQg6O0UlhyODXc6FgW9Vi5+98Cew63S0MkHcnuhLPwMxECA= Xref: feeder.eternal-september.org comp.lang.vhdl:4520 On Mon, 13 Dec 2010 00:23:30 +0100 Alessandro Basili wrote: > http://mysite.ncnetwork.net/reszotzl/uart.vhd > > Al > > Am I missing something, or is the transmitter slightly flawed in this code? I seem to see the following: 1. At some point, TxState_v is SEND, and you reach TxBitSampleCount_v = tic_per_bit_g and hence bit_done is true. Also, TxBitCount_v is 7. 2. You enter the "if" block in the SEND case in procedure tx_state. You set TxBitSampleCount_v to 0, serial_out_v to Tx_v(TxBitCount_v) = Tx_v(7). You set TxBitCount_v to TxBitCount_v+1 = 8. You notice that TxBitCount_v=char_len_g=8 and hence set TxState_v to STOP. 3. tic_per_bit_g clocks later, you enter the "if" block in the STOP case. You set serial_out_v to '1' and TxState_v to IDLE. 4. From this moment, if the application queries the status register, you will see that TxState_v is IDLE and hence report transmitter ready. The application could thus immediately strobe another byte of data into the transmit data register. Then tx_state will transition to TxState_v = START and, on the next clock, set serial_out_v to '0'. Problem: this might not have been a full bit-time since you started sending the '1' stop bit! You never actually guarantee to wait for the full stop bit to pass before accepting new data from the application in the transmit data register! Or am I missing something? Chris From newsfish@newsfish Fri Feb 3 13:09:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y23g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 21:32:44 -0800 (PST) Organization: http://groups.google.com Lines: 65 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292304764 11885 127.0.0.1 (14 Dec 2010 05:32:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 05:32:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y23g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4521 On Dec 13, 12:31=A0pm, Andy wrote: > On Dec 11, 10:44=A0am, Brian Drummond > wrote: > > > > > >What I mean is, if I want a down counter that uses the carry out to > > >give me an "end of count" flag, why can't I get that in a simple and > > >clear manner? =A0 > > > Here the issue appears to be how to get at the carry out of a counter..= . > > the syntax of integer arithmetic doesn't provide an easy way to do that= by > > default, in any language I know (other than assembler for pre-RISC CPUs= , with > > their flag registers). > > > It seems to me that you have two choices ... > > (1) implement an n-bit counter, and augment it in some way to recreate = the carry > > out (unfortunately you are fighting the synthesis tool in the process) > > > (2) implement an n+1 bit counter, with the excess bit assigned to the c= arry, and > > trust the synthesis tool to eliminate the excess flip-flop at the optim= isation > > stage... > > > I am willing to guess the second approach would be simpler. > > I have found the 1st approach far simpler, by using a natural subtype > for the counter. Then (count - 1 < 0) is the carry out for a down > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit > up counter. No fighting required. I won't argue that, both of these will utilize the carry out of an adder. But that may or may not be the same adder I am using to update count with. I have looked at the logic produced and at some time found two, apparently identical adder chains used, one of which had all outputs unconnected other than the carry out of the top and the other used the sum outputs to feed the register with the top carry ignored. Sure, there may have been something about my code that prevented these two adders being merged, but I couldn't figure out what it was. I see a number of posts that don't really get what I am trying to say. I'm not arguing that you can't do what you want in current HDLs. I am not saying I want to use something similar to assembly language to provide the maximum optimization possible. I am saying I find it not infrequent that HDL gives nothing close to optimal results because the coding style required was not obvious. I'm saying that it seems like it should be easier to get the sort of simple structures that are commonly used without jumping through hoops. Heck, reading the Lattice HDL user guide (not sure if that is the actual name or not) they say you shouldn't try to infer memory at all, instead you should instantiate it! Memory seems like it should be so easy to infer... I don't know Verilog that well, but I do know VHDL is a pig in many ways. It just seems like it could have been much simpler rather than being such a pie-in-the-sky language. Rick From newsfish@newsfish Fri Feb 3 13:09:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!l17g2000yqe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Mon, 13 Dec 2010 21:47:43 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: <51c54fde-234b-4b8e-853c-69216afae05e@l17g2000yqe.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292305663 7889 127.0.0.1 (14 Dec 2010 05:47:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 05:47:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l17g2000yqe.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4522 On Dec 13, 12:06=A0pm, d_s_klein wrote: > On Dec 10, 8:25=A0pm, rickman wrote: > > > Sometimes I wonder if HDLs are really the right way to go. =A0I mainly > > use VHDL which we all know is a pig in many ways with its verbosity > > and arcane type conversion gyrations. =A0But what bothers me most of al= l > > is that I have to learn how to tell the tools in their "language" how > > to construct the efficient logic I can picture in my mind. By > > "language" I don't mean the HDL language, but actually the specifics > > of a given inference tool. > > =A0 =A0 > > > Rick > > Back in the 8086 days, I had to do the same thing with compilers. =A0I > spent a fair amount of time learning how the code generation phase > worked so I could get the tools to work properly. =A0I remember a "brand- > name" 'C' compiler very carefully generating code to keep the loop > control variable in the CX register, then at the end of the loop > moving CX to AX and adding minus-one. =A0(For those that don't program > 86's in assembly, the CX register is a special purpose register for > the 'LOOP' instruction.) =A0Now that processors are real fast, and > memory is very cheap, I don't worry so much about efficient code. > > I would draw a parallel to the frustrations you are having with HDLs. > Another parallel I would draw is that when I wanted 'very fast tight > code' I would code certain modules in assembly, and link them with 'C' > routines. =A0When the synthesizer just won't get it right, I draw it a > picture. =A0(Which is one advantage the Acme-Brand tool has over the > Brand-X tool) > > Yeah, it's not portable, and it isn't "right". =A0But I'm getting > product out the door. > > RK. I never said I don't get a working design. I just feel that HDLs are more complex than useful. BTW, I don't agree with the analogy between HDLs and compilers. For one, you are considering the case of PCs where speed and memory are virtually unlimited. My apps tend to be more like coding for a PIC with 8K Flash and 1K RAM. A perfect target for a Forth cross- compiler, but likely a poor target for a C compiler. Where is the Forth equivalent for hardware design? Rick From newsfish@newsfish Fri Feb 3 13:09:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w18g2000vbe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 00:54:28 -0800 (PST) Organization: http://groups.google.com Lines: 85 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292316869 10183 127.0.0.1 (14 Dec 2010 08:54:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 08:54:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w18g2000vbe.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4523 On Dec 14, 5:32=A0am, rickman wrote: > On Dec 13, 12:31=A0pm, Andy wrote: > > > > > On Dec 11, 10:44=A0am, Brian Drummond > > wrote: > > > > >What I mean is, if I want a down counter that uses the carry out to > > > >give me an "end of count" flag, why can't I get that in a simple and > > > >clear manner? =A0 > > > > Here the issue appears to be how to get at the carry out of a counter= ... > > > the syntax of integer arithmetic doesn't provide an easy way to do th= at by > > > default, in any language I know (other than assembler for pre-RISC CP= Us, with > > > their flag registers). > > > > It seems to me that you have two choices ... > > > (1) implement an n-bit counter, and augment it in some way to recreat= e the carry > > > out (unfortunately you are fighting the synthesis tool in the process= ) > > > > (2) implement an n+1 bit counter, with the excess bit assigned to the= carry, and > > > trust the synthesis tool to eliminate the excess flip-flop at the opt= imisation > > > stage... > > > > I am willing to guess the second approach would be simpler. > > > I have found the 1st approach far simpler, by using a natural subtype > > for the counter. Then (count - 1 < 0) is the carry out for a down > > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit > > up counter. No fighting required. > > I won't argue that, both of these will utilize the carry out of an > adder. =A0But that may or may not be the same adder I am using to update > count with. =A0I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. =A0Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. > > I see a number of posts that don't really get what I am trying to > say. =A0I'm not arguing that you can't do what you want in current > HDLs. =A0I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. =A0I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. =A0I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! =A0Memory seems like it should be so > easy to infer... > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. =A0It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. > > Rick >From all this reading, Im guessing its not a problem with the language you have, its more the synthesisors. So my two thoughts: 1. Try AHDL - its pretty explicit (but you'll be stuck with Altera). 2. Instead of getting pissed off with the tools and pretending its an HDL problem, how about raising the issue with the vendors and asking them why they've done it the way the have. Personally, I have never had too much of a problem with the tools. The Firmware works as I intend. Im not usually interested in the detail because it works, it ships, the customer pays and we make a profit. I dont care if a counter has used efficient carry out logic or not - it works and thats all the customer cares about. When its working, or I have fit problems I can then go into the finer detail. From newsfish@newsfish Fri Feb 3 13:09:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.85.MISMATCH!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-ID: <4D075258.7010904@jandecaluwe.com> Date: Tue, 14 Dec 2010 12:17:44 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Andy Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> In-Reply-To: <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 70 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: b99fdfda.news.skynet.be X-Trace: 1292325465 news.skynet.be 14256 91.177.199.237:37361 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4524 Andy wrote: > On Dec 12, 3:15 am, rickman wrote: >> I'm not that worried about the >> particulars of this case. I am just lamenting that everything I do in >> an HDL is about describing the behavior of the logic and not actually >> describing the logic itself. I am an old school hardware designer. I >> cut my teeth on logic in TO packages, hand soldering the wire leads. >> I still think in terms of the hardware, not the software to describe >> the hardware. Many of my designs need to be efficient in terms of >> hardware used and so I have to waste time learning how to get what I >> want from the tools. Sometimes I just get tired of having to work >> around the tools rather than with them. > > I seem to recall a similar argument when assemblers gave way to higher > level language compilers... > > This change in digital hardware design is not unlike the change from > one-man furniture shops to furniture factories. The craftsmen of the > one-man shops painstakingly treated every detail as critical to their > product: a chair. And the result was an exquisite piece of furniture, > albeit at a very high price, and very low volume (unless you hired a > lot of one man shops at the same time). > > Circuit designers are no different (being one myself, dating back to > those "I can do that function in one less part" days gone by). But the > target has changed. We no longer need a chair, we need a stadium full > of them. And we need the elevators, climate control, fire suppression, > lighting, and all the other support systems, to go along with them. > > Perhaps we should take a step back, and look at what we really need > (hint: a place for a lot of people to watch an event, while seated > most of the time). Now I can optimize my stadium to recognize that all > of my seats don't need to be finely crafted pieces of furniture. But I > don't know that until I focus on the requirements: "What must my > project do?" So, instead of finding a way to describe the project as > a collection of specific chairs, elevators and fire extinguishers, we > need to describe it as a set of desired behaviors, and then, through > some process (hopefully semi-automated), convert that description into > an optimized design for the stadium. Could the craftsman and his tools > have done that? > > What do you want from the tools, a collection of exquisitely crafted > chairs, or an efficient stadium? This analogy suggests the need for a compromise, which I think isn't there. I don't see a case where the schematic entry craftsman can realistically hope to beat the guy with the HDL tools. For example, for smallish designs, it can be shown that logic synthesis can generate a solution close to the optimum, *regardless* of the quality of the starting point. The craftsman can draw any pictures he wants, even if the tool guy writes the worst possible code, the synthesis result will still be as good or better. Of course, for realistic, larger designs, the structure of the input code becomes more and more significant. But thanks to powerful heuristics, local optimization algorithms, and the ability to recognize higher level structures, this is a gradual process. In contrast, the craftsman's ability to cope with complexity quickly detoriates beyond a certain point. As a result, he has to rely on logic-wise inefficient strategies, such as excessive hierarchy. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 14 Dec 2010 13:50:37 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 69 Message-ID: <4d07681e$0$14247$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 1c276260.news.skynet.be X-Trace: 1292331038 news.skynet.be 14247 91.177.199.237:56170 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4525 rickman wrote: > On Dec 13, 12:31 pm, Andy wrote: >> On Dec 11, 10:44 am, Brian Drummond >> wrote: >> >> >> >>>> What I mean is, if I want a down counter that uses the carry out to >>>> give me an "end of count" flag, why can't I get that in a simple and >>>> clear manner? >>> Here the issue appears to be how to get at the carry out of a counter... >>> the syntax of integer arithmetic doesn't provide an easy way to do that by >>> default, in any language I know (other than assembler for pre-RISC CPUs, with >>> their flag registers). >>> It seems to me that you have two choices ... >>> (1) implement an n-bit counter, and augment it in some way to recreate the carry >>> out (unfortunately you are fighting the synthesis tool in the process) >>> (2) implement an n+1 bit counter, with the excess bit assigned to the carry, and >>> trust the synthesis tool to eliminate the excess flip-flop at the optimisation >>> stage... >>> I am willing to guess the second approach would be simpler. >> I have found the 1st approach far simpler, by using a natural subtype >> for the counter. Then (count - 1 < 0) is the carry out for a down >> counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bit >> up counter. No fighting required. > > I won't argue that, both of these will utilize the carry out of an > adder. But that may or may not be the same adder I am using to update > count with. I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. > > I see a number of posts that don't really get what I am trying to > say. Probably because many people don't see what you say you are seeing, so they must think you don't have a case. I'm not arguing that you can't do what you want in current > HDLs. I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! Memory seems like it should be so > easy to infer... > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. I think Verilog will suit you better as a language, you really should consider switching one of these days. However, there is no reason why it would help you with the issues that you say you are seeing here. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!f20g2000vbc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 06:09:42 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <0084cfa7-ab13-40b1-9642-dfcf7c1fa8aa@29g2000prb.googlegroups.com> <4D075258.7010904@jandecaluwe.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292335782 26728 127.0.0.1 (14 Dec 2010 14:09:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 14:09:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000vbc.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4526 On Dec 14, 5:17=A0am, Jan Decaluwe wrote: > Andy wrote: > > On Dec 12, 3:15 am, rickman wrote: > >> I'm not that worried about the > >> particulars of this case. =A0I am just lamenting that everything I do = in > >> an HDL is about describing the behavior of the logic and not actually > >> describing the logic itself. =A0I am an old school hardware designer. = =A0I > >> cut my teeth on logic in TO packages, hand soldering the wire leads. > >> I still think in terms of the hardware, not the software to describe > >> the hardware. =A0Many of my designs need to be efficient in terms of > >> hardware used and so I have to waste time learning how to get what I > >> want from the tools. =A0Sometimes I just get tired of having to work > >> around the tools rather than with them. > > > I seem to recall a similar argument when assemblers gave way to higher > > level language compilers... > > > This change in digital hardware design is not unlike the change from > > one-man furniture shops to furniture factories. The craftsmen of the > > one-man shops painstakingly treated every detail as critical to their > > product: a chair. And the result was an exquisite piece of furniture, > > albeit at a very high price, and very low volume (unless you hired a > > lot of one man shops at the same time). > > > Circuit designers are no different (being one myself, dating back to > > those "I can do that function in one less part" days gone by). But the > > target has changed. We no longer need a chair, we need a stadium full > > of them. And we need the elevators, climate control, fire suppression, > > lighting, and all the other support systems, to go along with them. > > > Perhaps we should take a step back, and look at what we really need > > (hint: a place for a lot of people to watch an event, while seated > > most of the time). Now I can optimize my stadium to recognize that all > > of my seats don't need to be finely crafted pieces of furniture. But I > > don't know that until I focus on the requirements: "What must my > > project do?" =A0So, instead of finding a way to describe the project as > > a collection of specific chairs, elevators and fire extinguishers, we > > need to describe it as a set of desired behaviors, and then, through > > some process (hopefully semi-automated), convert that description into > > an optimized design for the stadium. Could the craftsman and his tools > > have done that? > > > What do you want from the tools, a collection of exquisitely crafted > > chairs, or an efficient stadium? > > This analogy suggests the need for a compromise, which I think isn't > there. > > I don't see a case where the schematic entry craftsman can > realistically hope to beat the guy with the HDL tools. For example, > for smallish designs, it can be shown that logic synthesis can > generate a solution close to the optimum, *regardless* of the quality > of the starting point. The craftsman can draw any pictures he wants, > even if the tool guy writes the worst possible code, the synthesis > result will still be as good or better. > > Of course, for realistic, larger designs, the structure of the > input code becomes more and more significant. But thanks to > powerful heuristics, local optimization algorithms, and the > ability to recognize higher level structures, this is a > gradual process. In contrast, the craftsman's ability to > cope with complexity quickly detoriates beyond a certain > point. As a result, he has to rely on logic-wise inefficient > strategies, such as excessive hierarchy. > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0 Python as a HDL:http://www.myhdl.org > =A0 =A0 VHDL development, the modern way:http://www.sigasi.com > =A0 =A0 Analog design automation:http://www.mephisto-da.com > =A0 =A0 World-class digital design:http://www.easics.com- Hide quoted tex= t - > > - Show quoted text - I've seen too many examples where a bit more performance can be obtained by either tweaking the code, or "hard-coding" the solution. They are getting fewer and farther between, but they are still there. My point was that the extra performance is seldom, but not never, needed, and on a larger scale, letting the synthesis tool do the heavy lifting results in a better overall design MOST of the time. There're ain't no 100% solutions. If you try to hard code 100%, you lose; if you try to let the synthesis tool do 100%, you lose. Compromise is necessary. Andy From newsfish@newsfish Fri Feb 3 13:09:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c17g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 07:04:22 -0800 (PST) Organization: http://groups.google.com Lines: 73 Message-ID: <7a3d3125-07cf-4434-b484-cdeecb444339@c17g2000prm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292339095 23985 127.0.0.1 (14 Dec 2010 15:04:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:04:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c17g2000prm.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4527 On Dec 13, 11:32=A0pm, rickman wrote: > > I won't argue that, both of these will utilize the carry out of an > adder. =A0But that may or may not be the same adder I am using to update > count with. =A0I have looked at the logic produced and at some time > found two, apparently identical adder chains used, one of which had > all outputs unconnected other than the carry out of the top and the > other used the sum outputs to feed the register with the top carry > ignored. =A0Sure, there may have been something about my code that > prevented these two adders being merged, but I couldn't figure out > what it was. I have very seldom have that problem (two adders), and when I do, the reason (usually some extra condition on one adder that was not there on the other) is easily found and fixed. To be fair, the synthesis tools do not always implement a simple carry chain for either, but what they do implement is at least as fast and compact as a simple carry chain. > > I see a number of posts that don't really get what I am trying to > say. =A0I'm not arguing that you can't do what you want in current > HDLs. =A0I am not saying I want to use something similar to assembly > language to provide the maximum optimization possible. =A0I am saying I > find it not infrequent that HDL gives nothing close to optimal results > because the coding style required was not obvious. =A0I'm saying that it > seems like it should be easier to get the sort of simple structures > that are commonly used without jumping through hoops. I think "obvious" is related closely to the experience level of the observer. What appears obvious to me may not be obvious (yet) to you. > > Heck, reading the Lattice HDL user guide (not sure if that is the > actual name or not) they say you shouldn't try to infer memory at all, > instead you should instantiate it! =A0Memory seems like it should be so > easy to infer... Either their documentation is woefully out of date, or their synthesis tool is far from the state of the industry. > > I don't know Verilog that well, but I do know VHDL is a pig in many > ways. =A0It just seems like it could have been much simpler rather than > being such a pie-in-the-sky language. > Trust me; about 18 years ago, I was in exactly the same boat WRT to VHDL synthesis. Why do I need this much "stuff" to do what I can do in a sheet of schematics, and know without hardly thinking about it that it is correct? And at the time, the synthesis tools were not nearly as good as they are now, and FPGA performance was also not nearly as good, so much more of my typical design work needed to be done at a lower level. But sythesis and FPGA performance are now vastly superior to what they were then, and I can do the vast majority of a design without having to deal too much at the gates and flops level. It is a difficult paradigm to embrace when you come from a structural, schematic based design background. As for whether Verilog might work better for you, perhaps. I know I could not be nearly as productive with the constraints of what you cannot do in verilog at the higher levels of abstraction. Something like the fixed and floating point capabilities of VHDL is completely beyond the capabilities of verilog without major changes to the language, but all it took was a couple of packages in VHDL. The only problem any synthesis tools had with it was tied to the fact that they assumed (improperly) that only non-negative indices would ever be used for vectors. Andy From newsfish@newsfish Fri Feb 3 13:09:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!postnews.google.com!35g2000prt.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Using integers for counters in synthesis Date: Tue, 14 Dec 2010 07:04:39 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: References: <3eaf569e-5cb1-49e9-bff5-da7484dea87e@y19g2000prb.googlegroups.com> <633a4a29-f467-4b0d-b25e-8a38f0a5a9e2@p38g2000vbn.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292339111 12332 127.0.0.1 (14 Dec 2010 15:05:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:05:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 35g2000prt.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4528 On 13 d=E9c, 10:23, Martin Thompson wrote: > rickman writes: > > How exactly would my simulation be different from synthesis if I used > > a max of 200 for a counter? =A0If my simulation tries to increment the > > counter past 200 it stops! =A0That would not be an issue of different > > results, that would be my simulation failing to complete! =A0If my usag= e > > of the counter never pushes it past 200, then the simulation and synth > > match. > > OK, yes, I think I expressed myself badly :) > > I was trying to talk about unexpected behaviour, and confused the > issue by talking about mismatches. =A0As I said to Jan, if the > simulation doesn't test far enough, one might get different behaviour > to what one (might) expect (however innaccurate that expectation may be). > > > I think people are making far too big of an issue about this. =A0An HDL > > is supposed to be describing hardware, hence the name HDL. =A0If you > > take the position that the simulation and synthesis should always > > match 10% you can never design anything real. =A0 > > =A0 =A0 =A0 =A0 ^^^ > I assume you mean 100% there? > > > If I have a counter that is only needed for values of 200 or less > > and I don't care what happens when the value is over 200, then case > > 2 is perfectly ok. > > Quite so, I never intended to say anything other. > > > > > The OP has not responded, but I think he is just asking what the > > synthesizer does. =A0I don't think his issue is about what the "correct= " > > thing to do is. > > On re-reading the OP with that in mind, I agree. > > Sorry for any confusion caused! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.co.uk/capabilities/39-electronic-hardware Thnaks for the answers. My question was mostly out of curiosity, I tried it with ISE and I got a regular 8-bit wrapround counter. From newsfish@newsfish Fri Feb 3 13:09:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i41g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 07:57:07 -0800 (PST) Organization: http://groups.google.com Lines: 122 Message-ID: <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292342228 18999 127.0.0.1 (14 Dec 2010 15:57:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 15:57:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i41g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4529 On Dec 14, 3:54=A0am, Tricky wrote: > On Dec 14, 5:32=A0am, rickman wrote: > > > > > On Dec 13, 12:31=A0pm, Andy wrote: > > > > On Dec 11, 10:44=A0am, Brian Drummond > > > wrote: > > > > > >What I mean is, if I want a down counter that uses the carry out t= o > > > > >give me an "end of count" flag, why can't I get that in a simple a= nd > > > > >clear manner? =A0 > > > > > Here the issue appears to be how to get at the carry out of a count= er... > > > > the syntax of integer arithmetic doesn't provide an easy way to do = that by > > > > default, in any language I know (other than assembler for pre-RISC = CPUs, with > > > > their flag registers). > > > > > It seems to me that you have two choices ... > > > > (1) implement an n-bit counter, and augment it in some way to recre= ate the carry > > > > out (unfortunately you are fighting the synthesis tool in the proce= ss) > > > > > (2) implement an n+1 bit counter, with the excess bit assigned to t= he carry, and > > > > trust the synthesis tool to eliminate the excess flip-flop at the o= ptimisation > > > > stage... > > > > > I am willing to guess the second approach would be simpler. > > > > I have found the 1st approach far simpler, by using a natural subtype > > > for the counter. Then (count - 1 < 0) is the carry out for a down > > > counter. Similarly, (count + 1 > 2**n-1) is the carry out for an n bi= t > > > up counter. No fighting required. > > > I won't argue that, both of these will utilize the carry out of an > > adder. =A0But that may or may not be the same adder I am using to updat= e > > count with. =A0I have looked at the logic produced and at some time > > found two, apparently identical adder chains used, one of which had > > all outputs unconnected other than the carry out of the top and the > > other used the sum outputs to feed the register with the top carry > > ignored. =A0Sure, there may have been something about my code that > > prevented these two adders being merged, but I couldn't figure out > > what it was. > > > I see a number of posts that don't really get what I am trying to > > say. =A0I'm not arguing that you can't do what you want in current > > HDLs. =A0I am not saying I want to use something similar to assembly > > language to provide the maximum optimization possible. =A0I am saying I > > find it not infrequent that HDL gives nothing close to optimal results > > because the coding style required was not obvious. =A0I'm saying that i= t > > seems like it should be easier to get the sort of simple structures > > that are commonly used without jumping through hoops. > > > Heck, reading the Lattice HDL user guide (not sure if that is the > > actual name or not) they say you shouldn't try to infer memory at all, > > instead you should instantiate it! =A0Memory seems like it should be so > > easy to infer... > > > I don't know Verilog that well, but I do know VHDL is a pig in many > > ways. =A0It just seems like it could have been much simpler rather than > > being such a pie-in-the-sky language. > > > Rick > > From all this reading, Im guessing its not a problem with the language > you have, its more the synthesisors. > > So my two thoughts: > > 1. Try AHDL - its pretty explicit (but you'll be stuck with Altera). > 2. Instead of getting pissed off with the tools and pretending its an > HDL problem, how about raising the issue with the vendors and asking > them why they've done it the way the have. > > Personally, I have never had too much of a problem with the tools. The > Firmware works as I intend. Im not usually interested in the detail > because it works, it ships, the customer pays and we make a profit. I > dont care if a counter has used efficient carry out logic or not - it > works and thats all the customer cares about. When its working, or I > have fit problems I can then go into the finer detail. Ok, so there ARE times when you care if the synthesis uses two carry chains instead of one or if it used a set of LUTs to check terminal case rather than the carry chain. You are just saying that is not so often. That's not the same as saying, "It works, it ships". The same is true for most people I'm sure and I expect no small number of them virtually never look past the HDL. But when you do need speed or minimal area this can be important. I recently did a design where I had to cram five pounds of logic into a 4 pound FPGA. It ended up working, but I had to optimize every module. That worked out ok for the most part as I typically test bench each module anyway, so I just had to do a synthesis on it as well and work the code to get a good size result. That is how I found things like double carry chains, etc. That is also why I am now wondering why we have a language that is so far removed from the end product. I don't agree that this is a matter for the synthesis vendors. Like I said somewhere else, if you want a particular solution, the vendors tell you to instantiate. Instantiation is very undesirable since it is not portable across vendors and often not portable across product lines within a vendor! The language is flexible, that's for sure. But it seems to be flexible without purpose. Many of the changes currently being suggested in VHDL is to provide an easier to use language by getting a bit closer to what engineers want to use it for. I just think that in many ways the language is way too far removed from what we want to do with it. Rick From newsfish@newsfish Fri Feb 3 13:09:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q8g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 10:47:51 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292352471 12618 127.0.0.1 (14 Dec 2010 18:47:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 18:47:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q8g2000prm.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4530 The last time I had to cram too much logic into too little FPGA, I optimized the architecture, not the implementation. Among other changes, I took a half dozen separate UARTs, and replaced them with a six channel time-division-multiplexed UART using distributed RAM (it could have been a sixteen channel UART for virtually the same amount of resources excluding IO). Each channel still had independent baud rate, word length, parity, #stop bits, interrupts, etc. The design placed and routed in no time, with plenty of resources to share (it had been about 125% utilization). The reason I bring this up is that often we have challenges that are better addressed at the architectural level, rather than the implementation level. In these cases, a description farther above the gates and flops is preferable, becuase it is easier to re-work. You can bet I did not instantiate any RAMs in that design! That is not to say that it is never necessary to deal with the gates and flops (and carry chains, etc.). Sometimes we do, but it is relatively rare. So we rarely need a language that is "closer to the end product", and we often need a language that allows us to design at a higher level. I'm not really sure exactly what you want in your new flavor of HDL. Do you have any specific ideas? How would you make it closer to the end product? Andy From newsfish@newsfish Fri Feb 3 13:09:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!ecngs!feeder2.ecngs.de!news.netcologne.de!ramfeed1.netcologne.de!news.tele.dk!feed118.news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 14 Dec 2010 20:16:12 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> In-Reply-To: <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 34 Message-ID: <4d07c27b$0$14258$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: d7bf9db0.news.skynet.be X-Trace: 1292354171 news.skynet.be 14258 91.177.199.237:46068 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4531 Andy wrote: > The last time I had to cram too much logic into too little FPGA, I > optimized the architecture, not the implementation. Among other > changes, I took a half dozen separate UARTs, and replaced them with a > six channel time-division-multiplexed UART using distributed RAM (it > could have been a sixteen channel UART for virtually the same amount > of resources excluding IO). Each channel still had independent baud > rate, word length, parity, #stop bits, interrupts, etc. The design > placed and routed in no time, with plenty of resources to share (it > had been about 125% utilization). > > The reason I bring this up is that often we have challenges that are > better addressed at the architectural level, rather than the > implementation level. In these cases, a description farther above the > gates and flops is preferable, becuase it is easier to re-work. You > can bet I did not instantiate any RAMs in that design! > > That is not to say that it is never necessary to deal with the gates > and flops (and carry chains, etc.). Sometimes we do, but it is > relatively rare. So we rarely need a language that is "closer to the > end product", and we often need a language that allows us to design at > a higher level. Finally a breath of fresh air :-) Thanks for sharing a great story that should remind all of us where the true opportunities for optimization are to be found. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:09:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!w18g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 14:40:04 -0800 (PST) Organization: http://groups.google.com Lines: 64 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 108.8.13.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292366404 6336 127.0.0.1 (14 Dec 2010 22:40:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Dec 2010 22:40:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w18g2000vbe.googlegroups.com; posting-host=108.8.13.125; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4532 On Dec 14, 1:47=A0pm, Andy wrote: > The last time I had to cram too much logic into too little FPGA, I > optimized the architecture, not the implementation. Among other > changes, I took a half dozen separate UARTs, and replaced them with a > six channel time-division-multiplexed UART using distributed RAM (it > could have been a sixteen channel UART for virtually the same amount > of resources excluding IO). Each channel still had independent baud > rate, word length, parity, #stop bits, interrupts, etc. The design > placed and routed in no time, with plenty of resources to share (it > had been about 125% utilization). > > The reason I bring this up is that often we have challenges that are > better addressed at the architectural level, rather than the > implementation level. In these cases, a description farther above the > gates and flops is preferable, becuase it is easier to re-work. You > can bet I did not instantiate any RAMs in that design! > > That is not to say that it is never necessary to deal with the gates > and flops (and carry chains, etc.). Sometimes we do, but it is > relatively rare. So we rarely need a language that is "closer to the > end product", and we often need a language that allows us to design at > a higher level. > > I'm not really sure exactly what you want in your new flavor of HDL. > Do you have any specific ideas? How would you make it closer to the > end product? > > Andy You keep saying things like "a description farther above the gates and flops is preferable". I have not said I want to place LUTs and FFs. I would like to *know* what the logic will be for a given piece of code without having to run it through the tool and wading through a machine drawn schematic. I am all in favor of a language that allows higher level constructs. But that does not require that visibility to and knowledge of the lower levels be blocked. The current languages are much like C compilers in that the take entire design, break it down to its lowest level and then builds it back up in a way that it chooses. I think that philosophy is wrong. I don't think I need to work with total abstraction to be effective as a designer. Ray Andraka has made a career of designing efficient designs in an efficient way. He uses VHDL, but he uses a lot of instantiation, which to him is very much like written schematics. That is not what I want. I wish I could tell you how I'd like to see this solved. If I could do that, I'd likely start a company doing it. I guess it would be something like instantiation but without all the hassle of instantiation at the VHDL level. Heck, maybe what I am trying to describe is C? or maybe even Forth? I have thought before that Forth would make an interesting HDL. It is very hierarchical and it most likely could support very efficient simulation by compiling the original program to native machine code, but with extremely fast compiles too. I was hoping to get some input from others on this rather than a lot of reasons why the current HDLs are so good. I know their strengths, but I can also see their weaknesses. That is what I am discussing here, the weaknesses. Rick From newsfish@newsfish Fri Feb 3 13:09:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 16:34:36 -0800 Lines: 15 Message-ID: <8mqgorFls9U1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9GCVCfWB2uNssNa1VyTNJQkgTUqX2u6Kq1OO9jRoJjTxFVCsyl Cancel-Lock: sha1:co13jrYnwxsyF4Rjl1TEkiXiWzw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <20101213204033.7c01f784@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4533 On 12/13/2010 8:40 PM, Christopher Head wrote: > Problem: this might not have been a full bit-time since you started > sending the '1' stop bit! You never actually guarantee to wait for the > full stop bit to pass before accepting new data from the application in > the transmit data register! > > Or am I missing something? Note the source comment: -- reads anytime, expects smart,handshaking reader Click on waves or zoom for the sim details -- Mike From newsfish@newsfish Fri Feb 3 13:09:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Tue, 14 Dec 2010 21:39:50 -0800 Organization: solani.org Lines: 42 Message-ID: <20101214213950.4f7e9e1b@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mqgorFls9U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292391591 26078 eJwNyMEBwEAEBMCW4thFOXLov4RkngOl8LoRNCz27mOv1plwl9a5EGFP5DhPWmtYN/4QZFXpByAPET0= (15 Dec 2010 05:39:51 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Wed, 15 Dec 2010 05:39:51 +0000 (UTC) X-User-ID: eJwNysEBwCAIA8CVCiahjCNQ9x/B3vu4ZOqAKPDwAG3sb5mHSXvctSKLj++sROX/AxbzDhOnL/8hEBk= X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:lTUooLcDx/2bRytfz2OSHGU+gD0= X-NNTP-Posting-Host: eJwNxMkVADAEBcCWLB9POYj0X0IyhzF19gm4OezaFZUddEz+sog5RZWnzlmqRm8wCCVqTsh6FqsQsA== Xref: feeder.eternal-september.org comp.lang.vhdl:4534 On Tue, 14 Dec 2010 16:34:36 -0800 Mike Treseler wrote: > On 12/13/2010 8:40 PM, Christopher Head wrote: > > > Problem: this might not have been a full bit-time since you started > > sending the '1' stop bit! You never actually guarantee to wait for > > the full stop bit to pass before accepting new data from the > > application in the transmit data register! > > > > Or am I missing something? > > Note the source comment: > -- reads anytime, expects smart,handshaking reader > > Click on waves or zoom for the sim details > > -- Mike Sorry, I still don't see it. Looking at the write of 0x83 (the second write in the zoom example), I see the data going out over serialout_s, and I watch the txstate_v. There's a low between time 9900 and 10us for the start bit, then two bits of high time for bits 0 and 1, then a pile of low time, then you see serialout_s go high just before time 10200. That's bit 7 (MSb), which for data 0x83 is high. Looking down at txstate_v, it changes from "send" to "stop" right at the start of that bit, then changes from "stop" to "idle" one bit time later. But that wasn't the stop bit, that was data bit 7! The stop bit has only just started, right where txstate_v became "idle". If the application polls the status register right then, because txstate_v=idle, it will see TxReady asserted, indicating the transmitter is willing to accept another data byte. If it immediately sends that next byte, the start bit will happen only a cycle or two later. With only three clock cycles per bit, the system probably can't actually turn around fast enough for the start bit to trample on the stop bit, but it could with a faster system clock or lower baud rate. Or did the idea of a "smart, handshaking reader" mean something else? I took it to mean that the application should poll the status register and wait for TxReady before sending data. Chris From newsfish@newsfish Fri Feb 3 13:09:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q18g2000vbm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 00:55:49 -0800 (PST) Organization: http://groups.google.com Lines: 88 Message-ID: <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292403349 29479 127.0.0.1 (15 Dec 2010 08:55:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 08:55:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbm.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4535 On Dec 14, 10:40=A0pm, rickman wrote: > On Dec 14, 1:47=A0pm, Andy wrote: > > > > > The last time I had to cram too much logic into too little FPGA, I > > optimized the architecture, not the implementation. Among other > > changes, I took a half dozen separate UARTs, and replaced them with a > > six channel time-division-multiplexed UART using distributed RAM (it > > could have been a sixteen channel UART for virtually the same amount > > of resources excluding IO). Each channel still had independent baud > > rate, word length, parity, #stop bits, interrupts, etc. The design > > placed and routed in no time, with plenty of resources to share (it > > had been about 125% utilization). > > > The reason I bring this up is that often we have challenges that are > > better addressed at the architectural level, rather than the > > implementation level. In these cases, a description farther above the > > gates and flops is preferable, becuase it is easier to re-work. You > > can bet I did not instantiate any RAMs in that design! > > > That is not to say that it is never necessary to deal with the gates > > and flops (and carry chains, etc.). Sometimes we do, but it is > > relatively rare. So we rarely need a language that is "closer to the > > end product", and we often need a language that allows us to design at > > a higher level. > > > I'm not really sure exactly what you want in your new flavor of HDL. > > Do you have any specific ideas? How would you make it closer to the > > end product? > > > Andy > > You keep saying things like "a description farther above the gates and > flops is preferable". =A0I have not said I want to place LUTs and FFs. > I would like to *know* what the logic will be for a given piece of > code without having to run it through the tool and wading through a > machine drawn schematic. > > I am all in favor of a language that allows higher level constructs. > But that does not require that visibility to and knowledge of the > lower levels be blocked. > > The current languages are much like C compilers in that the take > entire design, break it down to its lowest level and then builds it > back up in a way that it chooses. =A0I think that philosophy is wrong. > I don't think I need to work with total abstraction to be effective as > a designer. =A0Ray Andraka has made a career of designing efficient > designs in an efficient way. =A0He uses VHDL, but he uses a lot of > instantiation, which to him is very much like written schematics. > That is not what I want. > > I wish I could tell you how I'd like to see this solved. =A0If I could > do that, I'd likely start a company doing it. =A0I guess it would be > something like instantiation but without all the hassle of > instantiation at the VHDL level. =A0Heck, maybe what I am trying to > describe is C? =A0or maybe even Forth? =A0I have thought before that Fort= h > would make an interesting HDL. =A0It is very hierarchical and it most > likely could support very efficient simulation by compiling the > original program to native machine code, but with extremely fast > compiles too. > > I was hoping to get some input from others on this rather than a lot > of reasons why the current HDLs are so good. =A0I know their strengths, > but I can also see their weaknesses. =A0That is what I am discussing > here, the weaknesses. > > Rick Personally, I still dont see why this is needed, or how it would be done. HDLs offer the user the option to either abstract their designs with behavioural code or create a schematic like design with instantiations, or a mixture of both. The big problem with what you are suggesting is that Different vendors, and different parts across the same vendor, have LUTs, FFS, multipliers etc that behave differently, with different number of IOs. To cover all cases, the only way to ensure the same code works across a range is with behavioural code. The only way to know what will come out in advance is either with experience or instantiation. To get what you are suggesting would require all vendors to produce their FPGAs with the same base parts, but that will never happen. Vendors provide code templates for various things, so you should know what you are getting with these. Recently, the only things I have had to directly instantiate are Dual clock dual port RAMs, because Altera still cannot infer them from code. Im pretty sure that one day they will. From newsfish@newsfish Fri Feb 3 13:09:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!30g2000yql.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 01:55:55 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: <1c90bd70-a381-4a05-901c-24eb095d9a93@30g2000yql.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292406955 12518 127.0.0.1 (15 Dec 2010 09:55:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 09:55:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 30g2000yql.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4536 > I don't have time to draw a diagram, but here is some code. That makes it easier. Here=92s the XST RTL schematic of the circuit: http://www.mypicx.com/uploadimg/1078299247_12152010_1.jpg And a wave diagram: http://www.mypicx.com/uploadimg/694346392_12152010_2.jpg Any particular reason for using the negative edge in the Scfg_Sync process? I used the positive edge. data_in is clocked on the positive sysclk edge without enable. data_out is clocked on the positive scfg_str edge when scfg_clk_en is high. Am I using this in a way you recognize? /B From newsfish@newsfish Fri Feb 3 13:09:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z17g2000prz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 06:22:15 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <26d457c7-6cfa-4eb9-8be9-9347b1e74989@fu15g2000vbb.googlegroups.com> <1c90bd70-a381-4a05-901c-24eb095d9a93@30g2000yql.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292422936 26508 127.0.0.1 (15 Dec 2010 14:22:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 14:22:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000prz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4537 On Dec 15, 4:55 am, Beppe wrote: > > I don't have time to draw a diagram, but here is some code. > > That makes it easier. Here=92s the XST RTL schematic of the circuit: > > http://www.mypicx.com/uploadimg/1078299247_12152010_1.jpg > > And a wave diagram: > > http://www.mypicx.com/uploadimg/694346392_12152010_2.jpg This is why I hate these machine drawn schematics. The machine has no clue about the logical flow. Scfg_StbLatch should be in the same line with the other blocks clearly showing the flow with the feedback loop back to the other clock domain. The feedback loop is what makes it work (each side is not armed until the other acknowledges) and the following logic is just to reconstruct the enable or clock. > Any particular reason for using the negative edge in the Scfg_Sync > process? I used the positive edge. data_in is clocked on the positive > sysclk edge without enable. data_out is clocked on the positive > scfg_str edge when scfg_clk_en is high. > > Am I using this in a way you recognize? Yes, Scfg_Sync was required to use the falling edge in my design as it is an external interface. This looks exactly as it should look for a clock enable circuit. Metastability precautions are required for the signal Scfg_StbLatch. The only other note is to make sure the data is held stable long enough for it to be registered in the destination domain. This may require a register in the data path driven by SysClk. There are a lot of details dependent on the relative clock speeds. If you need to convey a clock enable just add that to the Scfg_SysClk register. Rick From newsfish@newsfish Fri Feb 3 13:09:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 19:02:09 +0100 Lines: 28 Message-ID: <8mse51FtmjU1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Dt+uXbgbID+MqghcRXH2aQoak80YCtBTyoMn1c/kZQmDiZwiO7 Cancel-Lock: sha1:cVDzXo4hbmqV/2Cyfw2x7QY1eTY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <20101213204033.7c01f784@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4538 On 12/14/2010 5:40 AM, Christopher Head wrote: > On Mon, 13 Dec 2010 00:23:30 +0100 > Alessandro Basili wrote: > >> http://mysite.ncnetwork.net/reszotzl/uart.vhd >> >> Al >> >> > > Am I missing something, or is the transmitter slightly flawed in this > code? I seem to see the following: [snip] > 4. From this moment, if the application queries the status register, > you will see that TxState_v is IDLE and hence report transmitter ready. I believe only 1 clock after TxState_v is IDLE, hence you have a 1 bit stop. > The application could thus immediately strobe another byte of data into > the transmit data register. Then tx_state will transition to TxState_v > = START and, on the next clock, set serial_out_v to '0'. > The application needs to read the 0x04 as status register and if you check the zoom file you find that read_data_v is 0x04 only one clock after the TxState_v is idle. Hence the 1 bit stop is guaranteed. Al From newsfish@newsfish Fri Feb 3 13:09:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!216.196.98.146.MISMATCH!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n32g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 10:40:51 -0800 (PST) Organization: http://groups.google.com Lines: 26 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292438452 3617 127.0.0.1 (15 Dec 2010 18:40:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 18:40:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n32g2000pre.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4539 To be able to "know" what hardware you are going to get requires having a language and description that, from the same code, will always produce the exact same logic, regardless of required performance, space, and target architecture. Unfortunately it also means having a language and description which will not produce reasonably optimal hardware over all combinations of those same constraints, given the same code. You can't have it both ways. I think we may have a disconnect with regards to the meaning of "higher level constructs". If you mean things like hierarchy, etc. I agree that it should not get in the way of a deterministic hardware description (and I don't think it does, though your methods of using the language may not be optimal for this). However, I take "higher level constructs" as being those that support a behavioral description ("what does the circuit do?", not "what is the circuit?"), with necessarily less direct mapping to implemented hardware. It is the use of these constructs that provides the tremendous increase in productivity over past methods (more primitive languages and schematics). You would not consider creating a word processor or spreadsheet in assembler, so why would you create a complex FPGA design with what amounts to a netlist? Andy From newsfish@newsfish Fri Feb 3 13:09:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!news.buerger.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 20:50:49 +0100 Lines: 118 Message-ID: <8mskgpF4joU1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-Trace: individual.net NmAUBzjkATvTLM/xQEMAow2+cbHD/rc9ZbSfCitpc1zP9HE35n Cancel-Lock: sha1:+DnXFJYXDQqgecW/B15BEW19HX8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4540 On 12/14/2010 4:56 AM, rickman wrote: [snip] >> I am sorry but I disagree with you on this point. There are "good >> practices" that help a lot in guaranteeing the quality of your project. > > I never said testing isn't useful. I said that testing can't assure > that something works unless you test every possible condition and that > is not possible in an absolute sense. > I don't get that. What you call as "every possible condition" is intended as every possible state of a particular set of logic. If your logic cannot be described as a well defined number of states then I agree that testing will never be enough (but in this case I suggest a rework of the design). If your states are not controllable (i.e. by an external control signal) then there's little you can do in testing. If your states are even not observable then I believe you are "doomed" (as somebody said earlier...). > Besides, you snipped the OP's comment I was responding to... > > "the design seems to be working fine in hardware although I havent > made any extensive tests yet." > I snipped the OP's comment because didn't add anything that wasn't already said in your sentence. > The problem we are discussing is ***exactly*** the sort of thing you > may not find in testing. The way the OP has constructed the circuit > it may work in 99.99% of the systems he builds. Or it may work 99.99% > of the time in all of the systems. But testing can't validate timing > since you can't control all of the variables. > This is why the way OP constructed the circuit was suboptimal and that is why it was suggested not to use a generated clock, but an enable signal (or even clock the UART with the original 25MHz clock). > The only thing testing can really do is to verify that your design > meets your requirements... if your requirements are testable! If something cannot be testable, how would you accept those requirements? And how can than be said the system doesn't work? according to which requirement violation? > >> I believe that coding is just part of the story. Having the possibility >> to test the design by a different team from the designers one will make >> a huge difference. > > "a huge difference"... I understand there are lots of ways to improve > testing, but that doesn't change the fundamental limitation of > testing. > The fundamental limitation of testing are most probably due to a very poor description of the device under test. That is why documentation should be the first step in a work flow, rather then the last one where the designer tend to leave out all the "unnecessary" details which eventually lead to misunderstanding. How hard is to test one single flip-flop? Not much, only because if fully described. >> >> http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > > I'm not sure what to say about this article. It is actually a bit > shallow in my opinion. But it also contains errors! Much of it is > really just the opinion of the author. > Could you please post the errors? Since I haven't found them, most probably your reading was deeper than mine and it would be very helpful to me. The author not only gives an opinion, it lays down an approach which is at a higher level of abstraction than the flops and gates. > > I think that terms like "good practices" are some of the least useful > concepts I've ever seen. First, where are "good practices" defined? In many books, standards, proceedings, articles and you may be lucky that your company has already defined a set of them. > Without a clear, detailed definition of the term, it doesn't > communicate anything. Usually it is used to mean "what I do". It may > be defined within a company, in some limited ways it may be defined > within a sector. But in general this is a term that has little > meaning as used by most people. This is much like recommending to > design "carefully". I can't say how many times I have seen that word > used in engineering without actually saying anything. > Usually it means "what most of the people do" as opposed of what you suggested. Of course circumstances and requirements maybe some how very demanding but an alternative architectural approach will surely have an higher impact. > >>> I recently discussed a multiple clock design with my customer. He >>> said he had more than 50 clocks in this design and wanted details on >>> how I deal with syncing multiple clock domains. I explained that I do >>> all my work in one clock domain and use a particular logic circuit to >>> transport clocks, enables and data into that one domain. I solve the >>> synchronization problem once at the interface and never have to worry >>> about it again. >> >> I would recommend an alternative to the 50 clocks domains, instead. > > What alternative would that be??? Is that different than the solution > I recommended? > As in the OP example, instead of suggesting how to control the timing of the clk_250k I would recommend not to use it at all (that means one clock less). > Rick From newsfish@newsfish Fri Feb 3 13:09:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w21g2000vby.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 13:35:19 -0800 (PST) Organization: http://groups.google.com Lines: 156 Message-ID: <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292448920 14547 127.0.0.1 (15 Dec 2010 21:35:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 21:35:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w21g2000vby.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4541 On Dec 15, 2:50=A0pm, Alessandro Basili wrote: > On 12/14/2010 4:56 AM, rickman wrote: > > I never said testing isn't useful. =A0I said that testing can't assure > > that something works unless you test every possible condition and that > > is not possible in an absolute sense. > > I don't get that. What you call as "every possible condition" is > intended as every possible state of a particular set of logic. If your > logic cannot be described as a well defined number of states then I > agree that testing will never be enough (but in this case I suggest a > rework of the design). > If your states are not controllable (i.e. by an external control signal) > then there's little you can do in testing. If your states are even not > observable then I believe you are "doomed" (as somebody said earlier...). If you are only talking about testing logic, yes, you can do that exhaustively assuming a few conditions. But testing in general takes on a lot more than that and the condition the OP was not a logic issue, rather it would depend on uncontrolled variables and potentially very intermittent. > > Besides, you snipped the OP's comment I was responding to... > > > "the design seems to be working fine in hardware although I haven t > > made any extensive tests yet." > > I snipped the OP's comment because didn't add anything that wasn't > already said in your sentence. It gave the context. Without the relevant context, which seems to be the issue we are not communicating on, the points mean nothing. > > The problem we are discussing is ***exactly*** the sort of thing you > > may not find in testing. =A0The way the OP has constructed the circuit > > it may work in 99.99% of the systems he builds. =A0Or it may work 99.99= % > > of the time in all of the systems. =A0But testing can't validate timing > > since you can't control all of the variables. > > This is why the way OP constructed the circuit was suboptimal and that > is why it was suggested not to use a generated clock, but an enable > signal (or even clock the UART with the original 25MHz clock). > > > The only thing testing can really do is to verify that your design > > meets your requirements... if your requirements are testable! > > If something cannot be testable, how would you accept those > requirements? And how can than be said the system doesn't work? > according to which requirement violation? > > > > >> I believe that coding is just part of the story. Having the possibilit= y > >> to test the design by a different team from the designers one will mak= e > >> a huge difference. > > > "a huge difference"... I understand there are lots of ways to improve > > testing, but that doesn't change the fundamental limitation of > > testing. > > The fundamental limitation of testing are most probably due to a very > poor description of the device under test. That is why documentation > should be the first step in a work flow, rather then the last one where > the designer tend to leave out all the "unnecessary" details which > eventually lead to misunderstanding. How hard is to test one single > flip-flop? Not much, only because if fully described. > > > > >>http://www.designabstraction.co.uk/Articles/Common%20HDL%20Errors.PDF > > > I'm not sure what to say about this article. =A0It is actually a bit > > shallow in my opinion. =A0But it also contains errors! =A0Much of it is > > really just the opinion of the author. > > Could you please post the errors? Since I haven't found them, most > probably your reading was deeper than mine and it would be very helpful > to me. > The author not only gives an opinion, it lays down an approach which is > at a higher level of abstraction than the flops and gates. I don't have time to do that now. Maybe I can come back to this over the weekend. > > I think that terms like "good practices" are some of the least useful > > concepts I've ever seen. =A0First, where are "good practices" defined? > > In many books, standards, proceedings, articles and you may be lucky > that your company has already defined a set of them. My experience is that most "good practices" are really just experience. When they are "codified" they often loose their impact because of being applied poorly. Yes, "good practices" is clearly good. But it is a term that has no real definition except within some specific context and so is not really useful in a conversation about a concrete issue. > > Without a clear, detailed definition of the term, it doesn't > > communicate anything. =A0Usually it is used to mean "what I do". =A0It = may > > be defined within a company, in some limited ways it may be defined > > within a sector. =A0But in general this is a term that has little > > meaning as used by most people. =A0This is much like recommending to > > design "carefully". =A0I can't say how many times I have seen that word > > used in engineering without actually saying anything. > > Usually it means "what most of the people do" as opposed of what you > suggested. Of course circumstances and requirements maybe some how very > demanding but an alternative architectural approach will surely have an > higher impact. I see no value in doing "what most people do". I have seen the same mistakes made over and over with people reciting their mantras. Mostly these mistakes are just time wasters, but they are mistakes none the less. I expect you will ask me for an example. One I see often is the poor application of decoupling caps on devices. Many people use all sorts of rules of thumb and claim that their rule must not be violated or you aren't using "good practices". Meanwhile the electric fields ignore their good practices and instead obey the laws of physics. > >>> I recently discussed a multiple clock design with my customer. =A0He > >>> said he had more than 50 clocks in this design and wanted details on > >>> how I deal with syncing multiple clock domains. =A0I explained that I= do > >>> all my work in one clock domain and use a particular logic circuit to > >>> transport clocks, enables and data into that one domain. =A0I solve t= he > >>> synchronization problem once at the interface and never have to worry > >>> about it again. > > >> I would recommend an alternative to the 50 clocks domains, instead. > > > What alternative would that be??? =A0Is that different than the solutio= n > > I recommended? > > As in the OP example, instead of suggesting how to control the timing of > the clk_250k I would recommend not to use it at all (that means one > clock less). I'm not sure we are communicating on this one. That is what I told my customer, use one clock on the inside and cross the clock domain at the interface. This often makes the design much simpler and in the customer's design allows the tools to figure out much simpler timing and routing constraints. Rick From newsfish@newsfish Fri Feb 3 13:09:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 13:46:53 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> NNTP-Posting-Host: 70.88.113.221 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292449614 20760 127.0.0.1 (15 Dec 2010 21:46:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 21:46:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prn.googlegroups.com; posting-host=70.88.113.221; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4542 On Dec 15, 1:40=A0pm, Andy wrote: > To be able to "know" what hardware you are going to get requires > having a language and description that, from the same code, will > always produce the exact same logic, regardless of required > performance, space, and target architecture. Unfortunately it also > means having a language and description which will not produce > reasonably optimal hardware over all combinations of those same > constraints, given the same code. You can't have it both ways. I don't think you conclusions come from the facts. An HDL can unambiguously describe a counter with a carry out and allow that counter and carry to implemented in any manner the device can support. If I am using a device that can't implement a counter, why would I attempt to describe a counter? How could any HDL code that counts possibly be portable in a system that can't implement a counter? > I think we may have a disconnect with regards to the meaning of > "higher level constructs". If you mean things like hierarchy, etc. I > agree that it should not get in the way of a deterministic hardware > description (and I don't think it does, though your methods of using > the language may not be optimal for this). Not only should hierarchical design not get in the way of deterministic design, it is mandatory, otherwise you *would* need to design every logic element. > However, I take "higher level constructs" as being those that support > a behavioral description ("what does the circuit do?", not "what is > the circuit?"), with necessarily less direct mapping to implemented > hardware. It is the use of these constructs that provides the > tremendous increase in productivity over past methods (more primitive > languages and schematics). You would not consider creating a word > processor or spreadsheet in assembler, so why would you create a > complex FPGA design with what amounts to a netlist? I think you are drawing too fine a line between behavioral and structural. I am not saying I want to design gates. I am saying I want to clearly know how my code will be implemented. No, I don't know exactly how this would be done, but like I've said before, when I figure it out, I'll start a company and get rich from it. The first step to developing something new is to realize that there is an opportunity. Some folks are trying to convince me that my editor is not adequate and I should consider another tool that "understands" the language. Before I will evaluate that, I have to recognize that I'm not happy with my editor. I think a lot of people are very complacent about their tools. I see things a bit differently. Rick From newsfish@newsfish Fri Feb 3 13:09:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e20g2000vbn.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Wed, 15 Dec 2010 14:36:57 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> NNTP-Posting-Host: 77.218.224.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292452621 1207 127.0.0.1 (15 Dec 2010 22:37:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Dec 2010 22:37:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e20g2000vbn.googlegroups.com; posting-host=77.218.224.36; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101027 Ubuntu/10.10 (maverick) Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4543 > As in the OP example, instead of suggesting how to control the timing of > the clk_250k I would recommend not to use it at all (that means one > clock less). What are you're arguments against using the clk_250k apart from having one clock less? clk_25 is only used for generating the clk_250k. No data is passing from the clk_25 domain to the clk_250k domain and clk_250k is put on a low skew global clock net. /B From newsfish@newsfish Fri Feb 3 13:09:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 17:03:51 -0800 (PST) Organization: http://groups.google.com Lines: 42 Message-ID: <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292461432 15719 127.0.0.1 (16 Dec 2010 01:03:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Dec 2010 01:03:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000yqe.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4544 On Dec 15, 3:46=A0pm, rickman wrote: > On Dec 15, 1:40=A0pm, Andy wrote: > > > To be able to "know" what hardware you are going to get requires > > having a language and description that, from the same code, will > > always produce the exact same logic, regardless of required > > performance, space, and target architecture. Unfortunately it also > > means having a language and description which will not produce > > reasonably optimal hardware over all combinations of those same > > constraints, given the same code. You can't have it both ways. > > I don't think you conclusions come from the facts. =A0An HDL can > unambiguously describe a counter with a carry out and allow that > counter and carry to implemented in any manner the device can > support. =A0If I am using a device that can't implement a counter, why > would I attempt to describe a counter? =A0How could any HDL code that > counts possibly be portable in a system that can't implement a > counter? I don't think you understand that knowing whether a carry output is used or not is almost worthless if you don't know which way that carry output should be created, which then gets us back to performance, resources, and target architectures. You have a pre-conceived notion that using a carry output will, in all cases of performance, resources, and target architecture, be an optimal solution. This is simply not true. Using my method (count - 1 < 0), I have seen the same synthesis tool, for the same target architecture, use the the built-in carry-chain output (shared), use combination of sub-carry outputs and LUTS, and just LUTS, depending on what it thought would be optimal (and when I checked them, I found it had made very good choices!) I would prefer the synthesis tools figure out for themselves that if I am testing the output of a down counter with count=3D0 (which is more readable/ understandable than count-1<0), it could use a carry out if it was optimal. I would really prefer that it figure out that, if count is not used anywhere else, it could translate a behavior of counting from 1 to n (which is even more readable/understandable) into a down counter from n-1 to zero (if doing so would be more optimal). But these are synthesis tool issues, not language issues. Andy From newsfish@newsfish Fri Feb 3 13:09:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Wed, 15 Dec 2010 21:30:54 -0800 Organization: solani.org Lines: 41 Message-ID: <20101215213054.2cdbe4d2@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292477455 6726 eJwNwoERADEEBMCWiBxSjuH0X8L/7MJcveM6/GJ/KRbHsue0CbHJN4znqISt0KaHNVpasrwfFg8Rkw== (16 Dec 2010 05:30:55 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Thu, 16 Dec 2010 05:30:55 +0000 (UTC) X-User-ID: eJwFwYEBwDAEBMCVCP4ZR7T2HyF3YVAMHQGPjYWJZLcS8C+rKcZhnX9wQ7c7a+bcAuE20Q8IFhCr X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:Vib3wtTiFvhcNSKbzQy9XsDfpno= X-NNTP-Posting-Host: eJwNx8EBwCAIA8CVEEyAcRBl/xHa+x2Mi+2b4MZgdKtzsvj+Vrlckah811JaPSas8xxHBHS1fxVoELU= Xref: feeder.eternal-september.org comp.lang.vhdl:4545 On Wed, 15 Dec 2010 19:02:09 +0100 Alessandro Basili wrote: > On 12/14/2010 5:40 AM, Christopher Head wrote: > > On Mon, 13 Dec 2010 00:23:30 +0100 > > Alessandro Basili wrote: > > > >> http://mysite.ncnetwork.net/reszotzl/uart.vhd > >> > >> Al > >> > >> > > > > Am I missing something, or is the transmitter slightly flawed in > > this code? I seem to see the following: > [snip] > > 4. From this moment, if the application queries the status register, > > you will see that TxState_v is IDLE and hence report transmitter > > ready. > > I believe only 1 clock after TxState_v is IDLE, hence you have a 1 > bit stop. > > > The application could thus immediately strobe another byte of data > > into the transmit data register. Then tx_state will transition to > > TxState_v = START and, on the next clock, set serial_out_v to '0'. > > > > The application needs to read the 0x04 as status register and if you > check the zoom file you find that read_data_v is 0x04 only one clock > after the TxState_v is idle. Hence the 1 bit stop is guaranteed. > > Al Each bit is actually three clocks wide. As I pointed out in my other message, you can't actually stomp on the stop bit at these particular choices of timing, but the UART code nowhere suggests that it's only usable with values of (clocks/baud) <= 3. Why else would tic_per_bit_g be a generic parameter instead of a constant? Chris From newsfish@newsfish Fri Feb 3 13:09:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!news2.glorb.com!postnews.google.com!15g2000vbz.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 06:00:52 -0800 (PST) Organization: http://groups.google.com Lines: 7 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292508052 22221 127.0.0.1 (16 Dec 2010 14:00:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Dec 2010 14:00:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 15g2000vbz.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4547 I haven't seen the code, but this would be an excellent place to use a range constraint on the generic tic_per_bit_g. Failing that, a concurrent assertion that verifies useable values of the generic(s) would work. It could actually work better than a range constraint if there are interdependencies between the values of multiple generics. Andy From newsfish@newsfish Fri Feb 3 13:09:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 12:12:40 -0800 Lines: 16 Message-ID: <8mva5lFvlqU1@mid.individual.net> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /Cc0sv9LVChCLcrveTT6OwWMipIzWG53z1CNRRfDbQC8RJ5oQv Cancel-Lock: sha1:8MYVysTExBxfxwKGGhmrteClhbg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <20101215213054.2cdbe4d2@is.invalid> Xref: feeder.eternal-september.org comp.lang.vhdl:4548 On 12/15/2010 9:30 PM, Christopher Head wrote: > Each bit is actually three clocks wide. As I pointed out in my other > message, you can't actually stomp on the stop bit at these particular > choices of timing, but the UART code nowhere suggests that it's only > usable with values of (clocks/baud)<= 3. Why else would tic_per_bit_g > be a generic parameter instead of a constant? This example works fine for baud rates slower than two ticks per bit. I left it a constant so I could play with it without having to explain it. Chris, you have the source and a testbench, so feel free to make any changes you like. My goal was only to demonstrate that variables may be used for synthesis of luts and flops. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:09:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder3.news.weretis.net!news.solani.org!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Thu, 16 Dec 2010 13:03:13 -0800 Organization: solani.org Lines: 26 Message-ID: <20101216130313.49b0eb3c@is.invalid> References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <8ml3riFgg9U2@mid.individual.net> <20101213204033.7c01f784@is.invalid> <8mse51FtmjU1@mid.individual.net> <20101215213054.2cdbe4d2@is.invalid> <8mva5lFvlqU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1292533394 16245 eJwFwYEBwDAEBMCVhPeNcQj2H6F3bjx8H+iEr+9W1kQoU29NU+KMFrtNDFCNRUNas4P3rf0sWxFh (16 Dec 2010 21:03:14 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Thu, 16 Dec 2010 21:03:14 +0000 (UTC) X-User-ID: eJwFwQENADAIAzBLI2cM5MAf/Et4yxMWVx4M53JlRVHrd57OlbzZ6EnHJLZRMiS7+YCt/BAaEKE= X-Newsreader: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Cancel-Lock: sha1:BPLWv2PbAztajh2i+5243SfJyTA= X-NNTP-Posting-Host: eJwFwQcBwEAIBDBLUGblcAz/Ej4xcfYOdXO1s0tMoAsD1AqdfDy121npGbo8GSNlRj9dEB5KCxIY Xref: feeder.eternal-september.org comp.lang.vhdl:4549 On Thu, 16 Dec 2010 12:12:40 -0800 Mike Treseler wrote: > On 12/15/2010 9:30 PM, Christopher Head wrote: > > > Each bit is actually three clocks wide. As I pointed out in my other > > message, you can't actually stomp on the stop bit at these > > particular choices of timing, but the UART code nowhere suggests > > that it's only usable with values of (clocks/baud)<= 3. Why else > > would tic_per_bit_g be a generic parameter instead of a constant? > > This example works fine for baud rates slower than two ticks per bit. > I left it a constant so I could play with it without having to > explain it. Chris, you have the source and a testbench, so feel free > to make any changes you like. My goal was only to demonstrate that > variables may be used for synthesis of luts and flops. > > -- Mike Treseler > Oh, sure, it didn't cause any trouble. I read the code out of curiosity, liked the style, and then noticed what I thought looked like a possible problem and wondered if anyone had seen it. So, no big deal :) Chris From newsfish@newsfish Fri Feb 3 13:09:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 13:36:53 +0100 Lines: 20 Message-ID: <8n13r2FdueU1@mid.individual.net> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net DXALSvhnTO7SU+HKjnR5hgsRU5AuI/uUFvq7IL1qvckZvivFtT Cancel-Lock: sha1:/cw2yivH9PhNx1p5ZfZ/Macz43o= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 In-Reply-To: <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4551 On 12/15/2010 11:36 PM, Beppe wrote: >> As in the OP example, instead of suggesting how to control the timing of >> the clk_250k I would recommend not to use it at all (that means one> clock less). > > What are you're arguments against using the clk_250k apart from having > one clock less? clk_25 is only used for generating the clk_250k. No > data is passing from the clk_25 domain to the clk_250k domain and > clk_250k is put on a low skew global clock net. > I believe the reason of having an additional clock should be motivated. All what I see reduces portability and invalidates a simple behavioral description, since you need to instance the low skew clock directly in your description. What would be your gain instead? The direct use of clk_25 in your uart suits perfectly and the argument to reduce the amount of power consumption on a bunch of flops (what, like 50???) is not worth the effort. > /B From newsfish@newsfish Fri Feb 3 13:09:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!c2g2000yqc.googlegroups.com!not-for-mail From: Beppe Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 05:43:26 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: <6a78e56f-76d9-40a7-8c30-dbec6d2730ca@c2g2000yqc.googlegroups.com> References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> <8n13r2FdueU1@mid.individual.net> NNTP-Posting-Host: 194.68.102.253 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1292593406 29588 127.0.0.1 (17 Dec 2010 13:43:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Dec 2010 13:43:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c2g2000yqc.googlegroups.com; posting-host=194.68.102.253; posting-account=vgXigAoAAAAe6bUw1rU8WaOnI_4E_A-J User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.7 (KHTML, like Gecko) Chrome/7.0.517.44 Safari/534.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4552 Well, I can see the point of using an enable instead of a divided clock even if this clock is on a low skew clock net. It=92s good design practice and you don=92t introduce an additional clock. Fine. However, I think you should always question good design practice and understand why it=92s better to do it the =93good=94 way rather than the unknown, unexplored, uncommon, etc. way. At least if you want to get some deeper understanding of the subject. Also, what was good design practice yesterday is not always good design practice today. E.g. Xilinx have changed their recommended coding styles quite a lot since the introduction of the 6-input LUTs. > I believe the reason of having an additional clock should be motivated. > All what I see reduces portability and invalidates a simple behavioral > description, since you need to instance the low skew clock directly in > your description. What would be your gain instead? The direct use of > clk_25 in your uart suits perfectly and the argument to reduce the > amount of power consumption on a bunch of flops (what, like 50???) is > not worth the effort. How would it reduce portability? The DCM has already reduced the portability and I don=92t see how the clock divider would reduce it even more. Well, I can agree that instantiating a design element somehow invalidates a behavioral description (if that=92s what you meant), but how do you go through a design without instantiating a single vendor specific component? BTW, I didn=92t have to instantiate the BUFG, the tool inferred it! /B From newsfish@newsfish Fri Feb 3 13:09:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r8g2000prm.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: When are two clock domains actually considered asynchronous? Date: Fri, 17 Dec 2010 05:52:13 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: References: <908e286a-db80-4f21-b8b2-27b1e29626cb@v23g2000vbi.googlegroups.com> <147763ef-555e-4e8c-a41a-45b1ec881ee8@o4g2000yqd.googlegroups.com> <194bee3e-c505-43ec-aaa2-3f320fc3b8ad@z19g2000yqb.googlegroups.com> <27f95262-5b23-4344-8a93-262236492d07@m37g2000vbn.googlegroups.com> <706eaf1c-5b7b-497f-b1b9-b3dc96f89e55@o14g2000yqe.googlegroups.com> <680eefb7-30ff-4eb4-8726-b24dfd3250c6@r29g2000yqj.googlegroups.com> <8mkq3rFo01U1@mid.individual.net> <1cc365a8-778d-4a5a-a9b0-99cf9deb1e5e@z19g2000yqb.googlegroups.com> <8mskgpF4joU1@mid.individual.net> <0a5fb99d-fd01-48ae-a6f0-6b454850263e@w21g2000vby.googlegroups.com> <1022b3e2-0472-43ce-9e70-0f9238b09b46@e20g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1292593933 9028 127.0.0.1 (17 Dec 2010 13:52:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Dec 2010 13:52:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r8g2000prm.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4553 On Dec 15, 5:36 pm, Beppe wrote: > > As in the OP example, instead of suggesting how to control the timing of > > the clk_250k I would recommend not to use it at all (that means one > clock less). > > What are you're arguments against using the clk_250k apart from having > one clock less? clk_25 is only used for generating the clk_250k. No > data is passing from the clk_25 domain to the clk_250k domain and > clk_250k is put on a low skew global clock net. I'm not trying to argue or convince you, so I don't have an argument. You asked for opinions, I am offering mine. I don't know how much logic you have in the various clock domains or if there are others. I think you have said there is very little in the 28 MHz domain, but I'm not at all clear on what is in the 25 MHz and 250 kHz domains. I know little about letting the timing tools figure out how to handle dual outputs from a DCM. Unless there is some compelling reason, I would use clock crossing logic going between any of these clock domains. On the other hand, it is entirely possible to use a single clock domain for the entire design. You have a 125 MHz clock domain which is a super set of each of the slower clocks. A clock does not need to be an integer multiple to use a clock enable. For that matter, it doesn't even need to be 2x. In this design if the Midi code uses a clock enable to set the rate, you could easily use the 28 MHz clock with a 25 MHz enable. But a lot depends on how much interface you have vs. the hassle of converting code to work with enabled clocks. Clock crossing logic is not large or complex. I mainly find it unpleasant in that it clutters up a design somewhat. A recent design I did had expanded an existing design running on a 12.288 MHz clock from off board PLL controlled based on an interface FIFO. So this clock had to be used to establish interface timing, both sides in fact. The code I was adding had to have a section that ran on a 32 MHz clock to operate a digital PLL for a third interface. I had planned to provide a clock crossing interface between the two new sections of logic. But at some point this became a PITA and I ended up making the entire new design run on the 32 MHz clock and turned the 12.288 into an enable for the two exiting interfaces. OTOH, the previous circuit was working fine and had little to do with the new circuit (different modes of operation) so it was left alone clocking off the 12.288. Yet another interface for configuration was clocked off the interface clock (sort of a bastard SPI) and was also not changed for the new section. So multiple clocks are not bad, but I find it easier to live with if I convert at the external interface and run on one clock as much as possible. Rick From newsfish@newsfish Fri Feb 3 13:09:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!news2.glorb.com!usenet.stanford.edu!ctu-gate!news.nctu.edu.tw!newsfeed.nthu.edu.tw!news.cs.nthu.edu.tw!MapleBBS From: ppacc.bbs@bbs.cs.nthu.edu.tw (ccapp) Newsgroups: comp.lang.vhdl Subject: =?big5?Q?=ABC=A6~=AC=A1=B0=CA=A5=F8=B9=BA=AEv=B0=F6=B0V=AFZ=A8=B3=B3t=C3z=BA=A1=A4=A4!=BF=F9=B9L=B3o=A6=B8=A6A=B5=A5=A5b=A6~?= Date: 24 Dec 2010 05:58:14 GMT Organization: 毸 Lines: 44 Message-ID: NNTP-Posting-Host: bbs.cs.nthu.edu.tw Mime-Version: 1.0 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: 8bit X-Trace: news.cs.nthu.edu.tw 1293169221 23264 140.114.87.5 (24 Dec 2010 05:40:21 GMT) X-Complaints-To: manager@cs.nthu.edu.tw NNTP-Posting-Date: Fri, 24 Dec 2010 05:40:21 +0000 (UTC) Xref: feeder.eternal-september.org comp.lang.vhdl:4555 ljjv}eNbCCAPPC~ʥvI l    l{ʥARqAII<(á`)b l |iJiDAҵ{ܽШ ~wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww  x ճ]]p̡GTqѮvAPƳзN~¤OII  x wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww ~wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww  x @եxWNzƷ~GɼzѮvK@ɯŬʡIII  x wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww ~wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww  x WsiquNOsivзN`ʡGզѮvзNPNAȤ۰ʤWIx wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww ܽЪ15~ɬʡB[BiBPBsiMWqCEODZ±M~DA{ Ⱦާ@zwʥ¦C ------ CCAPP51B52 H}ҡA mɶAڭnWhttp://ppt.cc/evBY n ufɶG2010~1231e  mhufTЬfeng@planning.com.twn i ӤHufKj iTHHWγɤC̨uf + [جʥԿj Rqɶ    51G2011~117(@)B18(G)B20(|)B21()B24(@) tzI     52G2011~122()B23()B28()B29()B30() YNBI     OWvdj iױs j} ֤WʺGhttp://www.planning.com.tw/ccapp/ ҵ{߰02-23650930 --  Origin: 毸  From: ppacc @ 59-125-98-32.HINET-IP.hinet.net  From newsfish@newsfish Fri Feb 3 13:09:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: spacewire project on opencores.org Date: Fri, 24 Dec 2010 16:51:24 +0000 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <8ma3hpF3caU1@mid.individual.net> <8mmsqvF12mU1@mid.individual.net> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="26846"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/AUett3Vj6KoPGwCrAHyvaynX8S5bFxNCXfiXWm3ZoDg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <8mmsqvF12mU1@mid.individual.net> Cancel-Lock: sha1:AbRlFTWuV8iPoTKtqqH2Lv88JTU= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.arch.fpga:13775 comp.lang.vhdl:4556 comp.lang.verilog:2735 Alessandro Basili sent on December 13th, 2010: |-------------------------------------------------------------------------------| |"On 12/10/2010 3:57 PM, Thomas Stanka wrote: | |[snip] | |> Open cores tend to have a lack in documentation and verification, | |> which is a no-go for developing space electronics. | | | |[..]" | |-------------------------------------------------------------------------------| Verification is not always tried, though it has been dishonestly claimed to have been achieved in publications such as Sergio Saponara; Francesco Vitullo; Esa Petri; and Luca Fanucci, "A Reusable Pseudo-Random Verification Environment for Complex Digital Designs: the SpaceWire Interface Case Study", IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications 21-23 September 2009, Rende (Cosenza), Italy. Testing some examples instead of proving is not verification. |--------------------------------------------------------------------------------| |"I just want to mention that on an FPGA based application the choice of the FPGA| |may guarantee certain level of radiation hardness," | |--------------------------------------------------------------------------------| Choose Aeroflex: WWW.Aeroflex.com/ams/pagesproduct/prods-hirel-fpga.cfm |-------------------------------------------------------------------------------| |" while specific design | |techniques may improve the level of hardness even further (TMR, [..]" | |-------------------------------------------------------------------------------| TMR could actually be harmful when using technologies with small feature sizes, if sufficient care is not taken: Blum and Delgado-Frias, "Schemes for Eliminating Transient-Width Clock Overhead From SET-Tolerant Memory-Based Systems", "I.E.E.E. Transactions on Nuclear Science", June 2006. |-------------------------------------------------------------------------------| |"[..] | | | |Even though I believe that Space Agencies around the world are politically and | |technically bond to follow standardization processes based mostly on lessons | |learned, [..] | |[..] | | | |[..]" | |-------------------------------------------------------------------------------| The European Space Agency does not adhere to its own standards. Yours sincerely, Paul Colin Gloster From newsfish@newsfish Fri Feb 3 13:09:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 18:35:13 +0000 Organization: A noiseless patient Spider Lines: 12 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <4d07681e$0$14247$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="19278"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19BQ2Vo5oHbGFVeOaXYUVm3yUL88UULIbQi+c25SwHYBA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <4d07681e$0$14247$ba620e4c@news.skynet.be> Cancel-Lock: sha1:Q2lL4BSMfiWhdc+W5mWYHD/D0LE= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4557 Jan Decaluwe sent on December 14th, 2010: |---------------------------------------------------------------------| |"[..] | | | |I think Verilog will suit you better as a language, you really should| |consider switching one of these days. However, there is no reason why| |it would help you with the issues that you say you are seeing here." | |---------------------------------------------------------------------| He did try Verilog many months ago, but he has resumed with VHDL. From newsfish@newsfish Fri Feb 3 13:09:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 18:46:15 +0000 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <5da5eb09-d959-4c5f-a8a3-6f2d401f1593@o14g2000prn.googlegroups.com> <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx01.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="3594"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+CaUeNsV881PMSu0QITUeaJ9kZ5bx+YQhRB3ahxe8Pzg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <0992adf9-09ae-476a-935a-14781187e48b@o14g2000yqe.googlegroups.com> Cancel-Lock: sha1:+pHQEvnWyiT0+rGJjiiRJpOjH8c= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4558 Andy sent on December 15th, 2010: |----------------------------------------------------------------------| |"[..] | | | |[..] | |[..] You have a pre-conceived notion | |that using a carry output will, in all cases of performance, | |resources, and target architecture, be an optimal solution. This is | |simply not true. | | | |Using my method (count - 1 < 0), I have seen the same synthesis tool, | |for the same target architecture, use the the built-in carry-chain | |output (shared), use combination of sub-carry outputs and LUTS, and | |just LUTS, depending on what it thought would be optimal (and when I | |checked them, I found it had made very good choices!) [..] | |[..] | |[..] But | |these are synthesis tool issues, not language issues. | | | |Andy" | |----------------------------------------------------------------------| Yes, these are good examples of why Rick is naive to expect to know in advance the efficient output of a synthesizer. If one variable is always the sum of two other particular variables and these "variables" are always constant, then the corresponding hardware (if any) should naturally be less than for three changing variables. Rick was proposing something which in reality would be uniform and hence not generally efficient. From newsfish@newsfish Fri Feb 3 13:09:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 19:00:53 +0000 Organization: A noiseless patient Spider Lines: 11 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> <607a3384-9ea9-4aee-a4be-0007a6479169@q8g2000prm.googlegroups.com> <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx03.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="24946"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1857eN8/LnGS0dnp+zelTvnGO2eiIBymTC1cRCreY2EjA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <87ffcd52-8b04-480c-a9fb-afe14281296d@q18g2000vbm.googlegroups.com> Cancel-Lock: sha1:R5b3Y/6LrZnBY1havfyUNycB4Co= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4559 Tricky sent on December 15th, 2010: |---------------------------------------------------------------------| |"[..] | |[..] The only way to know what will come out in advance | |is either with experience or instantiation. [..] | |[..] | | | |[..]" | |---------------------------------------------------------------------| It is not possible to know. From newsfish@newsfish Fri Feb 3 13:09:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl Subject: Re: Are HDLs Misguided? Date: Fri, 24 Dec 2010 19:44:44 +0000 Organization: A noiseless patient Spider Lines: 54 Message-ID: References: <6af958ff-1b6b-4865-923a-629549dd65e8@y23g2000yqd.googlegroups.com> <14389ad7-bbe7-49a0-9ebf-883e3fdd0af0@f21g2000prn.googlegroups.com> <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Injection-Info: mx01.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="16816"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fzECZARF0m1FAk/cV0mj2cf41GWy5opVcXVvFkbcYfg==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <266d3f73-bd80-45c7-990c-ed6d3c8ae7c2@i41g2000vbn.googlegroups.com> Cancel-Lock: sha1:J9C00uX93MYtbjKbVsMAfdU+02o= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4560 Rick Collins had sent on December 10th, 2010: |----------------------------------------------------------------------| |"[..] | | | |What I mean is, if I want a down counter that uses the carry out to | |give me an "end of count" flag, why can't I get that in a simple and | |clear manner? It seems like every time I want to design a circuit I | |have to experiment with the exact style to get the logic I want and it| |often is a real PITA to make that happen. | | | |[..] | | | |I guess what I am trying to say is I would like to be able to specify | |detailed logic rather than generically coding the function and letting| |a tool try to figure out how to implement it. [..] | |[..]" | |----------------------------------------------------------------------| On December 13th, 2010, Rick has claimed: |-----------------------------------------------------------------| |"[..] | | | |[..] | |[..] I am not saying I want to use something similar to assembly| |language [..] | |[..] | | | |[..]" | |-----------------------------------------------------------------| Rick Collins sent on December 14th, 2010: |---------------------------------------------------------------------| |"[..] | | | |[..] | |[..] Like I said somewhere else, if you want a | |particular solution, the vendors tell you to instantiate. | |Instantiation is very undesirable since it is not portable across | |vendors and often not portable across product lines within a vendor!"| |---------------------------------------------------------------------| As with many assembly languages for different models in a single processor family. |--------------------------------------------------------------------| |"The language is flexible, that's for sure. [..] | |[..]" | |--------------------------------------------------------------------| As flexible as Lisp or Confluence or Lava? From newsfish@newsfish Fri Feb 3 13:09:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!f21g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: VHDL Automated Testing Date: Sat, 25 Dec 2010 20:23:25 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <97b68281-4ae2-4dcd-9d3b-4b9bf9dd28c0@f21g2000prn.googlegroups.com> References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> NNTP-Posting-Host: 98.246.137.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1293337405 17670 127.0.0.1 (26 Dec 2010 04:23:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 26 Dec 2010 04:23:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f21g2000prn.googlegroups.com; posting-host=98.246.137.228; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4562 turn on VHDL-2008 and use: std.env.stop(2) ; The intent is that the integer parameter is returned to the calling program. Not sure how the simulators are implementing it, but if it does not work like you expect, submit a bug report against it. Best, Jim From newsfish@newsfish Fri Feb 3 13:09:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f8g2000yqd.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Call for Papers & Sessions: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 26 Dec 2010 01:29:33 -0800 (PST) Organization: http://groups.google.com Lines: 293 Message-ID: <41e0f87d-b12e-4617-80a1-b54ca988ef3c@f8g2000yqd.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1293355774 18864 127.0.0.1 (26 Dec 2010 09:29:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 26 Dec 2010 09:29:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f8g2000yqd.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:147570 sci.electronics.cad:6963 sci.electronics.misc:3546 sci.engr.semiconductors:730 comp.lang.vhdl:4563 CALL FOR PAPERS and Call For Workshop/Session Proposals MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods Date and Location: July 18-21, 2011, USA http://www.world-academy-of-science.org/ Location: See the above web site for venue/city You are invited to submit a full paper for consideration. All accepted papers will be published in the MSV conference proceedings (in printed book form; later, the proceedings will also be accessible online). Those interested in proposing workshops/sessions, should refer to the relevant sections that appear below. SCOPE: Topics of interest include, but are not limited to, the following: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: To see the DBLP list of accepted papers of MSV 2009, go to: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2009.html The DBLP list of accepted papers of MSV 2010 will soon appear at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html MSV 2011 URL: http://www.world-academy-of-science.org/ IMPORTANT DATES: March 10, 2011: Submission of papers (about 5 to 7 pages) April 03, 2011: Notification of acceptance (+/- two days) April 24, 2011: Final papers + Copyright/Consent + Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) ACADEMIC CO-SPONSORS: Currently being prepared - The Academic sponsors of the last offering of MSV (2010) included research labs and centers affiliated with (a partial list): University of California, Berkeley; University of Southern California; University of Texas at Austin; Harvard University, Cambridge, Massachusetts; Georgia Institute of Technology, Georgia; Emory University, Georgia; University of Minnesota; University of Iowa; University of North Dakota; NDSU-CIIT Green Computing & Comm. Lab.; University of Siegen, Germany; UMIT, Austria; SECLAB (University of Naples Federico II + University of Naples Parthenope + Second University of Naples, Italy); National Institute for Health Research; World Academy of Biomedical Sciences and Technologies; Russian Academy of Sciences, Russia; International Society of Intelligent Biological Medicine (ISIBM); The International Council on Medical and Care Compunetics; Eastern Virginia Medical School & the American College of Surgeons, USA. SUBMISSION OF PAPERS: Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by March 10, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) that the paper is being submitted for consideration must be stated on the first page. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject) - often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/philosophical papers will not be refereed but may be considered for discussion/panels). All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering & Technology, DBLP / CS Bibliography, and others. The printed proceedings will be available for distribution on site at the conference. In addition to the publication of the proceedings, selected authors will be invited to submit extended versions of their papers for publication in a number of research books being proposed/contracted with various publishers (such as, Springer, Elsevier, ...) - these books would be composed after the conference. Also, many chairs of sessions and workshops will be forming journal special issues to be published after the conference. MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES: The members of the Steering Committee of The 2010 congress included: Dr. Selim Aissi (Chief Strategist, Intel Corporation, USA); Prof. Hamid Arabnia (ISIBM Fellow & Professor, University of Georgia; Associate Editor, IEEE Transactions on Information Technology in Biomedicine; Editor-in-Chief, Journal of Supercomputing, Springer; Advisory Board, IEEE TC on Scalable Computing); Prof. Ruzena Bajcsy (Member, National Academy of Engineering, IEEE Fellow, ACM Fellow, Professor; University of California, Berkeley, USA); Prof. Hyunseung Choo (ITRC Director of Ministry of Information & Communication; Director, ITRC; Director, Korea Information Processing Society; Assoc. Editor, ACM Transactions on Internet Technology; Professor, Sungkyunkwan University, Korea); Prof. Winston Wai-Chi Fang (IEEE Fellow, TSMC Distinguished Chair Professor, National ChiaoTung University, Hsinchu, Taiwan, ROC); Prof. Andy Marsh (Director HoIP, Secretary-General WABT; Vice-president ICET and ICMCC, Visiting Professor, University of Westminster, UK); Dr. Rahman Tashakkori (Director, S-STEM NSF Supported Scholarship Program and NSF Supported AUAS, Appalachian State U., USA); Prof. Layne T. Watson (IEEE Fellow, NIA Fellow, ISIBM Fellow, Fellow of The National Institute of Aerospace, Virginia Polytechnic Institute & State University, USA); and Prof. Lotfi A. Zadeh (Member, National Academy of Engineering; IEEE Fellow, ACM Fellow, AAAS Fellow, AAAI Fellow, IFSA Fellow; Director, BISC; Professor, University of California, Berkeley, USA). The list of Program Committee of MSV 2010 appears at: http://www.world-academy-of-science.org/worldcomp10/ws/conferences/msv10/committee The MSV 2011 program committee is currently being compiled. Many who have already joined the committee are renowned leaders, scholars, researchers, scientists and practitioners of the highest ranks; many are directors of research labs., members of National Academy of Engineering, fellows of various societies, heads/chairs of departments, program directors of research funding agencies, deans and provosts as well as members of chapters of World Academy of Science. Program Committee members are expected to have established a strong and documented research track record. Those interested in joining the Program Committee should email editor@world-comp.org the following information for consideration/evaluation: Name, affiliation and position, complete mailing address, email address, a one-page biography that includes research expertise and the name of the conference (ie, MSV 2011) offering to help with. GENERAL INFORMATION: MSV conference is an important track of a federated research conference. It is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,000 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different branches of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub- disciplines. PROPOSAL FOR ORGANIZING SESSIONS/WORKSHOPS: Each session will have at least 6 paper presentations from different authors (12 papers in the case of workshops). The session chairs will be responsible for all aspects of their sessions; including, soliciting papers, reviewing, selecting, ... The names of session chairs will appear as Associate Editors in the conference proceedings and on the cover of the books. Proposals to organize sessions should include the following information: name and address (+ email) of proposer, his/her biography, title of session, a 100-word description of the topic of the session, the name of the conference the session is submitted for consideration (ie, MSV), and a short description on how the session will be advertised (in most cases, session proposers solicit papers from colleagues and researchers whose work is known to the session proposer). email your session proposal to editor@world-comp.org We would like to receive the session proposals by January 16, 2011 (or as soon as possible). NEWS: Thanks to authors and speakers of last WORLDCOMP congress and members of the editorial boards who informed us of the following good news: According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" and specific information extracted from it (in reference to WORLDCOMP's individual conferences' names/acronyms and tracks) from the link below: http://www.worldacademyofscience.org/worldcomp10/ws/news From newsfish@newsfish Fri Feb 3 13:09:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kpn.net!pfeed09.wxs.nl!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d19f2fc$0$41103$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: VHDL Automated Testing Newsgroups: comp.lang.vhdl Date: Tue, 28 Dec 2010 15:23:56 +0100 References: <5dba4285-2650-45d6-8201-9713d1d595f0@i41g2000vbn.googlegroups.com> <97b68281-4ae2-4dcd-9d3b-4b9bf9dd28c0@f21g2000prn.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 26 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1293546236 news.xs4all.nl 41103 puiterl/[::ffff:195.242.97.150]:38721 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4566 JimLewis wrote: > turn on VHDL-2008 and use: > std.env.stop(2) ; > > The intent is that the integer parameter is > returned to the calling program. Not sure > how the simulators are implementing it, but > if it does not work like you expect, submit a > bug report against it. In ModelSim it has been implemented as: For both STOP and FINISH the STATUS values are those used in the Verilog $finish task 0 prints nothing 1 prints simulation time and location 2 prints simulation time, location, and statistics about the memory and CPU times used in simulation Other STATUS values are interpreted as 0. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:09:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w17g2000yqh.googlegroups.com!not-for-mail From: laserbeak43 Newsgroups: comp.lang.vhdl Subject: Working on an FSM Date: Fri, 31 Dec 2010 00:07:53 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: NNTP-Posting-Host: 66.233.229.70 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1293782873 17637 127.0.0.1 (31 Dec 2010 08:07:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 31 Dec 2010 08:07:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w17g2000yqh.googlegroups.com; posting-host=66.233.229.70; posting-account=MUQwpQoAAAA9_IapFtScznKkXs6s5-S0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4568 Hello, I'm learning about FSMs and I'm having a hard time getting my code to run correctly. I'm getting errors that say the registers for my states won't hold outside of the clock edge, and another set of errors saying that i have multiple constant drivers that can't be resolved. Does anyone think that they could help me out with this code? I've truncated the switch, the full source can be found here http://paste.org/pastebin/view/26824 Thanks Malik **************************************************************************************************************** LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity part1take2 is port( CLOCK_50 : in std_logic; SW : in unsigned(1 downto 0); LEDR : out unsigned(8 downto 0) ); end part1take2; architecture behavioral of part1take2 is type statet is ( A, B, C, D, E, F, G, H, I ); constant FMil: integer := 50000000; signal count : unsigned(25 downto 0); signal CLK : std_logic; signal cstate, nstate : statet; signal lstate : unsigned(8 downto 0); begin LEDR <= lstate; process(CLK, SW, cstate) begin nstate <= cstate; LEDR <= to_unsigned(0, 9); if(SW(0) = '1') then nstate <= A; else if(rising_edge(CLK)) then case cstate is when A => lstate <= to_unsigned(000000001, 9); if(SW(1) = '1') then nstate <= F; else nstate <= B; end if; when B => lstate <= to_unsigned(000000010, 9); if(SW(1) = '1') then nstate <= F; else nstate <= C; end if; t--truncated end case; end if; end if; end process; process(CLOCK_50) begin if rising_edge(CLOCK_50) then if(count = FMil) then CLK <= (not CLK); if(CLK = '1') then cstate <= nstate; end if; else count <= count + 1; end if; end if; end process; end behavioral; From newsfish@newsfish Fri Feb 3 13:09:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Fri, 31 Dec 2010 10:56:25 -0800 Lines: 12 Message-ID: <8o6nanFlomU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vfbs/Ia9tO7Al4jgKjAhUwwc0Tux4s8S+x2Yf4PSk1d2Ki5CqW Cancel-Lock: sha1:5TsyUqYkZf4JKeXb0jlFBu/fhto= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4569 On 12/31/2010 12:07 AM, laserbeak43 wrote: > Hello, > I'm learning about FSMs and I'm having a hard time getting my code to > run correctly. > I'm getting errors that say the registers for my states won't hold > outside of the clock edge, and another set of errors saying that i > have multiple constant drivers that can't be resolved. I use a single process (reset, clock) This would fix most of your problems. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:09:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!195.114.241.41.MISMATCH!feeder.news-service.com!feeder.news-service.com!postnews.google.com!u3g2000vbj.googlegroups.com!not-for-mail From: Dave Pollum Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Mon, 3 Jan 2011 05:58:57 -0800 (PST) Organization: http://groups.google.com Lines: 61 Message-ID: References: NNTP-Posting-Host: 108.18.250.64 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: base64 X-Trace: posting.google.com 1294063137 1191 127.0.0.1 (3 Jan 2011 13:58:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 3 Jan 2011 13:58:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbj.googlegroups.com; posting-host=108.18.250.64; posting-account=k4CBzgkAAAAs9YjexmeomdQ-EXRg4yzs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4571 T24gRGVjIDMxIDIwMTAsIDM6MDegYW0sIGxhc2VyYmVhazQzIDxsYXNlcmJlYS4uLkBnbWFpbC5j b20+IHdyb3RlOgo+IEhlbGxvLAo+IEknbSBsZWFybmluZyBhYm91dCBGU01zIGFuZCBJJ20gaGF2 aW5nIGEgaGFyZCB0aW1lIGdldHRpbmcgbXkgY29kZSB0bwo+IHJ1biBjb3JyZWN0bHkuCj4gSSdt IGdldHRpbmcgZXJyb3JzIHRoYXQgc2F5IHRoZSByZWdpc3RlcnMgZm9yIG15IHN0YXRlcyB3b24n dCBob2xkCj4gb3V0c2lkZSBvZiB0aGUgY2xvY2sgZWRnZSwgYW5kIGFub3RoZXIgc2V0IG9mIGVy cm9ycyBzYXlpbmcgdGhhdCBpCj4gaGF2ZSBtdWx0aXBsZSBjb25zdGFudCBkcml2ZXJzIHRoYXQg Y2FuJ3QgYmUgcmVzb2x2ZWQuCj4KPiBEb2VzIGFueW9uZSB0aGluayB0aGF0IHRoZXkgY291bGQg aGVscCBtZSBvdXQgd2l0aCB0aGlzIGNvZGU/IEkndmUKPiB0cnVuY2F0ZWQgdGhlIHN3aXRjaCwg dGhlIGZ1bGwKPiBzb3VyY2UgY2FuIGJlIGZvdW5kIGhlcmVodHRwOi8vcGFzdGUub3JnL3Bhc3Rl YmluL3ZpZXcvMjY4MjQKPgo+IFRoYW5rcwo+IE1hbGlrCj4KPiAqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqCj4KPiBMSUJSQVJZIGllZWU7Cj4g VVNFIGllZWUuc3RkX2xvZ2ljXzExNjQuYWxsOwo+IFVTRSBpZWVlLm51bWVyaWNfc3RkLmFsbDsK Pgo+IGVudGl0eSBwYXJ0MXRha2UyIGlzCj4goCCgIKAgoCBwb3J0KAo+IKAgoCCgIKAgoCCgIKAg oCBDTE9DS181MCCgIKAgoCCgOiBpbiBzdGRfbG9naWM7Cj4goCCgIKAgoCCgIKAgoCCgIFNXIKAg oCCgIKAgoCCgIKAgoCCgIKAgoDogaW4gdW5zaWduZWQoMSBkb3dudG8gMCk7Cj4goCCgIKAgoCCg IKAgoCCgIExFRFIgoCCgIKAgoCCgIKA6IG91dCB1bnNpZ25lZCg4IGRvd250byAwKQo+IKAgoCCg IKAgKTsKPiBlbmQgcGFydDF0YWtlMjsKPgo+IGFyY2hpdGVjdHVyZSBiZWhhdmlvcmFsIG9mIHBh cnQxdGFrZTIgaXMKPgo+IKAgoCCgIKAgdHlwZSBzdGF0ZXQgaXMgKCBBLCBCLCBDLCBELCBFLCBG LCBHLCBILCBJICk7Cj4goCCgIKAgoCBjb25zdGFudCBGTWlsOiBpbnRlZ2VyIDo9IDUwMDAwMDAw Owo+Cj4goCCgIKAgoCBzaWduYWwgY291bnQgoCCgOiB1bnNpZ25lZCgyNSBkb3dudG8gMCk7Cj4g oCCgIKAgoCBzaWduYWwgQ0xLIKAgoCCgIKAgoCCgIKA6IHN0ZF9sb2dpYzsKPiCgIKAgoCCgIHNp Z25hbCBjc3RhdGUsIG5zdGF0ZSA6IHN0YXRldDsKPiCgIKAgoCCgIHNpZ25hbCBsc3RhdGUgoCA6 IHVuc2lnbmVkKDggZG93bnRvIDApOwo+Cj4gYmVnaW4KPgo+IKAgoCCgIKAgTEVEUiA8PSBsc3Rh dGU7Cj4KPiCgIKAgoCCgIHByb2Nlc3MoQ0xLLCBTVywgY3N0YXRlKQo+IKAgoCCgIKAgYmVnaW4K Pgo+IKAgoCCgIKAgoCCgIKAgoCBuc3RhdGUgPD0gY3N0YXRlOwo+IKAgoCCgIKAgoCCgIKAgoCBM RURSIDw9IHRvX3Vuc2lnbmVkKDAsIDkpOwo+Cj4goCCgIKAgoCCgIKAgoCCgIGlmKFNXKDApID0g JzEnKSB0aGVuCj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgbnN0YXRlIDw9IEE7Cj4goCCgIKAg oCCgIKAgoCCgIGVsc2UKPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBpZihyaXNpbmdfZWRnZShD TEspKSB0aGVuCj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBjYXNlIGNzdGF0ZSBp cwo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCB3aGVuIEEgPT4KPiCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBsc3RhdGUgPD0g dG9fdW5zaWduZWQoMDAwMDAwMDAxLCA5KTsKPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg oCCgIKAgoCCgIKAgoCCgIKAgoCBpZihTVygxKSA9ICcxJykgdGhlbgo+IKAgoCCgIKAgoCCgIKAg oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgbnN0YXRlIDw9IEY7Cj4g oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgZWxzZQo+IKAg oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgbnN0 YXRlIDw9IEI7Cj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg IKAgZW5kIGlmOwo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCB3aGVu IEIgPT4KPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBs c3RhdGUgPD0gdG9fdW5zaWduZWQoMDAwMDAwMDEwLCA5KTsKPiCgIKAgoCCgIKAgoCCgIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBpZihTVygxKSA9ICcxJykgdGhlbgo+IKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgbnN0YXRl IDw9IEY7Cj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg ZWxzZQo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg oCCgIKAgbnN0YXRlIDw9IEM7Cj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg oCCgIKAgoCCgIKAgZW5kIGlmOwo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg IKAgoCB0LS10cnVuY2F0ZWQKPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIGVuZCBj YXNlOwo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIGVuZCBpZjsKPiCgIKAgoCCgIKAgoCCgIKAg ZW5kIGlmOwo+IKAgoCCgIKAgZW5kIHByb2Nlc3M7Cj4KPiCgIKAgoCCgIHByb2Nlc3MoQ0xPQ0tf NTApIGJlZ2luCj4KPiCgIKAgoCCgIKAgoCCgIKAgaWYgcmlzaW5nX2VkZ2UoQ0xPQ0tfNTApIHRo ZW4KPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBpZihjb3VudCA9IEZNaWwpIHRoZW4KPiCgIKAg oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIENMSyA8PSAobm90IENMSyk7Cj4goCCgIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBpZihDTEsgPSAnMScpIHRoZW4KPiCgIKAgoCCgIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgY3N0YXRlIDw9IG5zdGF0ZTsKPiCgIKAgoCCgIKAg oCCgIKAgoCCgIKAgoCCgIKAgoCCgIGVuZCBpZjsKPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBl bHNlCj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBjb3VudCA8PSBjb3VudCArIDE7 Cj4goCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgZW5kIGlmOwo+IKAgoCCgIKAgoCCgIKAgoCBlbmQg aWY7Cj4KPiCgIKAgoCCgIGVuZCBwcm9jZXNzOwo+Cj4gZW5kIGJlaGF2aW9yYWw7CgpDb21tZW50 IG91dCAibnN0YXRlIDw9IGNzdGF0ZTsiIChpbiB0aGUgZmlyc3QgcHJvY2VzcykgYW5kIHNlZSBp ZiB0aGF0CmhlbHBzLgotRGF2ZSBQb2xsdW0= From newsfish@newsfish Fri Feb 3 13:09:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!q8g2000prm.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Mon, 3 Jan 2011 14:31:39 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <023b15dc-99ab-4c19-878e-621474951dc4@q8g2000prm.googlegroups.com> References: NNTP-Posting-Host: 98.246.137.228 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1294093899 12580 127.0.0.1 (3 Jan 2011 22:31:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 3 Jan 2011 22:31:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q8g2000prm.googlegroups.com; posting-host=98.246.137.228; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4572 Hi Malik, 1) You have multiple drivers on LEDR. One outside the process and one in the process. For every signal assigned in a separate process (and think of a concurrent assignment as a separate process), a separate piece of hardware is created. If you have more than one piece of hardware, you are connecting outputs directly together in a bad way. 2) You probably do not want derived clocks. Instead use enables - you are kind of doing this with CLK in the process that includes CLOCK_50. I suspect you do not need the "rising_edge(CLK)" in the other process. 3) You need to work on your logic revolving around count. Does count ever go back to 0? Otherwise the condition, count = FMil will only be true once. You could probably evolve it to something that captures the nstate when count = 2*FMil and resets count to 0, and otherwise increments count. 4) You need to simulate before you synthesize. 5) Although Mike hates using more than one process to code a statemachine, I prefer using two. 6) The assignment "nstate <= cstate;" is called a default assignment and can help you take short-cuts in some statemachines, but looking at the rest of your statemachine, you are neither using it nor would you benefit from it (except in state E - and I am not going to use a default assignment to help only in one state). Good luck. Try the simulator. Best, Jim Lewis From newsfish@newsfish Fri Feb 3 13:09:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!z19g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Mon, 3 Jan 2011 14:35:54 -0800 (PST) Organization: http://groups.google.com Lines: 140 Message-ID: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1294094154 20693 127.0.0.1 (3 Jan 2011 22:35:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 3 Jan 2011 22:35:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z19g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4573 On Dec 31 2010, 3:07=A0am, laserbeak43 wrote: > Hello, > I'm learning about FSMs and I'm having a hard time getting my code to > run correctly. > I'm getting errors that say the registers for my states won't hold > outside of the clock edge, and another set of errors saying that i > have multiple constant drivers that can't be resolved. > > Does anyone think that they could help me out with this code? I've > truncated the switch, the full > source can be found herehttp://paste.org/pastebin/view/26824 > > Thanks > Malik > > *************************************************************************= *************************************** > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > USE ieee.numeric_std.all; > > entity part1take2 is > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLOCK_50 =A0 =A0 =A0 =A0: in std_logic; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SW =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0: in unsigned(1 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR =A0 =A0 =A0 =A0 =A0 =A0: out unsigne= d(8 downto 0) > =A0 =A0 =A0 =A0 ); > end part1take2; > > architecture behavioral of part1take2 is > > =A0 =A0 =A0 =A0 type statet is ( A, B, C, D, E, F, G, H, I ); > =A0 =A0 =A0 =A0 constant FMil: integer :=3D 50000000; > > =A0 =A0 =A0 =A0 signal count =A0 =A0: unsigned(25 downto 0); > =A0 =A0 =A0 =A0 signal CLK =A0 =A0 =A0 =A0 =A0 =A0 =A0: std_logic; > =A0 =A0 =A0 =A0 signal cstate, nstate : statet; > =A0 =A0 =A0 =A0 signal lstate =A0 : unsigned(8 downto 0); > > begin > > =A0 =A0 =A0 =A0 LEDR <=3D lstate; > > =A0 =A0 =A0 =A0 process(CLK, SW, cstate) In a clocked process only the clock and any async inputs should be in the sensitivity list. This can make your simulation differ from the synthesized logic. Remove cstate. > =A0 =A0 =A0 =A0 begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D cstate; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDR <=3D to_unsigned(0, 9); > These two lines are outside of the conditional clauses. That means they are executed anytime any of the signals in the sensitivity list change. There is no reasonable synthesizable logic that will match this description. What are you trying to do with these two lines? They are the ones giving the error. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(SW(0) =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D A; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(rising_edge(CLK)) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case csta= te is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 when A =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 lstate <=3D to_unsigned(000000001, 9); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 if(SW(1) =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D F; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D B; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 when B =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 lstate <=3D to_unsigned(000000010, 9); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 if(SW(1) =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D F; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 nstate <=3D C; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 t--truncated > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 process(CLOCK_50) begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rising_edge(CLOCK_50) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(count =3D FMil) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK <=3D = (not CLK); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(CLK = =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 cstate <=3D nstate; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 count <= =3D count + 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end process; > > end behavioral; I also don't understand what you are trying to acheive with the two processes. The second process synthesizes a clock for the first. The values of cstate and nstate run through BOTH clocks, two registers! One is clocked by the rising edge of CLK while the other is clocked by the rising edget of CLOCK_50, but enabled when CLK is high which roughly corresponds to the falling edge of CLK. Is that what you intend? BTW, to get the CLK <=3D not CLK; line to simulate you need to initialize CLK in a reset statement or in the signal declaration. The former will be synthesized while the latter may or may not be. Rick From newsfish@newsfish Fri Feb 3 13:09:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z17g2000prz.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Wed, 5 Jan 2011 11:26:51 -0800 (PST) Organization: http://groups.google.com Lines: 13 Message-ID: <15baf693-5f32-413e-a8b4-8d5e41621e6d@z17g2000prz.googlegroups.com> References: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1294255726 11598 127.0.0.1 (5 Jan 2011 19:28:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 5 Jan 2011 19:28:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000prz.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4574 On Jan 3, 2:35=A0pm, rickman wrote: > > In a clocked process only the clock and any async inputs should be in > the sensitivity list. =A0This can make your simulation differ from the > synthesized logic. =A0Remove cstate. > > Rick I suggest that only 'clock' and 'reset' be on the sensitivity list of a clocked process. RK From newsfish@newsfish Fri Feb 3 13:09:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!i32g2000pri.googlegroups.com!not-for-mail From: paypal cash Newsgroups: comp.lang.vhdl Subject: BOLLYWOOD MIDNIGHT VIDEOS Date: Wed, 5 Jan 2011 17:23:57 -0800 (PST) Organization: http://groups.google.com Lines: 4 Message-ID: <9a82a117-74f5-4b42-b86d-ee33ab2f2a6e@i32g2000pri.googlegroups.com> NNTP-Posting-Host: 117.195.171.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1294277037 27468 127.0.0.1 (6 Jan 2011 01:23:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 6 Jan 2011 01:23:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i32g2000pri.googlegroups.com; posting-host=117.195.171.211; posting-account=ELWkcwoAAABXfFXLjUMA2Yy9T3uwcHCW User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4575 HOT SEXY BIPASA BASU BIKINI HOT JUNGLE VIDEOS,HOT AISHWARIYA RAI DATING VIDEOS, ANGELINA JOLIE LATE NIGHT JUNGLE VIDEOS hot&sexy photos,KATRINA HOT SEXY PHOTOS... more =BBAT http://aish201fashionvideos.co= .cc From newsfish@newsfish Fri Feb 3 13:09:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Thu, 06 Jan 2011 14:06:06 +0000 Organization: TRW Conekt Lines: 25 Message-ID: References: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> <15baf693-5f32-413e-a8b4-8d5e41621e6d@z17g2000prz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net Klt+YbF2Lw1uuhkLCc/Y2QQDbksHHiK667Kiagy0AD/ZS7Ck8= Cancel-Lock: sha1:BO8Tm6Cq6dYlfTF17dc9xl3p4/4= sha1:dsImprxKSUrFYOEQAsPUcQsSNpU= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4578 d_s_klein writes: > On Jan 3, 2:35pm, rickman wrote: >> >> In a clocked process only the clock and any async inputs should be in >> the sensitivity list. This can make your simulation differ from the >> synthesized logic. Remove cstate. >> >> Rick > > I suggest that only 'clock' and 'reset' be on the sensitivity list of > a clocked process. Good suggestion iff reset is an async input. When using synchronous resets, then *only* clock should be in the sensitivity list. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed01.sul.t-online.de!t-online.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!k9g2000pre.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Thu, 6 Jan 2011 11:03:41 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <95a85cc3-db4b-4d2c-844e-8216a31077b4@k9g2000pre.googlegroups.com> References: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> <15baf693-5f32-413e-a8b4-8d5e41621e6d@z17g2000prz.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1294340622 28691 127.0.0.1 (6 Jan 2011 19:03:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 6 Jan 2011 19:03:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000pre.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4579 On Jan 6, 6:06=A0am, Martin Thompson wrote: > > Good suggestion iff reset is an async input. =A0 > You are correct; all of the synthesis tools I have used behave exactly as you describe. I wonder how many understand that 'iff' is not a typo. RK From newsfish@newsfish Fri Feb 3 13:09:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Fri, 07 Jan 2011 10:20:32 +0000 Organization: TRW Conekt Lines: 46 Message-ID: References: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> <15baf693-5f32-413e-a8b4-8d5e41621e6d@z17g2000prz.googlegroups.com> <95a85cc3-db4b-4d2c-844e-8216a31077b4@k9g2000pre.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net tSjNmtzbF66u5Wm6xotTegrs3GPSfhkdgYyvZVNkH5ZNh6oyg= Cancel-Lock: sha1:wmcOMADKEPbOSImPGIbGFAuNSsk= sha1:QT6cDvghJ8e4a2K4pVptcoMeFWY= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4580 d_s_klein writes: > On Jan 6, 6:06am, Martin Thompson wrote: >> >> Good suggestion iff reset is an async input. >> > > You are correct; all of the synthesis tools I have used behave exactly > as you describe. And the simulators I hope - it's the way the language is specified! [aside] Of course, if you omit reset from the sensitivity list and then use it in an "asynchronous" way in the process (outside of the "clocked" part), all bets are off synthesis-behaviour-wise: process (clk) begin if asyncreset = '1' then -- do stuff on both clock edges when asyncreset is high! elsif rising_edge(clk) then -- do stuff on rising edges when syncreset is low... end if; end; Some (all?) synthesisers will assume you meant to include reset in the sensitivity list and synth an async reset. Whereas the simulator will execute the reset clause on *every* clock edge, but the "normal" clocked part on the rising edges. I'm sure no-one would ever write code like that though :) > > I wonder how many understand that 'iff' is not a typo. > I have to admit I wondered that as I wrote it... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:09:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i32g2000pri.googlegroups.com!not-for-mail From: paypal cash Newsgroups: comp.lang.vhdl Subject: ALL STARS HOT VIDEOS Date: Fri, 7 Jan 2011 18:10:14 -0800 (PST) Organization: http://groups.google.com Lines: 4 Message-ID: NNTP-Posting-Host: 117.195.163.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1294452614 31019 127.0.0.1 (8 Jan 2011 02:10:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 8 Jan 2011 02:10:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i32g2000pri.googlegroups.com; posting-host=117.195.163.153; posting-account=ELWkcwoAAABXfFXLjUMA2Yy9T3uwcHCW User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4581 Watch Bollywood sex stars, TAMIL ACTRES new hot exposing dating videos,TOLLYWOOD ACTRES excellent Sexy night videos and FASHION GIRLS Romantic scheans... more =BBAT http://500bikinivideos.co= .cc From newsfish@newsfish Fri Feb 3 13:09:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!news.internetdienste.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 08 Jan 2011 20:26:19 -0600 From: james Newsgroups: comp.lang.vhdl Subject: Re: Working on an FSM Date: Sat, 08 Jan 2011 21:26:21 -0500 Reply-To: beerkeg@budu.edu Message-ID: <467ii6tiqlq75tauhgnujfsjnq86kd9d73@4ax.com> References: <34c4ac69-4275-43dc-be98-ea4a91cffbd3@z19g2000yqb.googlegroups.com> <15baf693-5f32-413e-a8b4-8d5e41621e6d@z17g2000prz.googlegroups.com> <95a85cc3-db4b-4d2c-844e-8216a31077b4@k9g2000pre.googlegroups.com> X-Newsreader: Forte Agent 1.92/32.572 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 9 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 72.91.132.136 X-Trace: sv3-xnNEgaERExXZth+CP/E8DGdPUjTeLAM4Bwlp0N8rUJpeUbtuIwK8p3efK2qOLBnd7Ap5yLupWqqV6X0!XaJXxhlea31ztwn7Hq26mMFCgUO4t1G3gysJF1aAs/ohVzf3A/9htcrVwR0NdYfuKfibPwIgQWM3!hCDDsSRfmKxwXV+a6o7bTQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1436 Xref: feeder.eternal-september.org comp.lang.vhdl:4583 On Thu, 6 Jan 2011 11:03:41 -0800 (PST), d_s_klein wrote: |I wonder how many understand that 'iff' is not a typo. If and only if james From newsfish@newsfish Fri Feb 3 13:09:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!f20g2000vbc.googlegroups.com!not-for-mail From: Jonathan Ross Newsgroups: comp.lang.vhdl Subject: Programmable Logic and FPGA Design Stack Date: Tue, 11 Jan 2011 14:31:33 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <40214c5b-d347-47e4-94c9-6c163bf66103@f20g2000vbc.googlegroups.com> NNTP-Posting-Host: 72.5.43.201 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1294785093 26826 127.0.0.1 (11 Jan 2011 22:31:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 11 Jan 2011 22:31:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000vbc.googlegroups.com; posting-host=72.5.43.201; posting-account=m87LFgoAAADoHQtuLwQyC2N65M8PRiTd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_5; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.231 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4584 The Programmable Logic and FPGA Design Stack (from the creators of Stack Overflow, but specific to FPGAs) has finally gotten past the definition phase and is now in the commit phase. To reach a phase were we can use it we need more people to commit to using it. As VHDL and Verilog are the two main FPGA development languages it's likely many people here will be interested. Please commit to supporting it as soon as possible as sites that don't get enough attention are canceled. http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=im91SDhGvqGFAaI1gMp5oQ2 Best Regards, Jonathan Ross From newsfish@newsfish Fri Feb 3 13:09:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f20g2000prn.googlegroups.com!not-for-mail From: Richard Molgner Newsgroups: comp.lang.vhdl Subject: VHDL subprocedure call Date: Tue, 18 Jan 2011 05:27:54 -0800 (PST) Organization: http://groups.google.com Lines: 70 Message-ID: NNTP-Posting-Host: 137.222.102.176 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295357275 29938 127.0.0.1 (18 Jan 2011 13:27:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 18 Jan 2011 13:27:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000prn.googlegroups.com; posting-host=137.222.102.176; posting-account=VnhOuwoAAADcjmEmuM8HxuMsb-UYhuH3 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.7) Gecko/20100713 Firefox/3.6.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4585 Hi all, I have two nested procedures, where the "main" procedure makes use of "subproc" to accumulates a result in variables t0 and t1, which is then returned at the end. This should all be computed in one clock cycle, and the circuit more or less just consists of simple logic gates (xor, or, and). When I try to describe the circuit as below I get the following error: Acutal (variable t0) for formal "a" is not a signal That makes sense as the subprocure requires signals as input, but I wanna pass it a variable during the main procedure. Is there a simple way to circumvent this problem with casting for example? Thanks procedure subproc ( signal a : in std_logic_vector(31 downto 0); signal b : in std_logic_vector(31 downto 0); signal c : in std_logic_vector(31 downto 0); signal d : in std_logic_vector(31 downto 0); signal e : out std_logic_vector(31 downto 0); signal f : out std_logic_vector(31 downto 0) ) is variable x : std_logic_vector(31 downto 0); variable y : std_logic_vector(31 downto 0); begin x := (others => '0'); y := (others => '0'); for i in 0 to 31 loop x(i) := (a(i) xor b(i)) and (c(i) xor d(i)); y(i) := (a(i) xor b(i)) or ((d(i) xor c(i)) xor b(i)); end loop; e <= x(31 downto 0); f <= y(31 downto 0); end; procedure main ( signal a : in std_logic_vector(31 downto 0); signal b : in std_logic_vector(31 downto 0); signal r : out std_logic_vector(31 downto 0) ) is variable res : std_logic_vector(31 downto 0); variable t0, t1 : std_logic_vector(31 downto 0); constant c : std_logic_vector(31 downto 0) := X"fedcba90"; constant d : std_logic_vector(31 downto 0) := X"7654321f"; begin t0 := (others => '0'); t1 := (others => '0'); for i in 0 to 31 loop if ( (c(i) = '0') && (d(i) = '1') ) then subproc( t0, t1, a, b, t0, t1 ); end if; end loop; r <= t0; end; From newsfish@newsfish Fri Feb 3 13:09:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!f2g2000vby.googlegroups.com!not-for-mail From: Richard Molgner Newsgroups: comp.lang.vhdl Subject: Re: VHDL subprocedure call Date: Tue, 18 Jan 2011 06:29:09 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: References: NNTP-Posting-Host: 137.222.102.176 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295360949 32245 127.0.0.1 (18 Jan 2011 14:29:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 18 Jan 2011 14:29:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f2g2000vby.googlegroups.com; posting-host=137.222.102.176; posting-account=VnhOuwoAAADcjmEmuM8HxuMsb-UYhuH3 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.7) Gecko/20100713 Firefox/3.6.7,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4586 Hi again, I updated the routine now, and it looks as follows. Although it compiles fine, the output of the computation is ALWAYS ZERO. It seems with this software-like implementation I wont be able to describe the hardware circuit I want to. Or does anyone see a problem with my VHDL description? procedure main ( signal a : in std_logic_vector(31 downto 0); signal b : in std_logic_vector(31 downto 0); signal r : out std_logic_vector(31 downto 0) ) is variable res : std_logic_vector(31 downto 0); variable t0, t1 : std_logic_vector(31 downto 0); constant c : std_logic_vector(31 downto 0) := X"fedcba90"; constant d : std_logic_vector(31 downto 0) := X"7654321f"; begin t0 := (others => '0'); t1 := (others => '0'); for i in 0 to 31 loop if ( (c(i) = '0') and (d(i) = '1') ) then for j in 0 to 31 loop t0(j) := (a(j) xor b(j)) and (t0(j) xor t1(j)); t1(j) := (a(j) xor b(j)) or ((t1(j) xor t0(j)) xor b(j)); end loop; end if; end loop; r <= t0; end; many thanks From newsfish@newsfish Fri Feb 3 13:09:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: VHDL subprocedure call Date: Tue, 18 Jan 2011 15:38:10 +0000 Organization: TRW Conekt Lines: 62 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net YctK3NFXHtZXeIhHz9Eh7wb1iLAMNiZrN+CFzDcBTbvl7ikS4= Cancel-Lock: sha1:22TZOExxTBzoiBUysNlUFavA2AM= sha1:nx8QHAXTpzP0nNvnTNDvzWWtCqk= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4587 Richard Molgner writes: > Hi again, > > I updated the routine now, and it looks as follows. Although it > compiles fine, the output > of the computation is ALWAYS ZERO. In simulation or synthesis? I might expect the output to be all Us in simulation. Zeros seems plausible for synthesis. > It seems with this software-like > implementation I wont > be able to describe the hardware circuit I want to. Or does anyone see > a problem with my > VHDL description? > Have you put a call to that procedure inside an entity? Unless *you* call the procedure it won't get called - there's no implicit (well, startup-code defined) call to main like there is in c. The simulator "runs" a top-level entity that you tell it to. The synthesiser also works on a top-level entity. Procedures are not the "top" that you may be thinking they are. I'll attempt to describes what needs to go on (on the assumption that you are new to VHDL, not and old hand trying some new tricks :) If we're lucky, it's possible that Jonathan Bromley will also chip in and give you a description - his is likely to be much better than mine as he's (been) a professional trainer! Anyway.... What you have to do is create an "entity" which describes the interface (in terms of input and/or output pins) to the logic you want. (This interface will look like the procedure definition currently does.) That entity then has an "architecture" which describes what goes on inside the block to bring the ins and outs of that interface together. Your procedure is a description of some logic which can go inside that architecture... inside a "process". Processes control when code "runs", and you want to run yours whenever a or b changes. So you need to give a sensitivity list to the process which has both a and b in it. Then, whenever a or b changes, the process will run and that can call your procedure. At the end of the process, it will stop and wait for the next change on any of the signals in the sensitivity list. I hope that helps a little! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:10:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!nntp.cybernetik.net!216.196.98.142.MISMATCH!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!i32g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL subprocedure call Date: Tue, 18 Jan 2011 08:32:55 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <51b53098-ccdc-415a-b4a3-cb82d8437598@i32g2000pri.googlegroups.com> References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295368376 32073 127.0.0.1 (18 Jan 2011 16:32:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 18 Jan 2011 16:32:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i32g2000pri.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4588 On Jan 18, 9:29=A0am, Richard Molgner wrote: > Hi again, > > I updated the routine now, and it looks as follows. Although it > compiles fine, the output > of the computation is ALWAYS ZERO. It seems with this software-like > implementation I wont > be able to describe the hardware circuit I want to. Or does anyone see > a problem with my > VHDL description? > > =A0procedure main > =A0 =A0 ( > =A0 =A0 =A0 signal a : in =A0std_logic_vector(31 downto 0); > =A0 =A0 =A0 signal b : in =A0std_logic_vector(31 downto 0); > =A0 =A0 =A0 signal r : out std_logic_vector(31 downto 0) > =A0 =A0 ) > =A0 =A0 is > =A0 =A0 =A0 variable res : std_logic_vector(31 downto 0); > =A0 =A0 =A0 variable t0, t1 : std_logic_vector(31 downto 0); > =A0 =A0 =A0 constant c : std_logic_vector(31 downto 0) :=3D X"fedcba90"; > =A0 =A0 =A0 constant d : std_logic_vector(31 downto 0) :=3D > X"7654321f"; > =A0 =A0 begin > > =A0 =A0 =A0 t0 :=3D (others =3D> '0'); > =A0 =A0 =A0 t1 :=3D (others =3D> '0'); > > =A0 =A0 =A0 for i in 0 to 31 loop > =A0 =A0 =A0 =A0 if ( (c(i) =3D '0') and (d(i) =3D '1') ) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0for j in 0 to 31 loop > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0t0(j) :=3D (a(j) xor b(j)) and (t0(j) xor = t1(j)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0t1(j) :=3D (a(j) xor b(j)) or ((t1(j) xor = t0(j)) xor > b(j)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0end loop; > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end loop; > > =A0 =A0 =A0 r <=3D t0; > =A0 =A0 end; > > many thanks If you don't think it is calculating the result correctly, why don't you simulate it where you can view all the details? The calculations seem a bit odd. I can't picture what problem this might be solving. I also don't know why you make it so complicated. The constants c and d are only used in the "if" condition where they are bit-wise anded. Why couldn't you replace that with a single constant that has already been bit-wise anded? The rest of it is a bit too complex to analyze easily and you don't provide your test data. It looks to me like it would require a fairly special set of inputs on a and b to cause bits to be set in t0. First you have to get past the not c and d filter which only passes the 4 lsbs. If you computed the value of not c and d you would see this. Then in a bit-wise fashion, to set t0 it has to be different from t1. Since they are both initialized to all zeros, that means t1 has to be set. To set t1 either a and b must be different or t1, t0 and b must have an odd number of bits set. Are you sure your input vectors provide for anything other than zero bit values output? Rick From newsfish@newsfish Fri Feb 3 13:10:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l24g2000vby.googlegroups.com!not-for-mail From: "Guenter.Bartsch@googlemail.com" Newsgroups: comp.lang.vhdl Subject: IEEE 1076.6-2004 support, understanding the examples Date: Tue, 18 Jan 2011 09:49:06 -0800 (PST) Organization: http://groups.google.com Lines: 56 Message-ID: NNTP-Posting-Host: 88.65.228.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295372950 7826 127.0.0.1 (18 Jan 2011 17:49:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 18 Jan 2011 17:49:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l24g2000vby.googlegroups.com; posting-host=88.65.228.42; posting-account=9LIt0AoAAAD1RwjzmxSl-ZWHi9YEVn76 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.630.0 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4589 Hi everyone, I am currently working on VHDL RTL synthesis support for zamiacad (http://zamia.org) and stumbled upon the 2004 revision of the 1076.6 std. Until recently I wasn't aware this revision existed and now I am slowly making my way through the examples given in the standard. So far, I came across two questions (more to come, I guess ;)): (1) what is the general experience, do the proprietary tools in the market support the 2004 revision? parts of it, the whole thing? I just tried a few of the examples in Altera's Quartus II and none of them worked so I was beginning to wonder whether this might be a failed standard so far (although I must say I do like some of the ideas they outline in there). Can anybody recommend a tool that is known to have good 2004 support? (2) I do have trouble understanding some of the examples in there - Example 6 on page 11 in particular. I have come up with my own algorithm how to implement some of the synthesis rules so far and it seems to work on most examples _including_ example 6 which is supposed to be illegal. Basically what i am doing is compute logic expressions that act as conditions under which certain assignments happen. In example 6 we have: if rising_edge(clock) or reset = '1' then if reset = '1' then Q <= '0' ; -- assignment 1 else Q <= D; -- assignment 2 end if; end if; so assignment 1 happens when (clock' || reset) & reset is true which can be simplified to just reset so this is an async assignment of '0' to Q if reset='1'. for assignment 2 i get (clk' || reset) & ^reset = clk' & ^reset which is a sync assignment under the condition that reset='0' (which could actually be optimized out later since when reset='1' the async assignment kicks in). so this could be synthesized as a flipflop that has an asynchroneous reset, I guess? anyone see where I go wrong and why this example should be illegal? thanks and best regards, guenter From newsfish@newsfish Fri Feb 3 13:10:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d360fd8$0$34849$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: VHDL subprocedure call Newsgroups: comp.lang.vhdl Date: Tue, 18 Jan 2011 23:10:32 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 135 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295388632 news.xs4all.nl 34849 puiterl/[::ffff:195.242.97.150]:41898 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4590 Richard Molgner wrote: > Hi again, > > I updated the routine now, and it looks as follows. Although it > compiles fine, the output > of the computation is ALWAYS ZERO. It seems with this software-like > implementation I wont > be able to describe the hardware circuit I want to. Or does anyone see > a problem with my > VHDL description? > > procedure main > ( > signal a : in std_logic_vector(31 downto 0); > signal b : in std_logic_vector(31 downto 0); > signal r : out std_logic_vector(31 downto 0) > ) > is > variable res : std_logic_vector(31 downto 0); > variable t0, t1 : std_logic_vector(31 downto 0); > constant c : std_logic_vector(31 downto 0) := X"fedcba90"; > constant d : std_logic_vector(31 downto 0) := > X"7654321f"; > begin > > t0 := (others => '0'); > t1 := (others => '0'); > > for i in 0 to 31 loop > if ( (c(i) = '0') and (d(i) = '1') ) then > for j in 0 to 31 loop > t0(j) := (a(j) xor b(j)) and (t0(j) xor t1(j)); > t1(j) := (a(j) xor b(j)) or ((t1(j) xor t0(j)) xor > b(j)); > end loop; > end if; > end loop; > > r <= t0; > end; With the given values of constants c and d, the only bits for which the 'if' holds true are 0 to 3. Is that what you intended? As you have rewritten your code, you now modify t0 and then use it in the computation of t1. That is not what was intended in the original code, as far as I can see. It seems you messed up in an attempt to transform the original code. Let me try to modify that code so it will compile. No guarantees on functionality, I'll probably mess up as well! procedure subproc ( a : inout std_logic_vector(31 downto 0); b : inout std_logic_vector(31 downto 0); c : in std_logic_vector(31 downto 0); d : in std_logic_vector(31 downto 0) ) is variable x : std_logic_vector(31 downto 0); variable y : std_logic_vector(31 downto 0); begin x := (a xor b) and (c xor d); y := (a xor b) or ((d xor c) xor b); a := x; b := y; end; procedure main ( constant a : in std_logic_vector(31 downto 0); constant b : in std_logic_vector(31 downto 0); signal r : out std_logic_vector(31 downto 0) ) is variable t0, t1 : std_logic_vector(31 downto 0); constant c : std_logic_vector(31 downto 0) := X"fedcba90"; constant d : std_logic_vector(31 downto 0) := X"7654321f"; begin t0 := (others => '0'); t1 := (others => '0'); for i in c'range loop if (c(i) = '0') and (d(i) = '1') then subproc(t0, t1, a, b); end if; end loop; r <= t0; end; Remarks: 1) No need to always use separate bits. Operators like and, or, xor also work on vectors. No loop needed. 2) If you want to use the complete vector, there is no need to specify the range. So these are all equivalent: a := x; a := x(31 downto 0); a(31 downto 0) := x; a(31 downto 0) := x(31 downto 0); 3) Parameters of procedures need not always be of class signal. Depends on where they are used. 4) Parenthesis around the condition in an 'if' statement are not needed (style issue). VHDL is not C. 5) There is no operator &&: it is 'and'. VHDL is not C. 6) Variable res in procedure main was never used. 7) If you want to loop over all bits in a vector, use the 'range attribute. In my opinion it is clearer and it is more robust against code changes (like changing the vector length). 8) The class of parameters c and d of procedure subproc and parameters a and b of main all are constant. For input parameters that is the default. I have the habit to only actually specify the class of subprogram parameters if one of the parameters has a non-default class, such as parameter r of main in this case. 9) Simulate before synthesize. That also means: make a testbench. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!w2g2000vbp.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Wed, 19 Jan 2011 00:31:28 -0800 (PST) Organization: http://groups.google.com Lines: 144 Message-ID: References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295425888 32137 127.0.0.1 (19 Jan 2011 08:31:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 19 Jan 2011 08:31:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w2g2000vbp.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4591 On 18 Jan., 18:49, "Guenter.Bart...@googlemail.com" wrote: > Hi everyone, > > I am currently working on VHDL RTL synthesis support for zamiacad > (http://zamia.org) and stumbled upon the 2004 revision of the 1076.6 > std. Until recently I wasn't aware this revision existed and now I am > slowly making my way through the examples given in the standard. So > far, I came across two questions (more to come, I guess ;)): > > (1) what is the general experience, do the proprietary tools in the > market support the 2004 revision? parts of it, the whole thing? I just > tried a few of the examples in Altera's Quartus II and none of them > worked so I was beginning to wonder whether this might be a failed > standard so far (although I must say I do like some of the ideas they > outline in there). Can anybody recommend a tool that is known to have > good 2004 support? > > (2) I do have trouble understanding some of the examples in there - > Example 6 on page 11 in particular. I have come up with my own > algorithm how to implement some of the synthesis rules so far and it > seems to work on most examples _including_ example 6 which is supposed > to be illegal. Basically what i am doing is compute logic expressions > that act as conditions under which certain assignments happen. In > example 6 we have: > > if rising_edge(clock) or reset =3D '1' then > =A0 if reset =3D '1' then > =A0 =A0 Q <=3D '0' ; -- assignment 1 > =A0 else > =A0 =A0 Q <=3D D; -- assignment 2 > =A0 end if; > end if; > > so assignment 1 happens when > > (clock' || reset) & reset > > is true which can be simplified to just > > reset > > so this is an async assignment of '0' to Q if reset=3D'1'. > > for assignment 2 i get > > (clk' || reset) & ^reset =3D clk' & ^reset > > which is a sync assignment under the condition that reset=3D'0' (which > could actually be optimized out later since when reset=3D'1' the async > assignment kicks in). so this could be synthesized as a flipflop that > has an asynchroneous reset, I guess? anyone see where I go wrong and > why this example should be illegal? > > thanks and best regards, > > =A0 =A0guenter Hi Guenter, this is the synthesis part of the original standard. It refers to the 2002 release of the full VHDL standard (see top of page iii, which is page 4 in the pdf) That also explains, why it is two years "late" compared to the full standard. Tool vendors normally only refer to the original standard, not the derived substandards. So you probably won't find a tool that explicitly supports some 2004 release. I found the paper here: http://www.ece.gatech.edu/academic/courses/spring2007/ece4170/DesignDocumen= tation/IEEE_1076%206.pdf About the example: the violated rule (a) is mentioned. To become a valid synthesizable description I think the "else" should be replaced by "elsif rising_edge(clk) then". Anyway, the examples in the standard are kind of weird, in order to reflect the synthesis rules. They are not intended to bee good practice examples. Your musing about the code incorporates human understanding, but is not based on the rules given on page nine. See: . An assignment to a signal or variable that is controlled explicitly by in all execution paths. ... Edge-sensitive storage shall be modeled for a signal or variable assigned inside a process with sensitivity list when all of the following apply: a) The signal or variable has a . b) There is no execution path in which the value update from a overrides the value update from an unless the is an assignment to itself. c) It is possible to statically enumerate all execution paths to the signal or variable assignments. d) The process sensitivity list includes the clock and any signal controlling an . e) The is present in the conditions only, and the always expresses the same edge of the same clock signal. f) For a variable, the value written by a given clock edge is read during a subsequent clock edge. Rule a is violated by the example because the first if may be triggered by a rising edge of the clock signal only, but the assignment Q<=3DD is just depending on the state of reset. On first reading I stepped into the same trap as you did. The problem is that event triggereing (rising_edge) and state logic can not be mixed up the way you did. let me reanalyse the code: first if: entered on rising clock edge or active reset. (This allows the tool to proceed reading the code, nothing more, nothing less) second if: Deciding which of two asynchronous assignments has to be mate relating to the state of reset. (Tool doesn't know why it is reading this.) --- If the tool would remember why it has entered the second if, there may be the chance that on active reset you also have a rising clock edge. This would cause a flipflop to be synthesized. But at anoter time when Reset is active but there's no rising clock edge, for the same if, just some asynchronous assignment has to be done, and no Flip Flop will be synthesized. This is a contradiction the synthesis tool can't resolve. The mistake you made is that you can not overrule the rising clock edge with logical optimization of the clock signal. It has to be treated different. For this one example your method may work, but when things become more complicated (e.g. with clockenables and/or mixing of asynchronous and synchronous reset/presets) it will fail. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:10:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w2g2000vbp.googlegroups.com!not-for-mail From: "Guenter.Bartsch@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Wed, 19 Jan 2011 08:17:38 -0800 (PST) Organization: http://groups.google.com Lines: 187 Message-ID: <2c218d93-b7bc-46ba-9a32-34ab03d68945@w2g2000vbp.googlegroups.com> References: NNTP-Posting-Host: 88.67.82.154 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295453859 18099 127.0.0.1 (19 Jan 2011 16:17:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 19 Jan 2011 16:17:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w2g2000vbp.googlegroups.com; posting-host=88.67.82.154; posting-account=9LIt0AoAAAD1RwjzmxSl-ZWHi9YEVn76 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.630.0 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4592 Eilert, first of all thank you for your quick and very detailed answer, you helped me a lot! On Jan 19, 3:31=A0am, backhus wrote: > this is the synthesis part of the original standard. > It refers to the 2002 release of the full VHDL standard (see top of > page iii, which is page 4 in the pdf) > That also explains, why it is two years "late" compared to the full > standard. > Tool vendors normally only refer to the original standard, not the > derived substandards. > So you probably won't find a tool that explicitly supports some 2004 > release. I guess you're right :) - at least the big vendors hardly ever mention the 1076.6 standard (no matter which revision). for simulation, that is completely fine, but I do wonder why they do not claim at least 1076.6-1999 conformance for their synthesis tools. Anyway, my question was more about what is working in practice - so what user's experiences are in the real world when they try to model hardware the way the 2004 revision describes it - e.g. does design compiler handle multiple wait statements in one process? sync assignments controlled by "complicated boolean expressions"? > About the example: > the violated rule (a) is mentioned. > To become a valid synthesizable description I think the "else" should > be replaced by > "elsif rising_edge(clk) then". I was kinda wondering why they keep repeating parts of the conditional expressions in the other examples ;) that explains a lot - however, I have no clue why they're specifying this the way they do - maybe I'm viewing this from a completely wrong perspective, but it seems very complicated and unelegant to me... > > See: > . An assignment to a signal or variable that is > controlled explicitly by in > all execution paths. > ... > Edge-sensitive storage shall be modeled for a signal or variable > assigned inside a process with sensitivity list > when all of the following apply: > a) The signal or variable has a . > b) There is no execution path in which the value update from a > overrides the value > update from an unless the is an > assignment to itself. > c) It is possible to statically enumerate all execution paths to the > signal or variable assignments. > d) The process sensitivity list includes the clock and any signal > controlling an . > e) The is present in the conditions only, and the > always expresses the > same edge of the same clock signal. > f) For a variable, the value written by a given clock edge is read > during a subsequent clock edge. > > Rule a is violated by the example because the first if may be > triggered by a rising edge of the clock signal only, > but the assignment Q<=3DD is just depending on the state of reset. obviously I am reading the rules wrong in here - I thought rule a) is met since there is a sync assignment (Q <=3D D since the two if- statements around it result in if rising_edge(clk)) - there is, of course, also an async assignment (Q<=3D'0') but rule a) doesn't specify that there have to be _only_ sync assignments. > On first reading I stepped into the same trap as you did. > The problem is that event triggereing (rising_edge) and state logic > can not be mixed up the way you did. > let me reanalyse the code: > first if: entered on rising clock edge or active reset. (This allows > the tool to proceed reading the code, nothing more, nothing less) > second if: Deciding which of two asynchronous assignments has to be > mate relating to the state of reset. (Tool doesn't know why it is > reading this.) I really do not understand when and why the tool is supposed to forget about outer if-conditions - is that specified anywhere in the standard? But you're right, the algorithm I am thinking about does collect if- conditions, ands them together (or and-nots them together in case of else-branches) and then analyses them when it reaches an assignment. so in this case i'd end up with (rising_edge(clk) or reset=3D'1') and not (reset=3D'1') which I could then simplify into rising_edge(clk) > --- > If the tool would remember why it has entered the second if, there may > be the chance that on active reset you also have a rising clock edge. > This would cause a flipflop to be synthesized. > But at anoter time when Reset is active but there's no rising clock > edge, for the same if, just some asynchronous assignment has to be > done, and no Flip Flop will be synthesized. > This is a contradiction the synthesis tool can't resolve. ok - the part I obviously do not understand is the one where conditions from outer if-statements get dropped. With the approach I have in mind this would cleanly synthesize as a flipflop that has an asynchroneous reset-input, I think. > The mistake you made is that you can not overrule the rising clock > edge with logical optimization of the clock signal. It has to be > treated different. > For this one example your method may work, but when things become more > complicated (e.g. with clockenables and/or mixing of asynchronous and > synchronous reset/presets) it will fail. can you five an example where my approach would fail? I must confess, I have only sketched it so far and will need to write it down in a formal way (I am writing a paper right now ;) ) - my idea was basically to collect conditions, basically I have an expression engine which can handle logic equations, arithmetic expressions and you can also have clock edge specifications in there, all mixed together and it will apply standard optimizations to those expressions. whenever I reach an assignment, I look at the current condition I have collected, optimize it down and check, whether it still contains a clock edge or not. if it does contain a clock edge, i will use that clock for a flipflop (which can have additional async inputs, if needed to synthesize other assignments) clk input, will tell the expression engine to tread that part of the expression as don't care and optimize it further down, which i will then use to synthesize synced enable and data inputs for the flipflop. I do wonder how much of the standard I cover, where I am not compliant - I am definitely not "bug-compatible" with my approach since obviously I can handle designs which I shouldn't be able to handle. Actually, I could easily live with that - but I am worried about examples that I should be able according to the standard which my approach fails to handle. BTW: in the meantime I have read on. I was very surprised about 6.1.3.3 where they allow multiple clock signals for assignments to the same signal - I wonder what that would result in when synthesized - would I need flip flops that have several separate clock inputs in my target library to support that? in chapter 6.1.3.4 they model implicit FSMs using multiple wait- statements in a single process - which I could imagine is pretty useful (I was always wondering why VHDL doesn't have a syntax for FSMs) but then again I have trouble really understanding their rules. What gives me most headaches is the way they use loops and next statements: from the examples I gather that they - have at most one outer infinite loop and next-statements immediately following the wait statements to model the async reset state. the rules they state are pretty elaborate about the conditions used in the wait statements having to be the same throughout the process - not pretty, but makes sense. but i don't see them specify anywhere that the next statement has to follow the wait statement immediately, nor, that one can have at most one such infinite loop - so I wonder what would happen if the user breaks these rules? has next statements in arbitrary locations or nests infinite loops, possibly mixed with if- and for-loops, has multiple labels in there, uses next-statements to jump to any of them? is all that forbidden or is the tool supposed to handle all that in some way? - maybe a simpler question: is there a rules which dictates that if one wants to have wait statements in for-loops, it has to be the first statement in the loop body? that assumption certainly holds for the examples they give, yet i cannot find a rule about that what I am aiming for maybe has become clear already: I'd like to extend my approach to handle FSM specifications as well - I would basically treat the examples before 6.1.3.4 as mealy automata that have at most one state (plus additional async logic) and would like to extend my approach smoothly to FSM descriptions which then generate automata with multiple states (basically one per wait-statement). thanks again for your help, sorry for my far too long post and best regards, guenter From newsfish@newsfish Fri Feb 3 13:10:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o14g2000prn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Wed, 19 Jan 2011 12:06:47 -0800 (PST) Organization: http://groups.google.com Lines: 76 Message-ID: References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295467608 18466 127.0.0.1 (19 Jan 2011 20:06:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 19 Jan 2011 20:06:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4593 On Jan 18, 12:49=A0pm, "Guenter.Bart...@googlemail.com" wrote: > Hi everyone, > > I am currently working on VHDL RTL synthesis support for zamiacad > (http://zamia.org) and stumbled upon the 2004 revision of the 1076.6 > std. Until recently I wasn't aware this revision existed and now I am > slowly making my way through the examples given in the standard. So > far, I came across two questions (more to come, I guess ;)): > > (1) what is the general experience, do the proprietary tools in the > market support the 2004 revision? parts of it, the whole thing? I just > tried a few of the examples in Altera's Quartus II and none of them > worked so I was beginning to wonder whether this might be a failed > standard so far (although I must say I do like some of the ideas they > outline in there). Can anybody recommend a tool that is known to have > good 2004 support? > > (2) I do have trouble understanding some of the examples in there - > Example 6 on page 11 in particular. I have come up with my own > algorithm how to implement some of the synthesis rules so far and it > seems to work on most examples _including_ example 6 which is supposed > to be illegal. Basically what i am doing is compute logic expressions > that act as conditions under which certain assignments happen. In > example 6 we have: > > if rising_edge(clock) or reset =3D '1' then > =A0 if reset =3D '1' then > =A0 =A0 Q <=3D '0' ; -- assignment 1 > =A0 else > =A0 =A0 Q <=3D D; -- assignment 2 > =A0 end if; > end if; > > so assignment 1 happens when > > (clock' || reset) & reset > > is true which can be simplified to just > > reset > > so this is an async assignment of '0' to Q if reset=3D'1'. > > for assignment 2 i get > > (clk' || reset) & ^reset =3D clk' & ^reset > > which is a sync assignment under the condition that reset=3D'0' (which > could actually be optimized out later since when reset=3D'1' the async > assignment kicks in). so this could be synthesized as a flipflop that > has an asynchroneous reset, I guess? anyone see where I go wrong and > why this example should be illegal? As Eilert says, you need the risingedge test in the IF statement for this to be valid. Why? Because the sensitivity list is not the same as a condition test. The values in the sensitivity list do not need to be true for the process to run, there only needs to be a change in the items in the list for the process to run. So your logical analysis above is flawed. For example, when the reset is asserted, the process runs and the reset clause of the IF is executed. When the reset is deasserted the process runs again and the else clause of the IF is executed, which a FF will only perform on the rising edge of the clock. It seems like an inefficiency for a sensitivity clause to allow a process to run when nothing is supposed to happen, but I assume the simulation vendors know how to optimize this so it has little impact. Otherwise I would want to tailor my sensitivity list to only run on the leading edge of the reset and not all transitions. BTW, if you assign anything other than a constant value in the reset clause of the IF, it is no longer a standard DFF with async reset and you must add those signals to the sensitivity list for it to simulate properly. Rick From newsfish@newsfish Fri Feb 3 13:10:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!y31g2000vbt.googlegroups.com!not-for-mail From: "Guenter.Bartsch@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Wed, 19 Jan 2011 12:49:24 -0800 (PST) Organization: http://groups.google.com Lines: 57 Message-ID: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> References: NNTP-Posting-Host: 88.67.82.154 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295470164 9292 127.0.0.1 (19 Jan 2011 20:49:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 19 Jan 2011 20:49:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbt.googlegroups.com; posting-host=88.67.82.154; posting-account=9LIt0AoAAAD1RwjzmxSl-ZWHi9YEVn76 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.630.0 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4594 Rick, On Jan 19, 9:06=A0pm, rickman wrote: > > > if rising_edge(clock) or reset =3D '1' then > > =A0 if reset =3D '1' then > > =A0 =A0 Q <=3D '0' ; -- assignment 1 > > =A0 else > > =A0 =A0 Q <=3D D; -- assignment 2 > > =A0 end if; > > end if; > > As Eilert says, you need the risingedge test in the IF statement for > this to be valid. =A0Why? =A0Because the sensitivity list is not the same > as a condition test. =A0The values in the sensitivity list do not need > to be true for the process to run, there only needs to be a change in > the items in the list for the process to run. =A0So your logical > analysis above is flawed. actually the outer if-statement does have the risingedge test, so that is not the point :o) what puzzles me is that apparently the else-branch of the inner if- statement needs the risingedge-test again. of course, if one wanted this example to be completely synchroneous then yes, there needs to be a risingedge-test in the else-branch (or one could just drop the "or reset=3D'1'" part from the outer if in the first place... ). all that of course requires the synthesis tool to remember all nested if- conditions - if the synthesis tool is to forget the outer if-condition then yes, it would need to be repeated. > For example, when the reset is asserted, the process runs and the > reset clause of the IF is executed. =A0When the reset is deasserted the > process runs again and the else clause of the IF is executed, which a > FF will only perform on the rising edge of the clock. if reset switches to '0' and there is no clk event, the inner if never gets executed since neither "risingedge(clk)" nor "reset=3D'1'" is true if reset switches to '0' and clk has a rising edge, the else branch of the inner if does indeed execute, but that would be a synchroneous assignment. > =A0BTW, if you > assign anything other than a constant value in the reset clause of the > IF, it is no longer a standard DFF with async reset my tool would use a DFF with async reset and set signals in that case > and you must add > those signals to the sensitivity list for it to simulate properly. agreed :) thanks for your reply and best regards, guenter From newsfish@newsfish Fri Feb 3 13:10:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q18g2000vbk.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Thu, 20 Jan 2011 03:42:19 -0800 (PST) Organization: http://groups.google.com Lines: 148 Message-ID: <51f76ba2-2adc-4f2a-840b-e542ace5d8b5@q18g2000vbk.googlegroups.com> References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295523739 4014 127.0.0.1 (20 Jan 2011 11:42:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 11:42:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbk.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4595 On 19 Jan., 21:49, "Guenter.Bart...@googlemail.com" wrote: > Rick, > > On Jan 19, 9:06=A0pm, rickman wrote: > > > > > > if rising_edge(clock) or reset =3D '1' then > > > =A0 if reset =3D '1' then > > > =A0 =A0 Q <=3D '0' ; -- assignment 1 > > > =A0 else > > > =A0 =A0 Q <=3D D; -- assignment 2 > > > =A0 end if; > > > end if; > > > As Eilert says, you need the risingedge test in the IF statement for > > this to be valid. =A0Why? =A0Because the sensitivity list is not the sa= me > > as a condition test. =A0The values in the sensitivity list do not need > > to be true for the process to run, there only needs to be a change in > > the items in the list for the process to run. =A0So your logical > > analysis above is flawed. > > actually the outer if-statement does have the risingedge test, so that > is not the point :o) > > what puzzles me is that apparently the else-branch of the inner if- > statement needs the risingedge-test again. of course, if one wanted > this example to be completely synchroneous then yes, there needs to be > a risingedge-test in the else-branch (or one could just drop the "or > reset=3D'1'" part from the outer if in the first place... ). all that of > course requires the synthesis tool to remember all nested if- > conditions - if the synthesis tool is to forget the outer if-condition > then yes, it would need to be repeated. > > > For example, when the reset is asserted, the process runs and the > > reset clause of the IF is executed. =A0When the reset is deasserted the > > process runs again and the else clause of the IF is executed, which a > > FF will only perform on the rising edge of the clock. > > if reset switches to '0' and there is no clk event, the inner if never > gets executed since neither "risingedge(clk)" nor "reset=3D'1'" is true > > if reset switches to '0' and clk has a rising edge, the else branch of > the inner if does indeed execute, but that would be a synchroneous > assignment. > > > =A0BTW, if you > > assign anything other than a constant value in the reset clause of the > > IF, it is no longer a standard DFF with async reset > > my tool would use a DFF with async reset and set signals in that case > > > and you must add > > those signals to the sensitivity list for it to simulate properly. > > agreed :) > > thanks for your reply and best regards, > > =A0 =A0guenter Hi, you probably know, but just to clarify for other readers: Synthesis tools don't care about the sensitivity list of a process. Guenther asked for an example, so I give it a try: if rising_edge(clock) or areset =3D '1' or sreset =3D '1'then if reset =3D '1' then Q <=3D '0' ; -- assignment 1 elsif sreset =3D '1' then Q <=3D '0' ; -- assignment 1 else Q <=3D D; -- assignment 2 end if; end if; So, how do you decide by logic reduction which of these is the synchronous reset? ;-) Following rule a) this should work: if rising_edge(clock) or areset =3D '1' or sreset =3D '1'then if reset =3D '1' then Q <=3D '0' ; -- assignment 1 elsif rising_edge(clock) and sreset =3D '1' then Q <=3D '0' ; -- assignment 1 elsif rising_edge(clock) then Q <=3D D; -- assignment 2 end if; end if; You also asked why synthesis tool vendors don't mention to comply to the synthesis standard. Maybe because they just don't support everything of it. Sometimes just because the target architecture can't handle all of the allowed constructs anyway. Like multiple clocked processes or dual edge Flipflops. Also, the tool vendors are more concerned about supporting approved coding styles and useful extra features (like file I/O for ROM contents) that are not covered by the syntehsis standard. I remember the good old WARP compiler for Cypress CPLDs (way back when in the las millenium). There you had to follow a strict template for synchronous descriptions. All other styles, that work well for other synthesis tools, were simply rejected. Tools become better now, but still they are focussed on a special target architecture, while the VHDL standard has to cover everything. So, if a synthesis tool understands many or all of the good examples this is a real progress. As I said before, the known-bad example looked weird to me. Even when corrected according to the rules. The point is, that neither for simulation nor for synthesis the pseudo- sensitivity-list made with the first if-condition makes sense. It's just code redundancy, and that can cause errors. Lets take a look at the everyday synchronous process: goodsync: process (reset, clock) is variable Data : std_logic_vector 8 downto 0); -- just an example begin if Reset =3D '1' then -- the asynchronous part starts here Data <=3D (others =3D> '0'); elsif rising_edge(clock) then -- the synchronous part starts here Data <=3D Input end if; Output <=3D Data; -- Just some renaming, in case Data has a feedback path (Yes, asynchronous, but theres nothing really happening here) end process goodsync; So, here we have clean separated areas for asynchronous and synchronous coded stuff, and no repetition. Its just useles to mention in the code that reset shall be '0' during the synchronous part. If it's '1' the other branch isn't reached anyway. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:10:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f35g2000vbl.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Thu, 20 Jan 2011 08:36:09 -0800 (PST) Organization: http://groups.google.com Lines: 101 Message-ID: <7d893a46-ee5c-48ea-8826-fd85ea9117e7@f35g2000vbl.googlegroups.com> References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295541369 20152 127.0.0.1 (20 Jan 2011 16:36:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 16:36:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f35g2000vbl.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4596 On Jan 19, 3:49=A0pm, "Guenter.Bart...@googlemail.com" wrote: > Rick, > > On Jan 19, 9:06=A0pm, rickman wrote: > > > > if rising_edge(clock) or reset =3D '1' then > > > =A0 if reset =3D '1' then > > > =A0 =A0 Q <=3D '0' ; -- assignment 1 > > > =A0 else > > > =A0 =A0 Q <=3D D; -- assignment 2 > > > =A0 end if; > > > end if; > > > As Eilert says, you need the risingedge test in the IF statement for > > this to be valid. =A0Why? =A0Because the sensitivity list is not the sa= me > > as a condition test. =A0The values in the sensitivity list do not need > > to be true for the process to run, there only needs to be a change in > > the items in the list for the process to run. =A0So your logical > > analysis above is flawed. > > actually the outer if-statement does have the risingedge test, so that > is not the point :o) You misunderstand. No changes in clock will trigger the process other than the rising edge, but any transition of the reset=3D1 expression will trigger execution of the process. Any transition that does not result in reset=3D'1' being true will be handled by the else clause and treated as if it were a rising edge of the clock signal. Try it yourself in simulation. If you have the D input high at the time the reset signal goes low, the Q output will be set high as if it had been clocked! That behavior is not synthesizable as a DFF. > what puzzles me is that apparently the else-branch of the inner if- > statement needs the risingedge-test again. of course, if one wanted > this example to be completely synchroneous then yes, there needs to be > a risingedge-test in the else-branch (or one could just drop the "or > reset=3D'1'" part from the outer if in the first place... ). all that of > course requires the synthesis tool to remember all nested if- > conditions - if the synthesis tool is to forget the outer if-condition > then yes, it would need to be repeated. You need to realize that rising_edge(clock) and changes in reset=3D'1' are not mutually exclusive. So you can enter the process under other conditions such as the falling edge of reset! Oddly enough, in Verilog you don't need the rising edge condition on clock in the IF, but then they require a rising edge condition of reset in the sensitivity list... I think. I've seen some code that doesn't use it, but that was in a second rate tutorial. > > For example, when the reset is asserted, the process runs and the > > reset clause of the IF is executed. =A0When the reset is deasserted the > > process runs again and the else clause of the IF is executed, which a > > FF will only perform on the rising edge of the clock. > > if reset switches to '0' and there is no clk event, the inner if never > gets executed since neither "risingedge(clk)" nor "reset=3D'1'" is true This is what you don't get. The sensitivity list is not an IF statement. It lists the conditions of which ANY CHANGE will cause the process to be run. Rising_edge is defined so that it only triggers on the rising edge. But reset=3D1 changes any time reset changes to or FROM a 1. So it triggers the process to run on both the leading and falling edge of reset. That is why they use rising_edge and falling_edge functions. > if reset switches to '0' and clk has a rising edge, the else branch of > the inner if does indeed execute, but that would be a synchroneous > assignment. If reset=3D1 triggered when it was true and not on a change, it would run the process continually while reset was asserted. Not good for performance. Also, if there is no change in an expression, it can have no impact on the value of the assignments. So instead they trigger on changes. > > =A0BTW, if you > > assign anything other than a constant value in the reset clause of the > > IF, it is no longer a standard DFF with async reset > > my tool would use a DFF with async reset and set signals in that case > > > and you must add > > those signals to the sensitivity list for it to simulate properly. > > agreed :) > > thanks for your reply and best regards, I hope you understand this now. Rick From newsfish@newsfish Fri Feb 3 13:10:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j1g2000vbl.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Thu, 20 Jan 2011 08:43:36 -0800 (PST) Organization: http://groups.google.com Lines: 89 Message-ID: <3d84a15f-d650-4382-b919-f01abf9c90e2@j1g2000vbl.googlegroups.com> References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> <51f76ba2-2adc-4f2a-840b-e542ace5d8b5@q18g2000vbk.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295541817 4070 127.0.0.1 (20 Jan 2011 16:43:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 16:43:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j1g2000vbl.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4597 On Jan 20, 6:42 am, backhus wrote: > On 19 Jan., 21:49, "Guenter.Bart...@googlemail.com" > > wrote: > > Rick, > > > On Jan 19, 9:06 pm, rickman wrote: > > > > > if rising_edge(clock) or reset = '1' then > > > > if reset = '1' then > > > > Q <= '0' ; -- assignment 1 > > > > else > > > > Q <= D; -- assignment 2 > > > > end if; > > > > end if; > > > > As Eilert says, you need the risingedge test in the IF statement for > > > this to be valid. Why? Because the sensitivity list is not the same > > > as a condition test. The values in the sensitivity list do not need > > > to be true for the process to run, there only needs to be a change in > > > the items in the list for the process to run. So your logical > > > analysis above is flawed. > > > actually the outer if-statement does have the risingedge test, so that > > is not the point :o) > > > what puzzles me is that apparently the else-branch of the inner if- > > statement needs the risingedge-test again. of course, if one wanted > > this example to be completely synchroneous then yes, there needs to be > > a risingedge-test in the else-branch (or one could just drop the "or > > reset='1'" part from the outer if in the first place... ). all that of > > course requires the synthesis tool to remember all nested if- > > conditions - if the synthesis tool is to forget the outer if-condition > > then yes, it would need to be repeated. > > > > For example, when the reset is asserted, the process runs and the > > > reset clause of the IF is executed. When the reset is deasserted the > > > process runs again and the else clause of the IF is executed, which a > > > FF will only perform on the rising edge of the clock. > > > if reset switches to '0' and there is no clk event, the inner if never > > gets executed since neither "risingedge(clk)" nor "reset='1'" is true > > > if reset switches to '0' and clk has a rising edge, the else branch of > > the inner if does indeed execute, but that would be a synchroneous > > assignment. > > > > BTW, if you > > > assign anything other than a constant value in the reset clause of the > > > IF, it is no longer a standard DFF with async reset > > > my tool would use a DFF with async reset and set signals in that case > > > > and you must add > > > those signals to the sensitivity list for it to simulate properly. > > > agreed :) > > > thanks for your reply and best regards, > > > guenter > > Hi, > you probably know, but just to clarify for other readers: > Synthesis tools don't care about the sensitivity list of a process. > > Guenther asked for an example, so I give it a try: > > if rising_edge(clock) or areset = '1' or sreset = '1'then > if reset = '1' then > Q <= '0' ; -- assignment 1 > elsif sreset = '1' then > Q <= '0' ; -- assignment 1 > else > Q <= D; -- assignment 2 > end if; > end if; This is NOT the same as a sensitivity list.... I think. First, an IF can only be used inside a process and that process will have a sensitivity list. But assuming you instead implemented this in an equivalent conditional assignment statement, the assignment would be triggered to run on ANY change in areset='1' or sreset='1'. So like Guenter's example, the deassertion of areset or sreset will trigger the assignment and cause Q to be set to the value of D like a clock edge. Rick From newsfish@newsfish Fri Feb 3 13:10:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!m35g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Thu, 20 Jan 2011 09:02:47 -0800 (PST) Organization: http://groups.google.com Lines: 7 Message-ID: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295542967 1670 127.0.0.1 (20 Jan 2011 17:02:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 17:02:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m35g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4598 The title is self explanatory. When found that Verilog lets you use a * in the sensitivity list of a combinatorial process. Why doesn't VHDL have that? There doesn't seem to be a down side that I can think of. Didn't they just finalize changes to VHDL in 2008? Isn't seven years enough time to pick up on a useful feature like this? Rick From newsfish@newsfish Fri Feb 3 13:10:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 20 Jan 2011 11:07:20 -0600 Date: Thu, 20 Jan 2011 09:07:23 -0800 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 17 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-3sGyACEzi0yAW0DeOthZiIHVeRamDT9EED1sBAnrcZsFIyoKb+ax5lkfpACTeSbW8kfmr1VYe4Eyqi9!HeDOqG74ArHxm6ei5dOAQZ98EwbF6pxImUBJlY5uqcBdN/TvCuR5B6oewfYCoT29F4wIR9nOjyS1!Ag== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1852 Xref: feeder.eternal-september.org comp.lang.vhdl:4599 On 1/20/2011 9:02 AM, rickman wrote: > The title is self explanatory. When found that Verilog lets you use a > * in the sensitivity list of a combinatorial process. Why doesn't > VHDL have that? There doesn't seem to be a down side that I can think > of. Didn't they just finalize changes to VHDL in 2008? Isn't seven > years enough time to pick up on a useful feature like this? > > Rick Someone correct me if I'm wrong, but I think VHDL2008 allows for 'all' as a sensitivity list. Now, that said, just TRY to find a synthesis tool that supports it. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:10:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe20.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Lines: 33 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe20.ams2 1295543607 213.105.6.183 (Thu, 20 Jan 2011 17:13:27 UTC) NNTP-Posting-Date: Thu, 20 Jan 2011 17:13:27 UTC Organization: virginmedia.com Date: Thu, 20 Jan 2011 17:13:10 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4600 "Rob Gaddi" wrote in message news:s82dnYG3SLRV9qXQnZ2dnUVZ_vudnZ2d@lmi.net... > On 1/20/2011 9:02 AM, rickman wrote: >> The title is self explanatory. When found that Verilog lets you use a >> * in the sensitivity list of a combinatorial process. Why doesn't >> VHDL have that? There doesn't seem to be a down side that I can think >> of. Didn't they just finalize changes to VHDL in 2008? Isn't seven >> years enough time to pick up on a useful feature like this? >> >> Rick > > Someone correct me if I'm wrong, but I think VHDL2008 allows for 'all' as a > sensitivity list. Yes process(all) works fine in Modelsim 10.0 and ActiveHDL/Riviera, not sure about ncsim, isim etc. > > Now, that said, just TRY to find a synthesis tool that supports it. Precision and Synplify and I believe QNS (not 100% sure), Hans www.ht-lab.com > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order > From newsfish@newsfish Fri Feb 3 13:10:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q18g2000vbk.googlegroups.com!not-for-mail From: "Guenter.Bartsch@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Thu, 20 Jan 2011 10:13:40 -0800 (PST) Organization: http://groups.google.com Lines: 125 Message-ID: References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> <7d893a46-ee5c-48ea-8826-fd85ea9117e7@f35g2000vbl.googlegroups.com> NNTP-Posting-Host: 88.66.108.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295547222 20617 127.0.0.1 (20 Jan 2011 18:13:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 18:13:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q18g2000vbk.googlegroups.com; posting-host=88.66.108.116; posting-account=9LIt0AoAAAD1RwjzmxSl-ZWHi9YEVn76 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.630.0 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4601 Rick, On Jan 20, 11:36=A0am, rickman wrote: > > > > if rising_edge(clock) or reset =3D '1' then > > > > =A0 if reset =3D '1' then > > > > =A0 =A0 Q <=3D '0' ; -- assignment 1 > > > > =A0 else > > > > =A0 =A0 Q <=3D D; -- assignment 2 > > > > =A0 end if; > > > > end if; > > > > As Eilert says, you need the risingedge test in the IF statement for > > > this to be valid. =A0Why? =A0Because the sensitivity list is not the = same > > > as a condition test. =A0The values in the sensitivity list do not nee= d > > > to be true for the process to run, there only needs to be a change in > > > the items in the list for the process to run. =A0So your logical > > > analysis above is flawed. > > > actually the outer if-statement does have the risingedge test, so that > > is not the point :o) > > You misunderstand. =A0No changes in clock will trigger the process other > than the rising edge, but any transition of the reset=3D1 expression > will trigger execution of the process. =A0Any transition that does not > result in reset=3D'1' being true will be handled by the else clause and > treated as if it were a rising edge of the clock signal. =A0Try it > yourself in simulation. =A0If you have the D input high at the time the > reset signal goes low, the Q output will be set high as if it had been > clocked! tried it in ghdl and q stays '0', just as i expected. here is the test program i tried: use std.textio.all; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; entity dir_test is end dir_test; architecture behaviour of dir_test is signal clock, reset, d, q : std_logic; begin process (clock, reset, d) begin if rising_edge(clock) or reset =3D '1' then if reset =3D '1' then Q <=3D '0' ; -- assignment 1 else Q <=3D D; -- assignment 2 end if; end if; end process; tb: process function to_string (value : STD_LOGIC) return STRING is begin if value =3D '1' then return "1"; else return "0"; end if; end function to_string; variable l : line; begin clock <=3D '0'; reset <=3D '0'; d <=3D '1'; wait for 10 ns; write (l, "clock: " & to_string(clock) & ", reset: " & to_string(reset) & ", q: " & to_string(q)); writeline (output, l); clock <=3D '0'; reset <=3D '1'; d <=3D '1'; wait for 10 ns; write (l, "clock: " & to_string(clock) & ", reset: " & to_string(reset) & ", q: " & to_string(q)); writeline (output, l); clock <=3D '0'; reset <=3D '0'; d <=3D '1'; wait for 10 ns; write (l, "clock: " & to_string(clock) & ", reset: " & to_string(reset) & ", q: " & to_string(q)); writeline (output, l); wait; end process; end behaviour; output I get: clock: 0, reset: 0, q: 0 clock: 0, reset: 1, q: 0 clock: 0, reset: 0, q: 0 best regards, guenter From newsfish@newsfish Fri Feb 3 13:10:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Thu, 20 Jan 2011 19:33:06 +0000 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6402"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+kB6cjNpwyn17Ofk0Rmb7qKj0Y5d+3zCw=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:4kY9GjN4RekU0aU8WUHZc8p/Qh4= Xref: feeder.eternal-september.org comp.lang.vhdl:4602 On Thu, 20 Jan 2011 09:02:47 -0800 (PST), rickman wrote: >The title is self explanatory. When found that Verilog lets you use a >* in the sensitivity list of a combinatorial process. Why doesn't >VHDL have that? There doesn't seem to be a down side that I can think >of. Didn't they just finalize changes to VHDL in 2008? Isn't seven >years enough time to pick up on a useful feature like this? heh. As others have said, "process(all)" is in VHDL-2008 and it's just a matter of waiting for Your Favourite Tool (TM) to support it. However, don't believe everything you read in the headlines. You do know about the flaws in Verilog @*, don't you? :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t8g2000prh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Thu, 20 Jan 2011 11:37:42 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <454c7769-8730-4e7d-8633-9a0a05822cc9@t8g2000prh.googlegroups.com> References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> <7d893a46-ee5c-48ea-8826-fd85ea9117e7@f35g2000vbl.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295552262 20163 127.0.0.1 (20 Jan 2011 19:37:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 19:37:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000prh.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4603 > > You misunderstand. =A0No changes in clock will trigger the process other > than the rising edge, but any transition of the reset=3D1 expression > will trigger execution of the process. =A0Any transition that does not > result in reset=3D'1' being true will be handled by the else clause and > treated as if it were a rising edge of the clock signal. =A0Try it > yourself in simulation. =A0If you have the D input high at the time the > reset signal goes low, the Q output will be set high as if it had been > clocked! No it won't! The outer "if rising_edge(clock) or reset =3D '1' then" statement will prevent any assignment if rising_edge() is false and reset is '0'. Don't confuse "triggering a process," and "executing code within that process" Any event on any signal in the sensitivity list will "trigger the process," and start execution of the first executable statement. Whether other code within that process gets executed is dependent upon BOTH the process being triggered, AND any surrounding conditional statements. Andy From newsfish@newsfish Fri Feb 3 13:10:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!v12g2000vbx.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Thu, 20 Jan 2011 14:52:34 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: References: NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295563954 26995 127.0.0.1 (20 Jan 2011 22:52:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 20 Jan 2011 22:52:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v12g2000vbx.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4604 On Jan 20, 2:33=A0pm, Jonathan Bromley wrote: > On Thu, 20 Jan 2011 09:02:47 -0800 (PST), rickman wrote: > >The title is self explanatory. =A0When found that Verilog lets you use a > >* in the sensitivity list of a combinatorial process. =A0Why doesn't > >VHDL have that? =A0There doesn't seem to be a down side that I can think > >of. =A0Didn't they just finalize changes to VHDL in 2008? =A0Isn't seven > >years enough time to pick up on a useful feature like this? > > heh. As others have said, "process(all)" is in > VHDL-2008 and it's just a matter of waiting for > Your Favourite Tool (TM) to support it. > > However, don't believe everything you read in the > headlines. =A0You do know about the flaws in > Verilog @*, don't you? :-) > -- > Jonathan Bromley In my experience the "flaws" of Verilog @* don't show up under typical design conditions. For example when implementing a memory, I understand that the block won't fire in simulation just because the currently addressed cell of memory changes, however most of the time I'm using non-clocked memory I only expect the value to change due to a change in the address, i.e. I don't write the memory cell while reading the same cell. For a large combinatorial process, the likelihood of forgetting an item in the sensitivity list becomes more of a "flaw" than the little quirks of @*. Obviously you can look through the warnings and complete the list recursively, assuming you synthesize the code before you're done debugging it in behavioral simulation where leaving out an item is not considered worthy of a warning. Just my 2 cents, Gabor From newsfish@newsfish Fri Feb 3 13:10:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Thu, 20 Jan 2011 23:33:24 +0000 Organization: A noiseless patient Spider Lines: 40 Message-ID: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="25001"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX182BoyQ3xPNNyKwLyUsr3RbcJ1vPrp9l2E=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:fJ0LfJEzBIuevSzcFORy/8cs0+E= Xref: feeder.eternal-september.org comp.lang.vhdl:4605 On Thu, 20 Jan 2011 14:52:34 -0800 (PST), Gabor Sz wrote: >In my experience the "flaws" of Verilog @* don't show up under >typical design conditions. For example when implementing a >memory, I understand that the block won't fire in simulation >just because the currently addressed cell of memory changes, >however most of the time I'm using non-clocked memory I only >expect the value to change due to a change in the address, >i.e. I don't write the memory cell while reading the same >cell. For a large combinatorial process, the likelihood of >forgetting an item in the sensitivity list becomes more of >a "flaw" than the little quirks of @*. Obviously you can >look through the warnings and complete the list recursively, >assuming you synthesize the code before you're done debugging >it in behavioral simulation where leaving out an item is >not considered worthy of a warning. Sure, there's no doubt @* is a big win. always_comb (the pumped-up SystemVerilog version of always@*) fixes the array sensitivity problem, and also the issue about sensitivity to free variables that are read by called functions. That problem with @* is, I reckon, at least as dangerous as array (in)sensitivity. Good point about using your synthesis tool to flush out any problems, though. And of course a good linting or formal checking tool would tell you the same things. On a purely practical note, it's worth remembering that continuous assign *is* sensitive to everything it needs, including arrays. So it's probably a better choice than always@* for modelling the "read" side of an asynchronous memory. cheers -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e4g2000vbg.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Thu, 20 Jan 2011 23:37:50 -0800 (PST) Organization: http://groups.google.com Lines: 61 Message-ID: <1a12d508-aa5a-43d2-a9b1-e7226a3bdb46@e4g2000vbg.googlegroups.com> References: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295595470 31202 127.0.0.1 (21 Jan 2011 07:37:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 07:37:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e4g2000vbg.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4606 On 21 Jan., 00:33, Jonathan Bromley wrote: > On Thu, 20 Jan 2011 14:52:34 -0800 (PST), Gabor Sz wrote: > >In my experience the "flaws" of Verilog @* don't show up under > >typical design conditions. =A0For example when implementing a > >memory, I understand that the block won't fire in simulation > >just because the currently addressed cell of memory changes, > >however most of the time I'm using non-clocked memory I only > >expect the value to change due to a change in the address, > >i.e. I don't write the memory cell while reading the same > >cell. =A0For a large combinatorial process, the likelihood of > >forgetting an item in the sensitivity list becomes more of > >a "flaw" than the little quirks of @*. =A0Obviously you can > >look through the warnings and complete the list recursively, > >assuming you synthesize the code before you're done debugging > >it in behavioral simulation where leaving out an item is > >not considered worthy of a warning. > > Sure, there's no doubt @* is a big win. > > always_comb (the pumped-up SystemVerilog version > of always@*) fixes the array sensitivity problem, > and also the issue about sensitivity to free > variables that are read by called functions. =A0 > That problem with @* is, I reckon, at least as > dangerous as array (in)sensitivity. > > Good point about using your synthesis tool to > flush out any problems, though. =A0And of course a > good linting or formal checking tool would tell > you the same things. > > On a purely practical note, it's worth remembering > that continuous assign *is* sensitive to everything > it needs, including arrays. =A0So it's probably a > better choice than always@* for modelling the > "read" side of an asynchronous memory. > > cheers > -- > Jonathan Bromley Hi everybody if you want to implement the all keyword in your favorite synthesis tool, you can do it like this: signal all : std_logic ; Now you can use process(all) in your non-VHDL2008 synthesis tool, and it won't throw errors. (Maybe warnings, but these can be filtered out) Maybe you can put this declaration in a global package that you use for synthesis only, to avoid conflicts with a VHDL2008 compatible simulator. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:10:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe14.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Lines: 32 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Response Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe14.ams2 1295599832 213.105.6.183 (Fri, 21 Jan 2011 08:50:32 UTC) NNTP-Posting-Date: Fri, 21 Jan 2011 08:50:32 UTC Organization: virginmedia.com Date: Fri, 21 Jan 2011 08:48:29 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4607 "HT-Lab" wrote in message news:X2_Zo.3326$S16.1073@newsfe20.ams2... > > "Rob Gaddi" wrote in message > news:s82dnYG3SLRV9qXQnZ2dnUVZ_vudnZ2d@lmi.net... >> On 1/20/2011 9:02 AM, rickman wrote: >>> The title is self explanatory. When found that Verilog lets you use a >>> * in the sensitivity list of a combinatorial process. Why doesn't >>> VHDL have that? There doesn't seem to be a down side that I can think >>> of. Didn't they just finalize changes to VHDL in 2008? Isn't seven >>> years enough time to pick up on a useful feature like this? >>> >>> Rick >> >> Someone correct me if I'm wrong, but I think VHDL2008 allows for 'all' as a >> sensitivity list. > > Yes process(all) works fine in Modelsim 10.0 and ActiveHDL/Riviera, not sure > about ncsim, isim etc. > >> >> Now, that said, just TRY to find a synthesis tool that supports it. > > Precision and Synplify and I believe QNS (not 100% sure), QNS (Quartus 10.1) supports it as well, XST(ISE 12.3) does not. Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:10:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!fm22g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 07:17:03 -0800 (PST) Organization: http://groups.google.com Lines: 66 Message-ID: References: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> <1a12d508-aa5a-43d2-a9b1-e7226a3bdb46@e4g2000vbg.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295623023 19291 127.0.0.1 (21 Jan 2011 15:17:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 15:17:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fm22g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4608 On Jan 21, 2:37=A0am, backhus wrote: > On 21 Jan., 00:33, Jonathan Bromley > wrote: > > > > > On Thu, 20 Jan 2011 14:52:34 -0800 (PST), Gabor Sz wrote: > > >In my experience the "flaws" of Verilog @* don't show up under > > >typical design conditions. =A0For example when implementing a > > >memory, I understand that the block won't fire in simulation > > >just because the currently addressed cell of memory changes, > > >however most of the time I'm using non-clocked memory I only > > >expect the value to change due to a change in the address, > > >i.e. I don't write the memory cell while reading the same > > >cell. =A0For a large combinatorial process, the likelihood of > > >forgetting an item in the sensitivity list becomes more of > > >a "flaw" than the little quirks of @*. =A0Obviously you can > > >look through the warnings and complete the list recursively, > > >assuming you synthesize the code before you're done debugging > > >it in behavioral simulation where leaving out an item is > > >not considered worthy of a warning. > > > Sure, there's no doubt @* is a big win. > > > always_comb (the pumped-up SystemVerilog version > > of always@*) fixes the array sensitivity problem, > > and also the issue about sensitivity to free > > variables that are read by called functions. =A0 > > That problem with @* is, I reckon, at least as > > dangerous as array (in)sensitivity. > > > Good point about using your synthesis tool to > > flush out any problems, though. =A0And of course a > > good linting or formal checking tool would tell > > you the same things. > > > On a purely practical note, it's worth remembering > > that continuous assign *is* sensitive to everything > > it needs, including arrays. =A0So it's probably a > > better choice than always@* for modelling the > > "read" side of an asynchronous memory. > > > cheers > > -- > > Jonathan Bromley > > Hi everybody > if you want to implement the all keyword in your favorite synthesis > tool, you can do it like this: > > signal all : std_logic ; > > Now you can use > > process(all) > > in your non-VHDL2008 synthesis tool, and it won't throw errors. (Maybe > warnings, but these can be filtered out) > > Maybe you can put this declaration in a global package that you use > for synthesis only, to avoid conflicts with a VHDL2008 compatible > simulator. You lost me somewhere. How will this work at all in simulation? Rick From newsfish@newsfish Fri Feb 3 13:10:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!b25g2000vbz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Fri, 21 Jan 2011 07:30:34 -0800 (PST) Organization: http://groups.google.com Lines: 37 Message-ID: References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> <7d893a46-ee5c-48ea-8826-fd85ea9117e7@f35g2000vbl.googlegroups.com> <454c7769-8730-4e7d-8633-9a0a05822cc9@t8g2000prh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295623834 26681 127.0.0.1 (21 Jan 2011 15:30:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 15:30:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b25g2000vbz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4609 On Jan 20, 2:37=A0pm, Andy wrote: > > You misunderstand. =A0No changes in clock will trigger the process othe= r > > than the rising edge, but any transition of the reset=3D1 expression > > will trigger execution of the process. =A0Any transition that does not > > result in reset=3D'1' being true will be handled by the else clause and > > treated as if it were a rising edge of the clock signal. =A0Try it > > yourself in simulation. =A0If you have the D input high at the time the > > reset signal goes low, the Q output will be set high as if it had been > > clocked! > > No it won't! The outer "if rising_edge(clock) or reset =3D '1' then" > statement will prevent any assignment if rising_edge() is false and > reset is '0'. > > Don't confuse "triggering a process," and "executing code within that > process" Any event on any signal in the sensitivity list will "trigger > the process," and start execution of the first executable statement. > Whether other code within that process gets executed is dependent upon > BOTH the process being triggered, AND any surrounding conditional > statements. > > Andy You are absolutely right. Somehow as many times as I read this, I saw the first IF statement as a process statement. But I have no idea why anyone would write code that way. The fact that code is logically correct (meaning it should simulate ok) does not mean it will synthesize. I think that is the purpose of IEEE 1076.6-2004, to explain the subset of VHDL that will give you what you want in synthesis. The tool vendors can't create reasonable hardware from every combination of code that will simulate in the same manner. They have to pick code templates that they can recognize and match to hardware. Rick From newsfish@newsfish Fri Feb 3 13:10:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!m7g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Fri, 21 Jan 2011 07:36:16 -0800 (PST) Organization: http://groups.google.com Lines: 138 Message-ID: <58c2e60c-fcfd-4117-b119-94b0c3431bc8@m7g2000vbn.googlegroups.com> References: <28a3d42d-a33d-457b-a5ad-071a9e8235ab@y31g2000vbt.googlegroups.com> <7d893a46-ee5c-48ea-8826-fd85ea9117e7@f35g2000vbl.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295624176 29391 127.0.0.1 (21 Jan 2011 15:36:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 15:36:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4610 On Jan 20, 1:13=A0pm, "Guenter.Bart...@googlemail.com" wrote: > Rick, > > On Jan 20, 11:36=A0am, rickman wrote: > > > > > > > > if rising_edge(clock) or reset =3D '1' then > > > > > =A0 if reset =3D '1' then > > > > > =A0 =A0 Q <=3D '0' ; -- assignment 1 > > > > > =A0 else > > > > > =A0 =A0 Q <=3D D; -- assignment 2 > > > > > =A0 end if; > > > > > end if; > > > > > As Eilert says, you need the risingedge test in the IF statement fo= r > > > > this to be valid. =A0Why? =A0Because the sensitivity list is not th= e same > > > > as a condition test. =A0The values in the sensitivity list do not n= eed > > > > to be true for the process to run, there only needs to be a change = in > > > > the items in the list for the process to run. =A0So your logical > > > > analysis above is flawed. > > > > actually the outer if-statement does have the risingedge test, so tha= t > > > is not the point :o) > > > You misunderstand. =A0No changes in clock will trigger the process othe= r > > than the rising edge, but any transition of the reset=3D1 expression > > will trigger execution of the process. =A0Any transition that does not > > result in reset=3D'1' being true will be handled by the else clause and > > treated as if it were a rising edge of the clock signal. =A0Try it > > yourself in simulation. =A0If you have the D input high at the time the > > reset signal goes low, the Q output will be set high as if it had been > > clocked! > > tried it in ghdl and q stays '0', just as i expected. here is the test > program i tried: > > use std.textio.all; > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned."+"; > use IEEE.std_logic_unsigned."-"; > > entity dir_test is > > end dir_test; > > architecture behaviour of dir_test is > > signal clock, reset, d, q : std_logic; > > begin > > =A0 process (clock, reset, d) > > =A0 begin > > =A0 =A0 if rising_edge(clock) or reset =3D '1' then > =A0 =A0 =A0 if reset =3D '1' then > =A0 =A0 =A0 =A0 Q <=3D '0' ; -- assignment 1 > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 Q <=3D D; -- assignment 2 > =A0 =A0 =A0 end if; > =A0 =A0 end if; > > =A0 end process; > > =A0 tb: process > > =A0 =A0 function to_string (value : STD_LOGIC) return STRING is > =A0 =A0 begin > =A0 =A0 =A0 if value =3D '1' then > =A0 =A0 =A0 =A0 return "1"; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 return "0"; > =A0 =A0 =A0 end if; > =A0 =A0 end function to_string; > > =A0 =A0 variable l =A0: line; > > =A0 begin > > =A0 =A0 clock <=3D '0'; reset <=3D '0'; d <=3D '1'; > > =A0 =A0 wait for 10 ns; > > =A0 =A0 write (l, "clock: " & to_string(clock) & ", reset: " & > to_string(reset) & ", q: " & to_string(q)); > =A0 =A0 writeline (output, l); > > =A0 =A0 clock <=3D '0'; reset <=3D '1'; d <=3D '1'; > > =A0 =A0 wait for 10 ns; > > =A0 =A0 write (l, "clock: " & to_string(clock) & ", reset: " & > to_string(reset) & ", q: " & to_string(q)); > =A0 =A0 writeline (output, l); > > =A0 =A0 clock <=3D '0'; reset <=3D '0'; d <=3D '1'; > > =A0 =A0 wait for 10 ns; > > =A0 =A0 write (l, "clock: " & to_string(clock) & ", reset: " & > to_string(reset) & ", q: " & to_string(q)); > =A0 =A0 writeline (output, l); > > =A0 =A0 wait; > > =A0 end process; > > end behaviour; > > output I get: > > clock: 0, reset: 0, q: 0 > clock: 0, reset: 1, q: 0 > clock: 0, reset: 0, q: 0 > > best regards, > > =A0 =A0guenter I was misreading the code in your original post. I thought the first IF was a process statement... I've been using the same template too long I guess, I'm starting to see it whether it's there or not. So this code should simulate the same as a D FF with async reset. But what does that have to do with synthesis? See my reply to Andy. Rick From newsfish@newsfish Fri Feb 3 13:10:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!goblin1!goblin3!goblin.stu.neva.ru!news.netfront.net!not-for-mail From: Walter Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 14:17:19 -0200 Organization: W Software & FPGA Services Lines: 9 Message-ID: References: NNTP-Posting-Host: 189.121.103.134 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: adenine.netfront.net 1295626643 94683 189.121.103.134 (21 Jan 2011 16:17:23 GMT) X-Complaints-To: news@netfront.net NNTP-Posting-Date: Fri, 21 Jan 2011 16:17:23 +0000 (UTC) User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; es-ES; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4611 VHDL is a reasonably safe hardware description language; why we insist on make holes over the bridge ? Walter --- news://freenews.netfront.net/ - complaints: news@netfront.net --- From newsfish@newsfish Fri Feb 3 13:10:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeder.news-service.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 08:38:10 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: References: NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295627890 30590 127.0.0.1 (21 Jan 2011 16:38:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 16:38:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4612 On Jan 21, 8:17=A0am, Walter wrote: > VHDL is a reasonably safe hardware description language; why we insist > on make holes over the bridge ? > > Walter > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- I thought that I was the only one who thought that. Why would one want to make it harder to spot mistakes? I have spent many hours debugging code where shortcuts had allowed "bad things" to go undetected. For my time and energy, it's less work to do it the old way than to manually sift through the code. RK From newsfish@newsfish Fri Feb 3 13:10:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!fx12g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 09:25:31 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295630732 23994 127.0.0.1 (21 Jan 2011 17:25:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 17:25:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fx12g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4613 On Jan 21, 11:17=A0am, Walter wrote: > VHDL is a reasonably safe hardware description language; why we insist > on make holes over the bridge ? > > Walter > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- How is the "all" keyword a hole? VHDL may be "safe", but so are four point harnesses and full helmets. You don't see them used in standard automobiles, instead we opt for a tradeoff between safety and convenience. Forgetting a signal in the sensitivity list of a combinatorial process (such as a complex case statement) is not an uncommon mistake. I believe the tools will give you warnings about this, but why bother with all that when you can just say "use all input signals in the sensitivity list... stupid" to the tools? Where is the danger? Rick From newsfish@newsfish Fri Feb 3 13:10:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f2g2000vby.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 09:26:23 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <3b8aef18-eee3-4353-9ad5-66e6ff182e59@f2g2000vby.googlegroups.com> References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295630785 7007 127.0.0.1 (21 Jan 2011 17:26:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 17:26:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f2g2000vby.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4614 On Jan 21, 11:38=A0am, d_s_klein wrote: > On Jan 21, 8:17=A0am, Walter wrote: > > > VHDL is a reasonably safe hardware description language; why we insist > > on make holes over the bridge ? > > > Walter > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- > > I thought that I was the only one who thought that. > > Why would one want to make it harder to spot mistakes? > > I have spent many hours debugging code where shortcuts had allowed > "bad things" to go undetected. =A0For my time and energy, it's less work > to do it the old way than to manually sift through the code. I'm not following. How would using the "all" keyword in a sensitivity list hide a mistake? Rick From newsfish@newsfish Fri Feb 3 13:10:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 21 Jan 2011 11:28:15 -0600 Date: Fri, 21 Jan 2011 09:28:16 -0800 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 33 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-2axk3VQfzpeAWyb4tKJ5sKi2992lE748t7j/coeyEpRIYOYzGimRXoFZzayY4IJYnATg/ddcUE3ntjA!8Ge71cxx6FBrt/5+xNBxK/kfuxtmANjrSZAIKk+NYKYyreTGDmB22aOd5tT5NpO/xnZV773MzTy7!Ug== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2630 Xref: feeder.eternal-september.org comp.lang.vhdl:4615 On 1/21/2011 8:38 AM, d_s_klein wrote: > On Jan 21, 8:17 am, Walter wrote: >> VHDL is a reasonably safe hardware description language; why we insist >> on make holes over the bridge ? >> >> Walter >> >> --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- > > I thought that I was the only one who thought that. > > Why would one want to make it harder to spot mistakes? > > I have spent many hours debugging code where shortcuts had allowed > "bad things" to go undetected. For my time and energy, it's less work > to do it the old way than to manually sift through the code. > > RK Whereas I find the sensitivity lists on large combinational processes to be one of the serious banes of my VHDL existence. I've lost untold hours to trying to figure out why one input to, for instance, a 16:1 mux with multi-part enable, wasn't getting updated properly, only to find that I had forgotten it in the 17+ element long sensitivity list. In order to get around it I've had to add unnecessary registers to my outputs just so as to be able to use only the clock in the SL, or try to write the entire thing outside of a process, leading to some serious verbage nightmares. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:10:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c13g2000prc.googlegroups.com!not-for-mail From: d_s_klein Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 11:37:11 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: References: <3b8aef18-eee3-4353-9ad5-66e6ff182e59@f2g2000vby.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295638631 29853 127.0.0.1 (21 Jan 2011 19:37:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 19:37:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c13g2000prc.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4616 On Jan 21, 9:26=A0am, rickman wrote: > On Jan 21, 11:38=A0am, d_s_klein wrote: > > > > > On Jan 21, 8:17=A0am, Walter wrote: > > > > VHDL is a reasonably safe hardware description language; why we insis= t > > > on make holes over the bridge ? > > > > Walter > > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- > > > I thought that I was the only one who thought that. > > > Why would one want to make it harder to spot mistakes? > > > I have spent many hours debugging code where shortcuts had allowed > > "bad things" to go undetected. =A0For my time and energy, it's less wor= k > > to do it the old way than to manually sift through the code. > > I'm not following. =A0How would using the "all" keyword in a sensitivity > list hide a mistake? > > Rick You said: "I believe the tools will give you warnings about this" IME, this is not a true statement. RK From newsfish@newsfish Fri Feb 3 13:10:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.85.MISMATCH!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Fri, 21 Jan 2011 21:27:57 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: <3b8aef18-eee3-4353-9ad5-66e6ff182e59@f2g2000vby.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 38 Message-ID: <4d39ec4c$0$14249$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 70e61b30.news.skynet.be X-Trace: 1295641676 news.skynet.be 14249 91.177.214.50:59206 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4617 d_s_klein wrote: > On Jan 21, 9:26 am, rickman wrote: >> On Jan 21, 11:38 am, d_s_klein wrote: >> >> >> >>> On Jan 21, 8:17 am, Walter wrote: >>>> VHDL is a reasonably safe hardware description language; why we insist >>>> on make holes over the bridge ? >>>> Walter >>>> --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- >>> I thought that I was the only one who thought that. >>> Why would one want to make it harder to spot mistakes? >>> I have spent many hours debugging code where shortcuts had allowed >>> "bad things" to go undetected. For my time and energy, it's less work >>> to do it the old way than to manually sift through the code. >> I'm not following. How would using the "all" keyword in a sensitivity >> list hide a mistake? >> >> Rick > > You said: "I believe the tools will give you warnings about this" > > IME, this is not a true statement. Are you sure you understand what "all" in a sensitivity list does? I detect some major misunderstandings in this conversation. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:10:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.datemas.de!weretis.net!feeder4.news.weretis.net!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!m13g2000yqb.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 13:15:07 -0800 (PST) Organization: http://groups.google.com Lines: 76 Message-ID: <5475f117-821e-4284-8523-bb25d41013b0@m13g2000yqb.googlegroups.com> References: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> <1a12d508-aa5a-43d2-a9b1-e7226a3bdb46@e4g2000vbg.googlegroups.com> NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295644508 17863 127.0.0.1 (21 Jan 2011 21:15:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 21:15:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m13g2000yqb.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4618 On Jan 21, 10:17=A0am, rickman wrote: > On Jan 21, 2:37=A0am, backhus wrote: > > > > > On 21 Jan., 00:33, Jonathan Bromley > > wrote: > > > > On Thu, 20 Jan 2011 14:52:34 -0800 (PST), Gabor Sz wrote: > > > >In my experience the "flaws" of Verilog @* don't show up under > > > >typical design conditions. =A0For example when implementing a > > > >memory, I understand that the block won't fire in simulation > > > >just because the currently addressed cell of memory changes, > > > >however most of the time I'm using non-clocked memory I only > > > >expect the value to change due to a change in the address, > > > >i.e. I don't write the memory cell while reading the same > > > >cell. =A0For a large combinatorial process, the likelihood of > > > >forgetting an item in the sensitivity list becomes more of > > > >a "flaw" than the little quirks of @*. =A0Obviously you can > > > >look through the warnings and complete the list recursively, > > > >assuming you synthesize the code before you're done debugging > > > >it in behavioral simulation where leaving out an item is > > > >not considered worthy of a warning. > > > > Sure, there's no doubt @* is a big win. > > > > always_comb (the pumped-up SystemVerilog version > > > of always@*) fixes the array sensitivity problem, > > > and also the issue about sensitivity to free > > > variables that are read by called functions. =A0 > > > That problem with @* is, I reckon, at least as > > > dangerous as array (in)sensitivity. > > > > Good point about using your synthesis tool to > > > flush out any problems, though. =A0And of course a > > > good linting or formal checking tool would tell > > > you the same things. > > > > On a purely practical note, it's worth remembering > > > that continuous assign *is* sensitive to everything > > > it needs, including arrays. =A0So it's probably a > > > better choice than always@* for modelling the > > > "read" side of an asynchronous memory. > > > > cheers > > > -- > > > Jonathan Bromley > > > Hi everybody > > if you want to implement the all keyword in your favorite synthesis > > tool, you can do it like this: > > > signal all : std_logic ; > > > Now you can use > > > process(all) > > > in your non-VHDL2008 synthesis tool, and it won't throw errors. (Maybe > > warnings, but these can be filtered out) > > > Maybe you can put this declaration in a global package that you use > > for synthesis only, to avoid conflicts with a VHDL2008 compatible > > simulator. > > You lost me somewhere. =A0How will this work at all in simulation? > > Rick It won't. The idea is to allow you to build the design in synthesis without errors. It presumes that your simulator does support the "all" directive. In synthesis, the sensitivity list is ignored anyway. I imagine you'd need to make sure that the declaration for signal "all" does not show up in the code for simulation. -- Gabor From newsfish@newsfish Fri Feb 3 13:10:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!15g2000vbz.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 13:22:27 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295644947 3507 127.0.0.1 (21 Jan 2011 21:22:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 21:22:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 15g2000vbz.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4619 On Jan 21, 12:25=A0pm, rickman wrote: > On Jan 21, 11:17=A0am, Walter wrote: > > > VHDL is a reasonably safe hardware description language; why we insist > > on make holes over the bridge ? > > > Walter > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- > > How is the "all" keyword a hole? =A0VHDL may be "safe", but so are four > point harnesses and full helmets. =A0You don't see them used in standard > automobiles, instead we opt for a tradeoff between safety and > convenience. =A0Forgetting a signal in the sensitivity list of a > combinatorial process (such as a complex case statement) is not an > uncommon mistake. =A0I believe the tools will give you warnings about > this, but why bother with all that when you can just say "use all > input signals in the sensitivity list... stupid" to the tools? =A0Where > is the danger? > > Rick It's not clear to me that the simulator will complain about an incomplete sensitivity list. It should just blithely use the list it's given. It's the synthesizer that pops up the warnings about not matching simulation when your list is not complete. For those who do most of their design work with simulation and then try to pop off a synthesis at the end of "getting it right" in simulation, this is a bit late to find out that your design will not do what you described to the simulator. In this respect the "all" keyword actually helps prevent problems. A major issue I have with only seeing a warning during synthesis and not simulation, is that the synthesis process is usually rife with warnings that can be safely ignored. This means I'm more likely to miss the useful ones, like "incomplete sensitivity list" if I don't also get the same warning during simulation, where generally speaking all warnings should be addressed. My 2 cents, Gabor From newsfish@newsfish Fri Feb 3 13:10:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 21:28:45 +0000 Organization: A noiseless patient Spider Lines: 20 Message-ID: <7kujj612ak7vd3i08cekgk0ube5rkpra5d@4ax.com> References: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> <1a12d508-aa5a-43d2-a9b1-e7226a3bdb46@e4g2000vbg.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="24049"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/SabXZV91yQKYoIcjCUPdrTMNK1O6hbps=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:FSfN8+gAbAfWeiSax2vnmp8xc28= Xref: feeder.eternal-september.org comp.lang.vhdl:4620 On Thu, 20 Jan 2011 23:37:50 -0800 (PST), backhus wrote: >if you want to implement the all keyword in your favorite synthesis >tool, you can do it like this: > >signal all : std_logic ; > >Now you can use > >process(all) > >in your non-VHDL2008 synthesis tool, and it won't throw errors. I fear not. 'all' is already a reserved word in every version of the VHDL standard that I know of. (Think of "use ieee.std_logic_1164.all;") Cute idea, though. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t35g2000yqj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 13:58:58 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295647138 23351 127.0.0.1 (21 Jan 2011 21:58:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Jan 2011 21:58:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t35g2000yqj.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4621 On Jan 21, 12:28=A0pm, Rob Gaddi wrote: > > In order to get around it I've had to add unnecessary registers to my > outputs just so as to be able to use only the clock in the SL, or try to > write the entire thing outside of a process, leading to some serious > verbage nightmares. > Consider using a function (for one output, or a procedure for multiple outputs) instead. Then the only extra baggage is that of instantianting the function/procedure call. The code you would've written in the process simply moves to the function/procedure. If you forget some input, the compiler complains. KJ From newsfish@newsfish Fri Feb 3 13:10:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Newsgroups: comp.lang.vhdl Date: Fri, 21 Jan 2011 23:45:12 +0100 References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 36 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295649913 news.xs4all.nl 41103 puiterl/[::ffff:195.242.97.150]:55091 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4622 Gabor Sz wrote: > It's not clear to me that the simulator will complain about an > incomplete sensitivity list. It should just blithely use the > list it's given. It's the synthesizer that pops up the warnings > about not matching simulation when your list is not complete. > For those who do most of their design work with simulation and > then try to pop off a synthesis at the end of "getting it right" > in simulation, this is a bit late to find out that your design > will not do what you described to the simulator. In this > respect the "all" keyword actually helps prevent problems. > A major issue I have with only seeing a warning during > synthesis and not simulation, is that the synthesis process > is usually rife with warnings that can be safely ignored. > This means I'm more likely to miss the useful ones, like > "incomplete sensitivity list" if I don't also get the > same warning during simulation, where generally speaking > all warnings should be addressed. I fully agree with what you say. Especially when you say that finding out only at synthesis time about incomplete process sensitivity lists is too late (*if* you find it at all in the flood of warnings a synthesizer usually spews out). That brings me to my 2 euro cents: 1) use a linting tool to catch errors like this in an early stage 2) avoid long sensitivity lists in the first place (as KJ also said) 3) why do synthesis tools spit out so many warnings? 4) synthesis tools should have a setting to make the "incomplete sensitivity list" warning a fatal -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!eweka.nl!lightspeed.eweka.nl!82.197.223.108.MISMATCH!feeder2.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 22 Jan 2011 02:03:39 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> In-Reply-To: <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 54 Message-ID: <4d3a2ce9$0$14255$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 9a06f1af.news.skynet.be X-Trace: 1295658217 news.skynet.be 14255 91.177.214.50:44097 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4623 Paul Uiterlinden wrote: > Gabor Sz wrote: > >> It's not clear to me that the simulator will complain about an >> incomplete sensitivity list. It should just blithely use the >> list it's given. It's the synthesizer that pops up the warnings >> about not matching simulation when your list is not complete. >> For those who do most of their design work with simulation and >> then try to pop off a synthesis at the end of "getting it right" >> in simulation, this is a bit late to find out that your design >> will not do what you described to the simulator. In this >> respect the "all" keyword actually helps prevent problems. >> A major issue I have with only seeing a warning during >> synthesis and not simulation, is that the synthesis process >> is usually rife with warnings that can be safely ignored. >> This means I'm more likely to miss the useful ones, like >> "incomplete sensitivity list" if I don't also get the >> same warning during simulation, where generally speaking >> all warnings should be addressed. > > I fully agree with what you say. Especially when you say that finding out > only at synthesis time about incomplete process sensitivity lists is too > late (*if* you find it at all in the flood of warnings a synthesizer > usually spews out). > > That brings me to my 2 euro cents: > > 1) use a linting tool to catch errors like this in an early stage ... or even better: an IDE that flags and offers a quick fix for them as you are developing (like Sigasi HDT). > 2) avoid long sensitivity lists in the first place (as KJ also said) Yes. > 3) why do synthesis tools spit out so many warnings? > 4) synthesis tools should have a setting to make the "incomplete > sensitivity list" warning a fatal Fully agree. To me, this shouldn't even be optional. There is no way how synthesis can match simulation in such a case, so such code should be treated as non-synthesizable. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:10:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v26g2000yqf.googlegroups.com!not-for-mail From: "evilkidder@googlemail.com" Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Fri, 21 Jan 2011 18:20:15 -0800 (PST) Organization: http://groups.google.com Lines: 14 Message-ID: References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> <4d3a2ce9$0$14255$ba620e4c@news.skynet.be> NNTP-Posting-Host: 86.25.220.231 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295662815 608 127.0.0.1 (22 Jan 2011 02:20:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 02:20:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v26g2000yqf.googlegroups.com; posting-host=86.25.220.231; posting-account=HqbchAkAAAC-Jv0afbWZ8S8Oga-m3wGi User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-GB; rv:1.9.2.8) Gecko/20100723 Ubuntu/10.04 (lucid) Firefox/3.6.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4624 Why are we going over the same problems again and again rather than producing a new language? I've just snipped a massive rant about VHDL and Verilog I was about to post ... rather I wonder if anyone feels the same way, and if so what they think would improve things. Or indeed if they don't need improving. FWIW my view is hardware is just a cyclic graph and if you have good enough tools to manipulate that graph you don't need HDL's. -Andy From newsfish@newsfish Fri Feb 3 13:10:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i22g2000prd.googlegroups.com!not-for-mail From: shilla Newsgroups: comp.lang.vhdl Subject: Become The master in computer hardware to become successfull Date: Fri, 21 Jan 2011 20:45:43 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <513b76fb-39c6-4284-8948-f81c1e3e1f9b@i22g2000prd.googlegroups.com> NNTP-Posting-Host: 202.177.247.71 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295671543 13437 127.0.0.1 (22 Jan 2011 04:45:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 04:45:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i22g2000prd.googlegroups.com; posting-host=202.177.247.71; posting-account=zZMXuQoAAACVFGw6UdwqtYuolb__VPYh User-Agent: G2/1.0 X-HTTP-Via: 1.1 fivenet4.netsolutioninc.com:8103 (squid/2.7.STABLE9) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4625 Making the decision to attend a computer tech school can be one of the best decisions of your life. Another great decision is to tap a hidden wealth of knowledge that is right before every student at schools such as ECPI and ITT, but very few students take advantage of it so hurry up and visit Wild Trick From newsfish@newsfish Fri Feb 3 13:10:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news2.euro.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sat, 22 Jan 2011 13:12:29 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> <4d3a2ce9$0$14255$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 Message-ID: <4d3ac9ad$0$14246$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 29bf893f.news.skynet.be X-Trace: 1295698350 news.skynet.be 14246 91.177.213.67:36457 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4626 evilkidder@googlemail.com wrote: > Why are we going over the same problems again and again rather than > producing a new language? At the heart of the matter, there is fundamental disagreement about where the problems are. > I've just snipped a massive rant about VHDL and Verilog I was about to > post ... Admirable example. Usually, I'm not very impressed with HDL rants. More often than not, they merely illustrate the ranter's lack of knowledge and experience. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:10:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w2g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 06:33:24 -0800 (PST) Organization: http://groups.google.com Lines: 55 Message-ID: <952fecd7-5f2f-4207-84fb-427dc6be7826@w2g2000yqb.googlegroups.com> References: <3b8aef18-eee3-4353-9ad5-66e6ff182e59@f2g2000vby.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295706804 1494 127.0.0.1 (22 Jan 2011 14:33:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 14:33:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w2g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4627 On Jan 21, 2:37=A0pm, d_s_klein wrote: > On Jan 21, 9:26=A0am, rickman wrote: > > > On Jan 21, 11:38=A0am, d_s_klein wrote: > > > > On Jan 21, 8:17=A0am, Walter wrote: > > > > > VHDL is a reasonably safe hardware description language; why we ins= ist > > > > on make holes over the bridge ? > > > > > Walter > > > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net -= -- > > > > I thought that I was the only one who thought that. > > > > Why would one want to make it harder to spot mistakes? > > > > I have spent many hours debugging code where shortcuts had allowed > > > "bad things" to go undetected. =A0For my time and energy, it's less w= ork > > > to do it the old way than to manually sift through the code. > > > I'm not following. =A0How would using the "all" keyword in a sensitivit= y > > list hide a mistake? > > > Rick > > You said: "I believe the tools will give you warnings about this" > > IME, this is not a true statement. I'm afraid I don't understand what you are talking about. The context is lost and you are quoting me from somewhere other than the line of messages. So I have no way of knowing what "this" refers to. My original post was: > The title is self explanatory. When found that Verilog lets you use a > * in the sensitivity list of a combinatorial process. Why doesn't > VHDL have that? There doesn't seem to be a down side that I can think > of. Didn't they just finalize changes to VHDL in 2008? Isn't seven > years enough time to pick up on a useful feature like this? Walter replied to that and you replied to Walter, which is all quoted above. Please explain how using "all" as a wildcard in the sensitivity list would hide mistakes... Rick From newsfish@newsfish Fri Feb 3 13:10:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!32g2000yqz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 06:35:55 -0800 (PST) Organization: http://groups.google.com Lines: 24 Message-ID: References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295706955 22996 127.0.0.1 (22 Jan 2011 14:35:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 14:35:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 32g2000yqz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4628 On Jan 21, 4:58=A0pm, KJ wrote: > On Jan 21, 12:28=A0pm, Rob Gaddi wrote: > > > > > In order to get around it I've had to add unnecessary registers to my > > outputs just so as to be able to use only the clock in the SL, or try t= o > > write the entire thing outside of a process, leading to some serious > > verbage nightmares. > > Consider using a function (for one output, or a procedure for multiple > outputs) instead. =A0Then the only extra baggage is that of > instantianting the function/procedure call. =A0The code you would've > written in the process simply moves to the function/procedure. =A0If you > forget some input, the compiler complains. > > KJ Are you sure about that? If you use a function/procedure in a process and don't include one of the inputs to that function/procedure in the sensitivity list, the compiler complains? How is this reported? Rick From newsfish@newsfish Fri Feb 3 13:10:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u6g2000yqk.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 06:50:39 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295707839 11374 127.0.0.1 (22 Jan 2011 14:50:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 14:50:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u6g2000yqk.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4629 On Jan 21, 4:22 pm, Gabor Sz wrote: > On Jan 21, 12:25 pm, rickman wrote: > > > On Jan 21, 11:17 am, Walter wrote: > > > > VHDL is a reasonably safe hardware description language; why we insist > > > on make holes over the bridge ? > > > > Walter > > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- > > > How is the "all" keyword a hole? VHDL may be "safe", but so are four > > point harnesses and full helmets. You don't see them used in standard > > automobiles, instead we opt for a tradeoff between safety and > > convenience. Forgetting a signal in the sensitivity list of a > > combinatorial process (such as a complex case statement) is not an > > uncommon mistake. I believe the tools will give you warnings about > > this, but why bother with all that when you can just say "use all > > input signals in the sensitivity list... stupid" to the tools? Where > > is the danger? > > > Rick > > It's not clear to me that the simulator will complain about an > incomplete sensitivity list. It should just blithely use the > list it's given. It's the synthesizer that pops up the warnings > about not matching simulation when your list is not complete. > For those who do most of their design work with simulation and > then try to pop off a synthesis at the end of "getting it right" > in simulation, this is a bit late to find out that your design > will not do what you described to the simulator. In this > respect the "all" keyword actually helps prevent problems. > A major issue I have with only seeing a warning during > synthesis and not simulation, is that the synthesis process > is usually rife with warnings that can be safely ignored. > This means I'm more likely to miss the useful ones, like > "incomplete sensitivity list" if I don't also get the > same warning during simulation, where generally speaking > all warnings should be addressed. > > My 2 cents, > Gabor I find that both tools throw many bbwarnings on my first pass of the code. Although the synthesis tool warns me of things like carry chain outputs that are not used anywhere in the code... duh, I didn't add them, the synthesis did! Still, many of the warnings are useful and need to be addressed. I have to say that I never implement a design without running it through both simulator and synthesis periodically as the design progresses. Two reasons why... 1) To find anything I'm doing that one, the other or both tools think is not a good idea. That directly applied here. 2) To check the size of the design sections. This helps me spot anything I am doing that is blowing up the size by poor implementation (most likely my bad, not the tool). 3) To check that any hardware targeted features are being implemented properly. FFs in IOs, block rams, LUT rams, etc. Yes, I know that was three and I said two. See, I needed a tool to check that for me! Rick From newsfish@newsfish Fri Feb 3 13:10:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r29g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 06:54:24 -0800 (PST) Organization: http://groups.google.com Lines: 24 Message-ID: References: <66821e39-0cb4-43d4-82df-8db16405402e@fx12g2000vbb.googlegroups.com> <8d3a4ced-dd42-47aa-a4b6-21975c300fb8@15g2000vbz.googlegroups.com> <4d3a0c79$0$41103$e4fe514c@news.xs4all.nl> <4d3a2ce9$0$14255$ba620e4c@news.skynet.be> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295708064 460 127.0.0.1 (22 Jan 2011 14:54:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 14:54:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r29g2000yqj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4630 On Jan 21, 9:20 pm, "evilkid...@googlemail.com" wrote: > Why are we going over the same problems again and again rather than > producing a new language? > > I've just snipped a massive rant about VHDL and Verilog I was about to > post ... rather I wonder if anyone feels the same way, and if so what > they think would improve things. Or indeed if they don't need > improving. > > FWIW my view is hardware is just a cyclic graph and if you have good > enough tools to manipulate that graph you don't need HDL's. > > -Andy I agree that HDLs are not even close to ideal. But they seem to be better than the schematics we had before and the best we currently have. Also, there is the issue of "good enough". I like to get work done. Sometimes HDLs get in the way of that, but in many ways they are a great facilitator. I'm not ready to toss out the baby with the bath water. Rick From newsfish@newsfish Fri Feb 3 13:10:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!k42g2000yqa.googlegroups.com!not-for-mail From: jr kv Newsgroups: comp.lang.vhdl Subject: Top Social Networking Sites in India Date: Sat, 22 Jan 2011 08:26:11 -0800 (PST) Organization: http://groups.google.com Lines: 1 Message-ID: NNTP-Posting-Host: 223.191.233.114 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295713571 29849 127.0.0.1 (22 Jan 2011 16:26:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 16:26:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k42g2000yqa.googlegroups.com; posting-host=223.191.233.114; posting-account=Yfz6TQoAAAC7FqKpdZyAoFn2fpBE4jZQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.15 (KHTML, like Gecko) Chrome/10.0.612.1 Safari/534.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4631 http://new-on-internet.blogspot.com/2011/01/top-social-networking-sites-in-india.html From newsfish@newsfish Fri Feb 3 13:10:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d3b08b1$0$65870$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Newsgroups: comp.lang.vhdl Date: Sat, 22 Jan 2011 17:41:21 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8Bit Lines: 59 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295714481 news.xs4all.nl 65870 puiterl/[::ffff:195.242.97.150]:48795 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4632 rickman wrote: >> Consider using a function (for one output, or a procedure for multiple >> outputs) instead.  Then the only extra baggage is that of >> instantianting the function/procedure call.  The code you would've >> written in the process simply moves to the function/procedure.  If you >> forget some input, the compiler complains. >> >> KJ > > Are you sure about that? If you use a function/procedure in a process > and don't include one of the inputs to that function/procedure in the > sensitivity list, the compiler complains? How is this reported? I think what KJ meant (correct me if I'm wrong) is using a function or procedure outside a process. That solves the sensitivity list problem: no process, hence no sensitivity list, hence no chance of an incomplete sensitivity list. With a procedure you would use a concurrent procedure call (so outside a process): my_proc_i: my_proc(sig1, sig2, sig3, sig4, sig5); The procedure declaration should look like: PROCEDURE my_proc ( SIGNAL out1 : OUT sig1_type; SIGNAL out2 : OUT sig2_type; SIGNAL in1 : IN sig3_type; SIGNAL in2 : IN sig4_type; SIGNAL in3 : IN sig5_type ) IS BEGIN ... END PROCEDURE my_proc; With a function you would use a concurrent signal assignment (again: outside a process) sig1 <= my_func(sig2, sig3, sig4); The function declaration would be something like this: FUNCTION my_func ( in1: sig1_type; in2: sig2_type; in3: sig3_type ) RETURN sig1_type IS BEGIN ... END FUNCTION my_func; -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!l7g2000vbv.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 09:03:18 -0800 (PST) Organization: http://groups.google.com Lines: 71 Message-ID: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295715798 17404 127.0.0.1 (22 Jan 2011 17:03:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 17:03:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l7g2000vbv.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4633 On Jan 22, 9:35=A0am, rickman wrote: > On Jan 21, 4:58=A0pm, KJ wrote: > > On Jan 21, 12:28=A0pm, Rob Gaddi wrote: > > > > In order to get around it I've had to add unnecessary registers to my > > > outputs just so as to be able to use only the clock in the SL, or try= to > > > write the entire thing outside of a process, leading to some serious > > > verbage nightmares. > > > Consider using a function (for one output, or a procedure for multiple > > outputs) instead. =A0Then the only extra baggage is that of > > instantianting the function/procedure call. =A0The code you would've > > written in the process simply moves to the function/procedure. =A0If yo= u > > forget some input, the compiler complains. > > > KJ > > Are you sure about that? Yes...you will get an error message of the form shown below if you don't connect something up "No feasible entries for subprogram "xyz" > =A0If you use a function/procedure in a process > and don't include one of the inputs to that function/procedure in the > sensitivity list, the compiler complains? =A0 That's not what I was suggesting. What I was suggesting is to take a process like this... architecture rtl of foo is signal a, b, c: std_logic; begin process(a, b: std_logic) begin c <=3D a or b; end process; end rtl; and replace it with a function/procedure that is defined in the architecture, and then call the function/procedure as a concurrent statement. So the code above would then look like this... architecture rtl of foo is signal a, b, c: std_logic; function my_func(a, b: std_logic) return std_logic is begin return(a or b); end process; begin c <=3D my_func(a, b); end rtl; The only extra baggage compared to using the process is the extra typing of "c <=3D my_func(a, b);". The rest of the code that was in the process simply moves to the function/procedure with some minor edits as shown. In exchange for the bit of extra typing, you get the full benefit of using 'sequential VHDL statements' like 'if', 'case', etc., in a place where you need to implement logic that is not to be clocked. The benefit is that the equivalent of missing a signal in the sensitivity list in the 'process' form will be missing an input to a function in the 'function/process' form which will result in the compiler flagging the error. Use this method where others would use a process and you can ignore all the chatter about sensitivity list maintenance. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:10:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n10g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 14:02:14 -0800 (PST) Organization: http://groups.google.com Lines: 94 Message-ID: <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295733734 15481 127.0.0.1 (22 Jan 2011 22:02:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 22 Jan 2011 22:02:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4634 On Jan 22, 12:03 pm, KJ wrote: > On Jan 22, 9:35 am, rickman wrote: > > > On Jan 21, 4:58 pm, KJ wrote: > > > > Consider using a function (for one output, or a procedure for multiple > > > outputs) instead. Then the only extra baggage is that of > > > instantianting the function/procedure call. The code you would've > > > written in the process simply moves to the function/procedure. If you > > > forget some input, the compiler complains. > > > > KJ > > > Are you sure about that? > > Yes...you will get an error message of the form shown below if you > don't connect something up > "No feasible entries for subprogram "xyz" > > > If you use a function/procedure in a process > > and don't include one of the inputs to that function/procedure in the > > sensitivity list, the compiler complains? > > That's not what I was suggesting. What I was suggesting is to take a > process like this... > architecture rtl of foo is > signal a, b, c: std_logic; > begin > process(a, b: std_logic) > begin > c <= a or b; > end process; > end rtl; > > and replace it with a function/procedure that is defined in the > architecture, and then call the function/procedure as a concurrent > statement. So the code above would then look like this... > > architecture rtl of foo is > signal a, b, c: std_logic; > function my_func(a, b: std_logic) return std_logic is > begin > return(a or b); > end process; > begin > c <= my_func(a, b); > end rtl; > > The only extra baggage compared to using the process is the extra > typing of "c <= my_func(a, b);". The rest of the code that was in the > process simply moves to the function/procedure with some minor edits > as shown. In exchange for the bit of extra typing, you get the full > benefit of using 'sequential VHDL statements' like 'if', 'case', etc., > in a place where you need to implement logic that is not to be > clocked. > > The benefit is that the equivalent of missing a signal in the > sensitivity list in the 'process' form will be missing an input to a > function in the 'function/process' form which will result in the > compiler flagging the error. > > Use this method where others would use a process and you can ignore > all the chatter about sensitivity list maintenance. > > Kevin Jennings Ok, that's a different animal. I've used functions like this, but only for simple functions with few ins and outs... well, one out to be exact... :^) Paul was saying you can use procedures like this too, I'm not aware of that. I guess the downside of this is that it can get pretty messy to describe a complex process as functions, which is pretty much what we are talking about. If it doesn't have many inputs and if they are in a single assignment, then you aren't likely to mess up the sensitivity list. I'm expecting this to apply to something like a state machine. That would have lots of inputs and outputs. Mapping that to functions would be a bit of a mess. I never realized that a procedure could be used as a concurrent statement, or maybe I've just never done it and forgot! While looking this up just now I found that the Entity declaration can contain statements including a "passive concurrent procedure call". They don't define what "passive" means in this context. Also allowed are "concurrent assertion statements" and "passive process statements". That is pretty amazing and I'm not even sure exactly what that means compared to the same statements in the architecture. When would these statements be evaluated? Anyone familiar with this? Rick From newsfish@newsfish Fri Feb 3 13:10:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w2g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sat, 22 Jan 2011 16:33:46 -0800 (PST) Organization: http://groups.google.com Lines: 126 Message-ID: <379fd0f6-3644-40a4-8c95-42a5a39c316b@w2g2000yqb.googlegroups.com> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295742826 31215 127.0.0.1 (23 Jan 2011 00:33:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 23 Jan 2011 00:33:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w2g2000yqb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4635 On Jan 22, 5:02=A0pm, rickman wrote: > On Jan 22, 12:03 pm, KJ wrote: > > On Jan 22, 9:35 am, rickman wrote: > > > Use this method where others would use a process and you can ignore > > all the chatter about sensitivity list maintenance. > > > Kevin Jennings > > Ok, that's a different animal. =A0I've used functions like this, but > only for simple functions with few ins and outs... well, one out to be > exact... :^) =A0 Paul was saying you can use procedures like this too, > I'm not aware of that. > In this case, functions are just a special case of procedures. If you have more than one output signal to describe with a particular hunk of code you have to use a procedure since you're unlimited on the number of outputs. If you *happen* to have only one output signal to generate you can choose to use either a procedure or a function. For consistency, maybe you would want to always use procedures, that would be your choice. > I guess the downside of this is that it can get pretty messy to > describe a complex process as functions, which is pretty much what we > are talking about. =A0 That's not correct. The code for the 'complex process' will look nearly identical to the code for a function (if you have only one output to generate) or a procedure (which you can use for one output or several). If you think one looks messy, the other will look just as messy. > If it doesn't have many inputs and if they are in > a single assignment, then you aren't likely to mess up the sensitivity > list. > Your original post was complaining about the lack of wildcards on sensitivity lists. Presumably that complaint was based on your use of processes with many signal inputs not processes with only a few. > I'm expecting this to apply to something like a state machine. =A0That > would have lots of inputs and outputs. =A0Mapping that to functions > would be a bit of a mess. =A0 Maybe you're missing the point that you can only use a function *if* your messy hunk of code just happens to only be generating one output. Without any extra work you could use a procedure in that case. The point is you have a choice in that one particular case. You must use a procedure if your messy hunk of code generates more than one output. The syntax for when you call the procedure will look nearly the same as when you instantiate an entity. If there are a number of I/O, then the port map will be pretty long. For the particular case of a state machine that you mention here, the far better approach is the clocked process which avoids all of this discussion. All that being said, I haven't happened to need to describe complex code in an unclocked process so I haven't needed to worry much about getting the sensitivity list correct. I do recognize the sensitivity list as a potential design issue though so I avoid using it for the most part to avoid getting bitten. The general approach is - Processes are sensitive only to clock - Concurrent statements picked up most everything else. - Occasionally, I'll use an unclocked process if there are very few inputs (like < 4). - On the rare occasions where none of the above were suitable, I would use a function or a procedure as described above. > I never realized that a procedure could be > used as a concurrent statement, or maybe I've just never done it and > forgot! > Now you've acquired two approaches to solving your original complaint. - Use the VHDL-2008 syntax with a tool that supports the updated syntax - Use a procedure (in some cases a function if you choose) > While looking this up just now I found that the Entity declaration can > contain statements including a "passive concurrent procedure call". > They don't define what "passive" means in this context. =A0Also allowed > are "concurrent assertion statements" and "passive process > statements". =A0That is pretty amazing and I'm not even sure exactly > what that means compared to the same statements in the architecture. > When would these statements be evaluated? > > Anyone familiar with this? > Practically speaking, I haven't found it to mean much compared to putting the same code in the architecture. The syntax for the assertion in an entity is entity foo is port( ...); begin assert ... report "OOPS!" severity ERROR; end foo; So you could put assertions to check that related items in the entity have the proper relationship. However, you won't get any feedback from the compiler that you've connected anything incorrectly since that check won't come until you start the simulator. When you do start sim though the assertion will fire but that is the same time that the same assertion would be checked if it had been put into the architecture. If for some reason you wanted to keep the architecture code secret but allow access to the entity then you may be motivated to put the assertions in the entity so the user would have the information they need to connect things properly. I haven't had such a need, maybe others have. Lastly, brand 'S' synthesis tool didn't used to support assertions in the entity at all. I reported the bug and I think it has been fixed. I tend to use brand 'A' tools now though and don't use brand 'S' anymore, in part due to the number of bugs I reported, the length of time it took to fix them and the obscure error message that made it next to impossible to figure out what the work around is while they work the problem. Brand 'A' supports (or at least doesn't choke on) assertions in the entity, I haven't tried with brand 'X'. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:10:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sun, 23 Jan 2011 09:23:51 -0800 Lines: 31 Message-ID: <8q36h8F919U1@mid.individual.net> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net s10EDnKynjsHNsN1TeY46QiRU2Dmrcxp9siETrbqrjNwpzmvZp Cancel-Lock: sha1:1DO5au4jY/VL2ar0Mi1WcbQaW7Q= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4636 On 1/22/2011 2:02 PM, rickman wrote: > Ok, that's a different animal. I've used functions like this, but > only for simple functions with few ins and outs... well, one out to be > exact... :^) I can use more than one. > Paul was saying you can use procedures like this too, A function returns a value. A procedure returns a block of code. A concurrent procedure returns a process. > I guess the downside of this is that it can get pretty messy to > describe a complex process as functions, which is pretty much what we > are talking about. I disagree. A function is a clean way to hide an asynchronous process and the wires and sensitivity that go with it. > I never realized that a procedure could be > used as a concurrent statement, or maybe I've just never done it and > forgot! It would be hard for me to forget that experience. I prefer using an direct instance in this case. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:10:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!m7g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sun, 23 Jan 2011 11:11:44 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295809904 4055 127.0.0.1 (23 Jan 2011 19:11:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 23 Jan 2011 19:11:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4637 On Jan 23, 12:23=A0pm, Mike Treseler wrote: > On 1/22/2011 2:02 PM, rickman wrote: > > > Ok, that's a different animal. =A0I've used functions like this, but > > only for simple functions with few ins and outs... well, one out to be > > exact... :^) > > I can use more than one. If you replace a process that assigns multiple signals with multiple functions, you are likely going to duplicate a lot of code. It is very likely that because you would use a process to begin with, the signals were not easy to describe with concurrent assignments anyway, so functions would likely be using IFs and CASEs. If the signal assignments partitioned very cleanly, then yes, functions could be ok. But it is very likely that much of the IF and CASE structure would need to be duplicated. Of course, procedures are a different matter. Then the entire process can be shoved into the procedure if you wanted. Personally, I prefer not to do this mainly because it separates relevant code so that I can't see it together in one screen. Or can you define procedures anywhere you wish in the concurrent code? I believe they have to be at the head of the architecture in the definitions. > > Paul was saying you can use procedures like this too, > > A function returns a value. > A procedure returns a block of code. > A concurrent procedure returns a process. That was the part I wasn't aware of. Not that I am likely to use a concurrent procedure. But it is something to keep in mind. I mostly use subprograms when there is a likelihood of reuse. But I am aware that it can help with design partitioning and decision hiding. Too bad I am working on learning Verilog. Simpler tools for simpler minds perhaps. :^) > > I guess the downside of this is that it can get pretty messy to > > describe a complex process as functions, which is pretty much what we > > are talking about. > > I disagree. A function is a clean way > to hide an asynchronous process and > the wires and sensitivity that go with it. Whaaa..? What wires does it hide that doesn't happen in a process? Rick From newsfish@newsfish Fri Feb 3 13:10:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 23 Jan 2011 21:22:01 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 24 Message-ID: <4d3c8de8$0$14253$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 69b487dd.news.skynet.be X-Trace: 1295814120 news.skynet.be 14253 91.177.14.122:50808 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4638 rickman wrote: > On Jan 23, 12:23 pm, Mike Treseler wrote: >>> I guess the downside of this is that it can get pretty messy to >>> describe a complex process as functions, which is pretty much what we >>> are talking about. >> I disagree. A function is a clean way >> to hide an asynchronous process and >> the wires and sensitivity that go with it. > > Whaaa..? What wires does it hide that doesn't happen in a process? A function that works on intermediate/temporary variables within a clocked process can create combinatorial logic without requiring sensitivity specifications. Big news? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:10:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!194.109.133.84.MISMATCH!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4d3ca077$0$81481$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Newsgroups: comp.lang.vhdl Date: Sun, 23 Jan 2011 22:41:11 +0100 References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 65 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295818871 news.xs4all.nl 81481 puiterl/[::ffff:195.242.97.150]:57502 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4639 Mike Treseler wrote: > On 1/22/2011 2:02 PM, rickman wrote: > >> Ok, that's a different animal. I've used functions like this, but >> only for simple functions with few ins and outs... well, one out to be >> exact... :^) > > I can use more than one. > >> Paul was saying you can use procedures like this too, > > A function returns a value. > A procedure returns a block of code. > A concurrent procedure returns a process. In my opinion this tends to unneeded mystification. A procedure does not return anything. The only thing that happens are the assignments via the OUT an INOUT mode parameters. Every concurrent procedure call has its equivalent process description. So in my example: my_proc_i: my_proc(sig1, sig2, sig3, sig4, sig5); where the third to fifth formal parameter are of mode IN, the equivalent process description would be: my_proc_i: PROCESS IS BEGIN my_proc(sig1, sig2, sig3, sig4, sig5); WAIT ON sig3, sig4, sig5; END PROCESS my_proc_i; No more, no less. It also shows that any local varaible declared in in the procedure will not hold its value over time. Each time one or more signals changes (has an event), the procedure is called and the local variable are initialized again. >> I never realized that a procedure could be >> used as a concurrent statement, or maybe I've just never done it and >> forgot! > > It would be hard for me to forget that experience. > I prefer using an direct instance in this case. I use concurrent procedure calls in behavioral code. Another trick I use then is to make an endless loop in the body of the procedure. That way the local variables of the procedure hold their values over time. That is because the procedure is never left: it does not contain a RETURN statement, nor does it ever reach the end. Of course, the procedure will contain a WAIT statement in the endless loop. All this of course is highly non-synthesisable! But I guess the simple concurrent procedure call is synthesisable. Never tried it though: I hardly ever write synthesisable code. Synthesizers are sooo limiting.... ;-) -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.kpn.net!pfeed09.wxs.nl!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d3ca3c6$0$41114$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Newsgroups: comp.lang.vhdl Date: Sun, 23 Jan 2011 22:55:18 +0100 References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 19 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295819719 news.xs4all.nl 41114 puiterl/[::ffff:195.242.97.150]:32984 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4640 rickman wrote: > While looking this up just now I found that the Entity declaration can > contain statements including a "passive concurrent procedure call". > They don't define what "passive" means in this context. >From the LRM (Language Reference Manual): A process statement is said to be a passive process if neither the process itself, nor any procedure of which the process is a parent, contains a signal assignment statement. It is an error if a process or a concurrent statement, other than a passive process or a concurrent statement equivalent to such a process, appears in the entity statement part of an entity declaration. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sun, 23 Jan 2011 14:17:28 -0800 Lines: 29 Message-ID: <8q3nnpF9vgU1@mid.individual.net> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3ca077$0$81481$e4fe514c@news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net mT9zXJJVlPdVp3qED2K6Vg/yKPF7BTdLYZl5KBzx3w8FHrXXu0 Cancel-Lock: sha1:NACUI1V5Yd2TNOYYJEE2eZzXo60= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <4d3ca077$0$81481$e4fe514c@news.xs4all.nl> Xref: feeder.eternal-september.org comp.lang.vhdl:4641 > Mike Treseler wrote: >> A function returns a value. >> A procedure returns a block of code. >> A concurrent procedure returns a process. On 1/23/2011 1:41 PM, Paul Uiterlinden wrote: > In my opinion this tends to unneeded mystification. > A procedure does not return anything. Yes, that is a simplification, but I could elaborate a procedure call in my editor by pasting the procedure, and replacing the formal parameters. That's my mental picture. > The only thing that happens are the assignments via the > OUT an INOUT mode parameters. The structural view is also valid. I often use process variables in scope, so I don't see the wires. ... > It also shows that any local variable declared in in the procedure will not > hold its value over time. But process variables do, and synthesis will make the gates or flops as needed. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:10:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d3cad65$0$41103$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Newsgroups: comp.lang.vhdl Date: Sun, 23 Jan 2011 23:36:21 +0100 References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3ca077$0$81481$e4fe514c@news.xs4all.nl> <8q3nnpF9vgU1@mid.individual.net> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 25 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295822182 news.xs4all.nl 41103 puiterl/[::ffff:195.242.97.150]:40572 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4642 Mike Treseler wrote: >> The only thing that happens are the assignments via the >> OUT an INOUT mode parameters. > > The structural view is also valid. > I often use process variables in scope, so I don't see the wires. You mean that you use the process variables within the procedure body without passing them as procedure arguments, right? >> It also shows that any local variable declared in in the procedure will >> not hold its value over time. > > But process variables do, and synthesis will make > the gates or flops as needed. Indeed they do. I merely wanted to make clear that local variables in procedures don't, even if the procedure is used with a concurrent procedure call. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n10g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sun, 23 Jan 2011 17:37:31 -0800 (PST) Organization: http://groups.google.com Lines: 24 Message-ID: <6eb485fb-d774-4c8a-b298-aa01da5d94ab@n10g2000yqd.googlegroups.com> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295833051 21890 127.0.0.1 (24 Jan 2011 01:37:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 01:37:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqd.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4643 On Jan 23, 2:11=A0pm, rickman wrote: > Personally, I prefer > not to do this mainly because it separates relevant code so that I > can't see it together in one screen. =A0Or can you define procedures > anywhere you wish in the concurrent code? =A0I believe they have to be > at the head of the architecture in the definitions. > Not necessarily. With a few more keystrokes you can make the procedure right where you want it in the code using a block statement. The 'block' is essentially the same as an architecture in structure allowing you to define functions, procedure, signals, etc. Not much extra typing to get this, and can be worth it in terms of keeping the code readable without having to jump around. Example: my_block: block -- Define your procedures and functions here -- You can also define 'local' signals here that are -- not visible outside of the block. begin -- Put your code here that uses the procedure end block my_block; From newsfish@newsfish Fri Feb 3 13:10:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w2g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Sun, 23 Jan 2011 21:23:23 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <87a79625-f71f-43ca-8515-d9afe308136d@w2g2000yqb.googlegroups.com> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3c8de8$0$14253$ba620e4c@news.skynet.be> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295846603 9078 127.0.0.1 (24 Jan 2011 05:23:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 05:23:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w2g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4644 On Jan 23, 3:22=A0pm, Jan Decaluwe wrote: > rickman wrote: > > On Jan 23, 12:23 pm, Mike Treseler wrote: > >>> I guess the downside of this is that it can get pretty messy to > >>> describe a complex process as functions, which is pretty much what we > >>> are talking about. > >> I disagree. A function is a clean way > >> to hide an asynchronous process and > >> the wires and sensitivity that go with it. > > > Whaaa..? =A0What wires does it hide that doesn't happen in a process? > > A function that works on intermediate/temporary variables > within a clocked process can create combinatorial logic > without requiring sensitivity specifications. > > Big news? And how exactly is that different from a process??? Sounds to me like no news at all. Rick From newsfish@newsfish Fri Feb 3 13:10:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Mon, 24 Jan 2011 09:31:54 +0100 From: Jan Decaluwe User-Agent: Thunderbird 2.0.0.24 (X11/20101027) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3c8de8$0$14253$ba620e4c@news.skynet.be> <87a79625-f71f-43ca-8515-d9afe308136d@w2g2000yqb.googlegroups.com> In-Reply-To: <87a79625-f71f-43ca-8515-d9afe308136d@w2g2000yqb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 32 Message-ID: <4d3d38fa$0$14258$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: c22302e1.news.skynet.be X-Trace: 1295857914 news.skynet.be 14258 91.177.14.122:42960 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:4645 rickman wrote: > On Jan 23, 3:22 pm, Jan Decaluwe wrote: >> rickman wrote: >>> On Jan 23, 12:23 pm, Mike Treseler wrote: >>>>> I guess the downside of this is that it can get pretty messy to >>>>> describe a complex process as functions, which is pretty much what we >>>>> are talking about. >>>> I disagree. A function is a clean way >>>> to hide an asynchronous process and >>>> the wires and sensitivity that go with it. >>> Whaaa..? What wires does it hide that doesn't happen in a process? >> A function that works on intermediate/temporary variables >> within a clocked process can create combinatorial logic >> without requiring sensitivity specifications. >> >> Big news? > > And how exactly is that different from a process??? Again, because functions don't have sensitivity lists of course! Still, they are guaranteed to have combinatorial semantics as they can't have side effects in VHDL. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:10:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Mon, 24 Jan 2011 00:41:22 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: <5eec2f09-2f56-434e-9470-b6342b09d69f@k22g2000yqh.googlegroups.com> References: <41hhj6ljkk0j57pe2ji6dkh104jhvl9dk6@4ax.com> <1a12d508-aa5a-43d2-a9b1-e7226a3bdb46@e4g2000vbg.googlegroups.com> <7kujj612ak7vd3i08cekgk0ube5rkpra5d@4ax.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295858482 20986 127.0.0.1 (24 Jan 2011 08:41:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 08:41:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4646 On 21 Jan., 22:28, Jonathan Bromley wrote: > On Thu, 20 Jan 2011 23:37:50 -0800 (PST), backhus wrote: > >if you want to implement the all keyword in your favorite synthesis > >tool, you can do it like this: > > >signal all : std_logic ; > > >Now you can use > > >process(all) > > >in your non-VHDL2008 synthesis tool, and it won't throw errors. > > I fear not. =A0'all' is already a reserved word in every > version of the VHDL standard that I know of. (Think of > "use ieee.std_logic_1164.all;") > > Cute idea, though. > -- > Jonathan Bromley Hi Jonathan, *$%&! You're right, of course. My only excuse is that the library stuff is handled by templates in 99.9% of my sources. Sorry everybody for causing confusion. Regards Eilert From newsfish@newsfish Fri Feb 3 13:10:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k13g2000vbq.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Mon, 24 Jan 2011 06:47:57 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <4e30fa85-6d88-4f7d-be03-86711bbeaf6e@k13g2000vbq.googlegroups.com> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3c8de8$0$14253$ba620e4c@news.skynet.be> <87a79625-f71f-43ca-8515-d9afe308136d@w2g2000yqb.googlegroups.com> <4d3d38fa$0$14258$ba620e4c@news.skynet.be> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295880477 23101 127.0.0.1 (24 Jan 2011 14:47:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 14:47:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k13g2000vbq.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4647 On Jan 24, 3:31=A0am, Jan Decaluwe wrote: > rickman wrote: > > On Jan 23, 3:22 pm, Jan Decaluwe wrote: > >> rickman wrote: > >>> On Jan 23, 12:23 pm, Mike Treseler wrote: > >>>>> I guess the downside of this is that it can get pretty messy to > >>>>> describe a complex process as functions, which is pretty much what = we > >>>>> are talking about. > >>>> I disagree. A function is a clean way > >>>> to hide an asynchronous process and > >>>> the wires and sensitivity that go with it. > >>> Whaaa..? =A0What wires does it hide that doesn't happen in a process? > >> A function that works on intermediate/temporary variables > >> within a clocked process can create combinatorial logic > >> without requiring sensitivity specifications. > > >> Big news? > > > And how exactly is that different from a process??? =A0 > > Again, because functions don't have sensitivity lists of course! > > Still, they are guaranteed to have combinatorial semantics as > they can't have side effects in VHDL. So in regards to hiding the "wires", they are not different at all... Rick From newsfish@newsfish Fri Feb 3 13:10:26 2012 Date: Mon, 24 Jan 2011 21:32:01 +0100 From: =?ISO-8859-1?Q?Trygve_Laugst=F8l?= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 196.80-203-21.nextgentel.com X-Original-NNTP-Posting-Host: 196.80-203-21.nextgentel.com Message-ID: <4d3de1c1$1@news.broadpark.no> X-Trace: news.broadpark.no 1295901121 80.203.21.196 (24 Jan 2011 21:32:01 +0200) Lines: 35 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!feed.news.qwest.net!mpls-nntp-07.inet.qwest.net!nntp1.phx1.gblx.net!nntp.gblx.net!nntp.gblx.net!nntp3.phx1!news.broadpark.no!not-for-mail Xref: feeder.eternal-september.org comp.arch.fpga:14122 comp.lang.vhdl:4648 Hello! I'm trying to get the following snippet to work and I'm 1) wondering what's wrong and 2) wondering if I'm going about this the right way. I have two clocks, one CPU clock (at 48MHz) and a LCD clock (200kHz) which control the CPU and the output to the LCD (obviously enough). What I want to happen is that the CPU will set trigger on the leading edge of the CPU clock and clear it on the falling edge of the LCD clock (which should ensure that it has been picked up by the 'main' process). The error message I'm getting is "statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition". The code: trigger_xfer: process(reset, clk, clk_200kHz, output_trigger) begin trigger <= '0'; if reset = '1' then trigger <= '0'; elsif clk'event and clk = '1' and output_trigger = '1' then trigger <= '1'; elsif clk_200kHz'event and clk_200kHz = '0' then trigger <= '0'; end if; end process; main: process(...) if reset ... elsif clk_200kHz'event and clk_200kHz = '1' then ... end if; end process; From newsfish@newsfish Fri Feb 3 13:10:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m20g2000prc.googlegroups.com!not-for-mail From: Gabor Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition Date: Mon, 24 Jan 2011 12:41:01 -0800 (PST) Organization: http://groups.google.com Lines: 58 Message-ID: <8bc5dd48-09ae-4e42-bbb3-1438759af346@m20g2000prc.googlegroups.com> References: <4d3de1c1$1@news.broadpark.no> NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295901661 21306 127.0.0.1 (24 Jan 2011 20:41:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 20:41:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000prc.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14123 comp.lang.vhdl:4649 On Jan 24, 3:32=A0pm, Trygve Laugst=F8l wrote: > Hello! > > I'm trying to get the following snippet to work and I'm 1) wondering > what's wrong and 2) wondering if I'm going about this the right way. > > I have two clocks, one CPU clock (at 48MHz) and a LCD clock (200kHz) > which control the CPU and the output to the LCD (obviously enough). What > I want to happen is that the CPU will set trigger on the leading edge of > the CPU clock and clear it on the falling edge of the LCD clock (which > should ensure that it has been picked up by the 'main' process). > > The error message I'm getting is "statement is not synthesizable since > it does not hold its value under NOT(clock-edge) condition". > > The code: > > =A0 =A0 =A0trigger_xfer: process(reset, clk, clk_200kHz, output_trigger) > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0trigger <=3D '0'; > =A0 =A0 =A0 =A0 =A0if reset =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0trigger <=3D '0'; > =A0 =A0 =A0 =A0 =A0elsif clk'event and clk =3D '1' and output_trigger =3D= '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0trigger <=3D '1'; > =A0 =A0 =A0 =A0 =A0elsif clk_200kHz'event and clk_200kHz =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0trigger <=3D '0'; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0end process; > > =A0 =A0 =A0main: process(...) > =A0 =A0 =A0 =A0 =A0if reset > =A0 =A0 =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 =A0 =A0elsif clk_200kHz'event and clk_200kHz =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0end process; First, I know of no FPGA that has dual-clocked flip-flops available in the internal fabric. So it's no wonder that the code is not synthesizable. Second, 200 KHz is really slow, so you should probably just sample it with the 48 MHz CPU clock and use the sampled signal with another flip-flop delay to detect edges instead of trying to create a dual-clocked process. Third. It's not clear to me that you are taking care of synchronization properly here. If the intent is for a single event on the CPU clock to create an output that can be sampled at the falling edge of the 200 KHz clock, then I don't see how you will ensure any minimum setup time unless the event was already somehow synchronous to the 200 KHz clock. -- Gabor From newsfish@newsfish Fri Feb 3 13:10:27 2012 Date: Mon, 24 Jan 2011 21:47:26 +0100 From: =?ISO-8859-1?Q?Trygve_Laugst=F8l?= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.5; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition References: <4d3de1c1$1@news.broadpark.no> <8bc5dd48-09ae-4e42-bbb3-1438759af346@m20g2000prc.googlegroups.com> In-Reply-To: <8bc5dd48-09ae-4e42-bbb3-1438759af346@m20g2000prc.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit NNTP-Posting-Host: 196.80-203-21.nextgentel.com X-Original-NNTP-Posting-Host: 196.80-203-21.nextgentel.com Message-ID: <4d3de55e$1@news.broadpark.no> X-Trace: news.broadpark.no 1295902046 80.203.21.196 (24 Jan 2011 21:47:26 +0200) Lines: 73 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!usenet.stanford.edu!news.kjsl.com!rahul.net!wasp.rahul.net!rahul.net!nntp1.phx1.gblx.net!nntp.gblx.net!nntp.gblx.net!nntp3.phx1!news.broadpark.no!not-for-mail Xref: feeder.eternal-september.org comp.arch.fpga:14124 comp.lang.vhdl:4650 [Note that I'm quite a newbie to VHDL] On 1/24/11 9:41 PM, Gabor wrote: > On Jan 24, 3:32 pm, Trygve Laugstl wrote: >> Hello! >> >> I'm trying to get the following snippet to work and I'm 1) wondering >> what's wrong and 2) wondering if I'm going about this the right way. >> >> I have two clocks, one CPU clock (at 48MHz) and a LCD clock (200kHz) >> which control the CPU and the output to the LCD (obviously enough). What >> I want to happen is that the CPU will set trigger on the leading edge of >> the CPU clock and clear it on the falling edge of the LCD clock (which >> should ensure that it has been picked up by the 'main' process). >> >> The error message I'm getting is "statement is not synthesizable since >> it does not hold its value under NOT(clock-edge) condition". >> >> The code: >> >> trigger_xfer: process(reset, clk, clk_200kHz, output_trigger) >> begin >> trigger<= '0'; >> if reset = '1' then >> trigger<= '0'; >> elsif clk'event and clk = '1' and output_trigger = '1' then >> trigger<= '1'; >> elsif clk_200kHz'event and clk_200kHz = '0' then >> trigger<= '0'; >> end if; >> end process; >> >> main: process(...) >> if reset >> ... >> elsif clk_200kHz'event and clk_200kHz = '1' then >> ... >> end if; >> end process; > > First, I know of no FPGA that has dual-clocked flip-flops available in > the internal > fabric. So it's no wonder that the code is not synthesizable. Hm, I though this should synthesize a S/R+reset flip flop but I guess because of the 'event it will become clocks instead. > Second, 200 KHz is really slow, so you should probably just sample it > with the > 48 MHz CPU clock and use the sampled signal with another flip-flop > delay > to detect edges instead of trying to create a dual-clocked process. How would that work? It is generated from the 48MHz clock already just on the outside of the entity. > Third. It's not clear to me that you are taking care of > synchronization properly > here. If the intent is for a single event on the CPU clock to create > an output > that can be sampled at the falling edge of the 200 KHz clock, then I > don't > see how you will ensure any minimum setup time unless the event was > already somehow synchronous to the 200 KHz clock. Hm, I'm not really seeing the problem but that's probably because of my lack of understanding. Could you elaborate or show/point me some code that does what I want to do? I've been trying to read up on links from searches like "clock synchronization" and "clock domains" but haven't found something that really applies to my case (and makes sense to me). -- Trygve From newsfish@newsfish Fri Feb 3 13:10:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d3def63$0$81483$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition Newsgroups: comp.arch.fpga,comp.lang.vhdl Followup-To: comp.arch.fpga Date: Mon, 24 Jan 2011 22:30:11 +0100 References: <4d3de1c1$1@news.broadpark.no> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8Bit Lines: 38 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1295904611 news.xs4all.nl 81483 puiterl/[::ffff:195.242.97.150]:45199 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.arch.fpga:14127 comp.lang.vhdl:4651 Trygve Laugstøl wrote: > Hello! > > I'm trying to get the following snippet to work and I'm 1) wondering > what's wrong The first assignment to "trigger" (right after the "begin") cannot be right. What you have described here is something like: "reset trigger on any event on signals reset, clk, clk_200kHz and output_trigger, unless there is a rising edge on clk while output_trigger is '1'. In the latter case, set trigger." If you leave out the first assignment, things perhaps start looking what you want. If it will be synthesisable, I don't know (I don't do synthesis). Have you simulated this code at all? > The code: > > trigger_xfer: process(reset, clk, clk_200kHz, output_trigger) > begin > trigger <= '0'; > if reset = '1' then > trigger <= '0'; > elsif clk'event and clk = '1' and output_trigger = '1' then > trigger <= '1'; > elsif clk_200kHz'event and clk_200kHz = '0' then > trigger <= '0'; > end if; > end process; > -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y9g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition Date: Mon, 24 Jan 2011 14:00:00 -0800 (PST) Organization: http://groups.google.com Lines: 111 Message-ID: <45f94028-eff4-40ef-b10f-4ec8f6561438@y9g2000prf.googlegroups.com> References: <4d3de1c1$1@news.broadpark.no> <8bc5dd48-09ae-4e42-bbb3-1438759af346@m20g2000prc.googlegroups.com> <4d3de55e$1@news.broadpark.no> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1295906400 31488 127.0.0.1 (24 Jan 2011 22:00:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 24 Jan 2011 22:00:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y9g2000prf.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14129 comp.lang.vhdl:4652 On Jan 24, 3:47 pm, Trygve Laugst=F8l wrote: > [Note that I'm quite a newbie to VHDL] > > On 1/24/11 9:41 PM, Gabor wrote: > > > > > On Jan 24, 3:32 pm, Trygve Laugst=F8l wrote: > >> Hello! > > >> I'm trying to get the following snippet to work and I'm 1) wondering > >> what's wrong and 2) wondering if I'm going about this the right way. > > >> I have two clocks, one CPU clock (at 48MHz) and a LCD clock (200kHz) > >> which control the CPU and the output to the LCD (obviously enough). Wh= at > >> I want to happen is that the CPU will set trigger on the leading edge = of > >> the CPU clock and clear it on the falling edge of the LCD clock (which > >> should ensure that it has been picked up by the 'main' process). > > >> The error message I'm getting is "statement is not synthesizable since > >> it does not hold its value under NOT(clock-edge) condition". > > >> The code: > > >> trigger_xfer: process(reset, clk, clk_200kHz, output_trigger) > >> begin > >> trigger<=3D '0'; > >> if reset =3D '1' then > >> trigger<=3D '0'; > >> elsif clk'event and clk =3D '1' and output_trigger =3D '1' t= hen > >> trigger<=3D '1'; > >> elsif clk_200kHz'event and clk_200kHz =3D '0' then > >> trigger<=3D '0'; > >> end if; > >> end process; > > >> main: process(...) > >> if reset > >> ... > >> elsif clk_200kHz'event and clk_200kHz =3D '1' then > >> ... > >> end if; > >> end process; > > > First, I know of no FPGA that has dual-clocked flip-flops available in > > the internal > > fabric. So it's no wonder that the code is not synthesizable. > > Hm, I though this should synthesize a S/R+reset flip flop but I guess > because of the 'event it will become clocks instead. > > > Second, 200 KHz is really slow, so you should probably just sample it > > with the > > 48 MHz CPU clock and use the sampled signal with another flip-flop > > delay > > to detect edges instead of trying to create a dual-clocked process. > > How would that work? It is generated from the 48MHz clock already just > on the outside of the entity. > > > Third. It's not clear to me that you are taking care of > > synchronization properly > > here. If the intent is for a single event on the CPU clock to create > > an output > > that can be sampled at the falling edge of the 200 KHz clock, then I > > don't > > see how you will ensure any minimum setup time unless the event was > > already somehow synchronous to the 200 KHz clock. > > Hm, I'm not really seeing the problem but that's probably because of my > lack of understanding. Could you elaborate or show/point me some code > that does what I want to do? I've been trying to read up on links from > searches like "clock synchronization" and "clock domains" but haven't > found something that really applies to my case (and makes sense to me). > > -- > Trygve Here is how I do it. I cut this from a program and ripped out all the other code to just highlight the edge detection. Replace TT_B2 with your LCD clock and add your code where indicated. The function NegEdge() just ANDs TT_DD with not TT_D to make it clear what the IF statement is doing. There will be a delay of one to two clock cycles from the edge of your slow clock before the code in the IF statement is executed, but with your app, I expect this doesn't matter. CTPData: process (SysClk, SysRst) begin if (SysRst =3D '1') then TT_D <=3D '0'; TT_DD <=3D '0'; elsif (rising_edge(SysClk)) then TT_D <=3D TT_B2; TT_DD <=3D TT_D; -- RD output interface if (NegEdge(TT_D, TT_DD)) then -- falling edge of TT data strobe -- This is where you put your LCD code end if; -- NegEdge(TT end if; -- elsif (rising_edge(SysClk end process CTPData; This approach solves a lot of problems. It gets rid of communication issues between clock domains and the two FFs handle metastability issues, which you can still have even though the two frequencies are locked, the phase is likely not. If you really want to be sure of dealing with meta stability, combine the two delay FFs and register that. With only one LUT, 20 ns will be lots of settling time. Rick From newsfish@newsfish Fri Feb 3 13:10:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why Doesn't VHDL Have a Wildcard Sensitivity List? Date: Mon, 24 Jan 2011 14:04:29 -0800 Lines: 51 Message-ID: <8q6bbcFcuuU1@mid.individual.net> References: <073c5601-8f33-4e7d-b0f1-a758f65292f5@l7g2000vbv.googlegroups.com> <4dc847b0-e6c1-4ee8-a8f6-4d377e03d303@n10g2000yqd.googlegroups.com> <8q36h8F919U1@mid.individual.net> <4d3c8de8$0$14253$ba620e4c@news.skynet.be> <87a79625-f71f-43ca-8515-d9afe308136d@w2g2000yqb.googlegroups.com> <4d3d38fa$0$14258$ba620e4c@news.skynet.be> <4e30fa85-6d88-4f7d-be03-86711bbeaf6e@k13g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 7yvAClTgstKNqikRqwQRIgoSxztjXOlzqeWTsWotCxW5mIcVfg Cancel-Lock: sha1:8I7x1MQ/mqfg9JakSmd36YdJ3BY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <4e30fa85-6d88-4f7d-be03-86711bbeaf6e@k13g2000vbq.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4653 On 1/24/2011 6:47 AM, rickman wrote: > On Jan 24, 3:31 am, Jan Decaluwe wrote: >> rickman wrote: >>> On Jan 23, 3:22 pm, Jan Decaluwe wrote: >>>> rickman wrote: >>>>> On Jan 23, 12:23 pm, Mike Treseler wrote: >>>>>>> I guess the downside of this is that it can get pretty messy to >>>>>>> describe a complex process as functions, which is pretty much what we >>>>>>> are talking about. >>>>>> I disagree. A function is a clean way >>>>>> to hide an asynchronous process and >>>>>> the wires and sensitivity that go with it. >>>>> Whaaa..? What wires does it hide that doesn't happen in a process? >>>> A function that works on intermediate/temporary variables >>>> within a clocked process can create combinatorial logic >>>> without requiring sensitivity specifications. >> >>>> Big news? >> >>> And how exactly is that different from a process??? >> >> Again, because functions don't have sensitivity lists of course! >> >> Still, they are guaranteed to have combinatorial semantics as >> they can't have side effects in VHDL. > > So in regards to hiding the "wires", they are not different at all... This thread is about the vhdl process sensitivity list and how to avoid simulation problems if I use it for anything other than the clock or reset inputs. This question has been answered. The "wires" issue is a red herring. http://en.wikipedia.org/wiki/Red_herring By "wire hiding" I mean that by using a single process description using variables, there are only port inputs and outputs in the logic description. Everything goes in one box -- the entity. There are no internal "directions" to worry about, other than code going from the top to the bottom of the page. In a multi-process description, I have two or more process boxes inside the entity, each with inputs and outputs. I claim that not having to worry about connecting internal "outputs" together in my description is a side benefit *for me* of this description style. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:10:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!feeder.news-service.com!postnews.google.com!v31g2000pri.googlegroups.com!not-for-mail From: Rejin James Newsgroups: comp.lang.vhdl Subject: Project help Date: Mon, 24 Jan 2011 21:49:53 -0800 (PST) Organization: http://groups.google.com Lines: 118 Message-ID: NNTP-Posting-Host: 115.184.117.134 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1295934593 23926 127.0.0.1 (25 Jan 2011 05:49:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 25 Jan 2011 05:49:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v31g2000pri.googlegroups.com; posting-host=115.184.117.134; posting-account=sVZi6woAAAALUtg7YjdT9QJbVW4okBS2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1.4) Gecko/20091016 FireDownload/2.0.1 Firefox/3.5.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4654 Hi Friends I am currently doin my university project on the topic Low Power AES algorithm using VHDL I was having problems understanding the logic of Mixcolumns operation in GALIOS FIELD and other parts of the algorithm like galios field multiplication and key expansion. Can anyone help me out >?? this is the base paper im following www.martes-itea.org/.../Hamalainen-Design_and_Implementation_2.pdf actually i got the cores from their website and was having a problem in understanding it . They are using 8- bit data paths and i was having problems in understanding their architecture and implementation in VHDl. The following is the code for mixcolumns operation . can somebody help me out with it ?? i was not understanding the GALIOS FIELD multiplication concept. library ieee; use ieee.std_logic_1164.all; entity mixcolumns is port( clk : in std_logic; start_in : in std_logic; inverse_in : in std_logic; -- '1' = inverse transformation data_in : in std_logic_vector (7 downto 0); -- input data data0_out : out std_logic_vector (7 downto 0); -- output data data1_out : out std_logic_vector (7 downto 0); -- output data data2_out : out std_logic_vector (7 downto 0); -- output data data3_out : out std_logic_vector (7 downto 0) -- output data ); end mixcolumns; -- fwd_rtl = forward only architecture fwd_rtl of mixcolumns is -- GF(2^8) multiplication with constant: x -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 function gf256_mul2 (a : std_logic_vector(7 downto 0)) return std_logic_vector is variable b : std_logic_vector(7 downto 0); begin b(0) := a(7); b(1) := a(0) xor a(7); b(2) := a(1); b(3) := a(2) xor a(7); b(4) := a(3) xor a(7); b(5) := a(4); b(6) := a(5); b(7) := a(6); return b; end; type accum_array_t is array (0 to 3) of std_logic_vector(7 downto 0); signal accum_r : accum_array_t; signal prod2, prod3 : std_logic_vector(7 downto 0); signal x : std_logic_vector(7 downto 0); begin -- rtl assert (inverse_in /= '1') report "this architecture supports only forward operation" severity failure; x <= data_in; prod2 <= gf256_mul2(x); prod3 <= prod2 xor x; -- forward transform: -- -- x0 |02 03 01 01| y0 -- x1 = |01 02 03 01|*y1 -- x2 |01 01 02 03| y2 -- x3 |03 01 01 02| y3 -- inverse transform -- y0 |0e 0b 0d 09| x0 -- y1 = |09 0e 0b 0d|*x1 -- y2 |0d 09 0e 0b| x2 -- y3 |0b 0d 09 0e| x3 clocked : process (clk) begin -- process clocked if rising_edge(clk) then -- rising clock edge if (start_in = '1') then accum_r(0) <= x; accum_r(1) <= x; accum_r(2) <= prod3; accum_r(3) <= prod2; else accum_r(0) <= x xor accum_r(1); accum_r(1) <= x xor accum_r(2); accum_r(2) <= prod3 xor accum_r(3); accum_r(3) <= prod2 xor accum_r(0); end if; end if; end process clocked; data0_out <= accum_r(0); data1_out <= accum_r(1); data2_out <= accum_r(2); data3_out <= accum_r(3); end fwd_rtl; ANY HELP WOULD BE APPRECIATED .. thanks From newsfish@newsfish Fri Feb 3 13:10:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y19g2000prb.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Wed, 26 Jan 2011 00:10:22 -0800 (PST) Organization: http://groups.google.com Lines: 153 Message-ID: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296029626 8774 127.0.0.1 (26 Jan 2011 08:13:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 26 Jan 2011 08:13:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y19g2000prb.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4655 On 25 Jan., 06:49, Rejin James wrote: > Hi Friends I am currently doin my university project on the topic > Low Power AES algorithm using VHDL > > I was having problems understanding the logic of Mixcolumns operation > in GALIOS FIELD and other parts of the algorithm like galios field > multiplication and key expansion. > Can anyone help me out >?? > > this is the base paper im followingwww.martes-itea.org/.../Hamalainen-Des= ign_and_Implementation_2.pdf > > actually i got the cores from their website and was having a problem > in understanding it . > They are using 8- bit data paths and i was having problems in > understanding their architecture and implementation in VHDl. > > The following is the code for mixcolumns operation . can somebody help > me out with it ?? > i was not understanding the GALIOS FIELD multiplication concept. > > library ieee; > use ieee.std_logic_1164.all; > > entity mixcolumns is > =A0 port( > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > =A0 =A0 start_in =A0 : in =A0std_logic; > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' =3D inverse > transformation > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); =A0-- input= data > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0-- output da= ta > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0-- output da= ta > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0-- output da= ta > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 -- output da= ta > =A0 =A0 ); > end mixcolumns; > > -- fwd_rtl =3D forward only > architecture fwd_rtl of mixcolumns is > > =A0 -- GF(2^8) multiplication with constant: x > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > =A0 =A0 return std_logic_vector is > =A0 =A0 variable b : std_logic_vector(7 downto 0); > =A0 begin > =A0 =A0 b(0) :=3D a(7); > =A0 =A0 b(1) :=3D a(0) xor a(7); > =A0 =A0 b(2) :=3D a(1); > =A0 =A0 b(3) :=3D a(2) xor a(7); > =A0 =A0 b(4) :=3D a(3) xor a(7); > =A0 =A0 b(5) :=3D a(4); > =A0 =A0 b(6) :=3D a(5); > =A0 =A0 b(7) :=3D a(6); > =A0 =A0 return b; > =A0 end; > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vector(7 downto > 0); > =A0 signal accum_r : accum_array_t; > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0); > > begin =A0-- rtl > > =A0 assert (inverse_in /=3D '1') report "this architecture supports only > forward operation" > =A0 =A0 severity failure; > =A0 x <=3D data_in; > > =A0 prod2 <=3D gf256_mul2(x); > =A0 prod3 <=3D prod2 xor x; > > =A0 -- forward transform: > =A0 -- > =A0 -- x0 =A0 |02 03 01 01| y0 > =A0 -- x1 =3D |01 02 03 01|*y1 > =A0 -- x2 =A0 |01 01 02 03| y2 > =A0 -- x3 =A0 |03 01 01 02| y3 > > =A0 -- inverse transform > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > =A0 clocked : process (clk) > =A0 begin =A0-- process clocked > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising clock e= dge > =A0 =A0 =A0 if (start_in =3D '1') then > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process clocked; > > =A0 data0_out <=3D accum_r(0); > =A0 data1_out <=3D accum_r(1); > =A0 data2_out <=3D accum_r(2); > =A0 data3_out <=3D accum_r(3); > > end fwd_rtl; > > ANY HELP WOULD BE APPRECIATED .. thanks Hi, that's a lot of questions at once. :-) Galois Field math is a topic for 10th semester math students. So don't be bothered when it seems complicated to understand. In some VERY simple words: The galois field is a limited bunch of numbers, that obeys defined mathematical rules. This is only possible because he operations can always be seen as modulo operations in order to keep the number space constant. When you chop down the field size to tw0 you can work with simple gate functions (AND and XOR) for multiplication and addition. Mix columns is an ordinary vector/matrix multiplication, where you multiply a row of the input matrix with a given transformation matrix. The result is then written to a column of the result matrix. The code you provided has one strange property. It takes a single stream of data (data_in) and creates four result values. You need to find out in which order the input stram has to provide the data of the input matrix (and when to apply start_in) and what to do with the four result values. Maybe you should take a look ath this book: The Design of Rijndael: AES. The Advanced Encryption Standard Written by the designers of the algorithm. There you find many examples and calculations that you can compare with your simulations, in order to understand how the code works that you have. Have a nice simulation Eilert From newsfish@newsfish Fri Feb 3 13:10:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: pbartosz Newsgroups: comp.lang.vhdl Subject: Wake process - Quartus II Date: Wed, 26 Jan 2011 02:57:13 -0800 (PST) Organization: http://groups.google.com Lines: 20 Message-ID: <5b441a12-1fc2-4673-acd5-4dd85a19c0af@k22g2000yqh.googlegroups.com> NNTP-Posting-Host: 149.156.96.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296039433 23188 127.0.0.1 (26 Jan 2011 10:57:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 26 Jan 2011 10:57:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=149.156.96.15; posting-account=jZyXKwoAAAA8AI09i4lgLgFwqJh4fw6g User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; pl-PL; rv:1.9.1.16) Gecko/20101227 Iceweasel/3.5.16 (like Firefox/3.5.16),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4656 I have a sample code: variable state : integer := 0; process (wake) begin if state = 0 then --some code; state := 1; wake <= not wake; elsif state = 1 then --some code; end if; end process; In ModelSim simulation it works correct, but in Quartus II simulation when process returns from state 0 it negates wake signal but process doesn't start again. What's the problem? Any solution? From newsfish@newsfish Fri Feb 3 13:10:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k21g2000prb.googlegroups.com!not-for-mail From: Rejin James Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Wed, 26 Jan 2011 04:32:34 -0800 (PST) Organization: http://groups.google.com Lines: 181 Message-ID: <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> NNTP-Posting-Host: 115.242.146.17 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296045155 17746 127.0.0.1 (26 Jan 2011 12:32:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 26 Jan 2011 12:32:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k21g2000prb.googlegroups.com; posting-host=115.242.146.17; posting-account=sVZi6woAAAALUtg7YjdT9QJbVW4okBS2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1.4) Gecko/20091016 FireDownload/2.0.1 Firefox/3.5.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4657 On Jan 26, 1:10=A0pm, backhus wrote: > On 25 Jan., 06:49, Rejin James wrote: > > > > > Hi Friends I am currently doin my university project on the topic > > Low Power AES algorithm using VHDL > > > I was having problems understanding the logic of Mixcolumns operation > > in GALIOS FIELD and other parts of the algorithm like galios field > > multiplication and key expansion. > > Can anyone help me out >?? > > > this is the base paper im followingwww.martes-itea.org/.../Hamalainen-D= esign_and_Implementation_2.pdf > > > actually i got the cores from their website and was having a problem > > in understanding it . > > They are using 8- bit data paths and i was having problems in > > understanding their architecture and implementation in VHDl. > > > The following is the code for mixcolumns operation . can somebody help > > me out with it ?? > > i was not understanding the GALIOS FIELD multiplication concept. > > > library ieee; > > use ieee.std_logic_1164.all; > > > entity mixcolumns is > > =A0 port( > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > =A0 =A0 start_in =A0 : in =A0std_logic; > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' =3D invers= e > > transformation > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); =A0-- inp= ut data > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0-- output = data > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0-- output = data > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0-- output = data > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 -- output = data > > =A0 =A0 ); > > end mixcolumns; > > > -- fwd_rtl =3D forward only > > architecture fwd_rtl of mixcolumns is > > > =A0 -- GF(2^8) multiplication with constant: x > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > =A0 =A0 return std_logic_vector is > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > =A0 begin > > =A0 =A0 b(0) :=3D a(7); > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > =A0 =A0 b(2) :=3D a(1); > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > =A0 =A0 b(5) :=3D a(4); > > =A0 =A0 b(6) :=3D a(5); > > =A0 =A0 b(7) :=3D a(6); > > =A0 =A0 return b; > > =A0 end; > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vector(7 down= to > > 0); > > =A0 signal accum_r : accum_array_t; > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0); > > > begin =A0-- rtl > > > =A0 assert (inverse_in /=3D '1') report "this architecture supports onl= y > > forward operation" > > =A0 =A0 severity failure; > > =A0 x <=3D data_in; > > > =A0 prod2 <=3D gf256_mul2(x); > > =A0 prod3 <=3D prod2 xor x; > > > =A0 -- forward transform: > > =A0 -- > > =A0 -- x0 =A0 |02 03 01 01| y0 > > =A0 -- x1 =3D |01 02 03 01|*y1 > > =A0 -- x2 =A0 |01 01 02 03| y2 > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > =A0 -- inverse transform > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > =A0 clocked : process (clk) > > =A0 begin =A0-- process clocked > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising clock= edge > > =A0 =A0 =A0 if (start_in =3D '1') then > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > =A0 =A0 =A0 end if; > > =A0 =A0 end if; > > =A0 end process clocked; > > > =A0 data0_out <=3D accum_r(0); > > =A0 data1_out <=3D accum_r(1); > > =A0 data2_out <=3D accum_r(2); > > =A0 data3_out <=3D accum_r(3); > > > end fwd_rtl; > > > ANY HELP WOULD BE APPRECIATED .. thanks > > Hi, > that's a lot of questions at once. :-) > Galois Field math is a topic for 10th semester math students. > So don't be bothered when it seems complicated to understand. > In some VERY simple words: The galois field is a limited bunch of > numbers, that obeys defined mathematical rules. > This is only possible because he operations can always be seen as > modulo operations in order to keep the number space constant. > When you chop down the field size to tw0 you can work with simple gate > functions (AND and XOR) for multiplication and addition. > > Mix columns is an ordinary vector/matrix multiplication, where you > multiply a row of the input matrix with a given transformation > matrix. > The result is then written to a column of the result matrix. > > The code you provided has one strange property. > It takes a single stream of data (data_in) and creates four result > values. > You need to find out in which order the input stram has to provide the > data of the input matrix (and when to apply start_in) > and what to do with the four result values. > > Maybe you should take a look ath this book: > The Design of Rijndael: AES. TheAdvanced Encryption Standard > Written by the designers of the algorithm. > There you find many examples and calculations that you can compare > with your simulations, in order to understand how the code works that > you have. > > Have a nice simulation > =A0 Eilert Hey Eilert, Thanks a lot for the reply. :-) i went through the galois Field multiplication once more from a book on cryptography and got a basic idea as to wat happens in that. The reason dat the code only takes one input is because i am implementing Aes algorithm with 8 bit DAta path (data input) And according to the paper that i am using the mix columns multiplier unit takes in the 8 bit data and produces 32 bit output which is then given to a parallel to serial converter. If u cud see the base paper which i was referring once then i guess u wud understand it better. Coz i was not able to understand much. And i also understood when to apply start_in. it helps us to control operation of mixcolumns for encryption or decryption. when start_in is not one it signifies we want to do the inverse operation i.e. decryption. From newsfish@newsfish Fri Feb 3 13:10:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d7g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Wake process - Quartus II Date: Wed, 26 Jan 2011 06:46:27 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: References: <5b441a12-1fc2-4673-acd5-4dd85a19c0af@k22g2000yqh.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296053187 16127 127.0.0.1 (26 Jan 2011 14:46:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 26 Jan 2011 14:46:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000vbv.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4658 On Jan 26, 10:57=A0am, pbartosz wrote: > I have a sample code: > > variable state : integer :=3D 0; > > process (wake) > begin > =A0 if state =3D 0 then > =A0 =A0 --some code; > =A0 =A0 state :=3D 1; > =A0 =A0 wake <=3D not wake; > =A0 elsif state =3D 1 then > =A0 =A0 =A0--some code; > =A0 end if; > end process; > > In ModelSim simulation it works correct, but in Quartus II simulation > when process returns from state 0 it negates wake signal but process > doesn't start again. > What's the problem? > Any solution? You shouldnt have a process that is sensitive to a signal inside the process, as you end up building a combinatorial loop. Think about the logic you are trying to describe, rather than trying to write software. Processes never return from anything. They are activiated whenever one of the signals in the sensitivity list changes. I suspect that Quartus built different logic to the behaviour you expected from modelsim because Quartus ignores sensitivity lists. From newsfish@newsfish Fri Feb 3 13:10:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder7.xlned.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d403eea$0$81474$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Wake process - Quartus II Newsgroups: comp.lang.vhdl Date: Wed, 26 Jan 2011 16:34:02 +0100 References: <5b441a12-1fc2-4673-acd5-4dd85a19c0af@k22g2000yqh.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 38 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1296056042 news.xs4all.nl 81474 puiterl/[::ffff:195.242.97.150]:42576 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4659 pbartosz wrote: > I have a sample code: > > variable state : integer := 0; > > process (wake) > begin > if state = 0 then > --some code; > state := 1; > wake <= not wake; > elsif state = 1 then > --some code; > end if; > end process; > > In ModelSim simulation it works correct, but in Quartus II simulation > when process returns from state 0 it negates wake signal but process > doesn't start again. > What's the problem? > Any solution? Besides what Tricky already said, I see a problem with multiple drivers on signal wake. Your process as described above forms the first driver on wake. There has to be second driver (process) that you have not described here. How else could wake ever be toggled to awake your process? Multiple processes driving a signal won't work, unless describing some bus system using tri-state buffers. Your description is not synthesisable anyhow. You try to describe hardware that is sensitive on both edges of wake. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u14g2000vbg.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Wed, 26 Jan 2011 23:29:29 -0800 (PST) Organization: http://groups.google.com Lines: 208 Message-ID: References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296113370 2231 127.0.0.1 (27 Jan 2011 07:29:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 27 Jan 2011 07:29:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u14g2000vbg.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4660 On 26 Jan., 13:32, Rejin James wrote: > On Jan 26, 1:10=A0pm, backhus wrote: > > > > > On 25 Jan., 06:49, Rejin James wrote: > > > > Hi Friends I am currently doin my university project on the topic > > > Low Power AES algorithm using VHDL > > > > I was having problems understanding the logic of Mixcolumns operation > > > in GALIOS FIELD and other parts of the algorithm like galios field > > > multiplication and key expansion. > > > Can anyone help me out >?? > > > > this is the base paper im followingwww.martes-itea.org/.../Hamalainen= -Design_and_Implementation_2.pdf > > > > actually i got the cores from their website and was having a problem > > > in understanding it . > > > They are using 8- bit data paths and i was having problems in > > > understanding their architecture and implementation in VHDl. > > > > The following is the code for mixcolumns operation . can somebody hel= p > > > me out with it ?? > > > i was not understanding the GALIOS FIELD multiplication concept. > > > > library ieee; > > > use ieee.std_logic_1164.all; > > > > entity mixcolumns is > > > =A0 port( > > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > > =A0 =A0 start_in =A0 : in =A0std_logic; > > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' =3D inve= rse > > > transformation > > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); =A0-- i= nput data > > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0-- outpu= t data > > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0-- outpu= t data > > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0-- outpu= t data > > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 -- outpu= t data > > > =A0 =A0 ); > > > end mixcolumns; > > > > -- fwd_rtl =3D forward only > > > architecture fwd_rtl of mixcolumns is > > > > =A0 -- GF(2^8) multiplication with constant: x > > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > > =A0 =A0 return std_logic_vector is > > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > > =A0 begin > > > =A0 =A0 b(0) :=3D a(7); > > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > > =A0 =A0 b(2) :=3D a(1); > > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > > =A0 =A0 b(5) :=3D a(4); > > > =A0 =A0 b(6) :=3D a(5); > > > =A0 =A0 b(7) :=3D a(6); > > > =A0 =A0 return b; > > > =A0 end; > > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vector(7 do= wnto > > > 0); > > > =A0 signal accum_r : accum_array_t; > > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0); > > > > begin =A0-- rtl > > > > =A0 assert (inverse_in /=3D '1') report "this architecture supports o= nly > > > forward operation" > > > =A0 =A0 severity failure; > > > =A0 x <=3D data_in; > > > > =A0 prod2 <=3D gf256_mul2(x); > > > =A0 prod3 <=3D prod2 xor x; > > > > =A0 -- forward transform: > > > =A0 -- > > > =A0 -- x0 =A0 |02 03 01 01| y0 > > > =A0 -- x1 =3D |01 02 03 01|*y1 > > > =A0 -- x2 =A0 |01 01 02 03| y2 > > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > > =A0 -- inverse transform > > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > > =A0 clocked : process (clk) > > > =A0 begin =A0-- process clocked > > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising clo= ck edge > > > =A0 =A0 =A0 if (start_in =3D '1') then > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > > =A0 =A0 =A0 else > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > > =A0 =A0 =A0 end if; > > > =A0 =A0 end if; > > > =A0 end process clocked; > > > > =A0 data0_out <=3D accum_r(0); > > > =A0 data1_out <=3D accum_r(1); > > > =A0 data2_out <=3D accum_r(2); > > > =A0 data3_out <=3D accum_r(3); > > > > end fwd_rtl; > > > > ANY HELP WOULD BE APPRECIATED .. thanks > > > Hi, > > that's a lot of questions at once. :-) > > Galois Field math is a topic for 10th semester math students. > > So don't be bothered when it seems complicated to understand. > > In some VERY simple words: The galois field is a limited bunch of > > numbers, that obeys defined mathematical rules. > > This is only possible because he operations can always be seen as > > modulo operations in order to keep the number space constant. > > When you chop down the field size to tw0 you can work with simple gate > > functions (AND and XOR) for multiplication and addition. > > > Mix columns is an ordinary vector/matrix multiplication, where you > > multiply a row of the input matrix with a given transformation > > matrix. > > The result is then written to a column of the result matrix. > > > The code you provided has one strange property. > > It takes a single stream of data (data_in) and creates four result > > values. > > You need to find out in which order the input stram has to provide the > > data of the input matrix (and when to apply start_in) > > and what to do with the four result values. > > > Maybe you should take a look ath this book: > > The Design of Rijndael: AES. TheAdvanced Encryption Standard > > Written by the designers of the algorithm. > > There you find many examples and calculations that you can compare > > with your simulations, in order to understand how the code works that > > you have. > > > Have a nice simulation > > =A0 Eilert > > Hey Eilert, > Thanks a lot for the reply. :-) > > i went through the galois Field multiplication once more from a book > on cryptography and got a basic idea as to wat happens in that. > > The reason dat the code only takes one input is because i am > implementing Aes algorithm with 8 bit DAta path (data input) > And according to the paper that i am using the mix columns multiplier > unit takes in the 8 bit data and produces 32 bit output which is then > given to a parallel to serial converter. > > If u cud see the base paper which i was referring once then i guess u > wud understand it better. Coz i was not able to understand much. > > And i also understood when to apply start_in. it helps us to control > operation of mixcolumns for encryption or decryption. > when start_in is not one it signifies we want to do the inverse > operation i.e. decryption. Hi, you confused start_in with inverse_in. Also inverse_in has to be '1' all the time since the code doesn't suport the inverse transformation. (Look at the assert statement) In the mentioned paper there is a signal mentioned called "en". That's probably called start_in in the provided source now. It has to be applied "During inputting the first byte of a column (bytes 0, 4, 8, and 12 in Fig. 1)" as mentioned in the paper. It seems like the results have to be taken after every four clock cycles. So, start in can be also used for the following stage to take over the results from the mix column stage. If you have the full sources of that project, there should be some design unit that controlls the datapath. Some kind of FSM. By analysing that you probably gain more detailed insights how the whole thing works. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:10:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.tcx.org.uk!weretis.net!feeder4.news.weretis.net!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!d12g2000vbz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Wake process - Quartus II Date: Thu, 27 Jan 2011 06:10:24 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <5b441a12-1fc2-4673-acd5-4dd85a19c0af@k22g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296137424 24022 127.0.0.1 (27 Jan 2011 14:10:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 27 Jan 2011 14:10:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d12g2000vbz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4661 On Jan 26, 5:57 am, pbartosz wrote: > I have a sample code: > > variable state : integer := 0; > > process (wake) > begin > if state = 0 then > --some code; > state := 1; > wake <= not wake; > elsif state = 1 then > --some code; > end if; > end process; > > In ModelSim simulation it works correct, but in Quartus II simulation > when process returns from state 0 it negates wake signal but process > doesn't start again. > What's the problem? > Any solution? Like the others have said, your design is flawed because it is not synthesizable. I suggest you draw a block diagram of how you expect the logic to look. Draw boxes for registers and circles or ovals for logic with the equations or a description inside. Include some level of detail such as register enables. Look up synthesis templates for registers and copy that to your program for all of the registers. Describe the logic in combinatorial processes or concurrent statements. BTW, don't be afraid to label your processes. This can help in analyzing simulations and synthesis. Rick From newsfish@newsfish Fri Feb 3 13:10:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!k14g2000pre.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 06:22:19 -0800 (PST) Organization: http://groups.google.com Lines: 15 Message-ID: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296138140 30578 127.0.0.1 (27 Jan 2011 14:22:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 27 Jan 2011 14:22:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k14g2000pre.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14231 comp.lang.vhdl:4662 comp.lang.verilog:2773 This is the first project I've done in Verilog in many years. With a long history in VHDL I have a new perspective and am seeing Verilog in a different way. I am finding some of the differences to be pretty interesting actually. I've already commented on the lack of the wildcard sensitivity only to find that VHDL has recently added this. Now I am learning how Verilog allows hierarchical path references to signals for test benches. This is awesome!!! I would love to have had this in Verilog. It is such a PITA to have to bring every generic or debug signal to the top of a design just to support a test bench. ... or did I miss something again? Rick From newsfish@newsfish Fri Feb 3 13:10:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!newsfeed01.sul.t-online.de!newsfeed00.sul.t-online.de!t-online.de!kanaga.switch.ch!switch.ch!newsfeed-00.mathworks.com!news.mathworks.com!not-for-mail From: Tim McBrayer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 09:50:41 -0500 Organization: The MathWorks, Inc. Lines: 23 Message-ID: References: NNTP-Posting-Host: tmcbraye-deb5-64.dhcp.mathworks.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: fred.mathworks.com 1296139841 16029 144.212.115.51 (27 Jan 2011 14:50:41 GMT) X-Complaints-To: news@mathworks.com NNTP-Posting-Date: Thu, 27 Jan 2011 14:50:41 +0000 (UTC) User-Agent: Mozilla-Thunderbird 2.0.0.24 (X11/20100329) In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:14234 comp.lang.vhdl:4663 comp.lang.verilog:2774 rickman wrote: > This is the first project I've done in Verilog in many years. With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. Now I am learning how Verilog > allows hierarchical path references to signals for test benches. This > is awesome!!! I would love to have had this in Verilog. It is such a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. > > ... or did I miss something again? Yep; VHDL 2008 added External Names (P1076-2008, section 8.7), which I believe are the moral equivalent of Verilog hierarchical references. Google's first hit on them: http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/#hierarchicalnames -- Tim McBrayer MathWorks From newsfish@newsfish Fri Feb 3 13:10:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.nobody.at!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe14.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog References: In-Reply-To: Subject: Re: Wow! No TestbenchWow! Lines: 1 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 15.4.3508.1109 X-MimeOLE: Produced By Microsoft MimeOLE V15.4.3508.1109 X-Antivirus: avast! (VPS 110127-0, 27/01/2011), Outbound message X-Antivirus-Status: Clean Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe14.ams2 1296140102 213.105.6.183 (Thu, 27 Jan 2011 14:55:02 UTC) NNTP-Posting-Date: Thu, 27 Jan 2011 14:55:02 UTC Organization: virginmedia.com Date: Thu, 27 Jan 2011 14:54:40 -0000 Xref: feeder.eternal-september.org comp.arch.fpga:14235 comp.lang.vhdl:4664 comp.lang.verilog:2775 "rickman" wrote in message news:f8d79600-a7d4-4c5b-b5d3-655122ad1124@k14g2000pre.googlegroups.com... .. I've already commented on the lack of the wildcard sensitivity only to find that VHDL has recently added this. Now I am learning how Verilog allows hierarchical path references to signals for test benches. This is awesome!!! I would love to have had this in Verilog. It is such a PITA to have to bring every generic or debug signal to the top of a design just to support a test bench. ... or did I miss something again? Yes, VHDL2008 supports hierarchical references (works fine in Modelsim 10.0), before that you had SignalSpy and many other custom solutions to this issue. <> <= force "011"; -- inject error Hans. www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:10:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder7.xlned.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d418f6d$0$81473$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Wow! No TestbenchWow! Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Followup-To: comp.arch.fpga Date: Thu, 27 Jan 2011 16:29:49 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 73 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1296142189 news.xs4all.nl 81473 puiterl/[::ffff:195.242.97.150]:53122 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.arch.fpga:14236 comp.lang.vhdl:4665 comp.lang.verilog:2776 rickman wrote: > This is the first project I've done in Verilog in many years. With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. Now I am learning how Verilog > allows hierarchical path references to signals for test benches. This > is awesome!!! I would love to have had this in Verilog. It is such a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. > > ... or did I miss something again? Yes! ;-) Well, maybe.... For bringing up debug signals to the testbench you can use "global" signals declared in a package. It is not synthesizable (but for debug signals that would not be a problem). Also, the assignment to the global signal has to take place at the location were the object to be observed is visible. Example: PACKAGE pkg IS SIGNAL spy: std_logic_vector(7 DOWNTO 0); END PACKAGE pkg; In the architecture where you want to observe a signal: USE work.pkg.ALL; ARCHITECTURE arch OF design_block IS BEGIN ... spy <= observed_signal; ... END ARCHITECTURE arch; In your testbench: USE work.pkg.ALL; ARCHITECTURE arch OF tb IS BEGIN ... -- spy is visible here, due to the USE statement IF spy = ... -- whatever ... END ARCHITECTURE arch; Another way to do all this is using the new VHDL-2008 feature called "external names". Then you can peek into the DUV every which way you want, without the need of changing DUV code. Example (from the Ashenden/Lewis book: VHDL-2008 just the new stuff): ASSERT <> /= "00000" REPORT "Illegal controller state"; VHDL-2008 also includes FORCE and RELEASE assignments. This means that you don't need simulator dependant commands anymore for forcing signals in the DUT. I have no idea if there already is a simulator that supports these constructs. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:10:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o14g2000prb.googlegroups.com!not-for-mail From: comp arch Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 08:43:41 -0800 (PST) Organization: http://groups.google.com Lines: 24 Message-ID: <683c7702-e7a6-4376-88a7-7d02002a9ed1@o14g2000prb.googlegroups.com> References: NNTP-Posting-Host: 62.221.5.234 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296146622 9567 127.0.0.1 (27 Jan 2011 16:43:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 27 Jan 2011 16:43:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prb.googlegroups.com; posting-host=62.221.5.234; posting-account=807CZgoAAAD1uALwPgCBqmI0V4mIw2qY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14238 comp.lang.vhdl:4666 comp.lang.verilog:2777 On Jan 27, 2:22=A0pm, rickman wrote: > This is the first project I've done in Verilog in many years. =A0With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. =A0I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. =A0Now I am learning how Verilog > allows hierarchical path references to signals for test benches. =A0This > is awesome!!! =A0I would love to have had this in Verilog. =A0It is such = a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. > > ... or did I miss something again? > > Rick I've always thought that it would be nice if FPGA synthesis tools supported the hierarchical path names too. i.e. if you wanted to debug a core with chipscope, you could do assign trig0[0] =3D my_core.some_internal_block.troublesome_node; From newsfish@newsfish Fri Feb 3 13:10:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Sean Durkin Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 20:15:30 +0100 Lines: 41 Message-ID: <8qduk1FbtsU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net /lx4OslqWO5WCa20MvV6NwM1Me3eFAEuI/Fefc/KfZw1jCAz38 Cancel-Lock: sha1:FveGU/rBDQimcaU46iD5eSuvzY0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.arch.fpga:14243 comp.lang.vhdl:4667 comp.lang.verilog:2778 rickman wrote: > This is the first project I've done in Verilog in many years. With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. Now I am learning how Verilog > allows hierarchical path references to signals for test benches. This > is awesome!!! I would love to have had this in Verilog. It is such a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. If you're using ModelSim, there's a library "modelsim_lib" that has a function called "SignalSpy". With that you can access any signal in your design from a test bench. Use it like this: library modelsim_lib; use modelsim_lib.util.all; -- entity, architecture, signal declarations skipped ----------------------------------------------------------------------------- -- spy process ----------------------------------------------------------------------------- sig_spy : process is begin init_signal_spy("/DUT/submodule1/submodule2/interesting_signal", "tb_sig", 1); wait; end process sig_spy; This connects "interesting_signal" to your test bench signal "tb_sig". This is not synthesizable and you have to consider ModelSim's built in optimization, which might optimize away the signal you want to look at during elaboration, but it's a start and works with older VHDL releases. Doesn't work for GENERICs, though... HTH, Sean From newsfish@newsfish Fri Feb 3 13:10:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t13g2000vbo.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 13:23:53 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <8409fbf1-3cd3-41e7-98d7-75f90faf3fe2@t13g2000vbo.googlegroups.com> References: <683c7702-e7a6-4376-88a7-7d02002a9ed1@o14g2000prb.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296163433 31347 127.0.0.1 (27 Jan 2011 21:23:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 27 Jan 2011 21:23:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000vbo.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14247 comp.lang.vhdl:4668 comp.lang.verilog:2779 > I've always thought that it would be nice if FPGA synthesis tools > supported the hierarchical path names too. > i.e. if you wanted to debug a core with chipscope, you could do > > assign trig0[0] = my_core.some_internal_block.troublesome_node; VHDL: I've successfully used signals in packages (global signals) in synthesis (synplify). Declare a signal in a package (I used std_ulogic to try to catch multiple drivers at compile time, but the error(s) came at elaboration...). So at the top entity you "use debug_pkg" and get access to the debug_signal. Just drive it to your output, i.e. debug_pin <= debug_signal; In the lower level entity, also "use debug_pkg" and send your troublesome_node to the debug_signal: debug_signal <= troublesome_node; HTH -- Pont From newsfish@newsfish Fri Feb 3 13:10:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: Wow! No TestbenchWow! Date: Thu, 27 Jan 2011 22:27:01 +0000 Organization: A noiseless patient Spider Lines: 72 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="27857"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19uGLvq0RAOOgkCs9cnd11oAhMNIvGWakI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:iMjenHFWxFTvRcxBP3q4QP+paQc= Xref: feeder.eternal-september.org comp.arch.fpga:14250 comp.lang.vhdl:4669 comp.lang.verilog:2780 On Thu, 27 Jan 2011 06:22:19 -0800 (PST), rickman wrote: > Now I am learning how Verilog >allows hierarchical path references to signals for test benches. This >is awesome!!! Not as awesome as the ability to call tasks (procedures) in a module, from another module. That's just the neatest thing ever, for stimulus generation. This little example should give you a flavour of what you can do: `timescale 1ns/1ns module simulatedUartTransmitter(output reg TxD); time bitTime; // task setBitTime(input time newBitTime); bitTime = newBitTime; endtask task sendChar(input [7:0] char); begin // send start bit TxD = 0; // send eight data bits, LSB first repeat (8) begin #(bitTime) TxD = char[0]; char = char >> 1; end // send stop bit #(bitTime) TxD = 1; #(bitTime); end endtask // initial TxD = 1; // line idles in "Mark" state // endmodule module justTryThisOne; // connections wire serial_TxD; // stimulus generator instance simulatedUartTransmitter txGenerator(.TxD(serial_TxD)); // // There's no DUT in this example, but you can still // see the signal generator at work. // // code to generate some stimulus initial begin txGenerator.setBitTime(104000); // 9600Bd, roughly #1_000_000; // idle awhile before starting txGenerator.sendChar("h"); // ask the sig-gen... txGenerator.sendChar("i"); // ...to send some data txGenerator.sendChar("!"); // ...at our request #1_000_000; // idle awhile at the end end endmodule Utterly fantastic when you want to do stuff like mimicking the behaviour of a CPU in your testbench. Just write a module that can generate read or write cycles on a bus, then connect an instance of it to your DUT and get it to do accesses in the same way you'd expect your CPU to behave. Apologies if this is stuff you've seen already. It's so useful that I couldn't resist sharing the example (again). -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w19g2000yqa.googlegroups.com!not-for-mail From: Rejin James Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Thu, 27 Jan 2011 20:31:16 -0800 (PST) Organization: http://groups.google.com Lines: 232 Message-ID: <4013774f-e2e6-40eb-ba45-87cbdd44e90f@w19g2000yqa.googlegroups.com> References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> NNTP-Posting-Host: 115.242.153.249 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296189076 1325 127.0.0.1 (28 Jan 2011 04:31:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 28 Jan 2011 04:31:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w19g2000yqa.googlegroups.com; posting-host=115.242.153.249; posting-account=sVZi6woAAAALUtg7YjdT9QJbVW4okBS2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1.4) Gecko/20091016 FireDownload/2.0.1 Firefox/3.5.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4670 On Jan 27, 12:29=A0pm, backhus wrote: > On 26 Jan., 13:32, Rejin James wrote: > > > > > On Jan 26, 1:10=A0pm, backhus wrote: > > > > On 25 Jan., 06:49, Rejin James wrote: > > > > > Hi Friends I am currently doin my university project on the topic > > > > Low Power AES algorithm using VHDL > > > > > I was having problems understanding the logic of Mixcolumns operati= on > > > > in GALIOS FIELD and other parts of the algorithm like galios field > > > > multiplication and key expansion. > > > > Can anyone help me out >?? > > > > > this is the base paper im followingwww.martes-itea.org/.../Hamalain= en-Design_and_Implementation_2.pdf > > > > > actually i got the cores from their website and was having a proble= m > > > > in understanding it . > > > > They are using 8- bit data paths and i was having problems in > > > > understanding their architecture and implementation in VHDl. > > > > > The following is the code for mixcolumns operation . can somebody h= elp > > > > me out with it ?? > > > > i was not understanding the GALIOS FIELD multiplication concept. > > > > > library ieee; > > > > use ieee.std_logic_1164.all; > > > > > entity mixcolumns is > > > > =A0 port( > > > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > > > =A0 =A0 start_in =A0 : in =A0std_logic; > > > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' =3D in= verse > > > > transformation > > > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); =A0--= input data > > > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0-- out= put data > > > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0-- out= put data > > > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0-- out= put data > > > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 -- out= put data > > > > =A0 =A0 ); > > > > end mixcolumns; > > > > > -- fwd_rtl =3D forward only > > > > architecture fwd_rtl of mixcolumns is > > > > > =A0 -- GF(2^8) multiplication with constant: x > > > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > > > =A0 =A0 return std_logic_vector is > > > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > > > =A0 begin > > > > =A0 =A0 b(0) :=3D a(7); > > > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > > > =A0 =A0 b(2) :=3D a(1); > > > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > > > =A0 =A0 b(5) :=3D a(4); > > > > =A0 =A0 b(6) :=3D a(5); > > > > =A0 =A0 b(7) :=3D a(6); > > > > =A0 =A0 return b; > > > > =A0 end; > > > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vector(7 = downto > > > > 0); > > > > =A0 signal accum_r : accum_array_t; > > > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0); > > > > > begin =A0-- rtl > > > > > =A0 assert (inverse_in /=3D '1') report "this architecture supports= only > > > > forward operation" > > > > =A0 =A0 severity failure; > > > > =A0 x <=3D data_in; > > > > > =A0 prod2 <=3D gf256_mul2(x); > > > > =A0 prod3 <=3D prod2 xor x; > > > > > =A0 -- forward transform: > > > > =A0 -- > > > > =A0 -- x0 =A0 |02 03 01 01| y0 > > > > =A0 -- x1 =3D |01 02 03 01|*y1 > > > > =A0 -- x2 =A0 |01 01 02 03| y2 > > > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > > > =A0 -- inverse transform > > > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > > > =A0 clocked : process (clk) > > > > =A0 begin =A0-- process clocked > > > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising c= lock edge > > > > =A0 =A0 =A0 if (start_in =3D '1') then > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > > > =A0 =A0 =A0 else > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > > > =A0 =A0 =A0 end if; > > > > =A0 =A0 end if; > > > > =A0 end process clocked; > > > > > =A0 data0_out <=3D accum_r(0); > > > > =A0 data1_out <=3D accum_r(1); > > > > =A0 data2_out <=3D accum_r(2); > > > > =A0 data3_out <=3D accum_r(3); > > > > > end fwd_rtl; > > > > > ANY HELP WOULD BE APPRECIATED .. thanks > > > > Hi, > > > that's a lot of questions at once. :-) > > > Galois Field math is a topic for 10th semester math students. > > > So don't be bothered when it seems complicated to understand. > > > In some VERY simple words: The galois field is a limited bunch of > > > numbers, that obeys defined mathematical rules. > > > This is only possible because he operations can always be seen as > > > modulo operations in order to keep the number space constant. > > > When you chop down the field size to tw0 you can work with simple gat= e > > > functions (AND and XOR) for multiplication and addition. > > > > Mix columns is an ordinary vector/matrix multiplication, where you > > > multiply a row of the input matrix with a given transformation > > > matrix. > > > The result is then written to a column of the result matrix. > > > > The code you provided has one strange property. > > > It takes a single stream of data (data_in) and creates four result > > > values. > > > You need to find out in which order the input stram has to provide th= e > > > data of the input matrix (and when to apply start_in) > > > and what to do with the four result values. > > > > Maybe you should take a look ath this book: > > > The Design of Rijndael: AES. TheAdvanced Encryption Standard > > > Written by the designers of the algorithm. > > > There you find many examples and calculations that you can compare > > > with your simulations, in order to understand how the code works that > > > you have. > > > > Have a nice simulation > > > =A0 Eilert > > > Hey Eilert, > > Thanks a lot for the reply. :-) > > > i went through the galois Field multiplication once more from a book > > on cryptography and got a basic idea as to wat happens in that. > > > The reason dat the code only takes one input is because i am > > implementing Aes algorithm with 8 bit DAta path (data input) > > And according to the paper that i am using the mix columns multiplier > > unit takes in the 8 bit data and produces 32 bit output which is then > > given to a parallel to serial converter. > > > If u cud see the base paper which i was referring once then i guess u > > wud understand it better. Coz i was not able to understand much. > > > And i also understood when to apply start_in. it helps us to control > > operation of mixcolumns for encryption or decryption. > > when start_in is not one it signifies we want to do the inverse > > operation i.e. decryption. > > Hi, > you confused start_in with inverse_in. > Also inverse_in has to be '1' all the time since the code doesn't > suport the inverse transformation. > (Look at the assert statement) > > In the mentioned paper there is a signal mentioned called "en". > That's probably called start_in in the provided source now. > > It has to be applied "During inputting the first byte of a column > (bytes 0, 4, 8, and 12 in Fig. 1)" > as mentioned in the paper. > It seems like the results have to be taken after every four clock > cycles. > So, start in can be also used for the following stage to take over the > results from the mix column stage. > > If you have the full sources of that project, there should be some > design unit that controlls the datapath. > Some kind of FSM. By analysing that you probably gain more detailed > insights how the whole thing works. > > Have a nice synthesis > =A0 Eilert Hi, i think when inverse_in is 1 it means reverse process i.e decryption. it was given as comment somewhere in the full sources. As for start _in i think u are right. But the things mentioned about taking data byte by byte is not making sense to me as the input that we feed is 8-bit(i.e 1 byte) so how come rest of the bytes are coming. And how can one make The state when input is only 8-bit ? Here is the link for the full source. http://www.tkt.cs.tut.fi/research/daci/ra_security_8bit_aes_hw.html Thanks for your help. I did not go through the top level. Ill try to go through it and understand. If u could also just take a look it would be a big help. Thanks Eilert Rejin From newsfish@newsfish Fri Feb 3 13:10:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!s18g2000vbe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Thu, 27 Jan 2011 23:57:44 -0800 (PST) Organization: http://groups.google.com Lines: 338 Message-ID: <9d44362b-281f-4974-8368-c825a3714162@s18g2000vbe.googlegroups.com> References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> <4013774f-e2e6-40eb-ba45-87cbdd44e90f@w19g2000yqa.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296201465 3616 127.0.0.1 (28 Jan 2011 07:57:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 28 Jan 2011 07:57:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s18g2000vbe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4671 On 28 Jan., 05:31, Rejin James wrote: > On Jan 27, 12:29=A0pm, backhus wrote: > > > > > On 26 Jan., 13:32, Rejin James wrote: > > > > On Jan 26, 1:10=A0pm, backhus wrote: > > > > > On 25 Jan., 06:49, Rejin James wrote: > > > > > > Hi Friends I am currently doin my university project on the topic > > > > > Low Power AES algorithm using VHDL > > > > > > I was having problems understanding the logic of Mixcolumns opera= tion > > > > > in GALIOS FIELD and other parts of the algorithm like galios fiel= d > > > > > multiplication and key expansion. > > > > > Can anyone help me out >?? > > > > > > this is the base paper im followingwww.martes-itea.org/.../Hamala= inen-Design_and_Implementation_2.pdf > > > > > > actually i got the cores from their website and was having a prob= lem > > > > > in understanding it . > > > > > They are using 8- bit data paths and i was having problems in > > > > > understanding their architecture and implementation in VHDl. > > > > > > The following is the code for mixcolumns operation . can somebody= help > > > > > me out with it ?? > > > > > i was not understanding the GALIOS FIELD multiplication concept. > > > > > > library ieee; > > > > > use ieee.std_logic_1164.all; > > > > > > entity mixcolumns is > > > > > =A0 port( > > > > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > > > > =A0 =A0 start_in =A0 : in =A0std_logic; > > > > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' =3D = inverse > > > > > transformation > > > > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); =A0= -- input data > > > > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0-- o= utput data > > > > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0-- o= utput data > > > > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0-- o= utput data > > > > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 -- o= utput data > > > > > =A0 =A0 ); > > > > > end mixcolumns; > > > > > > -- fwd_rtl =3D forward only > > > > > architecture fwd_rtl of mixcolumns is > > > > > > =A0 -- GF(2^8) multiplication with constant: x > > > > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > > > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > > > > =A0 =A0 return std_logic_vector is > > > > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > > > > =A0 begin > > > > > =A0 =A0 b(0) :=3D a(7); > > > > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > > > > =A0 =A0 b(2) :=3D a(1); > > > > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > > > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > > > > =A0 =A0 b(5) :=3D a(4); > > > > > =A0 =A0 b(6) :=3D a(5); > > > > > =A0 =A0 b(7) :=3D a(6); > > > > > =A0 =A0 return b; > > > > > =A0 end; > > > > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vector(= 7 downto > > > > > 0); > > > > > =A0 signal accum_r : accum_array_t; > > > > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > > > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0); > > > > > > begin =A0-- rtl > > > > > > =A0 assert (inverse_in /=3D '1') report "this architecture suppor= ts only > > > > > forward operation" > > > > > =A0 =A0 severity failure; > > > > > =A0 x <=3D data_in; > > > > > > =A0 prod2 <=3D gf256_mul2(x); > > > > > =A0 prod3 <=3D prod2 xor x; > > > > > > =A0 -- forward transform: > > > > > =A0 -- > > > > > =A0 -- x0 =A0 |02 03 01 01| y0 > > > > > =A0 -- x1 =3D |01 02 03 01|*y1 > > > > > =A0 -- x2 =A0 |01 01 02 03| y2 > > > > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > > > > =A0 -- inverse transform > > > > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > > > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > > > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > > > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > > > > =A0 clocked : process (clk) > > > > > =A0 begin =A0-- process clocked > > > > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising= clock edge > > > > > =A0 =A0 =A0 if (start_in =3D '1') then > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > > > > =A0 =A0 =A0 else > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > > > > =A0 =A0 =A0 end if; > > > > > =A0 =A0 end if; > > > > > =A0 end process clocked; > > > > > > =A0 data0_out <=3D accum_r(0); > > > > > =A0 data1_out <=3D accum_r(1); > > > > > =A0 data2_out <=3D accum_r(2); > > > > > =A0 data3_out <=3D accum_r(3); > > > > > > end fwd_rtl; > > > > > > ANY HELP WOULD BE APPRECIATED .. thanks > > > > > Hi, > > > > that's a lot of questions at once. :-) > > > > Galois Field math is a topic for 10th semester math students. > > > > So don't be bothered when it seems complicated to understand. > > > > In some VERY simple words: The galois field is a limited bunch of > > > > numbers, that obeys defined mathematical rules. > > > > This is only possible because he operations can always be seen as > > > > modulo operations in order to keep the number space constant. > > > > When you chop down the field size to tw0 you can work with simple g= ate > > > > functions (AND and XOR) for multiplication and addition. > > > > > Mix columns is an ordinary vector/matrix multiplication, where you > > > > multiply a row of the input matrix with a given transformation > > > > matrix. > > > > The result is then written to a column of the result matrix. > > > > > The code you provided has one strange property. > > > > It takes a single stream of data (data_in) and creates four result > > > > values. > > > > You need to find out in which order the input stram has to provide = the > > > > data of the input matrix (and when to apply start_in) > > > > and what to do with the four result values. > > > > > Maybe you should take a look ath this book: > > > > The Design of Rijndael: AES. TheAdvanced Encryption Standard > > > > Written by the designers of the algorithm. > > > > There you find many examples and calculations that you can compare > > > > with your simulations, in order to understand how the code works th= at > > > > you have. > > > > > Have a nice simulation > > > > =A0 Eilert > > > > Hey Eilert, > > > Thanks a lot for the reply. :-) > > > > i went through the galois Field multiplication once more from a book > > > on cryptography and got a basic idea as to wat happens in that. > > > > The reason dat the code only takes one input is because i am > > > implementing Aes algorithm with 8 bit DAta path (data input) > > > And according to the paper that i am using the mix columns multiplier > > > unit takes in the 8 bit data and produces 32 bit output which is then > > > given to a parallel to serial converter. > > > > If u cud see the base paper which i was referring once then i guess u > > > wud understand it better. Coz i was not able to understand much. > > > > And i also understood when to apply start_in. it helps us to control > > > operation of mixcolumns for encryption or decryption. > > > when start_in is not one it signifies we want to do the inverse > > > operation i.e. decryption. > > > Hi, > > you confused start_in with inverse_in. > > Also inverse_in has to be '1' all the time since the code doesn't > > suport the inverse transformation. > > (Look at the assert statement) > > > In the mentioned paper there is a signal mentioned called "en". > > That's probably called start_in in the provided source now. > > > It has to be applied "During inputting the first byte of a column > > (bytes 0, 4, 8, and 12 in Fig. 1)" > > as mentioned in the paper. > > It seems like the results have to be taken after every four clock > > cycles. > > So, start in can be also used for the following stage to take over the > > results from the mix column stage. > > > If you have the full sources of that project, there should be some > > design unit that controlls the datapath. > > Some kind of FSM. By analysing that you probably gain more detailed > > insights how the whole thing works. > > > Have a nice synthesis > > =A0 Eilert > > Hi, > i think when inverse_in is 1 it means reverse process i.e decryption. > it was given as comment somewhere in the full sources. > As for start _in i think u are right. But the things mentioned about > taking data byte by byte is not making sense to me as the input that > we feed is 8-bit(i.e 1 byte) so how come rest of the bytes are coming. > And how can one make The state when input is only 8-bit ? > > Here is the link for the full source.http://www.tkt.cs.tut.fi/research/da= ci/ra_security_8bit_aes_hw.html > > Thanks for your help. > I did not go through the top level. Ill try to go through it and > understand. > If u could also just take a look it would be a big help. > Thanks Eilert > Rejin Hi Rejin, the README file in the sources sais it's only an encryption core, and also the paper mentiones only encryption in the tables. And even the sources say that the inverse algorithm (needed for decryption) is not implemented. So no chance for generating the inverse algorithm. The AES state matrix consists of 16 bytes. So for each operation, 16 bytes have to be provided. This implementation works in a "byteserial" manner, that mewans you have to provide all the bytes on 16 consecutive clock cycles. (The same applies to the key matrix) Look at the main file aes.vhd. there you find the processes control_clocked and control_comb. These are a 2-process implementation of the controlling FSM. The signal sequence_r there counts the state matrix position that's been worked on. Furthermore there's a signal round, that counts the rounds of the AES algorithm. Depending on the data- and keywidth the input data has to iterate 8 to 14 times through the algorithm. (and the fist or last round is treated special, depending wether you do en- or decryption) So, by further analysing this part of the code you can learn how to feed data into the core, and when to read out the results. Maybe you could start with reconstructing the state diagramm from the vhdl source, so you have a graphical point of orientation. Also there are three testbenches. I think you can see how to controll the input data pretty well by looking at this part of the code from aes_tb_test1.vhd: =20 ------------------------------------------------------------------------- -- encrypt =20 ------------------------------------------------------------------------- -- load input for i in 0 to 15 loop wait until falling_edge(clk); inverse_in <=3D '0'; load_in <=3D '1'; data_in <=3D std_logic_vector(to_unsigned(ptext(t)(i), 8)); key_in <=3D std_logic_vector(to_unsigned(key_fwd(t)(i), 8)); end loop; -- i wait until falling_edge(clk); load_in <=3D '0'; start_in <=3D '1'; wait until falling_edge(clk); start_in <=3D '0'; -- compute wait until rising_edge(clk) and busy_out =3D '0'; -- read output & check result wait until falling_edge(clk); unload_in <=3D '1'; for i in 0 to 15 loop wait until rising_edge(clk); assert ctext(t)(i) =3D to_integer(unsigned(data_out)) report "forward failed" severity error; end loop; -- i unload_in <=3D '0'; wait until rising_edge(clk); Have a nice simulation Eilert From newsfish@newsfish Fri Feb 3 13:10:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.tcx.org.uk!cs.uu.nl!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!tudelft.nl!txtfeed1.tudelft.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!o1g2000yqb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Wake process - Quartus II Date: Fri, 28 Jan 2011 09:00:33 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: References: <5b441a12-1fc2-4673-acd5-4dd85a19c0af@k22g2000yqh.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296234033 8152 127.0.0.1 (28 Jan 2011 17:00:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 28 Jan 2011 17:00:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o1g2000yqb.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4672 I'm going to assume this is part of a testbench, and not synthesizable. We need a little more information... What is wake doing? Is something else driving it too? What type is wake (resolved)? How is wake initialized? What happens when the initial value is "not"ed (e.g. not 'X' = 'X' which won't generate an event to retrigger the process) How do you know the process does not start again? What evidence of that are you seeing? Without any wait statements, that process will spend a lot of execution cycles without advancing time (just advancing deltas) while state is 0. Andy From newsfish@newsfish Fri Feb 3 13:10:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Unconstrained integers and synthesis Date: Sat, 29 Jan 2011 17:10:51 +0100 Lines: 68 Message-ID: <8qisgbFhviU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net q55TscjM9260YwdHyKLc+QRAQAO5pTxf47aL9RGRmf7NoODUI= Cancel-Lock: sha1:km/iFWD+qXlrJFuPTRz6CzcgKCY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 Xref: feeder.eternal-september.org comp.lang.vhdl:4673 I have written some code that uses a unconstrained integer and wonder how (and why) it can be synthesized. Here is the code; it is an SPI slave receiver which uses an unconstrained output port. The word size is determined by the instantiation; I connect the 'data_out' signal to an std_logic_vector(11 downto 0). The code works correctly in the target device; I have not yet tried to simulate it. As I said: how is the counter instantiated? Is this valid VHLD or does it rely on some accidential features of xilinx implementation? Would it be better to define the valid range of the integer 'bitcount'? Thanks, Thomas library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity spislave is Port ( sysclock : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR; data_strobe : out STD_LOGIC; sclk : in STD_LOGIC; mosi : in STD_LOGIC; cs : in STD_LOGIC); end spislave; architecture Behavioral of spislave is -- universal spi slave receiver, number of bits is determined by instantiation. signal sclk_pipe : std_logic_vector(1 downto 0); signal data_sr : std_logic_vector(data_out'length-1 downto 0); signal bitcount : integer; -- <===== ????? begin process(sysclock) begin if rising_edge(sysclock) then sclk_pipe(0) <= sclk; sclk_pipe(1) <= sclk_pipe(0); if cs = '1' then -- async reset bitcount <= 0; elsif sclk_pipe = "01" then -- rising edge of SCLK detected: increment bitcount, shift data in bitcount <= bitcount + 1; data_sr <= data_sr(data_sr'length-2 downto 0) & mosi; if bitcount = data_out'length-1 then data_out <= data_sr(data_sr'length-2 downto 0) & mosi; data_strobe <= '1'; else data_strobe <= '0'; end if; end if; end if; end process; end Behavioral; From newsfish@newsfish Fri Feb 3 13:10:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp5-2.free.fr!not-for-mail Date: Sat, 29 Jan 2011 18:38:43 +0100 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis References: <8qisgbFhviU1@mid.individual.net> In-Reply-To: <8qisgbFhviU1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit Lines: 22 Message-ID: <4d4450a2$0$31440$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Jan 2011 18:38:42 MET NNTP-Posting-Host: 82.246.229.10 X-Trace: 1296322722 news-1.free.fr 31440 82.246.229.10:60547 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:4674 Le 29/01/2011 17:10, Thomas Heller a crit : > I have written some code that uses a unconstrained integer > and wonder how (and why) it can be synthesized. Here is the code; > it is an SPI slave receiver which uses an unconstrained output port. > The word size is determined by the instantiation; I connect the > 'data_out' signal to an std_logic_vector(11 downto 0). > The code works correctly in the target device; I have not yet > tried to simulate it. > > As I said: how is the counter instantiated? Is this valid VHLD > or does it rely on some accidential features of xilinx implementation? > Would it be better to define the valid range of the integer 'bitcount'? Hi This is perfectly legal VHDL but bad practice. Either your synthesis tool is dumb and it implemented a 32-bit counter, or it is a bit smarter than that and noticed your integer is actually a natural, or even that it doesn't need to count further than data_out'length-1. Anyway you'd better constrain your signal Nicolas From newsfish@newsfish Fri Feb 3 13:10:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k9g2000yqi.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sat, 29 Jan 2011 15:11:43 -0800 (PST) Organization: http://groups.google.com Lines: 37 Message-ID: <7acf836c-734c-4457-983f-a273d3a59fcb@k9g2000yqi.googlegroups.com> References: <8qisgbFhviU1@mid.individual.net> <4d4450a2$0$31440$426a74cc@news.free.fr> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296342703 21852 127.0.0.1 (29 Jan 2011 23:11:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 29 Jan 2011 23:11:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000yqi.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4675 On Jan 29, 12:38=A0pm, Nicolas Matringe wrote: > Le 29/01/2011 17:10, Thomas Heller a crit : > > > I have written some code that uses a unconstrained integer > > and wonder how (and why) it can be synthesized. Here is the code; > > it is an SPI slave receiver which uses an unconstrained output port. > > The word size is determined by the instantiation; I connect the > > 'data_out' signal to an std_logic_vector(11 downto 0). > > The code works correctly in the target device; I have not yet > > tried to simulate it. > > > As I said: how is the counter instantiated? Is this valid VHLD > > or does it rely on some accidential features of xilinx implementation? > > Would it be better to define the valid range of the integer 'bitcount'? > > Hi > This is perfectly legal VHDL but bad practice. > Either your synthesis tool is dumb and it implemented a 32-bit counter, > or it is a bit smarter than that and noticed your integer is actually a > natural, or even that it doesn't need to count further than > data_out'length-1. > Anyway you'd better constrain your signal > > Nicolas The other advantage of constraining the integer is that it can help you catch errors. It may seem like perfectly good code now, but if you make modifications and are still expecting the counter to run in a given range and it exceeds that range, the simulation will stop and tell you about the error. This can be very useful as it prevents things like unintended counter wraparound which can be hard to debug on a chip! On the other hand, if you want the counter to wrap around, you need to explain that clearly to the tool by using the mod operator when you do the addition. Rick From newsfish@newsfish Fri Feb 3 13:10:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t13g2000vbo.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sat, 29 Jan 2011 17:52:18 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <349b9f93-2411-4f01-bdcf-3a622c666556@t13g2000vbo.googlegroups.com> References: <8qisgbFhviU1@mid.individual.net> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296352338 2697 127.0.0.1 (30 Jan 2011 01:52:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Jan 2011 01:52:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t13g2000vbo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4676 On Jan 29, 11:10=A0am, Thomas Heller wrote: > As I said: how is the counter instantiated? =A0Is this valid VHLD > or does it rely on some accidential features of xilinx implementation? It's valid code, but you're wasting resources because synthesis will build a full 32 bit counter. Since your code is the SPI slave, SCLK and CS are primary inputs so you have no real control over how many SCLKs you'll actually get. You could get 12...or you could get 12,000,000. The bitcount signal depends only on those two inputs, nothing else. All 32 bits will be used in the comparison because those upper XX bits must be checked to make sure they are indeed 0. Nicolas' statement "Either your synthesis tool is dumb and it implemented a 32-bit counter..." is incorrect. Synthesis will generate a full 32 bit counter (not just the 'dumb ones') and it must do so because that is precisely what you described (don't take my word for it, try it yourself and look to see that all 32 bits of bitcount show up...because they are ALL needed in the comparison to see if bitcount has hit the magic number needed). Instead you should make the following changes: - Define bitcount to be "integer range data_out'range" - Change when bitcount is incremented as shown below. This change will prevent bitcount from ever exceeding the specified range. This might not exactly be what you want, since bitcount will stop at "data_out'high-1" rather than "data_out'high", but you get the idea. - You might want to consider what will happen in your code if 'data_out' is connected to a non-zero based vector (i.e. connected to a vector that is "111 downto 100"). Notice how I changed the compare value for bitcount below. > if bitcount =3D data_out'length-1 then (Not data_out'high - 1) > data_out <=3D data_sr(data_sr'length-2 downto 0) & mosi; > data_strobe <=3D '1'; > else > bitcount <=3D bitcount + 1; > data_strobe <=3D '0'; > end if; Left as an exercise for you is to work out what you want data_strobe to do if you do get more than the expected number of SCLKs. Although bitcount will stop incrementing, you might not want to keep data_strobe asserted in that situation. Again, maybe your system is masking this condition, and maybe nothing really needs to be done to guard against it, but you should consider the possibility and make an informed design decision about what to do if the SPI master generates more clocks than you're expecting. Here is a good case where simulation will allow you to really exercise 'unexpected' conditions so that you know what your design will actually do when those conditions occur. One should always simulate first. Synthesis should be done in parallel to give you additional information about your design while your getting the simulation correct. But the first serious synthesis run should occur after you get the simulation running, not the other way around. Doing synthesis first and simulating later is quite possible, many people do it, but I've found that this tends to lead to 'fragile' designs where 'fragile' means that yes it works when the rest of the system behaves as expected, but when some condition that wasn't considered occurs, the design does something totally unreasonable. Better to have a robust design, many times it doesn't have any real device resource cost. > Would it be better to define the valid range of the integer 'bitcount'? Always define the range of any integers, without exception. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:10:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.x-privat.org!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!k38g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sat, 29 Jan 2011 17:57:51 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <4097a9df-cd19-4e99-b665-93d5e187ff3c@k38g2000vbn.googlegroups.com> References: <8qisgbFhviU1@mid.individual.net> <4d4450a2$0$31440$426a74cc@news.free.fr> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296352672 14948 127.0.0.1 (30 Jan 2011 01:57:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Jan 2011 01:57:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k38g2000vbn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4677 On Jan 29, 12:38=A0pm, Nicolas Matringe wrote: > Either your synthesis tool is dumb and it implemented a 32-bit counter, > or it is a bit smarter than that and noticed your integer is actually a > natural, or even that it doesn't need to count further than > data_out'length-1. There is no information in the design that the synthesis tool could use to infer that the counter would never exceed data_out'length-1. The primary inputs of CS and SCLK are (presumably) off chip and come from some device that could very well generate lotza clockz. A full 32 bit counter would be generated. Where bitcount is used in the comparison, the upper bits above data_out'high would have to be checked to insure that they are 0. The way bitcount is defined in the OP's code, there is nothing preventing bitcount from exceeding the range of data_out. > Anyway you'd better constrain your signal > Yep Kevin Jennings From newsfish@newsfish Fri Feb 3 13:10:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!w7g2000pre.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sun, 30 Jan 2011 01:06:34 -0800 (PST) Organization: http://groups.google.com Lines: 83 Message-ID: References: <8qisgbFhviU1@mid.individual.net> NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296378394 8651 127.0.0.1 (30 Jan 2011 09:06:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Jan 2011 09:06:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w7g2000pre.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Linux; U; Android 2.2; en-au; HTC Legend Build/FRF91) AppleWebKit/533.1 (KHTML, like Gecko) Version/4.0 Mobile Safari/533.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4678 Why don't you have the process clocked by the serial clock then resync the strobe? This will require an additional clock domain but means your serial clock is not used as a flip flop input. Darrin havOn Jan 30, 3:10=A0am, Thomas Heller wrote: > I have written some code that uses a unconstrained integer > and wonder how (and why) it can be synthesized. =A0Here is the code; > it is an SPI slave receiver which uses an unconstrained output port. > The word size is determined by the instantiation; I connect the > 'data_out' signal to an std_logic_vector(11 downto 0). > The code works correctly in the target device; I have not yet > tried to simulate it. > > As I said: how is the counter instantiated? =A0Is this valid VHLD > or does it rely on some accidential features of xilinx implementation? > Would it be better to define the valid range of the integer 'bitcount'? > > Thanks, > Thomas > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > > entity spislave is > =A0 =A0 =A0Port ( sysclock : in STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0 data_out : out STD_LOGIC_VECTOR; > =A0 =A0 =A0 =A0 =A0 =A0 data_strobe : out STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0 sclk : in =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0 mosi : in =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0 cs : in =A0STD_LOGIC); > end spislave; > > architecture Behavioral of spislave is > > -- universal spi slave receiver, number of bits is determined by > instantiation. > > signal sclk_pipe : std_logic_vector(1 downto 0); > signal data_sr : std_logic_vector(data_out'length-1 downto 0); > signal bitcount : integer; =A0 -- <=3D=3D=3D=3D=3D ????? > > begin > > =A0 =A0process(sysclock) > =A0 =A0begin > =A0 =A0 =A0if rising_edge(sysclock) then > > =A0 =A0 =A0 =A0sclk_pipe(0) <=3D sclk; > =A0 =A0 =A0 =A0sclk_pipe(1) <=3D sclk_pipe(0); > > =A0 =A0 =A0 =A0if cs =3D '1' then > =A0 =A0 =A0 =A0 =A0-- async reset > =A0 =A0 =A0 =A0 =A0bitcount <=3D 0; > =A0 =A0 =A0 =A0elsif sclk_pipe =3D "01" then > =A0 =A0 =A0 =A0 =A0-- rising edge of SCLK detected: increment bitcount, s= hift data in > =A0 =A0 =A0 =A0 =A0bitcount <=3D bitcount + 1; > =A0 =A0 =A0 =A0 =A0data_sr <=3D data_sr(data_sr'length-2 downto 0) & mosi= ; > > =A0 =A0 =A0 =A0 =A0if bitcount =3D data_out'length-1 then > =A0 =A0 =A0 =A0 =A0 =A0data_out <=3D data_sr(data_sr'length-2 downto 0) &= mosi; > =A0 =A0 =A0 =A0 =A0 =A0data_strobe <=3D '1'; > =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0data_strobe <=3D '0'; > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0end if; > =A0 =A0end process; > > end Behavioral; > From newsfish@newsfish Fri Feb 3 13:10:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sun, 30 Jan 2011 11:23:16 +0100 Lines: 11 Message-ID: <8qksgkFrnhU1@mid.individual.net> References: <8qisgbFhviU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net EiT+jW+l1JdYzw/MgWCpegm1BRDc+tlV7j6iUcfALjZu22/+k= Cancel-Lock: sha1:3aq74W8q+uIfWBcamUjhPHQsIC8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4679 Am 30.01.2011 10:06, schrieb Dal: > Why don't you have the process clocked by the serial clock then resync > the strobe? Because the way I do it there is a little noise immunity. > This will require an additional clock domain but means your serial > clock is not used as a flip flop input. I see no problem with that. Thomas From newsfish@newsfish Fri Feb 3 13:10:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!tudelft.nl!txtfeed1.tudelft.nl!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!o18g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Sun, 30 Jan 2011 05:08:08 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <14f4637b-d04d-4b95-a2a1-02c7cb804838@o18g2000prh.googlegroups.com> References: <8qisgbFhviU1@mid.individual.net> <349b9f93-2411-4f01-bdcf-3a622c666556@t13g2000vbo.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296392889 22691 127.0.0.1 (30 Jan 2011 13:08:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Jan 2011 13:08:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000prh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4680 On Jan 29, 8:52=A0pm, KJ wrote: Ignore part of previous post where I said "Notice how I changed the compare value for bitcount below", that part was correct in the OP. Also, the range of bitcount should be "0 to data_out'length - 1" not "data_out'range" to accomodate non-zero based vectors KJ From newsfish@newsfish Fri Feb 3 13:10:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!m27g2000prj.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: CFP: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 30 Jan 2011 10:08:20 -0800 (PST) Organization: http://groups.google.com Lines: 293 Message-ID: <5bef9d54-506b-4cd6-8dff-bfbee43fc1b5@m27g2000prj.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296410901 24127 127.0.0.1 (30 Jan 2011 18:08:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Jan 2011 18:08:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m27g2000prj.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:154146 sci.electronics.cad:7108 sci.electronics.misc:3658 sci.engr.semiconductors:752 comp.lang.vhdl:4681 CALL FOR PAPERS and Call For Workshop/Session Proposals MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods Date and Location: July 18-21, 2011, USA http://www.world-academy-of-science.org/ Location: See the above web site for venue/city You are invited to submit a full paper for consideration. All accepted papers will be published in the MSV conference proceedings (in printed book form; later, the proceedings will also be accessible online). Those interested in proposing workshops/sessions, should refer to the relevant sections that appear below. SCOPE: Topics of interest include, but are not limited to, the following: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: To see the DBLP list of accepted papers of MSV 2009, go to: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2009.html The DBLP list of accepted papers of MSV 2010 will soon appear at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html MSV 2011 URL: http://www.world-academy-of-science.org/worldcomp11/ws/conferences/msv11 IMPORTANT DATES: March 10, 2011: Submission of papers (about 5 to 7 pages) April 03, 2011: Notification of acceptance (+/- two days) April 24, 2011: Final papers + Copyright/Consent + Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) ACADEMIC CO-SPONSORS: Currently being prepared - The Academic sponsors of the last offering of MSV (2010) included research labs and centers affiliated with (a partial list): University of California, Berkeley; University of Southern California; University of Texas at Austin; Harvard University, Cambridge, Massachusetts; Georgia Institute of Technology, Georgia; Emory University, Georgia; University of Minnesota; University of Iowa; University of North Dakota; NDSU-CIIT Green Computing & Comm. Lab.; University of Siegen, Germany; UMIT, Austria; SECLAB (University of Naples Federico II + University of Naples Parthenope + Second University of Naples, Italy); National Institute for Health Research; World Academy of Biomedical Sciences and Technologies; Russian Academy of Sciences, Russia; International Society of Intelligent Biological Medicine (ISIBM); The International Council on Medical and Care Compunetics; Eastern Virginia Medical School & the American College of Surgeons, USA. SUBMISSION OF PAPERS: Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by March 10, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) that the paper is being submitted for consideration must be stated on the first page. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject) - often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/philosophical papers will not be refereed but may be considered for discussion/panels). All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering & Technology, DBLP / CS Bibliography, and others. The printed proceedings will be available for distribution on site at the conference. In addition to the publication of the proceedings, selected authors will be invited to submit extended versions of their papers for publication in a number of research books being proposed/contracted with various publishers (such as, Springer, Elsevier, ...) - these books would be composed after the conference. Also, many chairs of sessions and workshops will be forming journal special issues to be published after the conference. MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES: The members of the Steering Committee of The 2010 congress included: Dr. Selim Aissi (Chief Strategist, Intel Corporation, USA); Prof. Hamid Arabnia (ISIBM Fellow & Professor, University of Georgia; Associate Editor, IEEE Transactions on Information Technology in Biomedicine; Editor-in-Chief, Journal of Supercomputing, Springer; Advisory Board, IEEE TC on Scalable Computing); Prof. Ruzena Bajcsy (Member, National Academy of Engineering, IEEE Fellow, ACM Fellow, Professor; University of California, Berkeley, USA); Prof. Hyunseung Choo (ITRC Director of Ministry of Information & Communication; Director, ITRC; Director, Korea Information Processing Society; Assoc. Editor, ACM Transactions on Internet Technology; Professor, Sungkyunkwan University, Korea); Prof. Winston Wai-Chi Fang (IEEE Fellow, TSMC Distinguished Chair Professor, National ChiaoTung University, Hsinchu, Taiwan, ROC); Prof. Andy Marsh (Director HoIP, Secretary-General WABT; Vice-president ICET and ICMCC, Visiting Professor, University of Westminster, UK); Dr. Rahman Tashakkori (Director, S-STEM NSF Supported Scholarship Program and NSF Supported AUAS, Appalachian State U., USA); Prof. Layne T. Watson (IEEE Fellow, NIA Fellow, ISIBM Fellow, Fellow of The National Institute of Aerospace, Virginia Polytechnic Institute & State University, USA); and Prof. Lotfi A. Zadeh (Member, National Academy of Engineering; IEEE Fellow, ACM Fellow, AAAS Fellow, AAAI Fellow, IFSA Fellow; Director, BISC; Professor, University of California, Berkeley, USA). The list of Program Committee of MSV 2010 appears at: http://www.world-academy-of-science.org/worldcomp10/ws/conferences/msv10/committee The MSV 2011 program committee is currently being compiled. Many who have already joined the committee are renowned leaders, scholars, researchers, scientists and practitioners of the highest ranks; many are directors of research labs., members of National Academy of Engineering, fellows of various societies, heads/chairs of departments, program directors of research funding agencies, deans and provosts as well as members of chapters of World Academy of Science. Program Committee members are expected to have established a strong and documented research track record. Those interested in joining the Program Committee should email editor@world-comp.org the following information for consideration/evaluation: Name, affiliation and position, complete mailing address, email address, a one-page biography that includes research expertise and the name of the conference (ie, MSV 2011) offering to help with. GENERAL INFORMATION: MSV conference is an important track of a federated research conference. It is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,000 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different branches of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub- disciplines. PROPOSAL FOR ORGANIZING SESSIONS/WORKSHOPS: Each session will have at least 6 paper presentations from different authors (12 papers in the case of workshops). The session chairs will be responsible for all aspects of their sessions; including, soliciting papers, reviewing, selecting, ... The names of session chairs will appear as Associate Editors in the conference proceedings and on the cover of the books. Proposals to organize sessions should include the following information: name and address (+ email) of proposer, his/her biography, title of session, a 100-word description of the topic of the session, the name of the conference the session is submitted for consideration (ie, MSV), and a short description on how the session will be advertised (in most cases, session proposers solicit papers from colleagues and researchers whose work is known to the session proposer). email your session proposal to editor@world-comp.org We would like to receive the session proposals as soon as possible. NEWS: Thanks to authors and speakers of last WORLDCOMP congress and members of the editorial boards who informed us of the following good news: According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" and specific information extracted from it (in reference to WORLDCOMP's individual conferences' names/acronyms and tracks) from the link below: http://www.worldacademyofscience.org/worldcomp10/ws/news From newsfish@newsfish Fri Feb 3 13:10:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Association list in component instantiations Date: Sun, 30 Jan 2011 19:25:38 +0100 Lines: 34 Message-ID: <8qlop2F19bU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net gAXFss/eX97QYqIDkijd5g1+D1PhcsAPCX5bIazQ4IV6WulPk= Cancel-Lock: sha1:oeOG+TTf6Qeyz7T3gpGjn1vMebY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 Xref: feeder.eternal-september.org comp.lang.vhdl:4682 I do not understand what I can use in the association list of a component instantiation. Say, I have a component declaration like this: entity spislave is Port ( sysclock : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR(7 downto 0); data_strobe : out STD_LOGIC; sclk : in STD_LOGIC; mosi : in STD_LOGIC; cs : in STD_LOGIC); end spislave; Then a typical instantiation is: U1: spislave PORT MAP( sysclock => clk64, data_out => spi_data, data_strobe => spi_strobe, sclk => spi_clk, mosi => spi_mosi, cs => spi_cs ); If I want to connect the data_out signal to parts of a databus then I cannot write data_out => data_bus(7 downto 0), although I can write sclk => not pin_7; Can someone point me to a reference that explains which kind of 'things' I can use in the instantiation? Thanks, Thomas From newsfish@newsfish Fri Feb 3 13:10:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Sun, 30 Jan 2011 21:09:24 +0000 Organization: A noiseless patient Spider Lines: 65 Message-ID: References: <8qlop2F19bU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="28125"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ufZd3LK5VJP/vfaHQxyU7vgmRl+vBwX0=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:09lJQTX5jDIva8jeGFRupuQNZ34= Xref: feeder.eternal-september.org comp.lang.vhdl:4683 On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote: >I do not understand what I can use in the association list of a >component instantiation. Say, I have a component declaration like this: > >entity spislave is > Port ( sysclock : in STD_LOGIC; > data_out : out STD_LOGIC_VECTOR(7 downto 0); > data_strobe : out STD_LOGIC; > sclk : in STD_LOGIC; > mosi : in STD_LOGIC; > cs : in STD_LOGIC); >end spislave; > >Then a typical instantiation is: > > U1: spislave PORT MAP( > sysclock => clk64, > data_out => spi_data, > data_strobe => spi_strobe, > sclk => spi_clk, > mosi => spi_mosi, > cs => spi_cs > ); > >If I want to connect the data_out signal to parts of a databus then >I cannot write > data_out => data_bus(7 downto 0), Why not? Works for me. Who's complaining? Did you *really* say (7 downto 0), or was there something non-static going on in your slice range? >although I can write > sclk => not pin_7; That's slightly different; the actual association can be any monadic function of a signal. This was done to allow for type conversions in the port map, but it works for any monadic function and the "not" operator is, of course, nothing more than the monadic function function "not"(v: in std_logic) return std_logic; >Can someone point me to a reference that explains which kind of 'things' >I can use in the instantiation? For an input port: signals or slices thereof; expressions yielding a constant value. For an output or inout port: signals or slices thereof. Conversion functions can be applied: they must be monadic, and the syntax is different for input and output ports: port map (some_input => F1(in_sig), F2(some_output) => out_sig, F3out(some_inout) => F3in(io_sig)) The actual must be a "static name" but that should be OK... In VHDL-2008 you can put arbitrary expressions to an input port, but your port will suffer an added delta cycle delay from the implied process that computes the expression. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!nx01.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!PRIMUS.CA-a2nVz4C4Vq3uM!not-for-mail From: legg Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Re: CFP: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 30 Jan 2011 20:33:31 -0500 Message-ID: References: <5bef9d54-506b-4cd6-8dff-bfbee43fc1b5@m27g2000prj.googlegroups.com> X-Newsreader: Forte Agent 4.2/32.1118 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@usenetserver.com Organization: UseNetServer.com Lines: 17 X-Trace: 621ca4d4610dd86b241305173 Xref: feeder.eternal-september.org sci.electronics.design:154218 sci.electronics.cad:7109 sci.electronics.misc:3659 sci.engr.semiconductors:753 comp.lang.vhdl:4684 On Sun, 30 Jan 2011 10:08:20 -0800 (PST), "A. M. G. Solo" wrote: > CALL FOR PAPERS > and > Call For Workshop/Session Proposals > > MSV'11 > The 2011 International Conference on Modeling, > Simulation and Visualization Methods > > Date and Location: July 18-21, 2011, USA > > http://www.world-academy-of-science.org/ > Location: See the above web site for venue/city Las Vegas. From newsfish@newsfish Fri Feb 3 13:10:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.supernews.com!news.supernews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 30 Jan 2011 19:54:55 -0600 From: John Larkin Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Re: CFP: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 30 Jan 2011 17:54:56 -0800 Message-ID: References: <5bef9d54-506b-4cd6-8dff-bfbee43fc1b5@m27g2000prj.googlegroups.com> X-Newsreader: Forte Agent 1.91/32.564 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 25 X-Trace: sv3-OYwHJ3F4lDPN/Kkc5oqGaNMp08HFrnNoZVPJxMoHw3W/fOmwmrQsKU/hCxliwl3qb6TCp/uTysW+YGo!6HaaEmV3VeVggACfv6MJThPHi2XF3B2KpByzWSks0C/+C92FBl1oRFnmQGY78sU216Rf71m+klf5!wut/fQ== X-Complaints-To: www.supernews.com/docs/abuse.html X-DMCA-Complaints-To: www.supernews.com/docs/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1985 Xref: feeder.eternal-september.org sci.electronics.design:154225 sci.electronics.cad:7110 sci.electronics.misc:3660 sci.engr.semiconductors:754 comp.lang.vhdl:4685 On Sun, 30 Jan 2011 20:33:31 -0500, legg wrote: >On Sun, 30 Jan 2011 10:08:20 -0800 (PST), "A. M. G. Solo" > wrote: > >> CALL FOR PAPERS >> and >> Call For Workshop/Session Proposals >> >> MSV'11 >> The 2011 International Conference on Modeling, >> Simulation and Visualization Methods >> >> Date and Location: July 18-21, 2011, USA >> >> http://www.world-academy-of-science.org/ >> Location: See the above web site for venue/city > >Las Vegas. Yuk! What an awful place. John From newsfish@newsfish Fri Feb 3 13:10:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Rich Grise Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Re: CFP: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Followup-To: sci.electronics.design Date: Sun, 30 Jan 2011 22:22:15 -0800 Organization: As Little as Possible Lines: 35 Message-ID: References: <5bef9d54-506b-4cd6-8dff-bfbee43fc1b5@m27g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Injection-Info: mx02.eternal-september.org; posting-host="N1UKalwBQj1T+VLI2nvw0w"; logging-data="21030"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Y8SN02wDUu4WlWbKqGkjeRDL1Sz1rDIc=" User-Agent: KNode/0.10.4 Cancel-Lock: sha1:IIH3rbiFPLWoFXEBbyrNjK26UQA= Xref: feeder.eternal-september.org sci.electronics.design:154254 sci.electronics.cad:7111 sci.electronics.misc:3661 sci.engr.semiconductors:755 comp.lang.vhdl:4686 John Larkin wrote: > On Sun, 30 Jan 2011 20:33:31 -0500, legg wrote: >>On Sun, 30 Jan 2011 10:08:20 -0800 (PST), "A. M. G. Solo" >> wrote: >> >>> CALL FOR PAPERS >>> and >>> Call For Workshop/Session Proposals >>> >>> MSV'11 >>> The 2011 International Conference on Modeling, >>> Simulation and Visualization Methods >>> >>> Date and Location: July 18-21, 2011, USA >>> >>> http://www.world-academy-of-science.org/ >>> Location: See the above web site for venue/city >> >>Las Vegas. > > Yuk! What an awful place. > Agreed. Laughlin is much, much nicer, especially for conventions. I've been to an RV convention there, and the last time I moved from MN to Mexifornia, I stopped off and they were playing one-deck blackjack and you were allowed to touch your cards! I didn't win much, but I don't consider myself much of a gambler - I allocate a certain amount of money, and consider it sort of "the price of admission" to have a little fun playing cards or dice or whatever. It's like Laughlin takes itself less seriously than Vegas. :-) Cheers! Rich From newsfish@newsfish Fri Feb 3 13:10:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.karotte.org!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!o21g2000prn.googlegroups.com!not-for-mail From: Andy Peters Newsgroups: comp.lang.vhdl Subject: numeric_std_unsigned Date: Mon, 31 Jan 2011 08:16:54 -0800 (PST) Organization: http://groups.google.com Lines: 2 Message-ID: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> NNTP-Posting-Host: 63.227.85.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296490614 3107 127.0.0.1 (31 Jan 2011 16:16:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 31 Jan 2011 16:16:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o21g2000prn.googlegroups.com; posting-host=63.227.85.78; posting-account=Layx9AoAAACK4VnidxCRPHXPJwnFs4B0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4687 So, what's the point? People still like to use the old Synopsys libraries and can't be bothered declaring unsigned signals? From newsfish@newsfish Fri Feb 3 13:10:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!z3g2000prz.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Mon, 31 Jan 2011 15:19:00 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: <7d7d33c5-d9d3-4f95-8b1d-6f9be42df167@z3g2000prz.googlegroups.com> References: <8qisgbFhviU1@mid.individual.net> <8qksgkFrnhU1@mid.individual.net> NNTP-Posting-Host: 203.58.241.190 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296515940 7657 127.0.0.1 (31 Jan 2011 23:19:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 31 Jan 2011 23:19:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z3g2000prz.googlegroups.com; posting-host=203.58.241.190; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4688 Having the serial to parallel converter on the serial clock domain allows the serial clock to go up to (and slightly exceed) the system clock frequency. Not an issue if your system clock > 4xserial clock frequency. What is your max sclk frequency? It also has the advantage of not having jittery setup and hold times which can also be covered by STA. As this is for an FPGA having deterministic setup/hold is not a issue. If it were for an ASIC it might make characterising setup/hold a little tricky. If you use the same clocking method for serial transmit you would also get a jittery clock to output. Again, not a problem if the serial clock is slow wrt system clock and you don't need constant clock to out times. Have you got an timing constraint on the mosi pin? The pin has two destination flops. One should go in a IOB but the other may go into a slice so could suffer a longish delay. Again not a problem if serial clock is clock is slow and you have lots of timing margin. Still worth a constraint to make sure it doesn't end up on the other side of the device. I also noticed you have used "cs" synchronously. Darrin On Jan 30, 9:23=A0pm, Thomas Heller wrote: > Am 30.01.2011 10:06, schrieb Dal: > > > Why don't you have the process clocked by the serial clock then resync > > the strobe? > > Because the way I do it there is a little noise immunity. > > > This will require an additional clock domain but means your serial > > clock is not used as a flip flop input. > > I see no problem with that. > Thomas From newsfish@newsfish Fri Feb 3 13:10:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!d1g2000yqb.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: VHDL MEMORY MODLELS DESIGNER? Date: Mon, 31 Jan 2011 21:31:28 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <6e9edd2d-beb0-47e5-be2e-cd05afbd0784@d1g2000yqb.googlegroups.com> NNTP-Posting-Host: 109.186.46.235 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296538288 15095 127.0.0.1 (1 Feb 2011 05:31:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Feb 2011 05:31:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d1g2000yqb.googlegroups.com; posting-host=109.186.46.235; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4689 Hi all I have some experience in VHDL based hardware design . I want to work from home as a memeory models designer with VHDL . Is this idea realistic ? How do I go about it if it is ? Thanks EC From newsfish@newsfish Fri Feb 3 13:10:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Petter Gustad Newsgroups: comp.lang.vhdl Subject: Re: VHDL MEMORY MODLELS DESIGNER? Date: Tue, 01 Feb 2011 10:54:24 +0100 Organization: 502 You are not allowed to talk Lines: 14 Sender: newsmailcomp6@gustad.com Message-ID: <87bp2w13n3.fsf@pangea.home.gustad.com> References: <6e9edd2d-beb0-47e5-be2e-cd05afbd0784@d1g2000yqb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Injection-Info: mx03.eternal-september.org; posting-host="yKWtMg7t7nwZ3cJxe+dM5Q"; logging-data="8172"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+TDDU/O1kCr1FEEjPMK5BZ" User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/22.3 (gnu/linux) Cancel-Lock: sha1:NFOfbpO3jpuGGSioTWeIilUfzJI= sha1:nBGK53OvRYeLJZlCNwddWNEL+kc= X-Home-Page: http://gustad.com Xref: feeder.eternal-september.org comp.lang.vhdl:4690 TheRightInfo writes: > I want to work from home as a memeory models designer with VHDL . > Is this idea realistic ? If you can beat Denali at quality/price it could be good business. > How do I go about it if it is ? That's the hard part. //Petter -- .sig removed by request. From newsfish@newsfish Fri Feb 3 13:10:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!p11g2000vbq.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: VHDL MEMORY MODLELS DESIGNER? Date: Tue, 1 Feb 2011 05:55:29 -0800 (PST) Organization: http://groups.google.com Lines: 28 Message-ID: References: <6e9edd2d-beb0-47e5-be2e-cd05afbd0784@d1g2000yqb.googlegroups.com> NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296568529 30379 127.0.0.1 (1 Feb 2011 13:55:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Feb 2011 13:55:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p11g2000vbq.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4691 On Feb 1, 12:31=A0am, TheRightInfo wrote: > Hi all > I have some experience in VHDL based hardware design . > > I want to work from home as a memeory models designer with VHDL . > Is this idea realistic ? > > How do I go about it if it is ? > > Thanks > EC If you're talking about memory models for mass-market memory chips like SDRAM, then you need to contact the companies directly. There is probably a very large market for the use of memory models, but unfortunately (for you) most people are accustomed to getting the models for free from the memory chip vendors. Maybe you could find a niche for VHDL models, since the major chip vendors now supply only Verilog models. However you should realize that customers for these models always have the choice of spending their money on mixed-language simulation and using the well-tested, vendor-supplied Verilog models vs. paying for third-party VHDL models. Just my 2 cents. Gabor From newsfish@newsfish Fri Feb 3 13:10:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.buerger.net!newsfeed00.sul.t-online.de!t-online.de!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!g1g2000prb.googlegroups.com!not-for-mail From: TheRightInfo Newsgroups: comp.lang.vhdl Subject: FPGA BOARD FOR NEWBIE TO FPGA Date: Tue, 1 Feb 2011 23:55:48 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: NNTP-Posting-Host: 93.172.140.79 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296633349 12437 127.0.0.1 (2 Feb 2011 07:55:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 07:55:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g1g2000prb.googlegroups.com; posting-host=93.172.140.79; posting-account=ZzVb6woAAAB0OgSxXntGEEID4PJGH_mq User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4692 Hi all I ned an FPGA bord to practice FPGA with VHDL . That board will hopefully serve me in my first "real" payed FPGA design projects. Can you offer me a not so expensive board please ? Thanks in advance EC From newsfish@newsfish Fri Feb 3 13:10:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!x3g2000yqj.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: FPGA BOARD FOR NEWBIE TO FPGA Date: Wed, 2 Feb 2011 03:19:56 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: <896f43db-41f9-4e66-87b2-be719156891a@x3g2000yqj.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296645596 14194 127.0.0.1 (2 Feb 2011 11:19:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 11:19:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqj.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4693 On Feb 2, 7:55=A0am, TheRightInfo wrote: > Hi all > > I ned an FPGA bord to practice FPGA with VHDL . > > That board will hopefully serve me in my first "real" payed FPGA > design projects. > > Can you offer me a not so expensive board please ? > > Thanks in advance > > EC Its not that simple. different projects will require different FPGAs, different complexities, different features etc. So unless you plan on getting paid to do pretty simple designs, you cant really get away with a single board. From newsfish@newsfish Fri Feb 3 13:10:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Sequential microprocessor code to vhdl - easy conversion tips? Date: Wed, 2 Feb 2011 14:04:04 -0800 (PST) Organization: http://groups.google.com Lines: 49 Message-ID: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 155.198.116.83 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296684244 24276 127.0.0.1 (2 Feb 2011 22:04:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 22:04:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.198.116.83; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4694 Hi, I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): SetPin(A1, HIGH); delay(100ms) SetPin(A1, LOW); delay(10ms) SetPin(A1, HIGH); delay(100ms) for (i=0; i<10; i++) { SetPin(A1, LOW); SetPin(A2, (data>>=1)&1 ); delay(10ms) SetPin(A1, HIGH); delay(12ms) } ... etc. Basically, it's a sequence of actions happening at variable time intervals. How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. One method I thought of: WAIT UNTIL rising_edge(clk); time <= time+1; IF time < 0 THEN A1 <= '1'; END IF; IF time < 100 THEN A1 <= '0'; END IF; IF time < 210 THEN A1 <= '1'; END IF; IF time < 310 THEN A1 <= '0'; END IF; IF time < 310 THEN A2 <= data(0); END IF; IF time < 410 THEN A1 <= '1'; END IF; IF time < 510 THEN A1 <= '0'; END IF; IF time < 510 THEN A2 <= data(1); END IF; IF time < 610 THEN A1 <= '1'; END IF; IF time < 710 THEN A1 <= '0'; END IF; IF time < 710 THEN A2 <= data(2); END IF; etc.... I'm guessing the above logic will lead to a large slow design and messy code... Is there a nice and easy way to do this? Oliver PS. yes I realize there are bugs in both bits of code, but it gets the example across... From newsfish@newsfish Fri Feb 3 13:10:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Conversion of sequential time-sensitive algorithm to VHDL Date: Wed, 2 Feb 2011 14:07:05 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 155.198.116.83 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296684425 11385 127.0.0.1 (2 Feb 2011 22:07:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 22:07:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.198.116.83; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4695 Hi, I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): SetPin(A1, HIGH); delay(100ms) SetPin(A1, LOW); delay(10ms) SetPin(A1, HIGH); delay(100ms) for (i=0; i<10; i++) { SetPin(A1, LOW); SetPin(A2, (data>>=1)&1 ); delay(10ms) SetPin(A1, HIGH); delay(12ms) } ... etc. Basically, it's a sequence of actions happening at variable time intervals. How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. One method I thought of: WAIT UNTIL rising_edge(clk); time <= time+1; IF time > 0 THEN A1 <= '1'; END IF; IF time > 100 THEN A1 <= '0'; END IF; IF time > 210 THEN A1 <= '1'; END IF; IF time > 310 THEN A1 <= '0'; END IF; IF time > 310 THEN A2 <= data(0); END IF; IF time > 410 THEN A1 <= '1'; END IF; IF time > 510 THEN A1 <= '0'; END IF; IF time > 510 THEN A2 <= data(1); END IF; IF time > 610 THEN A1 <= '1'; END IF; IF time > 710 THEN A1 <= '0'; END IF; IF time > 710 THEN A2 <= data(2); END IF; etc.... I'm guessing the above logic will lead to a large slow design and messy code... Is there a nice and easy way to do this? Oliver PS. yes I realize there are bugs in both bits of code, but it gets the example across... From newsfish@newsfish Fri Feb 3 13:10:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Re: FPGA BOARD FOR NEWBIE TO FPGA Date: Wed, 2 Feb 2011 14:33:08 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 155.198.116.83 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296685988 9273 127.0.0.1 (2 Feb 2011 22:33:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 22:33:08 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.198.116.83; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4696 I can recommend one of these: http://cgi.ebay.com/280608972510 and one of these to program it: http://cgi.ebay.com/170576125417 All the software to do stuff is available online free. The FPGA itself is low-end, but that will probably only be a limitation for big designs. Note that this board doesn't come with any peripherals (like audio outputs, tv outputs, sd card slots, ethernet, etc.) - you'll need to find a more expensive board for that. From newsfish@newsfish Fri Feb 3 13:10:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!i40g2000yqh.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Wed, 2 Feb 2011 14:49:12 -0800 (PST) Organization: http://groups.google.com Lines: 107 Message-ID: <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296686953 1915 127.0.0.1 (2 Feb 2011 22:49:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 22:49:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i40g2000yqh.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4697 On Feb 2, 5:07 pm, Oliver Mattos wrote: > Hi, > I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): > > SetPin(A1, HIGH); > delay(100ms) > SetPin(A1, LOW); > delay(10ms) > SetPin(A1, HIGH); > delay(100ms) > for (i=0; i<10; i++) { > SetPin(A1, LOW); > SetPin(A2, (data>>=1)&1 ); > delay(10ms) > SetPin(A1, HIGH); > delay(12ms)} > > ... etc. > > Basically, it's a sequence of actions happening at variable time intervals. > > How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. > > One method I thought of: > > WAIT UNTIL rising_edge(clk); > time <= time+1; > IF time > 0 THEN A1 <= '1'; END IF; > IF time > 100 THEN A1 <= '0'; END IF; > IF time > 210 THEN A1 <= '1'; END IF; > IF time > 310 THEN A1 <= '0'; END IF; > IF time > 310 THEN A2 <= data(0); END IF; > IF time > 410 THEN A1 <= '1'; END IF; > IF time > 510 THEN A1 <= '0'; END IF; > IF time > 510 THEN A2 <= data(1); END IF; > IF time > 610 THEN A1 <= '1'; END IF; > IF time > 710 THEN A1 <= '0'; END IF; > IF time > 710 THEN A2 <= data(2); END IF; > etc.... > > I'm guessing the above logic will lead to a large slow design and messy code... > > Is there a nice and easy way to do this? > > Oliver > > PS. yes I realize there are bugs in both bits of code, but it gets the example across... I don't think that would be so large or slow. You might be able to improve on it a bit by separating the state machine and counter. Your state machine would have 11 or 12 states depending. In each state it waits for the counter to reach zero, then loads a new value into the counter and moves to the next state. Something along that line should do the job. The point is that your compares don't have to be from time zero. Instead they can be relative and you can reuse many of the values rather than having each point a different value. In the loop it is the same two wait values over and over. Take advantage of that, just like you would in software. Also, I would use a case statement rather than a bunch of ifs. The logic produced likely won't be different... no I take that back. In a case statement the tools know that the conditions are mutually exclusive. In the if structure you are using there is a chain of priority and the tools aren't always smart enough to figure out that the conditions are mutually exclusive. procedure RunTimer (IntervalMS : in natural; Enable : in std_logic; CurState : inout natural; TimeCntr : inout natural) is begin if (Enable = '1') then if (TimeCntr = 0) then TimeCntr <= IntervalMS; CurState <= CurState + 1; else TimeCntr <= TimeCntr - 1; end if; end if; end procedure RunTimer; case (CurState) is when 0 => A1 <= '1'; RunTiimer(100, CurState, TimeCntr); when 1 => A1 <= '0'; RunTiimer(10, CurState, TimeCntr); when 2 => A1 <= '1'; RunTiimer(100, CurState, TimeCntr); when 3, 5, 7, 9, 11 => A1 <= '0'; A2 <= data AND 1; RunTiimer(10, CurState, TimeCntr); when 4, 6, 8, 10, 12 => A1 <= '1'; RunTiimer(12, CurState, TimeCntr); when 13 => -- wait for start trigger if (Start = '1') then CurState <= 0; end case; Something like this. You will need a counter to count down to milliseconds to use as an enable for the TimeCntr. And of course, I'm sure the logic doesn't match exactly what you need. Rick From newsfish@newsfish Fri Feb 3 13:10:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n10g2000yqf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Wed, 2 Feb 2011 14:50:38 -0800 (PST) Organization: http://groups.google.com Lines: 4 Message-ID: <9c3671e0-d608-4ff2-9199-22a26ec73e06@n10g2000yqf.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296687038 2614 127.0.0.1 (2 Feb 2011 22:50:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Feb 2011 22:50:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqf.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4698 Oh yeah, don't forget to constrain your integer signals so that they aren't implemented as 32 bits. Rick From newsfish@newsfish Fri Feb 3 13:10:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d1g2000yqb.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Wed, 2 Feb 2011 23:45:34 -0800 (PST) Organization: http://groups.google.com Lines: 62 Message-ID: <90a3b62d-e73a-4aa3-82d3-865207d0b8b6@d1g2000yqb.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296719134 8676 127.0.0.1 (3 Feb 2011 07:45:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 07:45:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d1g2000yqb.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4699 On 2 Feb., 23:07, Oliver Mattos wrote: > Hi, > I have a bit of microprocessor code that looks like this =A0(it's basical= ly bit banging a synchronous serial protocol, with certain timing requireme= nts): > > SetPin(A1, HIGH); > delay(100ms) > SetPin(A1, LOW); > delay(10ms) > SetPin(A1, HIGH); > delay(100ms) > for (i=3D0; i<10; i++) { > =A0 SetPin(A1, LOW); > =A0 SetPin(A2, (data>>=3D1)&1 ); > =A0 delay(10ms) > =A0 SetPin(A1, HIGH); > =A0 delay(12ms)} > > ... etc. > > Basically, it's a sequence of actions happening at variable time interval= s. > > How would you convert this neatly to VHDL? (I have a clock source of know= n frequency) =A0I've thought of various methods involving state machines an= d counters, but they always end up horribly complex. > > One method I thought of: > > WAIT UNTIL rising_edge(clk); > time <=3D time+1; > IF time > 0 THEN A1 <=3D '1'; END IF; > IF time > 100 THEN A1 <=3D '0'; END IF; > IF time > 210 THEN A1 <=3D '1'; END IF; > IF time > 310 THEN A1 <=3D '0'; END IF; > IF time > 310 THEN A2 <=3D data(0); END IF; > IF time > 410 THEN A1 <=3D '1'; END IF; > IF time > 510 THEN A1 <=3D '0'; END IF; > IF time > 510 THEN A2 <=3D data(1); END IF; > IF time > 610 THEN A1 <=3D '1'; END IF; > IF time > 710 THEN A1 <=3D '0'; END IF; > IF time > 710 THEN A2 <=3D data(2); END IF; > etc.... > > I'm guessing the above logic will lead to a large slow design and messy c= ode... > > Is there a nice and easy way to do this? > > Oliver > > PS. yes I realize there are bugs in both bits of code, but it gets the ex= ample across... Hi, why invent a state machine, whan you could use a premade one that is programmable. :-) eg. KCPSM (also known as Picoblaze) Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:10:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo2.news.osn.de!news.osn.de!diablo2.news.osn.de!feeder2-2.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Thu, 3 Feb 2011 08:42:36 -0800 (PST) Organization: http://groups.google.com Lines: 6 Message-ID: <1bfd982b-cb3e-41b2-8706-e3315fd3324e@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 155.198.116.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296751357 32136 127.0.0.1 (3 Feb 2011 16:42:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 16:42:37 +0000 (UTC) In-Reply-To: <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.198.116.106; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4700 Hi, Thanks very much for your responses! I think I'll try both approaches, and see which comes out faster/less area. Thanks Oliver From newsfish@newsfish Fri Feb 3 13:10:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!newsfeed.x-privat.org!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Thu, 03 Feb 2011 17:48:37 +0100 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: VHDL and Sin Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110203-2, 03/02/2011), Outbound message X-Antivirus-Status: Clean Lines: 6 Message-ID: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.245.85.168 X-Trace: 1296751716 reader1.news.tin.it 1356 95.245.85.168:13701 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4701 hello all guys I really need help to write a behavioral and RTL for: e^sin(x) with |x| < 2 any help is appreciate thanks! From newsfish@newsfish Fri Feb 3 13:10:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!news.wiretrip.org!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Thu, 3 Feb 2011 09:20:13 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 155.198.116.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296753614 23210 127.0.0.1 (3 Feb 2011 17:20:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 17:20:14 +0000 (UTC) In-Reply-To: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=155.198.116.106; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4702 What resolution/performance do you need? I'd start with some kind of ROM as a lookup table. To do better than that you'll need to do lots of maths to come up with an iterative algorithm that can come up with the exact result using only basic functions (* + -). From newsfish@newsfish Fri Feb 3 13:10:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.wiretrip.org!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!news2.euro.net!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Chris Maryan Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Thu, 3 Feb 2011 10:43:19 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: <58f7ffab-6e2a-4465-b58a-4a832a78235e@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 204.187.63.106 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296758599 3782 127.0.0.1 (3 Feb 2011 18:43:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 18:43:19 +0000 (UTC) In-Reply-To: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=204.187.63.106; posting-account=X7y8VwoAAABRatUHKb0_XV_h2SmGb2rK User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4703 In order of ease of use: The first thing you should look at is LUTs. Then polynomial or spline approximation. Then specialized algorithms for the exact function you are trying to create (i.e. CORDIC). Chris From newsfish@newsfish Fri Feb 3 13:10:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d17g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Unconstrained integers and synthesis Date: Thu, 3 Feb 2011 11:04:57 -0800 (PST) Organization: http://groups.google.com Lines: 87 Message-ID: References: <8qisgbFhviU1@mid.individual.net> <349b9f93-2411-4f01-bdcf-3a622c666556@t13g2000vbo.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296759898 15788 127.0.0.1 (3 Feb 2011 19:04:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 19:04:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d17g2000vbn.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4704 On Jan 29, 7:52=A0pm, KJ wrote: > On Jan 29, 11:10=A0am, Thomas Heller wrote: > > > As I said: how is the counter instantiated? =A0Is this valid VHLD > > or does it rely on some accidential features of xilinx implementation? > > It's valid code, but you're wasting resources because synthesis will > build a full 32 bit counter. =A0Since your code is the SPI slave, SCLK > and CS are primary inputs so you have no real control over how many > SCLKs you'll actually get. =A0You could get 12...or you could get > 12,000,000. =A0The bitcount signal depends only on those two inputs, > nothing else. =A0All 32 bits will be used in the comparison because > those upper XX bits must be checked to make sure they are indeed 0. > Nicolas' statement "Either your synthesis tool is dumb and it > implemented a 32-bit counter..." is incorrect. =A0Synthesis will > generate a full 32 bit counter (not just the 'dumb ones') and it must > do so because that is precisely what you described (don't take my word > for it, try it yourself and look to see that all 32 bits of bitcount > show up...because they are ALL needed in the comparison to see if > bitcount has hit the magic number needed). > > Instead you should make the following changes: > - Define bitcount to be "integer range data_out'range" > - Change when bitcount is incremented as shown below. =A0This change > will prevent bitcount from ever exceeding the specified range. =A0This > might not exactly be what you want, since bitcount will stop at > "data_out'high-1" rather than "data_out'high", but you get the idea. > - You might want to consider what will happen in your code if > 'data_out' is connected to a non-zero based vector (i.e. connected to > a vector that is "111 downto 100"). =A0Notice how I changed the compare > value for bitcount below. > > > =A0 =A0 =A0 =A0 =A0if bitcount =3D data_out'length-1 then =A0(Not data_= out'high - 1) > > =A0 =A0 =A0 =A0 =A0 =A0data_out <=3D data_sr(data_sr'length-2 downto 0)= & mosi; > > =A0 =A0 =A0 =A0 =A0 =A0data_strobe <=3D '1'; > > =A0 =A0 =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 =A0 =A0 bitcount <=3D bitcount + 1; > > =A0 =A0 =A0 =A0 =A0 =A0data_strobe <=3D '0'; > > =A0 =A0 =A0 =A0 =A0end if; > > Left as an exercise for you is to work out what you want data_strobe > to do if you do get more than the expected number of SCLKs. =A0Although > bitcount will stop incrementing, you might not want to keep > data_strobe asserted in that situation. =A0Again, maybe your system is > masking this condition, and maybe nothing really needs to be done to > guard against it, but you should consider the possibility and make an > informed design decision about what to do if the SPI master generates > more clocks than you're expecting. =A0Here is a good case where > simulation will allow you to really exercise 'unexpected' conditions > so that you know what your design will actually do when those > conditions occur. > > One should always simulate first. =A0Synthesis should be done in > parallel to give you additional information about your design while > your getting the simulation correct. =A0But the first serious synthesis > run should occur after you get the simulation running, not the other > way around. =A0Doing synthesis first and simulating later is quite > possible, many people do it, but I've found that this tends to lead to > 'fragile' designs where 'fragile' means that yes it works when the > rest of the system behaves as expected, but when some condition that > wasn't considered occurs, the design does something totally > unreasonable. =A0Better to have a robust design, many times it doesn't > have any real device resource cost. > > > Would it be better to define the valid range of the integer 'bitcount'? > > Always define the range of any integers, without exception. > > Kevin Jennings The synthesized length of an integer type object is implementation dependent, but must be at least 32 bits unless optimization (e.g. reachability analysis) permits truncation. Every synthesis tool I know of implements an integer as 32 bits (prior to optimization), but that could change at any time, on any tool. There is a difference between the "size" of an unconstrained vector type and of a base integer type. The type Integer is NOT unconstrained, rather it is defined, but implementation specific, with a minimum required numeric value range per the LRM. An unconstrained vector has truly undefined length, and must be defined somewhere in the code (during elaboration), either by the associated signal in an instantiation, or by a default value specification. Andy From newsfish@newsfish Fri Feb 3 13:10:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Thu, 03 Feb 2011 21:49:58 +0100 Lines: 87 Message-ID: <8r0innFdruU1@mid.individual.net> References: <8qlop2F19bU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net mVr4VO2r5P8N18Wtp74XlwI3LbNB1UM+8xHrAYTjW3ebPH79k= Cancel-Lock: sha1:ADG39dkPWDRxwnpxroibbiOjd8M= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4705 Am 30.01.2011 22:09, schrieb Jonathan Bromley: > On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote: > >> I do not understand what I can use in the association list of a >> component instantiation. Say, I have a component declaration like this: >> >> entity spislave is >> Port ( sysclock : in STD_LOGIC; >> data_out : out STD_LOGIC_VECTOR(7 downto 0); >> data_strobe : out STD_LOGIC; >> sclk : in STD_LOGIC; >> mosi : in STD_LOGIC; >> cs : in STD_LOGIC); >> end spislave; >> >> Then a typical instantiation is: >> >> U1: spislave PORT MAP( >> sysclock => clk64, >> data_out => spi_data, >> data_strobe => spi_strobe, >> sclk => spi_clk, >> mosi => spi_mosi, >> cs => spi_cs >> ); >> >> If I want to connect the data_out signal to parts of a databus then >> I cannot write >> data_out => data_bus(7 downto 0), > > Why not? Works for me. Who's complaining? Did you *really* > say (7 downto 0), or was there something non-static going on > in your slice range? I was confused. Of course it works. What I really want and what didn't work is connecting some bits of an input signal on the component (say, the data bus of an ADC) to a signal, and other bits to a constant. Example: X: myinstance PORT MAP( ... data_input => data_bus(7 downto 0) & "00000000", ...) Is it possible to implement this without using another signal, like this: adc_datainput <= data_bus(7 downto 0) & "00000000"; X: myinstance PORT MAP( ... data_input => adc_input, ...) >> although I can write >> sclk => not pin_7; > > That's slightly different; the actual association can be > any monadic function of a signal. This was done to allow > for type conversions in the port map, but it works for > any monadic function and the "not" operator is, of course, > nothing more than the monadic function > function "not"(v: in std_logic) return std_logic; > >> Can someone point me to a reference that explains which kind of 'things' >> I can use in the instantiation? > > For an input port: > signals or slices thereof; expressions yielding a constant value. > For an output or inout port: > signals or slices thereof. > Conversion functions can be applied: they must be monadic, > and the syntax is different for input and output ports: > > port map (some_input => F1(in_sig), > F2(some_output) => out_sig, > F3out(some_inout) => F3in(io_sig)) > > The actual must be a "static name" but that should be OK... > > In VHDL-2008 you can put arbitrary expressions to an input port, > but your port will suffer an added delta cycle delay from the > implied process that computes the expression. > Thanks for this useful info, Thomas From newsfish@newsfish Fri Feb 3 13:10:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Thu, 03 Feb 2011 21:38:13 +0000 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <8qlop2F19bU1@mid.individual.net> <8r0innFdruU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="23450"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Cu/oJMYPZNRa5q4TRqnaSKMTWNsl37OY=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:Kl8oRlP76oX8BVy/xASk6vlfbEY= Xref: feeder.eternal-september.org comp.lang.vhdl:4706 On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote: >What I really want and what didn't work is connecting some bits of an >input signal on the component (say, the data bus of an ADC) to a signal, >and other bits to a constant. Example: > >X: myinstance PORT MAP( > ... > data_input => data_bus(7 downto 0) & "00000000", > ...) > >Is it possible to implement this without using another signal Only in VHDL-2008, as far as I'm aware. Have you tried data_input(15 downto 8) => data_bus(7 downto 0), data_input(7 downto 0) => "00000000" ??? I know you can do that to split a vector port out to several different signals, but I'm not sure whether it's legal to mix constants and signals in that way. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Thu, 03 Feb 2011 21:39:46 +0000 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="23450"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX195Y9G3pJhlXbJGnoxKJVvOoa3Mi/BPm+k=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:si454awXWZ9rbO8NSp0ZQBSlDb8= Xref: feeder.eternal-september.org comp.lang.vhdl:4707 On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: See the other responses. I love the subject line. Sin in VHDL, repent in Verilog? -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Sequential microprocessor code to vhdl - easy conversion tips? Date: Thu, 03 Feb 2011 14:04:57 -0800 Lines: 29 Message-ID: <8r0n3tFbt0U1@mid.individual.net> References: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net MtTdhr/CIJCbvj+b+mEmyQdgNhQeCM4u45OiM3FiHAFR9DlE7z Cancel-Lock: sha1:qMBEXJt9rY25tHl6m/wPssgSxl8= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4708 On 2/2/2011 2:04 PM, Oliver Mattos wrote: > I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): > SetPin(A1, HIGH); > delay(100ms) > SetPin(A1, LOW); > delay(10ms) > SetPin(A1, HIGH); > delay(100ms) > for (i=0; i<10; i++) { > SetPin(A1, LOW); > SetPin(A2, (data>>=1)&1 ); > delay(10ms) > SetPin(A1, HIGH); > delay(12ms) > } > Basically, it's a sequence of actions happening at variable time intervals. > How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. I would write a single clocked process using the 'clock source of known frequency' to do the following at every rising edge: 1. count gets count + 1 2. if rollover count gets zero 3. case count is special, toggle appropriate output. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:10:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!d23g2000prj.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Thu, 3 Feb 2011 15:46:31 -0800 (PST) Organization: http://groups.google.com Lines: 73 Message-ID: <3c1bcfd9-b4bd-494c-9454-34586e6d95cd@d23g2000prj.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 203.58.241.190 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296776792 22126 127.0.0.1 (3 Feb 2011 23:46:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Feb 2011 23:46:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d23g2000prj.googlegroups.com; posting-host=203.58.241.190; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4709 Does this need to be synthesisable? If not, why don't you write a procedure for SetPinA1() and delay()? procedure delay(t : in time) is begin wait for (t); end procedure; procedure SetPinA1(val : std_logic) is begin wait rising_edge(clk); A1 <=3D val; end procedure; Then call from inside a process. Darrin On Feb 3, 9:07=A0am, Oliver Mattos wrote: > Hi, > I have a bit of microprocessor code that looks like this =A0(it's basical= ly bit banging a synchronous serial protocol, with certain timing requireme= nts): > > SetPin(A1, HIGH); > delay(100ms) > SetPin(A1, LOW); > delay(10ms) > SetPin(A1, HIGH); > delay(100ms) > for (i=3D0; i<10; i++) { > =A0 SetPin(A1, LOW); > =A0 SetPin(A2, (data>>=3D1)&1 ); > =A0 delay(10ms) > =A0 SetPin(A1, HIGH); > =A0 delay(12ms)} > > ... etc. > > Basically, it's a sequence of actions happening at variable time interval= s. > > How would you convert this neatly to VHDL? (I have a clock source of know= n frequency) =A0I've thought of various methods involving state machines an= d counters, but they always end up horribly complex. > > One method I thought of: > > WAIT UNTIL rising_edge(clk); > time <=3D time+1; > IF time > 0 THEN A1 <=3D '1'; END IF; > IF time > 100 THEN A1 <=3D '0'; END IF; > IF time > 210 THEN A1 <=3D '1'; END IF; > IF time > 310 THEN A1 <=3D '0'; END IF; > IF time > 310 THEN A2 <=3D data(0); END IF; > IF time > 410 THEN A1 <=3D '1'; END IF; > IF time > 510 THEN A1 <=3D '0'; END IF; > IF time > 510 THEN A2 <=3D data(1); END IF; > IF time > 610 THEN A1 <=3D '1'; END IF; > IF time > 710 THEN A1 <=3D '0'; END IF; > IF time > 710 THEN A2 <=3D data(2); END IF; > etc.... > > I'm guessing the above logic will lead to a large slow design and messy c= ode... > > Is there a nice and easy way to do this? > > Oliver > > PS. yes I realize there are bugs in both bits of code, but it gets the ex= ample across... From newsfish@newsfish Fri Feb 3 13:10:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!d16g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Thu, 3 Feb 2011 22:33:10 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <9978a033-cba7-496a-bd54-c987abb20ed6@d16g2000yqd.googlegroups.com> References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296801190 1850 127.0.0.1 (4 Feb 2011 06:33:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Feb 2011 06:33:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d16g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4710 On Feb 3, 4:39=A0pm, Jonathan Bromley wrote: > On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: > > See the other responses. > > I love the subject line. =A0Sin in VHDL, repent in Verilog? > -- > Jonathan Bromley LOL! From newsfish@newsfish Fri Feb 3 13:10:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!q2g2000pre.googlegroups.com!not-for-mail From: noobie Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Fri, 4 Feb 2011 00:58:49 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <18070e2a-390a-412f-bad6-1ff3c0109250@q2g2000pre.googlegroups.com> References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 122.174.92.44 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296809929 20819 127.0.0.1 (4 Feb 2011 08:58:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Feb 2011 08:58:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000pre.googlegroups.com; posting-host=122.174.92.44; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.237 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4711 On Feb 3, 9:48=A0pm, tommy wrote: > hello all guys > I really need help to write a behavioral and RTL for: > > e^sin(x) with |x| < 2 > > any help is appreciate thanks! Choose either LUT or Taylor series method depending upon the follwoing situations: 1)You want the result in one clock cycle - Use LUT's. 2)You can wait several clock cycles for the output(and you want a high precision for the output) - Use Taylor series. See Taylor series expansion in the following wiki link: http://en.wikipedia.org/wiki/Taylor_series --Vipin Lal From newsfish@newsfish Fri Feb 3 13:10:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Thomas Heller Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Fri, 04 Feb 2011 13:49:26 +0100 Lines: 29 Message-ID: <8r2aupF6r4U1@mid.individual.net> References: <8qlop2F19bU1@mid.individual.net> <8r0innFdruU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net +uwyKAziJr0cgje88lhAcQU/yI270yxE4sUgj1cvRd0TxBue8= Cancel-Lock: sha1:PX0On/72YissBXWEbtH1VgbtWqE= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4712 Am 03.02.2011 22:38, schrieb Jonathan Bromley: > On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote: > >> What I really want and what didn't work is connecting some bits of an >> input signal on the component (say, the data bus of an ADC) to a signal, >> and other bits to a constant. Example: >> >> X: myinstance PORT MAP( >> ... >> data_input => data_bus(7 downto 0)& "00000000", >> ...) >> >> Is it possible to implement this without using another signal > > Only in VHDL-2008, as far as I'm aware. > > Have you tried > > data_input(15 downto 8) => data_bus(7 downto 0), > data_input(7 downto 0) => "00000000" > > ??? I know you can do that to split a vector port out to > several different signals, but I'm not sure whether it's > legal to mix constants and signals in that way. Seems to work. Cool! Thanks, Thomas From newsfish@newsfish Fri Feb 3 13:10:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n18g2000vbq.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Sequential microprocessor code to vhdl - easy conversion tips? Date: Fri, 4 Feb 2011 07:34:31 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: References: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> <8r0n3tFbt0U1@mid.individual.net> NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296833671 26067 127.0.0.1 (4 Feb 2011 15:34:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Feb 2011 15:34:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n18g2000vbq.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4713 On Feb 3, 5:04=A0pm, Mike Treseler wrote: > On 2/2/2011 2:04 PM, Oliver Mattos wrote: > > > > > I have a bit of microprocessor code that looks like this =A0(it's basic= ally bit banging a synchronous serial protocol, with certain timing require= ments): > > SetPin(A1, HIGH); > > delay(100ms) > > SetPin(A1, LOW); > > delay(10ms) > > SetPin(A1, HIGH); > > delay(100ms) > > for (i=3D0; i<10; i++) { > > =A0 =A0SetPin(A1, LOW); > > =A0 =A0SetPin(A2, (data>>=3D1)&1 ); > > =A0 =A0delay(10ms) > > =A0 =A0SetPin(A1, HIGH); > > =A0 =A0delay(12ms) > > } > > Basically, it's a sequence of actions happening at variable time interv= als. > > How would you convert this neatly to VHDL? (I have a clock source of kn= own frequency) =A0I've thought of various methods involving state machines = and counters, but they always end up horribly complex. > > I would write a single clocked process using the > 'clock source of known frequency' to do > the following at every rising edge: > > 1. count gets count + 1 > 2. if rollover count gets zero > 3. case count is special, toggle appropriate output. > > =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Mike Treseler I've seen an interesting use of "subroutines" in a state machine for just this sort of process. The FSM would have a state called "spin" or something like that. From another state, you'd set a signal "time_to_spin" with the number of clock cycles to sit in the "spin" state, and another signal "return_state" with the state to fall into when the spin time expires. Then the "spin" state looks something like: when SPIN =3D> time_to_spin <=3D time_to_spin - 1; if time_to_spin =3D (others =3D> '0') then state <=3D return_state; end if; -- Gabor From newsfish@newsfish Fri Feb 3 13:10:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.nobody.at!news.glorb.com!news2.glorb.com!postnews.google.com!s29g2000pra.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Fri, 4 Feb 2011 08:25:11 -0800 (PST) Organization: http://groups.google.com Lines: 15 Message-ID: References: <8qlop2F19bU1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296836712 23385 127.0.0.1 (4 Feb 2011 16:25:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Feb 2011 16:25:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s29g2000pra.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4714 On Jan 30, 4:09 pm, Jonathan Bromley wrote: > > That's slightly different; the actual association can be > any monadic function of a signal. Why did you use the term "monadic" rather than "unary"? Do I misunderstand the meaning of either or both? It took me five minutes to find a simple definition of "monadic function". That may sound like a pretty short time, but when was the last time you spent five minutes looking for a word definition? "Unary" is a much more common term and I think more clear in this context unless there is some useful connotation to "monadic" I don't appreciate. Rick From newsfish@newsfish Fri Feb 3 13:10:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 4 Feb 2011 10:21:00 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.31.241.144 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1296843660 31781 127.0.0.1 (4 Feb 2011 18:21:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Feb 2011 18:21:00 +0000 (UTC) In-Reply-To: <3c1bcfd9-b4bd-494c-9454-34586e6d95cd@d23g2000prj.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.31.241.144; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4715 Yes - unfortunately stabilizability is a requirement... good plan otherwise though - certainly a minimal effort solution, and thats good :-) From newsfish@newsfish Fri Feb 3 13:10:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Fri, 04 Feb 2011 19:24:20 +0000 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <8qlop2F19bU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="13763"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/sxu4saGEMxRqBNjlKpUI2qCLdA/LTTrw=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:I+YMD1sSpAN9gJcmUVIP9tGPEbU= Xref: feeder.eternal-september.org comp.lang.vhdl:4716 On Fri, 4 Feb 2011 08:25:11 -0800 (PST), rickman wrote: >Why did you use the term "monadic" rather than "unary"? Thanks - that's a bit of jargon that I must have incorrectly absorbed from somewhere. Now you've provoked me into looking, I see that it's not even strictly correct, at least not if you're a mathematician or a (Haskell-style) functional programmer. As you may guess, I am neither. (Side note: some programming languages do tend to use "monadic" and "dyadic" (and even "variadic") to describe the number of arguments of a function. APL is certainly one such. Maybe they're wrong too.) > "Unary" is a much more common term And rigorously accurate too. The style-checker in my head (which usually serves me tolerably well) has no problem with "unary operator", but finds the sound of "unary function" rather strange. Time for a re-calibrate, maybe. Ho hum. Still getting things wrong after all these years :-( -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!a8g2000pri.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 4 Feb 2011 16:49:05 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: <965fe338-b221-487b-8504-e6446d934d02@a8g2000pri.googlegroups.com> References: NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296866945 27325 127.0.0.1 (5 Feb 2011 00:49:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 5 Feb 2011 00:49:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a8g2000pri.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4717 Is the sequence always the same or does can a host change the sequence of events? On Feb 5, 5:21=A0am, Oliver Mattos wrote: > Yes - unfortunately stabilizability is a requirement... > > good plan otherwise though - certainly a minimal effort solution, and tha= ts good :-) From newsfish@newsfish Fri Feb 3 13:10:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k16g2000vbq.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Fri, 4 Feb 2011 16:51:48 -0800 (PST) Organization: http://groups.google.com Lines: 40 Message-ID: <83b50900-e1e5-4983-9b82-a7b5c5bfee49@k16g2000vbq.googlegroups.com> References: igjok69o8jpb4k38l2ugq5h5pm17bua727@4ax.com NNTP-Posting-Host: 64.241.37.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1296867108 28756 127.0.0.1 (5 Feb 2011 00:51:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 5 Feb 2011 00:51:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k16g2000vbq.googlegroups.com; posting-host=64.241.37.140; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4718 On Feb 4, 2:24=A0pm, Jonathan Bromley wrote: > On Fri, 4 Feb 2011 08:25:11 -0800 (PST), rickman =A0wrote: > >Why did you use the term "monadic" rather than "unary"? > > Thanks - that's a bit of jargon that I must have > incorrectly absorbed from somewhere. =A0Now you've > provoked me into looking, I see that it's not even > strictly correct, at least not if you're a > mathematician or a (Haskell-style) functional > programmer. =A0As you may guess, I am neither. > > (Side note: some programming languages do tend to > use "monadic" and "dyadic" (and even "variadic") > to describe the number of arguments of a function. > APL is certainly one such. =A0Maybe they're wrong too.) > > > "Unary" is a much more common term > > And rigorously accurate too. =A0The style-checker > in my head (which usually serves me tolerably well) > has no problem with "unary operator", but finds > the sound of "unary function" rather strange. > Time for a re-calibrate, maybe. > > Ho hum. =A0Still getting things wrong after all > these years :-( I didn't think much of it until I googled "monacdic" and found all sorts of incomprehensible info (at least to me) that only remotely seemed to apply to the context. Not being sure what monadic meant I had to search for awhile until I found one definition which said, "1. unary, when describing an operator or function." I was adding my bias when I said unary is more common. But it seems that monadic is equally correct, but there seems to be some specialized usage in programming languages that was the part I found incomprehensible. Rick From newsfish@newsfish Fri Feb 3 13:10:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Dave Higton Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Sat, 05 Feb 2011 19:32:15 GMT Organization: Home Lines: 22 Message-ID: References: <83b50900-e1e5-4983-9b82-a7b5c5bfee49@k16g2000vbq.googlegroups.com> X-Trace: individual.net cyJfxB/pxEAn8D9kf3gitA/7VWUGnpjidQOh+Sg11MA/5GcJY= X-Orig-Path: dsl.pipex.com%davehigton Cancel-Lock: sha1:Q9rdkI8Uol2Abk+FaQ5BkiKQBbo= User-Agent: Messenger-Pro/3.29 (MsgServe/3.10) (RISC-OS/5.16) NewsHound/v1.50-32 X-Editor: Zap 1.47 (20 Aug 2005) [TEST], ZapEmail 0.27 (21 Mar 2003) test-6 (32) Xref: feeder.eternal-september.org comp.lang.vhdl:4719 In message <83b50900-e1e5-4983-9b82-a7b5c5bfee49@k16g2000vbq.googlegroups.com> rickman wrote: > I didn't think much of it until I googled "monacdic" and found all > sorts of incomprehensible info (at least to me) that only remotely > seemed to apply to the context. Not being sure what monadic meant I > had to search for awhile until I found one definition which said, "1. > unary, when describing an operator or function." > > I was adding my bias when I said unary is more common. But it seems > that monadic is equally correct, but there seems to be some > specialized usage in programming languages that was the part I found > incomprehensible. I remember reading the words "monadic" and "dyadic" for the first time in the Motorola 6809 Preliminary Programmer's Reference Manual. Gosh, that's a long time ago. Dave From newsfish@newsfish Fri Feb 3 13:10:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Sequential microprocessor code to vhdl - easy conversion tips? Date: Sun, 06 Feb 2011 11:16:58 -0800 Lines: 55 Message-ID: <4D4EF3AA.2070308@gmail.com> References: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> <8r0n3tFbt0U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net kOPfVig1Pw74XOJ5kZZ2/gRaD4babl8fagKnbQGiPdHyK/6u3N Cancel-Lock: sha1:w9LJmYtF38+Sx15P5VEWXjFhD6Y= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4720 On 2/4/2011 7:34 AM, Gabor Sz wrote: > On Feb 3, 5:04 pm, Mike Treseler wrote: >> On 2/2/2011 2:04 PM, Oliver Mattos wrote: >> >> >> >>> I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): >>> SetPin(A1, HIGH); >>> delay(100ms) >>> SetPin(A1, LOW); >>> delay(10ms) >>> SetPin(A1, HIGH); >>> delay(100ms) >>> for (i=0; i<10; i++) { >>> SetPin(A1, LOW); >>> SetPin(A2, (data>>=1)&1 ); >>> delay(10ms) >>> SetPin(A1, HIGH); >>> delay(12ms) >>> } >>> Basically, it's a sequence of actions happening at variable time intervals. >>> How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. >> >> I would write a single clocked process using the >> 'clock source of known frequency' to do >> the following at every rising edge: >> >> 1. count gets count + 1 >> 2. if rollover count gets zero >> 3. case count is special, toggle appropriate output. >> >> -- Mike Treseler > > I've seen an interesting use of "subroutines" in a state machine > for just this sort of process. The FSM would have a state called > "spin" or something like that. From another state, you'd > set a signal "time_to_spin" with the number of clock cycles > to sit in the "spin" state, and another signal "return_state" > with the state to fall into when the spin time expires. Then > the "spin" state looks something like: > > when SPIN => > time_to_spin<= time_to_spin - 1; > if time_to_spin = (others => '0') then > state<= return_state; > end if; > > -- Gabor Yes. Nice example. It's ok to have more than one 'state' register. Sometimes structure and syntax gets it the way of logic. And vice versa. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:10:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n16g2000prc.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Mon, 7 Feb 2011 10:29:34 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: <7a4c4ed7-70ba-4ab8-99da-48f7cca2076c@n16g2000prc.googlegroups.com> References: <8qlop2F19bU1@mid.individual.net> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297103375 29327 127.0.0.1 (7 Feb 2011 18:29:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 7 Feb 2011 18:29:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n16g2000prc.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4721 On Feb 4, 1:24=A0pm, Jonathan Bromley wrote: > The style-checker > in my head (which usually serves me tolerably well) > has no problem with "unary operator", but finds > the sound of "unary function" rather strange. > Time for a re-calibrate, maybe. I agree, unary more commonly applies to operators with only one operand. While all operators are functions (in vhdl), not all functions are operators, and perhaps that would be a/the problem. Would "unary function" imply a function that was invoked as a unary operator? What what would be the term for a function with zero arguments? Nonadic? ;^) OK, I did not look up monadic, but I took a lucky guess... and I knew what dyadic meant, which helped a lot. Andy From newsfish@newsfish Fri Feb 3 13:10:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!k15g2000prk.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Mon, 7 Feb 2011 10:39:38 -0800 (PST) Organization: http://groups.google.com Lines: 18 Message-ID: References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297103979 4737 127.0.0.1 (7 Feb 2011 18:39:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 7 Feb 2011 18:39:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k15g2000prk.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4722 On Feb 3, 3:39=A0pm, Jonathan Bromley wrote: > On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: > > See the other responses. > > I love the subject line. =A0Sin in VHDL, repent in Verilog? > -- > Jonathan Bromley Well, there's original sin(), concurrent sin(), sequential (serial?) sin(), procedural sin(), functional sin() Let's not forget monadic err... unary sin() and dyadic sin(). Or just "Go Forth and sin() no more." Andy From newsfish@newsfish Fri Feb 3 13:10:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Mon, 07 Feb 2011 21:42:00 +0000 Organization: A noiseless patient Spider Lines: 7 Message-ID: References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="12749"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/emFCG153hid8w5Uxr4c3fLoAzCF51Mis=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:OWVGib6GiiIs0iZ42m3TpIQDDUk= Xref: feeder.eternal-september.org comp.lang.vhdl:4723 On Mon, 7 Feb 2011 10:39:38 -0800 (PST), Andy wrote: >dyadic sin() That's co-sin, right? Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:10:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w6g2000vbo.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Mon, 7 Feb 2011 14:24:19 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <6b5c4f87-2aa9-4d02-851f-7008ba72dd04@w6g2000vbo.googlegroups.com> References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297117459 4079 127.0.0.1 (7 Feb 2011 22:24:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 7 Feb 2011 22:24:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w6g2000vbo.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4724 On Feb 7, 4:42=A0pm, Jonathan Bromley wrote: > On Mon, 7 Feb 2011 10:39:38 -0800 (PST), Andy wrote: > >dyadic sin() > > That's co-sin, right? > > Jonathan Bromley You two really should get off this tangent. KJ From newsfish@newsfish Fri Feb 3 13:10:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder1.xlned.com!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!bandi.nntp.kabelfoon.nl!198.186.194.249.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!s11g2000yqh.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Mon, 7 Feb 2011 19:39:30 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: <497626dd-49f5-4e58-9346-ec8346c74d21@s11g2000yqh.googlegroups.com> References: <8qlop2F19bU1@mid.individual.net> <7a4c4ed7-70ba-4ab8-99da-48f7cca2076c@n16g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297136370 23984 127.0.0.1 (8 Feb 2011 03:39:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Feb 2011 03:39:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s11g2000yqh.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4725 On Feb 7, 1:29=A0pm, Andy wrote: > On Feb 4, 1:24=A0pm, Jonathan Bromley > wrote: > > > The style-checker > > in my head (which usually serves me tolerably well) > > has no problem with "unary operator", but finds > > the sound of "unary function" rather strange. > > Time for a re-calibrate, maybe. > > I agree, unary more commonly applies to operators with only one > operand. While all operators are functions (in vhdl), not all > functions are operators, and perhaps that would be a/the problem. > Would "unary function" imply a function that was invoked as a unary > operator? > > What what would be the term for a function with zero arguments? > Nonadic? ;^) > > OK, I did not look up monadic, but I took a lucky guess... and I knew > what dyadic meant, which helped a lot. > > Andy Maybe you should have looked up Nonadic... nonadic (comparative more nonadic, superlative most nonadic) 1. of or pertaining to an nonad; ninefold Rick From newsfish@newsfish Fri Feb 3 13:11:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w19g2000yqa.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Mon, 7 Feb 2011 19:40:32 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <93ec3e05-47aa-4c46-9c00-db13a23855ff@w19g2000yqa.googlegroups.com> References: <8qlop2F19bU1@mid.individual.net> <7a4c4ed7-70ba-4ab8-99da-48f7cca2076c@n16g2000prc.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297136432 24624 127.0.0.1 (8 Feb 2011 03:40:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Feb 2011 03:40:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w19g2000yqa.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4726 On Feb 7, 1:29=A0pm, Andy wrote: > On Feb 4, 1:24=A0pm, Jonathan Bromley > wrote: > > > The style-checker > > in my head (which usually serves me tolerably well) > > has no problem with "unary operator", but finds > > the sound of "unary function" rather strange. > > Time for a re-calibrate, maybe. > > I agree, unary more commonly applies to operators with only one > operand. While all operators are functions (in vhdl), not all > functions are operators, and perhaps that would be a/the problem. > Would "unary function" imply a function that was invoked as a unary > operator? > > What what would be the term for a function with zero arguments? > Nonadic? ;^) > > OK, I did not look up monadic, but I took a lucky guess... and I knew > what dyadic meant, which helped a lot. > > Andy Or maybe you should have looked up "unary function"? Rick From newsfish@newsfish Fri Feb 3 13:11:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.x-privat.org!nntp.eutelia.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Tue, 08 Feb 2011 11:20:59 +0100 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110207-0, 07/02/2011), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 79.35.66.119 X-Trace: 1297160458 reader2.news.tin.it 1353 79.35.66.119:4761 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4727 Il 07/02/2011 19:39, Andy ha scritto: > On Feb 3, 3:39 pm, Jonathan Bromley > wrote: >> On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: >> >> See the other responses. >> >> I love the subject line. Sin in VHDL, repent in Verilog? >> -- >> Jonathan Bromley > > Well, there's original sin(), concurrent sin(), sequential (serial?) > sin(), procedural sin(), functional sin() > > Let's not forget monadic err... unary sin() and dyadic sin(). > > Or just "Go Forth and sin() no more." > > Andy I need to write an entity for the approximate calculation of e^sin (x) where x is a number representation in fixed point 2's complement, and | x | <3.14 / 2. my entity will be like this: exp_sin_x entity is port (x: in signed (15 downto 0), y: out signed (15 downto 0), clk: in std_ulogic) end entity; where the type is defined in the package signed IEEE / numeric_std, x must be interpreted as a fixed point number format Q3.13 (i.e. x between -4 and +4) and y as a fixed point number format with Q3.13 (then y lies between -4 and +4)), clk is a clock signal to synchronize operations. First I need a behavioral model and test it with a suitable test-bench. Then I have to write a synthesizable RTL model is tested by comparing the behavioral model. I can approximate both the behavioral and structural model with: e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6 (in the structural relationship, the coefficients are processed in fixed point and the polynomial is calculated using fixed-point operations). thanks again in advance From newsfish@newsfish Fri Feb 3 13:11:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news-peer.in.tum.de!news.belwue.de!newsfeed.ision.net!newsfeed2.easynews.net!ision!newsfeed.arcor.de!newsspool1.arcor-online.net!news.arcor.de.POSTED!not-for-mail Date: Tue, 08 Feb 2011 12:57:32 +0100 From: Gerhard Hoffmann User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 15 Message-ID: <4d512fa9$0$7662$9b4e6d93@newsspool1.arcor-online.net> Organization: Arcor NNTP-Posting-Date: 08 Feb 2011 12:57:29 CET NNTP-Posting-Host: 30f29a99.newsspool1.arcor-online.net X-Trace: DXC=UbNk;kCED1O[kmHKHnaEnMic==]BZ:afN4Fo<]lROoRA<`=YMgDjhgB@=hXjXc:15CGP1Ih[`?MoAcHc<8jl=oPF What resolution/performance do you need? > > I'd start with some kind of ROM as a lookup table. To do better than that you'll need to do lots of maths to come up with an iterative algorithm that can come up with the exact result using only basic functions (* + -). I just have confessed my sin at opencores.org under arith/sincos. If you can afford the block ram/rom you can use that as a starter. Filling the table is in a function and is done in Pascal/C style with floats. regards, Gerhard btw: Is ISE12.4 able to synthesize sfixed/ufixed or are there surprises? From newsfish@newsfish Fri Feb 3 13:11:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!noris.net!newsfeed.arcor.de!newsspool4.arcor-online.net!news.arcor.de.POSTED!not-for-mail Date: Tue, 08 Feb 2011 13:27:23 +0100 From: Gerhard Hoffmann User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d512fa9$0$7662$9b4e6d93@newsspool1.arcor-online.net> In-Reply-To: <4d512fa9$0$7662$9b4e6d93@newsspool1.arcor-online.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 3 Message-ID: <4d5136a8$0$7660$9b4e6d93@newsspool1.arcor-online.net> Organization: Arcor NNTP-Posting-Date: 08 Feb 2011 13:27:20 CET NNTP-Posting-Host: e1660f3e.newsspool1.arcor-online.net X-Trace: DXC=he8HFZ?=OX?D]ncZ]`hZ;1ic==]BZ:af>4Fo<]lROoR1<`=YMgDjhg2LfXBb]\`GL9GP1Ih[`?Mo1cHc<8jl=oP6W_4BNSD_@f4 X-Complaints-To: usenet-abuse@arcor.de Xref: feeder.eternal-september.org comp.lang.vhdl:4729 Ich mach mal die Ingrid: From newsfish@newsfish Fri Feb 3 13:11:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.unit0.net!weretis.net!feeder3.news.weretis.net!feeder.news-service.com!postnews.google.com!y26g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Tue, 8 Feb 2011 08:55:20 -0800 (PST) Organization: http://groups.google.com Lines: 86 Message-ID: <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297184120 4326 127.0.0.1 (8 Feb 2011 16:55:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Feb 2011 16:55:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y26g2000yqd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4730 On Feb 8, 10:20=A0am, tommy wrote: > Il 07/02/2011 19:39, Andy ha scritto: > > > > > On Feb 3, 3:39 pm, Jonathan Bromley > > wrote: > >> On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: > > >> See the other responses. > > >> I love the subject line. =A0Sin in VHDL, repent in Verilog? > >> -- > >> Jonathan Bromley > > > Well, there's original sin(), concurrent sin(), sequential (serial?) > > sin(), procedural sin(), functional sin() > > > Let's not forget monadic err... unary sin() and dyadic sin(). > > > Or just "Go Forth and sin() no more." > > > Andy > > I need to write an entity =A0for the approximate calculation of e^sin (x) > where x is a number representation in fixed point 2's complement, and | > x | <3.14 / 2. > > my entity will be like this: > > =A0 exp_sin_x entity is > =A0 port (x: in signed (15 downto 0), y: out signed (15 downto 0), > =A0 clk: in std_ulogic) > =A0 end entity; > > =A0 where the type is defined in the package signed IEEE / numeric_std, x > must be interpreted as a fixed point number format Q3.13 (i.e. x between > -4 and +4) and y as a fixed point number format with Q3.13 (then y lies > between -4 and +4)), clk is a clock signal to synchronize operations. > > First I need a behavioral model and test it with a suitable test-bench. > Then I have to write a synthesizable RTL model is tested by comparing > the behavioral model. > > I can approximate both the behavioral and structural model with: > > =A0 e ^ sin (x) with the polynomial P (x) =3D 1 + x + x ^ 2 / 2! - 3 / 4!= x > ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6 > > (in the structural relationship, the coefficients are processed in fixed > point and the polynomial is calculated using fixed-point operations). > > thanks again in advance First of all, why not look into the new IEEE fixed point package. For VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/ Then you can do nice things like: port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc So the bit numbers represent the real powers of 2 in the fixed point numbers. Then for a behavioural model, you can do this: use ieee.math_real.all; ... port (clk : in std_logic; x: in sfixed (2 downto -13); y: out sfixed(2 downto -13)); .... process variable x_rl : real; variable y_rl : real; begin wait until rising_edge(clk); x_rl :=3D to_real(x); y_rl :=3D math_e ** sin(x_rl); y <=3D to_sfixed(y_rl, y'high, y'low); end process; This wont be synthesisable, but it is a nice simple behavioural model. For a synthesisable implementation, a look up table is usually the best approach, but at 16 bits thats a fair chunk of memory! From newsfish@newsfish Fri Feb 3 13:11:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin Date: Tue, 08 Feb 2011 16:09:02 -0800 Lines: 19 Message-ID: <8re489Fj19U1@mid.individual.net> References: <4d512fa9$0$7662$9b4e6d93@newsspool1.arcor-online.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vJ4KsxIFv1IYBxLts3eXBAxSLo67SardV+7xX2JFVLmdlKQLoc Cancel-Lock: sha1:vETPejWDYHQ0081VZf6LJQ3bJ/M= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <4d512fa9$0$7662$9b4e6d93@newsspool1.arcor-online.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4731 On 2/8/2011 3:57 AM, Gerhard Hoffmann wrote: > Am 03.02.2011 18:20, schrieb Oliver Mattos: >> What resolution/performance do you need? >> >> I'd start with some kind of ROM as a lookup table. To do better than >> that you'll need to do lots of maths to come up with an iterative >> algorithm that can come up with the exact result using only basic >> functions (* + -). > > > I just have confessed my sin at opencores.org under arith/sincos. > If you can afford the block ram/rom you can use that as a starter. > Filling the table is in a function and is done in Pascal/C style > with floats. Nice example. Thanks for the link. The opencores site is much improved since my last visit. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:11:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.newsland.it!nntp.infostrada.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Wed, 09 Feb 2011 09:15:53 +0100 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> In-Reply-To: <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110208-1, 08/02/2011), Outbound message X-Antivirus-Status: Clean Lines: 89 Message-ID: <4d524d36$0$1367$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 80.117.195.129 X-Trace: 1297239350 reader1.news.tin.it 1367 80.117.195.129:5874 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4732 Il 08/02/2011 17:55, Tricky ha scritto: > On Feb 8, 10:20 am, tommy wrote: >> Il 07/02/2011 19:39, Andy ha scritto: >> >> >> >>> On Feb 3, 3:39 pm, Jonathan Bromley >>> wrote: >>>> On Thu, 03 Feb 2011 17:48:37 +0100, tommy wrote: >> >>>> See the other responses. >> >>>> I love the subject line. Sin in VHDL, repent in Verilog? >>>> -- >>>> Jonathan Bromley >> >>> Well, there's original sin(), concurrent sin(), sequential (serial?) >>> sin(), procedural sin(), functional sin() >> >>> Let's not forget monadic err... unary sin() and dyadic sin(). >> >>> Or just "Go Forth and sin() no more." >> >>> Andy >> >> I need to write an entity for the approximate calculation of e^sin (x) >> where x is a number representation in fixed point 2's complement, and | >> x |<3.14 / 2. >> >> my entity will be like this: >> >> exp_sin_x entity is >> port (x: in signed (15 downto 0), y: out signed (15 downto 0), >> clk: in std_ulogic) >> end entity; >> >> where the type is defined in the package signed IEEE / numeric_std, x >> must be interpreted as a fixed point number format Q3.13 (i.e. x between >> -4 and +4) and y as a fixed point number format with Q3.13 (then y lies >> between -4 and +4)), clk is a clock signal to synchronize operations. >> >> First I need a behavioral model and test it with a suitable test-bench. >> Then I have to write a synthesizable RTL model is tested by comparing >> the behavioral model. >> >> I can approximate both the behavioral and structural model with: >> >> e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x >> ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6 >> >> (in the structural relationship, the coefficients are processed in fixed >> point and the polynomial is calculated using fixed-point operations). >> >> thanks again in advance > > First of all, why not look into the new IEEE fixed point package. For > VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/ > > Then you can do nice things like: > > port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc > > So the bit numbers represent the real powers of 2 in the fixed point > numbers. > > Then for a behavioural model, you can do this: > > use ieee.math_real.all; > ... > port (clk : in std_logic; > x: in sfixed (2 downto -13); > y: out sfixed(2 downto -13)); > .... > process > variable x_rl : real; > variable y_rl : real; > begin > wait until rising_edge(clk); > x_rl := to_real(x); > y_rl := math_e ** sin(x_rl); > y<= to_sfixed(y_rl, y'high, y'low); > end process; > > This wont be synthesisable, but it is a nice simple behavioural model. > For a synthesisable implementation, a look up table is usually the > best approach, but at 16 bits thats a fair chunk of memory! This is nice approach but i need help for synthesisable codes... how can I develop this ? From newsfish@newsfish Fri Feb 3 13:11:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe16.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> <4d524d36$0$1367$4fafbaef@reader1.news.tin.it> In-Reply-To: <4d524d36$0$1367$4fafbaef@reader1.news.tin.it> Subject: Re: VHDL and Sin Lines: 1 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=response Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 15.4.3508.1109 X-MimeOLE: Produced By Microsoft MimeOLE V15.4.3508.1109 X-Antivirus: avast! (VPS 110208-1, 08/02/2011), Outbound message X-Antivirus-Status: Clean Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe16.ams2 1297246705 213.105.6.183 (Wed, 09 Feb 2011 10:18:25 UTC) NNTP-Posting-Date: Wed, 09 Feb 2011 10:18:25 UTC Organization: virginmedia.com Date: Wed, 9 Feb 2011 10:17:56 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4733 "tommy" wrote in message news:4d524d36$0$1367$4fafbaef@reader1.news.tin.it... >Il 08/02/2011 17:55, Tricky ha scritto: >..> >> This wont be synthesisable, but it is a nice simple behavioural model. >> For a synthesisable implementation, a look up table is usually the >> best approach, but at 16 bits thats a fair chunk of memory! > >This is nice approach but i need help for synthesisable codes... how can I >develop this ? As Tricky and and others wrote, go for Cordic or look-up table approach. There are lots of Cordic examples on the web, this paper might also help: http://www.ht-lab.com/misc/papers/paper_mapld_6.pdf If you want to use a LUT then try to find a paper by Robert Sutherland which describes a method of using two much smaller look-up tables. I can't remember all the details but a picture of the architecture is on slide 16 here: http://klabs.org/richcontent/MAPLDCon99/Presentations/A2_Vladimirova_S.pdf Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:11:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Wed, 09 Feb 2011 07:53:12 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Association list in component instantiations Date: Wed, 09 Feb 2011 13:55:45 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <5u65l6dteln6rf89j60i65m7t9goe194b6@4ax.com> References: <8qlop2F19bU1@mid.individual.net> <8r0innFdruU1@mid.individual.net> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 33 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-NDNxGJaVYiWdONwRtrlaRQw0TjhiHyqka+fbL5hQvFg9qqw1j4qG3n/EDmpM1W97u16Q4AScBC07apC!5ApD5Y+ulDwnpZYulax9ja0N6QHfcXvZdezxuTzuevqdtFoXYzd0V7m2vTF+lVKs4ma4pq3iURnw!dVE= X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2374 Xref: feeder.eternal-september.org comp.lang.vhdl:4734 On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote: >Am 30.01.2011 22:09, schrieb Jonathan Bromley: >> On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote: >> >>> I do not understand what I can use in the association list of a >>> component instantiation. Say, I have a component declaration like this: >What I really want and what didn't work is connecting some bits of an >input signal on the component (say, the data bus of an ADC) to a signal, >and other bits to a constant. Example: > >X: myinstance PORT MAP( > ... > data_input => data_bus(7 downto 0) & "00000000", > ...) > >> the actual association can be >> any monadic function of a signal. This was done to allow >> for type conversions in the port map, but it works for >> any monadic function then data_input => pad_low_byte(data_bus(7 downto 0)), ought to work, yes? Writing the function pad_low_byte should be a simple exercise. One caveat : some design tools (including older Xilinx synthesis tools) place unnecessary restrictions on what you can do in port associations, either explicitly, or by triggering tool bugs. - Brian From newsfish@newsfish Fri Feb 3 13:11:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!194.134.4.91.MISMATCH!news2.euro.net!newsfeed.x-privat.org!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Wed, 09 Feb 2011 17:08:25 +0100 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> <4d524d36$0$1367$4fafbaef@reader1.news.tin.it> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110209-0, 09/02/2011), Outbound message X-Antivirus-Status: Clean Lines: 31 Message-ID: <4d52bbf9$0$1350$4fafbaef@reader2.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 80.117.195.129 X-Trace: 1297267705 reader2.news.tin.it 1350 80.117.195.129:7329 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4735 Il 09/02/2011 11:17, HT-Lab ha scritto: > "tommy" wrote in message > news:4d524d36$0$1367$4fafbaef@reader1.news.tin.it... > >> Il 08/02/2011 17:55, Tricky ha scritto: >> ..> >>> This wont be synthesisable, but it is a nice simple behavioural model. >>> For a synthesisable implementation, a look up table is usually the >>> best approach, but at 16 bits thats a fair chunk of memory! >> >> This is nice approach but i need help for synthesisable codes... how >> can I develop this ? > > As Tricky and and others wrote, go for Cordic or look-up table approach. > There are lots of Cordic examples on the web, this paper might also help: > > http://www.ht-lab.com/misc/papers/paper_mapld_6.pdf > > If you want to use a LUT then try to find a paper by Robert Sutherland > which describes a method of using two much smaller look-up tables. I > can't remember all the details but a picture of the architecture is on > slide 16 here: > > http://klabs.org/richcontent/MAPLDCon99/Presentations/A2_Vladimirova_S.pdf > > Hans > www.ht-lab.com > > > this is very hard for me, but thanks :s From newsfish@newsfish Fri Feb 3 13:11:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q2g2000pre.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Why doesn't this produce the logic I expect? Date: Thu, 10 Feb 2011 10:18:03 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297361883 13756 127.0.0.1 (10 Feb 2011 18:18:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Feb 2011 18:18:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000pre.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4736 This seems trivial. I'm clearly missing something very basic. Here is the code: process(reset, clk) is begin if(reset = '1') then output <= FALSE; elsif(rising_edge(clk)) then if set = '0' then output <= TRUE; elsif trig <= '1' then output <= FALSE; end if; end if; end process; What I expected this to produce was a type of priority mux feeding a flip-flop. If set is '0' then output goes true (i.e highest priority). If set is anything else then we check trig (i.e lower priority). If trig is '1' then output goes false. Any other conditions output should hold it's state. The code produces the required flip-flop but completely ignores the trig signal. The only signal feeding the input to the flip-flop is set. I'm missing something fundamental here. Please help. From newsfish@newsfish Fri Feb 3 13:11:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q40g2000prh.googlegroups.com!not-for-mail From: Daniel Leu Newsgroups: comp.lang.vhdl Subject: Re: Why doesn't this produce the logic I expect? Date: Thu, 10 Feb 2011 10:41:26 -0800 (PST) Organization: http://groups.google.com Lines: 37 Message-ID: References: NNTP-Posting-Host: 99.35.48.120 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297363286 5636 127.0.0.1 (10 Feb 2011 18:41:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Feb 2011 18:41:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q40g2000prh.googlegroups.com; posting-host=99.35.48.120; posting-account=vg5e4goAAAAGOhAcfiR_nSjiLBi7pokl User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.84 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4737 On Feb 10, 10:18=A0am, Shannon wrote: > This seems trivial. =A0I'm clearly missing something very basic. =A0Here > is the code: > > =A0 =A0 =A0 =A0 process(reset, clk) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(reset =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output <=3D FALSE; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif(rising_edge(clk)) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if set =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output <= =3D TRUE; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif trig <=3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output <= =3D FALSE; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > What I expected this to produce was a type of priority mux feeding a > flip-flop. =A0If set is '0' then output goes true (i.e highest > priority). =A0If set is anything else then we check trig (i.e lower > priority). =A0If trig is '1' then output goes false. =A0Any other > conditions output should hold it's state. > > The code produces the required flip-flop but completely ignores the > trig signal. =A0The only signal feeding the input to the flip-flop is > set. =A0I'm missing something fundamental here. =A0Please help. How about > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif trig =3D '1' then ^^^^ Cheers, Daniel From newsfish@newsfish Fri Feb 3 13:11:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!transit3.readnews.com!postnews.google.com!a8g2000pri.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: Why doesn't this produce the logic I expect? Date: Thu, 10 Feb 2011 10:51:49 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: References: NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297363909 32133 127.0.0.1 (10 Feb 2011 18:51:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Feb 2011 18:51:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a8g2000pri.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4738 On Feb 10, 10:41=A0am, Daniel Leu wrote: > On Feb 10, 10:18=A0am, Shannon wrote: > > > > > This seems trivial. =A0I'm clearly missing something very basic. =A0Her= e > > is the code: > > > =A0 =A0 =A0 =A0 process(reset, clk) is > > =A0 =A0 =A0 =A0 begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(reset =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output <=3D FALSE; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif(rising_edge(clk)) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if set =3D '0' then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output = <=3D TRUE; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif trig <=3D '1' the= n > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 output = <=3D FALSE; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end process; > > > What I expected this to produce was a type of priority mux feeding a > > flip-flop. =A0If set is '0' then output goes true (i.e highest > > priority). =A0If set is anything else then we check trig (i.e lower > > priority). =A0If trig is '1' then output goes false. =A0Any other > > conditions output should hold it's state. > > > The code produces the required flip-flop but completely ignores the > > trig signal. =A0The only signal feeding the input to the flip-flop is > > set. =A0I'm missing something fundamental here. =A0Please help. > > How about > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif trig =3D '1' then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ^= ^^^ > > Cheers, > Daniel It's just not fair! I just saw the typo about 30 seconds ago. Daniel I guess I still owe you the +1 for finding it but I want it on the internet's permanent record that I DID in fact see my typo BEFORE I saw your reply. Is there a posting undo button? (going to hide under a rock now) From newsfish@newsfish Fri Feb 3 13:11:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!s29g2000pra.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Why doesn't this produce the logic I expect? Date: Thu, 10 Feb 2011 16:37:18 -0800 (PST) Organization: http://groups.google.com Lines: 5 Message-ID: References: NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297384638 29182 127.0.0.1 (11 Feb 2011 00:37:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Feb 2011 00:37:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s29g2000pra.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4739 It is a well known fact that posting unsolved problems on the internet improves vision. ;^) Andy From newsfish@newsfish Fri Feb 3 13:11:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 10 Feb 2011 22:16:57 -0600 Date: Thu, 10 Feb 2011 23:17:29 -0500 From: David Bishop User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> In-Reply-To: <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <9t2dnRY9cdekJcnQRVn_vwA@giganews.com> Lines: 57 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-hkq5iR6g2qGiJM66p2GQx2IYqc4LA2dQXW1E3bUzqlufYEUsz011BXqHGm8oDYx3H9NNMu7Ehfn/An7!DS0PwjhoLO+rdpffnBJl8xDKeooKYtWgLGiU3gYpl6/k8s0frsD7ae2W8v4ZYWoY X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3322 Xref: feeder.eternal-september.org comp.lang.vhdl:4740 On 2/8/2011 11:55 AM, Tricky wrote: >>> Well, there's original sin(), concurrent sin(), sequential (serial?) >>> sin(), procedural sin(), functional sin() >> >>> Let's not forget monadic err... unary sin() and dyadic sin(). >> >>> Or just "Go Forth and sin() no more." I've tried a few to solve this problem. The LUT turned out to be the easiest. My second choice, and the one I used in the floating point packages was the taylor series done below. >> I can approximate both the behavioral and structural model with: >> >> e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x >> ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6 >> >> (in the structural relationship, the coefficients are processed in fixed >> point and the polynomial is calculated using fixed-point operations). >> >> thanks again in advance > > First of all, why not look into the new IEEE fixed point package. For > VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/ > > Then you can do nice things like: > > port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc > > So the bit numbers represent the real powers of 2 in the fixed point > numbers. > > Then for a behavioural model, you can do this: > > use ieee.math_real.all; > ... > port (clk : in std_logic; > x: in sfixed (2 downto -13); > y: out sfixed(2 downto -13)); > .... > process > variable x_rl : real; > variable y_rl : real; > begin > wait until rising_edge(clk); > x_rl := to_real(x); > y_rl := math_e ** sin(x_rl); > y<= to_sfixed(y_rl, y'high, y'low); > end process; > > This wont be synthesisable, but it is a nice simple behavioural model. > For a synthesisable implementation, a look up table is usually the > best approach, but at 16 bits thats a fair chunk of memory! Create a look up table for 0 - PI/2, then just reflect it for the other 3 quadrants. From newsfish@newsfish Fri Feb 3 13:11:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 10 Feb 2011 22:18:51 -0600 Date: Thu, 10 Feb 2011 23:19:25 -0500 From: David Bishop User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101207 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: numeric_std_unsigned References: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> In-Reply-To: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <9t2dnRE9cdc2JcnQRVn_vwA@giganews.com> Lines: 7 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-VFKlE9k+ZiH9x86NKmrbOpy8WPqziV3ROnb3NnnmV1mt9SrmAlKdi3dRk7sdg5/ZZmq5oXsd3UXBi1g!ynpH9cG/UPuMxYHRMn9rDMiNbi8OUFFKIarM0CWlZO5bvawwR1evPj6jBcnaw94t X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1488 Xref: feeder.eternal-september.org comp.lang.vhdl:4741 On 1/31/2011 11:16 AM, Andy Peters wrote: > So, what's the point? People still like to use the old Synopsys > libraries and can't be bothered declaring unsigned signals? It was done because users requested it. So we did it. I helped write it and I thought it was a bit redundant. From newsfish@newsfish Fri Feb 3 13:11:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Trygve_Laugst=F8l?= Newsgroups: comp.lang.vhdl Subject: Re: Why doesn't this produce the logic I expect? Date: Fri, 11 Feb 2011 04:32:44 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 85.19.69.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297427564 8740 127.0.0.1 (11 Feb 2011 12:32:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Feb 2011 12:32:44 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.19.69.42; posting-account=UuG_LwoAAABVo101RSSamuvnISa0weGs User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4742 On Friday, February 11, 2011 1:37:18 AM UTC+1, Andy wrote: > It is a well known fact that posting unsolved problems on the internet > improves vision. ;^) The concept even has a name! http://en.wikipedia.org/wiki/Rubber_duck_debugging -- Trygve From newsfish@newsfish Fri Feb 3 13:11:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 11 Feb 2011 10:44:24 -0500 Lines: 153 Message-ID: <8rl3qrFkg2U1@mid.individual.net> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Xpr3nf8CodOEA0See4GPagU7UUjpzK/OX+TPdiG5WLCzknK1Ju Cancel-Lock: sha1:IaMeJBAY47aKOUuG9og7ZhHvHyI= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4743 On 2/2/2011 5:49 PM, rickman wrote: > On Feb 2, 5:07 pm, Oliver Mattos wrote: >> Hi, >> I have a bit of microprocessor code that looks like this (it's basically bit banging a synchronous serial protocol, with certain timing requirements): >> >> SetPin(A1, HIGH); >> delay(100ms) >> SetPin(A1, LOW); >> delay(10ms) >> SetPin(A1, HIGH); >> delay(100ms) >> for (i=0; i<10; i++) { >> SetPin(A1, LOW); >> SetPin(A2, (data>>=1)&1 ); >> delay(10ms) >> SetPin(A1, HIGH); >> delay(12ms)} >> >> ... etc. >> >> Basically, it's a sequence of actions happening at variable time intervals. >> >> How would you convert this neatly to VHDL? (I have a clock source of known frequency) I've thought of various methods involving state machines and counters, but they always end up horribly complex. >> >> One method I thought of: >> >> WAIT UNTIL rising_edge(clk); >> time<= time+1; >> IF time> 0 THEN A1<= '1'; END IF; >> IF time> 100 THEN A1<= '0'; END IF; >> IF time> 210 THEN A1<= '1'; END IF; >> IF time> 310 THEN A1<= '0'; END IF; >> IF time> 310 THEN A2<= data(0); END IF; >> IF time> 410 THEN A1<= '1'; END IF; >> IF time> 510 THEN A1<= '0'; END IF; >> IF time> 510 THEN A2<= data(1); END IF; >> IF time> 610 THEN A1<= '1'; END IF; >> IF time> 710 THEN A1<= '0'; END IF; >> IF time> 710 THEN A2<= data(2); END IF; >> etc.... >> >> I'm guessing the above logic will lead to a large slow design and messy code... >> >> Is there a nice and easy way to do this? >> >> Oliver >> >> PS. yes I realize there are bugs in both bits of code, but it gets the example across... > > I don't think that would be so large or slow. You might be able to > improve on it a bit by separating the state machine and counter. Your > state machine would have 11 or 12 states depending. In each state it > waits for the counter to reach zero, then loads a new value into the > counter and moves to the next state. Something along that line should > do the job. The point is that your compares don't have to be from > time zero. Instead they can be relative and you can reuse many of the > values rather than having each point a different value. In the loop > it is the same two wait values over and over. Take advantage of that, > just like you would in software. > > Also, I would use a case statement rather than a bunch of ifs. The > logic produced likely won't be different... no I take that back. In a > case statement the tools know that the conditions are mutually > exclusive. In the if structure you are using there is a chain of > priority and the tools aren't always smart enough to figure out that > the conditions are mutually exclusive. > > procedure RunTimer (IntervalMS : in natural; Enable : in std_logic; > CurState : inout natural; TimeCntr : inout natural) > is > begin > if (Enable = '1') then > if (TimeCntr = 0) then > TimeCntr<= IntervalMS; > CurState<= CurState + 1; > else > TimeCntr<= TimeCntr - 1; > end if; > end if; > end procedure RunTimer; > > case (CurState) is > when 0 => > A1<= '1'; > RunTiimer(100, CurState, TimeCntr); > when 1 => > A1<= '0'; > RunTiimer(10, CurState, TimeCntr); > when 2 => > A1<= '1'; > RunTiimer(100, CurState, TimeCntr); > when 3, 5, 7, 9, 11 => > A1<= '0'; > A2<= data AND 1; > RunTiimer(10, CurState, TimeCntr); > when 4, 6, 8, 10, 12 => > A1<= '1'; > RunTiimer(12, CurState, TimeCntr); > when 13 => -- wait for start trigger > if (Start = '1') then CurState<= 0; > end case; > > > Something like this. You will need a counter to count down to > milliseconds to use as an enable for the TimeCntr. And of course, I'm > sure the logic doesn't match exactly what you need. I suggest you simulate what you wrote, at least to find out that RunTiimer is defined as RunTimer and then that there is the Enable signal defined as "in std_logic" which you forgot when calling the procedure. I urge the need to draw your attention on the name of the procedure as well, I believe that RunTimer is misleading since it is neither a Timer neither is running (what does "run" means in this context?). On top of it why the counter should be a down counter? Looking at the structure of his sequence I don't believe the OP needs more than an FSM and a counter and it looks to me it will need only 4 states: idle (wait for the conditions to start the sequence) set1 (used to set 100ms signal) wait (used to wait 10ms) set2 (used to set 12ms signals) The FSM will need some additional logic to distinguish the two phases: init_done loop_done and arcs may follow this logic: idle -> set1 (start/reset/begin... as you like) set1 -> wait when timer = 100ms wait -> set1 when (timer = 10ms) and init_done = 0; wait -> set2 when (timer = 10ms) and init_done = 1; wait -> idle when (timer = 10ms) and loop_done = 1; set2 -> wait when timer = 12ms In case one day you will find that instead of a loop of 10 you will need a loop of 200 you will simply need to change the logic for loop_done, without the need to add 190 states to the FSM, same applies for the init part. The code the OP posted in my opinion will not work since the priority encoder will almost always be set to the first case (time > 0), since it will always be true except when time = 0 (during rollover). Al p.s.: I intentionally avoided to include vhdl since I believe that different people have different styles. From newsfish@newsfish Fri Feb 3 13:11:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z27g2000prz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 11 Feb 2011 08:14:47 -0800 (PST) Organization: http://groups.google.com Lines: 192 Message-ID: <90a37173-974f-4f58-84dc-dd3134d9c656@z27g2000prz.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> <8rl3qrFkg2U1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297440888 7520 127.0.0.1 (11 Feb 2011 16:14:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Feb 2011 16:14:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z27g2000prz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4744 On Feb 11, 10:44=A0am, Alessandro Basili wrote: > On 2/2/2011 5:49 PM, rickman wrote: > > On Feb 2, 5:07 pm, Oliver Mattos =A0wrote: > >> Hi, > >> I have a bit of microprocessor code that looks like this =A0(it's basi= cally bit banging a synchronous serial protocol, with certain timing requir= ements): > > >> SetPin(A1, HIGH); > >> delay(100ms) > >> SetPin(A1, LOW); > >> delay(10ms) > >> SetPin(A1, HIGH); > >> delay(100ms) > >> for (i=3D0; i<10; i++) { > >> =A0 =A0SetPin(A1, LOW); > >> =A0 =A0SetPin(A2, (data>>=3D1)&1 ); > >> =A0 =A0delay(10ms) > >> =A0 =A0SetPin(A1, HIGH); > >> =A0 =A0delay(12ms)} > > >> ... etc. > > >> Basically, it's a sequence of actions happening at variable time inter= vals. > > >> How would you convert this neatly to VHDL? (I have a clock source of k= nown frequency) =A0I've thought of various methods involving state machines= and counters, but they always end up horribly complex. > > >> One method I thought of: > > >> WAIT UNTIL rising_edge(clk); > >> time<=3D time+1; > >> IF time> =A00 THEN A1<=3D '1'; END IF; > >> IF time> =A0100 THEN A1<=3D '0'; END IF; > >> IF time> =A0210 THEN A1<=3D '1'; END IF; > >> IF time> =A0310 THEN A1<=3D '0'; END IF; > >> IF time> =A0310 THEN A2<=3D data(0); END IF; > >> IF time> =A0410 THEN A1<=3D '1'; END IF; > >> IF time> =A0510 THEN A1<=3D '0'; END IF; > >> IF time> =A0510 THEN A2<=3D data(1); END IF; > >> IF time> =A0610 THEN A1<=3D '1'; END IF; > >> IF time> =A0710 THEN A1<=3D '0'; END IF; > >> IF time> =A0710 THEN A2<=3D data(2); END IF; > >> etc.... > > >> I'm guessing the above logic will lead to a large slow design and mess= y code... > > >> Is there a nice and easy way to do this? > > >> Oliver > > >> PS. yes I realize there are bugs in both bits of code, but it gets the= example across... > > > I don't think that would be so large or slow. =A0You might be able to > > improve on it a bit by separating the state machine and counter. =A0You= r > > state machine would have 11 or 12 states depending. =A0In each state it > > waits for the counter to reach zero, then loads a new value into the > > counter and moves to the next state. =A0Something along that line shoul= d > > do the job. =A0The point is that your compares don't have to be from > > time zero. =A0Instead they can be relative and you can reuse many of th= e > > values rather than having each point a different value. =A0In the loop > > it is the same two wait values over and over. =A0Take advantage of that= , > > just like you would in software. > > > Also, I would use a case statement rather than a bunch of ifs. =A0The > > logic produced likely won't be different... no I take that back. =A0In = a > > case statement the tools know that the conditions are mutually > > exclusive. =A0In the if structure you are using there is a chain of > > priority and the tools aren't always smart enough to figure out that > > the conditions are mutually exclusive. > > > =A0 =A0procedure RunTimer (IntervalMS : in natural; Enable : in std_log= ic; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CurState : inout natural; TimeC= ntr : inout natural) > > is > > =A0 =A0begin > > =A0 =A0 =A0if (Enable =3D '1') then > > =A0 =A0 =A0 =A0if (TimeCntr =3D 0) then > > =A0 =A0 =A0 =A0 =A0TimeCntr<=3D IntervalMS; > > =A0 =A0 =A0 =A0 =A0CurState<=3D CurState + 1; > > =A0 =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 =A0TimeCntr<=3D TimeCntr - 1; > > =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0end if; > > =A0 =A0end procedure RunTimer; > > > case (CurState) is > > =A0 =A0when 0 =3D> > > =A0 =A0 =A0A1<=3D '1'; > > =A0 =A0 =A0RunTiimer(100, CurState, TimeCntr); > > =A0 =A0when 1 =3D> > > =A0 =A0 =A0A1<=3D '0'; > > =A0 =A0 =A0RunTiimer(10, CurState, TimeCntr); > > =A0 =A0when 2 =3D> > > =A0 =A0 =A0A1<=3D '1'; > > =A0 =A0 =A0RunTiimer(100, CurState, TimeCntr); > > =A0 =A0when 3, 5, 7, 9, 11 =3D> > > =A0 =A0 =A0A1<=3D '0'; > > =A0 =A0 =A0A2<=3D data AND 1; > > =A0 =A0 =A0RunTiimer(10, CurState, TimeCntr); > > =A0 =A0when 4, 6, 8, 10, 12 =3D> > > =A0 =A0 =A0A1<=3D '1'; > > =A0 =A0 =A0RunTiimer(12, CurState, TimeCntr); > > =A0 =A0when 13 =3D> =A0-- wait for start trigger > > =A0 =A0 =A0if (Start =3D '1') then CurState<=3D 0; > > =A0 =A0end case; > > > Something like this. =A0You will need a counter to count down to > > milliseconds to use as an enable for the TimeCntr. =A0And of course, I'= m > > sure the logic doesn't match exactly what you need. > > I suggest you simulate what you wrote, at least to find out that > RunTiimer is defined as RunTimer and then that there is the Enable > signal defined as "in std_logic" which you forgot when calling the > procedure. Thank you for your suggestion. If you would like me to run simulations for you, please contact me directly and I will be happy to provide you with my consulting rates and a contract. > I urge the need to draw your attention on the name of the procedure as > well, I believe that RunTimer is misleading since it is neither a Timer > neither is running (what does "run" means in this context?). > On top of it why the counter should be a down counter? I don't know why you think RunTimer does not run a timer. if (TimeCntr =3D 0) then TimeCntr <=3D IntervalMS; else TimeCntr <=3D TimeCntr - 1; end if; This does not look like a timer to you? > Looking at the structure of his sequence I don't believe the OP needs > more than an FSM and a counter and it looks to me it will need only 4 > states: Isn't that what my code provides? > idle (wait for the conditions to start the sequence) > set1 (used to set 100ms signal) > wait (used to wait 10ms) > set2 (used to set 12ms signals) > > The FSM will need some additional logic to distinguish the two phases: > > init_done > loop_done > > and arcs may follow this logic: > > idle -> set1 (start/reset/begin... as you like) > set1 -> wait when timer =3D 100ms > wait -> set1 when (timer =3D 10ms) and init_done =3D 0; > wait -> set2 when (timer =3D 10ms) and init_done =3D 1; > wait -> idle when (timer =3D 10ms) and loop_done =3D 1; > set2 -> wait when timer =3D 12ms > > In case one day you will find that instead of a loop of 10 you will need > a loop of 200 you will simply need to change the logic for loop_done, > without the need to add 190 states to the FSM, same applies for the init > part. > > The code the OP posted in my opinion will not work since the priority > encoder will almost always be set to the first case (time > 0), since it > will always be true except when time =3D 0 (during rollover). > > Al > > p.s.: I intentionally avoided to include vhdl since I believe that > different people have different styles. Ok, that looks great. When you are ready to provide some code let us know. Rick From newsfish@newsfish Fri Feb 3 13:11:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin1!goblin3!goblin.stu.neva.ru!gegeweb.org!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!a8g2000pri.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: numeric_std_unsigned Date: Fri, 11 Feb 2011 08:19:26 -0800 (PST) Organization: http://groups.google.com Lines: 24 Message-ID: <39fd5970-0e7a-4ffe-ac46-5538f8167062@a8g2000pri.googlegroups.com> References: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> <9t2dnRE9cdc2JcnQRVn_vwA@giganews.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297441167 10386 127.0.0.1 (11 Feb 2011 16:19:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Feb 2011 16:19:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a8g2000pri.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4745 On Feb 10, 11:19=A0pm, David Bishop wrote: > On 1/31/2011 11:16 AM, Andy Peters wrote: > > > So, what's the point? People still like to use the old Synopsys > > libraries and can't be bothered declaring unsigned signals? > > It was done because users requested it. =A0So we did it. =A0 I helped wri= te > it and I thought it was a bit redundant. I've never looked at this package. Does it work like the synopsys library where it provides unsigned arithmetic for the SLV data type? One of the things I like about the numeric_std library is that I don't have to type std_logic_vector anymore! I hated that and signed/ unsigned are so much easier on the fingers! But then I'm currently using Verilog. After a brief trial run I am finding it is pleasant to work with saving both my fingers and my brain for the real work I need to get done. I'm not fully conversant with the language however and may yet find some issues with it that make me very unhappy. But for now I'm putting aside my VHDL. Rick From newsfish@newsfish Fri Feb 3 13:11:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.tcx.org.uk!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news2.euro.net!newsfeed.freenet.ag!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 11 Feb 2011 12:03:17 -0500 Lines: 53 Message-ID: <8rl8enFkroU1@mid.individual.net> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> <8rl3qrFkg2U1@mid.individual.net> <90a37173-974f-4f58-84dc-dd3134d9c656@z27g2000prz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net ovUj8mPpjGRTR5emjFk6sg966d0ofS4sdRAWoloB4Y5We5JQYI Cancel-Lock: sha1:LPySK+L/lY087DAZvEioks1oi4I= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <90a37173-974f-4f58-84dc-dd3134d9c656@z27g2000prz.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4746 On 2/11/2011 11:14 AM, rickman wrote: >>> procedure RunTimer (IntervalMS : in natural; Enable : in std_logic; >>> CurState : inout natural; TimeCntr : inout natural) >>> is >>> begin >>> if (Enable = '1') then >>> if (TimeCntr = 0) then >>> TimeCntr<= IntervalMS; >>> CurState<= CurState + 1; >>> else >>> TimeCntr<= TimeCntr - 1; >>> end if; >>> end if; >>> end procedure RunTimer; >> > I don't know why you think RunTimer does not run a timer. > > if (TimeCntr = 0) then > TimeCntr<= IntervalMS; > else > TimeCntr<= TimeCntr - 1; > end if; > > This does not look like a timer to you? If it is "only" a timer why don't you call the procedure "timer"? What happened to CurState? Isn't the procedure taking care also about the fsm? Why the name of the procedure does not reflect what it is doing? I would assume that if you have to implement a fifo you will call the module fifo.vhd as well as the main entity. > > >> Looking at the structure of his sequence I don't believe the OP needs >> more than an FSM and a counter and it looks to me it will need only 4 >> states: > > Isn't that what my code provides? > Your state machine looks like a counter to me and I believe that fsm are different from counters. > Ok, that looks great. When you are ready to provide some code let us > know. > I believe I gave enough info to the OP to write the vhdl on his own, after all I think we are here to exchange ideas and problems, not pieces of (untested) code. > Rick From newsfish@newsfish Fri Feb 3 13:11:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!o39g2000prb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: numeric_std_unsigned Date: Fri, 11 Feb 2011 09:16:28 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: <3248697a-9f65-41d7-a129-e0e94acb947e@o39g2000prb.googlegroups.com> References: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> <9t2dnRE9cdc2JcnQRVn_vwA@giganews.com> <39fd5970-0e7a-4ffe-ac46-5538f8167062@a8g2000pri.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297444589 30608 127.0.0.1 (11 Feb 2011 17:16:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Feb 2011 17:16:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o39g2000prb.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4747 On Feb 11, 10:19=A0am, rickman wrote: > On Feb 10, 11:19=A0pm, David Bishop wrote: > > > On 1/31/2011 11:16 AM, Andy Peters wrote: > > > > So, what's the point? People still like to use the old Synopsys > > > libraries and can't be bothered declaring unsigned signals? > > > It was done because users requested it. =A0So we did it. =A0 I helped w= rite > > it and I thought it was a bit redundant. > > I've never looked at this package. =A0Does it work like the synopsys > library where it provides unsigned arithmetic for the SLV data type? > > One of the things I like about the numeric_std library is that I don't > have to type std_logic_vector anymore! =A0I hated that and signed/ > unsigned are so much easier on the fingers! > > But then I'm currently using Verilog. =A0After a brief trial run I am > finding it is pleasant to work with saving both my fingers and my > brain for the real work I need to get done. =A0I'm not fully conversant > with the language however and may yet find some issues with it that > make me very unhappy. =A0But for now I'm putting aside my VHDL. > > Rick Yes, afaik, it defines arithmetic operators that work on slv, and assumes an unsigned binary interpretation of the bits. I always create a subtype: subtype slv is std_logic_vector; Then I can use "slv" anywhere I would use "std_logic_vector" (declarations, type conversions, etc.) I'm betting that if you ever do much fixed point arithmetic, you'll be back. But it's a good thing to know more than one HDL language. Andy From newsfish@newsfish Fri Feb 3 13:11:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Al Newsgroups: comp.lang.vhdl Subject: Re: Sequential microprocessor code to vhdl - easy conversion tips? Date: Fri, 11 Feb 2011 15:13:49 -0500 Lines: 75 Message-ID: <8rljjvF2f2U1@mid.individual.net> References: <928f584a-202d-419a-82a3-a2a9cfa2b4d6@glegroupsg2000goo.googlegroups.com> <8r0n3tFbt0U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net /uwRijYTT0MF1RgcY0FdQQusoKumLSaX7yc9f8YprYc7RlXCfa Cancel-Lock: sha1:AAJfOdNwqpsbXwuwytbmB3CKBJc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: <8r0n3tFbt0U1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:4749 On 2/3/2011 5:04 PM, Mike Treseler wrote: > On 2/2/2011 2:04 PM, Oliver Mattos wrote: >> I have a bit of microprocessor code that looks like this (it's >> basically bit banging a synchronous serial protocol, with certain >> timing requirements): >> SetPin(A1, HIGH); >> delay(100ms) >> SetPin(A1, LOW); >> delay(10ms) >> SetPin(A1, HIGH); >> delay(100ms) >> for (i=0; i<10; i++) { >> SetPin(A1, LOW); >> SetPin(A2, (data>>=1)&1 ); >> delay(10ms) >> SetPin(A1, HIGH); >> delay(12ms) >> } > >> Basically, it's a sequence of actions happening at variable time >> intervals. >> How would you convert this neatly to VHDL? (I have a clock source of >> known frequency) I've thought of various methods involving state >> machines and counters, but they always end up horribly complex. > > > I would write a single clocked process using the > 'clock source of known frequency' to do > the following at every rising edge: > > 1. count gets count + 1 > 2. if rollover count gets zero > 3. case count is special, toggle appropriate output. > I think this approach is very straight forward and easy to implement, even though I believe it carries no information on the structure of the data itself and maybe very hard to modify or extend. I replied to the "same" post (with a different subject) arguing that an fsm with 4 states may do the job. Here is repeated: Looking at the structure of his sequence I don't believe the OP needs more than an FSM and a counter and it looks to me it will need only 4 states: idle (wait for the conditions to start the sequence) set1 (used to set 100ms signal) wait (used to wait 10ms) set2 (used to set 12ms signals) The FSM will need some additional logic to distinguish the two phases: init_done loop_done and arcs may follow this logic: idle -> set1 (start/reset/begin... as you like) set1 -> wait when timer = 100ms wait -> set1 when (timer = 10ms) and init_done = 0; wait -> set2 when (timer = 10ms) and init_done = 1; wait -> idle when (timer = 10ms) and loop_done = 1; set2 -> wait when timer = 12ms In case one day you will find that instead of a loop of 10 you will need a loop of 200 you will simply need to change the logic for loop_done, without the need to add 190 states to the FSM, same applies for the init part. Al p.s.: didn't know how to reference to my other post, that is why I copied it here. From newsfish@newsfish Fri Feb 3 13:11:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.newsland.it!nntp.eutelia.it!feeder.news.tin.it!spool.news.tin.it!not-for-mail Date: Fri, 11 Feb 2011 21:20:56 +0100 From: tommy User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; it; rv:1.9.1.16) Gecko/20101125 Thunderbird/3.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL and Sin References: <4d4adc64$0$1356$4fafbaef@reader1.news.tin.it> <4d51190a$0$1353$4fafbaef@reader2.news.tin.it> <9a62bbdc-b7ba-489e-8f1b-ca27e3245870@y26g2000yqd.googlegroups.com> <9t2dnRY9cdekJcnQRVn_vwA@giganews.com> In-Reply-To: <9t2dnRY9cdekJcnQRVn_vwA@giganews.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110211-0, 11/02/2011), Outbound message X-Antivirus-Status: Clean Lines: 62 Message-ID: <4d559a23$0$1362$4fafbaef@reader1.news.tin.it> Organization: TIN.IT (http://www.tin.it) X-Comments: Please send technical notifications to newsmaster@tin.it NNTP-Posting-Host: 95.238.65.108 X-Trace: 1297455651 reader1.news.tin.it 1362 95.238.65.108:5104 X-Complaints-To: Please send abuse reports to abuse@retail.telecomitalia.it Xref: feeder.eternal-september.org comp.lang.vhdl:4750 Il 11/02/2011 05:17, David Bishop ha scritto: > On 2/8/2011 11:55 AM, Tricky wrote: > >>>> Well, there's original sin(), concurrent sin(), sequential (serial?) >>>> sin(), procedural sin(), functional sin() >>> >>>> Let's not forget monadic err... unary sin() and dyadic sin(). >>> >>>> Or just "Go Forth and sin() no more." > > I've tried a few to solve this problem. The LUT turned out to be the > easiest. My second choice, and the one I used in the floating point > packages was the taylor series done below. > >>> I can approximate both the behavioral and structural model with: >>> >>> e ^ sin (x) with the polynomial P (x) = 1 + x + x ^ 2 / 2! - 3 / 4! x >>> ^ 4 - 8 / 5! x ^ 5 - 3 / 6! x ^ 6 >>> >>> (in the structural relationship, the coefficients are processed in fixed >>> point and the polynomial is calculated using fixed-point operations). >>> >>> thanks again in advance >> >> First of all, why not look into the new IEEE fixed point package. For >> VHDL '93 compatible version, see here: http://www.vhdl.org/fphdl/ >> >> Then you can do nice things like: >> >> port (x: in sfixed (2 downto -13), y: out sfixed(2 downto -13) etc >> >> So the bit numbers represent the real powers of 2 in the fixed point >> numbers. >> >> Then for a behavioural model, you can do this: >> >> use ieee.math_real.all; >> ... >> port (clk : in std_logic; >> x: in sfixed (2 downto -13); >> y: out sfixed(2 downto -13)); >> .... >> process >> variable x_rl : real; >> variable y_rl : real; >> begin >> wait until rising_edge(clk); >> x_rl := to_real(x); >> y_rl := math_e ** sin(x_rl); >> y<= to_sfixed(y_rl, y'high, y'low); >> end process; >> >> This wont be synthesisable, but it is a nice simple behavioural model. >> For a synthesisable implementation, a look up table is usually the >> best approach, but at 16 bits thats a fair chunk of memory! > > Create a look up table for 0 - PI/2, then just reflect it for the other > 3 quadrants. Hello, can you paste your solution please? I can try to study the code, thanks again From newsfish@newsfish Fri Feb 3 13:11:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f30g2000yqa.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conversion of sequential time-sensitive algorithm to VHDL Date: Fri, 11 Feb 2011 19:40:38 -0800 (PST) Organization: http://groups.google.com Lines: 75 Message-ID: <3d394e58-e8e2-4c52-b68b-304a0deaa6ba@f30g2000yqa.googlegroups.com> References: <87bd9c98-00b6-464b-a10f-c0a7484b2884@glegroupsg2000goo.googlegroups.com> <6a8e76b1-3e2b-43b1-aa45-deda733193e3@i40g2000yqh.googlegroups.com> <8rl3qrFkg2U1@mid.individual.net> <90a37173-974f-4f58-84dc-dd3134d9c656@z27g2000prz.googlegroups.com> <8rl8enFkroU1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297482038 14948 127.0.0.1 (12 Feb 2011 03:40:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 12 Feb 2011 03:40:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f30g2000yqa.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4751 On Feb 11, 12:03 pm, Alessandro Basili wrote: > On 2/11/2011 11:14 AM, rickman wrote: > > >>> procedure RunTimer (IntervalMS : in natural; Enable : in std_logic; > >>> CurState : inout natural; TimeCntr : inout natural) > >>> is > >>> begin > >>> if (Enable = '1') then > >>> if (TimeCntr = 0) then > >>> TimeCntr<= IntervalMS; > >>> CurState<= CurState + 1; > >>> else > >>> TimeCntr<= TimeCntr - 1; > >>> end if; > >>> end if; > >>> end procedure RunTimer; > > > I don't know why you think RunTimer does not run a timer. > > > if (TimeCntr = 0) then > > TimeCntr<= IntervalMS; > > else > > TimeCntr<= TimeCntr - 1; > > end if; > > > This does not look like a timer to you? > > If it is "only" a timer why don't you call the procedure "timer"? > What happened to CurState? Isn't the procedure taking care also about > the fsm? Why the name of the procedure does not reflect what it is doing? > I would assume that if you have to implement a fifo you will call the > module fifo.vhd as well as the main entity. I have no idea where you are coming from. If you don't like the name I used, feel free to change it to suit yourself. I'm not writing the code for work. I was trying to show someone an alternative approach to solving his problem which would make this code simpler. If you don't like it why not post some of your own? > >> Looking at the structure of his sequence I don't believe the OP needs > >> more than an FSM and a counter and it looks to me it will need only 4 > >> states: > > > Isn't that what my code provides? > > Your state machine looks like a counter to me and I believe that fsm are > different from counters. If you think a counter is not a FSM, then you need to reread your text books. The OP's problem stepped through a number of states sequentially. That makes a counter an appropriate form of FSM to represent his design. Further, he was trying to turn a sequential language program into hardware. This style of FSM would make it very easy for him to make that translation. > > Ok, that looks great. When you are ready to provide some code let us > > know. > > I believe I gave enough info to the OP to write the vhdl on his own, > after all I think we are here to exchange ideas and problems, not pieces > of (untested) code. That was my purpose. I didn't intend that he should take my code, type it in and it would run. In essence I was providing pseudo-code to express my ideas. Do me a favor. Next time I try to help someone, feel free to offer help as well, but don't criticize others for doing the same. Your criticism didn't help me, it didn't help the OP and I expect it didn't help you either. Rick From newsfish@newsfish Fri Feb 3 13:11:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!news.dfncis.de!not-for-mail From: Hannes <"h.mcchoc"@gmx.de> Newsgroups: comp.lang.vhdl Subject: and bitwise operation on std_logic_vector bits Date: Mon, 14 Feb 2011 16:50:00 +0100 Lines: 25 Message-ID: <8rt198F7tnU1@mid.dfncis.de> Reply-To: h.mcchoc@gmx.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.dfncis.de C12xev2Z8YdHhj3+0+RXsQfKPowwfJzNS0ArxTx/+0FbbD User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 Xref: feeder.eternal-september.org comp.lang.vhdl:4752 Hello, I am relatively new to VHDL. I search for a command to realize a Boolean OR operation on all bits of a std_logic_vector in a compact way. example: signal a : std_logic vector (3 downto 0); signal b : std_logic; b <= a(0) or a(1) or a(2) or a(3); this solution works fine with four bits, but with larger vectors it is not very comfortable. Do somebody have an idea? Regards Hannes From newsfish@newsfish Fri Feb 3 13:11:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <8rt198F7tnU1@mid.dfncis.de> In-Reply-To: <8rt198F7tnU1@mid.dfncis.de> Subject: Re: and bitwise operation on std_logic_vector bits Lines: 2 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 15.4.3508.1109 X-MimeOLE: Produced By Microsoft MimeOLE V15.4.3508.1109 X-Antivirus: avast! (VPS 110214-0, 14/02/2011), Outbound message X-Antivirus-Status: Clean Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1297701845 213.105.6.183 (Mon, 14 Feb 2011 16:44:05 UTC) NNTP-Posting-Date: Mon, 14 Feb 2011 16:44:05 UTC Organization: virginmedia.com Date: Mon, 14 Feb 2011 16:43:48 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4753 VHDL2008 supports reduction operators, b<= OR a; Hans www.ht-lab.com "Hannes" wrote in message news:8rt198F7tnU1@mid.dfncis.de... Hello, I am relatively new to VHDL. I search for a command to realize a Boolean OR operation on all bits of a std_logic_vector in a compact way. example: signal a : std_logic vector (3 downto 0); signal b : std_logic; b <= a(0) or a(1) or a(2) or a(3); this solution works fine with four bits, but with larger vectors it is not very comfortable. Do somebody have an idea? Regards Hannes From newsfish@newsfish Fri Feb 3 13:11:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!news.dfncis.de!not-for-mail From: Hannes <"h.mcchoc"@gmx.de> Newsgroups: comp.lang.vhdl Subject: Re: and bitwise operation on std_logic_vector bits Date: Mon, 14 Feb 2011 18:51:22 +0100 Lines: 41 Message-ID: <8rt8cqFq5hU1@mid.dfncis.de> References: <8rt198F7tnU1@mid.dfncis.de> Reply-To: h.mcchoc@gmx.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.dfncis.de NwhVPz5SPEX7hpTMK1E7dQvRq5yRfSbJ0Z5wKsDsEJ+wix User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4754 Thank you, regards Hannes On 02/14/2011 05:43 PM, HT-Lab wrote: > VHDL2008 supports reduction operators, > > b<= OR a; > > Hans > www.ht-lab.com > > > "Hannes" wrote in message news:8rt198F7tnU1@mid.dfncis.de... > Hello, > > I am relatively new to VHDL. > > I search for a command to realize a Boolean OR operation on all bits of > a std_logic_vector in a compact way. > > example: > > signal a : std_logic vector (3 downto 0); > signal b : std_logic; > > b <= a(0) or a(1) or a(2) or a(3); > > > > this solution works fine with four bits, but with larger vectors it is > not very comfortable. > Do somebody have an idea? > > Regards > > Hannes > From newsfish@newsfish Fri Feb 3 13:11:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z31g2000vbs.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: and bitwise operation on std_logic_vector bits Date: Tue, 15 Feb 2011 00:40:38 -0800 (PST) Organization: http://groups.google.com Lines: 61 Message-ID: References: <8rt198F7tnU1@mid.dfncis.de> <8rt8cqFq5hU1@mid.dfncis.de> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297759239 14913 127.0.0.1 (15 Feb 2011 08:40:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 08:40:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z31g2000vbs.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4755 On 14 Feb., 18:51, Hannes <"h.mcchoc"@gmx.de> wrote: > Thank you, > > regards > > Hannes > > On 02/14/2011 05:43 PM, HT-Lab wrote: > > > VHDL2008 supports reduction operators, > > > b<=3D OR a; > > > Hans > >www.ht-lab.com > > > "Hannes" =A0wrote in messagenews:8rt198F7tnU1@mid.dfncis.de... > > Hello, > > > I am relatively new to VHDL. > > > I search for a command to realize a Boolean OR operation on all bits of > > a std_logic_vector in a compact way. > > > example: > > > signal a : std_logic vector (3 downto 0); > > signal b : std_logic; > > > b <=3D a(0) or a(1) or a(2) or a(3); > > > this solution works fine with four bits, but with larger vectors it is > > not very comfortable. > > Do somebody have an idea? > > > Regards > > > Hannes > > Hi, nice tip for the future, when all tools finally support VHDL 2008. For now, you can find reduce-functions in std_logic_misc. e.g. function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01; function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01; Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:11:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: and bitwise operation on std_logic_vector bits Date: Tue, 15 Feb 2011 06:59:18 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: <647563e2-bdd3-4c8d-a7b5-2e460233f685@d28g2000yqc.googlegroups.com> References: <8rt198F7tnU1@mid.dfncis.de> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297781958 15187 127.0.0.1 (15 Feb 2011 14:59:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 14:59:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4756 On 14 Feb., 16:50, Hannes <"h.mcchoc"@gmx.de> wrote: > signal a : std_logic vector (3 downto 0); > signal b : std_logic; > > b <= a(0) or a(1) or a(2) or a(3); beside the defined reduce functions(see other post in this thread) you could use a for-loop as generic solution to do bitwise reduction for any function. for i in a'range loop b_var := b_var or a(i); c_var := my_function(c_var, a(i)); end loop bye Thomas From newsfish@newsfish Fri Feb 3 13:11:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder5.xlned.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!s28g2000prb.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: numeric_std_unsigned Date: Tue, 15 Feb 2011 08:09:22 -0800 (PST) Organization: http://groups.google.com Lines: 46 Message-ID: <7347dfda-bede-4048-8433-0eee590ace9f@s28g2000prb.googlegroups.com> References: <8156ea57-ed22-444d-8fc4-3ddee70d4700@o21g2000prn.googlegroups.com> <9t2dnRE9cdc2JcnQRVn_vwA@giganews.com> <39fd5970-0e7a-4ffe-ac46-5538f8167062@a8g2000pri.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297786163 23194 127.0.0.1 (15 Feb 2011 16:09:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 16:09:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s28g2000prb.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4757 > > > So, what's the point? People still like to use the old Synopsys > > > libraries and can't be bothered declaring unsigned signals? > > > It was done because users requested it. =A0So we did it. =A0 I helped w= rite > > it and I thought it was a bit redundant. > > I've never looked at this package. =A0Does it work like the synopsys > library where it provides unsigned arithmetic for the SLV data type? > > One of the things I like about the numeric_std library is that I don't > have to type std_logic_vector anymore! =A0I hated that and signed/ > unsigned are so much easier on the fingers! I think using the types unsigned and signed everywhere instead of SLV is a good idea. In fact, if you don't use numeric_std_unsigned and you use std_logic_vector with a relational operator, life is bad. OTOH, if you are careful, you never need numeric_std_unsigned for RTL. The one place I like numeric_std_unsigned though is in testbenches. When an address input to a DUT is std_logic_vector and I want to algorithmically add one to it, I find the code much more readable if I use numeric_std_unsigned than use one of the numerous different approaches that use type conversions. When you consider readability, you need to consider not just people who are at your skill level, but also the people who will take on maintaining the design. As Andy mentioned, mentioned, what is the point, people still use the old std_logic_arith and std_logic_unsigned. My answer to that is it is hard to get people to transition if you don't give them the packages they want to use when they transition - namely numeric_std_unsigned was missing. So hopefully we can get them to transition. Going further, it would be nice if vendor documentation, notably Xilinx (at least through 12.1) replacing std_logic_arith with numeric_std. Best, Jim From newsfish@newsfish Fri Feb 3 13:11:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!o21g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: VHDL MEMORY MODLELS DESIGNER? Date: Tue, 15 Feb 2011 08:14:24 -0800 (PST) Organization: http://groups.google.com Lines: 3 Message-ID: <00482864-4002-40a9-85a0-aa8220de376d@o21g2000prn.googlegroups.com> References: <6e9edd2d-beb0-47e5-be2e-cd05afbd0784@d1g2000yqb.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297786464 25821 127.0.0.1 (15 Feb 2011 16:14:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 16:14:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o21g2000prn.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4758 See http://www.freemodelfoundry.com/ they provide alot of VHDL memory models for free. From newsfish@newsfish Fri Feb 3 13:11:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o18g2000prh.googlegroups.com!not-for-mail From: Rejin James Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Tue, 15 Feb 2011 09:31:13 -0800 (PST) Organization: http://groups.google.com Lines: 538 Message-ID: <1ba6a96b-8f3e-4f1d-83bd-512e0dbe66f7@o18g2000prh.googlegroups.com> References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> <4013774f-e2e6-40eb-ba45-87cbdd44e90f@w19g2000yqa.googlegroups.com> <9d44362b-281f-4974-8368-c825a3714162@s18g2000vbe.googlegroups.com> NNTP-Posting-Host: 115.242.154.111 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297791073 17059 127.0.0.1 (15 Feb 2011 17:31:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 17:31:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000prh.googlegroups.com; posting-host=115.242.154.111; posting-account=sVZi6woAAAALUtg7YjdT9QJbVW4okBS2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1.4) Gecko/20091016 FireDownload/2.0.1 Firefox/3.5.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4759 On Jan 28, 12:57=A0pm, backhus wrote: > On 28 Jan., 05:31, Rejin James wrote: > > > On Jan 27, 12:29=A0pm, backhus wrote: > > > > On 26 Jan., 13:32, Rejin James wrote: > > > > > On Jan 26, 1:10=A0pm, backhus wrote: > > > > > > On 25 Jan., 06:49, Rejin James wrote: > > > > > > > Hi Friends I am currently doin my university project on the top= ic > > > > > > Low Power AES algorithm using VHDL > > > > > > > I was having problems understanding the logic of Mixcolumns ope= ration > > > > > > in GALIOS FIELD and other parts of the algorithm like galios fi= eld > > > > > > multiplication and key expansion. > > > > > > Can anyone help me out >?? > > > > > > > this is the base paper im followingwww.martes-itea.org/.../Hama= lainen-Design_and_Implementation_2.pdf > > > > > > > actually i got the cores from their website and was having a pr= oblem > > > > > > in understanding it . > > > > > > They are using 8- bit data paths and i was having problems in > > > > > > understanding their architecture and implementation in VHDl. > > > > > > > The following is the code for mixcolumns operation . can somebo= dy help > > > > > > me out with it ?? > > > > > > i was not understanding the GALIOS FIELD multiplication concept= . > > > > > > > library ieee; > > > > > > use ieee.std_logic_1164.all; > > > > > > > entity mixcolumns is > > > > > > =A0 port( > > > > > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > > > > > =A0 =A0 start_in =A0 : in =A0std_logic; > > > > > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' = =3D inverse > > > > > > transformation > > > > > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0); = =A0-- input data > > > > > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0--= output data > > > > > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0--= output data > > > > > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0--= output data > > > > > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 --= output data > > > > > > =A0 =A0 ); > > > > > > end mixcolumns; > > > > > > > -- fwd_rtl =3D forward only > > > > > > architecture fwd_rtl of mixcolumns is > > > > > > > =A0 -- GF(2^8) multiplication with constant: x > > > > > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > > > > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > > > > > =A0 =A0 return std_logic_vector is > > > > > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > > > > > =A0 begin > > > > > > =A0 =A0 b(0) :=3D a(7); > > > > > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > > > > > =A0 =A0 b(2) :=3D a(1); > > > > > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > > > > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > > > > > =A0 =A0 b(5) :=3D a(4); > > > > > > =A0 =A0 b(6) :=3D a(5); > > > > > > =A0 =A0 b(7) :=3D a(6); > > > > > > =A0 =A0 return b; > > > > > > =A0 end; > > > > > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vecto= r(7 downto > > > > > > 0); > > > > > > =A0 signal accum_r : accum_array_t; > > > > > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > > > > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto 0)= ; > > > > > > > begin =A0-- rtl > > > > > > > =A0 assert (inverse_in /=3D '1') report "this architecture supp= orts only > > > > > > forward operation" > > > > > > =A0 =A0 severity failure; > > > > > > =A0 x <=3D data_in; > > > > > > > =A0 prod2 <=3D gf256_mul2(x); > > > > > > =A0 prod3 <=3D prod2 xor x; > > > > > > > =A0 -- forward transform: > > > > > > =A0 -- > > > > > > =A0 -- x0 =A0 |02 03 01 01| y0 > > > > > > =A0 -- x1 =3D |01 02 03 01|*y1 > > > > > > =A0 -- x2 =A0 |01 01 02 03| y2 > > > > > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > > > > > =A0 -- inverse transform > > > > > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > > > > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > > > > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > > > > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > > > > > =A0 clocked : process (clk) > > > > > > =A0 begin =A0-- process clocked > > > > > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- risi= ng clock edge > > > > > > =A0 =A0 =A0 if (start_in =3D '1') then > > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > > > > > =A0 =A0 =A0 else > > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > > > > > =A0 =A0 =A0 end if; > > > > > > =A0 =A0 end if; > > > > > > =A0 end process clocked; > > > > > > > =A0 data0_out <=3D accum_r(0); > > > > > > =A0 data1_out <=3D accum_r(1); > > > > > > =A0 data2_out <=3D accum_r(2); > > > > > > =A0 data3_out <=3D accum_r(3); > > > > > > > end fwd_rtl; > > > > > > > ANY HELP WOULD BE APPRECIATED .. thanks > > > > > > Hi, > > > > > that's a lot of questions at once. :-) > > > > > Galois Field math is a topic for 10th semester math students. > > > > > So don't be bothered when it seems complicated to understand. > > > > > In some VERY simple words: The galois field is a limited bunch of > > > > > numbers, that obeys defined mathematical rules. > > > > > This is only possible because he operations can always be seen as > > > > > modulo operations in order to keep the number space constant. > > > > > When you chop down the field size to tw0 you can work with simple= gate > > > > > functions (AND and XOR) for multiplication and addition. > > > > > > Mix columns is an ordinary vector/matrix multiplication, where yo= u > > > > > multiply a row of the input matrix with a given transformation > > > > > matrix. > > > > > The result is then written to a column of the result matrix. > > > > > > The code you provided has one strange property. > > > > > It takes a single stream of data (data_in) and creates four resul= t > > > > > values. > > > > > You need to find out in which order the input stram has to provid= e the > > > > > data of the input matrix (and when to apply start_in) > > > > > and what to do with the four result values. > > > > > > Maybe you should take a look ath this book: > > > > > The Design of Rijndael: AES. TheAdvanced Encryption Standard > > > > > Written by the designers of the algorithm. > > > > > There you find many examples and calculations that you can compar= e > > > > > with your simulations, in order to understand how the code works = that > > > > > you have. > > > > > > Have a nice simulation > > > > > =A0 Eilert > > > > > Hey Eilert, > > > > Thanks a lot for the reply. :-) > > > > > i went through the galois Field multiplication once more from a boo= k > > > > on cryptography and got a basic idea as to wat happens in that. > > > > > The reason dat the code only takes one input is because i am > > > > implementing Aes algorithm with 8 bit DAta path (data input) > > > > And according to the paper that i am using the mix columns multipli= er > > > > unit takes in the 8 bit data and produces 32 bit output which is th= en > > > > given to a parallel to serial converter. > > > > > If u cud see the base paper which i was referring once then i guess= u > > > > wud understand it better. Coz i was not able to understand much. > > > > > And i also understood when to apply start_in. it helps us to contro= l > > > > operation of mixcolumns for encryption or decryption. > > > > when start_in is not one it signifies we want to do the inverse > > > > operation i.e. decryption. > > > > Hi, > > > you confused start_in with inverse_in. > > > Also inverse_in has to be '1' all the time since the code doesn't > > > suport the inverse transformation. > > > (Look at the assert statement) > > > > In the mentioned paper there is a signal mentioned called "en". > > > That's probably called start_in in the provided source now. > > > > It has to be applied "During inputting the first byte of a column > > > (bytes 0, 4, 8, and 12 in Fig. 1)" > > > as mentioned in the paper. > > > It seems like the results have to be taken after every four clock > > > cycles. > > > So, start in can be also used for the following stage to take over th= e > > > results from the mix column stage. > > > > If you have the full sources of that project, there should be some > > > design unit that controlls the datapath. > > > Some kind of FSM. By analysing that you probably gain more detailed > > > insights how the whole thing works. > > > > Have a nice synthesis > > > =A0 Eilert > > > Hi, > > i think when inverse_in is 1 it means reverse process i.e decryption. > > it was given as comment somewhere in the full sources. > > As for start _in i think u are right. But the things mentioned about > > taking data byte by byte is not making sense to me as the input that > > we feed is 8-bit(i.e 1 byte) so how come rest of the bytes are coming. > > And how can one make The state when input is only 8-bit ? > > > Here is the link for the full source.http://www.tkt.cs.tut.fi/research/= daci/ra_security_8bit_aes_hw.html > > > Thanks for your help. > > I did not go through the top level. Ill try to go through it and > > understand. > > If u could also just take a look it would be a big help. > > Thanks Eilert > > Rejin > > Hi Rejin, > the README file in the sources sais it's only an encryption core, and > also the paper mentiones only encryption in the tables. > And even the sources say that the inverse algorithm (needed for > decryption) is not implemented. > So no chance for generating the inverse algorithm. > > The AES state matrix consists of 16 bytes. > So for each operation, 16 bytes have to be provided. > This implementation works in a "byteserial" manner, that mewans you > have to provide all the bytes on 16 consecutive clock cycles. > (The same applies to the key matrix) > > Look at the main file aes.vhd. > there you find the processes > =A0 control_clocked > and > =A0 control_comb. > > These are a 2-process implementation of the controlling FSM. > The signal sequence_r there counts the state matrix position that's > been worked on. > Furthermore there's a signal round, that counts the rounds of the AES > algorithm. > Depending on the data- and keywidth the input data has to iterate 8 to > 14 times through the algorithm. > (and the fist or last round is treated special, depending wether you > do en- or decryption) > > So, by further analysing this part of the code you can learn how to > feed data into the core, and when to read out the results. > Maybe you could start with reconstructing the state diagramm from the > vhdl source, so you have a graphical point of orientation. > > Also there are three testbenches. > I think you can see how to controll the input data pretty well by > looking at this part of the code from aes_tb_test1.vhd: > > ------------------------------------------------------------------------- > > =A0 =A0 =A0 -- encrypt > > ------------------------------------------------------------------------- > > =A0 =A0 =A0 -- load input > > =A0 =A0 =A0 for i in 0 to 15 loop > > =A0 =A0 =A0 =A0 wait until falling_edge(clk); > > =A0 =A0 =A0 =A0 inverse_in <=3D '0'; > > =A0 =A0 =A0 =A0 load_in =A0 =A0<=3D '1'; > > =A0 =A0 =A0 =A0 data_in <=3D std_logic_vector(to_unsigned(ptext(t)(i), 8)= ); > > =A0 =A0 =A0 =A0 key_in =A0<=3D std_logic_vector(to_unsigned(key_fwd(t)(i)= , 8)); > > =A0 =A0 =A0 end loop; =A0-- i > > =A0 =A0 =A0 wait until falling_edge(clk); > > =A0 =A0 =A0 load_in =A0<=3D '0'; > > =A0 =A0 =A0 start_in <=3D '1'; > > =A0 =A0 =A0 wait until falling_edge(clk); > > =A0 =A0 =A0 start_in <=3D '0'; > > =A0 =A0 =A0 -- compute > > =A0 =A0 =A0 wait until rising_edge(clk) and busy_out =3D '0'; > > =A0 =A0 =A0 -- read output & check result > > =A0 =A0 =A0 wait until falling_edge(clk); > > =A0 =A0 =A0 unload_in <=3D '1'; > > =A0 =A0 =A0 for i in 0 to 15 loop > > =A0 =A0 =A0 =A0 wait until rising_edge(clk); > > =A0 =A0 =A0 =A0 assert ctext(t)(i) =3D to_integer(unsigned(data_out)) > > =A0 =A0 =A0 =A0 =A0 report "forward failed" severity error; > > =A0 =A0 =A0 end loop; =A0-- i > > =A0 =A0 =A0 unload_in <=3D '0'; > > =A0 =A0 =A0 wait until rising_edge(clk); > > Have a nice simulation > =A0 Eilert Hi eilert.. so sorry for replying so late.. had taken a mini vacation ;).. Ya i got the inputting part.. im not sure whether ill be able to reconstruct the FSM ., ill try.. Currently i was doing the key expansion unit and was facing problems understanding this part of the core.. im gettin confused as to wen and during wich clock puse we have 2 send key)_in to the key expansion unit and during which clock pulse we send data to sbox and retrieve from it.. a further thing i noticed is that according to the table given for key expansion the data is supposed 2 shift and replaced by new data, but somehow i dint notice it actually happening,, if u cud just explain the code a lil... architecture fwd_rtl of keyexpansion is type control_seq_t is array (0 to 15) of integer range 0 to 4; constant control_seq : control_seq_t :=3D (1, 2, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4); signal sequence : integer range 0 to 15; type shiftreg_t is array (0 to 15) of std_logic_vector(7 downto 0); signal shift_r : shiftreg_t; signal rcon_value : std_logic_vector(7 downto 0); -- storage for key byte required for RotWord() -operation. signal rotword_r : std_logic_vector(7 downto 0); signal d0, d1, d2 : std_logic; -- mux control signals signal d3 : std_logic; -- '1' =3D signal "rcon_value" is zeroed -- key byte output (also fed back to shift register) signal key_out_int : std_logic_vector(7 downto 0); signal ext_control : std_logic_vector(1 downto 0); begin -- architecture rtl key_out <=3D key_out_int; key_d4_out <=3D shift_r(12); --mux0 data_to_sbox_out <=3D shift_r(13) when d0 =3D '1' else rotword_r; --mux1 and rcon xor key_out_int <=3D data_from_sbox_in xor rcon_value xor shift_r(0) when (d1 =3D '1' and d3 =3D '0') else data_from_sbox_in xor shift_r(0) when (d1 =3D '1' and d3 =3D '1') else shift_r(0); ext_control(1) <=3D load_in; ext_control(0) <=3D shift_in; sequence <=3D to_integer(unsigned(seq_in)); -- inverse is not implemented in this architecture assert (inverse_in /=3D '1') report "inverse operation not supported" severity warning; ---------------------------------------------+ -- | control | -- | 0 | 1 | 2 | 3 | 4 | ---------------+-----+-----+-----+-----+-----| -- d0 | 0 | 1 | 1 | 0 | 0 | -- d1 | 0 | 1 | 1 | 1 | 0 | -- d2 | 0 | 0 | 0 | 0 | 1 | -- d3 | 1 | 0 | 1 | 1 | 1 | ---------------------------------------------+ muxcontrol : process (sequence) is begin -- process muxcontrol case control_seq(sequence) is when 0 =3D> d0 <=3D '0'; d1 <=3D '0'; d2 <=3D '0'; d3 <=3D '1'; when 1 =3D> d0 <=3D '1'; d1 <=3D '1'; d2 <=3D '0'; d3 <=3D '0'; when 2 =3D> d0 <=3D '1'; d1 <=3D '1'; d2 <=3D '0'; d3 <=3D '1'; when 3 =3D> d0 <=3D '0'; d1 <=3D '1'; d2 <=3D '0'; d3 <=3D '1'; when others =3D> -- when 4 =3D> d0 <=3D '0'; d1 <=3D '0'; d2 <=3D '1'; d3 <=3D '1'; end case; end process muxcontrol; --shift register shifter : process (clk) is begin if rising_edge(clk) then -- rising clock edge case ext_control is when "00" =3D> -- stall when "01" =3D> -- shift shift_r(15) <=3D key_out_int; if (d2 =3D '0') then shift_r(3) <=3D key_out_int xor shift_r(4); else shift_r(3) <=3D shift_r(4); end if; when "10" =3D> -- load shift_r(15) <=3D key_in; shift_r(3) <=3D shift_r(4); when others =3D> -- load and shift, (used during -- simultaneous loading and unloading) shift_r(15) <=3D key_in; if (d2 =3D '0') then shift_r(3) <=3D key_out_int xor shift_r(4); else shift_r(3) <=3D shift_r(4); end if; end case; if (shift_in =3D '1' or load_in =3D '1') then for i in 4 to 14 loop shift_r(i) <=3D shift_r(i+1); end loop; -- i for i in 0 to 2 loop shift_r(i) <=3D shift_r(i+1); end loop; -- i end if; if (sequence =3D 0) then rotword_r <=3D shift_r(12); end if; end if; end process shifter; -- round constant "calculation" rcon : process (round_in) is begin -- process rcon case round_in is when "0000" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#01#, 8)); when "0001" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#02#, 8)); when "0010" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#04#, 8)); when "0011" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#08#, 8)); when "0100" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#10#, 8)); when "0101" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#20#, 8)); when "0110" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#40#, 8)); when "0111" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#80#, 8)); when "1000" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#1b#, 8)); when "1001" =3D> rcon_value <=3D std_logic_vector(to_unsigned(16#36#, 8)); when others =3D> rcon_value <=3D (others =3D> '-'); end case; end process rcon; end architecture fwd_rtl; From newsfish@newsfish Fri Feb 3 13:11:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!w9g2000prg.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: IEEE 1076.6-2004 support, understanding the examples Date: Tue, 15 Feb 2011 09:58:24 -0800 (PST) Organization: http://groups.google.com Lines: 83 Message-ID: References: NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297792704 32135 127.0.0.1 (15 Feb 2011 17:58:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 17:58:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000prg.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4760 Hi Guenter, A little history. 1076.6-1999 was a template based standard. For flip-flops there was a limited number of templates that a tool was required to support. When 1076.6-2004 was started we had to decide whether to add a limited number of additional templates - which would be tedious and require additional updates from time to time, or change to an algorithmic based description of the code. 1076.6-2004 chose to develop an algorithmic based description of the code. Note, I think it is ok if you support a superset of the standard as I think the language of the standard is, a tool shall support at least .... So a superset of the standard is still be compliant with the standard. I think the rules that were capture were thought of to be a line by line analysis. So looking at example 6 on page 11, the second assignment fails to be understood as a synchronous assignment from the perspective of the line by line analysis. OTOH, if you are building a graph based data structure of the code (as your webpage suggests), then your analysis will have a deeper understanding of the code. I would say this is a good thing. I suspect the rules still apply, however, you have a deeper understanding of what a synchronous and asynchronous assignment are - and as a result, in your world, example 6 on page 11 becomes legal. In my limited re-read of the standard text, it looks like your analysis is also a correct interpretation of the standard - as opposed to a superset. As I said, I am fairly certain the language committee (I was on the committee - it is just a long time ago) considered the analysis to be a line by line analysis and concluded, from that perspective, that example 6 is illegal. However, in the definitions, I do not see anything that makes a graph based analysis illegal and as a result my guess is that your conclusion is also valid and that from that perspective the example is legal. > Can anybody recommend a tool that is known to have good > 2004 support? When 1076.6-2004 was published, we did the normal rounds of papers to publicize it. However, it has gained little traction in the tool market. Vendors mostly have seemed to ignore its existence. Part of this is because of how vendors work - if there are no user requests for support, they don't implement it. Part of this is because how users work - hey it is a standard, the vendors will support it eventually right? If I had to guess, I expect Synplify to have some 2004 support. TO ALL: if you see value in 1076.6-2004, then let your vendors know that you want it supported. If you want something different or something additional, the committee needs to be reformed and the standard needs to be worked on. I can help you with this by giving guidance (I know the process well), however, I cannot do the work as I am already a over committed doing 1076 standard work. If you want my help, contact me directly via email as I don't read the news groups frequently enough. At this point 1076.6-2004 is a withdrawn standard - which means that anything is possible. One thing the standard touches on that we really need is a standard set of statemachine attributes/pragmas and memory modeling (RTL) attributes/pragmas. Best, Jim BTW, compliance claims to an IEEE standard are an interesting thing as there is no one who is in the role of confirming compliance. From newsfish@newsfish Fri Feb 3 13:11:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!8g2000prt.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: and bitwise operation on std_logic_vector bits Date: Tue, 15 Feb 2011 10:25:16 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: References: <8rt198F7tnU1@mid.dfncis.de> <647563e2-bdd3-4c8d-a7b5-2e460233f685@d28g2000yqc.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297794316 5096 127.0.0.1 (15 Feb 2011 18:25:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 18:25:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 8g2000prt.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4761 On Feb 15, 8:59=A0am, Thomas Stanka wrote: > On 14 Feb., 16:50, Hannes <"h.mcchoc"@gmx.de> wrote: > > > signal a : std_logic vector (3 downto 0); > > signal b : std_logic; > > > b <=3D a(0) or a(1) or a(2) or a(3); > > beside the defined reduce functions(see other post in this thread) you > could use a for-loop as generic solution to do bitwise reduction for > any function. > > for i in a'range loop > =A0 b_var :=3D b_var or a(i); > =A0 c_var :=3D my_function(c_var, a(i)); > end loop > > bye Thomas Don't forget to initialize b_var before entering the loop! Depending on the arbitrary function, the initialization value may differ. Hint: initialize it to first bit of a() and skip that bit in the loop. Andy From newsfish@newsfish Fri Feb 3 13:11:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!news2.glorb.com!postnews.google.com!y3g2000vbh.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Most popular VHDL/Verilog Followup-To: comp.lang.vhdl, comp.arch.fpga, comp.lang.verilog Date: Tue, 15 Feb 2011 11:29:04 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <3922c11a-eaa2-4352-bf78-0dec068960af@y3g2000vbh.googlegroups.com> NNTP-Posting-Host: 83.134.178.31 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297798144 17711 127.0.0.1 (15 Feb 2011 19:29:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 19:29:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y3g2000vbh.googlegroups.com; posting-host=83.134.178.31; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.94 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4762 comp.arch.fpga:14488 comp.lang.verilog:2812 Hi everybody. Could you please help me find out which is the most popular VHDL/ Verilog editor, by filling out this poll: http://www.vhdleditor.com/poll I'm not looking for the "best VHDL/Verilog editor" (that would only get a flame war started). I'm just trying to find out which is used more often. So, please go and vote! thanks Philippe From newsfish@newsfish Fri Feb 3 13:11:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!xlned.com!feeder3.xlned.com!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!d2g2000yqn.googlegroups.com!not-for-mail From: iamonion Newsgroups: comp.lang.vhdl Subject: unpredictable led output on nexys2 board Date: Tue, 15 Feb 2011 15:47:57 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <3f8cfe03-d1c1-4a67-bddc-dbfb92a66e6a@d2g2000yqn.googlegroups.com> NNTP-Posting-Host: 147.229.217.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297813678 30055 127.0.0.1 (15 Feb 2011 23:47:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Feb 2011 23:47:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d2g2000yqn.googlegroups.com; posting-host=147.229.217.49; posting-account=F3o-NAoAAACWr3Kw_9MiBLWzSGma4UcU User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; cs; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4763 Hi everyone! I'm learning to design PWM with nexys2 board and i've encountered very strange problem, I have one PWM that drives two LED-s, i program synthetised design by JTAG and everytime i load it, i observe one of two possible results: first... the expected one led 7 and led 4 lights up slowly, leds 6 and 5 are off as in code below: led(3 downto 1) <= pwm_out & pwm_out & pwm_out ; -- these leds work always ok led(0) <= slowclk; -- this led is ok too led(7 downto 4) <= pwm_out2 & '0' & '0' & pwm_out2; But sometimes led 7 has inverted driving so it is on at beginning and dims out and what is more weird led 6 is on, but it should be off, there's no special signal just '0' specified. There's also some self- test flashed to board, it's LED's work always as intended. Clock frequency of PWM is 50MHz. What could cause this problem? Thanks. Juraj Galbavy From newsfish@newsfish Fri Feb 3 13:11:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.tornevall.net!goblin1!goblin.stu.neva.ru!postnews.google.com!z20g2000yqe.googlegroups.com!not-for-mail From: iamonion Newsgroups: comp.lang.vhdl Subject: Re: unpredictable led output on nexys2 board Date: Tue, 15 Feb 2011 17:45:12 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: References: <3f8cfe03-d1c1-4a67-bddc-dbfb92a66e6a@d2g2000yqn.googlegroups.com> NNTP-Posting-Host: 147.229.217.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297820712 31976 127.0.0.1 (16 Feb 2011 01:45:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 16 Feb 2011 01:45:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z20g2000yqe.googlegroups.com; posting-host=147.229.217.49; posting-account=F3o-NAoAAACWr3Kw_9MiBLWzSGma4UcU User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; cs; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4764 Hello, I think i've solved my problem by moving one jumper pin from position slave serial to JTAG. Now after reset the default test is not run and i can transfer configuration many times with no defects on LED outputs, yet. As i realised before changing jumper, any design i tried to run had some chance to have led 7 and 6 outputs to be inverted both at the same time. Juraj On 16 =FAn, 00:47, iamonion wrote: > Hi everyone! > I'm learning to design PWM with nexys2 board and i've encountered very > strange problem, > I have one PWM that drives two LED-s, i program synthetised design by > JTAG and everytime i load it, i observe one of two possible results: > first... the expected one led 7 and led 4 lights up slowly, leds 6 and > 5 are off as in code below: > =A0 =A0 =A0 =A0 led(3 downto 1) <=3D pwm_out & pwm_out & pwm_out ; -- the= se leds work > always ok > =A0 =A0 =A0 =A0 led(0) <=3D slowclk; -- this led is ok too > =A0 =A0 =A0 =A0 led(7 downto 4) <=3D pwm_out2 & '0' & '0' & pwm_out2; > But sometimes led 7 has inverted driving so it is on at beginning and > dims out and what is more weird led 6 is on, but it should be off, > there's no special signal just '0' specified. There's also some self- > test flashed to board, it's LED's work always as intended. > Clock frequency of PWM is 50MHz. > What could cause this problem? > Thanks. > Juraj Galbavy From newsfish@newsfish Fri Feb 3 13:11:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4d5bd611$0$32470$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: and bitwise operation on std_logic_vector bits Newsgroups: comp.lang.vhdl Date: Wed, 16 Feb 2011 14:50:09 +0100 References: <8rt198F7tnU1@mid.dfncis.de> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 29 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1297864209 news.xs4all.nl 32470 puiterl/[::ffff:195.242.97.150]:36179 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4765 Hannes wrote: > Hello, > > I am relatively new to VHDL. > > I search for a command to realize a Boolean OR operation on all bits of > a std_logic_vector in a compact way. > > example: > > signal a : std_logic vector (3 downto 0); > signal b : std_logic; > > b <= a(0) or a(1) or a(2) or a(3); b <= '0' WHEN a = (a'range => '0') ELSE '1'; Caveat: it does not handle weak values such as 'L' and 'H'. If that is a concern, you can use: b <= '0' WHEN to_x01(a) = (a'range => '0') ELSE '1'; Function to_x01 is defined in ieee.std_logic_1164. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:11:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n10g2000yqf.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Case choice must be a locally static expression Date: Thu, 17 Feb 2011 00:39:03 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: NNTP-Posting-Host: 80.244.206.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297931943 21440 127.0.0.1 (17 Feb 2011 08:39:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Feb 2011 08:39:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqf.googlegroups.com; posting-host=80.244.206.7; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.1 STS-WEBGW, 1.1 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4766 Hi, I have searched the net for the above mentioned warning from Modelsim, but I cant really understand whats the problem. I have declared some constants in a package: Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6); Constant CONTREG : unsigned(5 downto 0):= To_unsigned(1,6); ..... They are used in a procedure in another entity: Procedure write_register is Begin case adr is when MASKREG => mask := shreg(mask'range); when CONTREG => cont := shreg(cont'range); when DEADTIMEREG => deadtime := shreg(deadtime'range); when FILTLOREG => filtlo := shreg(filtlo'range); when FILTHIREG => filthi := shreg(filthi'range); when MISCREG => misc := shreg(misc'range); when others => null; end case; End procedure write_register; Why is the case choice not considered locally static by Modelsim? Thanks in advance. /Peter From newsfish@newsfish Fri Feb 3 13:11:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!y26g2000yqd.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Thu, 17 Feb 2011 03:22:33 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: References: NNTP-Posting-Host: 80.244.206.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297941753 30508 127.0.0.1 (17 Feb 2011 11:22:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Feb 2011 11:22:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y26g2000yqd.googlegroups.com; posting-host=80.244.206.7; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.1 STS-WEBGW, 1.1 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4767 However, replacing then constant declaration with the code below, makes the warning disappear: Constant MASKREG : unsigned(5 downto 0):= "000000"; Constant CONTREG : unsigned(5 downto 0):= "000001"; So the problem seems to be the To_unsigned function? /Peter From newsfish@newsfish Fri Feb 3 13:11:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!o14g2000prb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Thu, 17 Feb 2011 06:13:34 -0800 (PST) Organization: http://groups.google.com Lines: 44 Message-ID: References: NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1297952074 32454 127.0.0.1 (17 Feb 2011 14:14:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Feb 2011 14:14:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000prb.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4768 On Feb 17, 8:39=A0am, Peter wrote: > Hi, > > I have searched the net for the above mentioned warning from Modelsim, > but I cant really understand whats the problem. > > I have declared some constants in a package: > > Constant MASKREG =A0 =A0 =A0 =A0: unsigned(5 downto 0):=3D To_unsigned(0,= 6); > Constant CONTREG =A0 =A0 =A0 =A0: unsigned(5 downto 0):=3D To_unsigned(1,= 6); > ..... > > They are used in a procedure in another entity: > > Procedure write_register is > Begin > =A0 =A0case adr is > =A0 =A0 =A0when MASKREG =A0 =A0 =A0 =A0=3D> =A0mask =A0 =A0 =A0:=3D shreg= (mask'range); > =A0 =A0 =A0when CONTREG =A0 =A0 =A0 =A0 =3D> =A0cont =A0 =A0 =A0 =A0:=3D = shreg(cont'range); > =A0 =A0 =A0when DEADTIMEREG =3D> =A0deadtime :=3D shreg(deadtime'range); > =A0 =A0 =A0when FILTLOREG =A0 =A0 =A0 =3D> =A0filtlo =A0 =A0 =A0 =A0 :=3D= shreg(filtlo'range); > =A0 =A0 =A0when FILTHIREG =A0 =A0 =A0 =A0=3D> =A0filthi =A0 =A0 =A0 =A0 := =3D shreg(filthi'range); > =A0 =A0 =A0when MISCREG =A0 =A0 =A0 =A0 =3D> =A0misc =A0 =A0 =A0 =A0:=3D = shreg(misc'range); > =A0 =A0 =A0when others =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> =A0null; > =A0 =A0end case; > End procedure write_register; > > Why is the case choice not considered locally static by Modelsim? > > Thanks in advance. > > /Peter Ive seen exactly the same warning with std_logic_vector constants declared in a package (and declared explicitly without a conversion function). I can only guess that its scared you could go and change the constant. But I dont get it. From newsfish@newsfish Fri Feb 3 13:11:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe30.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: In-Reply-To: Subject: Re: Case choice must be a locally static expression Lines: 1 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit Importance: Normal X-Newsreader: Microsoft Windows Live Mail 15.4.3508.1109 X-MimeOLE: Produced By Microsoft MimeOLE V15.4.3508.1109 X-Antivirus: avast! (VPS 110217-0, 17/02/2011), Outbound message X-Antivirus-Status: Clean Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe30.ams2 1297955186 213.105.6.183 (Thu, 17 Feb 2011 15:06:26 UTC) NNTP-Posting-Date: Thu, 17 Feb 2011 15:06:26 UTC Organization: virginmedia.com Date: Thu, 17 Feb 2011 15:05:55 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4769 >"Peter" wrote in message >news:bdeb4b98-df3c-442b-affc-dc412e06cf66@n10g2000yqf.googlegroups.com... > >Hi, > >I have searched the net for the above mentioned warning from Modelsim, >but I cant really understand whats the problem. > >I have declared some constants in a package: > >Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6); >Constant CONTREG : unsigned(5 downto 0):= To_unsigned(1,6); >..... > >They are used in a procedure in another entity: > >Procedure write_register is >Begin > case adr is > when MASKREG => mask := shreg(mask'range); > when CONTREG => cont := shreg(cont'range); > when DEADTIMEREG => deadtime := shreg(deadtime'range); > when FILTLOREG => filtlo := shreg(filtlo'range); > when FILTHIREG => filthi := shreg(filthi'range); > when MISCREG => misc := shreg(misc'range); > when others => null; > end case; >End procedure write_register; > >Why is the case choice not considered locally static by Modelsim? > >Thanks in advance. What happens if you compile under VHDL2008? (you need Modelsim 10.0) Hans www.ht-lab.com /Peter From newsfish@newsfish Fri Feb 3 13:11:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n18g2000vbq.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Thu, 17 Feb 2011 07:30:38 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> References: NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1297956638 12059 127.0.0.1 (17 Feb 2011 15:30:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Feb 2011 15:30:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n18g2000vbq.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4770 On 17 Feb., 15:13, Tricky wrote: > Ive seen exactly the same warning with std_logic_vector constants > declared in a package (and declared explicitly without a conversion > function). I can only guess that its scared you could go and change > the constant. But I dont get it. You actually could change the constant. It is possible to change package body. The same constants declared in the architecture which contains the case will avoid this error message. Before vhdl2008 this is one of the most crucial limitations for readablity in my opinion, that you are not allowed to use constants from packages as case-choice. Luckyly Modelsim does just warn, but uses the Constant. bye Thomas From newsfish@newsfish Fri Feb 3 13:11:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: Patrick Newsgroups: comp.lang.vhdl Subject: Hardware vs simulation mismatch problem Date: Thu, 17 Feb 2011 18:04:38 +0000 Organization: Aioe.org NNTP Server Lines: 115 Message-ID: NNTP-Posting-Host: Iw1Rg0XI7CrpPCPAVbzspw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) X-Notice: Filtered by postfilter v. 0.8.2 Xref: feeder.eternal-september.org comp.lang.vhdl:4771 Hi all, I have a very simple problem but I do not get my head around what is going wrong. Essentially, the whole thing works fine when simulating it, however, having it in hardware gives me the wrong result. Basically I have two ctrl signals that determine the behaviour of the entity: GET (ctrl = "00000000") sets register tx to input of op1 SH1_L (ctrl = "00000001") outputs (op1 << 1) or register tx shifts register tx to the right by 31 bits (tx >> 31) library ieee; use ieee.std_logic_1164.all; entity test is port ( op1 : in std_logic_vector(31 downto 0); -- Input operand ctrl : in std_logic_vector(7 downto 0); -- Control signal clk : in std_logic; -- clock res : out std_logic_vector(31 downto 0) -- Result ); end; architecture rtl of test is type res_sel_type is (GET, SH1_L); constant Z : std_logic_vector(31 downto 0) := (others => '0'); signal res_sel : res_sel_type; signal load : std_logic := '0'; signal shl : std_logic := '0'; signal tx : std_logic_vector(31 downto 0) := (others => '0'); signal inp1 : std_logic_vector(31 downto 0) := (others => '0'); begin dec_op: process (ctrl, op1) begin res_sel <= GET; load <= '0'; shl <= '0'; inp1 <= ( others => '0'); case ctrl is -- store operand when "00000000" => inp1 <= op1; load <= '1'; res_sel <= GET; -- 1-bit left-shift with carry when "00000001" => inp1 <= op1; shl <= '1'; res_sel <= SH1_L; when others => -- Leave default values end case; end process; -- Selection of output sel_out: process (res_sel, inp1) begin case res_sel is when GET => NULL; when SH1_L => res <= ( inp1(30 downto 0) & '0' ) or tx; when others => res <= (others => '0'); end case; end process; sync: process(clk) begin if clk'event and clk = '1' then if load = '1' then tx <= op1; elsif shl = '1' then tx <= Z(30 downto 0) & op1(31); end if; end if; end process; end rtl; TESTPROGRAM GET 0 SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521 SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643e SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace As you can see, the last bit is wrong for some reason. I must have something wrong with the timing, so that the register tx is first written before it is acutally used in the computation of the output. Anyone an idea how to solve this problem? Many thanks! From newsfish@newsfish Fri Feb 3 13:11:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe28.ams2.POSTED!00000000!not-for-mail Reply-To: "HT-Lab" From: "HT-Lab" Newsgroups: comp.lang.vhdl References: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> In-Reply-To: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> Subject: Re: Case choice must be a locally static expression Lines: 1 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Newsreader: Microsoft Windows Live Mail 15.4.3508.1109 X-MimeOLE: Produced By Microsoft MimeOLE V15.4.3508.1109 X-Antivirus: avast! (VPS 110217-1, 17/02/2011), Outbound message X-Antivirus-Status: Clean Message-ID: NNTP-Posting-Host: 213.105.6.183 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe28.ams2 1297966921 213.105.6.183 (Thu, 17 Feb 2011 18:22:01 UTC) NNTP-Posting-Date: Thu, 17 Feb 2011 18:22:01 UTC Organization: virginmedia.com Date: Thu, 17 Feb 2011 18:21:39 -0000 Xref: feeder.eternal-september.org comp.lang.vhdl:4772 >"Thomas Stanka" wrote in message >news:1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com... > >On 17 Feb., 15:13, Tricky wrote: ..> >You actually could change the constant. It is possible to change >package body. >The same constants declared in the architecture which contains the >case will avoid this error message. > >Before vhdl2008 this is one of the most crucial limitations for >readablity in my opinion, that you are not allowed to use constants >from packages as case-choice. Luckyly Modelsim does just warn, but >uses the Constant. With VHDL2008 you also no longer get the warning, I just created a quick test case based on Peter's code and with Modelsim I get: D:\Modelsim>vcom -2002 locally_static.vhd Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010 -- Compiling entity x -- Compiling architecture rtl of x ** Warning: locally_static.vhd(18): Choice in CASE statement alternative must be locally static. D:\Modelsim>vcom -2008 locally_static.vhd Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010 -- Compiling entity x -- Compiling architecture rtl of x Simple testcase shown below, Hans www.ht-lab.com library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity x is end x; architecture rtl of x is constant maskreg : unsigned(5 downto 0):= to_unsigned(0,6); signal shreg : unsigned(5 downto 0); procedure write_register(adr:in unsigned(5 downto 0)) is variable mask:unsigned(5 downto 0); begin case adr is when maskreg => mask := shreg(mask'range); -- Line18 when others => null; end case; end procedure write_register; begin end rtl; >bye Thomas From newsfish@newsfish Fri Feb 3 13:11:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4d5dadfb$0$32470$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Hardware vs simulation mismatch problem Newsgroups: comp.lang.vhdl Date: Fri, 18 Feb 2011 00:23:38 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 132 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1297985019 news.xs4all.nl 32470 puiterl/[::ffff:195.242.97.150]:33827 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4773 Patrick wrote: > Hi all, > > I have a very simple problem but I do not get my head around what is > going wrong. Essentially, the whole thing works fine when simulating it, > however, having it in hardware gives me the wrong result. Basically I > have two ctrl signals that determine the behaviour of the entity: > > GET (ctrl = "00000000") sets register tx to input of op1 > SH1_L (ctrl = "00000001") outputs (op1 << 1) or register tx > shifts register tx to the right by 31 bits > (tx >> 31) > > > library ieee; > use ieee.std_logic_1164.all; > > entity test is > port > ( > op1 : in std_logic_vector(31 downto 0); -- Input operand > ctrl : in std_logic_vector(7 downto 0); -- Control signal > clk : in std_logic; -- clock > res : out std_logic_vector(31 downto 0) -- Result > ); > end; > > architecture rtl of test is > > type res_sel_type is (GET, SH1_L); > > constant Z : std_logic_vector(31 downto 0) := (others => '0'); > > signal res_sel : res_sel_type; > signal load : std_logic := '0'; > signal shl : std_logic := '0'; > > signal tx : std_logic_vector(31 downto 0) := (others => '0'); > signal inp1 : std_logic_vector(31 downto 0) := (others => '0'); > > begin > > dec_op: process (ctrl, op1) > begin > > res_sel <= GET; > load <= '0'; > shl <= '0'; > inp1 <= ( others => '0'); > > case ctrl is > > -- store operand > when "00000000" => > inp1 <= op1; > load <= '1'; > res_sel <= GET; > > -- 1-bit left-shift with carry > when "00000001" => > inp1 <= op1; > shl <= '1'; > res_sel <= SH1_L; > > when others => > -- Leave default values > > end case; > > end process; > > -- Selection of output > sel_out: process (res_sel, inp1) > begin > > case res_sel is > > when GET => NULL; > > when SH1_L => > res <= ( inp1(30 downto 0) & '0' ) or tx; > > when others => > res <= (others => '0'); > > end case; > > end process; > > sync: process(clk) > begin > if clk'event and clk = '1' then > if load = '1' then > tx <= op1; > elsif shl = '1' then > tx <= Z(30 downto 0) & op1(31); > end if; > end if; > end process; > > end rtl; > > TESTPROGRAM > > GET 0 > SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521 > SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643e > SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace > > As you can see, No, I haven't looked at the function of the code yet. > the last bit is wrong for some reason. I must have > something wrong with the timing, so that the register tx is first > written before it is acutally used in the computation of the output. > > Anyone an idea how to solve this problem? First of all: look at the synthesis report. I would expect at least a warning about tx: it is read in process sel_out and it is not in the sensitivity list. Secondly: why so many processes? It only complicates things. That's why I see at first glance. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:11:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Thu, 17 Feb 2011 23:33:53 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <1b14d7f6-b9fc-4438-9425-30cf731e76e2@d28g2000yqc.googlegroups.com> References: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> NNTP-Posting-Host: 80.244.206.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298014433 10480 127.0.0.1 (18 Feb 2011 07:33:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 18 Feb 2011 07:33:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=80.244.206.7; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.1 STS-WEBGW, 1.1 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4774 > > Before vhdl2008 this is one of the most crucial limitations for > readablity in my opinion, that you are not allowed to use constants > from packages as case-choice. Luckyly Modelsim does just warn, but > uses the Constant. > > bye Thomas But it seems as constants in a package are allowed in a case-choice, as long as I dont use the "to_unsigned" function? Constant MASKREG : unsigned(5 downto 0):= "000000"; -- Gives no warning Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6); -- Does The package is compiled first. Why is the compiler unable to know the value of the constant just because it was set by a function? And I tried to move the declaration into the architecture where it is used. It gives the same warning. Thanks gentlemen for Your interest, Peter From newsfish@newsfish Fri Feb 3 13:11:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!news2.arglkargh.de!news.litech.org!news.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!s11g2000yqc.googlegroups.com!not-for-mail From: Thomas Rouam Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Fri, 18 Feb 2011 01:36:06 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: <12cfcb6b-0c00-4084-95b5-f38b898f93d3@s11g2000yqc.googlegroups.com> References: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> <1b14d7f6-b9fc-4438-9425-30cf731e76e2@d28g2000yqc.googlegroups.com> NNTP-Posting-Host: 81.178.188.62 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298021769 28239 127.0.0.1 (18 Feb 2011 09:36:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 18 Feb 2011 09:36:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s11g2000yqc.googlegroups.com; posting-host=81.178.188.62; posting-account=vIhpkAoAAACV9wAJCuf6epqbjFtl8vtN User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; Media Center PC 6.0; MDDC),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4775 On Feb 18, 7:33=A0am, Peter wrote: > > Before vhdl2008 this is one of the most crucial limitations for > > readablity in my opinion, that you are not allowed to use constants > > from packages as case-choice. Luckyly Modelsim does just warn, but > > uses the Constant. > > > bye Thomas > > But it seems as constants in a package are allowed in a case-choice, > as long as I dont use the "to_unsigned" function? > > Constant MASKREG =A0 =A0 =A0 =A0: unsigned(5 downto 0):=3D "000000"; =A0 = =A0 =A0 =A0 -- > Gives no warning > Constant MASKREG =A0 =A0 =A0 =A0: unsigned(5 downto 0):=3D To_unsigned(0,= 6); -- > Does > > The package is compiled first. Why is the compiler unable to know the > value of the constant just because it was set by a function? > > And I tried to move the declaration into the architecture where it is > used. It gives the same warning. > > Thanks gentlemen for Your interest, > > Peter Hi Peter, The simple use of a function defined in a package makes your constant non locally static. On the other hand, it is globally static because it can resolve the constant value without having to "run" the design. Unfortunately for you, the case wants to be able to know the value within the entity it is used which is not the case. Regards, Thomas From newsfish@newsfish Fri Feb 3 13:11:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!b15g2000pra.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Fri, 18 Feb 2011 15:22:36 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <063756da-af99-4f44-8234-455c96c74805@b15g2000pra.googlegroups.com> References: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> <1b14d7f6-b9fc-4438-9425-30cf731e76e2@d28g2000yqc.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298071356 24688 127.0.0.1 (18 Feb 2011 23:22:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 18 Feb 2011 23:22:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b15g2000pra.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4776 Hi Peter, This was addressed in the VHDL-2008 revision. There were a couple of changes to the language that now allow this to be locally static. Turn on the 2008 switch in modelsim. Double check that it works in your synthesis tool (or tools if you are making an FPGA then an ASIC) and you should be ok. Best, Jim From newsfish@newsfish Fri Feb 3 13:11:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k15g2000prk.googlegroups.com!not-for-mail From: Rejin James Newsgroups: comp.lang.vhdl Subject: Re: Project help Date: Sun, 20 Feb 2011 07:47:43 -0800 (PST) Organization: http://groups.google.com Lines: 569 Message-ID: <5f825453-2660-4599-9af5-177ac0f2163f@k15g2000prk.googlegroups.com> References: <01983fcc-3f1c-4bfc-bafb-47b5f8973e66@y19g2000prb.googlegroups.com> <6a91b19e-daf6-43a4-b51b-3772da5c2fe1@k21g2000prb.googlegroups.com> <4013774f-e2e6-40eb-ba45-87cbdd44e90f@w19g2000yqa.googlegroups.com> <9d44362b-281f-4974-8368-c825a3714162@s18g2000vbe.googlegroups.com> <1ba6a96b-8f3e-4f1d-83bd-512e0dbe66f7@o18g2000prh.googlegroups.com> NNTP-Posting-Host: 115.242.197.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298216972 13077 127.0.0.1 (20 Feb 2011 15:49:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Feb 2011 15:49:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k15g2000prk.googlegroups.com; posting-host=115.242.197.78; posting-account=sVZi6woAAAALUtg7YjdT9QJbVW4okBS2 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.1.4) Gecko/20091016 FireDownload/2.0.1 Firefox/3.5.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4777 On Feb 15, 10:31=A0pm, Rejin James wrote: > On Jan 28, 12:57=A0pm, backhus wrote: > > > On 28 Jan., 05:31, Rejin James wrote: > > > > On Jan 27, 12:29=A0pm, backhus wrote: > > > > > On 26 Jan., 13:32, Rejin James wrote: > > > > > > On Jan 26, 1:10=A0pm, backhus wrote: > > > > > > > On 25 Jan., 06:49, Rejin James wrote: > > > > > > > > Hi Friends I am currently doin my university project on the t= opic > > > > > > > Low Power AES algorithm using VHDL > > > > > > > > I was having problems understanding the logic of Mixcolumns o= peration > > > > > > > in GALIOS FIELD and other parts of the algorithm like galios = field > > > > > > > multiplication and key expansion. > > > > > > > Can anyone help me out >?? > > > > > > > > this is the base paper im followingwww.martes-itea.org/.../Ha= malainen-Design_and_Implementation_2.pdf > > > > > > > > actually i got the cores from their website and was having a = problem > > > > > > > in understanding it . > > > > > > > They are using 8- bit data paths and i was having problems in > > > > > > > understanding their architecture and implementation in VHDl. > > > > > > > > The following is the code for mixcolumns operation . can some= body help > > > > > > > me out with it ?? > > > > > > > i was not understanding the GALIOS FIELD multiplication conce= pt. > > > > > > > > library ieee; > > > > > > > use ieee.std_logic_1164.all; > > > > > > > > entity mixcolumns is > > > > > > > =A0 port( > > > > > > > =A0 =A0 clk =A0 =A0 =A0 =A0: in =A0std_logic; > > > > > > > =A0 =A0 start_in =A0 : in =A0std_logic; > > > > > > > =A0 =A0 inverse_in : in =A0std_logic; =A0 =A0 =A0 =A0 -- '1' = =3D inverse > > > > > > > transformation > > > > > > > > =A0 =A0 data_in =A0 =A0: in =A0std_logic_vector (7 downto 0);= =A0-- input data > > > > > > > =A0 =A0 data0_out =A0: out std_logic_vector (7 downto 0); =A0= -- output data > > > > > > > =A0 =A0 data1_out =A0: out std_logic_vector (7 downto 0); =A0= -- output data > > > > > > > =A0 =A0 data2_out =A0: out std_logic_vector (7 downto 0); =A0= -- output data > > > > > > > =A0 =A0 data3_out =A0: out std_logic_vector (7 downto 0) =A0 = -- output data > > > > > > > =A0 =A0 ); > > > > > > > end mixcolumns; > > > > > > > > -- fwd_rtl =3D forward only > > > > > > > architecture fwd_rtl of mixcolumns is > > > > > > > > =A0 -- GF(2^8) multiplication with constant: x > > > > > > > =A0 -- reduction polynomial is x^8 + x^4 + x^3 + x + 1 > > > > > > > =A0 function gf256_mul2 (a : std_logic_vector(7 downto 0)) > > > > > > > =A0 =A0 return std_logic_vector is > > > > > > > =A0 =A0 variable b : std_logic_vector(7 downto 0); > > > > > > > =A0 begin > > > > > > > =A0 =A0 b(0) :=3D a(7); > > > > > > > =A0 =A0 b(1) :=3D a(0) xor a(7); > > > > > > > =A0 =A0 b(2) :=3D a(1); > > > > > > > =A0 =A0 b(3) :=3D a(2) xor a(7); > > > > > > > =A0 =A0 b(4) :=3D a(3) xor a(7); > > > > > > > =A0 =A0 b(5) :=3D a(4); > > > > > > > =A0 =A0 b(6) :=3D a(5); > > > > > > > =A0 =A0 b(7) :=3D a(6); > > > > > > > =A0 =A0 return b; > > > > > > > =A0 end; > > > > > > > > =A0 type =A0 accum_array_t is array (0 to 3) of std_logic_vec= tor(7 downto > > > > > > > 0); > > > > > > > =A0 signal accum_r : accum_array_t; > > > > > > > > =A0 signal prod2, prod3 : std_logic_vector(7 downto 0); > > > > > > > =A0 signal x =A0 =A0 =A0 =A0 =A0 : std_logic_vector(7 downto = 0); > > > > > > > > begin =A0-- rtl > > > > > > > > =A0 assert (inverse_in /=3D '1') report "this architecture su= pports only > > > > > > > forward operation" > > > > > > > =A0 =A0 severity failure; > > > > > > > =A0 x <=3D data_in; > > > > > > > > =A0 prod2 <=3D gf256_mul2(x); > > > > > > > =A0 prod3 <=3D prod2 xor x; > > > > > > > > =A0 -- forward transform: > > > > > > > =A0 -- > > > > > > > =A0 -- x0 =A0 |02 03 01 01| y0 > > > > > > > =A0 -- x1 =3D |01 02 03 01|*y1 > > > > > > > =A0 -- x2 =A0 |01 01 02 03| y2 > > > > > > > =A0 -- x3 =A0 |03 01 01 02| y3 > > > > > > > > =A0 -- inverse transform > > > > > > > =A0 -- y0 =A0 |0e 0b 0d 09| x0 > > > > > > > =A0 -- y1 =3D |09 0e 0b 0d|*x1 > > > > > > > =A0 -- y2 =A0 |0d 09 0e 0b| x2 > > > > > > > =A0 -- y3 =A0 |0b 0d 09 0e| x3 > > > > > > > > =A0 clocked : process (clk) > > > > > > > =A0 begin =A0-- process clocked > > > > > > > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- ri= sing clock edge > > > > > > > =A0 =A0 =A0 if (start_in =3D '1') then > > > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x; > > > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x; > > > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3; > > > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2; > > > > > > > =A0 =A0 =A0 else > > > > > > > =A0 =A0 =A0 =A0 accum_r(0) <=3D x xor accum_r(1); > > > > > > > =A0 =A0 =A0 =A0 accum_r(1) <=3D x xor accum_r(2); > > > > > > > =A0 =A0 =A0 =A0 accum_r(2) <=3D prod3 xor accum_r(3); > > > > > > > =A0 =A0 =A0 =A0 accum_r(3) <=3D prod2 xor accum_r(0); > > > > > > > =A0 =A0 =A0 end if; > > > > > > > =A0 =A0 end if; > > > > > > > =A0 end process clocked; > > > > > > > > =A0 data0_out <=3D accum_r(0); > > > > > > > =A0 data1_out <=3D accum_r(1); > > > > > > > =A0 data2_out <=3D accum_r(2); > > > > > > > =A0 data3_out <=3D accum_r(3); > > > > > > > > end fwd_rtl; > > > > > > > > ANY HELP WOULD BE APPRECIATED .. thanks > > > > > > > Hi, > > > > > > that's a lot of questions at once. :-) > > > > > > Galois Field math is a topic for 10th semester math students. > > > > > > So don't be bothered when it seems complicated to understand. > > > > > > In some VERY simple words: The galois field is a limited bunch = of > > > > > > numbers, that obeys defined mathematical rules. > > > > > > This is only possible because he operations can always be seen = as > > > > > > modulo operations in order to keep the number space constant. > > > > > > When you chop down the field size to tw0 you can work with simp= le gate > > > > > > functions (AND and XOR) for multiplication and addition. > > > > > > > Mix columns is an ordinary vector/matrix multiplication, where = you > > > > > > multiply a row of the input matrix with a given transformation > > > > > > matrix. > > > > > > The result is then written to a column of the result matrix. > > > > > > > The code you provided has one strange property. > > > > > > It takes a single stream of data (data_in) and creates four res= ult > > > > > > values. > > > > > > You need to find out in which order the input stram has to prov= ide the > > > > > > data of the input matrix (and when to apply start_in) > > > > > > and what to do with the four result values. > > > > > > > Maybe you should take a look ath this book: > > > > > > The Design of Rijndael: AES. TheAdvanced Encryption Standard > > > > > > Written by the designers of the algorithm. > > > > > > There you find many examples and calculations that you can comp= are > > > > > > with your simulations, in order to understand how the code work= s that > > > > > > you have. > > > > > > > Have a nice simulation > > > > > > =A0 Eilert > > > > > > Hey Eilert, > > > > > Thanks a lot for the reply. :-) > > > > > > i went through the galois Field multiplication once more from a b= ook > > > > > on cryptography and got a basic idea as to wat happens in that. > > > > > > The reason dat the code only takes one input is because i am > > > > > implementing Aes algorithm with 8 bit DAta path (data input) > > > > > And according to the paper that i am using the mix columns multip= lier > > > > > unit takes in the 8 bit data and produces 32 bit output which is = then > > > > > given to a parallel to serial converter. > > > > > > If u cud see the base paper which i was referring once then i gue= ss u > > > > > wud understand it better. Coz i was not able to understand much. > > > > > > And i also understood when to apply start_in. it helps us to cont= rol > > > > > operation of mixcolumns for encryption or decryption. > > > > > when start_in is not one it signifies we want to do the inverse > > > > > operation i.e. decryption. > > > > > Hi, > > > > you confused start_in with inverse_in. > > > > Also inverse_in has to be '1' all the time since the code doesn't > > > > suport the inverse transformation. > > > > (Look at the assert statement) > > > > > In the mentioned paper there is a signal mentioned called "en". > > > > That's probably called start_in in the provided source now. > > > > > It has to be applied "During inputting the first byte of a column > > > > (bytes 0, 4, 8, and 12 in Fig. 1)" > > > > as mentioned in the paper. > > > > It seems like the results have to be taken after every four clock > > > > cycles. > > > > So, start in can be also used for the following stage to take over = the > > > > results from the mix column stage. > > > > > If you have the full sources of that project, there should be some > > > > design unit that controlls the datapath. > > > > Some kind of FSM. By analysing that you probably gain more detailed > > > > insights how the whole thing works. > > > > > Have a nice synthesis > > > > =A0 Eilert > > > > Hi, > > > i think when inverse_in is 1 it means reverse process i.e decryption. > > > it was given as comment somewhere in the full sources. > > > As for start _in i think u are right. But the things mentioned about > > > taking data byte by byte is not making sense to me as the input that > > > we feed is 8-bit(i.e 1 byte) so how come rest of the bytes are coming= . > > > And how can one make The state when input is only 8-bit ? > > > > Here is the link for the full source.http://www.tkt.cs.tut.fi/researc= h/daci/ra_security_8bit_aes_hw.html > > > > Thanks for your help. > > > I did not go through the top level. Ill try to go through it and > > > understand. > > > If u could also just take a look it would be a big help. > > > Thanks Eilert > > > Rejin > > > Hi Rejin, > > the README file in the sources sais it's only an encryption core, and > > also the paper mentiones only encryption in the tables. > > And even the sources say that the inverse algorithm (needed for > > decryption) is not implemented. > > So no chance for generating the inverse algorithm. > > > The AES state matrix consists of 16 bytes. > > So for each operation, 16 bytes have to be provided. > > This implementation works in a "byteserial" manner, that mewans you > > have to provide all the bytes on 16 consecutive clock cycles. > > (The same applies to the key matrix) > > > Look at the main file aes.vhd. > > there you find the processes > > =A0 control_clocked > > and > > =A0 control_comb. > > > These are a 2-process implementation of the controlling FSM. > > The signal sequence_r there counts the state matrix position that's > > been worked on. > > Furthermore there's a signal round, that counts the rounds of the AES > > algorithm. > > Depending on the data- and keywidth the input data has to iterate 8 to > > 14 times through the algorithm. > > (and the fist or last round is treated special, depending wether you > > do en- or decryption) > > > So, by further analysing this part of the code you can learn how to > > feed data into the core, and when to read out the results. > > Maybe you could start with reconstructing the state diagramm from the > > vhdl source, so you have a graphical point of orientation. > > > Also there are three testbenches. > > I think you can see how to controll the input data pretty well by > > looking at this part of the code from aes_tb_test1.vhd: > > > -----------------------------------------------------------------------= -- > > > =A0 =A0 =A0 -- encrypt > > > -----------------------------------------------------------------------= -- > > > =A0 =A0 =A0 -- load input > > > =A0 =A0 =A0 for i in 0 to 15 loop > > > =A0 =A0 =A0 =A0 wait until falling_edge(clk); > > > =A0 =A0 =A0 =A0 inverse_in <=3D '0'; > > > =A0 =A0 =A0 =A0 load_in =A0 =A0<=3D '1'; > > > =A0 =A0 =A0 =A0 data_in <=3D std_logic_vector(to_unsigned(ptext(t)(i), = 8)); > > > =A0 =A0 =A0 =A0 key_in =A0<=3D std_logic_vector(to_unsigned(key_fwd(t)(= i), 8)); > > > =A0 =A0 =A0 end loop; =A0-- i > > > =A0 =A0 =A0 wait until falling_edge(clk); > > > =A0 =A0 =A0 load_in =A0<=3D '0'; > > > =A0 =A0 =A0 start_in <=3D '1'; > > > =A0 =A0 =A0 wait until falling_edge(clk); > > > =A0 =A0 =A0 start_in <=3D '0'; > > > =A0 =A0 =A0 -- compute > > > =A0 =A0 =A0 wait until rising_edge(clk) and busy_out =3D '0'; > > > =A0 =A0 =A0 -- read output & check result > > > =A0 =A0 =A0 wait until falling_edge(clk); > > > =A0 =A0 =A0 unload_in <=3D '1'; > > > =A0 =A0 =A0 for i in 0 to 15 loop > > > =A0 =A0 =A0 =A0 wait until rising_edge(clk); > > > =A0 =A0 =A0 =A0 assert ctext(t)(i) =3D to_integer(unsigned(data_out)) > > > =A0 =A0 =A0 =A0 =A0 report "forward failed" severity error; > > > =A0 =A0 =A0 end loop; =A0-- i > > > =A0 =A0 =A0 unload_in <=3D '0'; > > > =A0 =A0 =A0 wait until rising_edge(clk); > > > Have a nice simulation > > =A0 Eilert > > Hi eilert.. > so sorry for replying so late.. > had takena mini vacation ;).. > > Ya i got the inputting part.. > im not sure whether ill be able to reconstruct the FSM ., ill try.. > Currently i was doing the key expansion unit and was facing problems > understanding this part of the core.. > im gettin confused as to wen and during wich clock puse we have 2 send > key)_in to the key expansion unit and during which clock pulse we send > data to sbox and retrieve from it.. > a further thing i noticed is that according to the table given for key > expansion the data is supposed 2 shift and replaced by new data, but > somehow i dint notice it actually happening,, > if u cud just explain the code a lil... > > architecture fwd_rtl of keyexpansion is > > =A0 type control_seq_t is array (0 to 15) of integer range 0 to 4; > =A0 constant control_seq : control_seq_t :=3D (1, 2, 2, 3, 0, 0, 0, 0, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A00, 0, 0, 0, 4, 4, 4, 4); > =A0 signal sequence : integer range 0 to 15; > > =A0 type shiftreg_t is array (0 to 15) of std_logic_vector(7 downto 0); > > =A0 signal shift_r =A0 =A0: shiftreg_t; > =A0 signal rcon_value : std_logic_vector(7 downto 0); > > =A0 -- storage for key byte required for RotWord() -operation. > =A0 signal rotword_r : std_logic_vector(7 downto 0); > > =A0 signal d0, d1, d2 : std_logic; =A0 =A0 =A0 =A0-- mux control signals > =A0 signal d3 =A0 =A0 =A0 =A0 : std_logic; =A0 =A0 =A0 =A0-- '1' =3D sign= al "rcon_value" > is zeroed > > =A0 -- key byte output (also fed back to shift register) > =A0 signal key_out_int : std_logic_vector(7 downto 0); > > =A0 signal ext_control : std_logic_vector(1 downto 0); > > begin =A0-- architecture rtl > > =A0 key_out =A0 =A0<=3D key_out_int; > =A0 key_d4_out <=3D shift_r(12); > > =A0 --mux0 > =A0 data_to_sbox_out <=3D shift_r(13) when d0 =3D '1' else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rotword_r; > =A0 --mux1 and rcon xor > =A0 key_out_int <=3D data_from_sbox_in xor rcon_value xor shift_r(0) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0when (d1 =3D '1' and d3 =3D '0') else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0data_from_sbox_in xor shift_r(0) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0when (d1 =3D '1' and d3 =3D '1') else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0shift_r(0); > > =A0 ext_control(1) <=3D load_in; > =A0 ext_control(0) <=3D shift_in; > > =A0 sequence <=3D to_integer(unsigned(seq_in)); > > =A0 -- inverse is not implemented in this architecture > =A0 assert (inverse_in /=3D '1') report "inverse operation not supported" > severity warning; > > =A0 ---------------------------------------------+ > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0control =A0 =A0 =A0 = =A0 =A0 =A0| > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 | =A00 =A0| =A01 =A0| =A02 =A0| =A03 =A0| = =A04 =A0| > =A0 ---------------+-----+-----+-----+-----+-----| > =A0 -- =A0 =A0d0 =A0 =A0 =A0 | =A00 =A0| =A01 =A0| =A01 =A0| =A00 =A0| = =A00 =A0| > =A0 -- =A0 =A0d1 =A0 =A0 =A0 | =A00 =A0| =A01 =A0| =A01 =A0| =A01 =A0| = =A00 =A0| > =A0 -- =A0 =A0d2 =A0 =A0 =A0 | =A00 =A0| =A00 =A0| =A00 =A0| =A00 =A0| = =A01 =A0| > =A0 -- =A0 =A0d3 =A0 =A0 =A0 | =A01 =A0| =A00 =A0| =A01 =A0| =A01 =A0| = =A01 =A0| > =A0 ---------------------------------------------+ > =A0 muxcontrol : process (sequence) is > =A0 begin =A0-- process muxcontrol > =A0 =A0 case control_seq(sequence) is > =A0 =A0 =A0 when 0 =3D> > =A0 =A0 =A0 =A0 d0 <=3D '0'; > =A0 =A0 =A0 =A0 d1 <=3D '0'; > =A0 =A0 =A0 =A0 d2 <=3D '0'; > =A0 =A0 =A0 =A0 d3 <=3D '1'; > > =A0 =A0 =A0 when 1 =3D> > =A0 =A0 =A0 =A0 d0 <=3D '1'; > =A0 =A0 =A0 =A0 d1 <=3D '1'; > =A0 =A0 =A0 =A0 d2 <=3D '0'; > =A0 =A0 =A0 =A0 d3 <=3D '0'; > > =A0 =A0 =A0 when 2 =3D> > =A0 =A0 =A0 =A0 d0 <=3D '1'; > =A0 =A0 =A0 =A0 d1 <=3D '1'; > =A0 =A0 =A0 =A0 d2 <=3D '0'; > =A0 =A0 =A0 =A0 d3 <=3D '1'; > > =A0 =A0 =A0 when 3 =3D> > =A0 =A0 =A0 =A0 d0 <=3D '0'; > =A0 =A0 =A0 =A0 d1 <=3D '1'; > =A0 =A0 =A0 =A0 d2 <=3D '0'; > =A0 =A0 =A0 =A0 d3 <=3D '1'; > > =A0 =A0 =A0 when others =3D> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- wh= en 4 =3D> > =A0 =A0 =A0 =A0 d0 <=3D '0'; > =A0 =A0 =A0 =A0 d1 <=3D '0'; > =A0 =A0 =A0 =A0 d2 <=3D '1'; > =A0 =A0 =A0 =A0 d3 <=3D '1'; > > =A0 =A0 end case; > =A0 end process muxcontrol; > > =A0 --shift register > =A0 shifter : process (clk) is > =A0 begin > =A0 =A0 if rising_edge(clk) then =A0 =A0 =A0 =A0 =A0 =A0-- rising clock e= dge > =A0 =A0 =A0 case ext_control is > =A0 =A0 =A0 =A0 when "00" =3D> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- = stall > > =A0 =A0 =A0 =A0 when "01" =3D> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- = shift > =A0 =A0 =A0 =A0 =A0 shift_r(15) <=3D key_out_int; > =A0 =A0 =A0 =A0 =A0 if (d2 =3D '0') then > =A0 =A0 =A0 =A0 =A0 =A0 shift_r(3) <=3D key_out_int xor shift_r(4); > =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 shift_r(3) <=3D shift_r(4); > =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 when "10" =3D> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- = load > =A0 =A0 =A0 =A0 =A0 shift_r(15) <=3D key_in; > =A0 =A0 =A0 =A0 =A0 shift_r(3) =A0<=3D shift_r(4); > > =A0 =A0 =A0 =A0 when others =3D> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- lo= ad and shift, (used > during > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 -- simultaneous loading and > unloading) > =A0 =A0 =A0 =A0 =A0 shift_r(15) <=3D key_in; > =A0 =A0 =A0 =A0 =A0 if (d2 =3D '0') then > =A0 =A0 =A0 =A0 =A0 =A0 shift_r(3) <=3D key_out_int xor shift_r(4); > =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 shift_r(3) <=3D shift_r(4); > =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 end case; > > =A0 =A0 =A0 if (shift_in =3D '1' or load_in =3D '1') then > =A0 =A0 =A0 =A0 for i in 4 to 14 loop > =A0 =A0 =A0 =A0 =A0 shift_r(i) <=3D shift_r(i+1); > =A0 =A0 =A0 =A0 end loop; =A0-- i > > =A0 =A0 =A0 =A0 for i in 0 to 2 loop > =A0 =A0 =A0 =A0 =A0 shift_r(i) <=3D shift_r(i+1); > =A0 =A0 =A0 =A0 end loop; =A0-- i > > =A0 =A0 =A0 end if; > > =A0 =A0 =A0 if (sequence =3D 0) then > =A0 =A0 =A0 =A0 rotword_r <=3D shift_r(12); > =A0 =A0 =A0 end if; > > =A0 =A0 end if; > =A0 end process shifter; > > -- round constant "calculation" > =A0 rcon : process (round_in) is > =A0 begin =A0-- process rcon > =A0 =A0 case round_in is > =A0 =A0 =A0 when "0000" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#01#, 8)); > =A0 =A0 =A0 when "0001" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#02#, 8)); > =A0 =A0 =A0 when "0010" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#04#, 8)); > =A0 =A0 =A0 when "0011" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#08#, 8)); > =A0 =A0 =A0 when "0100" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#10#, 8)); > =A0 =A0 =A0 when "0101" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#20#, 8)); > =A0 =A0 =A0 when "0110" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#40#, 8)); > =A0 =A0 =A0 when "0111" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#80#, 8)); > =A0 =A0 =A0 when "1000" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#1b#, 8)); > =A0 =A0 =A0 when "1001" =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D std_logic_vector(to_unsigned(16#36#, 8)); > =A0 =A0 =A0 when others =3D> > =A0 =A0 =A0 =A0 rcon_value <=3D (others =3D> '-'); > =A0 =A0 end case; > =A0 end process rcon; > > end architecture fwd_rtl; Hi I figured out the operation of the mux controls but im having trouble understanding the shift register process in the key expansion unit. Also im having lil trouble trying to understand the loading and unloading proces.. If someone could pls help me out it wud be a great help.. Thank you Rejin From newsfish@newsfish Fri Feb 3 13:11:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f30g2000yqa.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Case choice must be a locally static expression Date: Mon, 21 Feb 2011 03:09:10 -0800 (PST) Organization: http://groups.google.com Lines: 19 Message-ID: <940916b1-3bb3-4db7-bb4a-f1074e044b39@f30g2000yqa.googlegroups.com> References: <1b7be015-e1bc-434d-b93f-75346f7ee322@n18g2000vbq.googlegroups.com> <1b14d7f6-b9fc-4438-9425-30cf731e76e2@d28g2000yqc.googlegroups.com> <063756da-af99-4f44-8234-455c96c74805@b15g2000pra.googlegroups.com> NNTP-Posting-Host: 80.244.206.7 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298286550 9526 127.0.0.1 (21 Feb 2011 11:09:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 21 Feb 2011 11:09:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f30g2000yqa.googlegroups.com; posting-host=80.244.206.7; posting-account=-xRUXQkAAABLc5XmaAf5LkAukNsvCfNI User-Agent: G2/1.0 X-HTTP-Via: 1.1 STS-WEBGW, 1.1 STS-ISA X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; InfoPath.1; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4778 On 19 Feb, 00:22, JimLewis wrote: > Hi Peter, > This was addressed in the VHDL-2008 revision. =A0There were a > couple of changes to the language that now allow this to be > locally static. > > Turn on the 2008 switch in modelsim. =A0Double check that it works > in your synthesis tool (or tools if you are making an FPGA then > an ASIC) and you should be ok. > > Best, > Jim Thanks! Regards, Peter From newsfish@newsfish Fri Feb 3 13:11:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Trygve_Laugst=F8l?= Newsgroups: comp.lang.vhdl Subject: Re: Programmable Logic at StackExchange Date: Mon, 21 Feb 2011 06:43:41 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <6d9e46e3-e9b8-43aa-bb05-9c74777d2b71@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 85.19.69.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298299557 6529 127.0.0.1 (21 Feb 2011 14:45:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 21 Feb 2011 14:45:57 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.19.69.42; posting-account=UuG_LwoAAABVo101RSSamuvnISa0weGs User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4779 On Friday, November 12, 2010 12:43:05 AM UTC+1, Jonathan Ross wrote: > Someone recently added a Programmable Logic Stack on Stack Exchange, > and it needs more followers to get official status. As most VHDL > developers can attest, getting information can be difficult, and these > stack sites (the original is StackOverflow.com) are immensely useful. >=20 > The site can be found here: http://area51.stackexchange.com/proposals/206= 32/programmable-logic-and-fpga-design >=20 > Someone tried to start a VHDL stack but it was too specific and was > pruned. I've committed to the proposal and hope it will go through. The stackexchan= ge community is a very nice way to ask specific questions. I've been follow= ing the electronics [1] area for a while and it is a valuable resource for = both newcomers and old-timers. /me cheers for more commitment to the propos= al. [1]: http://electronics.stackexchange.com/ --=20 Trygve From newsfish@newsfish Fri Feb 3 13:11:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: =?ISO-8859-1?Q?Trygve_Laugst=F8l?= Newsgroups: comp.lang.vhdl Subject: Re: Programmable Logic at StackExchange Date: Mon, 21 Feb 2011 06:46:49 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <6bb98368-f963-439f-a437-6c7585940caa@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 85.19.69.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298299634 13821 127.0.0.1 (21 Feb 2011 14:47:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 21 Feb 2011 14:47:14 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=85.19.69.42; posting-account=UuG_LwoAAABVo101RSSamuvnISa0weGs User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4780 On Friday, November 12, 2010 12:43:05 AM UTC+1, Jonathan Ross wrote: > Someone recently added a Programmable Logic Stack on Stack Exchange, > and it needs more followers to get official status. As most VHDL > developers can attest, getting information can be difficult, and these > stack sites (the original is StackOverflow.com) are immensely useful. >=20 > The site can be found here: http://area51.stackexchange.com/proposals/206= 32/programmable-logic-and-fpga-design >=20 > Someone tried to start a VHDL stack but it was too specific and was > pruned. I've committed to the proposal and hope it will go through. The stackexchan= ge community is a very nice way to ask specific questions. I've been follow= ing the electronics [1] area for a while and it is a valuable resource for = both newcomers and old-timers. /me cheers for more commitment to the propos= al. [1]: http://electronics.stackexchange.com/ --=20 Trygve From newsfish@newsfish Fri Feb 3 13:11:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!n16g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Next VHDL-201X meeting Date: Mon, 21 Feb 2011 13:22:00 -0800 (PST) Organization: http://groups.google.com Lines: 26 Message-ID: <827645ea-871a-4d29-9707-f795fab06c11@n16g2000prc.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298323321 11890 127.0.0.1 (21 Feb 2011 21:22:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 21 Feb 2011 21:22:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n16g2000prc.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4781 Hi, The IEEE VHDL Analysis and Standardization Group (VASG) is in the preliminary stages of discussing items to be considered for the next VHDL standard. Anyone with a vested interest in VHDL is welcome to join the reflector and either observe or participate in the discussion. I would particularly encourage all experienced VHDL design and verification engineers to join. To join the working group reflector, see the following link: http://www.eda.org/vasg/index.html#Participation _Next Meeting_: Thursday March 3 at 8 am Pacific This is a phone conference. See reflector for dial-in details. _Homework_ due Thursday March 3: Post your change requirement list to the reflector. _minutes from previous meetings are here_: http://www.eda.org/vasg/meetings/ Best, Jim Lewis VHDL Study Group Chair From newsfish@newsfish Fri Feb 3 13:11:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: fido t Newsgroups: comp.lang.vhdl Subject: bIDIRECTIONAL hift register Date: Mon, 21 Feb 2011 19:53:24 -0800 (PST) Organization: http://groups.google.com Lines: 2 Message-ID: <650d66d6-a174-4e06-b56f-01f83b5b5057@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 125.19.237.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298346804 32727 127.0.0.1 (22 Feb 2011 03:53:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 03:53:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=125.19.237.34; posting-account=l3UZoQoAAAB6TFdWGnSwSK0gecqg5kxy User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4782 Hello, I'm unable to design an architectural layout for a bidirectional 8-bit shift register using d flip flop.Kindly help me with the same Regards From newsfish@newsfish Fri Feb 3 13:11:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x13g2000vbe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: bIDIRECTIONAL hift register Date: Mon, 21 Feb 2011 23:17:20 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: References: <650d66d6-a174-4e06-b56f-01f83b5b5057@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298359041 2759 127.0.0.1 (22 Feb 2011 07:17:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 07:17:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x13g2000vbe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4783 On 22 Feb., 04:53, fido t wrote: > Hello, I'm unable to design an architectural layout for a bidirectional 8-bit shift register using d flip flop.Kindly help me with the same > Regards Hi, I understand D-Flipflop. That just stores the value it sees on its input. But maybe you can explain (or draw some sketch) how bidirectional shifting should be done with it. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:11:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q2g2000pre.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: bIDIRECTIONAL hift register Date: Tue, 22 Feb 2011 05:29:20 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <850fd38a-25dc-4e99-bfb8-443cd3b6a2ba@q2g2000pre.googlegroups.com> References: <650d66d6-a174-4e06-b56f-01f83b5b5057@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 74.126.85.132 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298381360 26037 127.0.0.1 (22 Feb 2011 13:29:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 13:29:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q2g2000pre.googlegroups.com; posting-host=74.126.85.132; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; GTB6.6; .NET CLR 1.1.4322; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4784 On Feb 21, 10:53=A0pm, fido t wrote: > Hello, I'm unable to design an architectural layout for a bidirectional 8= -bit shift register using d flip flop.Kindly help me with the same > Regards Sounds like a homework assignment. KJ From newsfish@newsfish Fri Feb 3 13:11:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: bIDIRECTIONAL hift register Date: Tue, 22 Feb 2011 06:40:38 -0800 (PST) Organization: http://groups.google.com Lines: 14 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298385638 5561 127.0.0.1 (22 Feb 2011 14:40:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 14:40:38 +0000 (UTC) In-Reply-To: <650d66d6-a174-4e06-b56f-01f83b5b5057@glegroupsg2000goo.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4785 On Monday, February 21, 2011 10:53:24 PM UTC-5, fido t wrote: > Hello, I'm unable to design an architectural layout for a bidirectional 8-bit shift register using d flip flop.Kindly help me with the same > Regards I would suggest using a horizontal layout, as shifting is easier to understand when it goes left to right or right to left. Vertical layout would require the more difficult up- and down-shifting, which as anyone who has driven a standard transmission knows, is not for the beginner. Finally the horizontal layout fits better on your wide-screen monitor. HTH, Gabor From newsfish@newsfish Fri Feb 3 13:11:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!r19g2000prm.googlegroups.com!not-for-mail From: GoogleGoonsAreClueless Newsgroups: comp.lang.vhdl Subject: Re: bIDIRECTIONAL hift register Date: Tue, 22 Feb 2011 09:01:08 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <2e32ff79-a00e-4f08-8b2e-2fbab3cd1118@r19g2000prm.googlegroups.com> References: NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298394069 20341 127.0.0.1 (22 Feb 2011 17:01:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 17:01:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r19g2000prm.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4786 On Feb 22, 6:40=A0am, Gabor Sz wrote: > On Monday, February 21, 2011 10:53:24 PM UTC-5, fido t wrote: > > Hello, I'm unable to design an architectural layout for a bidirectional= 8-bit shift register using d flip flop.Kindly help me with the same > > Regards > > I would suggest using a horizontal layout, as shifting > is easier to understand when it goes left to right or > right to left. =A0Vertical layout would require the more > difficult up- and down-shifting, which as anyone who has > driven a standard transmission knows, is not for the > beginner. =A0Finally the horizontal layout fits better > on your wide-screen monitor. > > HTH, > Gabor Not true. The vertical layout works *just fine* so long as you use '1' for up, and '0' for down. You do need to stop clocking when you are done shifting, otherwise when direction goes to zero all of the bits will start sliding down. RK From newsfish@newsfish Fri Feb 3 13:11:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o18g2000prh.googlegroups.com!not-for-mail From: Vikram Newsgroups: comp.lang.vhdl,comp.os.linux.embedded,comp.os.linux.development.system Subject: Call for speakers & Vendors: FPGA Camp, Silicon Valley, CA - Apr'6 2011 Date: Tue, 22 Feb 2011 12:27:33 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: <2c608727-f5ce-4895-a9cf-403f616e3f33@o18g2000prh.googlegroups.com> NNTP-Posting-Host: 8.4.225.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298406454 5616 127.0.0.1 (22 Feb 2011 20:27:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Feb 2011 20:27:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000prh.googlegroups.com; posting-host=8.4.225.30; posting-account=ROblUgoAAABUCieY-adRND7iPJOdhLol User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4787 comp.os.linux.embedded:1015 comp.os.linux.development.system:3090 Announcing the next FPGA Camp on Apr'6 2011 visit http://www.fpgacentral.com/fpgacamp for more details. TOPIC: EMBEDDED PROCESSORS IN FPGA - FPGA CAMP, SILICON VALLEY FPGA Camp is a conference, which brings engineers together to discusses FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories. Since its inception in Year 2009, FPGA Camp decided to stay vendor neutral. The attendance is completely FREE (free like in beer) and so is putting up a booth. Due to the this approach we soon have been coined as an Open Source conference by Industry leaders like Eric Bogatin, Colin Warwick & Max Maxfield. f you or anyone you would like to speak or have a booth (free) then please contact us at fpgacamp @ fpgacentral .com or call (415)787-FPGA Attendees can also start registering for free. From newsfish@newsfish Fri Feb 3 13:11:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!i39g2000prd.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Most popular VHDL/Verilog Date: Wed, 23 Feb 2011 07:09:56 -0800 (PST) Organization: http://groups.google.com Lines: 20 Message-ID: References: <3922c11a-eaa2-4352-bf78-0dec068960af@y3g2000vbh.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298473797 22237 127.0.0.1 (23 Feb 2011 15:09:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 23 Feb 2011 15:09:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i39g2000prd.googlegroups.com; posting-host=195.144.71.15; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.102 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4788 comp.arch.fpga:14592 comp.lang.verilog:2828 Thanks to all who have participated. The results are now online at: http://www.vhdleditor.com It may not be surprising, but this poll says Emacs is the most popular VHDL/Verilog editor. Second and third are Notepad++ and VI. Philippe On Feb 15, 8:29=A0pm, Philippe wrote: > Hi everybody. > > Could you please help me find out which is the most popular VHDL/ > Verilog editor, by filling out this poll:http://www.vhdleditor.com/poll > I'm not looking for the "best VHDL/Verilog editor" (that would only > get a flame war started). I'm just trying to find out which is used > more often. So, please go and vote! > > thanks > > Philippe From newsfish@newsfish Fri Feb 3 13:11:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!feeder.news.orange.fr!not-for-mail Date: Thu, 24 Feb 2011 12:45:10 +0100 From: =?ISO-8859-15?Q?St=E9phane?= Goujet Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: Re: Most popular VHDL/Verilog Message-ID: <20110224124510.654a4b20@wana.fr.invalid> References: <3922c11a-eaa2-4352-bf78-0dec068960af@y3g2000vbh.googlegroups.com> X-Newsreader: Claws Mail 3.7.8 (GTK+ 2.20.1; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit Lines: 14 Organization: les newsgroups par Orange NNTP-Posting-Date: 24 Feb 2011 12:46:42 CET NNTP-Posting-Host: 92.134.211.103 X-Trace: 1298548002 reader.news.orange.fr 7710 92.134.211.103:13675 X-Complaints-To: abuse@orange.fr Xref: feeder.eternal-september.org comp.lang.vhdl:4789 comp.lang.verilog:2830 Le Wed, 23 Feb 2011 07:09:56 -0800 (PST), Philippe a crit : > Thanks to all who have participated. The results are now online at: > http://www.vhdleditor.com > It may not be surprising, but this poll says Emacs is the most popular > VHDL/Verilog editor. Second and third are Notepad++ and VI. Is there any editor that gathers a significant percentage of answers in the "others" ? Goodbye, Stphane G. From newsfish@newsfish Fri Feb 3 13:11:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o21g2000prn.googlegroups.com!not-for-mail From: svleest Newsgroups: comp.lang.vhdl Subject: iPhone app reference guide for VHDL and Verilog Date: Fri, 25 Feb 2011 09:43:22 -0800 (PST) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 153.106.140.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298655803 19717 127.0.0.1 (25 Feb 2011 17:43:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 25 Feb 2011 17:43:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o21g2000prn.googlegroups.com; posting-host=153.106.140.151; posting-account=1Bx2wwoAAADKNFeg_heEcR_soCWAKWda User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.102 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4790 My app company just produced an iPhone app reference guide for VHDL and Verilog (works on iPad too). It is meant to be a quick help (not a exhaustively complete reference). Please check it out if you are interested -- search for "VHDL Ref" in iTunes app store or else search for our company name, squishLogic. Thanks. From newsfish@newsfish Fri Feb 3 13:11:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!aioe.org!.POSTED!not-for-mail From: Patrick Newsgroups: comp.lang.vhdl Subject: Re: Hardware vs simulation mismatch problem Date: Sun, 27 Feb 2011 16:04:34 +0000 Organization: Aioe.org NNTP Server Lines: 120 Message-ID: References: <4d5dadfb$0$32470$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: Iw1Rg0XI7CrpPCPAVbzspw.user.speranza.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) X-Notice: Filtered by postfilter v. 0.8.2 Xref: feeder.eternal-september.org comp.lang.vhdl:4791 > First of all: look at the synthesis report. I would expect at least a > warning about tx: it is read in process sel_out and it is not in the > sensitivity list. Hi again, Thanks to your input, I implemented your suggestions, however the problem remains the same. I checked the synthesis report and there are no latches. The result in simulation works fine, but the hardware outputs something different. Just to briefly recap, I have two ctrl signals that determine the behaviour of the entity: GET (ctrl = "00000000") sets register tx to input of op1 SH1_L (ctrl = "00000001") res := (op1 << 1) | tx; tx := tx >> 31; library ieee; use ieee.std_logic_1164.all; entity test is port ( op1 : in std_logic_vector(31 downto 0); -- Input operand ctrl : in std_logic_vector(7 downto 0); -- Control signal clk : in std_logic; -- clock res : out std_logic_vector(31 downto 0) -- Result ); end; architecture rtl of test is type res_sel_type is (GET, SH1_L); constant Z : std_logic_vector(31 downto 0) := (others => '0'); signal res_sel : res_sel_type; signal load : std_logic := '0'; signal shl : std_logic := '0'; signal tx : std_logic_vector(31 downto 0) := (others => '0'); signal inp1 : std_logic_vector(31 downto 0) := (others => '0'); begin dec_op: process (ctrl, op1) begin res_sel <= GET; load <= '0'; shl <= '0'; inp1 <= ( others => '0'); case ctrl is -- store operand when "00000000" => inp1 <= op1; load <= '1'; res_sel <= GET; -- 1-bit left-shift with carry when "00000001" => inp1 <= op1; shl <= '1'; res_sel <= SH1_L; when others => -- Leave default values end case; end process; sel_out: process (res_sel, inp1, tx) begin case res_sel is when SH1_L => res <= ( inp1(30 downto 0) & '0' ) or tx; when others => res <= (others => '0'); end case; end process; sync: process(clk) begin if clk'event and clk = '1' then if load = '1' then tx <= op1; elsif shl = '1' then tx <= Z(30 downto 0) & op1(31); end if; end if; end process; end rtl; TESTPROGRAM GET 0 (this sets tx <= 0 ) SH1_L 0xfedcba90 exp. output: 0xfdb97520 act. output = 0xfdb97521 SH1_L 0x7654321f exp. output: 0xeca8643f act. output = 0xeca8643f SH1_L 0x71234567 exp. output: 0xe2468ace act. output = 0xe2468ace As you can see, the last bit is wrong for the first SH1_L operation. The first SH1_L operation produces a carry for the NEXT SH1_L operation sincethe MSB is set to one of the input, however, it seems that this carry is already considered in the current SH1_L operation, which is wrong (tx should be zero). So I am a bit clueless and almost desperate what is going wrong here. I use Xilinx ISE 12.1 for synthesis, could there be a problem because I do not have a reset signal in my architecture, that the wrong kind of latches are instantiated? Many thanks for further helpful comments to solve this issue, Patrick From newsfish@newsfish Fri Feb 3 13:11:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j9g2000prj.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Call for Papers: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 27 Feb 2011 08:25:57 -0800 (PST) Organization: http://groups.google.com Lines: 293 Message-ID: <0ada9e95-951a-4005-9739-5e3e9aa32b7e@j9g2000prj.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298823958 14336 127.0.0.1 (27 Feb 2011 16:25:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 27 Feb 2011 16:25:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prj.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; FDM; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:159448 sci.electronics.cad:7650 sci.electronics.misc:3682 sci.engr.semiconductors:757 comp.lang.vhdl:4792 CALL FOR PAPERS and Call For Workshop/Session Proposals MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods Date and Location: July 18-21, 2011, USA http://www.world-academy-of-science.org/ Location: See the above web site for venue/city You are invited to submit a full paper for consideration. All accepted papers will be published in the MSV conference proceedings (in printed book form; later, the proceedings will also be accessible online). Those interested in proposing workshops/sessions, should refer to the relevant sections that appear below. SCOPE: Topics of interest include, but are not limited to, the following: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: To see the DBLP list of accepted papers of MSV 2009, go to: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2009.html The DBLP list of accepted papers of MSV 2010 will soon appear at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html MSV 2011 URL: http://www.world-academy-of-science.org/worldcomp11/ws/conferences/msv11 IMPORTANT DATES: March 10, 2011: Submission of papers (about 5 to 7 pages) April 03, 2011: Notification of acceptance (+/- two days) April 24, 2011: Final papers + Copyright/Consent + Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) ACADEMIC CO-SPONSORS: Currently being prepared - The Academic sponsors of the last offering of MSV (2010) included research labs and centers affiliated with (a partial list): University of California, Berkeley; University of Southern California; University of Texas at Austin; Harvard University, Cambridge, Massachusetts; Georgia Institute of Technology, Georgia; Emory University, Georgia; University of Minnesota; University of Iowa; University of North Dakota; NDSU-CIIT Green Computing & Comm. Lab.; University of Siegen, Germany; UMIT, Austria; SECLAB (University of Naples Federico II + University of Naples Parthenope + Second University of Naples, Italy); National Institute for Health Research; World Academy of Biomedical Sciences and Technologies; Russian Academy of Sciences, Russia; International Society of Intelligent Biological Medicine (ISIBM); The International Council on Medical and Care Compunetics; Eastern Virginia Medical School & the American College of Surgeons, USA. SUBMISSION OF PAPERS: Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by March 10, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) that the paper is being submitted for consideration must be stated on the first page. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject) - often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/philosophical papers will not be refereed but may be considered for discussion/panels). All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering & Technology, DBLP / CS Bibliography, and others. The printed proceedings will be available for distribution on site at the conference. In addition to the publication of the proceedings, selected authors will be invited to submit extended versions of their papers for publication in a number of research books being proposed/contracted with various publishers (such as, Springer, Elsevier, ...) - these books would be composed after the conference. Also, many chairs of sessions and workshops will be forming journal special issues to be published after the conference. MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES: The members of the Steering Committee of The 2010 congress included: Dr. Selim Aissi (Chief Strategist, Intel Corporation, USA); Prof. Hamid Arabnia (ISIBM Fellow & Professor, University of Georgia; Associate Editor, IEEE Transactions on Information Technology in Biomedicine; Editor-in-Chief, Journal of Supercomputing, Springer; Advisory Board, IEEE TC on Scalable Computing); Prof. Ruzena Bajcsy (Member, National Academy of Engineering, IEEE Fellow, ACM Fellow, Professor; University of California, Berkeley, USA); Prof. Hyunseung Choo (ITRC Director of Ministry of Information & Communication; Director, ITRC; Director, Korea Information Processing Society; Assoc. Editor, ACM Transactions on Internet Technology; Professor, Sungkyunkwan University, Korea); Prof. Winston Wai-Chi Fang (IEEE Fellow, TSMC Distinguished Chair Professor, National ChiaoTung University, Hsinchu, Taiwan, ROC); Prof. Andy Marsh (Director HoIP, Secretary-General WABT; Vice-president ICET and ICMCC, Visiting Professor, University of Westminster, UK); Dr. Rahman Tashakkori (Director, S-STEM NSF Supported Scholarship Program and NSF Supported AUAS, Appalachian State U., USA); Prof. Layne T. Watson (IEEE Fellow, NIA Fellow, ISIBM Fellow, Fellow of The National Institute of Aerospace, Virginia Polytechnic Institute & State University, USA); and Prof. Lotfi A. Zadeh (Member, National Academy of Engineering; IEEE Fellow, ACM Fellow, AAAS Fellow, AAAI Fellow, IFSA Fellow; Director, BISC; Professor, University of California, Berkeley, USA). The list of Program Committee of MSV 2010 appears at: http://www.world-academy-of-science.org/worldcomp10/ws/conferences/msv10/committee The MSV 2011 program committee is currently being compiled. Many who have already joined the committee are renowned leaders, scholars, researchers, scientists and practitioners of the highest ranks; many are directors of research labs., members of National Academy of Engineering, fellows of various societies, heads/chairs of departments, program directors of research funding agencies, deans and provosts as well as members of chapters of World Academy of Science. Program Committee members are expected to have established a strong and documented research track record. Those interested in joining the Program Committee should email editor@world-comp.org the following information for consideration/evaluation: Name, affiliation and position, complete mailing address, email address, a one-page biography that includes research expertise and the name of the conference (ie, MSV 2011) offering to help with. GENERAL INFORMATION: MSV conference is an important track of a federated research conference. It is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,000 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different branches of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub- disciplines. PROPOSAL FOR ORGANIZING SESSIONS/WORKSHOPS: Each session will have at least 6 paper presentations from different authors (12 papers in the case of workshops). The session chairs will be responsible for all aspects of their sessions; including, soliciting papers, reviewing, selecting, ... The names of session chairs will appear as Associate Editors in the conference proceedings and on the cover of the books. Proposals to organize sessions should include the following information: name and address (+ email) of proposer, his/her biography, title of session, a 100-word description of the topic of the session, the name of the conference the session is submitted for consideration (ie, MSV), and a short description on how the session will be advertised (in most cases, session proposers solicit papers from colleagues and researchers whose work is known to the session proposer). email your session proposal to editor@world-comp.org We would like to receive the session proposals as soon as possible. NEWS: Thanks to authors and speakers of last WORLDCOMP congress and members of the editorial boards who informed us of the following good news: According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" and specific information extracted from it (in reference to WORLDCOMP's individual conferences' names/acronyms and tracks) from the link below: http://www.worldacademyofscience.org/worldcomp10/ws/news From newsfish@newsfish Fri Feb 3 13:11:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t15g2000prt.googlegroups.com!not-for-mail From: Sreenivas J Newsgroups: comp.lang.vhdl Subject: Need help on Automatic self checking testbench Date: Mon, 28 Feb 2011 09:22:27 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: <39deff3a-465b-457a-8ec4-be4b2e36834c@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 122.166.160.133 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298913747 15447 127.0.0.1 (28 Feb 2011 17:22:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 28 Feb 2011 17:22:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t15g2000prt.googlegroups.com; posting-host=122.166.160.133; posting-account=IRxnLgkAAAA4H7uc0muXvvWJOHXd2rcp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1) ; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4793 Hi all, I am working on self checking automated test bench. Here i have testbench having each step implemented in VHDL which includes processor READ and WRITE actions developed in package and calling into testbench. Example: Step_no<=1; por_n<='0'; wait for 100 ns; por_n<='1'; wait for 100 ns; Step_no<2; WRITE(
, ; ); My intension is to create Automated testbench golden reference file which can read all the step's expected results from the main testbench and compare with the actual results with step number reference. At some extent i tried to create a model using VHDL TEXT IO's but i am getting difficulties at READ and WRITE actions. Please suggest me some good process to follow,...that will be a gr8 help. Thanks, Nivas. From newsfish@newsfish Fri Feb 3 13:11:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o18g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Need help on Automatic self checking testbench Date: Mon, 28 Feb 2011 10:01:31 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: References: <39deff3a-465b-457a-8ec4-be4b2e36834c@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298916092 14653 127.0.0.1 (28 Feb 2011 18:01:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 28 Feb 2011 18:01:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o18g2000prh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4794 On Feb 28, 12:22=A0pm, Sreenivas J wrote: > > My intension is to create Automated testbench golden reference file > which can read all the step's expected results from the main testbench > and compare with the actual results with step number reference. > I find it more productive to create a VHDL model of the system under test rather than reading expected results from a file. Add assertion checking at will to check everything that needs checking. > At some extent i tried to create a model using VHDL TEXT IO's but i am > getting difficulties at READ and WRITE actions. > Unless you can explain "getting difficulties", it will be difficult for anyone to help. > Please suggest me some good process to follow,...that will be a gr8 > help. 1. Ask yourself how you are going to generate the expected results 2. Ask yourself if it wouldn't be easier to encode the process of #1 within your testbench in the first place and skip reading/writing files Kevin Jennings From newsfish@newsfish Fri Feb 3 13:11:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!w9g2000prg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Need help on Automatic self checking testbench Date: Mon, 28 Feb 2011 14:43:30 -0800 (PST) Organization: http://groups.google.com Lines: 7 Message-ID: References: <39deff3a-465b-457a-8ec4-be4b2e36834c@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298933010 31028 127.0.0.1 (28 Feb 2011 22:43:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 28 Feb 2011 22:43:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000prg.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4795 Hint: Read() could take an argument (default to others => '-'). with which to compare the results, and then it could report failures. Read could also have an output parameter to allow collecting the read data and analyzing as a whole after all the data is received. Andy From newsfish@newsfish Fri Feb 3 13:11:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news.glorb.com!news2.glorb.com!postnews.google.com!s18g2000prg.googlegroups.com!not-for-mail From: Sreenivas J Newsgroups: comp.lang.vhdl Subject: Re: Need help on Automatic self checking testbench Date: Mon, 28 Feb 2011 18:22:28 -0800 (PST) Organization: http://groups.google.com Lines: 38 Message-ID: References: <39deff3a-465b-457a-8ec4-be4b2e36834c@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 203.92.217.80 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298946148 21670 127.0.0.1 (1 Mar 2011 02:22:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 02:22:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s18g2000prg.googlegroups.com; posting-host=203.92.217.80; posting-account=IRxnLgkAAAA4H7uc0muXvvWJOHXd2rcp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; .NET CLR 1.1.4322),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4796 On Feb 28, 11:01=A0pm, KJ wrote: > On Feb 28, 12:22=A0pm, Sreenivas J wrote: > > > > > My intension is to create Automated testbench golden reference file > > which can read all the step's expected results from the main testbench > > and compare with the actual results with step number reference. > > I find it more productive to create a VHDL model of the system under > test rather than reading expected results from a file. =A0Add assertion > checking at will to check everything that needs checking. > > > At some extent i tried to create a model using VHDL TEXT IO's but i am > > getting difficulties at READ and WRITE actions. > > Unless you can explain "getting difficulties", it will be difficult > for anyone to help. > > > Please suggest me some good process to follow,...that will be a gr8 > > help. > > 1. Ask yourself how you are going to generate the expected results > 2. Ask yourself if it wouldn't be easier to encode the process of #1 > within your testbench in the first place and skip reading/writing > files > > Kevin Jennings Hi kevin, Thanks for your response. The aim of this is when we run for simulation we can see the responses in waveform file from Modelsim, so those responses or exptected results i have to capture in a text file and compare with actual results. reg, Nivas From newsfish@newsfish Fri Feb 3 13:11:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!b8g2000vbi.googlegroups.com!not-for-mail From: a s Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 04:59:01 -0800 (PST) Organization: http://groups.google.com Lines: 112 Message-ID: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298984341 14848 127.0.0.1 (1 Mar 2011 12:59:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 12:59:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b8g2000vbi.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14686 comp.lang.vhdl:4798 Dear all, I have come up with 2 solutions in VHDL, how to count number of bits in input data. The thing I don't understand is why the 2 solutions produce different results, at least with Xilinx ISE and its XST. There is quite a substantial difference in required number of slices/ LUTs. 1. solution with unrolled loop: 41 slices, 73 LUTs 2. solution with loop: 54 slices, 100 LUTs The entity of both architectures is the same: entity one_count is Port ( din : in STD_LOGIC_vector(31 downto 0); dout : out STD_LOGIC_vector(5 downto 0) ); end one_count; The architecture with an unrolled loop is the following: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity one_count is Port ( din : in STD_LOGIC_vector(31 downto 0); dout : out STD_LOGIC_vector(5 downto 0) ); end one_count; architecture one_count_unrolled_arch of one_count is signal cnt : integer range 0 to 32; begin cnt <= to_integer(unsigned(din( 0 downto 0))) + to_integer(unsigned(din( 1 downto 1))) + to_integer(unsigned(din( 2 downto 2))) + to_integer(unsigned(din( 3 downto 3))) + to_integer(unsigned(din( 4 downto 4))) + to_integer(unsigned(din( 5 downto 5))) + to_integer(unsigned(din( 6 downto 6))) + to_integer(unsigned(din( 7 downto 7))) + to_integer(unsigned(din( 8 downto 8))) + to_integer(unsigned(din( 9 downto 9))) + to_integer(unsigned(din(10 downto 10))) + to_integer(unsigned(din(11 downto 11))) + to_integer(unsigned(din(12 downto 12))) + to_integer(unsigned(din(13 downto 13))) + to_integer(unsigned(din(14 downto 14))) + to_integer(unsigned(din(15 downto 15))) + to_integer(unsigned(din(16 downto 16))) + to_integer(unsigned(din(17 downto 17))) + to_integer(unsigned(din(18 downto 18))) + to_integer(unsigned(din(19 downto 19))) + to_integer(unsigned(din(20 downto 20))) + to_integer(unsigned(din(21 downto 21))) + to_integer(unsigned(din(22 downto 22))) + to_integer(unsigned(din(23 downto 23))) + to_integer(unsigned(din(24 downto 24))) + to_integer(unsigned(din(25 downto 25))) + to_integer(unsigned(din(26 downto 26))) + to_integer(unsigned(din(27 downto 27))) + to_integer(unsigned(din(28 downto 28))) + to_integer(unsigned(din(29 downto 29))) + to_integer(unsigned(din(30 downto 30))) + to_integer(unsigned(din(31 downto 31))); dout <= std_logic_vector(to_unsigned(cnt,6)); end one_count_unrolled_arch ; And the architecture with a loop is the following: architecture one_count_loop_arch of one_count_loop is signal cnt : integer range 0 to 32; begin process(din) is variable tmp : integer range 0 to 32; begin tmp := to_integer(unsigned(din(0 downto 0))); for i in 1 to 31 loop tmp := tmp + to_integer(unsigned(din(i downto i))); end loop; cnt <= tmp; end process; dout <= std_logic_vector(to_unsigned(cnt,6)); end one_count_loop_arch ; I would be really grateful if somebody could point out what I did wrong with the 2. solution with loop. It certainly must be my mistake, but I can not find it... Additionally, I know that this "brute-force" one counting might not be the optimal approach, but this is just my first attempt to get the job done. If somebody has a better solution, I would appreciate it if you could share it. Regards, Peter From newsfish@newsfish Fri Feb 3 13:11:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!u3g2000vbe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 06:33:59 -0800 (PST) Organization: http://groups.google.com Lines: 136 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298990039 23282 127.0.0.1 (1 Mar 2011 14:33:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 14:33:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbe.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14688 comp.lang.vhdl:4799 On Mar 1, 12:59=A0pm, a s wrote: > Dear all, > > I have come up with 2 solutions in VHDL, how to count number of bits > in input data. > The thing I don't understand is why the 2 solutions produce different > results, at least with Xilinx ISE and its XST. > There is quite a substantial difference in required number of slices/ > LUTs. > > 1. solution with unrolled loop: =A0 =A0 =A0 =A041 slices, =A073 LUTs > 2. solution with loop: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A054 slices, = 100 LUTs > > The entity of both architectures is the same: > > entity one_count is > =A0 Port ( din : in =A0STD_LOGIC_vector(31 downto 0); > =A0 =A0 =A0 =A0 =A0dout : out =A0STD_LOGIC_vector(5 downto 0) > =A0 =A0 =A0 =A0 ); > end one_count; > > The architecture with an unrolled loop is the following: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity one_count is > =A0 Port ( din : in =A0STD_LOGIC_vector(31 downto 0); > =A0 =A0 =A0 =A0 =A0dout : out =A0STD_LOGIC_vector(5 downto 0) > =A0 =A0 =A0 =A0 ); > end one_count; > > architecture one_count_unrolled_arch of one_count is > > =A0 signal =A0cnt : integer range 0 to 32; > > begin > > =A0 =A0cnt <=3D to_integer(unsigned(din( 0 downto =A00))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 1 downto =A01))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 2 downto =A02))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 3 downto =A03))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 4 downto =A04))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 5 downto =A05))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 6 downto =A06))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 7 downto =A07))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 8 downto =A08))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din( 9 downto =A09))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(10 downto 10))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(11 downto 11))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(12 downto 12))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(13 downto 13))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(14 downto 14))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(15 downto 15))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(16 downto 16))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(17 downto 17))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(18 downto 18))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(19 downto 19))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(20 downto 20))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(21 downto 21))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(22 downto 22))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(23 downto 23))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(24 downto 24))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(25 downto 25))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(26 downto 26))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(27 downto 27))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(28 downto 28))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(29 downto 29))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(30 downto 30))) + > =A0 =A0 =A0 =A0 =A0 to_integer(unsigned(din(31 downto 31))); > > =A0 =A0dout <=3D std_logic_vector(to_unsigned(cnt,6)); > > end one_count_unrolled_arch ; > > And the architecture with a loop is the following: > > architecture one_count_loop_arch of one_count_loop is > > signal =A0cnt : integer range 0 to 32; > > begin > > =A0 process(din) is > =A0 =A0 variable =A0tmp : integer range 0 to 32; > =A0 =A0 begin > =A0 =A0 =A0 tmp :=3D to_integer(unsigned(din(0 downto 0))); > =A0 =A0 =A0 for i in 1 to 31 loop > =A0 =A0 =A0 =A0 =A0 tmp :=3D tmp + to_integer(unsigned(din(i downto i))); > =A0 =A0 =A0 end loop; > =A0 =A0 =A0 cnt <=3D tmp; > =A0 end process; > > =A0 dout <=3D std_logic_vector(to_unsigned(cnt,6)); > > end one_count_loop_arch ; > > I would be really grateful if somebody could point out what I did > wrong with the 2. solution with loop. > It certainly must be my mistake, but I can not find it... > > Additionally, I know that this "brute-force" one counting might not be > the optimal approach, > but this is just my first attempt to get the job done. If somebody has > a better solution, I would > appreciate it if you could share it. > > Regards, > Peter see what you get with this function instead (a function I have used before): function count_ones(slv : std_logic_vector) return natural is varaible n_ones : natural :=3D 0; begin for i in slv'range loop if slv(i) =3D '1' then n_ones :=3D n_ones + 1; end if; end loop; return n_ones; end function count_ones; .... inside architecture, no process needed: dout <=3D std_logic_vector( to_unsigned(count_ones(din), dout'length) ); The beauty with this is the function will work with a std_logic_vector of any length. From newsfish@newsfish Fri Feb 3 13:11:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z3g2000prz.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 06:49:39 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1298990979 11231 127.0.0.1 (1 Mar 2011 14:49:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 14:49:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z3g2000prz.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14690 comp.lang.vhdl:4800 A good synthesis tool should be able to optimize either version to the same implementation. But there are semantic differences that Xilinx may be getting hung up on. In the unrolled version, you have a long expression, and there is freedom within vhdl to evaluate it in different orders or groups of operations. In the loop version, since you are continually updating tmp, you are describing an explicitly sequential order in which the calculation takes place. Like I said, a good synthesis tool should be able to handle either one equally well, but you get what you pay for in synthesis tools. If you are looking for a general solution to the problem for any size vector, try a recursive function implentation of a binary tree and see what happens. Just for kicks, you might also put the whole calculation in the loop (0 to 31), with temp set to 0 before the loop. Shouldn't make any difference, but then again, we're already seeing differences where there should be none. On the other hand, if what you have works (fits and meets timing), use the most maintainable, understandable version. It will save you time (=money) in the long run. It is often interesting to find out what is "the optimal" way to code something such that it results in the smallest/fastest circuit. But in the big picture, it most often does not matter, especially when you write some cryptic code to squeeze the last pS/LUT out of it, and you had plenty of slack and space to spare anyway. Nevertheless, knowing how to squeeze every pS/LUT comes in handy every once in a while. Andy From newsfish@newsfish Fri Feb 3 13:11:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: a s Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 08:41:46 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1298997706 4610 127.0.0.1 (1 Mar 2011 16:41:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 16:41:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14694 comp.lang.vhdl:4801 Dear Andy, Tricky, thank you both for your valuable input. Please find my comments below. On Mar 1, 3:49=A0pm, Andy wrote: > A good synthesis tool should be able to optimize either version to the > same implementation. But there are semantic differences that Xilinx > may be getting hung up on. Aha, that's a good thing, it means that I did not make some obvious mistake. ;-) > If you are looking for a general solution to the problem for any size > vector, try a recursive function implentation of a binary tree and see > what happens. OK, I didn't quite get that but will consider it again. > Just for kicks, you might also put the whole calculation in the loop > (0 to 31), with temp set to 0 before the loop. Shouldn't make any > difference, but then again, we're already seeing differences where > there should be none. Sorry I didn't tell you before. I have already tried that and in this case XST produces the same result. > On the other hand, if what you have works (fits and meets timing), use > the most maintainable, understandable version. It will save you time > (=3Dmoney) in the long run. It is often interesting to find out what is > "the optimal" way to code something such that it results in the > smallest/fastest circuit. But in the big picture, it most often does > not matter, especially when you write some cryptic code to squeeze the > last pS/LUT out of it, and you had plenty of slack and space to spare > anyway. Nevertheless, knowing how to squeeze every pS/LUT comes in > handy every once in a while. Andy, I completely agree with what you have written above. One should strive for maintainable and understandable version. Although, on my particular case, I have to find a good solution in terms of LUT resources, because I need 8 instances of one counters with 64-bit input data. And the device is getting full... Tricky, your approach does indeed look very neat. I like it. Although it is far less efficient than mine. For the same input/output ports, your version with function requires 171 Slices in 313 LUTs. (The minimum that I get with unrolled version is 41 Slices and 73 LUTs). From newsfish@newsfish Fri Feb 3 13:11:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Need help on Automatic self checking testbench Date: Tue, 01 Mar 2011 12:48:22 -0500 Lines: 53 Message-ID: <8t4pr5Fs71U1@mid.individual.net> References: <39deff3a-465b-457a-8ec4-be4b2e36834c@t15g2000prt.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net XAeqx/FPmxvDi1TgRG+bWQgovc6CTTdPXs9l+CMLsVK80lvmto Cancel-Lock: sha1:ntKvB3cASpbblfvou20nkmqTNK0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.13) Gecko/20101207 Lightning/1.0b2 Thunderbird/3.1.7 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4802 On 2/28/2011 9:22 PM, Sreenivas J wrote: > The aim of this is when we run for simulation we can see the responses > in waveform file from Modelsim, > so those responses or exptected results i have to capture in a text > file and compare with actual results. > I had this idea in mind long time ago, thinking it would be a *great* (not gr8) way to test any dut, providing input patterns from a file and comparing output patterns with my "expected results" neatly stored in another file. Then I realize the file needed a format (wow!) and the procedure to read the file would have needed a way to check the format for typos (ouch!). Then I realized that I needed more than just a series of values to check since the logic would have processed the data after some time, so I would have needed to synchronize the reading of the next value with the logic... In no longer than a couple of days I realized I was writing a scripting language and the result was far away from what I wanted. The file approach was more of a burden rather than a help. In my mind you need to: 1. identify first the interfaces to your dut (serial/parallel communication, hand-shake protocol, bus interface), all the means that give you a handle on the dut. 2. write procedures to communicate with the dut (read/write) 3. identify all the output of the dut (data streams, serial/parallel interfaces, etc.), all the means that make you "see" what the dut is doing. 4. write procedure to sample the output and evaluate the result. Now you have a way to stimulate your dut with several operations and check the results. Use as much as possible existing models in your testbench, so if you have a spi interface try to find an existing implementation and use it. Just bear in mind that when your design is implemented you will only have inputs and outputs on your board, nothing else. If a state of the design cannot produce a transition on any output it means the state is not "observable" and you will spend the rest of your life trying to figure out what is your logic doing. If a state of the design cannot be forced through a series of inputs it means that state is not "controllable" and most probably you will not be able to perform what you wanted. > reg, what is reg? is it a register? if it stands for "regards" why not writing so? are you afraid to use the bandwidth of your internet connection efficiently? In this last case I spoiled your intent I believe ;-) > Nivas From newsfish@newsfish Fri Feb 3 13:11:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d23g2000prj.googlegroups.com!not-for-mail From: johnp Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 13:41:06 -0800 (PST) Organization: http://groups.google.com Lines: 121 Message-ID: <89969682-7d42-403c-9433-f354ac8a5ffe@d23g2000prj.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 67.136.133.82 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299015666 11508 127.0.0.1 (1 Mar 2011 21:41:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 21:41:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d23g2000prj.googlegroups.com; posting-host=67.136.133.82; posting-account=tiO7BgoAAAB2uqUBus2DRPVclhGttu0Z User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14697 comp.lang.vhdl:4803 Here's a slightly different approach to your problem.... It tries to take advantage of the fact that the LUTs are pretty good as lookup tables. It's in Verilog, but you should easily be able to convert it to VHDL. `define V1 module tst ( input [31:0] data, output [5:0] cnt ); `ifdef V1 /* Device utilization summary: --------------------------- Selected Device : 3s50pq208-5 Number of Slices: 35 out of 768 4% Number of 4 input LUTs: 62 out of 1536 4% Number of IOs: 38 Number of bonded IOBs: 0 out of 124 0% */ function [1:0] cnt3; input [2:0] d_in; begin case (d_in) 3'h0: cnt3 = 2'h0; 3'h1: cnt3 = 2'h1; 3'h2: cnt3 = 2'h1; 3'h3: cnt3 = 2'h2; 3'h4: cnt3 = 2'h1; 3'h5: cnt3 = 2'h2; 3'h6: cnt3 = 2'h2; 3'h7: cnt3 = 2'h3; endcase end endfunction assign cnt = cnt3(data[2:0]) + cnt3(data[5:3]) + cnt3(data[8:6]) + cnt3(data[11:9]) + cnt3(data[14:12]) + cnt3(data[17:15]) + cnt3(data[20:18]) + cnt3(data[23:21]) + cnt3(data[26:24]) + cnt3(data[29:27]) + cnt3({1'b0, data[31:30]}) ; `endif `ifdef V2 /* Selected Device : 3s50pq208-5 Number of Slices: 44 out of 768 5% Number of 4 input LUTs: 79 out of 1536 5% Number of IOs: 38 Number of bonded IOBs: 0 out of 124 0% */ function [2:0] cnt4; input [3:0] d_in; begin case (d_in) 4'h0: cnt4 = 3'h0; 4'h1: cnt4 = 3'h1; 4'h2: cnt4 = 3'h1; 4'h3: cnt4 = 3'h2; 4'h4: cnt4 = 3'h1; 4'h5: cnt4 = 3'h2; 4'h6: cnt4 = 3'h2; 4'h7: cnt4 = 3'h3; 4'h8: cnt4 = 3'h1; 4'h9: cnt4 = 3'h2; 4'ha: cnt4 = 3'h2; 4'hb: cnt4 = 3'h3; 4'hc: cnt4 = 3'h2; 4'hd: cnt4 = 3'h3; 4'he: cnt4 = 3'h3; 4'hf: cnt4 = 3'h4; endcase end endfunction assign cnt = cnt4(data[3:0]) + cnt4(data[7:4]) + cnt4(data[11:8]) + cnt4(data[15:12]) + cnt4(data[19:16]) + cnt4(data[23:20]) + cnt4(data[27:24]) + cnt4(data[31:28]) ; `endif endmodule John Providenza From newsfish@newsfish Fri Feb 3 13:11:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a11g2000pro.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 14:36:33 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <9be6a44d-b638-4347-9927-14f031cf530a@a11g2000pro.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299018993 9958 127.0.0.1 (1 Mar 2011 22:36:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Mar 2011 22:36:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a11g2000pro.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14700 comp.lang.vhdl:4804 > > If you are looking for a general solution to the problem for any size > > vector, try a recursive function implentation of a binary tree and see > > what happens. > > OK, I didn't quite get that but will consider it again. > The synthesis tool may not be able to figure out that it need not carry all the bits of the sum through every caculation in the loop. A binary tree implementation can manage the sum width at every stage. For a recursive binary tree implementation, define a function that divides the vector into two ~equal parts (i.e. n/2 and n/2 + n mod 2), calls itself on each one, and returns the sum of the two results. Stop recursion when the size of the incoming vector is 1 (just return 1 if the bit is set, and 0 if not). This is synthesizeable as long as the recursion is statically bound (which it is, by the size of the original vector). It should work out pretty close to what johnp's approach does, except work for any size input vector. Andy From newsfish@newsfish Fri Feb 3 13:11:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 00:20:05 +0000 (UTC) Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <9be6a44d-b638-4347-9927-14f031cf530a@a11g2000pro.googlegroups.com> Injection-Date: Wed, 2 Mar 2011 00:20:05 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="28070"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jYcbMxyFdutOJIOZx9at+" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:GKyWEVZ/K2wALsE10zNB1d/2dew= Xref: feeder.eternal-september.org comp.arch.fpga:14703 comp.lang.vhdl:4805 In comp.arch.fpga Andy wrote: (snip) > The synthesis tool may not be able to figure out that it need not > carry all the bits of the sum through every caculation in the loop. A > binary tree implementation can manage the sum width at every stage. Is that the same as a Carry Save Adder tree? Maybe not. The CSA has three inputs and two outputs, so it isn't exactly binary. -- glen From newsfish@newsfish Fri Feb 3 13:11:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!a8g2000pri.googlegroups.com!not-for-mail From: Brian Davis Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 16:59:58 -0800 (PST) Organization: http://groups.google.com Lines: 47 Message-ID: <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 72.64.5.20 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299027599 17976 127.0.0.1 (2 Mar 2011 00:59:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 00:59:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a8g2000pri.googlegroups.com; posting-host=72.64.5.20; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14705 comp.lang.vhdl:4806 Peter wrote: > > If somebody has a better solution, I would appreciate it if you could share it. > When I looked at this some years back, XST worked well enough at creating an adder cascade using the old "mask and add" software trick that I never bothered writing something more optimal: gen_bcnt32: if ( ALU_WIDTH = 32 ) generate begin process(din) -- multiple variables not needed, but make intermediate steps visible in simulation variable temp : unsigned (ALU_MSB downto 0); variable temp1 : unsigned (ALU_MSB downto 0); variable temp2 : unsigned (ALU_MSB downto 0); variable temp3 : unsigned (ALU_MSB downto 0); variable temp4 : unsigned (ALU_MSB downto 0); variable temp5 : unsigned (ALU_MSB downto 0); begin temp := unsigned(din); temp1 := (temp AND X"5555_5555") + ( ( temp srl 1) AND X"5555_5555"); -- 0..2 out x16 temp2 := (temp1 AND X"3333_3333") + ( ( temp1 srl 2) AND X"3333_3333"); -- 0..4 out x8 temp3 := (temp2 AND X"0707_0707") + ( ( temp2 srl 4) AND X"0707_0707"); -- 0..8 out x4 temp4 := (temp3 AND X"001f_001f") + ( ( temp3 srl 8) AND X"001f_001f"); -- 0..16 out x2 temp5 := (temp4 AND X"0000_003f") + ( ( temp4 srl 16) AND X"0000_003f"); -- 0..32 out cnt <= std_logic_vector(temp5(5 downto 0)); end process; end generate gen_bcnt32; Brian From newsfish@newsfish Fri Feb 3 13:11:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 05:55:31 +0000 (UTC) Organization: A noiseless patient Spider Lines: 38 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> Injection-Date: Wed, 2 Mar 2011 05:55:31 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="27364"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jTrTmTYAFqWxDGZSLZLMo" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:VorXp4mZJP7DXV3B8E881PW8o4M= Xref: feeder.eternal-september.org comp.arch.fpga:14707 comp.lang.vhdl:4807 In comp.arch.fpga Brian Davis wrote: (snip) > When I looked at this some years back, XST worked well enough > at creating an adder cascade using the old "mask and add" software > trick that I never bothered writing something more optimal: (snip) > temp1 := (temp AND X"5555_5555") + ( ( temp srl 1) AND > X"5555_5555"); -- 0..2 out x16 > > temp2 := (temp1 AND X"3333_3333") + ( ( temp1 srl 2) AND > X"3333_3333"); -- 0..4 out x8 OK, that would be a binary tree. I believe the CSA adder tree is slightly more efficient, though it might depend on the number of inputs. The binary tree cascade works especially well on word oriented machines, and can be easily written in many high-level languages (with the assumption of knowing the word size). The first stage of a CSA tree starts with N inputs, and generates N/3 two bit outputs that are the sums and carries from N/3 full adders. (If N isn't a multiple of three, then one bit may bypass the stage, and two bits go into a half adder.) The next stage takes the N/3 ones and N/3 twos, and generates N/9 ones, 2N/9 twos, and N/9 fours. You can continue until there is only one bit of each, or sometimes there are other optimizations near the end. Last time I did one, I only needed to know zero, one, two, three, or more than three, which simplifies it slightly. It also pipelines well, but then so does the binary tree. -- glen From newsfish@newsfish Fri Feb 3 13:11:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!u3g2000vbe.googlegroups.com!not-for-mail From: a s Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 22:50:18 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299048618 21836 127.0.0.1 (2 Mar 2011 06:50:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 06:50:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u3g2000vbe.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14708 comp.lang.vhdl:4808 Andy nailed it again when he said you get what you pay for regarding synthesis tool. Initially I was synthesising with ISE12.4 and the results were, hm, inconsistent. After switching the synthesis tool to SynplifyPro v2010.03 the results were as expected and, of course, even better than that. Please see the table below. Tricky's version is denoted "funct", where there are major differences between the 2 tools: ---------- 32-bit input data -------- unrolled: XST 74 LUTs, 41 slices unrolled: SynplifyPro 57 LUTs, 34 slices loop: XST 100 LUTs, 54 slices loop: SynplifyPro 57 LUTs, 34 slices funct: XST 317 LUTs, 161 slices funct: SynplifyPro 58 LUTs, 34 slices ---------- 64-bit input data -------- unrolled: XST 174 LUTs, 96 slices unrolled: SynplifyPro 129 LUTs, 80 slices loop: XST 227 LUTs, 121 slices loop: SynplifyPro 129 LUTs, 80 slices funct: XST 813 LUTs, 436 slices funct: SynplifyPro 130 LUTs, 82 slices Peter From newsfish@newsfish Fri Feb 3 13:11:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!n11g2000vbm.googlegroups.com!not-for-mail From: a s Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 1 Mar 2011 23:33:34 -0800 (PST) Organization: http://groups.google.com Lines: 32 Message-ID: <6e12bda6-1e7c-4876-b240-b97bb074ec88@n11g2000vbm.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299051215 13055 127.0.0.1 (2 Mar 2011 07:33:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 07:33:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n11g2000vbm.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14710 comp.lang.vhdl:4809 Johnp, Brian, thank you too for your input! Much appreciated. I have ran your code through 2 synthesisers and have updated the table of required resources. -------------- 32-bit input data -------------- unrolled: XST 74 LUTs, 41 slices unrolled: SynplifyPro 57 LUTs, 34 slices loop: XST 100 LUTs, 54 slices loop: SynplifyPro 57 LUTs, 34 slices funct: XST 317 LUTs, 161 slices funct: SynplifyPro 58 LUTs, 34 slices JohnpV1: XST 62 LUTs, 35 slices JohnpV1: SynplifyPro 57 LUTs, 33 slices JohnpV2: XST 78 LUTs, 43 slices JohnpV2: SynplifyPro 54 LUTs, 32 slices Brian: XST 57 LUTs, 39 slices Brian: SynplifyPro 57 LUTs, 41 slices The latest 3 pairs of results are interesting because even XST produces good results, especially in Brian's version where XST is surprisingly even slightly better. But anyway, it's not that XST is so clever, it is a clever coding of the design. Regards, Peter From newsfish@newsfish Fri Feb 3 13:11:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!t15g2000prt.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 08:30:40 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <8b8d17dd-1e65-4000-8912-9c489ca4693f@t15g2000prt.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> <6e12bda6-1e7c-4876-b240-b97bb074ec88@n11g2000vbm.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299083457 18617 127.0.0.1 (2 Mar 2011 16:30:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 16:30:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t15g2000prt.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14716 comp.lang.vhdl:4810 Thanks for publishing your results! It is interesting how little variance there is in the SynplifyPro results from widely different RTL implementations. This allows you, within limits, to code something so that it makes sense functionally to you and others, and the synthesis tool will still get pretty darn close to "the optimal" implementation so that it will work even in demanding environments (speed and/or space constrained). This also allows reuse of the same code across more environments. Andy From newsfish@newsfish Fri Feb 3 13:11:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 19:31:49 +0000 (UTC) Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> <6e12bda6-1e7c-4876-b240-b97bb074ec88@n11g2000vbm.googlegroups.com> <8b8d17dd-1e65-4000-8912-9c489ca4693f@t15g2000prt.googlegroups.com> Injection-Date: Wed, 2 Mar 2011 19:31:49 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="29325"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18L2WcY3TQra/qMY0h6SEBm" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:QK9i1QL5mgK4oMTMrMOLP8yI/b4= Xref: feeder.eternal-september.org comp.arch.fpga:14720 comp.lang.vhdl:4811 In comp.arch.fpga Andy wrote: > It is interesting how little variance there is in the SynplifyPro > results from widely different RTL implementations. This allows you, > within limits, to code something so that it makes sense functionally > to you and others, and the synthesis tool will still get pretty darn > close to "the optimal" implementation so that it will work even in > demanding environments (speed and/or space constrained). This also > allows reuse of the same code across more environments. As far as I know, yes, the tools are pretty good at optimizing combinatorial logic. This problem can be pipelined, though, and as far as I know the tools don't have a way to optimize that. You would at least have to specify the number of pipeline stages. It would be nice to have a tool that would optimize the partition between stages. Even more, given the clock frequency, it would be nice to have a tool that would find the optimal number of pipeline stages. -- glen From newsfish@newsfish Fri Feb 3 13:11:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a5g2000vbs.googlegroups.com!not-for-mail From: a s Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 12:38:09 -0800 (PST) Organization: http://groups.google.com Lines: 51 Message-ID: <71a752c4-a5e2-4c32-bbfb-2252a8f5bfe8@a5g2000vbs.googlegroups.com> References: <36d4291d-75de-4e19-bfa0-faefabbe6b70@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299098290 25496 127.0.0.1 (2 Mar 2011 20:38:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 20:38:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a5g2000vbs.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.98 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14723 comp.lang.vhdl:4812 On Mar 2, 5:52=A0pm, Gabor wrote: > I didn't catch which device you are targeting, but I > decided to try this myself with XST and Spartan 3A, > using Verilog to see if there are any significant > differences in synthesis performance. I am targeting Virtex4FX. > Here's the code: > module count_bits > #( > =A0 parameter IN_WIDTH =3D 32, > =A0 parameter OUT_WIDTH =3D 6 > ) > ( > =A0 input wire =A0[IN_WIDTH-1:0] =A0data_in, > =A0 output reg [OUT_WIDTH-1:0] =A0data_out > ); > > always @* > begin : proc > =A0 integer i; > =A0 integer sum; > =A0 sum =3D 0; > =A0 for (i =3D 0;i < IN_WIDTH;i =3D i + 1) sum =3D sum + data_in[i]; > =A0 data_out =3D sum; > end > > endmodule > > And the results for the 32-bit case (XST) > > Number of Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 41 =A0out o= f =A0 1792 =A0 =A0 2% =A0 > Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 73 =A0out of =A0 = 3584 =A0 =A0 2% =A0 > > which is very close to your original unrolled result. I get the same results with XST targeting V4. But that's really interesting how XST produces better results with Verilog than with VHDL for basically exactly the same input. Running your module through Synopsys results again in seemingly "optimum" 57LUTs and 34 slices. I find it pretty amusing how many options did we come up already with such a "basic" problem as is counting ones in a word. ;-) Regards From newsfish@newsfish Fri Feb 3 13:11:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED.131.215.176.116!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 20:53:34 +0000 (UTC) Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <36d4291d-75de-4e19-bfa0-faefabbe6b70@glegroupsg2000goo.googlegroups.com> <71a752c4-a5e2-4c32-bbfb-2252a8f5bfe8@a5g2000vbs.googlegroups.com> Injection-Date: Wed, 2 Mar 2011 20:53:34 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="131.215.176.116"; logging-data="26685"; mail-complaints-to="abuse@eternal-september.org" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Xref: feeder.eternal-september.org comp.arch.fpga:14724 comp.lang.vhdl:4813 In comp.arch.fpga a s wrote: (snip) > Running your module through Synopsys results again > in seemingly "optimum" 57LUTs and 34 slices. One should probably also compare propagation delay in addition to the number of LUTs or slices used. I don't believe it is large, but there is some tradeoff between the two. Worst delay would be (N-1) consecutive adders, increasing in width down the line. > I find it pretty amusing how many options did we come up already > with such a "basic" problem as is counting ones in a word. ;-) -- glen From newsfish@newsfish Fri Feb 3 13:11:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m7g2000vbq.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Wed, 2 Mar 2011 15:43:00 -0800 (PST) Organization: http://groups.google.com Lines: 40 Message-ID: <64a98040-8884-4a9d-a671-76f41ad07c33@m7g2000vbq.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> <6e12bda6-1e7c-4876-b240-b97bb074ec88@n11g2000vbm.googlegroups.com> <8b8d17dd-1e65-4000-8912-9c489ca4693f@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299109380 8988 127.0.0.1 (2 Mar 2011 23:43:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 2 Mar 2011 23:43:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000vbq.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14726 comp.lang.vhdl:4814 On Mar 2, 1:31=A0pm, glen herrmannsfeldt wrote: > As far as I know, yes, the tools are pretty good at optimizing > combinatorial logic. =A0This problem can be pipelined, though, and > as far as I know the tools don't have a way to optimize that. > > You would at least have to specify the number of pipeline stages. > It would be nice to have a tool that would optimize the partition > between stages. =A0Even more, given the clock frequency, it would be > nice to have a tool that would find the optimal number of pipeline > stages. =A0 > > -- glen Depending on which tools to which you are referring, yes they can be very good. But there is a large difference between some tools even in their ability to optimize purely combinatorial circuits, as shown in Peter's results. The Synplicity and Mentor tools have the capability to optimize logic across register boundaries (re-balancing). Some do it over more than one boundary (moving logic more than one clock cycle forward/back). You still have to model the pipeline stages, but that can be a simple register array tacked onto the beginning or end of the logic, and you just let the tool redistribute the logic amongst them. Latency often affects other portions of the design, so unless the entire design is "floated" WRT to latency (clock cycles or pipeline stages), it makes little sense for a local optimizing routine to pick the number of stages. The behavioral C synthesis tools (Catapult-C and others) take a completely untimed C algorithm in the form of a function, and allow you to trade resources, clock speed, latency, etc. with the help of different views including a Gant chart of various resources and their utilization. They also can synthesize different types of hardware interfaces, including registers, streaming data, memories (single and dual port), etc. around the function. Andy From newsfish@newsfish Fri Feb 3 13:11:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: glen herrmannsfeldt Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Thu, 3 Mar 2011 00:42:26 +0000 (UTC) Organization: A noiseless patient Spider Lines: 52 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> <831d0fc5-9526-4435-8f34-128a30ef0c3f@a8g2000pri.googlegroups.com> <6e12bda6-1e7c-4876-b240-b97bb074ec88@n11g2000vbm.googlegroups.com> <8b8d17dd-1e65-4000-8912-9c489ca4693f@t15g2000prt.googlegroups.com> <64a98040-8884-4a9d-a671-76f41ad07c33@m7g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 3 Mar 2011 00:42:26 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="VhYZ3ZDVkI1WvjO/5Jzlvw"; logging-data="26463"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+nK5sAaPKQECScHV0pTc5m" User-Agent: tin/1.9.6-20100522 ("Lochruan") (UNIX) (Linux/2.6.32-5-amd64 (x86_64)) Cancel-Lock: sha1:eSnnvtVfxlQZKmph6cXN1n2/Poo= Xref: feeder.eternal-september.org comp.arch.fpga:14728 comp.lang.vhdl:4815 In comp.arch.fpga Andy wrote: (after I wrote) >> As far as I know, yes, the tools are pretty good at optimizing >> combinatorial logic. This problem can be pipelined, though, and >> as far as I know the tools don't have a way to optimize that. > >> You would at least have to specify the number of pipeline stages. >> It would be nice to have a tool that would optimize the partition >> between stages. Even more, given the clock frequency, it would be >> nice to have a tool that would find the optimal number of pipeline >> stages. > Depending on which tools to which you are referring, yes they can be > very good. But there is a large difference between some tools even in > their ability to optimize purely combinatorial circuits, as shown in > Peter's results. > The Synplicity and Mentor tools have the capability to optimize logic > across register boundaries (re-balancing). Some do it over more than > one boundary (moving logic more than one clock cycle forward/back). > You still have to model the pipeline stages, but that can be a simple > register array tacked onto the beginning or end of the logic, and you > just let the tool redistribute the logic amongst them. That does sound pretty nice of them. Lately I mostly use Xilinx ISE which, as far as I know, doesn't do that. > Latency often affects other portions of the design, so unless the > entire design is "floated" WRT to latency (clock cycles or pipeline > stages), it makes little sense for a local optimizing routine to pick > the number of stages. I have done systolic array designs that do, as you say, float. The constraint is on the clock period. Though in addition there is the question of the number of unit cells that can fit into one FPGA. Throughput is clock frequency times (cells/FPGA). > The behavioral C synthesis tools (Catapult-C and others) take a > completely untimed C algorithm in the form of a function, and allow > you to trade resources, clock speed, latency, etc. with the help of > different views including a Gant chart of various resources and their > utilization. They also can synthesize different types of hardware > interfaces, including registers, streaming data, memories (single and > dual port), etc. around the function. Are there tools that will convert a sequential C code dynamic programming algorithm to a systolic array? That would be a pretty amazing optimization. -- glen From newsfish@newsfish Fri Feb 3 13:11:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!l14g2000pre.googlegroups.com!not-for-mail From: Don Otknow Newsgroups: comp.lang.vhdl Subject: DIfference between function and procedure Date: Thu, 3 Mar 2011 11:23:44 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: <26e707ea-8c2a-4efb-9d31-9eeb4c68e6e0@l14g2000pre.googlegroups.com> NNTP-Posting-Host: 174.62.68.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299180224 1953 127.0.0.1 (3 Mar 2011 19:23:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Mar 2011 19:23:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000pre.googlegroups.com; posting-host=174.62.68.188; posting-account=Ws3AqAoAAADYV_032p3vSJ-quHkhuKM0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4816 Hello, I've never really understood the difference between a function and a procedure in VHDL. I've read that a function returns 1 value whereas a procedure can return multiple values? Could someone elucidate this for me? Also, I am confused about the scope of signals. If I declare a signal within an architecture, does the scope of this signal extend to functions declared within processes in the architecture? If not, is there a way to do this without passing the signals? I would like to call functions in a way resembling scripts that allowed for greater code readability. Thanks, Don From newsfish@newsfish Fri Feb 3 13:11:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 03 Mar 2011 14:33:56 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: DIfference between function and procedure Date: Thu, 03 Mar 2011 20:37:01 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: <1utvm6t9ctslvl8qjlis4o5ijh8crgbfqj@4ax.com> References: <26e707ea-8c2a-4efb-9d31-9eeb4c68e6e0@l14g2000pre.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Lines: 52 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-gWESpW1CVmUITHpTTb8qzlcQ0n7CZRZ6biHAL5msKjk8j4AXfqXHoq22TErfmEV2lN3qIDBQsjYa/o5!6LXxlEoDI4++i+L3DyXKdpsvsgu9N6J9hLYG+c/vEn6a+IDDq1rYT9LtxFB3bzKsSdkS6J2GaAMX!vQ== X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3326 Xref: feeder.eternal-september.org comp.lang.vhdl:4817 On Thu, 3 Mar 2011 11:23:44 -0800 (PST), Don Otknow wrote: >Hello, > >I've never really understood the difference between a function and a >procedure in VHDL. I've read that a function returns 1 value whereas a >procedure can return multiple values? Could someone elucidate this for >me? Same as in just about any language except the C family. Function follows the basic pattern of a mathematical function; it (should) have no side-effects and it returns a value. It is an abstraction over an expression; it shouldn't change any term in that expression. Procedure returns NO values (though some of its parameters may have OUT or INOUT modes, which can be used to communicate results to the caller. ) It is an abstraction over a statement (or block, i.e. sequence of statements). >Also, I am confused about the scope of signals. If I declare a signal >within an architecture, does the scope of this signal extend to >functions declared within processes in the architecture? Yes. But please don't assign to that signal within a function! You can assign to that signal within a procedure. Functions and procedures (collectively, subprograms) can see the scope in which they are declared - plus their own local variables. So they can not only see signals outside the process, but any variables declared in the process (before their own declaration!) Parameters passed to the function or procedure come in useful when you want different calls of the procedure to operate on DIFFERENT signals. If you declare a library of useful subprograms in a package, you will find the visibility rules are different there, and you will normally pass parameters to them. One useful pattern is to keep the real subprograms there, and declare simple (e.g. parameterless) wrapper subprograms within your process, which simply call the real ones with appropriate parameters >I would like to >call functions in a way resembling scripts that allowed for greater >code readability. Good idea. But also; to allow programming - and hardware generation - at a higher level than VHDL is typically used for. - Brian From newsfish@newsfish Fri Feb 3 13:11:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!y31g2000prd.googlegroups.com!not-for-mail From: Don Otknow Newsgroups: comp.lang.vhdl Subject: Re: DIfference between function and procedure Date: Thu, 3 Mar 2011 13:34:10 -0800 (PST) Organization: http://groups.google.com Lines: 68 Message-ID: <81786c06-3eb2-49d1-95c2-08f7072145e7@y31g2000prd.googlegroups.com> References: <26e707ea-8c2a-4efb-9d31-9eeb4c68e6e0@l14g2000pre.googlegroups.com> <1utvm6t9ctslvl8qjlis4o5ijh8crgbfqj@4ax.com> NNTP-Posting-Host: 174.62.68.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299188051 1916 127.0.0.1 (3 Mar 2011 21:34:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 3 Mar 2011 21:34:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000prd.googlegroups.com; posting-host=174.62.68.188; posting-account=Ws3AqAoAAADYV_032p3vSJ-quHkhuKM0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101206 Ubuntu/10.04 (lucid) Firefox/3.6.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4818 On Mar 3, 12:37=A0pm, Brian Drummond wrote: > On Thu, 3 Mar 2011 11:23:44 -0800 (PST), Don Otknow > wrote: > > >Hello, > > >I've never really understood the difference between a function and a > >procedure in VHDL. I've read that a function returns 1 value whereas a > >procedure can return multiple values? Could someone elucidate this for > >me? > > Same as in just about any language except the C family. > > Function follows the basic pattern of a mathematical function; it (should= ) have > no side-effects and it returns a value. It is an abstraction over an expr= ession; > it shouldn't change any term in that expression. > > Procedure returns NO values (though some of its parameters may have OUT o= r INOUT > modes, which can be used to communicate results to the caller. ) It is an > abstraction over a statement (or block, i.e. sequence of statements). > > >Also, I am confused about the scope of signals. If I declare a signal > >within an architecture, does the scope of this signal extend to > >functions declared within processes in the architecture? > > Yes. > But please don't assign to that signal within a function! > You can assign to that signal within a procedure. > > Functions and procedures (collectively, subprograms) can see the scope in= which > they are declared - plus their own local variables. So they can not only = see > signals outside the process, but any variables declared in the process (b= efore > their own declaration!) > > Parameters passed to the function or procedure come in useful when you wa= nt > different calls of the procedure to operate on DIFFERENT signals. > > If you declare a library of useful subprograms in a package, you will fin= d the > visibility rules are different there, and you will normally pass paramete= rs to > them. One useful pattern is to keep the real subprograms there, and decla= re > simple (e.g. parameterless) wrapper subprograms within your process, whic= h > simply call the real ones with appropriate parameters > > >I would like to > >call functions in a way resembling scripts that allowed for greater > >code readability. > > Good idea. > But also; to allow programming - and hardware generation - at a higher le= vel > than VHDL is typically used for. > > - Brian Thanks a lot Brian! Your explanations are very helpful. From newsfish@newsfish Fri Feb 3 13:11:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4d700ea2$0$41110$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Wow! No TestbenchWow! Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Followup-To: comp.lang.verilog Date: Thu, 03 Mar 2011 22:56:49 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 91 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1299189410 news.xs4all.nl 41110 puiterl/[::ffff:195.242.97.150]:48213 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.arch.fpga:14741 comp.lang.vhdl:4819 comp.lang.verilog:2843 Jonathan Bromley wrote: > On Thu, 27 Jan 2011 06:22:19 -0800 (PST), rickman wrote: > >> Now I am learning how Verilog >>allows hierarchical path references to signals for test benches. This >>is awesome!!! > > Not as awesome as the ability to call tasks > (procedures) in a module, from another module. > That's just the neatest thing ever, for > stimulus generation. This little example > should give you a flavour of what you can do: > > `timescale 1ns/1ns > > module simulatedUartTransmitter(output reg TxD); > time bitTime; > // > task setBitTime(input time newBitTime); > bitTime = newBitTime; > endtask > > task sendChar(input [7:0] char); > begin > // send start bit > TxD = 0; > // send eight data bits, LSB first > repeat (8) begin > #(bitTime) TxD = char[0]; > char = char >> 1; > end > // send stop bit > #(bitTime) TxD = 1; > #(bitTime); > end > endtask > // > initial TxD = 1; // line idles in "Mark" state > // > endmodule > > module justTryThisOne; > // connections > wire serial_TxD; > // stimulus generator instance > simulatedUartTransmitter txGenerator(.TxD(serial_TxD)); > // > // There's no DUT in this example, but you can still > // see the signal generator at work. > // > // code to generate some stimulus > initial begin > txGenerator.setBitTime(104000); // 9600Bd, roughly > #1_000_000; // idle awhile before starting > txGenerator.sendChar("h"); // ask the sig-gen... > txGenerator.sendChar("i"); // ...to send some data > txGenerator.sendChar("!"); // ...at our request > #1_000_000; // idle awhile at the end > end > endmodule > > Utterly fantastic when you want to do stuff like > mimicking the behaviour of a CPU in your testbench. > Just write a module that can generate read or write > cycles on a bus, then connect an instance of it to > your DUT and get it to do accesses in the same way > you'd expect your CPU to behave. > > Apologies if this is stuff you've seen already. > It's so useful that I couldn't resist sharing > the example (again). Thanks for sharing. I've kept this for reference, as I don't use Verilog normally but want to keep up to date as much as possible. It is fantastically more simple than the hoops and loops you must go through when implementing this in VHDL. Been there, done that (or rather: doing that). And I am saying this as a VHDL aficionado. One question though: if the task sendChar is called concurrently from different procedural blocks in a way that the calls are overlapping, I think the result would be a great mess (I am saying this as a not so great lover of how Verilog works). Is there a simple way to deal with collisions like that? Or will the simplicity be lost then for the most part? -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:11:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t15g2000prt.googlegroups.com!not-for-mail From: Don Otknow Newsgroups: comp.lang.vhdl Subject: Structs in VHDL Date: Fri, 4 Mar 2011 11:40:09 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> NNTP-Posting-Host: 174.62.68.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299267609 28237 127.0.0.1 (4 Mar 2011 19:40:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Mar 2011 19:40:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t15g2000prt.googlegroups.com; posting-host=174.62.68.188; posting-account=Ws3AqAoAAADYV_032p3vSJ-quHkhuKM0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4820 Hello, I want to know if there is a way to group variables in VHDL that self- documents better than an array and allows for different types (IE the equivalent of a C struct). Is the record type this? Can one use signals and variables inside a record, and can a single record have both? Synthesis issues? Thanks, Don From newsfish@newsfish Fri Feb 3 13:11:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder5.news.weretis.net!feeder.news-service.com!postnews.google.com!w9g2000prg.googlegroups.com!not-for-mail From: JustJohn Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Fri, 4 Mar 2011 12:08:59 -0800 (PST) Organization: http://groups.google.com Lines: 119 Message-ID: <92031db7-f5ed-4e34-acb3-deba3c9c0b43@w9g2000prg.googlegroups.com> References: <36d4291d-75de-4e19-bfa0-faefabbe6b70@glegroupsg2000goo.googlegroups.com> <71a752c4-a5e2-4c32-bbfb-2252a8f5bfe8@a5g2000vbs.googlegroups.com> NNTP-Posting-Host: 76.88.81.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299269339 21418 127.0.0.1 (4 Mar 2011 20:08:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Mar 2011 20:08:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w9g2000prg.googlegroups.com; posting-host=76.88.81.145; posting-account=fukjzwoAAABuHemapiIrZ6w3ib3NTUtL User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB6.6; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14751 comp.lang.vhdl:4821 On Mar 2, 12:38=A0pm, a s wrote: > On Mar 2, 5:52=A0pm, Gabor wrote: > > > I didn't catch which device you are targeting, but I > > decided to try this myself with XST and Spartan 3A, > > using Verilog to see if there are any significant > > differences in synthesis performance. > > I am targeting Virtex4FX. > > > > > > > Here's the code: > > module count_bits > > #( > > =A0 parameter IN_WIDTH =3D 32, > > =A0 parameter OUT_WIDTH =3D 6 > > ) > > ( > > =A0 input wire =A0[IN_WIDTH-1:0] =A0data_in, > > =A0 output reg [OUT_WIDTH-1:0] =A0data_out > > ); > > > always @* > > begin : proc > > =A0 integer i; > > =A0 integer sum; > > =A0 sum =3D 0; > > =A0 for (i =3D 0;i < IN_WIDTH;i =3D i + 1) sum =3D sum + data_in[i]; > > =A0 data_out =3D sum; > > end > > > endmodule > > > And the results for the 32-bit case (XST) > > > Number of Slices: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 41 =A0out= of =A0 1792 =A0 =A0 2% =A0 > > Number of 4 input LUTs: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 73 =A0out of = =A0 3584 =A0 =A0 2% =A0 > > > which is very close to your original unrolled result. > > I get the same results with XST targeting V4. > > But that's really interesting how XST produces better results > with Verilog than with VHDL for basically exactly the same input. > > Running your module through Synopsys results again > in seemingly "optimum" 57LUTs and 34 slices. > > I find it pretty amusing how many options did we come up already > with such a "basic" problem as is counting ones in a word. ;-) > > Regards- Hide quoted text - > > - Show quoted text - Eight years ago (Sept/Oct 2003), we went through this exercise in the thread "Counting Ones" (I was posting as JustJohn back then, not John_H). See that thread for some ASCII art of the trees. I ended up with the following VHDL function that produces "optimum" 55 4-input LUTs for 32-bit vector input. I haven't seen anything better yet. I liked Andy's recursion suggestion, it'll take some thought to figure out how to auto-distribute the carry-in bits to the adders. Yesterday, Gabor posted 35 6-input LUTs. Gabor, what code did you use? I think a nice challenge to the C.A.F. group mind is to beat that. John L. Smith -- This function counts bits =3D '1' in a 32-bit word, using a tree -- structure with Full Adders at leafs for "minimum" logic utilization. function vec32_sum2( in_vec : in UNSIGNED ) return UNSIGNED is type FA_Arr_Type is array ( 0 to 9 ) of UNSIGNED( 1 downto 0 ); variable FA_Array : FA_Arr_Type; variable result : UNSIGNED( 5 downto 0 ); variable Leaf_Bits : UNSIGNED( 2 downto 0 ); variable Sum3_1 : UNSIGNED( 2 downto 0 ); variable Sum3_2 : UNSIGNED( 2 downto 0 ); variable Sum3_3 : UNSIGNED( 2 downto 0 ); variable Sum3_4 : UNSIGNED( 2 downto 0 ); variable Sum3_5 : UNSIGNED( 2 downto 0 ); variable Sum4_1 : UNSIGNED( 3 downto 0 ); variable Sum4_2 : UNSIGNED( 3 downto 0 ); variable Sum5_1 : UNSIGNED( 4 downto 0 ); begin for i in 0 to 9 loop Leaf_Bits :=3D in_vec( 3 * i + 2 downto 3 * i ); case Leaf_Bits is when "000" =3D> FA_Array( i ) :=3D "00"; when "001" =3D> FA_Array( i ) :=3D "01"; when "010" =3D> FA_Array( i ) :=3D "01"; when "011" =3D> FA_Array( i ) :=3D "10"; when "100" =3D> FA_Array( i ) :=3D "01"; when "101" =3D> FA_Array( i ) :=3D "10"; when "110" =3D> FA_Array( i ) :=3D "10"; when others =3D> FA_Array( i ) :=3D "11"; end case; end loop; Sum3_1 :=3D ( "0" & FA_Array( 0 ) ) + ( "0" & FA_Array( 1 ) ); Sum3_2 :=3D ( "0" & FA_Array( 2 ) ) + ( "0" & FA_Array( 3 ) ); Sum3_3 :=3D ( "0" & FA_Array( 4 ) ) + ( "0" & FA_Array( 5 ) ); Sum3_4 :=3D ( "0" & FA_Array( 6 ) ) + ( "0" & FA_Array( 7 ) ) + ( "00" & in_vec( 30 ) ); Sum3_5 :=3D ( "0" & FA_Array( 8 ) ) + ( "0" & FA_Array( 9 ) ) + ( "00" & in_vec( 31 ) ); Sum4_1 :=3D ( "0" & Sum3_1 ) + ( "0" & Sum3_2 ); Sum4_2 :=3D ( "0" & Sum3_3 ) + ( "0" & Sum3_4 ); Sum5_1 :=3D ( "0" & Sum4_1 ) + ( "0" & Sum4_2 ); result :=3D ( "0" & Sum5_1 ) + ( "000" & Sum3_5 ); return result; end vec32_sum2; From newsfish@newsfish Fri Feb 3 13:11:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!xlned.com!feeder7.xlned.com!news2.euro.net!newsfeed.freenet.ag!newsfeed.kamp.net!newsfeed0.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Structs in VHDL Date: Fri, 04 Mar 2011 12:33:44 -0800 Lines: 25 Message-ID: <8td0kkFjkeU1@mid.individual.net> References: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net U6eWh8dtMdFI8XctLASuigmIiSz/Ti6e/BbyI8BrxzKyBIg7Fn Cancel-Lock: sha1:fs7srOOGRrYgSLZM7hf2SGs9MMI= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.14) Gecko/20110221 Lightning/1.0b2 Thunderbird/3.1.8 In-Reply-To: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4822 On 3/4/2011 11:40 AM, Don Otknow wrote: > I want to know if there is a way to group variables in VHDL that self- > documents better than an array and allows for different types (IE the > equivalent of a C struct). Is the record type this? Yes, but not exactly. > Can one use > signals and variables inside a record, I can use a record variable inside a process or I can use a record signal inside an architecture. > and can a single record have > both? No. A record is *type* of signal, variable or constant. Synthesis issues? These are minimized by avoiding record type ports. Goggle comp.lang.vhdl. That subject has been beaten to death. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:11:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p3g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Structs in VHDL Date: Fri, 4 Mar 2011 15:30:51 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <0a614dc5-430a-465e-9564-d847aa10e141@p3g2000vbv.googlegroups.com> References: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> <8td0kkFjkeU1@mid.individual.net> NNTP-Posting-Host: 213.104.218.203 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299281451 15726 127.0.0.1 (4 Mar 2011 23:30:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 4 Mar 2011 23:30:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p3g2000vbv.googlegroups.com; posting-host=213.104.218.203; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.13) Gecko/20101203 Firefox/3.6.13 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4823 > > Synthesis issues? > > These are minimized by avoiding record type ports. > Goggle comp.lang.vhdl. That subject has been beaten to death. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler Avoid record types for ports - since when? Maybe for inouts, but for single direction they are handy. From newsfish@newsfish Fri Feb 3 13:11:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Fri, 4 Mar 2011 19:28:02 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: <096757fd-219b-4e7a-ac74-6efe701ee1c4@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 71.255.144.148 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299295683 31093 127.0.0.1 (5 Mar 2011 03:28:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 5 Mar 2011 03:28:03 +0000 (UTC) In-Reply-To: <92031db7-f5ed-4e34-acb3-deba3c9c0b43@w9g2000prg.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=71.255.144.148; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4824 On Friday, March 4, 2011 3:08:59 PM UTC-5, JustJohn wrote: [snip] > > Yesterday, Gabor posted 35 6-input LUTs. > Gabor, what code did you use? I posted the Verilog, it's just a simple loop. The difference was targeting V6 in XST 12.1 Looking through the synthesis report it became apparent that there are some new templates for "adder tree" that show up in the V6 implementation but not for V5. This seems to be the reason for the dramatic reduction going from V5 to V6 while both have 6-input LUT's. Only XST for V6 has the adder tree templates, so it got 65 LUT's down to 35. I haven't really thought about an optimal implementation for 6-input LUT's but given the fact that XST inferred a tree structure, it's probably pretty close to optimal already. -- Gabor From newsfish@newsfish Fri Feb 3 13:11:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 05 Mar 2011 01:41:49 -0600 From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Structs in VHDL Date: Sat, 05 Mar 2011 07:44:56 +0000 Reply-To: brian@shapes.demon.co.uk Message-ID: References: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> <8td0kkFjkeU1@mid.individual.net> <0a614dc5-430a-465e-9564-d847aa10e141@p3g2000vbv.googlegroups.com> X-Newsreader: Forte Agent 1.7/32.534 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 30 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-BmVCCL8CB9ReE6HrDa/ucwvTGdgTThBSgV80VymBEO9kWCi+lN31vwPxBxp9zBscQ2HH0hruLLRnbc0!BnqDzFef0CZk/RD5mWW2Bssul7QwFJfb9OGD7m+hphAtTM8DP7LVJLKE6XZUOBlEgZ+dR+vzp92Z!SRVY X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2313 Xref: feeder.eternal-september.org comp.lang.vhdl:4825 On Fri, 4 Mar 2011 15:30:51 -0800 (PST), Tricky wrote: > >> >> Synthesis issues? >> >> These are minimized by avoiding record type ports. >> Goggle comp.lang.vhdl. That subject has been beaten to death. >> >> -- Mike Treseler > >Avoid record types for ports - since when? Maybe for inouts, but for >single direction they are handy. The problem with inout ports being that you cannot (currently) drive different elements of the record in different directions. Which means you can't wrap Address, Data, Read, Write, Ack into a record (dammit...) Closest solution is two records : Address, Data_Out, Read, Write in one; Data_In and Ack in the other. (Bidirectional buses are deprecated inside new FPGAs anyway) Also avoid them for external (off-chip) ports. Synthesis etc will convert all off-chip signals to std_[u]_logic[_vector]. Which makes dropping the post-synth netlist into your testbench a pain, unless you create a wrapper to convert port types. Other than these, I can't think of any synthesis issues. - Brian From newsfish@newsfish Fri Feb 3 13:11:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!u24g2000prn.googlegroups.com!not-for-mail From: JustJohn Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Sun, 6 Mar 2011 23:30:07 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 76.88.81.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299483083 26218 127.0.0.1 (7 Mar 2011 07:31:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 7 Mar 2011 07:31:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u24g2000prn.googlegroups.com; posting-host=76.88.81.145; posting-account=fukjzwoAAABuHemapiIrZ6w3ib3NTUtL User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB6.6; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14776 comp.lang.vhdl:4826 On Mar 1, 8:41=A0am, Peter wrote: > Andy, I completely agree with what you have written above. > One should strive for maintainable and understandable version. > Although, on my particular case, I have to find a good solution > in terms of LUT resources, because I need 8 instances of > one counters with 64-bit input data. And the device is getting full... Peter, It looks like you've solved your problem simply by moving to a better synthesis tool, so this may not be of interest anymore. However, in addition to space, finding a more compact implementation often leads to a speed increase as well, AND power savings. Additionally, I like this counting bits problem, it turns up often enough that it deserves some attention. As to maintainability, nothing promotes that more than good comments. Once the function is written it can be stuffed away in a package, never dealt with again (If anyone copies the code, please include credit). See my other post for the most compact/fastest way to implement the 32- bit sum using 4-LUTs and taking advantage of carry logic fabric. Gabor's post of the 35 LUT number when using 6-LUTs got me looking at that case. Here are the results (Spartan 3 for the 4-LUTs, Spartan 6 for the 6-LUTs, XST for both, I'd be curious if any other synthesis tool does better). Synthesizers continually improve, but nothing beats a good look at the problem, as the 6-LUT case illustrates with a better than 2:1 savings: vec32_sum2: 4-input LUTs: 53 Slices: 31 vec32_sum3: 6-input LUTs: 15 Slices: 4 Finally, this is a neat problem because it's nice to make the little things count. Best regards all, John L. Smith Code for 6-LUT based 32 bit sum: function vec32_sum3( in_vec : in UNSIGNED ) return UNSIGNED is type Leaf_type is array ( 0 to 63 ) of UNSIGNED( 2 downto 0 ); -- Each ROM entry is sum of address bits: constant Leaf_ROM : Leaf_type :=3D ( "000", "001", "001", "010", "001", "010", "010", "011", "001", "010", "010", "011", "010", "011", "011", "100", "001", "010", "010", "011", "010", "011", "011", "100", "010", "011", "011", "100", "011", "100", "100", "101", "001", "010", "010", "011", "010", "011", "011", "100", "010", "011", "011", "100", "011", "100", "100", "101", "010", "011", "011", "100", "011", "100", "100", "101", "011", "100", "100", "101", "100", "101", "101", "110" ); type S3_Type is array ( 0 to 4 ) of UNSIGNED( 2 downto 0 ); variable S3 : S3_Type; variable result : UNSIGNED( 5 downto 0 ); variable Leaf_Bits : natural range 0 to 63; variable S4_1 : UNSIGNED( 3 downto 0 ); variable S4_2 : UNSIGNED( 3 downto 0 ); variable S5_1 : UNSIGNED( 4 downto 0 ); begin -- Form five 3-bit sums using three 6-LUTs each: for i in 0 to 4 loop Leaf_Bits :=3D TO_INTEGER( UNSIGNED( in_vec( 6 * i + 5 downto 6 * i ) ) ); S3( i ) :=3D Leaf_ROM( Leaf_Bits ); end loop; -- Add two 3-bit sums + leftover leaf bits as a carry in to get 4 bit sums: S4_1 :=3D ( "0" & S3( 0 ) ) + ( "0" & S3( 1 ) ) + ( "000" & in_vec( 30 ) ); S4_2 :=3D ( "0" & S3( 2 ) ) + ( "0" & S3( 3 ) ) + ( "000" & in_vec( 31 ) ); -- Add 4 bit sums to get 5 bit sum: S5_1 :=3D ( "0" & S4_1 ) + ( "0" & S4_2 ); -- Add leftover 3 bit sum to get 5 bit result: result :=3D ( "0" & S5_1 ) + ( "000" & S3( 4 ) ); return result; end vec32_sum3; From newsfish@newsfish Fri Feb 3 13:11:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m7g2000vbq.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Structs in VHDL Date: Tue, 8 Mar 2011 01:00:51 -0800 (PST) Organization: http://groups.google.com Lines: 16 Message-ID: <3b253814-9983-4218-8a46-472057694495@m7g2000vbq.googlegroups.com> References: <790c0c27-bf5c-4285-ab5e-ca3fc8cd0c31@t15g2000prt.googlegroups.com> <8td0kkFjkeU1@mid.individual.net> <0a614dc5-430a-465e-9564-d847aa10e141@p3g2000vbv.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299574852 32521 127.0.0.1 (8 Mar 2011 09:00:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Mar 2011 09:00:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000vbq.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.7612) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4827 On 5 Mrz., 08:44, Brian Drummond wrote: > Also avoid them for external (off-chip) ports. Synthesis etc will convert all > off-chip signals to std_[u]_logic[_vector]. Which makes dropping the post-synth > netlist into your testbench a pain, unless you create a wrapper to convert port > types. > > Other than these, I can't think of any synthesis issues. Synopsys DC converts all elements of the record into one array. No problem for small records, but it makes design handling quite hard, if your record is complex or nested and has some wide bus. I once had seen a record as Input that results in an array of more than 100 bits as Input after synthesis on top level of the design. Was no fun to collect adress, data and control signals out of this bus. bye Thomas From newsfish@newsfish Fri Feb 3 13:11:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!m7g2000vbq.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Anti-benchmarking clauses Date: Tue, 8 Mar 2011 07:09:58 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299596998 8743 127.0.0.1 (8 Mar 2011 15:09:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Mar 2011 15:09:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m7g2000vbq.googlegroups.com; posting-host=195.144.71.15; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.107 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4828 comp.arch.fpga:14787 comp.lang.verilog:2849 It was interesting to read some synthesis benchmarking results on comp.lang.vhdl last week. I feel it's high time that EDA vendors drop the anti-benchmarking clauses from their license agreements: http://www.sigasi.com/content/your-milage-may-vary-lot To summarize my points: 1. There is no clear definition of what a "benchmark result" is, you don't know when you are breaching the contract. 2. Public benchmarking hinders competition and innovation. 3. Customers deserve to be treated with more respect. I'd love to hear your thoughts, either on this newsgroup, or on my webpage. kind regards -- Philippe www.sigasi.com From newsfish@newsfish Fri Feb 3 13:11:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s18g2000prg.googlegroups.com!not-for-mail From: JustJohn Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Count bits in VHDL, with loop and unrolled loop produces different results Date: Tue, 8 Mar 2011 09:35:25 -0800 (PST) Organization: http://groups.google.com Lines: 53 Message-ID: <7a84c12b-9f83-404e-8a5d-825786f8d523@s18g2000prg.googlegroups.com> References: <8d449b0c-a18a-4246-b540-7d4904bdafc4@b8g2000vbi.googlegroups.com> NNTP-Posting-Host: 76.88.81.145 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299605726 24138 127.0.0.1 (8 Mar 2011 17:35:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 8 Mar 2011 17:35:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s18g2000prg.googlegroups.com; posting-host=76.88.81.145; posting-account=fukjzwoAAABuHemapiIrZ6w3ib3NTUtL User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; GTB6.6; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:14791 comp.lang.vhdl:4829 On Mar 6, 11:30=A0pm, JustJohn wrote: > On Mar 1, 8:41=A0am, Peter wrote: > > > Andy, I completely agree with what you have written above. > > One should strive for maintainable and understandable version. > > Although, on my particular case, I have to find a good solution > > in terms of LUT resources, because I need 8 instances of > > one counters with 64-bit input data. And the device is getting full... > > Peter, > =A0 It looks like you've solved your problem simply by moving to a > better synthesis tool, so this may not be of interest anymore. > However, in addition to space, finding a more compact implementation > often leads to a speed increase as well, AND power savings. > Additionally, I like this counting bits problem, it turns up often > enough that it deserves some attention. As to maintainability, nothing > promotes that more than good comments. Once the function is written it > can be stuffed away in a package, never dealt with again (If anyone > copies the code, please include credit). > > See my other post for the most compact/fastest way to implement the 32- > bit sum using 4-LUTs and taking advantage of carry logic fabric. > Gabor's post of the 35 LUT number when using 6-LUTs got me looking at > that case. Here are the results (Spartan 3 for the 4-LUTs, Spartan 6 > for the 6-LUTs, XST for both, I'd be curious if any other synthesis > tool does better). Synthesizers continually improve, but nothing beats > a good look at the problem, as the 6-LUT case illustrates with a > better than 2:1 savings: > > =A0 vec32_sum2: =A04-input LUTs: 53 =A0Slices: 31 > =A0 vec32_sum3: =A06-input LUTs: 15 =A0Slices: 4 > > Finally, this is a neat problem because it's nice to make the little > things count. > > Best regards all, > John L. Smith > Chagrinned OOPS!, synthesizer was throwing the leaf ROMs into BRAMs for the 6-LUT case. Actual numbers for the 6-LUT case without BRAMs are (and this is not a synthesis benchmark, it is an illustraion of efficient circuit structure expressed via coding style to reduce LUT usage, applicable across all synthesis tools, thanks for the warning Philippe, and BTW I AGREE, EULAs forbidding benchmarks are evil): vec32_sum3: 6-input LUTs: 30 Slices: 4 Still tops 35, although some may consider the code too complex for marginal improvement. Regards, John From newsfish@newsfish Fri Feb 3 13:11:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!o15g2000vbl.googlegroups.com!not-for-mail From: Brian Davis Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Tue, 8 Mar 2011 18:22:22 -0800 (PST) Organization: http://groups.google.com Lines: 67 Message-ID: <2747bfd9-17fa-4efc-b98b-4fd71bbc21f3@o15g2000vbl.googlegroups.com> References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> NNTP-Posting-Host: 72.64.4.237 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299637712 29986 127.0.0.1 (9 Mar 2011 02:28:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 9 Mar 2011 02:28:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o15g2000vbl.googlegroups.com; posting-host=72.64.4.237; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4830 comp.arch.fpga:14798 comp.lang.verilog:2850 Philippe posted: > > 1. There is no clear definition of what a "benchmark result" is, > you don't know when you are breaching the contract. > I agree that those clauses are a bit much. FYI, about a decade ago, there was some vendor clarification regarding this issue on comp.arch.fpga in the context of posting _single_ vendor Brand S result variations vs. tool settings/coding style: In 2001, I had posted [1] a summary of LUT counts vs. tool settings on a thread about big counters: > >And tweaking counter size/target frequency, gives: > > Synplify Synplify > CNT_MSB Frequency LUT count > __________________________________________ > 55 77 57 > 55 78 110 > > 31 95 33 > 31 96 46 > 31 122 46 > 31 123 83 > On a nearby thread about license benchmarking clauses [2], Andy P. posted [3], somewhat tongue-in-cheek : > > Uh oh! The person who posted Synplify's results for that > 56-bit counter problem is in line for an ass-whooping! > I replied [4] in part: > > Personally, I wouldn't consider answering a question on how > to make a counter synthesize better to be a "benchmark"... > Then Ken M. of Brand S, formerly known as Brand S, posted [5]: > > We don't consider it to be a "benchmark" either. > Brian Davis [1] post from thread "High level synthesis will never work well" http://groups.google.com/group/comp.arch.fpga/msg/01e9d02b8e85983d [2] Thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/a201fc7f4a639215 [3] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/6f9694e180581202 [4] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/172b3fbcb1ffe4a5 [5] post from thread "Synplicity/Leonardo License Agreement Information" http://groups.google.com/group/comp.arch.fpga/msg/52f4c2a915b383d3 From newsfish@newsfish Fri Feb 3 13:11:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!p12g2000vbo.googlegroups.com!not-for-mail From: pbartosz Newsgroups: comp.lang.vhdl Subject: Generics in VHDL - number of components Date: Wed, 9 Mar 2011 04:40:24 -0800 (PST) Organization: http://groups.google.com Lines: 4 Message-ID: <9314ae91-6279-4fe0-89d0-e2f275a87119@p12g2000vbo.googlegroups.com> NNTP-Posting-Host: 149.156.96.14 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299674519 13556 127.0.0.1 (9 Mar 2011 12:41:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 9 Mar 2011 12:41:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p12g2000vbo.googlegroups.com; posting-host=149.156.96.14; posting-account=jZyXKwoAAAA8AI09i4lgLgFwqJh4fw6g User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; pl-PL; rv:1.9.1.16) Gecko/20110107 Iceweasel/3.5.16 (like Firefox/3.5.16),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4831 I have an entity that is generic. For generic value N I'd like there were N the same components (with single input signal) connected to demultiplexer with N output signals. Is this doable (especially number of components dependent of generic value)? Sample code, please. From newsfish@newsfish Fri Feb 3 13:11:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r4g2000vbq.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Wed, 9 Mar 2011 04:57:43 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <42282a89-e457-49ba-95e2-51c511e2c411@r4g2000vbq.googlegroups.com> References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> <2747bfd9-17fa-4efc-b98b-4fd71bbc21f3@o15g2000vbl.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299675464 22309 127.0.0.1 (9 Mar 2011 12:57:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 9 Mar 2011 12:57:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r4g2000vbq.googlegroups.com; posting-host=195.144.71.15; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10_6_6; en-US) AppleWebKit/534.13 (KHTML, like Gecko) Chrome/9.0.597.107 Safari/534.13,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4832 comp.arch.fpga:14803 comp.lang.verilog:2851 Hi Brian, Thanks for pointing to this conversation from 2001. It seems that EDA vendors are not interested in enforcing this clause for small benchmark results. Still it gives them a stick to hit you with if you would ever publish something serious. That leaves al the benchmarking work for the brave and those with little to loose. -- Philippe http://www.sigasi.com From newsfish@newsfish Fri Feb 3 13:11:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v11g2000prb.googlegroups.com!not-for-mail From: JB Newsgroups: comp.lang.vhdl Subject: Re: Generics in VHDL - number of components Date: Wed, 9 Mar 2011 06:00:43 -0800 (PST) Organization: http://groups.google.com Lines: 7 Message-ID: References: <9314ae91-6279-4fe0-89d0-e2f275a87119@p12g2000vbo.googlegroups.com> NNTP-Posting-Host: 80.14.138.198 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299679243 24624 127.0.0.1 (9 Mar 2011 14:00:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 9 Mar 2011 14:00:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v11g2000prb.googlegroups.com; posting-host=80.14.138.198; posting-account=S4wEMQoAAADRjpmXQT29euLGCs6HM3WR User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; fr; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4833 On 9 mar, 13:40, pbartosz wrote: > I have an entity that is generic. For generic value N I'd like there > were N the same components (with single input signal) connected to > demultiplexer with N output signals. Is this doable (especially number > of components dependent of generic value)? Sample code, please. Yes it is doable, a generate loop can instantiate your N components. From newsfish@newsfish Fri Feb 3 13:11:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!c8g2000vbv.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: Generics in VHDL - number of components Date: Wed, 9 Mar 2011 06:47:41 -0800 (PST) Organization: http://groups.google.com Lines: 34 Message-ID: <05f1e09a-fc48-492d-a611-349257c21bec@c8g2000vbv.googlegroups.com> References: <9314ae91-6279-4fe0-89d0-e2f275a87119@p12g2000vbo.googlegroups.com> NNTP-Posting-Host: 134.102.219.52 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299682061 19030 127.0.0.1 (9 Mar 2011 14:47:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 9 Mar 2011 14:47:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c8g2000vbv.googlegroups.com; posting-host=134.102.219.52; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; de; rv:1.9.2.15) Gecko/20110303 Ubuntu/10.04 (lucid) Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4834 On Mar 9, 3:00=A0pm, JB wrote: > On 9 mar, 13:40, pbartosz wrote: > > > I have an entity that is generic. For generic value N I'd like there > > were N the same components (with single input signal) connected to > > demultiplexer with N output signals. Is this doable (especially number > > of components dependent of generic value)? Sample code, please. > > Yes it is doable, a generate loop can instantiate your N components. E.g.: gen_ramb16_s1_s36 : for i in 0 to NUMBER_OF_RAMS_REQUIRED_C - 1 generate RAMB16_S9_INSTANCE_NAME : RAMB16_S9 -- synthesis translate_off generic map ( INIT =3D> bit_value, SRVAL =3D> bit_value, write_mode =3D> user_WRITE_MODE, -- [...] INITP_07 =3D> vector_value) -- synopsys translate_on port map ( DO =3D> DO_RAM(i), DOP =3D> open, ADDR =3D> ADDR_RAM, CLK =3D> tcm8230md_sys_clk, DI =3D> tcm8239md_dout_s, DIP =3D> (others =3D> '0'), EN =3D> '1', -- !!! SSR =3D> '0', WE =3D> WE_RAM(i)); end generate; From newsfish@newsfish Fri Feb 3 13:11:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: Kolja Sulimma Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Thu, 10 Mar 2011 03:59:26 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: <66014c12-24b9-4a93-8358-1f4179559ed1@t16g2000vbi.googlegroups.com> References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> NNTP-Posting-Host: 79.255.2.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299758366 10115 127.0.0.1 (10 Mar 2011 11:59:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 11:59:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=79.255.2.74; posting-account=GgLtCgoAAAD1eGcaDvWVJ6l90w-YMYMc User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4835 comp.arch.fpga:14808 comp.lang.verilog:2852 On 8 Mrz., 16:09, Philippe wrote: > It was interesting to read some synthesis benchmarking results on > comp.lang.vhdl last week. I feel it's high time that EDA vendors drop > the anti-benchmarking clauses from their license agreements: Just make sure to purchase software in a way where that license agreement ist not included in a contract. A sales contract is finalized when goods and money have been exchanged. Afterwards no clauses can be added to the contract by one side alone. At least in Germany it is well established by court that this holds for software sales, and other countries have similar contract law. So as long as the clause is not included in a click through contract during a download purchase, or is presented to you before purchase in another way, the clause does not become part of the contract. Clauses presented during installation are irrelevant. Also note: Your contract is with the reseller, not with the vendor of the software. So information on the vendor homepage is irrelavant. For private users (not companies) the clause anyway is likely to violate EU law, because it is a surprising clause. Kolja From newsfish@newsfish Fri Feb 3 13:11:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!k15g2000prk.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: assert question Date: Thu, 10 Mar 2011 06:51:13 -0800 (PST) Organization: http://groups.google.com Lines: 21 Message-ID: <311dc0f0-ef3d-465b-89f7-cdd8dafb4aaa@k15g2000prk.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299768719 28591 127.0.0.1 (10 Mar 2011 14:51:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 14:51:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k15g2000prk.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.127 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4836 Hi everyone, I was wondering if I can do the following in VHDL : my_process : process(CLK) begin if rising_edge(CLK) then if (load_reg = '1') then assert unsigned(DATA) > 10 report "error, DATA must be greater than 10" severity error; end if; end if; end process; I've tried the following code in Active-HDL, and no assertions were triggered in simulation even though there should have. Is it supposed to trigger? Is there another way to write that assertion? Best regards From newsfish@newsfish Fri Feb 3 13:11:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r17g2000vbc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: assert question Date: Thu, 10 Mar 2011 07:17:30 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: <82430b6f-11cc-4376-833f-8d5153990590@r17g2000vbc.googlegroups.com> References: <311dc0f0-ef3d-465b-89f7-cdd8dafb4aaa@k15g2000prk.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299770251 12425 127.0.0.1 (10 Mar 2011 15:17:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 15:17:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r17g2000vbc.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4837 On Mar 10, 2:51=A0pm, Benjamin Couillard wrote: > Hi everyone, > > I was wondering if I can do the following in VHDL : > > my_process : process(CLK) > begin > =A0 =A0if rising_edge(CLK) then > =A0 =A0 =A0if (load_reg =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 assert unsigned(DATA) > 10 > =A0 =A0 =A0 =A0 =A0 =A0 report "error, DATA must be greater than 10" > =A0 =A0 =A0 =A0 =A0 =A0 severity error; > =A0 =A0 =A0end if; > =A0 =A0end if; > end process; > > I've tried the following code in Active-HDL, and no assertions were > triggered in simulation even though there should have. Is it supposed > to trigger? Is there another way to write that assertion? > > Best regards Theres nothing wrong with the code. I can only assume that DATA is greater than 10 whenever the process triggers. Or load_reg =3D '0'. From newsfish@newsfish Fri Feb 3 13:11:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x8g2000prh.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: assert question Date: Thu, 10 Mar 2011 07:20:28 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: <6e1583b3-9969-492d-a65f-cdeb5d5bfb77@x8g2000prh.googlegroups.com> References: <311dc0f0-ef3d-465b-89f7-cdd8dafb4aaa@k15g2000prk.googlegroups.com> <82430b6f-11cc-4376-833f-8d5153990590@r17g2000vbc.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299770494 24357 127.0.0.1 (10 Mar 2011 15:21:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 15:21:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x8g2000prh.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.127 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4838 On 10 mar, 10:17, Tricky wrote: > On Mar 10, 2:51=A0pm, Benjamin Couillard > wrote: > > > > > > > > > > > Hi everyone, > > > I was wondering if I can do the following in VHDL : > > > my_process : process(CLK) > > begin > > =A0 =A0if rising_edge(CLK) then > > =A0 =A0 =A0if (load_reg =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 assert unsigned(DATA) > 10 > > =A0 =A0 =A0 =A0 =A0 =A0 report "error, DATA must be greater than 10" > > =A0 =A0 =A0 =A0 =A0 =A0 severity error; > > =A0 =A0 =A0end if; > > =A0 =A0end if; > > end process; > > > I've tried the following code in Active-HDL, and no assertions were > > triggered in simulation even though there should have. Is it supposed > > to trigger? Is there another way to write that assertion? > > > Best regards > > Theres nothing wrong with the code. I can only assume that DATA is > greater than 10 whenever the process triggers. Or load_reg =3D '0'. Ok, I found out what the problem was. I was using variables instead of signals in the assert statement (I simplified my statement a bit to make it easier to understand) and I didn't realize that it would solve the problem. From newsfish@newsfish Fri Feb 3 13:11:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!xlned.com!feeder7.xlned.com!news2.euro.net!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y31g2000prd.googlegroups.com!not-for-mail From: Don Otknow Newsgroups: comp.lang.vhdl Subject: Re: assert question Date: Thu, 10 Mar 2011 13:01:05 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: References: <311dc0f0-ef3d-465b-89f7-cdd8dafb4aaa@k15g2000prk.googlegroups.com> <82430b6f-11cc-4376-833f-8d5153990590@r17g2000vbc.googlegroups.com> <6e1583b3-9969-492d-a65f-cdeb5d5bfb77@x8g2000prh.googlegroups.com> NNTP-Posting-Host: 174.62.68.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299790866 17577 127.0.0.1 (10 Mar 2011 21:01:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 21:01:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000prd.googlegroups.com; posting-host=174.62.68.188; posting-account=Ws3AqAoAAADYV_032p3vSJ-quHkhuKM0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4839 On Mar 10, 7:20=A0am, Benjamin Couillard wrote: > On 10 mar, 10:17, Tricky wrote: > > > > > > > > > > > On Mar 10, 2:51=A0pm, Benjamin Couillard > > wrote: > > > > Hi everyone, > > > > I was wondering if I can do the following in VHDL : > > > > my_process : process(CLK) > > > begin > > > =A0 =A0if rising_edge(CLK) then > > > =A0 =A0 =A0if (load_reg =3D '1') then > > > =A0 =A0 =A0 =A0 =A0 =A0 assert unsigned(DATA) > 10 > > > =A0 =A0 =A0 =A0 =A0 =A0 report "error, DATA must be greater than 10" > > > =A0 =A0 =A0 =A0 =A0 =A0 severity error; > > > =A0 =A0 =A0end if; > > > =A0 =A0end if; > > > end process; > > > > I've tried the following code in Active-HDL, and no assertions were > > > triggered in simulation even though there should have. Is it supposed > > > to trigger? Is there another way to write that assertion? > > > > Best regards > > > Theres nothing wrong with the code. I can only assume that DATA is > > greater than 10 whenever the process triggers. Or load_reg =3D '0'. > > Ok, I found out what the problem was. I was using variables instead of > signals in the assert statement (I simplified my statement a bit to > make it easier to understand) and I didn't realize that it would solve > the problem. I thought variables can only be declared in processes and thus their scope only extends to the process they're declared in? So then by your example my_process should not have been able to see DATA or load_reg, whichever was declared as a variable. Could you post the non-simplified code? I'm curious. From newsfish@newsfish Fri Feb 3 13:11:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z27g2000prz.googlegroups.com!not-for-mail From: Don Otknow Newsgroups: comp.lang.vhdl Subject: Weird XST error initializing record type on reset Date: Thu, 10 Mar 2011 15:41:36 -0800 (PST) Organization: http://groups.google.com Lines: 57 Message-ID: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> NNTP-Posting-Host: 174.62.68.188 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299800497 32387 127.0.0.1 (10 Mar 2011 23:41:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 10 Mar 2011 23:41:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z27g2000prz.googlegroups.com; posting-host=174.62.68.188; posting-account=Ws3AqAoAAADYV_032p3vSJ-quHkhuKM0 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.224 Safari/534.10,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4840 Hello, I just had an odd error with XST. I have a record and code to initialize it in a process: architecture behavioral of vectors is type six_vectors is record vect_a : std_logic_vector(15 DOWNTO 0); vect_b : std_logic_vector(15 DOWNTO 0); vect_c : std_logic_vector(15 DOWNTO 0); vect_d : std_logic_vector(15 DOWNTO 0); vect_e : std_logic_vector(15 DOWNTO 0); vect_f : std_logic_vector(15 DOWNTO 0); end record; signal six_vect_inst : six_vectors; begin some_process : process(rst,clk) begin if rst = '1' then six_vect_inst <= (others => (others => '0')); elsif clk'event and clk='1' then do_some_stuff end if; end process; end behavioral; This doesn't work. XST gives me: FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64.18.3.18.1 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 2582 Process will terminate. I read in a related error report on a Xilinx site that user-defined types would cause ISE 12.1 to throw these types of errors. So I changed the code to: some_process : process(rst,clk) begin if rst = '1' then six_vect_inst.vect_a <= (others => '0'); six_vect_inst.vect_b <= (others => '0'); six_vect_inst.vect_c <= (others => '0'); six_vect_inst.vect_d <= (others => '0'); six_vect_inst.vect_e <= (others => '0'); six_vect_inst.vect_f <= (others => '0'); elsif clk'event and clk='1' then do_some_stuff end if; end process; and it worked fine. Does anyone have any insight into why these cases are handled so differently? From newsfish@newsfish Fri Feb 3 13:11:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Weird XST error initializing record type on reset Date: Fri, 11 Mar 2011 06:34:34 +0100 Lines: 25 Message-ID: <8ttqjbFtanU1@mid.uni-berlin.de> References: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de BrrAQqB5yvDbDVCb9tDgMQn+6QSdjvEw67yMT4lqItEKMmLqk= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 In-Reply-To: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4841 Am 11.03.11 00:41, schrieb Don Otknow: > and it worked fine. Does anyone have any insight into why these cases > are handled so differently? I think the "(others => (others =>" works only for arrays like: type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0); For records I define an default constant beside: constant default_six_vectors: six_vectors := ( vect_a => (others => '0'), vect_b => (others => '0'), vect_c => (others => '0'), vect_d => (others => '0'), vect_e => (others => '0'), vect_f => (others => '0') ); You can use this default constant in your reset path. And you can easily mix diffrent data types in your record. Also you can never forget to reset an value in this record if you use the constant. The compiler will complain if the default constant is not complete. regards Bart From newsfish@newsfish Fri Feb 3 13:11:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p3g2000vbv.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Assignment of records Date: Thu, 10 Mar 2011 23:59:49 -0800 (PST) Organization: http://groups.google.com Lines: 43 Message-ID: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299830389 23602 127.0.0.1 (11 Mar 2011 07:59:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Mar 2011 07:59:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p3g2000vbv.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4842 Hi, I have the following record assignments which do not behave correctly in simulation (getting undefined record elements): type tr is record a: std_logic; b: std_logic; c: std_logic; end record; signal rec : tr; signal sig_a, sig_b, sig_c : std_logic; BR: block begin rec.a <= sig_a; rec.b <= sig_b; rec.c <= sig_c; end block; The solution seems to be the usage of a process: pBR: process(sig_a, sig_b, sig_c) begin rec.a <= sig_a; rec.b <= sig_b; rec.c <= sig_c; end process; Why is the first approach erroneous for simulation ? Does VHDL-2008 allow the correct use of record assignments in blocks ? When using big records the handling of the process sensitivity list becomes unclear. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:11:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!t8g2000vbd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: assert question Date: Fri, 11 Mar 2011 03:52:51 -0800 (PST) Organization: http://groups.google.com Lines: 54 Message-ID: References: <311dc0f0-ef3d-465b-89f7-cdd8dafb4aaa@k15g2000prk.googlegroups.com> <82430b6f-11cc-4376-833f-8d5153990590@r17g2000vbc.googlegroups.com> <6e1583b3-9969-492d-a65f-cdeb5d5bfb77@x8g2000prh.googlegroups.com> NNTP-Posting-Host: 194.202.236.116 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299844371 23039 127.0.0.1 (11 Mar 2011 11:52:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Mar 2011 11:52:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000vbd.googlegroups.com; posting-host=194.202.236.116; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4843 On Mar 10, 9:01=A0pm, Don Otknow wrote: > On Mar 10, 7:20=A0am, Benjamin Couillard > wrote: > > > > > On 10 mar, 10:17, Tricky wrote: > > > > On Mar 10, 2:51=A0pm, Benjamin Couillard > > > wrote: > > > > > Hi everyone, > > > > > I was wondering if I can do the following in VHDL : > > > > > my_process : process(CLK) > > > > begin > > > > =A0 =A0if rising_edge(CLK) then > > > > =A0 =A0 =A0if (load_reg =3D '1') then > > > > =A0 =A0 =A0 =A0 =A0 =A0 assert unsigned(DATA) > 10 > > > > =A0 =A0 =A0 =A0 =A0 =A0 report "error, DATA must be greater than 10= " > > > > =A0 =A0 =A0 =A0 =A0 =A0 severity error; > > > > =A0 =A0 =A0end if; > > > > =A0 =A0end if; > > > > end process; > > > > > I've tried the following code in Active-HDL, and no assertions were > > > > triggered in simulation even though there should have. Is it suppos= ed > > > > to trigger? Is there another way to write that assertion? > > > > > Best regards > > > > Theres nothing wrong with the code. I can only assume that DATA is > > > greater than 10 whenever the process triggers. Or load_reg =3D '0'. > > > Ok, I found out what the problem was. I was using variables instead of > > signals in the assert statement (I simplified my statement a bit to > > make it easier to understand) and I didn't realize that it would solve > > the problem. > > I thought variables can only be declared in processes and thus their > scope > only extends to the process they're declared in? So then by your > example > my_process should not have been able to see DATA or load_reg, > whichever was > declared as a variable. Could you post the non-simplified code? I'm > curious. shared variabled can be placed inside architectures and read by all processes. From newsfish@newsfish Fri Feb 3 13:11:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!fu19g2000vbb.googlegroups.com!not-for-mail From: geobsd Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Fri, 11 Mar 2011 03:58:13 -0800 (PST) Organization: http://groups.google.com Lines: 2 Message-ID: References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> NNTP-Posting-Host: 82.255.19.63 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299844694 26002 127.0.0.1 (11 Mar 2011 11:58:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Mar 2011 11:58:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fu19g2000vbb.googlegroups.com; posting-host=82.255.19.63; posting-account=Bi3m9AoAAAB_ife_Yz5LxcyS_WqXyqav User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.9.1.12) Gecko/20100911 Firefox/3.5.12,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4844 comp.arch.fpga:14820 comp.lang.verilog:2853 why do you complain about you restricted softwares while the hardwer is much more closed ? From newsfish@newsfish Fri Feb 3 13:11:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Fri, 11 Mar 2011 18:29:37 +0100 Lines: 16 Message-ID: <8tv4g0FgdbU1@mid.uni-berlin.de> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de zzwlz8biOen21tpOIQr9vwAcshj3RztkcJ2sZ1Ndhu0JKHefA= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 In-Reply-To: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4845 Am 11.03.11 08:59, schrieb hssig: > rec.a<= sig_a; > rec.b<= sig_b; > rec.c<= sig_c; ... > > Why is the first approach erroneous for simulation ? Put the tree assignments in a single assignment: rec <= (a => sig_a, b => sig_b, c => sig_c); I use records only in synchronous processes, so there is only the clock in the sensitivity list. Bart From newsfish@newsfish Fri Feb 3 13:11:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Marc Guardiani Newsgroups: comp.lang.vhdl Subject: Re: Weird XST error initializing record type on reset Date: Fri, 11 Mar 2011 11:27:04 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 72.37.171.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1299871625 14777 127.0.0.1 (11 Mar 2011 19:27:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 11 Mar 2011 19:27:05 +0000 (UTC) In-Reply-To: <8ttqjbFtanU1@mid.uni-berlin.de> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.37.171.140; posting-account=tm0w8woAAADeGQypQ3zH5sMmYM3ldVzT User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4846 On Friday, March 11, 2011 12:34:34 AM UTC-5, Bart Fox wrote: > Am 11.03.11 00:41, schrieb Don Otknow: > > and it worked fine. Does anyone have any insight into why these cases > > are handled so differently? > I think the "(others => (others =>" works only for arrays like: > type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0); > > For records I define an default constant beside: > > constant default_six_vectors: six_vectors := ( > vect_a => (others => '0'), > vect_b => (others => '0'), > vect_c => (others => '0'), > vect_d => (others => '0'), > vect_e => (others => '0'), > vect_f => (others => '0') > ); > > You can use this default constant in your reset path. > And you can easily mix diffrent data types in your record. > Also you can never forget to reset an value in this record if you use > the constant. The compiler will complain if the default constant is not > complete. > > regards > Bart But regardless of how one might butcher the syntax, the compiler should never crash as it did for the OP. -- Marc From newsfish@newsfish Fri Feb 3 13:11:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 11 Mar 2011 17:47:25 -0600 Date: Fri, 11 Mar 2011 23:47:25 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.13) Gecko/20101209 Fedora/3.1.7-0.35.b3pre.fc13 Thunderbird/3.1.7 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Weird XST error initializing record type on reset References: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> <8ttqjbFtanU1@mid.uni-berlin.de> In-Reply-To: <8ttqjbFtanU1@mid.uni-berlin.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 30 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-QJN/MOi0Ae2QDEZtrqvewPwOywB6uiFlewCjulJQ05qrlDppiDvAT8F7dKKxNLqKSjZLAI5e3/tfURA!z0/AG8jhHVemipJrLTS0cJ1OXkiLjhDSbyx8HXF60KxI3KV17XuXRh0f9bW0urG/GURgyHgrSSQq!a2Vm9BFZLHGbjR0ijbLjsABPlA== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2198 Xref: feeder.eternal-september.org comp.lang.vhdl:4847 On 11/03/11 05:34, Bart Fox wrote: > Am 11.03.11 00:41, schrieb Don Otknow: >> and it worked fine. Does anyone have any insight into why these cases >> are handled so differently? > I think the "(others => (others =>" works only for arrays like: > type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0); > Perhaps surprisingly, others is allowed for records: here's a quote from the 2002 LRM "If the type of an aggregate is a record type, the element names given as choices must denote elements of that record type. If the choice others is given as a choice of a record aggregate, it must represent at least one element. An element association with more than one choice, or with the choice others, is only allowed if the elements specified are all of the same type. The expression of an element association must have the type of the associated record elements." regards Alan > > regards > Bart -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:11:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!feeder.news-service.com!postnews.google.com!a11g2000pri.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Sat, 12 Mar 2011 05:32:06 -0800 (PST) Organization: http://groups.google.com Lines: 55 Message-ID: <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1299936727 32393 127.0.0.1 (12 Mar 2011 13:32:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 12 Mar 2011 13:32:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a11g2000pri.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4848 On Mar 11, 2:59=A0am, hssig wrote: > Hi, > > I have the following record assignments which do not behave correctly > in simulation (getting undefined record elements): > "getting undefined record elements" is not terribly descriptive of whatever problem you think there might be. > type tr is record > =A0 =A0 a: std_logic; > =A0 =A0 b: std_logic; > =A0 =A0 c: std_logic; > end record; > > signal rec : tr; > signal sig_a, sig_b, sig_c : std_logic; > > BR: block > begin > =A0 =A0 =A0 rec.a <=3D sig_a; > =A0 =A0 =A0 rec.b <=3D sig_b; > =A0 =A0 =A0 rec.c <=3D sig_c; > end block; > > The solution seems to be the usage of a process: > > pBR: process(sig_a, sig_b, sig_c) > begin > =A0 =A0 =A0rec.a <=3D sig_a; > =A0 =A0 =A0rec.b <=3D sig_b; > =A0 =A0 =A0rec.c <=3D sig_c; > end process; > > Why is the first approach erroneous for simulation ? It's not erroneous for simulation. Either approach is correct. > Does VHDL-2008 > allow the correct use of record assignments in blocks ? Yes...as does VHDL-2002, -93 and -87...it's always been there. > When using big records the handling of the process sensitivity list > becomes > unclear. > Why is it unclear? You still have to add any signal to the sensitivity list that is on the right hand side of an assignment, any signal that is used to determine some conditional assignment, no different than if you had a 'small' record. KJ From newsfish@newsfish Fri Feb 3 13:11:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k38g2000vbn.googlegroups.com!not-for-mail From: marian Newsgroups: comp.lang.vhdl Subject: my dream for S60 Date: Sat, 12 Mar 2011 23:47:00 -0800 (PST) Organization: http://groups.google.com Lines: 10 Message-ID: <559bf9ff-f4aa-4dc8-93ef-bd522167ebeb@k38g2000vbn.googlegroups.com> NNTP-Posting-Host: 213.233.67.172 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300002421 24958 127.0.0.1 (13 Mar 2011 07:47:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 13 Mar 2011 07:47:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k38g2000vbn.googlegroups.com; posting-host=213.233.67.172; posting-account=l70P4woAAAA64RUnlUnoQEa9NIOD8-5p User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; Trident/4.0; GTB6.3; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4849 Hello! Convincing a Volvo driver (in my case, a girl) for having a test-drive I was accepted into the present Volvo campaign (Romania). Winner will be the one with highest unique views for his link. My link is this: http://www.unlimitednaughty.ro/camera/video/concurent/Marian-Briceag (for English turn on the captions, the cc, under arrow from the right- bottom side of video). This battle for views ends in 16 march 2011. I feel in my heart that Volvo has designed this car for me. From Volvo emblem to every stitch, I found myself. Nobody seems to listen my message. Sir/ madame, my dream is in your hands. If you just post/ share it... Have a nice day! From newsfish@newsfish Fri Feb 3 13:11:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp.cybernetik.net!usenet-01.nntp.cybernetik.net!news.glorb.com!postnews.google.com!j13g2000pro.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Sun, 13 Mar 2011 12:43:19 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <4ddb0365-9193-42bd-b0ef-c4e480bbf05f@j13g2000pro.googlegroups.com> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> NNTP-Posting-Host: 77.9.74.206 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300045399 1003 127.0.0.1 (13 Mar 2011 19:43:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 13 Mar 2011 19:43:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000pro.googlegroups.com; posting-host=77.9.74.206; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4850 So is there a difference when making the assignment like in BR1 or like in BR ? From newsfish@newsfish Fri Feb 3 13:11:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!weretis.net!feeder5.news.weretis.net!feeder.news-service.com!postnews.google.com!o30g2000pra.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Sun, 13 Mar 2011 12:41:10 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> NNTP-Posting-Host: 77.9.74.206 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300045271 32524 127.0.0.1 (13 Mar 2011 19:41:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 13 Mar 2011 19:41:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o30g2000pra.googlegroups.com; posting-host=77.9.74.206; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4851 KJ wrote: > "getting undefined record elements" is not terribly descriptive of > whatever problem you think there might be. After starting the simulation record element "a" does not show the contents of "sig_a" but 'U'. Exactly the same behavior on the other record elements when using a block for assignments. > rec <= (a => sig_a, b => sig_b, c => sig_c); So is there a difference when making the assignment like that BR1: block begin rec <= (a => sig_a, b => sig_b, c => sig_c); end block; or like that BR: block begin rec.a <= sig_a; rec.b <= sig_b; rec.c <= sig_c; end block; Cheers, hssig From newsfish@newsfish Fri Feb 3 13:11:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p16g2000vbo.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Sun, 13 Mar 2011 17:42:37 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <6c1fe0bf-95e5-45f0-a04f-553528376c15@p16g2000vbo.googlegroups.com> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300063357 28965 127.0.0.1 (14 Mar 2011 00:42:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 14 Mar 2011 00:42:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p16g2000vbo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4852 On Mar 13, 3:41=A0pm, hssig wrote: > KJ wrote: > > "getting undefined record elements" is not terribly descriptive of > > whatever problem you think there might be. > > After starting the simulation record element "a" does not show the > contents of "sig_a" but 'U'. Exactly the same behavior on the other > record elements when using a block for assignments. > Since rec.a, rec.b and rec.c are all defined as std_logic type, and std_logic is an enumerated type whose leftmost element is 'U', that is exactly the correct behavior. > > rec <=3D (a =3D> sig_a, b =3D> sig_b, c =3D> sig_c); > > So is there a difference when making the assignment like that > > BR1: block > begin > =A0 =A0 rec <=3D (a =3D> sig_a, b =3D> sig_b, c =3D> sig_c); > end block; > > or like that > > BR: block > begin > =A0 =A0 =A0 rec.a <=3D sig_a; > =A0 =A0 =A0 rec.b <=3D sig_b; > =A0 =A0 =A0 rec.c <=3D sig_c; > end block; > No difference except for the extra typing. It also doesn't matter if the code was not in a block statement either. architecture foo of bar is begin rec <=3D (a =3D> sig_a, b =3D> sig_b, c =3D> sig_c); -- rec.a <=3D sig_a; -- rec.b <=3D sig_b; -- rec.c <=3D sig_c; end foo; KJ From newsfish@newsfish Fri Feb 3 13:11:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s18g2000prg.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Mon, 14 Mar 2011 15:04:02 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> <4ddb0365-9193-42bd-b0ef-c4e480bbf05f@j13g2000pro.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300140242 436 127.0.0.1 (14 Mar 2011 22:04:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 14 Mar 2011 22:04:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s18g2000prg.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4853 On Mar 13, 2:43=A0pm, hssig wrote: > So is there a difference when making the assignment like in BR1 or > like in BR ? Three concurrent assignments create three implied processes. Each process creates a driver for the entire aggregate. Unspecified elements in each implied process create drivers with value 'U'. When the driven values are resolved, the 'U' values from the other two processes override the value from the process that explicitly drives a non-U value. When you group these into a single process, one driver gets created from that process for the entire aggregate. There are no unspecified elements, and no drivers created for them, so it works as you expected. IIRC, an aggregate has only one event, so anytime any element of the aggregate has an event, the entire aggregate gets it, which in turn means all the other elements get the event. Andy From newsfish@newsfish Fri Feb 3 13:11:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a26g2000vbo.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Mon, 14 Mar 2011 18:22:29 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <04a253cc-92a5-4cd2-bafe-7a6aeed76f34@a26g2000vbo.googlegroups.com> References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> <4ddb0365-9193-42bd-b0ef-c4e480bbf05f@j13g2000pro.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300152149 18311 127.0.0.1 (15 Mar 2011 01:22:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Mar 2011 01:22:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a26g2000vbo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4854 On Mar 14, 6:04=A0pm, Andy wrote: > On Mar 13, 2:43=A0pm, hssig wrote: > > > So is there a difference when making the assignment like in BR1 or > > like in BR ? > > Three concurrent assignments create three implied processes. Each > process creates a driver for the entire aggregate. Not in the OP's case. The three separate concurrent assignments drive only the specified element of the record. > Unspecified > elements in each implied process create drivers with value 'U'. When > the driven values are resolved, the 'U' values from the other two > processes override the value from the process that explicitly drives a > non-U value. > This is not true...at least not for the case presented in this thread which is individual assignments of record elements. > When you group these into a single process, one driver gets created > from that process for the entire aggregate. There are no unspecified > elements, and no drivers created for them, so it works as you > expected. > The OP's code does not create multiple drivers for the record type signal 'rec'. The concurrent assignment approach and the process approach are for all practical purposes equivalent. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:11:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d26g2000prn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Assignment of records Date: Tue, 15 Mar 2011 09:28:05 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <0df66def-c50c-4800-bae2-e693e1653499@p3g2000vbv.googlegroups.com> <92e6dbb2-7f7d-4be2-8737-05a7114408c8@a11g2000pri.googlegroups.com> <2ddd3c2a-75d3-432a-82b5-a60ceb569ffe@o30g2000pra.googlegroups.com> <4ddb0365-9193-42bd-b0ef-c4e480bbf05f@j13g2000pro.googlegroups.com> <04a253cc-92a5-4cd2-bafe-7a6aeed76f34@a26g2000vbo.googlegroups.com> NNTP-Posting-Host: 192.91.172.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300206566 26163 127.0.0.1 (15 Mar 2011 16:29:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Mar 2011 16:29:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d26g2000prn.googlegroups.com; posting-host=192.91.172.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4855 Oops, I believe you may be right. Is this because the sub-elements are statically identified? Andy From newsfish@newsfish Fri Feb 3 13:11:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.netcologne.de!newsfeed-fusi2.netcologne.de!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Weird XST error initializing record type on reset Date: Wed, 16 Mar 2011 06:43:37 +0100 Lines: 13 Message-ID: <8ub108F734U1@mid.uni-berlin.de> References: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> <8ttqjbFtanU1@mid.uni-berlin.de> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de zSLWCzPnoJ3QhCQriVik2QJlgNsAiS3Bz8GfYjMdPAot74RpA= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4856 Am 12.03.11 00:47, schrieb Alan Fitch: > On 11/03/11 05:34, Bart Fox wrote: >> Am 11.03.11 00:41, schrieb Don Otknow: >>> and it worked fine. Does anyone have any insight into why these cases >>> are handled so differently? >> I think the "(others => (others =>" works only for arrays like: >> type six_vectors is array(0 to 5) of : std_logic_vector(15 DOWNTO 0); > Perhaps surprisingly, others is allowed for records: here's a quote from Thanks for pointing that out. This seems to be another one on my list: What XST should do, but it fails. regards Bart From newsfish@newsfish Fri Feb 3 13:11:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Weird XST error initializing record type on reset Date: Fri, 18 Mar 2011 18:47:00 +0100 Lines: 12 Message-ID: <8uhk4kF7rvU1@mid.uni-berlin.de> References: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de cHfuex+jxb/zTNjiBl2LQQA8LgI8ed0pkelDJ6kp9eX6tElKc= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 In-Reply-To: <8a06e152-d8b6-46cb-8693-6096ad393229@z27g2000prz.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4857 Am 11.03.11 00:41, schrieb Don Otknow: > This doesn't work. XST gives me: > > FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64.18.3.18.1 - Internal > Compiler Error in file ../src/VhdlExpr.cpp at line 2582 Process will > terminate. Ok, I have checked this case: Modelsim (6.5) do it right, XST (12.2) do it right, the problem is only ISIM, the simulator.... regards, Bart From newsfish@newsfish Fri Feb 3 13:11:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!i9g2000vby.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: CFP with extended deadline of Mar. 31, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Sun, 20 Mar 2011 03:14:04 -0700 (PDT) Organization: http://groups.google.com Lines: 275 Message-ID: <86d38e7f-21c7-40d4-99a5-6818728a4c84@i9g2000vby.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300616047 10601 127.0.0.1 (20 Mar 2011 10:14:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Mar 2011 10:14:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i9g2000vby.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; FDM; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:162768 sci.electronics.cad:7840 sci.electronics.misc:3705 sci.engr.semiconductors:764 comp.lang.vhdl:4858 Dear Colleagues: Please share the announcement below with those who may be interested. Thank you, Organizing Committee ------------ CALL FOR PAPERS =========================================== Paper Submission Deadline: March 31, 2011 MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods July 18-21, 2011, Las Vegas, USA http://www.world-academy-of-science.org/ ================================================== You are invited to submit a full paper for consideration. All accepted papers will be published in the respective conference proceedings. The proceedings will be indexed in Inspec / IET / The Institute for Engineering & Technology, DBLP / Computer Science Bibliography, and others.) In the past, all tracks of this federated conference have also been included in EI Compendex/Elsevier. Like prior years, extended versions of selected papers will appear in journals and edited research books (a large number of book projects and journal special issues are in the pipeline: Springer, Elsevier, BMC journals, ...) The main keynote lecture will be presented by Prof. David Lorge Parnas (Fellow of IEEE, ACM, RSC, CAE, GI; MRIA); there will also be 8 other distinguished invited speakers and 12 planned tutorials and panel discussions as well as 75 research paper presentations. SCOPE: Topics of interest include, but are not limited to: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: The DBLP list of accepted papers of MSV 2010 appears at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html The main web site of MSV'11 can be accessed via: http://www.world-academy-of-science.org/ IMPORTANT DATES: March 31, 2011: Submission of papers (about 5 to 7 pages) April 20, 2011: Notification of acceptance (+/- 6 days) May 7, 2011: Final papers + Copyright/Consent + Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) Those who have submitted papers during the month of February will receive the decision on their papers by the end of March 2011. ACADEMIC CO-SPONSORS: Currently being prepared - The Academic sponsors of the last offering of MSV (2010) included research labs and centers affiliated with (a partial list): University of California, Berkeley; University of Southern California; University of Texas at Austin; Harvard University, Cambridge, Massachusetts; Georgia Institute of Technology, Georgia; Emory University, Georgia; University of Minnesota; University of Iowa; University of North Dakota; NDSU-CIIT Green Computing & Comm. Lab.; University of Siegen, Germany; UMIT, Austria; SECLAB (University of Naples Federico II + University of Naples Parthenope + Second University of Naples, Italy); National Institute for Health Research; World Academy of Biomedical Sciences and Technologies; Russian Academy of Sciences, Russia; International Society of Intelligent Biological Medicine (ISIBM); The International Council on Medical and Care Compunetics; Eastern Virginia Medical School & the American College of Surgeons, USA. SUBMISSION OF PAPERS: Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by March 31, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) that the paper is being submitted for consideration must be stated on the first page. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject) - often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/philosophical papers will not be refereed but may be considered for discussion/panels). All proceedings of WORLDCOMP will be published and indexed in: Inspec / IET / The Institute for Engineering & Technology, DBLP / CS Bibliography, and others. The printed proceedings will be available for distribution on site at the conference. In the past, all tracks of the federated congress have also been included in EI Compendex/Elsevier. MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES: The members of the Steering Committee of The 2010 congress included: Dr. Selim Aissi (Chief Strategist, Intel Corporation, USA); Prof. Hamid Arabnia (ISIBM Fellow & Professor, University of Georgia; Associate Editor, IEEE Transactions on Information Technology in Biomedicine; Editor-in-Chief, Journal of Supercomputing, Springer; Advisory Board, IEEE TC on Scalable Computing); Prof. Ruzena Bajcsy (Member, National Academy of Engineering, IEEE Fellow, ACM Fellow, Professor; University of California, Berkeley, USA); Prof. Hyunseung Choo (ITRC Director of Ministry of Information & Communication; Director, ITRC; Director, Korea Information Processing Society; Assoc. Editor, ACM Transactions on Internet Technology; Professor, Sungkyunkwan University, Korea); Prof. Winston Wai-Chi Fang (IEEE Fellow, TSMC Distinguished Chair Professor, National ChiaoTung University, Hsinchu, Taiwan, ROC); Prof. Andy Marsh (Director HoIP, Secretary-General WABT; Vice-president ICET and ICMCC, Visiting Professor, University of Westminster, UK); Dr. Rahman Tashakkori (Director, S-STEM NSF Supported Scholarship Program and NSF Supported AUAS, Appalachian State U., USA); Prof. Layne T. Watson (IEEE Fellow, NIA Fellow, ISIBM Fellow, Fellow of The National Institute of Aerospace, Virginia Polytechnic Institute & State University, USA); and Prof. Lotfi A. Zadeh (Member, National Academy of Engineering; IEEE Fellow, ACM Fellow, AAAS Fellow, AAAI Fellow, IFSA Fellow; Director, BISC; Professor, University of California, Berkeley, USA). The list of Program Committee of MSV 2010 appears at: http://www.world-academy-of-science.org/worldcomp10/ws/conferences/msv10/committee The MSV 2011 program committee is currently being compiled. Many who have already joined the committee are renowned leaders, scholars, researchers, scientists and practitioners of the highest ranks; many are directors of research labs., members of National Academy of Engineering, fellows of various societies, heads/chairs of departments, program directors of research funding agencies, deans and provosts as well as members of chapters of World Academy of Science. 2011 PUBLICITY CHAIR: A. M. G. Solo BCS Fellow (British Computer Society Fellow) Principal/R&D Engineer, Maverick Technologies America Inc. Principal/Intelligent Systems Instructor, Trailblazer Intelligent Systems, Inc. GENERAL INFORMATION: MSV conference is an important track of a federated research conference. It is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,000 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different branches of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub- disciplines. According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" to extract citation data for each individual track of worldcomp using the following link: http://academic.research.microsoft.com/ As of March 4, 2011, the papers published in the proceeedings have received 14,385 citations which is a higher citation than many reputable journals in computer science. From newsfish@newsfish Fri Feb 3 13:11:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v31g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 20 Mar 2011 09:37:52 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300639073 19054 127.0.0.1 (20 Mar 2011 16:37:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Mar 2011 16:37:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v31g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4859 Am I the only user of this group who does not appreciate the endless posting about the multi-conference being held in Las Vegas this summer? They seem to be having a couple of dozen conferences all in the same place on the same day. Sounds a little odd to me. Wouldn't it make more sense to have one conference that covers all the topics? I guess if they did that they couldn't post every other day without it being obvious. Instead the advertise each of the two dozen conferences once a month. BTW, who wants to go to Las Vegas in July??? If they want people to come, why didn't they pick a more seasonable time of year.... oh yeah, it would cost them more! At least the deadline for the call for papers is close at hand. Maybe then the advertising will slack off. Rick From newsfish@newsfish Fri Feb 3 13:11:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 20 Mar 2011 21:34:14 -0500 Lines: 16 Message-ID: <8unrp7Fm7aU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net e3StSbUiVbmuMuhLXQPADA6XdKr2M0qCL7IH5GV1dVuWIpAGQe Cancel-Lock: sha1:MmoWUM38zhH9tssq7tf1EBwtbWc= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.14) Gecko/20110221 Lightning/1.0b2 Thunderbird/3.1.8 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4860 On 3/20/2011 11:37 AM, rickman wrote: > Am I the only user of this group who does not appreciate the endless > posting about the multi-conference being held in Las Vegas this > summer? They seem to be having a couple of dozen conferences all in > the same place on the same day. Sounds a little odd to me. Wouldn't > it make more sense to have one conference that covers all the topics? > I guess if they did that they couldn't post every other day without it > being obvious. Instead the advertise each of the two dozen > conferences once a month. > > Rick You may "kill file" those messages. Check this option with your news reader. If you are using Google Groups there's no hope (I'm sorry). Al From newsfish@newsfish Fri Feb 3 13:11:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 21 Mar 2011 19:02:08 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <927d203a-b6bb-4816-b458-af7498101f32@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.16.209.40 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300759328 12199 127.0.0.1 (22 Mar 2011 02:02:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Mar 2011 02:02:08 +0000 (UTC) Cc: Alessandro Basili In-Reply-To: <8unrp7Fm7aU1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.16.209.40; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4862 On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > On 3/20/2011 11:37 AM, rickman wrote: > > Am I the only user of this group who does not appreciate the endless > > posting about the multi-conference being held in Las Vegas this > > summer? They seem to be having a couple of dozen conferences all in > > the same place on the same day. Sounds a little odd to me. Wouldn't > > it make more sense to have one conference that covers all the topics? > > I guess if they did that they couldn't post every other day without it > > being obvious. Instead the advertise each of the two dozen > > conferences once a month. > > > > Rick > > You may "kill file" those messages. Check this option with your news reader. > If you are using Google Groups there's no hope (I'm sorry). > > Al Actually I'm using Google Groups and those messages are already hidden. I guess I have Rick to thank for that. -- Gabor From newsfish@newsfish Fri Feb 3 13:11:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d19g2000yql.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 21 Mar 2011 22:18:56 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <90ca38d3-17c8-415c-9b89-6fc4b05b6eb5@d19g2000yql.googlegroups.com> References: <927d203a-b6bb-4816-b458-af7498101f32@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300771136 2066 127.0.0.1 (22 Mar 2011 05:18:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 22 Mar 2011 05:18:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d19g2000yql.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.15) Gecko/20110303 Firefox/3.6.15,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4863 On Mar 21, 10:02=A0pm, Gabor Sz wrote: > On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > > On 3/20/2011 11:37 AM, rickman wrote: > > > Am I the only user of this group who does not appreciate the endless > > > posting about the multi-conference being held in Las Vegas this > > > summer? =A0They seem to be having a couple of dozen conferences all i= n > > > the same place on the same day. =A0Sounds a little odd to me. =A0Woul= dn't > > > it make more sense to have one conference that covers all the topics? > > > I guess if they did that they couldn't post every other day without i= t > > > being obvious. =A0Instead the advertise each of the two dozen > > > conferences once a month. > > > > Rick > > > You may "kill file" those messages. Check this option with your news re= ader. > > If you are using Google Groups there's no hope (I'm sorry). > > > Al > > Actually I'm using Google Groups and those messages > are already hidden. =A0I guess I have Rick to thank for > that. > > -- Gabor That's funny, I do flag them as spam, but they never seem to go away. The other spam tends to disappear. Oh, I am still using the older style interface. I tried the new groups interface and there all the spam goes away pretty quickly and anything I flag is gone immediately. I wonder why Google can't clear out the spam effectively from their standard interface while they do with the new interface. Rick From newsfish@newsfish Fri Feb 3 13:11:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!hq-usenetpeers.eweka.nl!81.171.88.15.MISMATCH!eweka.nl!lightspeed.eweka.nl!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Wed, 23 Mar 2011 12:28:32 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1300908512 15178 127.0.0.1 (23 Mar 2011 19:28:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 23 Mar 2011 19:28:32 +0000 (UTC) Cc: rickman In-Reply-To: <90ca38d3-17c8-415c-9b89-6fc4b05b6eb5@d19g2000yql.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4864 On Tuesday, March 22, 2011 1:18:56 AM UTC-4, rickman wrote: > On Mar 21, 10:02=A0pm, Gabor Sz wrote: > > On Sunday, March 20, 2011 10:34:14 PM UTC-4, Alessandro Basili wrote: > > > On 3/20/2011 11:37 AM, rickman wrote: > > > > Am I the only user of this group who does not appreciate the endles= s > > > > posting about the multi-conference being held in Las Vegas this > > > > summer? =A0They seem to be having a couple of dozen conferences all= in > > > > the same place on the same day. =A0Sounds a little odd to me. =A0Wo= uldn't > > > > it make more sense to have one conference that covers all the topic= s? > > > > I guess if they did that they couldn't post every other day without= it > > > > being obvious. =A0Instead the advertise each of the two dozen > > > > conferences once a month. > > > > > > Rick > > > > > You may "kill file" those messages. Check this option with your news = reader. > > > If you are using Google Groups there's no hope (I'm sorry). > > > > > Al > > > > Actually I'm using Google Groups and those messages > > are already hidden. =A0I guess I have Rick to thank for > > that. > > > > -- Gabor >=20 > That's funny, I do flag them as spam, but they never seem to go away. > The other spam tends to disappear. Oh, I am still using the older > style interface. I tried the new groups interface and there all the > spam goes away pretty quickly and anything I flag is gone > immediately. >=20 > I wonder why Google can't clear out the spam effectively from their > standard interface while they do with the new interface. >=20 > Rick Well they don't really go away. They're just "hidden" in plain sight. Still a bit less annoying that seeing the bold uppercase thread titles... -- Gabor From newsfish@newsfish Fri Feb 3 13:11:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder.news-service.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Wed, 23 Mar 2011 22:30:00 -0500 Lines: 44 Message-ID: <8uvs5nFq7kU1@mid.individual.net> References: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net tbGc6wZ4DEWlKTz9AFYAaQmpxJK6ZJm/l7bR3jvGToj/3DVjIN Cancel-Lock: sha1:OwJQo2pNbewPnjTude3mIH/OUIY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <01090dfd-564b-4929-ad7e-63c7c4da86b5@glegroupsg2000goo.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:4865 On 3/23/2011 2:28 PM, Gabor Sz wrote: > On Tuesday, March 22, 2011 1:18:56 AM UTC-4, rickman wrote: >> On Mar 21, 10:02 pm, Gabor Sz wrote: [snip] >> >> That's funny, I do flag them as spam, but they never seem to go away. >> The other spam tends to disappear. Oh, I am still using the older >> style interface. I tried the new groups interface and there all the >> spam goes away pretty quickly and anything I flag is gone >> immediately. >> >> I wonder why Google can't clear out the spam effectively from their >> standard interface while they do with the new interface. >> >> Rick > > Well they don't really go away. They're just "hidden" > in plain sight. Still a bit less annoying that seeing > the bold uppercase thread titles... > > -- Gabor FYI there is an interesting article with a tentative explanation of why GG does not work so effectively on SPAM: http://ejohn.org/blog/google-groups-is-dead/ I disagree with the claim that GG is dead, but I believe GG hit the usenet community really bad, giving a false impression to newbies about what is a newsgroup at large. You may also read "current usenet spam threshold and guidelines" (), which gives you an idea of how the newsgroup administrators deal with the spam. Given the BI of the post the OP was complaining about, there's no chance any newsgroup, nor GG may flag that post as spam. Nevertheless with your newsreader you may easily "kill file" it. Al p.s.: Gabor if you find the time please read the "Common questions about using newsgroups" (), especially Q6 and the related A6 From newsfish@newsfish Fri Feb 3 13:11:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Thu, 24 Mar 2011 07:25:39 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 70.91.141.242 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1300976739 22006 127.0.0.1 (24 Mar 2011 14:25:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 24 Mar 2011 14:25:39 +0000 (UTC) Cc: Alessandro Basili In-Reply-To: <8uvs5nFq7kU1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=70.91.141.242; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4866 On Wednesday, March 23, 2011 11:30:00 PM UTC-4, Alessandro Basili wrote: [snip] > p.s.: Gabor if you find the time please read the "Common questions about > using newsgroups" (), > especially Q6 and the related A6 I suppose if I used a newsreader instead of Google Groups, then I could find the topic you posted the "link" to. -- Gabor From newsfish@newsfish Fri Feb 3 13:12:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "scrts" Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Sun, 27 Mar 2011 13:47:45 +0300 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Injection-Date: Sun, 27 Mar 2011 10:47:54 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="PCoXu+X2HClsEvAir5PNww"; logging-data="24162"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18IfbQId5oPAvNxX0lsAOnl" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5994 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:6pLzYExBcl2ivYy72+Xkz3AJW3w= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4867 > I suppose if I used a newsreader instead of Google Groups, > then I could find the topic you posted the "link" to. I use Outlook Express to read the news and also Google Groups via news.eternal-september.org. Registration is easy, I see no spam and also threaded messages is a huge advantage instead of web interface. Tomas D. From newsfish@newsfish Fri Feb 3 13:12:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Only 11 More Days Until the Incessant Posting Ends Date: Mon, 28 Mar 2011 15:58:24 -0400 Organization: Alacron, Inc. Lines: 20 Message-ID: References: <5c7c53b4-a3ee-4428-b072-d42c07de6a12@glegroupsg2000goo.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Mar 2011 19:57:50 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="29686"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18jg33wB7y0RqYvX1AxbIMl" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:vQKxyYZtLD21MhssxBn3thfSMiY= Xref: feeder.eternal-september.org comp.lang.vhdl:4868 scrts wrote: >> I suppose if I used a newsreader instead of Google Groups, >> then I could find the topic you posted the "link" to. > > I use Outlook Express to read the news and also Google Groups via > news.eternal-september.org. Registration is easy, I see no spam and also > threaded messages is a huge advantage instead of web interface. > > Tomas D. > > O.K. I'll give "Eternal September" a shot. This is posted via Thunderbird. Still from within TB I can see the links to but clicking on them doesn't do anything. With any luck, though this method doesn't send the reply to each author in addition to the group... Regards, Gabor From newsfish@newsfish Fri Feb 3 13:12:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q12g2000prb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 09:13:18 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301415199 13923 127.0.0.1 (29 Mar 2011 16:13:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 16:13:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q12g2000prb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4869 I was using some logic to shorten typing of some operations where I was trying to create tristate drivers. To be sure of the result I looked up the logic tables and found that, for example the OR function on a constant 'z' and a signal produces a '1' when the signal is a '1', but when the signal is a zero results in an 'x'. This is not the same as a 'z' obviously, which is what I wanted. Clearly this is not a good idea even if it is shorter to type. But I realized, how do I know what will be synthesized by this expression? Then I came to my senses and realized I just needed to use the IF statement and not worry about brevity. Reading the sysnthesis standard 1076.6 it says, 'Three-state logic shall be modeled when an object, or an element of the object, is explicitly assigned the IEEE Std 1164-1993 value =93Z.=94 The assignment to =93Z=94 shall be a conditional assignment; that is, assignment occurs under the control of a condition.' So trying to get a logic function to do the job of a conditional assignment just won't work, eh? Rick From newsfish@newsfish Fri Feb 3 13:12:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feed.cnntp.org!news.cnntp.org!weretis.net!feeder4.news.weretis.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!a21g2000prj.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 09:42:05 -0700 (PDT) Organization: http://groups.google.com Lines: 86 Message-ID: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301416926 32678 127.0.0.1 (29 Mar 2011 16:42:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 16:42:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a21g2000prj.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4870 Hello folks, I'm posting this in hopes that folks have some suggestions on how to handle this in a clean way. I find myself (not surprisingly) writing testbenches for a lot of very similar bus interfaces. At the simplest I've got an address signal, data out, data in, and a write enable signal. On a more complex one I might have the full backend interface to the Actel PCI core or the Altera Avalon interface. Regardless, I would really like to be able to write my basic interaction procedures once and just use them after that. However I'm running into some difficulty with the language and scoping rules. So for talking purposes, here's a little skeleton use work.generic_bus_if_pkg.all; -- entity just_a_testbench is end entity just_a_testbench; architecture behavioral of just_a_testbench is signal be_addr : unsigned(15 downto 0); signal be_rddata : std_logic_vector(31 downto 0); signal be_wrdata : std_logic_vector(31 downto 0); signal be_wren : std_logic; begin DUT : entity work.foo port map ( .... be_addr => be_addr, be_rddata => be_rddata, be_wrdata => be_wrdata, be_wren => be_wren, .... ); BUS_CONTROL : process is begin ..... be_read32(); be_write32(); ..... end process BUS_CONTROL; end architecture behavioral; Alright, I think that's enough to give an idea. So I'd really like my procedure calls to be something I can abstract preferably into a package. Also I'd really like to keep the parameter list as minimal as possible. However I run into scope issues with signals. So if I use region A for declaring my read/write procedures, I can directly access all the signals running into the DUT. I don't have to pass them in. I can simply have an address and data parameters. However this means every testbench has to declare everything right there in the process and that's ugly to me. Now if I use B or C, then I no longer have scope on the signals. If I want to use a procedure for reading and writing, I've got to pass them into the procedure. With the example described, it's not really too big a deal, but consider a PCI interface with all its myriad signals or another example various PCI core backend interfaces with start, stop, rdcyc, wrcyc, and various other signals for backpressure. It seems to me that the parameter list could get unwieldy very quickly. So I can put the procedures here, but that violates my desire to have manageable calls. So, I'm hoping there's some sort of clever way of passing a bus in and out of procedure declarations to keep code readable and maintainable. The only way I've thought that might work is to declare a record that comprises the entire bus interface. Then I could pass in a single token that represents the entire bus. I haven't really worked out how that might work with different naming conventions (I'm usually pretty consistent with signal names, but sometimes there are variations.) There are very likely other ways to do it, but I haven't had a lot of exposure to folks who do large scale testbenches and have already worked out these tricks. So, in summary does anyone have any technique or best practice for how to organize bus interfaces for passing in and out of procedure calls? Thanks for any ideas. I appreciate it. Best regards, Mark Norton From newsfish@newsfish Fri Feb 3 13:12:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 12:24:19 -0700 Lines: 25 Message-ID: <8vepu0FtmdU1@mid.individual.net> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 9JQ4bnYQHgVEuhEOxUJfrg0t++FqLk14ES37c018+Oe23nhxxZ Cancel-Lock: sha1:fas9PZQmC52Vh71QXVFUxFjXK9g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4871 On 3/29/2011 9:42 AM, M. Norton wrote: > So, I'm hoping there's some sort of clever way of passing a bus in and > out of procedure declarations to keep code readable and maintainable. I haven't seen it, if we include the "readable" part. I like to use variables and procedures and minimize processes. Something like: ... constant reps : natural := 8; begin -- process main: Top level loop invokes top procedures. init; for i in 1 to reps loop timed_cycle; end loop; for i in 1 to reps loop handshake_cycle; end loop; coda; end process main; for details, see the testbench here: http://mysite.ncnetwork.net/reszotzl/ -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: Vikram Newsgroups: comp.arch.fpga,comp.lang.verilog,comp.lang.vhdl,comp.dsp,comp.arch.embedded Subject: only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley Date: Tue, 29 Mar 2011 12:42:22 -0700 (PDT) Organization: http://groups.google.com Lines: 47 Message-ID: <67767519-7edb-4527-b11c-91fa658bdeee@17g2000prr.googlegroups.com> NNTP-Posting-Host: 8.4.225.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301427743 17061 127.0.0.1 (29 Mar 2011 19:42:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 19:42:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=8.4.225.30; posting-account=ROblUgoAAABUCieY-adRND7iPJOdhLol User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15063 comp.lang.verilog:2931 comp.lang.vhdl:4872 comp.dsp:29489 comp.arch.embedded:20883 FPGA Camp (http://www.fpgacentral.com/fpgacamp) is a conference, which brings engineers together to discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories. Since its inception in Year 2009, FPGA Camp decided to stay vendor neutral. The attendance is completely FREE and so is putting up a booth. Due to the this approach we soon have been coined as an Open Source conference by Industry leaders like Eric Bogatin, Colin Warwick & Max Maxfield. REGISTER NOW http://bit.ly/fcjHCJ The event will focus on demonstrating key technologies available to bring processor inside the FPGAs. It will provide a glimpse of what to expect in the future, and how to use these great features for your next project. AGENDA (visit http://www.fpgacentral.com/fpgacamp for details) 4:00 PM Exhibit booths 4:25 PM Introductions 4:30 PM Tech Talk 1: On Die Instrumentation 5:05 PM Tech Talk 2: PCIe 3.0 case study 5:40 PM Tech Talk 3: Design Choices for Embedded Real-Time Control Systems 6:15 PM Dinner & Exhibit 6:45 PM Vendor Presentation 7:00 PM Panel: "State Of FPGAs - Current & Future" - Moderated by Dave Orecchio, CEO, Gaterocket 8:15 PM Closing Speakers & Moderator Dave Orecchio - GateRocket Gordon Hands - Lattice Chris Eddington - Synopsys Dave Bursky - Chip Design Magazine and more... Sponsors Lattice Semiconductor Altium Rhino Labs Agilent Technologies IEEE CNSV PLDA REGISTER NOW http://bit.ly/fcjHCJ (registration is FREE & Simple) Organized by: FPGA Cenral ( http://www.fpgacentral.com ) From newsfish@newsfish Fri Feb 3 13:12:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k3g2000prl.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 12:51:19 -0700 (PDT) Organization: http://groups.google.com Lines: 95 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301428279 22108 127.0.0.1 (29 Mar 2011 19:51:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 19:51:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k3g2000prl.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4873 On Mar 29, 11:42=A0am, "M. Norton" wrote: > Hello folks, > > I'm posting this in hopes that folks have some suggestions on how to > handle this in a clean way. =A0I find myself (not surprisingly) writing > testbenches for a lot of very similar bus interfaces. =A0At the simplest > I've got an address signal, data out, data in, and a write enable > signal. =A0On a more complex one I might have the full backend interface > to the Actel PCI core or the Altera Avalon interface. > > Regardless, I would really like to be able to write my basic > interaction procedures once and just use them after that. =A0However I'm > running into some difficulty with the language and scoping rules. =A0So > for talking purposes, here's a little skeleton > > use work.generic_bus_if_pkg.all; -- preferred> > > entity just_a_testbench is > end entity just_a_testbench; > > architecture behavioral of just_a_testbench is > =A0 =A0 =A0 > =A0 =A0 =A0signal be_addr : unsigned(15 downto 0); > =A0 =A0 =A0signal be_rddata : std_logic_vector(31 downto 0); > =A0 =A0 =A0signal be_wrdata : std_logic_vector(31 downto 0); > =A0 =A0 =A0signal be_wren : std_logic; > begin > =A0 =A0 DUT : entity work.foo > =A0 =A0 =A0 =A0 =A0port map ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_addr =3D> be_addr, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_rddata =3D> be_rddata, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_wrdata =3D> be_wrdata, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 be_wren =3D> be_wren, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 .... > =A0 =A0 =A0 =A0 =A0); > > =A0 =A0 =A0BUS_CONTROL : process is > =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 =A0..... > =A0 =A0 =A0 =A0 =A0 =A0be_read32(); > =A0 =A0 =A0 =A0 =A0 =A0be_write32(); > =A0 =A0 =A0 =A0 =A0 =A0..... > =A0 =A0 =A0end process BUS_CONTROL; > > end architecture behavioral; > > Alright, I think that's enough to give an idea. =A0So I'd really like my > procedure calls to be something I can abstract preferably into a > package. =A0Also I'd really like to keep the parameter list as minimal > as possible. =A0However I run into scope issues with signals. =A0So if I > use region A for declaring my read/write procedures, I can directly > access all the signals running into the DUT. =A0I don't have to pass > them in. =A0I can simply have an address and data parameters. =A0However > this means every testbench has to declare everything right there in > the process and that's ugly to me. > > Now if I use B or C, then I no longer have scope on the signals. =A0If I > want to use a procedure for reading and writing, I've got to pass them > into the procedure. =A0With the example described, it's not really too > big a deal, but consider a PCI interface with all its myriad signals > or another example various PCI core backend interfaces with start, > stop, rdcyc, wrcyc, and various other signals for backpressure. =A0It > seems to me that the parameter list could get unwieldy very quickly. > So I can put the procedures here, but that violates my desire to have > manageable calls. > > So, I'm hoping there's some sort of clever way of passing a bus in and > out of procedure declarations to keep code readable and maintainable. > The only way I've thought that might work is to declare a record that > comprises the entire bus interface. =A0Then I could pass in a single > token that represents the entire bus. =A0I haven't really worked out how > that might work with different naming conventions (I'm usually pretty > consistent with signal names, but sometimes there are variations.) > There are very likely other ways to do it, but I haven't had a lot of > exposure to folks who do large scale testbenches and have already > worked out these tricks. > > So, in summary does anyone have any technique or best practice for how > to organize bus interfaces for passing in and out of procedure calls? > > Thanks for any ideas. =A0I appreciate it. > > Best regards, > Mark Norton I've used a single record with an inout port on the procedure(s). All of the elements of the record must be resolved types. I declare an "undriven" constant of that record such that the elements that are never used as outputs by each process are harmlessly driven to 'Z'. Andy From newsfish@newsfish Fri Feb 3 13:12:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!f15g2000pro.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 13:26:55 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> <8vepu0FtmdU1@mid.individual.net> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301430415 18489 127.0.0.1 (29 Mar 2011 20:26:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 20:26:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f15g2000pro.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4874 On Mar 29, 2:24=A0pm, Mike Treseler wrote: > I haven't seen it, if we include the "readable" part. > I like to use variables and procedures and minimize processes. > Something like: ... > for details, see the testbench here:http://mysite.ncnetwork.net/reszotzl/ Yeah, this is essentially what I'm doing right now, one process describing test over time (with loops and whatnot as need requires) and then a lot of local procedures to handle the transactions. The only trouble I've got is that I end up repeating myself quite a lot over a number of testbenches that use identical or more-likely near- identical protocols. All it takes is a few names changed and my cut and paste of previously written transaction procedures gets smoked. I suppose I'm glad to know I'm not too far off in what I've come up with but it'd be nice to find something that's more reusable. Thanks for the information! Mark From newsfish@newsfish Fri Feb 3 13:12:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v11g2000prb.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 13:36:13 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301430973 17243 127.0.0.1 (29 Mar 2011 20:36:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 20:36:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v11g2000prb.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4875 On Mar 29, 2:51=A0pm, Andy wrote: > I've used a single record with an inout port on the procedure(s). All > of the elements of the record must be resolved types. I declare an > "undriven" constant of that record such that the elements that are > never used as outputs by each process are harmlessly driven to 'Z'. I've read and reread this a bit and while I get the theory of what you're doing with the constant, I'm not sure how it's being applied. So if we've got a package with a record containing the signal elements of a bus, including control lines, that would allow harnessing up a generic procedure to a testbench component. However when do you apply the constant that's got things set to high impedance? Does that happen inside the procedure at the beginning of the procedure and then subsequent assignments override it? So, possibly something like this? procedure my_generic_write( ... ; signal my_bus : T_BUS_RECORD; ... ) is begin my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; wait until rising_edge(some_clk); my_bus.address <=3D some_address; my_bus.wr_cyc <=3D '1'; wait until rising_edge(some_clk); my_bus.data <=3D some_data; my_bus.wren <=3D '1'; wait until rising_edge(some_clk); my_bus_wren <=3D '0'; wait until rising_edge(some_clk); my_bus.wr_cyc <=3D '0'; wait until rising_edge(some_clk); my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; end procedure my_generic_write; Then during that procedure call, all the my_bus.rd_cyc, my_bus.rd_stb, etc would remain Z. I will have to try that out and see how it goes. Seems like it might do what I want (assuming I have your intent divined correctly). Thanks for the information! Mark From newsfish@newsfish Fri Feb 3 13:12:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!e21g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 14:00:52 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301432452 8128 127.0.0.1 (29 Mar 2011 21:00:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 21:00:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000yqe.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4876 Using an existing operator may not work, but you could write a function that encapsulates the conditional assignment. For example: ts_out <= bufz(input, enable); You could also overload bufz() for SL and SLV inputs & return values (and SL and SLV [bitwise] enables). Andy From newsfish@newsfish Fri Feb 3 13:12:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 22:08:46 +0100 Organization: A noiseless patient Spider Lines: 228 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="8624"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/A+mmnLZMxVSV7n3d90Eac0U2fyY7A798=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:kZB88h36cMNT2FV42xUedVjA/q0= Xref: feeder.eternal-september.org comp.lang.vhdl:4877 On Tue, 29 Mar 2011 09:42:05 -0700 (PDT), "M. Norton" wrote: >I'm posting this in hopes that folks have some suggestions on how to >handle this in a clean way. I find myself (not surprisingly) writing >testbenches for a lot of very similar bus interfaces.[...] >I would really like to be able to write my basic >interaction procedures once and just use them after that. However I'm >running into some difficulty with the language and scoping rules. Yup. >Alright, I think that's enough to give an idea. So I'd really like my >procedure calls to be something I can abstract preferably into a >package. Also I'd really like to keep the parameter list as minimal >as possible. But, as you've found, a procedure in a package can only hit signals through its arguments (parameters). Which may be numerous, for any reasonably complex model. There are other issues too. Your bus model probably needs to keep track of some persistent state, which you can't comfortably do with a package either. So, here's what I would regard as the preferred way to start. Others will doubtless have different opinions, of course. First off, consider encapsulating your bus model not as a package but as an entity. That way it can have persistent PER-INSTANCE state, i.e. you can use the same model for numerous different buses in the same testbench with no difficulty. And you can provide ports on the entity that will connect to the physical pins of your interface. As a super-simple example we can model an asynchronous serial data (UART) protocol where the DUT is a receiver, and your testbench is the transmitter. So the physical interface is just two wires: TxD from TB to DUT, and CTS (Clear to Send) from DUT to TB. Something like this (yes I know it's no use like this: bear with me as I build up the example.) Lots of details and declarations missing, but I'm sure you can fill it all in yourself. entity UART_TX_incomplete is port ( TXD: out std_logic; -- to DUT CTS: in std_logic ); -- from DUT end; architecture incomplete of UART_TX_incomplete is begin Transmitter: process procedure Tx(bit_to_send: std_logic); begin TXD <= bit_to_send; wait for BIT_TIME; end; procedure Tx(byte_to_send: unsigned(7 downto 0)); begin wait until CTS = '1'; -- handshake Tx('0'); -- start bit for i in byte_to_send'reverse_range loop Tx(byte_to_send(i)); -- LSB first end loop; Tx('1'); -- stop bit end; begin end process; -- eh??? nothing in this process!!! end; OK, this is cool; we just create an instance of this thing, hook its ports to our DUT interface, and, errm, call the procedure... oh dear, we can't because the procedure is hidden away inside a process, inside the instance. So, how do we call that procedure from OUTSIDE the UART_TX entity? Answer: provide a port on said entity that allows your testbench to command it to do things. This port won't connect to DUT wires; it will be hooked to a very abstract signal in the TB, conveying commands. So we can usefully create a record type that represents a command. In our case that's kinda simple (just a byte) but you get the idea. While we're writing a package that defines this record, we can also write a procedure to encapsulate the whole business of getting the UART_TX to do something for us. package UART_TB_CONTROL_pkg is type UART_TB_CONTROL_RECORD is record info: unsigned(7 downto 0); end record; procedure send_message( data_to_send: unsigned(7 downto 0); signal request: out UART_TB_CONTROL_RECORD; signal response: in boolean ); begin -- issue command to UART_TX request.info <= data_to_send; -- wait for response signal to toggle wait on response; end endpackage Now, of course, we must modify our UART_TX so that it can cope with this request/response protocol. That costs a couple more ports, but thanks to the record type, there will ONLY be two such ports no matter how complex the protocol. entity UART_TX is port ( TXD: out std_logic; -- signals to DUT CTS: in std_logic; -- signals from DUT REQ: in UART_TB_CONTROL_RECORD; RSP: out boolean); end; architecture OK of UART_TX is signal response_toggle: boolean; begin Transmitter: process procedure Tx(bit_to_send: std_logic); begin TXD <= bit_to_send; wait for BIT_TIME; end; procedure Tx(byte_to_send: unsigned(7 downto 0)); begin wait until CTS = '1'; -- handshake Tx('0'); -- start bit for i in byte_to_send'reverse_range loop Tx(byte_to_send(i)); -- LSB first end loop; Tx('1'); -- stop bit end; begin -- here's the management process -- Wait for the TB to request a new action wait on REQ'transaction; -- Implement the requested action Tx(REQ.info); -- Indicate completion response_toggle <= not response_toggle; -- then loop back to wait for next command end process; -- Echo out the response indication RSP <= response_toggle; end; Now we're really ready to go. In your TB, create an instance of UART_TX with its TXD and CTS signals connected up to the DUT in the obvious way. Of course, in your real world there will be many more signals than two - but the same principles apply. Then, in the TB, provide signals for the REQ and RSP ports of your UART_TX instance. And then a process in the TB can generate stimulus like this: send_many_characters: process variable L: line; -- to get stimulus data from a file? variable Ch: character; variable V: unsigned(7 downto 0); begin -- Read L from a file using usual textio stuff. -- Or anything else to get some interesting data. -- Then, send the characters stored in L to the UART: for i in L'range loop Ch := L(i); V := to_unsigned(character'pos(Ch), V'length); send_message(V, REQ_signal, RSP_signal); end loop; end process; Now the send_message procedure (defined in the package) has only a small number of arguments, regardless of the complexity of your physical interface - the complexity is abstracted-away in the transaction record type. If you find yourself calling the procedure send_message() many times in the same process, with the same signal arguments every time, you can tidy that up too: process .... -- Simplified local version of the package procedure procedure send_message(V: unsigned(7 downto 0); begin -- Call the package procedure, with appropriate -- signals provided as arguments. These signals -- must be declared in the architecture, of course. send_message(V, REQ_signal, RSP_signal); end; begin -- main body of process -- calls the local procedure, which fills in the signals send_message("00001111"); -- it's that simple send_message("10101010"); ... I'm aware that this example has been quite sketchy, and uses some "advanced" (whatever that means) tricks like 'transaction, but I hope at least it points you in some interesting directions. Many details yet to fill in - initialization, declarations, you name it. Over to you. You can make this work the other way, too, for models that monitor (rather than drive) a DUT interface. Same idea applies: convert the messy signal-wiggles into a transaction record, and work with that in the TB. Capture the signal-to-record converter block as an entity, instantiate it with ports connected to DUT signals and just a couple of ports to expose the collected transaction record. Hook up those latter ports to TB-only signals so that the rest of the TB can see them. There are several interesting variants on this theme: for example, the blocks can be coded as procedures and "instanced" as concurrent procedure calls. That's convenient, but it causes some trouble with the 'transaction trickery, so personally I prefer to use entities. Enjoy, and thanks for asking all the right questions. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!cu4g2000vbb.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 14:42:16 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301434936 24183 127.0.0.1 (29 Mar 2011 21:42:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Mar 2011 21:42:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: cu4g2000vbb.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.204 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4878 On Mar 29, 4:08=A0pm, Jonathan Bromley wrote: > There are other issues too. =A0Your bus model probably > needs to keep track of some persistent state, which > you can't comfortably do with a package either. Glad you mentioned this. I hadn't even gotten to the point where I was concerned about persistent state. My initial examples were pretty straightforward and simple, but I do have in mind trying to create a PCI bus model to try to test this core we seem to be using and reusing and that absolutely would be a far more complex driver and would require persistent state for some transactions. > I'm aware that this example has been quite sketchy, > and uses some "advanced" (whatever that means) > tricks like 'transaction, but I hope at least > it points you in some interesting directions. > Many details yet to fill in - initialization, > declarations, you name it. =A0Over to you. Absolutely, sketchy is fine. I'm looking for theory mainly and this has given me a lot to chew on. In the past I have used entities as DUT drivers, usually for complex packet data, but I hadn't really thought of abstracting it a level further and giving myself command hooks into it. This also neatly dodges the issue of clocks. I was thinking about that when I wrote the little snippet asking about what Andy suggested, and was realizing I would need to pass in the clock as well as everything else, which seems a little on the messy side. Ideally the procedure call would be transaction and message related information only. And having a variety of tools in the toolbox is never a bad thing. Seems to me there's times when Mike's strategy is simplest, and then Andy's and then this feels like the sledgehammer. > Enjoy, and thanks for asking all the right questions. I appreciate it. Best regards, Mark From newsfish@newsfish Fri Feb 3 13:12:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d16g2000yqd.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Tue, 29 Mar 2011 20:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301457352 22420 127.0.0.1 (30 Mar 2011 03:55:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 03:55:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d16g2000yqd.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4879 On Mar 29, 5:00=A0pm, Andy wrote: > Using an existing operator may not work, but you could write a > function that encapsulates the conditional assignment. > > For example: > ts_out <=3D bufz(input, enable); > > You could also overload bufz() for SL and SLV inputs & return values > (and SL and SLV [bitwise] enables). > > Andy I found something that seems odd to me. I often forget details of a language when it is something that I don't use very often. I thought that VHDL did not care about case in all situations. But in the case of std_logic it would seem to care if the values assigned are 'x' or 'X' and 'z' or 'Z'! I was getting errors on assignments and comparisons along with a seemingly unrelated error in a separate file having to do with some intermediate conversion step that didn't involve the source code. When I changed the case to upper for the literals, it all worked again. I guess all these years I haven't made the mistake of using lower case for these values or possibly the other tools I've used don't care about the difference. Rick From newsfish@newsfish Fri Feb 3 13:12:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Tue, 29 Mar 2011 21:45:51 -0700 Lines: 24 Message-ID: <8vfqqrFp4oU1@mid.individual.net> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> <8vepu0FtmdU1@mid.individual.net> <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net fa/uySOQgYqXNGq+MNWi2gg7NLLUqeqTDNqYlg8uWgfwjB5KPu Cancel-Lock: sha1:FOSF/8auqy3HV0oTNY6K/0cTJaI= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <9e56f7c7-02de-45b5-8233-b640dcc12295@f15g2000pro.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4880 On 3/29/2011 1:26 PM, M. Norton wrote: > Yeah, this is essentially what I'm doing right now, one process > describing test over time (with loops and whatnot as need requires) > and then a lot of local procedures to handle the transactions. The > only trouble I've got is that I end up repeating myself quite a lot > over a number of testbenches that use identical or more-likely near- > identical protocols. All it takes is a few names changed and my cut > and paste of previously written transaction procedures gets smoked. I try to do the heavy lifting in functions, which are easily packaged with required and default parameters. I use simple procedures with no parameters when possible for readable code. > I suppose I'm glad to know I'm not too far off in what I've come up > with but it'd be nice to find something that's more reusable. Thanks > for the information! Functions are easily packaged and reused. Procedures can at least eliminate the local cut and paste. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!r13g2000yqk.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 05:43:33 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301489013 15431 127.0.0.1 (30 Mar 2011 12:43:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 12:43:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r13g2000yqk.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 17j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4881 On Mar 30, 4:55=A0am, rickman wrote: > I found something that seems odd to me. =A0I often forget details of a > language when it is something that I don't use very often. =A0I thought > that VHDL did not care about case in all situations. =A0But in the case > of std_logic it would seem to care if the values assigned are 'x' or > 'X' and 'z' or 'Z'! =A0I was getting errors on assignments and > comparisons along with a seemingly unrelated error in a separate file > having to do with some intermediate conversion step that didn't > involve the source code. =A0When I changed the case to upper for the > literals, it all worked again. > > I guess all these years I haven't made the mistake of using lower case > for these values or possibly the other tools I've used don't care > about the difference. heh! VHDL is completely case-insensitive BUT the values 'X', '0' etc for std_logic are in fact CHARACTER LITERALS and therefore they ARE case-sensitive. 'z' is not one of the literals in the std_(u)logic set of 9 values. By contrast, if you have an enumeration type (like for a state machine) then the values of that type are ordinary VHDL identifiers like IDLE_STATE and they are NOT case-sensitive. You can use character literals as the enumeration values in your own enum types if you wish... type foo is ('a', 'b', 'c'); but almost no-one ever does that. And the really funny thing is... Verilog is a case-sensitive language in every respect, EXCEPT that its numeric bit values X and Z (and its radix specifiers 'b, 'h etc) are NOT case sensitive. Exactly the opposite way round from VHDL. Any tool that gets this wrong is non-compliant; it must simply be that you've not made that mistake before. I blame your exposure to Verilog :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!s11g2000yqh.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 05:49:54 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301489395 14173 127.0.0.1 (30 Mar 2011 12:49:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 12:49:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s11g2000yqh.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4882 On 29 Mrz., 18:13, rickman wrote: > I was using some logic to shorten typing of some operations where I > was trying to create tristate drivers. =A0To be sure of the result I > looked up the logic tables and found that, for example the OR function > on a constant 'z' and a signal produces a '1' when the signal is a > '1', but when the signal is a zero results in an 'x'. =A0This is not the > same as a 'z' obviously, which is what I wanted. =A0Clearly this is not > a good idea even if it is shorter to type. So want the technology to contain a buffer that has an high impedance output in case of one input is high impedance? But else the output needs to be low impedance either driving '0' or '1'. Seems quite unusual to be found in any tech library. Your problems seems to me not vhdl related, instead you need to think in dedicated hardware functionality. It is quite easy to construct a logic function in vhdl that helps your need for simulation purpose, but quite a hard job, to build the needed transistor structure to implement the vhdl in real silicon. best regards Thomas From newsfish@newsfish Fri Feb 3 13:12:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a26g2000vbo.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 07:57:11 -0700 (PDT) Organization: http://groups.google.com Lines: 71 Message-ID: <7b29c505-eb6c-486c-87bc-43e5652ac3b6@a26g2000vbo.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <551ae42e-f669-41cd-aef2-8fa60508a8fc@e21g2000yqe.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301497031 638 127.0.0.1 (30 Mar 2011 14:57:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 14:57:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a26g2000vbo.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4883 On Mar 30, 8:43=A0am, Jonathan Bromley wrote: > On Mar 30, 4:55=A0am, rickman wrote: > > > I found something that seems odd to me. =A0I often forget details of a > > language when it is something that I don't use very often. =A0I thought > > that VHDL did not care about case in all situations. =A0But in the case > > of std_logic it would seem to care if the values assigned are 'x' or > > 'X' and 'z' or 'Z'! =A0I was getting errors on assignments and > > comparisons along with a seemingly unrelated error in a separate file > > having to do with some intermediate conversion step that didn't > > involve the source code. =A0When I changed the case to upper for the > > literals, it all worked again. > > > I guess all these years I haven't made the mistake of using lower case > > for these values or possibly the other tools I've used don't care > > about the difference. > > heh! =A0VHDL is completely case-insensitive > BUT the values 'X', '0' etc for std_logic > are in fact CHARACTER LITERALS and therefore > they ARE case-sensitive. =A0'z' is not one of > the literals in the std_(u)logic set of 9 > values. =A0By contrast, if you have an > enumeration type (like for a state machine) > then the values of that type are ordinary > VHDL identifiers like IDLE_STATE and they > are NOT case-sensitive. =A0You can use character > literals as the enumeration values in your > own enum types if you wish... > =A0 =A0type foo is ('a', 'b', 'c'); > but almost no-one ever does that. > > And the really funny thing is... Verilog is a > case-sensitive language in every respect, > EXCEPT that its numeric bit values X and Z > (and its radix specifiers 'b, 'h etc) are > NOT case sensitive. =A0Exactly the opposite > way round from VHDL. > > Any tool that gets this wrong is non-compliant; > it must simply be that you've not made that mistake > before. =A0I blame your exposure to Verilog :-) > -- > Jonathan Bromley Nice try, but my exposure to Verilog is pretty minimal in this context. :^p Actually, if this test bench and test fixture hadn't already been coded in VHDL, I would have likely done it in Verilog as a further part of my exploration into Verilog. I did a small project a month or two ago and was pretty happy with Verilog. Test benches are an area in Verilog I want to explore further. The test bench I did for the project was pretty limited, reading some hex values from a file to drive an SPI port. This test bench is a lot more complicated having to read commands as well as numerical data from a file. It also has a lot more going on requiring synchronization between all the parts. I have a CPU design that I may be returning to later this year. I'm thinking of recoding it to improve efficiency and may swing a Verilog bat at that pitch. Who knows, I may hit a home run! I also want to explore the Silicon Blue devices a bit more and will likely try their parts to test the implementation. I don't recall much about their eval board, but I think they are a bit pricey. I may use one of those super low cost PCB services like DorkbotPDX to create my own board. There is another part from Green Arrays that I might want to explore as well. Rick From newsfish@newsfish Fri Feb 3 13:12:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!feeder.news-service.com!xlned.com!feeder5.xlned.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!r6g2000vbo.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Wed, 30 Mar 2011 08:04:25 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301497466 5614 127.0.0.1 (30 Mar 2011 15:04:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 15:04:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r6g2000vbo.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4884 On Mar 30, 8:49=A0am, Thomas Stanka wrote: > On 29 Mrz., 18:13, rickman wrote: > > > I was using some logic to shorten typing of some operations where I > > was trying to create tristate drivers. =A0To be sure of the result I > > looked up the logic tables and found that, for example the OR function > > on a constant 'z' and a signal produces a '1' when the signal is a > > '1', but when the signal is a zero results in an 'x'. =A0This is not th= e > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is not > > a good idea even if it is shorter to type. > > So want the technology to contain a buffer that has an high impedance > output in case of one input is high impedance? > But else the output needs to be low impedance either driving '0' or > '1'. Seems quite unusual to be found in any tech library. > > Your problems seems to me not vhdl related, instead you need to think > in dedicated hardware functionality. > It is quite easy to construct a logic function in vhdl that helps your > need for simulation purpose, but quite a hard job, to build the needed > transistor structure to implement the vhdl in real silicon. > > best regards Thomas That's funny, I have some parts on a current board design that do pretty much this. They are called switches. One of the inputs will cause a 'Z' on the output when the input is a 'Z'. A little logic added to the control input and it would do exactly what I was coding. Rick From newsfish@newsfish Fri Feb 3 13:12:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.cgarbs.de!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!feeder.news-service.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Wed, 30 Mar 2011 14:20:31 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: <859f951f-4ef0-4a3e-aa6c-86b19acc13e2@d28g2000yqc.googlegroups.com> References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301520031 25843 127.0.0.1 (30 Mar 2011 21:20:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 21:20:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4885 On Mar 29, 12:42=A0pm, "M. Norton" wrote: > > So, in summary does anyone have any technique or best practice for how > to organize bus interfaces for passing in and out of procedure calls? > 1. Similar to what Jonathon suggested, but a bit easier (I think) to draw good boundary lines for the testing entity is to model real parts. FPGAs in real applications do not exist untethered to the rest of the world, they are connected to real parts on a circuit board so your 'FPGA testbench' could (I think 'should') be a model of that PCBA (and surrounding systems)...which means that if you model the parts that go on that PCBA and connect them per the netlist then you're modelling your real system. In your case, you had mentioned in later posts about modelling a PCI bus. I'm guessing that there is a processor on the board, so model that processor and you'll have your PCI bus. Maybe for starters, the PCI bus is about all that you will model, the rest can come later when needed. In any case, by doing this, you'll be refining your cheezy processor model over time and making it closer to the real thing which will make that model better and better over time. What I've also found is that as I model more of the real system, there comes less of a need for that 'magic communications interface' between two parts that Jonathon mentioned in his post. If needed, I simply put that interface into a 'magic comms' package which is project specific (but can be named the same for each project). For the most part, simulations become watching the system perform whatever it is that you set it up to do without too much 'magic' communications between components. 2. Standardize on a comm interface. For the most part, interfaces simply need to read and write. Use Avalon as a guide, at the low level you can write once and use over and over that handshake for any interface. Then the task becomes to create an 'Avalon to PCI' widget (as an example). If that same type of PCI interface is needed in a different application that is a totally different processor, then guess what? You can use that Avalon to PCI widget that you created in your new processor. Both processors could use the same Avalon protocol on the one side with PCI on the other. 3. As has been pointed out and you've discovered, removing the signals from procedures means putting them into a process which can be a pain. However, if you implement #2, then this becomes a straightforward wrapper to portion of your your part model from #1. That description is likely unique to that model so you wouldn't really have a need to 'reuse it' somewhere else other than to plop down your part model from #1. However, there can still be cutting and pasting within that part model. Consider a processor model where you implement the equivalent of several 'threads' that wake up and run at appropriate times. Each thread would be a process, therefore each 'thread' would have to have the shorthand procedures cut and pasted. A pain, but again those procedures are only of use to that part model so you're likely editing a single file. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j13g2000pro.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Wed, 30 Mar 2011 15:10:19 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: References: <0e7c4be1-4bcc-4641-9700-f8a2786b14d9@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301523019 816 127.0.0.1 (30 Mar 2011 22:10:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 30 Mar 2011 22:10:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000pro.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4886 On Mar 29, 3:36=A0pm, "M. Norton" wrote: > On Mar 29, 2:51=A0pm, Andy wrote: > > > I've used a single record with an inout port on the procedure(s). All > > of the elements of the record must be resolved types. I declare an > > "undriven" constant of that record such that the elements that are > > never used as outputs by each process are harmlessly driven to 'Z'. > > I've read and reread this a bit and while I get the theory of what > you're doing with the constant, I'm not sure how it's being applied. > So if we've got a package with a record containing the signal elements > of a bus, including control lines, that would allow harnessing up a > generic procedure to a testbench component. =A0However when do you apply > the constant that's got things set to high impedance? =A0Does that > happen inside the procedure at the beginning of the procedure and then > subsequent assignments override it? > > So, possibly something like this? > > =A0 =A0procedure my_generic_write( ... ; signal my_bus : > T_BUS_RECORD; ... ) is > =A0 =A0begin > =A0 =A0 =A0 =A0 my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.address <=3D some_address; > =A0 =A0 =A0 =A0 my_bus.wr_cyc <=3D '1'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.data <=3D some_data; > =A0 =A0 =A0 =A0 my_bus.wren <=3D '1'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus_wren <=3D '0'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus.wr_cyc <=3D '0'; > =A0 =A0 =A0 =A0 wait until rising_edge(some_clk); > =A0 =A0 =A0 =A0 my_bus <=3D C_HARMLESSLY_DRIVEN_TO_Z; > =A0 =A0end procedure my_generic_write; > > Then during that procedure call, all the my_bus.rd_cyc, my_bus.rd_stb, > etc would remain Z. =A0I will have to try that out and see how it goes. > Seems like it might do what I want (assuming I have your intent > divined correctly). > > Thanks for the information! > Mark Yes, you'd use it like that in the procedure(s), but you also need to make sure that processes in the DUT that interact with the record also drive the constant onto the signal, so that the DUT does not end up driving 'U' on input elements of the record. Andy From newsfish@newsfish Fri Feb 3 13:12:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!x3g2000yqj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Odd Simulator Error Date: Thu, 31 Mar 2011 00:03:39 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301555019 29894 127.0.0.1 (31 Mar 2011 07:03:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 07:03:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x3g2000yqj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4887 I am working on a test bench for a design that is working ok. The code for the design is not changing, just the test bench code. Occasionally when I compile in the Aldec ActiveHDL simulator I get a very odd error that I've never seen before. # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest \compile\muLaw_RTL._x86.bin The file that this occurs on is random. It can happen on multiple files as well. If I recompile it usually goes away although sometimes I have to recompile more than once. I thought maybe it was a memory issue but closing it and restarting doesn't really fix the issue. It just seems to be totally random failing perhaps two times out of five. Any idea what this is about? Rick From newsfish@newsfish Fri Feb 3 13:12:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k22g2000yqh.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Thu, 31 Mar 2011 01:38:55 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <46b1fa34-de95-47e8-9bba-e73d58651a40@k22g2000yqh.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301560735 15580 127.0.0.1 (31 Mar 2011 08:38:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 08:38:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k22g2000yqh.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4888 On 30 Mrz., 17:04, rickman wrote: > On Mar 30, 8:49=A0am, Thomas Stanka > wrote: > > > > > On 29 Mrz., 18:13, rickman wrote: > > > > I was using some logic to shorten typing of some operations where I > > > was trying to create tristate drivers. =A0To be sure of the result I > > > looked up the logic tables and found that, for example the OR functio= n > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > '1', but when the signal is a zero results in an 'x'. =A0This is not = the > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is n= ot > > > a good idea even if it is shorter to type. > > > So want the technology to contain a buffer that has an high impedance > > output in case of one input is high impedance? > > But else the output needs to be low impedance either driving '0' or > > '1'. Seems quite unusual to be found in any tech library. > > > Your problems seems to me not vhdl related, instead you need to think > > in dedicated hardware functionality. > > It is quite easy to construct a logic function in vhdl that helps your > > need for simulation purpose, but quite a hard job, to build the needed > > transistor structure to implement the vhdl in real silicon. > > > best regards Thomas > > That's funny, I have some parts on a current board design that do > pretty much this. =A0They are called switches. =A0One of the inputs will > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > added to the control input and it would do exactly what I was coding. Actually there is a difference between whats possible on a PCB, whats possible with dedicated structures in a device and whats possible using a given cell library. Your synthesis tool is only able to map a logic to the defined logic elements. And in fact the tool tends to be quite stupid when it comes to "unusual" functionality. I guess you will find no tool supporting your code even if it is possible map the functionlity in an ASIC library. For a lot of techologies it is impossible to build your described funtionlity using the given primitives. bye Thomas From newsfish@newsfish Fri Feb 3 13:12:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!f2g2000yqf.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Odd Simulator Error Date: Thu, 31 Mar 2011 02:25:32 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301563532 13705 127.0.0.1 (31 Mar 2011 09:25:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 31 Mar 2011 09:25:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f2g2000yqf.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 20j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4889 On Mar 31, 8:03=A0am, rickman wrote: > # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: > \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile > \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest > \compile\muLaw_RTL._x86.bin > > The file that this occurs on is random. =A0It can happen on multiple > files as well. =A0If I recompile it usually goes away although sometimes > I have to recompile more than once. > > I thought maybe it was a memory issue but closing it and restarting > doesn't really fix the issue. =A0It just seems to be totally random > failing perhaps two times out of five. > > Any idea what this is about? It's pretty clear that this is a tool bug. DAG =3D Directed Acyclic Graph, I would guess - the tree representation of your code that's created internally by the compiler. I cannot imagine why it should come and go on the same set of source code, unless there's some random seeding going on for the internal optimizations. Support case for Aldec, I'm afraid. A tool crash, or a tool failing on some internal operation, is NEVER your fault. If the tool can't report the problem back to something in your source code, it's the tool that's broken. Before anyone takes this the wrong way, let's point out that the name "Aldec" here is a placeholder for "any company whose tool misbehaves in such a way" - it's happened to me with tools from much bigger companies than Aldec :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Odd Simulator Error Date: Thu, 31 Mar 2011 16:58:32 +0000 (UTC) Organization: A noiseless patient Spider Lines: 59 Message-ID: References: <51c53c0a-4dfd-4497-a5a3-3e3bdfaf9e6e@x3g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 31 Mar 2011 16:58:32 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="pg/RQe9DTLnap+ldrpWP+w"; logging-data="24310"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18QjSxImoy2FUCPnqmHP+h/XONc3N40niU=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:Z55otHFiM4EsFNJr2qMj6ZsYr8s= Xref: feeder.eternal-september.org comp.lang.vhdl:4899 On Thu, 31 Mar 2011 02:25:32 -0700, Jonathan Bromley wrote: > On Mar 31, 8:03 am, rickman wrote: > >> # Error: DAGGEN_0007: mulaw.vhd : (0, 0): Error during conversion c: >> \Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest\compile >> \muLaw_RTL.dag to c:\Arius\Boards\IRIG-B-Testbed\FPGA\FullTest\FullTest >> \compile\muLaw_RTL._x86.bin >> >> The file that this occurs on is random.  It can happen on multiple >> files as well.  If I recompile it usually goes away although sometimes >> I have to recompile more than once. >> >> I thought maybe it was a memory issue but closing it and restarting >> doesn't really fix the issue.  It just seems to be totally random >> failing perhaps two times out of five. >> >> Any idea what this is about? > > It's pretty clear that this is a tool bug. DAG = Directed Acyclic > Graph, I would guess - the tree representation of your code that's > created internally by the compiler. > I agree, but even if it's a tool bug ... You can't just stop and wait until the tool supplier fixes it, unfortunately. What to do next? My experience with tool bugs is that often they have remained hidden because you are exercising some corner case ... possibly faulty VHDL that (another) tool bug allowed through the parser. In which case: (a) try building the project in other available systems (pref Modelsim, possibly Xilinx free ISIM or XST from Webpack, etc) and note any warnings or syntax errors. (b) go back to a previous version before the failure started (if there was one), and bisect until you find the suspect file. Not so easy if the failure is intermittent (c) comment out or rewrite to avoid any new VHDL tricks or constructs you are trying for the first time to see if there is a workaround. This way, you can often (a) carry on working in the absence of a fix, (b) localise the error to improve the bug report and (c) submit a tiny test case instead of having to hand over your whole project. If possible, it is better to report "Xilinx ISIM 10.1 exits suddenly with a Segment Violation when you return an access type (e.g. Line = access string) from a function" than "it crashed". Apologies to Rick if this is all old hat to him; however it may be useful to somebody else. - Brian From newsfish@newsfish Fri Feb 3 13:12:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!hg8g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Array pipeline Date: Thu, 31 Mar 2011 23:50:21 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301640622 13966 127.0.0.1 (1 Apr 2011 06:50:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 06:50:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hg8g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4900 Hi, I want to declare an array "vecarr " which consists of std_logic_vector, and a second array "arr3d " to pipeline the first array. When simuating the following test code Modelsim complains: ** Fatal: (vsim-3734) Index value 0 is out of range 4 downto 1. ------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity arr_pipe is end entity; architecture xy of arr_pipe is type t_vecarr is array(natural range <>) of std_logic_vector(7 downto 0); signal vecarr : t_vecarr(15 downto 0) := (others => (others => '1')); type t_arr3d is array(natural range <>) of t_vecarr(15 downto 0); signal arr3d : t_arr3d(4 downto 0); signal clk : std_logic; begin process begin clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end process; process(clk) begin if rising_edge(clk) then for m in 0 to 15 loop arr3d(arr3d'high)(m) <= vecarr(m); arr3d(arr3d'high-1 downto 0)(m) <= arr3d(arr3d'high downto 1)(m); --** ERROR end loop; end if; end process; end xy; ------------------------------------------------------------------------------------------------ Can someone explain to me what is wrong about that shift register ? Cheers, hssig From newsfish@newsfish Fri Feb 3 13:12:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!d2g2000yqn.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Fri, 1 Apr 2011 00:47:07 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <83c3181f-f827-49fc-bc10-03ac0f38b043@d2g2000yqn.googlegroups.com> References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301644028 16531 127.0.0.1 (1 Apr 2011 07:47:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 07:47:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d2g2000yqn.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4901 On 30 Mrz., 17:04, rickman wrote: > On Mar 30, 8:49=A0am, Thomas Stanka > wrote: > > > > > On 29 Mrz., 18:13, rickman wrote: > > > > I was using some logic to shorten typing of some operations where I > > > was trying to create tristate drivers. =A0To be sure of the result I > > > looked up the logic tables and found that, for example the OR functio= n > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > '1', but when the signal is a zero results in an 'x'. =A0This is not = the > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is n= ot > > > a good idea even if it is shorter to type. > > > So want the technology to contain a buffer that has an high impedance > > output in case of one input is high impedance? > > But else the output needs to be low impedance either driving '0' or > > '1'. Seems quite unusual to be found in any tech library. > > > Your problems seems to me not vhdl related, instead you need to think > > in dedicated hardware functionality. > > It is quite easy to construct a logic function in vhdl that helps your > > need for simulation purpose, but quite a hard job, to build the needed > > transistor structure to implement the vhdl in real silicon. > > > best regards Thomas > > That's funny, I have some parts on a current board design that do > pretty much this. =A0They are called switches. =A0One of the inputs will > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > added to the control input and it would do exactly what I was coding. > > Rick Hi Rick, if some input of a CMOS device really sees a 'Z' and does not use some internal pullup, it may end up oscillating at some very high frequency. In the worst case this may even blow up your input buffer. So if you have some board with switches that leave the inputs "open" you are either required to use the internal pullups, or there's some connector parallel to the switches so you can use the I/Os for some other optional hardware (this requires the switches always to be held in the open position). In any case, a CMOS input will never properly recognize a 'Z' condition, the input driver will either drive a '0' or '1' and you can't establish a pure wire connection between two pads inside an FPGA. There's always an IBUF and OBUF. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:12:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!hg8g2000vbb.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Array pipeline Date: Fri, 1 Apr 2011 04:10:38 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: References: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301656238 9799 127.0.0.1 (1 Apr 2011 11:10:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 11:10:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hg8g2000vbb.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 11j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4902 On Apr 1, 7:50=A0am, hssig wrote: > arr3d(arr3d'high-1 downto 0)(m) > <=3D arr3d(arr3d'high downto 1)(m); =A0--** ERROR Huh? You're taking a slice of an array, and then trying to subscript it? I didn't think that was possible, but it seems that maybe it is (must go check the LRM!) and the (m) is being used as a subscript into the slice arr3d(arr3d'high-1 downto 0). You need an inner for-loop to do that copy, scanning over the first subscript of arr3d. I don't see why you need the m-loop at all, since you're just copying bits broadside. What's wrong with this: arr3d(arr3d'high) <=3D vecarr; arr3d(arr3d'high-1 downto 0) <=3D arr3d(arr3d'high downto 1); Or something like this... for i in arr3d'range loop if i =3D arr3d'high then arr3d(i) <=3D vecarr; else arr3d(i) <=3D arr3d(i+1); end if; end loop; I don't see the need for a loop scanning over the subcomponents of the t_vecarr objects. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Fri, 1 Apr 2011 06:47:19 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 199.4.132.1 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301665639 6756 127.0.0.1 (1 Apr 2011 13:47:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 13:47:19 +0000 (UTC) In-Reply-To: <859f951f-4ef0-4a3e-aa6c-86b19acc13e2@d28g2000yqc.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=199.4.132.1; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4903 On Wednesday, March 30, 2011 4:20:31 PM UTC-5, KJ wrote: > 1. Similar to what Jonathon suggested, but a bit easier (I think) to > draw good boundary lines for the testing entity is to model real > parts. FPGAs in real applications do not exist untethered to the rest > of the world, they are connected to real parts on a circuit board so > your 'FPGA testbench' could (I think 'should') be a model of that PCBA > (and surrounding systems)...which means that if you model the parts > that go on that PCBA and connect them per the netlist then you're > modelling your real system. In your case, you had mentioned in later I've actually done this for downstream effects. If the FPGA is driving a A= DC or DAC or other peripheral, I base the model on the datasheet and implem= ent it to some degree of fidelity (usually loose at first, and then growing= complexity over time, with timing checking assertions and the like.) I've= not done this with the stimulus side though, as frequently it seems like t= hat task is more daunting than time permits. I rough in some interface bas= ics but it's pretty rough and ready (hence trying to find a better solution= .) I appreciate the thoughts. I'll consider more involved stimulus models if = I can get the reuse and maintainability aspects in line. Best regards, Mark From newsfish@newsfish Fri Feb 3 13:12:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!news.glorb.com!news2.glorb.com!postnews.google.com!w21g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Style Request for Testbench with Bus Interfaces Date: Fri, 1 Apr 2011 08:24:47 -0700 (PDT) Organization: http://groups.google.com Lines: 80 Message-ID: <298cbfbb-8d7b-4ebe-bd34-b766bb448bbb@w21g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301671487 559 127.0.0.1 (1 Apr 2011 15:24:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Apr 2011 15:24:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w21g2000yqm.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4904 On Apr 1, 9:47=A0am, "M. Norton" wrote: > On Wednesday, March 30, 2011 4:20:31 PM UTC-5, KJ wrote: > > 1. Similar to what Jonathon suggested, but a bit easier (I think) to > > draw good boundary lines for the testing entity is to model real > > parts. =A0FPGAs in real applications do not exist untethered to the res= t > > of the world, they are connected to real parts on a circuit board so > > your 'FPGA testbench' could (I think 'should') be a model of that PCBA > > (and surrounding systems)...which means that if you model the parts > > that go on that PCBA and connect them per the netlist then you're > > modelling your real system. =A0In your case, you had mentioned in later > > I've actually done this for downstream effects. =A0If the FPGA is driving= a ADC or DAC or other peripheral, I base the model on the datasheet and im= plement it to some degree of fidelity (usually loose at first, and then gro= wing complexity over time, with timing checking assertions and the like.) = =A0I've not done this with the stimulus side though, as frequently it seems= like that task is more daunting than time permits. =A0 KJ: In what way would it be more daunting to put stimulus code within the entity for the model for a real part then it is to put it in some freeform testbench? In order to provide stimulus (and check responses) you have to write 'something', I'm simply saying that putting that 'something' inside the model of real part(s) would be a better overall location than just into some otherwise probably non- reusable testbench. The only additional work is the creation of the entity for the part(s) and the creation of a PCBA and/or system model. The PCBA model creation is simply instantiating the parts and connecting nets. Tedious perhaps if you have a lot of parts, but not difficult. However, if you have a lot of parts that need modelling in order to test the design, it likely indicates that you'd also need a rather large and cumbersome freeform testbench. > I rough in some interface basics but it's pretty rough and ready (hence t= rying to find a better solution.) > > I appreciate the thoughts. =A0I'll consider more involved stimulus models= if I can get the reuse and maintainability aspects in line. > : I think you'll find that creating part models is a good enabler for reuse and maintainability. The reason for this is that entities are the easiest things to reuse, you simply instantiate the component and connect it up. Entities are also the natural hierarchy boundary in VHDL. Within a part model you might use existing designs that you already have. Or, when you're creating a new part you might realize that if you only partitioned some other model a bit differently you could now reuse that part. That's when you go back and re-factor the original design to create a now reusable entity. Re-factoring is a natural result of design, sometimes you get it correct right from the git-go, other times you want to break designs down into even smaller, reusable, maybe more generally useful pieces. By using real parts that have real specifications as the basis for your testbench you also pick up the following advantages that apply to reuse and maintainability: - The part model can be validated to the specification independently of the design that the part model is being used to verify in the testbench...one spends as much time or more verifying a design as you do designing the thing, yet what is the objective criteria for validating that the testbench itself is correct? - As the part model is refined to be more inclusive of functions that weren't initially needed, backwards compatibility is maintained. Since the entity for the part model is not changing (that gets setup at the begining based on the pinout of the part that you get from the specification), only the code in the architecture for the part model is getting tweaked. All this is doing is refining the function to more closely reflect reality. If that 'breaks' something in a simulation testbench then it indicates that either the changes to the part model are not quite correct (refer back to the part specification to determine) or you've uncovered a hole in the older design that should probably be fixed. Any result is a 'good thing' resulting in a higher quality design or higher quality part model or additional validation that the design really does work as expected. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of Logic on Non-boolean Constants Date: Fri, 1 Apr 2011 22:17:10 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: <0dfb9668-2d35-4dd9-92c7-fe5ebae52256@q12g2000prb.googlegroups.com> <302ebf85-eeab-4cac-a1ea-a37f2e542391@s11g2000yqh.googlegroups.com> <67270d79-5df2-40e8-86e7-31d915ec7c85@r6g2000vbo.googlegroups.com> <83c3181f-f827-49fc-bc10-03ac0f38b043@d2g2000yqn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1301721430 14028 127.0.0.1 (2 Apr 2011 05:17:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 2 Apr 2011 05:17:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4905 On Apr 1, 3:47=A0am, backhus wrote: > On 30 Mrz., 17:04, rickman wrote: > > > > > On Mar 30, 8:49=A0am, Thomas Stanka > > wrote: > > > > On 29 Mrz., 18:13, rickman wrote: > > > > > I was using some logic to shorten typing of some operations where I > > > > was trying to create tristate drivers. =A0To be sure of the result = I > > > > looked up the logic tables and found that, for example the OR funct= ion > > > > on a constant 'z' and a signal produces a '1' when the signal is a > > > > '1', but when the signal is a zero results in an 'x'. =A0This is no= t the > > > > same as a 'z' obviously, which is what I wanted. =A0Clearly this is= not > > > > a good idea even if it is shorter to type. > > > > So want the technology to contain a buffer that has an high impedance > > > output in case of one input is high impedance? > > > But else the output needs to be low impedance either driving '0' or > > > '1'. Seems quite unusual to be found in any tech library. > > > > Your problems seems to me not vhdl related, instead you need to think > > > in dedicated hardware functionality. > > > It is quite easy to construct a logic function in vhdl that helps you= r > > > need for simulation purpose, but quite a hard job, to build the neede= d > > > transistor structure to implement the vhdl in real silicon. > > > > best regards Thomas > > > That's funny, I have some parts on a current board design that do > > pretty much this. =A0They are called switches. =A0One of the inputs wil= l > > cause a 'Z' on the output when the input is a 'Z'. =A0A little logic > > added to the control input and it would do exactly what I was coding. > > > Rick > > Hi Rick, > if some input of a CMOS device really sees a 'Z' and does not use some > internal pullup, > it may end up oscillating at some very high frequency. In the worst > case this may even blow up your input buffer. > > So if you have some board with switches that leave the inputs "open" > you are either required to use the internal pullups, > or there's some connector parallel to the switches so you can use the > I/Os for some other optional hardware (this requires the switches > always to be held in the open position). > > In any case, a CMOS input will never properly recognize a 'Z' > condition, the input driver will either drive a '0' or '1' > and you can't establish a pure wire connection between two pads inside > an FPGA. There's always an IBUF and OBUF. > > Have a nice synthesis > =A0 Eilert I think you are confusing two things. One is how synthesis works. It concerns with the resulting overall behavior, it does not care how you construct that behavior with your equations. The fact that I propagate a 'z' through a logic block in the HDL does not require that this block be replaced by some sort of gate that exactly implements that block. This can easily be combined with whatever logic is producing the 'z' that is to be propagated through the block and result in a tristate driver with some logic function driving the enable... which is exactly what I was trying to do. The other point of confusion is how a switch works. A switch has a logic input that operates as you describe and two switch I/Os that literally operate as a passive switch. These I/Os will not oscillate in any sense because they do not amplify. This is all moot or as George Costanza might say, "moop". The logic block does not propagate a 'z' and it is not worth writing my own function for this. Rick From newsfish@newsfish Fri Feb 3 13:12:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!k9g2000yqi.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Array pipeline Date: Mon, 4 Apr 2011 00:45:43 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: References: <7c6bc392-a398-448e-9a54-09975cacc96c@hg8g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1301903143 30574 127.0.0.1 (4 Apr 2011 07:45:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 4 Apr 2011 07:45:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k9g2000yqi.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4906 Hi Jonathan, thank you for your alternative description. I have just been curious about the reason why my solution does not work. Now it is clear. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:12:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "Harold Aptroot" Newsgroups: comp.lang.vhdl Subject: "Clockless" computing Date: Thu, 7 Apr 2011 09:39:48 +0200 Organization: A noiseless patient Spider Lines: 1 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; format=flowed; charset="utf-8"; reply-type=original Content-Transfer-Encoding: 7bit Injection-Date: Thu, 7 Apr 2011 07:39:46 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="Jl9kUHHBpr7ZpIKLJZRZZw"; logging-data="4710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+OVIAXm9FueC+NN+oQYkvW" X-MimeOLE: Produced By Microsoft MimeOLE V12.0.1606 X-Newsreader: Microsoft Windows Live Mail 12.0.1606 Importance: Normal Cancel-Lock: sha1:+h83X6meME+339MG9QhFoKSBUmI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:4907 This isn't really a VHDL question, but I'm not sure where else to ask it. I'm considering designing a system using only the following building blocks (and wires and memory cells): 1: in || out c | v || x | y 0 | 0 || 0 | 0 0 | 1 || 0 | 0 1 | 0 || 0 | 1 1 | 1 || 1 | 0 2: in || out x | y || c | v 0 | 0 || 0 | ? 0 | 1 || 1 | 1 1 | 0 || 1 | 0 1 | 1 || 0 | ? (? represents "don't care") The C is supposed to be connected to an X or Y or C, V is should be connected to V. C represents the "clock" that is explicitly passed around. X and Y encode 0 and 1 respectively. The purpose of block type 1 is doing the main calculations, block 2 takes a result and turns it into a pair of (clock, value). One motivation for this system is that the block type 1 directly encodes a node from a (reduced) binary decision diagram, which are easy to manipulate. I know it's "logically complete" in the sense that I could compute anything with those blocks, but is it also a good way? Are there better ways? -- harold From newsfish@newsfish Fri Feb 3 13:12:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!a12g2000yqk.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: "Clockless" computing Date: Thu, 7 Apr 2011 01:50:19 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302166219 5229 127.0.0.1 (7 Apr 2011 08:50:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Apr 2011 08:50:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a12g2000yqk.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4908 On 7 Apr., 09:39, "Harold Aptroot" wrote: > This isn't really a VHDL question, but I'm not sure where else to ask it. > > I'm considering designing a system using only the following building blocks > (and wires and memory cells): > > 1: > in || out > c | v || x | y > 0 | 0 || 0 | 0 > 0 | 1 || 0 | 0 > 1 | 0 || 0 | 1 > 1 | 1 || 1 | 0 > > 2: > in || out > x | y || c | v > 0 | 0 || 0 | ? > 0 | 1 || 1 | 1 > 1 | 0 || 1 | 0 > 1 | 1 || 0 | ? > > (? represents "don't care") > > The C is supposed to be connected to an X or Y or C, V is should be > connected to V. > C represents the "clock" that is explicitly passed around. X and Y encode 0 > and 1 respectively. > The purpose of block type 1 is doing the main calculations, block 2 takes a > result and turns it into a pair of (clock, value). > One motivation for this system is that the block type 1 directly encodes a > node from a (reduced) binary decision diagram, which are easy to manipulate. > > I know it's "logically complete" in the sense that I could compute anything > with those blocks, but is it also a good way? Are there better ways? > > -- > harold Hi Harold, in this group and also in the rest of the net you find various informations when you look for "asynchronous logic" design. There are many projects and papers covering this topic. A starting point for your investigations may be this one, if you don't know it already: http://en.wikipedia.org/wiki/C-element Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:12:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!news.cgarbs.de!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!v8g2000yqb.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 08:12:52 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302275572 20269 127.0.0.1 (8 Apr 2011 15:12:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 15:12:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v8g2000yqb.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4909 Im building a model of a memory interface. The entity mimics the interface of the normal memory interface with multiple request, address, ack and data valid lines, one set per channel. Internally I have a protected type that handles the memory modelling (dynamically creating memory locations as they are accessed so I dont have a monstrous 256Mbyte array declared) and another protected that handles the read queue. As this is modelling a memory in a video system, I want to be able to dump whole images (ie bypassing the whole interface) into memory, for example if Im only testing the other bits of the design on the read side of the interface. I have everything I need for reading/writing bitmaps to specific array types, but I just need to get these arrays into this entity. Heres the pinch - I really dont want to specify the size of the image, as this may well handle multiple video standards on hardware, so I need the image sizes to vary accordingly. Id love to be able to pass in an access type and watch the transactions on it - but of course access types can only be variables - therefore not suitable for ports on an entity. Can anyone think of any other way I could get these arrays into the interface without padding? The only thing I can think of is sticking image sizes as generics and declaring the "image" port to this size, but I would prefer more flexibility. So - am I just pushing too hard? How long before someone pipes up that I should try System Verilog? From newsfish@newsfish Fri Feb 3 13:12:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!feedme.ziplink.net!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!2g2000vbl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 12:31:18 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302291078 27884 127.0.0.1 (8 Apr 2011 19:31:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 19:31:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 2g2000vbl.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4910 On Apr 8, 11:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > > Heres the pinch - I really dont want to specify the size of the image, > as this may well handle multiple video standards on hardware, so I > need the image sizes to vary accordingly. Id love to be able to pass > in an access type and watch the transactions on it - but of course > access types can only be variables - therefore not suitable for ports > on an entity. Can anyone think of any other way I could get these > arrays into the interface without padding? > Dump the data to a file. Use a string to pass the file name into the memory model. If the file name needs to be able to be changed during the simulation (i.e. if it must be a 'signal' rather than a 'generic') than the only limitation will be that the string name will need to be a fixed size. Even that limitation can be less onerous if you simply use a loooooong string size, null terminate the string and then have the memory model construct the file name by looking for the null termination. Even better, if you're using standard bitmap file formats like .BMP for the exchange than you can create read/write BMP file procedures which you will no doubt use somewhere down the road and not be tied to this particular memory model instance. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!j13g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 8 Apr 2011 13:54:48 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <46151aa6-c206-40a9-bb80-d2e8d40ce0c1@j13g2000yqj.googlegroups.com> References: NNTP-Posting-Host: 192.91.173.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302296088 13231 127.0.0.1 (8 Apr 2011 20:54:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Apr 2011 20:54:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000yqj.googlegroups.com; posting-host=192.91.173.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4911 On Apr 8, 10:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > > Heres the pinch - I really dont want to specify the size of the image, > as this may well handle multiple video standards on hardware, so I > need the image sizes to vary accordingly. Id love to be able to pass > in an access type and watch the transactions on it - but of course > access types can only be variables - therefore not suitable for ports > on an entity. Can anyone think of any other way I could get these > arrays into the interface without padding? > > The only thing I can think of is sticking image sizes as generics and > declaring the "image" port to this size, but I would prefer more > flexibility. > > So - am I just pushing too hard? How long before someone pipes up that > I should try System Verilog? How about flattening your image into a single vector, and pass it in on an unconstrained array (e.g. SLV) port? Add generics (static) or other ports (dynamic) for pixel/row/column size to tell the model how to extract the image from the linear vector. Andy From newsfish@newsfish Fri Feb 3 13:12:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Fri, 08 Apr 2011 22:48:12 +0100 Organization: A noiseless patient Spider Lines: 35 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx02.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="1142"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+v6Iwo+hBc4HvWtmCGGYUt7PTU3qw0eWo=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:oQpjgMwJlQpQF1fa3gnA0gl0qX8= Xref: feeder.eternal-september.org comp.lang.vhdl:4912 On Fri, 8 Apr 2011 08:12:52 -0700 (PDT), Tricky wrote: > Id love to be able to pass >in an access type and watch the transactions on it - but of course >access types can only be variables - therefore not suitable for ports >on an entity. Can anyone think of any other way I could get these >arrays into the interface without padding? In the past when I've needed to do this kind of thing, one approach has been to create a package with a pool of objects (shared variables) in it, and then have entity instances register themselves with the package by calling appropriate functions in it. An instance can supply its own instance name to such a call as a string including 'PATH_NAME, allowing the package to work out which instance placed the call. It's a bit upside-down and clumsy, but can sometimes provide the kind of functional communication you seem to be wanting. You likely need some sort of side-channel into the instances, in the form of a regular port of boolean or some enumerated type, to allow you to signal interesting events from one instance to another; the instances can then use the package pool as a shared communication medium, and the idea of each instance registering itself with the package by means of its string instance name stops things being outrageously global. It's a while since I did any of this, so the details are a bit sketchy in my mind. But it looks as though I may soon be needing to dust off these tricks once again... -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Sat, 9 Apr 2011 08:15:44 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <4b9cc046-42e6-44bb-bb59-f0b979f1d417@l6g2000vbn.googlegroups.com> References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> NNTP-Posting-Host: 213.104.217.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302362145 26141 127.0.0.1 (9 Apr 2011 15:15:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 9 Apr 2011 15:15:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=213.104.217.142; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 ( .NET CLR 3.5.30729; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4913 On Apr 8, 8:31=A0pm, KJ wrote: > On Apr 8, 11:12=A0am, Tricky wrote: > > > > > Im building a model of a memory interface. The entity mimics the > > interface of the normal memory interface with multiple request, > > address, ack and data valid lines, one set per channel. Internally I > > have a protected type that handles the memory modelling (dynamically > > creating memory locations as they are accessed so I dont have a > > monstrous 256Mbyte array declared) and another protected that handles > > the read queue. > > > As this is modelling a memory in a video system, I want to be able to > > dump whole images (ie bypassing the whole interface) into memory, for > > example if Im only testing the other bits of the design on the read > > side of the interface. I have everything I need for reading/writing > > bitmaps to specific array types, but I just need to get these arrays > > into this entity. > > > Heres the pinch - I really dont want to specify the size of the image, > > as this may well handle multiple video standards on hardware, so I > > need the image sizes to vary accordingly. Id love to be able to pass > > in an access type and watch the transactions on it - but of course > > access types can only be variables - therefore not suitable for ports > > on an entity. Can anyone think of any other way I could get these > > arrays into the interface without padding? > > Dump the data to a file. =A0Use a string to pass the file name into the > memory model. =A0If the file name needs to be able to be changed during > the simulation (i.e. if it must be a 'signal' rather than a 'generic') > than the only limitation will be that the string name will need to be > a fixed size. =A0Even that limitation can be less onerous if you simply > use a loooooong string size, null terminate the string and then have > the memory model construct the file name by looking for the null > termination. > > Even better, if you're using standard bitmap file formats like .BMP > for the exchange than you can create read/write BMP file procedures > which you will no doubt use somewhere down the road and not be tied to > this particular memory model instance. > > Kevin Jennings Thanks all of you for the ideas. Kevins is definatly the most practical for me. Ive had a library full of bitmap reading, writing and colour space converting for about 3 years, so the string thing is easiest (already have a string pad function and string tokenising protected type, so I can easily pass in multiple images in a single generic from the top level testbench) - normally I throw images around in their own array type once read, which is probably why I didnt think of it myself. Im going to make a record type with start address and image path, and sit on that port waiting for a transaction. Cheers guys :) From newsfish@newsfish Fri Feb 3 13:12:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 11 Apr 2011 11:14:12 +0100 Organization: TRW Conekt Lines: 30 Message-ID: References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net jOHp5o4KpTlsm/mh8rfgtw6gtqre08lKGA+I9yqsd14KenbZw= Cancel-Lock: sha1:gLY6LMliJT+ohQtbxg/FQXA5BRo= sha1:tDsvF+yu/zEddQ1r6ntEdaYLZbA= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4914 KJ writes: > Dump the data to a file. Use a string to pass the file name into the > memory model. If the file name needs to be able to be changed during > the simulation (i.e. if it must be a 'signal' rather than a 'generic') > than the only limitation will be that the string name will need to be > a fixed size. Even that limitation can be less onerous if you simply > use a loooooong string size, null terminate the string and then have > the memory model construct the file name by looking for the null > termination. > > Even better, if you're using standard bitmap file formats like .BMP > for the exchange than you can create read/write BMP file procedures > which you will no doubt use somewhere down the road and not be tied to > this particular memory model instance. Seconded. For other readers (as I know both KJ and Tricky know this) when I do this, I use ASCII-PGM files, as I've found accessing binary files (like BMP) to be non-portable across simulators. If this doesn't matter to you, by all means use BMP :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:12:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 11 Apr 2011 10:58:02 +0000 (UTC) Organization: A noiseless patient Spider Lines: 42 Message-ID: References: <518030f7-18bb-4fb6-b3dc-1cabf63c5d7d@2g2000vbl.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 11 Apr 2011 10:58:02 +0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="9/3/IeP/twTQFh5cJa2wYg"; logging-data="11742"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18sevUHvbT3NNClqEOHIg20mQmn+3yAV/8=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:mOL8XlEPP8QGWl5UF+pefxRySDg= Xref: feeder.eternal-september.org comp.lang.vhdl:4915 On Mon, 11 Apr 2011 11:14:12 +0100, Martin Thompson wrote: > KJ writes: > >> Dump the data to a file. Use a string to pass the file name into the >> memory model. If the file name needs to be able to be changed during >> the simulation (i.e. if it must be a 'signal' rather than a 'generic') >> than the only limitation will be that the string name will need to be a >> fixed size. Even that limitation can be less onerous if you simply use >> a loooooong string size, null terminate the string and then have the >> memory model construct the file name by looking for the null >> termination. >> >> Even better, if you're using standard bitmap file formats like .BMP for >> the exchange than you can create read/write BMP file procedures which >> you will no doubt use somewhere down the road and not be tied to this >> particular memory model instance. > > Seconded. > > For other readers (as I know both KJ and Tricky know this) when I do > this, I use ASCII-PGM files, as I've found accessing binary files (like > BMP) to be non-portable across simulators. If this doesn't matter to > you, by all means use BMP :) > My approach has been to perform binary I/O through an unofficial "portability layer". Modelsim and Xilinx ISIM (10.3) are the two I have experience of. ISIM insists on reading a short undocumented* header before the actual data. To satisfy this, I have simple scripts to separate header and file (using "head" and "tail) from ISIM output files, and to "cat" a header onto any binary file before I read it into ISIM. The other difference is endian-ness; I set a boolean flag ("is_isim") which controls end-swapping in both input/output routines. (* Xilinx refused to provide any documentation on the header despite a Webcase specifically asking for it) - Brian From newsfish@newsfish Fri Feb 3 13:12:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p3g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 05:37:48 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302525468 10526 127.0.0.1 (11 Apr 2011 12:37:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Apr 2011 12:37:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p3g2000vbv.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4916 I have the following line of code: img_height := ( img.get_image )'length(1); img is a protected type. get_image is a function returning a 2D array containing the image data. img_height is an integer. Now, in modesim I get the compilation error: # ** Error: hdl/mem_interface_model.vhd(745): near "'": expecting ';' The error is pointing to the 'length attribute. So I can see that modelsim wants to end the like at the function call, but what's wrong with taking the attribute of a return value. Before anyone asks, Ive found an annoying bug that crashes the modelsim compiler which mean (for reasons of my file) I cannot have functions that return the width or height of the image in the protected type. It works when I return the image array, so Im trying to work around this bug with the code above. From newsfish@newsfish Fri Feb 3 13:12:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 11:13:55 -0800 Lines: 14 Message-ID: <90gulfFpn9U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net Fw90fNAv8C5sKBjV4MNGtw2OUgDYiqlBoaAR83YwgBXb3GGjqP Cancel-Lock: sha1:7J7TWiCHX7t5n7CXbvS96nshOuk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4917 On 4/11/2011 4:37 AM, Tricky wrote: > I have the following line of code: > > img_height := ( img.get_image )'length(1); > > img is a protected type. > get_image is a function returning a 2D array containing the image > data. > img_height is an integer. Why doesn't the (1) go with the array? -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!o26g2000vby.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Mon, 11 Apr 2011 15:12:58 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <1c8f0e93-01c7-498b-b2c6-5b69130544a7@o26g2000vby.googlegroups.com> References: <90gulfFpn9U1@mid.individual.net> NNTP-Posting-Host: 213.104.217.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302559978 14583 127.0.0.1 (11 Apr 2011 22:12:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Apr 2011 22:12:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o26g2000vby.googlegroups.com; posting-host=213.104.217.142; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4918 On Apr 11, 8:13=A0pm, Mike Treseler wrote: > On 4/11/2011 4:37 AM, Tricky wrote: > > > I have the following line of code: > > > img_height =A0 =A0 =A0 =A0 =A0 =A0 =A0:=3D ( img.get_image )'length(1); > > > img is a protected type. > > get_image is a function returning a 2D array containing the image > > data. > > img_height is an integer. > > Why doesn't the (1) go with the array? > > =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Mike Treseler n-d arrays, declared like this: type my_array is array( integer range <>, integer range <>, integer range etc etc) of integer; means that you have to specify which dimension you are talking about when you try and take an attribute, hence the (1). From newsfish@newsfish Fri Feb 3 13:12:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: devas Newsgroups: comp.lang.vhdl Subject: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 08:37:07 +0200 Organization: A noiseless patient Spider Lines: 16 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 12 Apr 2011 06:37:08 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="ZslfkjcUaqWzR39Tw0NfYg"; logging-data="15920"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18cI5Hfj4DdADJRG++lD2wq" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 Cancel-Lock: sha1:UDQPW+9x9Ry4KrdwClztjUN7ZSk= Xref: feeder.eternal-september.org comp.lang.vhdl:4919 Hi Gurus, What is your opinion for coding combinational logic (multiplexer) in VHDL. Using a conditional signal assignment or using a process? What are the pro's and con's for both? I can imagine that for simulation performance a process is efficienter as it will only be reached when one of the signals on the sens. list changes. A con could be the danger of an incomplete sens. list. I would like to know your opinion and what your are using. Thanks, Devas From newsfish@newsfish Fri Feb 3 13:12:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!transit3.readnews.com!postnews.google.com!x18g2000yqe.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 00:01:49 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <19f24aaf-b117-47dd-9d23-6f67668efbc8@x18g2000yqe.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302591709 4442 127.0.0.1 (12 Apr 2011 07:01:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 07:01:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x18g2000yqe.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.16) Gecko/20110323 Ubuntu/10.04 (lucid) Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4920 On 12 Apr., 08:37, devas wrote: > Hi Gurus, > > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > > I can imagine that for simulation performance a process is efficienter > as it will only be reached when one of the signals on the sens. list > changes. A con could be the danger of an incomplete sens. list. > > I would like to know your opinion and what your are using. > > Thanks, > > Devas Hi Devas, with the upcoming of VHDL-2008 and the process(all) feature, the differences in performance and danger of simulation faults should be rendered to almost neglectable. Also with VHDL-2008 the when..else and with..select constructs can be used inside processes. So, even the coding style difference is mostly evened out. What's left is merely a question of personally prefered coding style. One might argue, that not all synthesis tools support this yet, but time flies and before long this won't be a problem anymore. --- My personal choice is to have as few concurrent code lines in my architecture as possible, and put every functional part in processes. Sometimes specific assignments to output ports are necessary, but that's just one-liners. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:12:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!p16g2000vbi.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 01:16:41 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302596201 21762 127.0.0.1 (12 Apr 2011 08:16:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 08:16:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p16g2000vbi.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4921 On Apr 12, 7:37=A0am, devas wrote: > Hi Gurus, > > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > Theres not really a lot of difference. A signal assignment outside of a formal process is really just another process, with the sensitivity list set by the signals on the right hand side. so this code: output <=3D a when sel =3D '0' else b; is the same as: process(a, b, sel) begin if sel =3D '0' then output <=3D a; else output <=3D b; end if; end process; From newsfish@newsfish Fri Feb 3 13:12:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!d28g2000yqc.googlegroups.com!not-for-mail From: AllianceGlobalServices Newsgroups: comp.lang.vhdl Subject: IT consulting offshore application custom software development outsourcing services from Philadelphia, New Jersey, New York, Boston- Alliance Global Services Date: Tue, 12 Apr 2011 04:03:24 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302606204 10103 127.0.0.1 (12 Apr 2011 11:03:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 11:03:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d28g2000yqc.googlegroups.com; posting-host=183.82.117.168; posting-account=K8umZQoAAADtiMCit-5hZ2nqeNYCEcor User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4922 Global IT consulting company in Boston, New Jersey, New York, Philadelphia specializing in offshore application custom software product development outsourcing maintenance, information publishing consulting and managed software testing outsourcing automation services www.allianceglobalservices.com From newsfish@newsfish Fri Feb 3 13:12:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!l11g2000yqb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 07:11:55 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302617515 26327 127.0.0.1 (12 Apr 2011 14:11:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 14:11:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l11g2000yqb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4923 On Apr 12, 4:16=A0am, Tricky wrote: > On Apr 12, 7:37=A0am, devas wrote: > > > Hi Gurus, > > > What is your opinion for coding combinational logic (multiplexer) in > > VHDL. Using a conditional signal assignment or using a process? What ar= e > > the pro's and con's for both? > > Theres not really a lot of difference. A signal assignment outside of > a formal process is really just another process, with the sensitivity > list set by the signals on the right hand side. > > so this code: > > output <=3D a when sel =3D '0' else b; > > is the same as: > > process(a, b, sel) > begin > =A0 if sel =3D '0' then > =A0 =A0 output <=3D a; > =A0 else > =A0 =A0 output <=3D b; > =A0 end if; > end process; I see one major difference. The process is eight lines of code and the concurrent statement is only one. Which do you think is easier to read and provides fewer opportunities for errors? Rick From newsfish@newsfish Fri Feb 3 13:12:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!v10g2000yqn.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 08:54:37 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302623948 26137 127.0.0.1 (12 Apr 2011 15:59:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 15:59:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v10g2000yqn.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 14j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4924 On Apr 12, 3:11=A0pm, rickman wrote: > > so this code: > > > output <=3D a when sel =3D '0' else b; > > > is the same as: > > > process(a, b, sel) > > begin > > =A0 if sel =3D '0' then > > =A0 =A0 output <=3D a; > > =A0 else > > =A0 =A0 output <=3D b; > > =A0 end if; > > end process; > > I see one major difference. =A0The process is eight lines of code and > the concurrent statement is only one. =A0Which do you think is easier to > read and provides fewer opportunities for errors? In the interests of civil discussion I'll temporarily pretend that this stance doesn't make my blood boil. Instead I'll politely point out that, on the very rare occasions when I really want something that simple as a standalone thing, then the concurrent statement is indeed probably better. Three-state I/O buffers are the best and commonest example. And I'll also politely point out that decomposing designs into pieces small enough to represent as concurrent statements makes each piece trivially easy to understand, but makes the whole design as comprehensible as a broken-up jigsaw puzzle. Taking a complicated thing and breaking it into lots of simple pieces doesn't make it simpler. It simply turns the complicated thing into a pile of pieces. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tramontana.escomposlinux.org!cagarruta.escomposlinux.org!escomposlinux.org!news.antakira.com!news.glorb.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 09:27:39 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302625941 23029 127.0.0.1 (12 Apr 2011 16:32:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 16:32:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4925 On Apr 12, 11:54=A0am, Jonathan Bromley wrote: > On Apr 12, 3:11=A0pm, rickman wrote: > > I see one major difference. =A0The process is eight lines of code and > > the concurrent statement is only one. =A0Which do you think is easier t= o > > read and provides fewer opportunities for errors? > > Instead I'll politely point out that, on the > very rare occasions when I really want something > that simple as a standalone thing, then the > concurrent statement is indeed probably better. Based on what devas posted, the 'standalone thing' is all that one can guess that devas is interested in for the reasons that were listed. > > Taking a complicated thing and breaking it > into lots of simple pieces doesn't make it > simpler. =A0It simply turns the complicated > thing into a pile of pieces. I agree in principle...but in this case, the only context given by devas in his posting was in the pros and cons of coding a mux as either a conditional signal assignment or using a process. In this case, there is no 'complicated thing' being broken into simpler pieces. Your comment though is valid, but should be directed to devas within the context of 'hey, why are you spending time thinking about the coding of a mux'? The opportunities to code a mux by itself are relatively few and far between. The opportunities to describe logic that also includes mux-like behavior are far more numerous and rarely are enhanced by the ability to describe this behavior explicitly as a standalone thing (whether as a process or concurrent statement). But then again maybe devas is just getting started in design and/or VHDL or perhaps his interest is not in designing something in VHDL but is actually in simulator performance, or some theoretical language aspect, something more abstract, who knows? In any case, devas was already aware of the major drawback from the standpoint of creating reliable/maintainable designs of the process which is that of an incomplete sensitivity list (prior to VHDL-2008). On the other hand, devas seems misinformed (or maybe needs to experimentally try) about why he thinks the process approach would be more efficient in simulation than the concurrent assignment. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 19:58:57 +0100 Organization: A noiseless patient Spider Lines: 32 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx03.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="2548"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18NJ8GIpJNfgEkL5hG8Eiz4jTaQD1gSqyA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:GdaioJjCHLlyFsisWj0yTxcqrGA= Xref: feeder.eternal-september.org comp.lang.vhdl:4926 On Tue, 12 Apr 2011 09:27:39 -0700 (PDT), KJ wrote: >Based on what devas posted, the 'standalone thing' is all that one can >guess that devas is interested in for the reasons that were listed. I apologize if I confused or misled the OP. My post was responding to yet another clear description of the position that states "bugs increase monotonically with lines of code, therefore anything that locally reduces the number of lines of code is good". This I regard as such pernicious nonsense that I will unapologetically seize on any opportunity to challenge it, especially if expressed in a way that encourages the decomposition of designs into absurdly small and meaningless pieces. >In this case, there is no 'complicated thing' >being broken into simpler pieces. True. I carefully pointed out that this can happen, in some very specific situations, and there the shorter description is entirely appropriate. >Your comment though is valid, but should be directed to devas within >the context of 'hey, why are you spending time thinking about the >coding of a mux'? It could have been, but wasn't; that was not my target. The OP's question was reasonable, and evinced reasonable answers; it was the added spin on those answers that riled me. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!talisker.lacave.net!lacave.net!nospam.fr.eu.org!nntpfeed.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!k30g2000yqb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 13:13:39 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.91.172.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302639219 5900 127.0.0.1 (12 Apr 2011 20:13:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Apr 2011 20:13:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k30g2000yqb.googlegroups.com; posting-host=192.91.172.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4927 For one simple, combinatorial function with one output, I prefer the concurrent assignment. Features that make me lean toward using a process include: more than one output controlled similarly by the same inputs, logic that feeds a register within the same architecture, nested if-then logic, existence of related logic that is already in a process Since one or more of these features is often present in my projects, I usually use processes with sequential statements, synchronous when possible. Extensive use of concurrent statements starts to look like coding a netlist (and reads like one too), instead of coding a synthesizeable behavior with sequential statements, which is usually easier to understand. Andy From newsfish@newsfish Fri Feb 3 13:12:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 13:23:03 -0800 Lines: 22 Message-ID: <90jqjiFhcaU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net YJ6yqRjObSMrQVKOwhE9GgklnjIOzI7lWwo3mrBOgl9AibKuBB Cancel-Lock: sha1:ZPkQlNwla96+5w9w1oltliqn+i0= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4928 On 4/11/2011 10:37 PM, devas wrote: > What is your opinion for coding combinational logic (multiplexer) in > VHDL. Using a conditional signal assignment or using a process? What are > the pro's and con's for both? > I would like to know your opinion and what your are using. Synthesis requires an entity. Since each entity has code overhead, I describe logic at a higher level for less overall code. I describe the entity output ports only in terms of input ports and local variables, rather than muxes and flops. For example in this stack design: http://bit.ly/fkbaqW no muxes are described directly, yet synthesis inferred several: http://bit.ly/g5Asyr -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r19g2000prm.googlegroups.com!not-for-mail From: "daniel.kho" Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 12 Apr 2011 23:03:41 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> NNTP-Posting-Host: 203.126.136.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302674622 16019 127.0.0.1 (13 Apr 2011 06:03:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 06:03:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r19g2000prm.googlegroups.com; posting-host=203.126.136.142; posting-account=E_uw0woAAADCvYspyKEeRBiQ2V7SG80D User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4929 On Apr 13, 4:13=A0am, Andy wrote: > For one simple, combinatorial function with one output, I prefer the > concurrent assignment. Yes, for me as well. If a block (or sub-block) seems simple enough to describe as a one-liner (or a few lines) of concurrent statements, go for it. If my block/sub-block starts getting a bit more complex, I'll start putting those concurrent statements within a process instead. When it gets difficult to behaviourally describe your functionality with just a few concurrent statements, and when you start breaking up a concurrent statement to multiple smaller concurrent statements, that's when you're beginning to change your behavioural design to a structural one, i.e. one that doesn't describe the behaviour and therefore is difficult to understand. When I could foresee that I'm heading this (wrong) direction, I'll steer myself back to enclose those statements in a process, and add whatever other functionality I need. Daniel Kho From newsfish@newsfish Fri Feb 3 13:12:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Joseph Newsgroups: comp.lang.vhdl Subject: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 00:00:13 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 78.133.124.146 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302678013 17390 127.0.0.1 (13 Apr 2011 07:00:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 07:00:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=78.133.124.146; posting-account=E3caeQkAAAAyJzC8H7b3MNpCrpcqXmGO User-Agent: G2/1.0 Xref: feeder.eternal-september.org comp.lang.vhdl:4930 Hi all, I am synthesizing a well known add-shift multiplication routine. I have the= Multiplier register Q ,an addition register A and a Carry register C (the = carry of the adder) which are concatenated together to give the multiplicat= ion results. For the shifting part I am writing the following code: Q <=3D A(0) & Q(3 downto 1); A <=3D C & A(3 downto 1); That should perform a right shift in both A and Q. This is being done in a = clocked process so registers are being created (that is working). When synt= hesizing using Xilinx and simulating using ISIM the right shift is being pe= rformed but the LSB of Q never has the correct value. Am I coding it incorrectly in Xilinx? Regards, Joseph From newsfish@newsfish Fri Feb 3 13:12:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z7g2000prh.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 04:19:09 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: <0a450894-cc76-4769-be03-c32a169c5f84@z7g2000prh.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302693617 17444 127.0.0.1 (13 Apr 2011 11:20:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 11:20:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z7g2000prh.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4931 On Apr 12, 11:54=A0am, Jonathan Bromley wrote: > On Apr 12, 3:11=A0pm, rickman wrote: > > > > > > so this code: > > > > output <=3D a when sel =3D '0' else b; > > > > is the same as: > > > > process(a, b, sel) > > > begin > > > =A0 if sel =3D '0' then > > > =A0 =A0 output <=3D a; > > > =A0 else > > > =A0 =A0 output <=3D b; > > > =A0 end if; > > > end process; > > > I see one major difference. =A0The process is eight lines of code and > > the concurrent statement is only one. =A0Which do you think is easier t= o > > read and provides fewer opportunities for errors? > > In the interests of civil discussion I'll > temporarily pretend that this stance doesn't > make my blood boil. > > Instead I'll politely point out that, on the > very rare occasions when I really want something > that simple as a standalone thing, then the > concurrent statement is indeed probably better. > Three-state I/O buffers are the best and > commonest example. > > And I'll also politely point out that > decomposing designs into pieces small enough > to represent as concurrent statements makes > each piece trivially easy to understand, but > makes the whole design as comprehensible as > a broken-up jigsaw puzzle. > > Taking a complicated thing and breaking it > into lots of simple pieces doesn't make it > simpler. =A0It simply turns the complicated > thing into a pile of pieces. > -- > Jonathan Bromley Ok Jonathan, take a deep breath. Now, tell me what you *really* feel! I think if you read my post again, you will see that all I am saying is that the above code is much simpler written as one line of concurrent code than eight lines of process. I'm not espousing a philosophy or promoting anything about a standard practice. I'm just saying that the two code examples do exactly the same thing and one is *much* simpler than the other. What exactly did you think was in my post that I am not aware of? Rick From newsfish@newsfish Fri Feb 3 13:12:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!dr5g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 04:28:06 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302694087 17055 127.0.0.1 (13 Apr 2011 11:28:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 11:28:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dr5g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4932 On Apr 12, 2:58=A0pm, Jonathan Bromley wrote: > On Tue, 12 Apr 2011 09:27:39 -0700 (PDT), KJ wrote: > >Based on what devas posted, the 'standalone thing' is all that one can > >guess that devas is interested in for the reasons that were listed. > > I apologize if I confused or misled the OP. =A0My post > was responding to yet another clear description of the > position that states "bugs increase monotonically with > lines of code, therefore anything that locally reduces > the number of lines of code is good". =A0This I regard as > such pernicious nonsense that I will unapologetically > seize on any opportunity to challenge it, especially > if expressed in a way that encourages the decomposition > of designs into absurdly small and meaningless pieces. > > >In this case, there is no 'complicated thing' > >being broken into simpler pieces. > > True. =A0I carefully pointed out that this can happen, in some > very specific situations, and there the shorter description > is entirely appropriate. > > >Your comment though is valid, but should be directed to devas within > >the context of 'hey, why are you spending time thinking about the > >coding of a mux'? > > It could have been, but wasn't; that was not my target. > The OP's question was reasonable, and evinced reasonable > answers; it was the added spin on those answers that > riled me. > -- > Jonathan Bromley I should have read all the posts before I replied to your earlier one. This tells me a bit more, but you are making claims without supporting them. Can you tell me why you believe your position? So far you have simply stated it. Rick M: An argument isn't just contradiction. A: It can be. M: No it can't. An argument is a connected series of statements intended to establish a proposition. A: No it isn't. M: Yes it is! It's not just contradiction. A: Look, if I argue with you, I must take up a contrary position. M: Yes, but that's not just saying 'No it isn't.' A: Yes it is! M: No it isn't! From newsfish@newsfish Fri Feb 3 13:12:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gandalf.srv.welterde.de!weretis.net!feeder4.news.weretis.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!dr5g2000vbb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 05:28:46 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <4a32911a-acd2-452b-817f-80ab1b51981f@dr5g2000vbb.googlegroups.com> References: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302697726 30020 127.0.0.1 (13 Apr 2011 12:28:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 12:28:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dr5g2000vbb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9396) X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4933 On 13 Apr., 09:00, Joseph wrote: > Q <=3D A(0) & Q(3 downto 1); > A <=3D C & A(3 downto 1); > > That should perform a right shift in both A and Q. This is being done in = a clocked process so registers are being created (that is working). When sy= nthesizing using Xilinx and simulating using ISIM the right shift is being = performed but the LSB of Q never has the correct value. This code snipplet has to less information. Actually there are plenty of reasons why a vhdl code simulates different than the synthesis result of this code. Without further information it is not predictabel which reason is your problem. You can not "code it incorrect in Xilinx". But you can easily write vhdl code which has "misleading" simulation result compared to the netlist you get after synthesis independend of the used tools. bye Thomas From newsfish@newsfish Fri Feb 3 13:12:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 06:05:10 -0700 (PDT) Organization: http://groups.google.com Lines: 51 Message-ID: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302699911 21554 127.0.0.1 (13 Apr 2011 13:05:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 13:05:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4934 On Apr 13, 2:03=A0am, "daniel.kho" wrote: > On Apr 13, 4:13=A0am, Andy wrote: > > > For one simple, combinatorial function with one output, I prefer the > > concurrent assignment. > > Yes, for me as well. If a block (or sub-block) seems simple enough to > describe as a one-liner (or a few lines) of concurrent statements, go > for it. If my block/sub-block starts getting a bit more complex, I'll > start putting those concurrent statements within a process instead. > > When it gets difficult to behaviourally describe your functionality > with just a few concurrent statements, and when you start breaking up > a concurrent statement to multiple smaller concurrent statements, > that's when you're beginning to change your behavioural design to a > structural one, i.e. one that doesn't describe the behaviour and > therefore is difficult to understand. When I could foresee that I'm > heading this (wrong) direction, I'll steer myself back to enclose > those statements in a process, and add whatever other functionality I > need. > > Daniel Kho I don't have any grand rules for when I describe combinatorial logic with a process, but it is seldom, mainly because I don't like maintaining the sensitivity list. Mostly the logic I code is included in sequential processes, but there are times when it doesn't make sense from a decomposition point of view to include some of the logic in the sequential process. Then I put it is concurrent statements. A data path mux is a perfect example of that. If the concurrent statements get too complex, I will use a process. I did that for some code controlling a couple of status LEDs. The concurrent logic was getting complex because of multiple modes displaying different status. The muxing was rather complex and hard to understand. In a process the IF statement structure was more clear. But for signal path logic it is often a series arrangement of processing steps. Putting that in a process requires that some of the outputs which feed into the logic for the next step be included in the sensitivity list. I find this rather messy. Otherwise these intermediate values need to be expressed with variables. But variables don't show up in the waveform display, at least in ActiveHDL. So I find variables harder to use in debug and only use them when there is a clear advantage, like in test benches. I've never had any real issues expressing a linear flow in four concurrent statements rather than four sequential statements inside the several lines of code to setup a process. Rick From newsfish@newsfish Fri Feb 3 13:12:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!w6g2000vbo.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Incorrect simulation of a shift register in multiplication Date: Wed, 13 Apr 2011 07:42:56 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: References: <6a57293b-d385-4f19-9d50-f8781d3a95e8@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302705776 20999 127.0.0.1 (13 Apr 2011 14:42:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 14:42:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w6g2000vbo.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4935 Not enough info. Are the other bits getting "correct" values? How can you tell that Q(0) is not getting the "correct" value? (What is the correct value?) Andy From newsfish@newsfish Fri Feb 3 13:12:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w7g2000pre.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 08:24:58 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302708299 15990 127.0.0.1 (13 Apr 2011 15:24:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 15:24:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w7g2000pre.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4936 I think there are two arguments in play here: how to describe combinatorial logic, and whether it needs to be described combinatorially at all. I very rarely need to describe combinatorial logic outside the context of a synchronous process, so that sensitivity lists and latches are rarely a problem. I usually debug source code, not waveforms, so variables not showing up in waveforms would not be a big issue for me, especially compared to the advantages of using variables. Andy From newsfish@newsfish Fri Feb 3 13:12:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!b13g2000prf.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 09:06:26 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> NNTP-Posting-Host: 206.83.242.170 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302710918 12136 127.0.0.1 (13 Apr 2011 16:08:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 16:08:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b13g2000prf.googlegroups.com; posting-host=206.83.242.170; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4937 On Apr 13, 11:24=A0am, Andy wrote: > I think there are two arguments in play here: how to describe > combinatorial logic, and whether it needs to be described > combinatorially at all. > > I very rarely need to describe combinatorial logic outside the context > of a synchronous process, so that sensitivity lists and latches are > rarely a problem. > > I usually debug source code, not waveforms, so variables not showing > up in waveforms would not be a big issue for me, especially compared > to the advantages of using variables. > > Andy Wow, we work so differently. The big difference between HDL and software that I love is the fact that I can access any point in the design with a simulation scope probe to see just what is happening. The few times I have used the code debugging tools I find them to be fairly painful to get to the point of the issue. Maybe I'm just not experienced enough with them. Rick From newsfish@newsfish Fri Feb 3 13:12:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!o21g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 10:05:02 -0700 (PDT) Organization: http://groups.google.com Lines: 55 Message-ID: <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302714302 17198 127.0.0.1 (13 Apr 2011 17:05:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 17:05:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o21g2000prh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4938 On Apr 13, 12:06=A0pm, rickman wrote: > On Apr 13, 11:24=A0am, Andy wrote: > > > I think there are two arguments in play here: how to describe > > combinatorial logic, and whether it needs to be described > > combinatorially at all. > > > I very rarely need to describe combinatorial logic outside the context > > of a synchronous process, so that sensitivity lists and latches are > > rarely a problem. > > > I usually debug source code, not waveforms, so variables not showing > > up in waveforms would not be a big issue for me, especially compared > > to the advantages of using variables. > > > Andy > > Wow, we work so differently. =A0The big difference between HDL and > software that I love is the fact that I can access any point in the > design with a simulation scope probe to see just what is happening. I agree. Debugging the source code implies that you have identified an incorrect behavior (presumably via an assertion or observation of some other 'incorrect' output) AND you have restarted the simulation to get it up near the suspected time of the failure so you can step through or otherwise 'debug the source code'. Not only is restarting the sim wasted time (although maybe it's not a 'lot' of time depending on the particular design) but if you guess incorrectly about the time that the root cause of the failure occurred you may have to restart the sim again...all because there is no equivalent to 'log -r /*' that captures the history of all variables in a design. Debugging with the waveform allows one to easily plop down the entire history of any signal anywhere in the entire design and testbench. The cost is a single command ('log -r /*') and some extra wall clock time and disk space to store the data to disk. Whether or not that extra bit of wall clock time was 'well spent' or not can be user dependent, I've found it to be 'worth it'. Which is 'best', is most likely a very user dependent question. Either way can work. To be efficient at using one method or the other may take time, but in the end I would guess that one can be equally productive either way. If there is a compelling reason for one way versus the other, I haven't heard about it. As a side note, to work around the issue of wanting to use sequential statements (because it more readily conveys the design intent) but need an unclocked signal but don't want to bother with sensitivity lists, there is always the ability to define a function or a procedure and instantiate call that function/procedure out just like a concurrent assignment. You get all of the benefits of sequential statement syntax along with proper checking of inputs (no missing signals in the sensitivity list) and a combinatorial output. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 13 Apr 2011 15:31:08 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1302733967 5454 127.0.0.1 (13 Apr 2011 22:32:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Apr 2011 22:32:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4939 I use waveforms occasionally to get a look at an interface (external or internal) but those are always signals anyway (ports). I use assertions in both the RTL and the testbench which stop the simulation when something goes wrong, then I can observe the variables and signals I need, and insert a few breakpoints and monitors if necessary. Given the cyclical nature of most hardware designs, it is often not necessary to "back up" to see what happened, just catch it again on the next time around. Backing up can be a pain though if I have to. Most of the RTL assertions get put in during design or unit testing, so they are already there by the time I have a larger system simulation that would be time consuming to restart (and that would be severely slowed down by dumping every signal to a file "just in case".) I'm a big proponent of self-checking testbenches, and they don't use waveforms either. Most of us use methods we are most comfortable with, and using waveforms is very similar to the typical test equipment in the lab that we learned on. I started using the source code debugger after working with the SW driver guys to debug HW/SW issues in the lab. I had also taken a couple of Ada courses to sharpen my VHDL, and was exposed to the techniques there. Then I started trying some of those techniques in my VHDL simulations, and it worked well for me. But what works well for me may not work for others. Having multiple examples to accomplish the same thing allows users to find what works best for them individually. Andy From newsfish@newsfish Fri Feb 3 13:12:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 00:04:03 +0100 Organization: A noiseless patient Spider Lines: 89 Message-ID: <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx01.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="20054"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+N0AK5K6tjig8pYjlH+C1Zh8XV2675Nrs=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:wpMS2cQSkfZUIPuLy5Gir+y0Gyo= Xref: feeder.eternal-september.org comp.lang.vhdl:4940 On Wed, 13 Apr 2011 04:28:06 -0700 (PDT), rickman wrote: > you are making claims without >supporting them. Can you tell me why you believe your position? So >far you have simply stated it. OK, let's keep separate things separate. The bit that got my dander up was your implied, but clear, statement that fewer lines of code makes for fewer bugs. Others have stated this much more starkly than you did. I rather strongly disagree with it. Whilst it is evidently true that adding more code to any project will of course increase the number of bugs, since code is rarely bug-free, that in itself provides not a shred of evidence that the implementation of a given set of functionality will have fewer bugs if implemented using coding techniques that result in fewer lines of code. My own experience suggests that very compact, dense coding styles increase the risk of subtle hidden bugs and oversights that are very hard to track down. A more literate coding style generally leads to more easily debugged code. Clearly you can go too far the other way - verbosity for its own sake is unlikely to help, and in particular it is never a good idea to have redundancy in code. But the basic argument that leads to the mantra "code it in fewer characters and you'll get fewer bugs" is groundless, and I'm convinced it has led to misguided choices in the design and application of HDLs. More directly related to what you posted is the question of the most desirable granularity to which you should decompose a problem. I think I was clear enough in my discomfort there. You can always make each piece of a design trivially easy to understand, simply by decomposing it into pieces that are small enough. Is a shift register small enough for you? A flop? A mux? A transistor? The snag is, this simplification comes at an unacceptable price: it hides the real functionality of the design or design fragment. As others have indicated, it's probably unhelpful to lay down rigid guidelines here. I can suggest some touchstones: is the piece of code amenable to testing that will show whether it does what you need it to do, without wasting effort by testing some function such as a mux that's already well-known to work? Can I write a few lines of comment in the code that describe succinctly what it does, and why it's there? Can I relate this fragment to any kind of specification or requirement? The reality, though, is that the optimum choices depend on the people doing the work, the nature of the problem, the customer's demands and a whole pile of other things. Despite all this fence-sitting, there is something that seems obvious to me. Breaking a design into excessively small pieces (transistors!!) clearly obscures its functionality. Leaving a design in huge monolithic chunks (an entire FPGA in one VHDL process!!) is clearly hopeless too; no-one could possibly understand it. Somewhere in the middle there is an optimum - not ideal, but certainly better than either end of that spectrum. Merely saying "simpler is better" is inadequate. For me, pieces of design small enough to write as a single concurrent statement are almost never big enough to give me useful clues about how they contribute to the overall functionality (unless you put a function call in the expression). Sorry about the lengthy ramblings. You did ask for a justification :-) -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 01:18:23 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 195.27.20.17 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302769103 606 127.0.0.1 (14 Apr 2011 08:18:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 08:18:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=195.27.20.17; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4941 On Apr 13, 11:31=A0pm, Andy wrote: > I use waveforms occasionally to get a look at an interface (external > or internal) but those are always signals anyway (ports). I use > assertions in both the RTL and the testbench which stop the simulation > when something goes wrong, then I can observe the variables and > signals I need, and insert a few breakpoints and monitors if > necessary. Given the cyclical nature of most hardware designs, it is > often not necessary to "back up" to see what happened, just catch it > again on the next time around. Backing up can be a pain though if I > have to. Most of the RTL assertions get put in during design or unit > testing, so they are already there by the time I have a larger system > simulation that would be time consuming to restart (and that would be > severely slowed down by dumping every signal to a file "just in > case".) I'm a big proponent of self-checking testbenches, and they > don't use waveforms either. > > Most of us use methods we are most comfortable with, and using > waveforms is very similar to the typical test equipment in the lab > that we learned on. I started using the source code debugger after > working with the SW driver guys to debug HW/SW issues in the lab. I > had also taken a couple of Ada courses to sharpen my VHDL, and was > exposed to the techniques there. Then I started trying some of those > techniques in my VHDL simulations, and it worked well for me. > > But what works well for me may not work for others. Having multiple > examples to accomplish the same thing allows users to find what works > best for them individually. > > Andy I can see where you're coming from andy. Ideally, your final test should be a black box test, with a self checking testbench. It worries me when I see designers stare at waveforms all day and using this for their verification. They should be using output data as the test - no waveforms needed. Working in video I use bitmaps for input and output data. Its so much easier looking at a whole picture than looking at a stream of pixels. Often this output picture gives you a clue as to whats wrong - its normally very obviously when something has gone wrong doing this. Then I can get in amongst the waveform for more specific debugging, using the clues from the output. From newsfish@newsfish Fri Feb 3 13:12:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 09:37:37 +0100 Organization: TRW Conekt Lines: 39 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net WVbF7vCgSRXe1/b9eM7PlQk4YzJMS5+94/zbzuwvch/rzqWHg= Cancel-Lock: sha1:qTYjznHdl1/r6SAUqqq1NxoT5R0= sha1:4WDupvi4GOAA7tnmOWHHd4z+nhw= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4942 Andy writes: > I use waveforms occasionally to get a look at an interface (external > or internal) but those are always signals anyway (ports). I use > assertions in both the RTL and the testbench which stop the simulation > when something goes wrong, then I can observe the variables and > signals I need, and insert a few breakpoints and monitors if > necessary. That's much the same as the methods I use (and even the odd printf^H^H^H^H^H report statement :) I'm sure Aldec can put variables in the wave window - it may be that (as with Modelsim) you have to do it before the sim for it to log them. At the subblock level, adding a few variables and restarting is not usually a killer - especially when you have asserts already in to stop the simulation as soon as things go wrong. (The variables I want to see are usually state variables - it'd be great to be able to do "log -r *state" on variables :) > Most of us use methods we are most comfortable with, and using > waveforms is very similar to the typical test equipment in the lab > that we learned on. I started using the source code debugger after > working with the SW driver guys to debug HW/SW issues in the lab. I > had also taken a couple of Ada courses to sharpen my VHDL, and was > exposed to the techniques there. Then I started trying some of those > techniques in my VHDL simulations, and it worked well for me. And there are times when I'm writing embedded software that I'd really like a waveform trace of my C variables :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:12:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!q40g2000prh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 05:56:36 -0700 (PDT) Organization: http://groups.google.com Lines: 49 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302785796 31242 127.0.0.1 (14 Apr 2011 12:56:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 12:56:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q40g2000prh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4943 On Apr 14, 4:18=A0am, Tricky wrote: > On Apr 13, 11:31=A0pm, Andy wrote: > > Ideally, your final test > should be a black box test, with a self checking testbench. It worries > me when I see designers stare at waveforms all day and using this for > their verification. They should be using output data as the test - no > waveforms needed. Just to be clear, I'm not talking about using waveforms for verification. What they are used for is investigation when the verification assertion fails...after all, one does not intentionally write bad code in the first place so the fact that an assertion has failed implies there is a problem somewhere that needs investigating. If the root cause of the problem (which you do not know a priori) happens to have occurred at the same time as the assertion (which is a symptom, not the problem itself), then one will have access to the *current* state of all signals and variables. Maybe that's enough to solve the problem, but many times one needs to see some history in addition to the current state of signals and variables in order to make the definitive diagnosis. By Andy's own admission he does not solve the current problem but typically can wait for the problem to occur again after the first time - "just catch it again on the next time around" - "and insert a few breakpoints and monitors if necessary" (implies running the sim s'more) Sometimes (maybe many times) that is sufficient. But it is just as likely that whatever the original problem that caused the first assertion, if you continue running the sim, has now caused a second downstream problem that just makes it more difficult because the symptoms of this secondary problem is less directly related to the original problem. Even the software guys write out a trace log file which captures important (to them) information about events that happen. They don't simply capture the current state of everything at the point of the failure...the history of what leads up to the problem is generally the key to solving the problem. The fact that this history gets stored in a file that is viewable as signals in a sim tool and not as a list of statement executions is not relevant and has nothing to do with 'source code debugging'. It means you're making use of the tools that are available. Not using the history that is available to you is a choice and has a cost, but that choice is not about 'source code debugging' versus 'waveform debugging' Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!matrix.darkstorm.co.uk!news-transit.tcx.org.uk!feeder.news-service.com!postnews.google.com!r35g2000prj.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 10:34:15 -0700 (PDT) Organization: http://groups.google.com Lines: 55 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302802979 31174 127.0.0.1 (14 Apr 2011 17:42:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 17:42:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r35g2000prj.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4944 On Apr 14, 4:18=A0am, Tricky wrote: > On Apr 13, 11:31=A0pm, Andy wrote: > > > > > I use waveforms occasionally to get a look at an interface (external > > or internal) but those are always signals anyway (ports). I use > > assertions in both the RTL and the testbench which stop the simulation > > when something goes wrong, then I can observe the variables and > > signals I need, and insert a few breakpoints and monitors if > > necessary. Given the cyclical nature of most hardware designs, it is > > often not necessary to "back up" to see what happened, just catch it > > again on the next time around. Backing up can be a pain though if I > > have to. Most of the RTL assertions get put in during design or unit > > testing, so they are already there by the time I have a larger system > > simulation that would be time consuming to restart (and that would be > > severely slowed down by dumping every signal to a file "just in > > case".) I'm a big proponent of self-checking testbenches, and they > > don't use waveforms either. > > > Most of us use methods we are most comfortable with, and using > > waveforms is very similar to the typical test equipment in the lab > > that we learned on. I started using the source code debugger after > > working with the SW driver guys to debug HW/SW issues in the lab. I > > had also taken a couple of Ada courses to sharpen my VHDL, and was > > exposed to the techniques there. Then I started trying some of those > > techniques in my VHDL simulations, and it worked well for me. > > > But what works well for me may not work for others. Having multiple > > examples to accomplish the same thing allows users to find what works > > best for them individually. > > > Andy > > I can see where you're coming from andy. Ideally, your final test > should be a black box test, with a self checking testbench. It worries > me when I see designers stare at waveforms all day and using this for > their verification. They should be using output data as the test - no > waveforms needed. Working in video I use bitmaps for input and output > data. Its so much easier looking at a whole picture than looking at a > stream of pixels. Often this output picture gives you a clue as to > whats wrong - its normally very obviously when something has gone > wrong doing this. Then I can get in amongst the waveform for more > specific debugging, using the clues from the output. I agree that verification is best done by the code and not by viewing waveforms. In fact, sometimes I think that my project is actually a matter of debugging the test bench and the FPGA design being verified is just a side effect! The importance of proper verification is drummed into me every time I don't do it. Just like the time they omitted an unnecessary test on the Hubble Space Telescope. Rick From newsfish@newsfish Fri Feb 3 13:12:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!nx02.iad01.newshosting.com!newshosting.com!novia!news-out.readnews.com!transit3.readnews.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 10:49:23 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302803364 9744 127.0.0.1 (14 Apr 2011 17:49:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 17:49:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4945 On Apr 14, 4:37=A0am, Martin Thompson wrote: > Andy writes: > > I use waveforms occasionally to get a look at an interface (external > > or internal) but those are always signals anyway (ports). I use > > assertions in both the RTL and the testbench which stop the simulation > > when something goes wrong, then I can observe the variables and > > signals I need, and insert a few breakpoints and monitors if > > necessary. > > That's much the same as the methods I use (and even the odd printf^H^H^H^= H^H > report statement :) =A0 > > I'm sure Aldec can put variables in the wave window - it may be that (as = with > Modelsim) you have to do it before the sim for it to log them. =A0At the = subblock > level, adding a few variables and restarting is not usually a killer - es= pecially > when you have asserts already in to stop the simulation as soon as things= go > wrong. Please show me how to do this. I have added variables to the waveform window until I was blue in the face and their values never show up. It makes some sense. Variables are not defined outside of the process, function or procedure and in many cases do not retain a value between invocations. So what would be displayed? I add variables by selecting them in the source file, right clicking and selecting "Add to waveform". But I can do this with anything in the design including VHDL keywords, so being able to add it to the waveform display doesn't mean anything. If I set a breakpoint and single step, I can see the variables in the Call Stack window and watch them change. But they never show up in the waveform. That further makes sense since a variable can change value several times with no time ticking off. How would you display that in a time based waveform? > (The variables I want to see are usually state variables - it'd be great > to be able to do "log -r *state" on variables :) > > > Most of us use methods we are most comfortable with, and using > > waveforms is very similar to the typical test equipment in the lab > > that we learned on. I started using the source code debugger after > > working with the SW driver guys to debug HW/SW issues in the lab. I > > had also taken a couple of Ada courses to sharpen my VHDL, and was > > exposed to the techniques there. Then I started trying some of those > > techniques in my VHDL simulations, and it worked well for me. > > And there are times when I'm writing embedded software that I'd really li= ke a > waveform trace of my C variables :) Too bad they don't have signals in C... Sometimes I turn variables into signals by outputting them on pins which can be displayed as waveforms by a logic analyzer. ;^) Rick From newsfish@newsfish Fri Feb 3 13:12:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z27g2000prz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 14 Apr 2011 11:12:45 -0700 (PDT) Organization: http://groups.google.com Lines: 102 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302804766 23978 127.0.0.1 (14 Apr 2011 18:12:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Apr 2011 18:12:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z27g2000prz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4946 On Apr 13, 7:04=A0pm, Jonathan Bromley wrote: > On Wed, 13 Apr 2011 04:28:06 -0700 (PDT), rickman wrote: > > you are making claims without > >supporting them. =A0Can you tell me why you believe your position? =A0So > >far you have simply stated it. > > OK, let's keep separate things separate. > > The bit that got my dander up was your implied, but > clear, statement that fewer lines of code makes for > fewer bugs. =A0 Mistake #1. I didn't say that and you inferred rather than my implying it. "Which do you think is easier to read and provides fewer opportunities for errors?" I was comparing the two sets of code, not making a general statement. ...snipped resulting conclusions... > More directly related to what you posted > is the question of the most desirable > granularity to which you should decompose > a problem. =A0 At least here you don't say that I made a statement about granularity. This is your topic. I'm not even clear on how this issue results from the OP's post. I do see how it relates to a wider conversation about coding in general, but not how it connects to me or my post. What did I write in regards to this? ...snip resulting discussion... > Despite all this fence-sitting, there is > something that seems obvious to me. =A0 > Breaking a design into excessively small > pieces (transistors!!) clearly obscures > its functionality. =A0Leaving a design in > huge monolithic chunks (an entire FPGA > in one VHDL process!!) is clearly hopeless > too; no-one could possibly understand it. > Somewhere in the middle there is an > optimum - not ideal, but certainly better > than either end of that spectrum. =A0Merely > saying "simpler is better" is inadequate. I don't agree that any of the three approaches is the "right" one. Rather to understand the design you need to understand as many levels as are important to the design. Typically there are parts of an HDL design that I want to see from the 10,000 m view, some I want to see from 10 m, some while sitting in front of it and some I want to see with a microscope. It all depends on which parts are standard, straightforward stuff and which parts are doing something more complex that needs to be explained more clearly. There are many times I use concurrent code because adding it to a process adds nothing to the clarity. It is still an assignment, but now, for example, a data path mux is obscured by all the control logic statements or vice versa. But mostly I just don't use combinatorial processes except for exceptions where it makes the code more clear. > For me, pieces of design small enough to > write as a single concurrent statement are > almost never big enough to give me useful > clues about how they contribute to the > overall functionality (unless you put a > function call in the expression). I'm curious, how do you write, for example, a data path mux if you don't put it in a concurrent statement? Do you lump it in with unrelated stuff? I had a design for a mulaw encoder with two sources, the data from the CODEC and a tone generator as well as a mute function. I added the data path mux (with mute function) using a combinatorial statement because to me it was not part of the mulaw logic so I didn't want to put it in the process for the mulaw logic. In fact, all of the data path to connect the mulaw logic with the CODEC and the IP interface was concurrent statements, some just simple assignments with no logic to connect wires... er, I mean signals. Can you tell I've been working with Verilog lately? What would you have done differently? Funny, I think is was one time I used variables for the mulaw encoding because that seemed like the right way to go given that it was all combinatorial and required several sequential steps. It also translated easier from the C code I used as a reference. It had it's own test bench so debugging with variables was not really an issue. > Sorry about the lengthy ramblings. =A0You > did ask for a justification :-) Yup, be careful what you ask for... ;^) You are always good for some interesting perspectives. Thanks. Rick From newsfish@newsfish Fri Feb 3 13:12:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 09:02:46 +0100 Organization: TRW Conekt Lines: 37 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net MpO7cc2mo02erF6ZjQyPqwV2QhHZ2eP2Vw7r63OlN8eOceUwg= Cancel-Lock: sha1:phWCIygQkcPKKJKNMuZvmce+RNg= sha1:EJU91+IoweAbjnSofSZLRI0ruBo= User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.1 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:4947 rickman writes: > Please show me how to do this. I have added variables to the waveform > window until I was blue in the face and their values never show up. > It makes some sense. Variables are not defined outside of the > process, function or procedure and in many cases do not retain a value > between invocations. So what would be displayed? I'm not an Aldec user, but on a brief perusal of the manual, I can't see how to do it either :( How disappointing! > If I set a breakpoint and single step, I can see the variables in the > Call Stack window and watch them change. But they never show up in > the waveform. That further makes sense since a variable can change > value several times with no time ticking off. How would you display > that in a time based waveform? Modelsim shows the value at the end of the process - effectively it wires it to a signal at the end of the process and displays that. >> And there are times when I'm writing embedded software that I'd really like a >> waveform trace of my C variables :) > > Too bad they don't have signals in C... Sometimes I turn variables > into signals by outputting them on pins which can be displayed as > waveforms by a logic analyzer. ;^) > Yep, BTDT too :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:12:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!gu8g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 07:16:30 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> NNTP-Posting-Host: 192.31.106.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302876990 5222 127.0.0.1 (15 Apr 2011 14:16:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 14:16:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gu8g2000vbb.googlegroups.com; posting-host=192.31.106.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4948 On Apr 14, 1:12=A0pm, rickman wrote: > I'm curious, how do you write, for example, a data path mux if you > don't put it in a concurrent statement? =A0Do you lump it in with > unrelated stuff? =A0I had a design for a mulaw encoder with two sources, > the data from the CODEC and a tone generator as well as a mute > function. =A0I added the data path mux (with mute function) using a > combinatorial statement because to me it was not part of the mulaw > logic so I didn't want to put it in the process for the mulaw logic. > In fact, all of the data path to connect the mulaw logic with the > CODEC and the IP interface was concurrent statements, some just simple > assignments with no logic to connect wires... er, I mean signals. =A0Can > you tell I've been working with Verilog lately? > > What would you have done differently? > It depends... How is the datapath (mux) controlled? Is it some external control, or is it a mode within the encoder? If the encoder has a requirement that under certain internal modes or conditions, it needs to load data from a different source, then I generally code that behavior into the encoder. On the other hand, if something external is directly controlling the source of the data, then I might break that functionality out into a separate mux. And if that mux was the only thing related to that control, I might even make it a concurrent statement. The focus is more about the function than it is about the circuit that will implement the function. Think of the function not as a mux but as a choice of which data to load. Then asks questions like "who/what determines (not implements) the choice?" The answer will often lead to the appropriate coding. Also, a functional approach will more often lead to closer coupling between that code and the requirements documents for that code. Good requirements don't usually include "shall have a mux to select data...," but more like "shall load different data based on..." Andy From newsfish@newsfish Fri Feb 3 13:12:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!noris.net!diablo2.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.69.MISMATCH!feeder.news-service.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: Peter Spjuth Newsgroups: comp.lang.vhdl Subject: Re: Is this a VHDL limitation, or Modelsim bug Date: Fri, 15 Apr 2011 11:20:40 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <1b282dd8-c48a-4f03-91c5-7a9f741abec9@dn9g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 62.119.43.195 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302891641 26163 127.0.0.1 (15 Apr 2011 18:20:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 18:20:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=62.119.43.195; posting-account=jm7q0goAAADpwFe3cgIgpxo53RNop6k7 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4949 On 11 Apr, 14:37, Tricky wrote: > I have the following line of code: > > img_height =A0 =A0 =A0 =A0 =A0 =A0 =A0:=3D ( img.get_image )'length(1); I think ' must be preceeded by a name or function call, and in your case it is preceeded by a parenthesised expression. Does img.get_image'length(1) or img.get_image()'length(1) work? /Peter From newsfish@newsfish Fri Feb 3 13:12:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!k36g2000vbr.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 15 Apr 2011 16:25:46 -0700 (PDT) Organization: http://groups.google.com Lines: 63 Message-ID: <14af7c89-4b3a-4618-93a6-0cac48f0873e@k36g2000vbr.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> NNTP-Posting-Host: 65.201.150.158 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302909946 24758 127.0.0.1 (15 Apr 2011 23:25:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Apr 2011 23:25:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k36g2000vbr.googlegroups.com; posting-host=65.201.150.158; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4950 On Apr 15, 10:16=A0am, Andy wrote: > On Apr 14, 1:12=A0pm, rickman wrote: > > > I'm curious, how do you write, for example, a data path mux if you > > don't put it in a concurrent statement? =A0Do you lump it in with > > unrelated stuff? =A0I had a design for a mulaw encoder with two sources= , > > the data from the CODEC and a tone generator as well as a mute > > function. =A0I added the data path mux (with mute function) using a > > combinatorial statement because to me it was not part of the mulaw > > logic so I didn't want to put it in the process for the mulaw logic. > > In fact, all of the data path to connect the mulaw logic with the > > CODEC and the IP interface was concurrent statements, some just simple > > assignments with no logic to connect wires... er, I mean signals. =A0Ca= n > > you tell I've been working with Verilog lately? > > > What would you have done differently? > > It depends... How is the datapath (mux) controlled? Is it some > external control, or is it a mode within the encoder? If the encoder > has a requirement that under certain internal modes or conditions, it > needs to load data from a different source, then I generally code that > behavior into the encoder. On the other hand, if something external is > directly controlling the source of the data, then I might break that > functionality out into a separate mux. And if that mux was the only > thing related to that control, I might even make it a concurrent > statement. The mux is controlled by configuration register settings in a different module, but also has a real time Left/Right control. Really the mux is completely independent of the mulaw encode/decode. I wrote that up as a independent, reusable module and instantiate it. > The focus is more about the function than it is about the circuit that > will implement the function. Think of the function not as a mux but as > a choice of which data to load. Then asks questions like "who/what > determines (not implements) the choice?" The answer will often lead to > the appropriate coding. Also, a functional approach will more often > lead to closer coupling between that code and the requirements > documents for that code. Good requirements don't usually include > "shall have a mux to select data...," but more like "shall load > different data based on..." Yes, exactly. Many of these independent functions that can be made peripheral to a given function are coded as concurrent statements. But there are times when I use concurrent signals to support easier debugging. I don't recall the exact portion of the design, but I had another function in this same design that was largely arithmetic. To facilitate debugging I coded each step as concurrent so that each intermediate value was a signal. Even if Active HDL would display variables, they can't really be viewed properly if they are not updated in a signal like manner. How do you view a sum of products when it is updated in a loop as a variable? It all happens in one instant in time when viewed in a waveform. Yes, you can use breakpoints and such, but that is a separate issue. Maybe there are things I can learn about this. I'll give code debugging (vs waveform debugging) another try next time I code up some HDL. Rick From newsfish@newsfish Fri Feb 3 13:12:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!m23g2000prl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Sat, 16 Apr 2011 08:41:53 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <5104832b-bb2a-4e9b-8a7c-94a36bd50d3a@l30g2000vbn.googlegroups.com> <189cq696tsvgelcrlhtbbbqq55krr9or8g@4ax.com> <548bc40d-239e-4d2a-bc3c-7c9186d4d711@gu8g2000vbb.googlegroups.com> <14af7c89-4b3a-4618-93a6-0cac48f0873e@k36g2000vbr.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1302968514 25965 127.0.0.1 (16 Apr 2011 15:41:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 16 Apr 2011 15:41:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m23g2000prl.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4951 On Apr 15, 7:25=A0pm, rickman wrote: > > Maybe there are things I can learn about this. =A0I'll give code > debugging (vs waveform debugging) another try next time I code up some > HDL. > Just curious here... - Would you turn off your monitor and use a speech synthesizer to read what is on your display to you? - Do you close the source window (and not view the source code via an editor) when you're debugging HDL designs today? Presuming the answer to these questions is 'no', then what do you think is to be gained by not using information that is currently available to you? Do you think you would be more productive? If so, can you explain why? I'm making the assumption with these question that when you say "I'll give code debugging (vs waveform debugging) another try" that this would mean, among other things, not displaying waveforms, instead using only the source code window and their tools. Which leads to the questions above about why you think it would be better to not use information that is available to solve the problem at hand. But of course, based on your postings, you seem a bit more practical than that and the reality is that you probably mean that you would try supplementing using waveforms with source code tools such as breakpoints and single stepping and such. On that premise... - If a problem occurs, do you typically try to solve it by waiting for it to happen again? - Even if, in your experience, it has turned out that 'waiting for it to happen again' will not usually mask the true problem and allows you to fix the problem, do you think that is a good methodology? - When you've solved problems in the past, are you always (or almost always) able to solve it using no other information than what is currently available right now? Looking only at present signal and variable values at the time of the failure, with no history of what led up to the event other that what you must infer by knowledge of the design and must retain in your head (or perhaps scribbled down on paper) since there is no history that can be displayed? Presumably the answer to all of these questions is also 'no' which suggests that making use of information that is readily available in whatever form would be a 'good thing' that most anyone with experience would make use of when solving the problem at hand...which then brings us around to the wrap up... Othen than if you've measured and found that logging signal activity to the disk during sim to be too high of a cost, then there really is no rationale to saying "code debugging vs waveform debugging". I'm not trying to slam you or anyone here on methods, being proficient in using source code tools is not a handicap. But those source code tools can only be applied to events *after* the bad thing has happened, they are of no help in diagnosing what has *already* ocurred short of restarting the sim (i.e. turning back the clock) so you must live with that limitation and work around it. Source code tools do allow you to step through and watch things unfold...but that would be using those tools for verification rather than debug....personally, I prefer testbenches for that task. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!z37g2000vbl.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 02:57:44 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303207064 12634 127.0.0.1 (19 Apr 2011 09:57:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 09:57:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z37g2000vbl.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4952 On Apr 15, 9:02=A0am, Martin Thompson wrote: > rickman writes: > > > > > Please show me how to do this. =A0I have added variables to the wavefor= m > > window until I was blue in the face and their values never show up. > > It makes some sense. =A0Variables are not defined outside of the > > process, function or procedure and in many cases do not retain a value > > between invocations. =A0So what would be displayed? > > I'm not an Aldec user, but on a brief perusal of the manual, I can't see = how to > do it either :( =A0How disappointing! =A0 > IIRC, compiling with the debug flag (acom -dbg) will allow variables to be traced in the same way as signals. From newsfish@newsfish Fri Feb 3 13:12:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!cs.uu.nl!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!feeder.news-service.com!postnews.google.com!hd10g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 08:01:13 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <0fd7924c-19eb-4fd0-a099-4f056ffcab3a@p16g2000vbi.googlegroups.com> <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303225273 3759 127.0.0.1 (19 Apr 2011 15:01:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 15:01:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hd10g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4953 On Apr 19, 5:57=A0am, Chris Higgs wrote: > On Apr 15, 9:02=A0am, Martin Thompson wrote: > > > rickman writes: > > > > > > > Please show me how to do this. =A0I have added variables to the wavef= orm > > > window until I was blue in the face and their values never show up. > > > It makes some sense. =A0Variables are not defined outside of the > > > process, function or procedure and in many cases do not retain a valu= e > > > between invocations. =A0So what would be displayed? > > > I'm not an Aldec user, but on a brief perusal of the manual, I can't se= e how to > > do it either :( =A0How disappointing! =A0 > > IIRC, compiling with the debug flag (acom -dbg) will allow variables > to be traced in the same way as signals. I use the GUI and in checking the preferences I see the compiler option "Enable Debug" is checked. Is that what you mean? I'm still not able to view variable as waveforms. Rick From newsfish@newsfish Fri Feb 3 13:12:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!e26g2000vbz.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 08:25:56 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303226757 18947 127.0.0.1 (19 Apr 2011 15:25:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 15:25:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e26g2000vbz.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4954 On Apr 19, 4:01=A0pm, rickman wrote: > I use the GUI and in checking the preferences I see the compiler > option "Enable Debug" is checked. =A0Is that what you mean? =A0I'm still > not able to view variable as waveforms. > > Rick Using Riviera-PRO on Linux (YMMV on other Aldec simulators/platforms) View->Debug Windows enable Hierarchy Viewer (shortcut alt + 5) and Object Viewer (alt + 6) After elaboration, navigate to the appropriate process and the variables declared by that process will show up in Object Viewer. Right click->Add to->Waveform. Alternatively use the command "wave sim:/path/to/your/process/ variable" From newsfish@newsfish Fri Feb 3 13:12:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.linkpendium.com!news.linkpendium.com!feeder1.hal-mli.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!bl1g2000vbb.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Tue, 19 Apr 2011 11:34:59 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303238100 5356 127.0.0.1 (19 Apr 2011 18:35:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Apr 2011 18:35:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: bl1g2000vbb.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4955 On Apr 19, 11:25=A0am, Chris Higgs wrote: > On Apr 19, 4:01=A0pm, rickman wrote: > > > I use the GUI and in checking the preferences I see the compiler > > option "Enable Debug" is checked. =A0Is that what you mean? =A0I'm stil= l > > not able to view variable as waveforms. > > > Rick > > Using Riviera-PRO on Linux (YMMV on other Aldec simulators/platforms) > > View->Debug Windows enable Hierarchy Viewer (shortcut alt + 5) and > Object Viewer (alt + 6) > > After elaboration, navigate to the appropriate process and the > variables declared by that process will show up in Object Viewer. > Right click->Add to->Waveform. > > Alternatively use the command "wave sim:/path/to/your/process/ > variable" My UI is not the same, but in the process of messing about with it to see if it comes close to yours, I found how to do it. The Design Browser sounds like it is similar to your Hierarchy Viewer. Once I select the appropriate process the variables are available to add to the waveform. It seems odd that I can add signals to the waveform display from the source file, but not variables. This will help with debugging variables, but it still does not supplant the Call Stack and breakpoints because variables update in zero time and so waveforms won't show everything that happens with them. Rick From newsfish@newsfish Fri Feb 3 13:12:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!r6g2000vbz.googlegroups.com!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 06:16:39 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> References: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> NNTP-Posting-Host: 85.115.54.180 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303305399 13643 127.0.0.1 (20 Apr 2011 13:16:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 13:16:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r6g2000vbz.googlegroups.com; posting-host=85.115.54.180; posting-account=g6RVrQoAAADU94cPK8lEZp9Ncbnf7mAt User-Agent: G2/1.0 X-HTTP-Via: 1.1 webdefence.global.blackspider.com:8081 WebDefence 4.3.3 (16832) 18j X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.0.5) Gecko/2008120122 Firefox/3.0.5 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4956 On Apr 19, 7:34=A0pm, rickman wrote: [variables in the wave view] > will help with debugging variables, but it still does not > supplant the Call Stack and breakpoints because variables update in > zero time and so waveforms won't show everything that happens with > them. But this is a red herring. Waveforms can't show everything that happens with signals, either. A signal's driver can be updated many times in a given delta cycle, and only the last such update will actually affect the signal in the upcoming delta. (Of course the story isn't even that simple in the general case, but for zero-delay RTL code it's close.) You can't see these driver updates unless you watch the code executing. I know, of course, that people tend to do more complicated things with variables than they do with repeated assignment to signals, so the problem may be more severe with variables in practice. But there isn't much difference in principle. The truth is that we EEs have grown accustomed to a level of visibility of our code's activity that makes little sense to software people, for whom invisible variables are a matter of routine. We get that visibility only because almost all the objects whose values we care about are static and can be traced/dumped easily as a function of simulation time. As soon as you start to do anything interesting and software-like, you can't do that quite so easily and it becomes much more important to be able to trace code execution - there's no shortage of ways to do it. Better still is to be able to reason about your code so that you can think your way through the offending code's behaviour to see where you messed-up. For me, a great way to achieve that is to add plenty of assertions; figuring out how to write the assertions is a powerful encouragement to think rigorously about your code, and if you find you *can't* write assertions that make sense, it's a fair bet that the code in question isn't properly designed. And well- written assertions often find the cause of an error long before its effect would be visible in waves. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:12:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!news2.glorb.com!postnews.google.com!y31g2000vbp.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 09:40:07 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303317607 5367 127.0.0.1 (20 Apr 2011 16:40:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 16:40:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y31g2000vbp.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4957 On Apr 19, 11:25=A0am, Chris Higgs wrote: > > After elaboration, navigate to the appropriate process and the > variables declared by that process will show up in Object Viewer. > Right click->Add to->Waveform. > > Alternatively use the command "wave sim:/path/to/your/process/ > variable" When you do that, does it show the entire history of the variable from t=3D0 until t=3Dnow? Or does it only allow you to see the variable from t=3Dnow until t=3Dfuture? KJ From newsfish@newsfish Fri Feb 3 13:12:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!w36g2000vbi.googlegroups.com!not-for-mail From: Chris Higgs Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 10:04:36 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <1db3c2a3-32e1-437b-80e3-c1ae3743bbd7@w36g2000vbi.googlegroups.com> References: <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> NNTP-Posting-Host: 208.51.93.163 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303319076 29598 127.0.0.1 (20 Apr 2011 17:04:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 17:04:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w36g2000vbi.googlegroups.com; posting-host=208.51.93.163; posting-account=LPuS2AoAAACOlBiX484DtwbhdfTS9K3L User-Agent: G2/1.0 X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.7.62 Version/11.00,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4958 On Apr 20, 5:40=A0pm, KJ wrote: > > Alternatively use the command "wave sim:/path/to/your/process/ > > variable" > > When you do that, does it show the entire history of the variable from > t=3D0 until t=3Dnow? =A0Or does it only allow you to see the variable fro= m > t=3Dnow until t=3Dfuture? The variable is traced from t=3Dnow onwards (this is the same behaviour as tracing signals). Recording everything in the database in case you want to retrospectively view it (to allow t=3D0 until t=3Dnow) sounds expensive! There may be an option to do that but I've never needed it - I trace whatever signals/variables (using wildcards) before starting the simulation. From newsfish@newsfish Fri Feb 3 13:12:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!l30g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 12:23:15 -0700 (PDT) Organization: http://groups.google.com Lines: 33 Message-ID: <5f78136b-c633-4e19-987d-b5333b0101d9@l30g2000vbn.googlegroups.com> References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <5d35ecd2-ebfa-4dc9-b08c-ab9a601099cc@y31g2000vbp.googlegroups.com> <1db3c2a3-32e1-437b-80e3-c1ae3743bbd7@w36g2000vbi.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303327395 18804 127.0.0.1 (20 Apr 2011 19:23:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Apr 2011 19:23:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l30g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.6; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4959 On Apr 20, 1:04=A0pm, Chris Higgs wrote: > On Apr 20, 5:40=A0pm, KJ wrote: > > > > Alternatively use the command "wave sim:/path/to/your/process/ > > > variable" > > > When you do that, does it show the entire history of the variable from > > t=3D0 until t=3Dnow? =A0Or does it only allow you to see the variable f= rom > > t=3Dnow until t=3Dfuture? > > The variable is traced from t=3Dnow onwards (this is the same behaviour > as tracing signals). Recording everything in the database in case you > want to retrospectively view it (to allow t=3D0 until t=3Dnow) sounds > expensive! There may be an option to do that but I've never needed it OK, good to know. For Modelsim, the 'log -r /*' logs all signals to disk (one can also be more specific about which signals if one chooses). I agree it *seems* like it should be expensive, but I haven't really found that to be the case. Then when I need a signal for debug it can be added to the wave window and the entire history is displayed. Having the entire history of every signal available to be waved is mighty handy. > - I trace whatever signals/variables (using wildcards) before starting > the simulation. Since I don't generally know what assertion will fail ahead of time, I don't know what signals I would be interested in prior to starting the simulation. I dislike restarting and re-running simulations because I guessed wrong about which signals I might want. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!postnews.google.com!32g2000vbe.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 17:58:10 -0700 (PDT) Organization: http://groups.google.com Lines: 91 Message-ID: References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303347490 20704 127.0.0.1 (21 Apr 2011 00:58:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Apr 2011 00:58:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 32g2000vbe.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4960 On Apr 20, 9:16=A0am, Jonathan Bromley wrote: > On Apr 19, 7:34=A0pm, rickman wrote: > > [variables in the wave view] > > > will help with debugging variables, but it still does not > > supplant the Call Stack and breakpoints because variables update in > > zero time and so waveforms won't show everything that happens with > > them. > > But this is a red herring. =A0Waveforms can't show > everything that happens with signals, either. > > A signal's driver can be updated many times in a > given delta cycle, and only the last such update > will actually affect the signal in the upcoming > delta. =A0(Of course the story isn't even that > simple in the general case, but for zero-delay > RTL code it's close.) =A0You can't see these driver > updates unless you watch the code executing. I think you misrepresent what happens with a signal. Although many assignments can be made to a signal, it is never updated until the process reaches a stopping point, either a wait or the end of the process. Only then is the value of the signal updated. You may feel this is semantics, but the point is that I don't care about assignments that don't impact the value of the signal, the intention of the code is for them to be ignored. A variable is different. It is updated just like a variable in software where each intermediate value can be significant. If I can't see those intermediate values, I have lost information about the process which can make it harder to debug. Perhaps there is value in single stepping multiple assignments to a signal if you want to debug the code making those assignments. But the way I write code this is seldom and issue. About the only time I have multiple assignments to a signal in a process is when I first assign a default value and later assign another value in specific instances. This is not complex to debug and does not require single stepping or breakpoints. Waveform viewing works just fine for that. > I know, of course, that people tend to do more > complicated things with variables than they do > with repeated assignment to signals, so the > problem may be more severe with variables in > practice. =A0But there isn't much difference > in principle. In theory, theory and practice are the same; in practice they can differ considerably. The reality is that I very seldom use breakpoints and single stepping to debug signals. My logic design methods are easy to debug using waveforms. I don't see any reason to make that more complex than it is. > The truth is that we EEs have grown accustomed > to a level of visibility of our code's activity > that makes little sense to software people, for > whom invisible variables are a matter of routine. > We get that visibility only because almost all > the objects whose values we care about are static > and can be traced/dumped easily as a function of > simulation time. =A0As soon as you start to do > anything interesting and software-like, you > can't do that quite so easily and it becomes > much more important to be able to trace code > execution - there's no shortage of ways to do it. > > Better still is to be able to reason about your > code so that you can think your way through the > offending code's behaviour to see where you > messed-up. =A0For me, a great way to achieve that > is to add plenty of assertions; figuring out > how to write the assertions is a powerful > encouragement to think rigorously about your > code, and if you find you *can't* write assertions > that make sense, it's a fair bet that the code > in question isn't properly designed. =A0And well- > written assertions often find the cause of an > error long before its effect would be visible > in waves. > -- > Jonathan Bromley I use assertions in my test benches. I don't use them in my target code. Maybe there are things I can learn about that idea. Rick From newsfish@newsfish Fri Feb 3 13:12:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!c26g2000vbq.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Wed, 20 Apr 2011 19:49:59 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: <3ab7ef8d-af96-4ac7-b4f8-c6301a25f4e1@c26g2000vbq.googlegroups.com> References: <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303354199 24263 127.0.0.1 (21 Apr 2011 02:49:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Apr 2011 02:49:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c26g2000vbq.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB6.6; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4961 On Apr 20, 8:58=A0pm, rickman wrote: > > I use assertions in my test benches. =A0I don't use them in my target > code. =A0Maybe there are things I can learn about that idea. > Assertions should also be placed wherever possible, definitely not restricted to testbench code. What you get then is a self checking design which is even better but usually not as comprehensive as a self checking testbench. Assertions in the design can be thought of as 'better' in that they will be active and checked which each and every instantiation of that widget, not just in the original testbench for the widget. Assertion in the design are usually 'not as comprehensive' in that it is not always practical to compute all of the outputs within the design itself. Interface handshake signal protocols can almost always be checked, the data path might not short of writing a second copy of the code. As an example, if you were to write the code for a JPEG encoder, you would probably be better off validating correct operation by reading files that have been computed by some separate widely used tool that presumably has a few miles under its belt. This type of thing though would best be put into a testbench for the encoder. If you put that form of checking into the encoder than each and every instantiation would have to somehow get the file name inputs through some private interface. In any case, it quickly becomes obvious which things 'could' be checked in the design and which probably should not...and then put those that 'could' be checked into the design so that they will be checked forever and for always. You'll get a more robust design since your self-checking design will catch bugs (or validate correct operation) as that design gets reused in other applications. On the other hand, if you don't develop any reusable widgets, it probably doesn't matter where you put your assertions. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Thu, 21 Apr 2011 20:30:03 -0800 Lines: 28 Message-ID: <91cei7Fi4lU1@mid.individual.net> References: <60f73442-9aad-4b3f-ad87-700c98742872@k30g2000yqb.googlegroups.com> <769560c4-02fe-47fd-a198-1ba8cfabb746@r19g2000prm.googlegroups.com> <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net SOp1dWJFProhzC3IxfSXtgbs1o5fMlPcwLN8lVQZMtr1Vt2ut+ Cancel-Lock: sha1:Fk8vWZXjS95BjL4I4ewlZLlZ9zM= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.15) Gecko/20110303 Lightning/1.0b2 Thunderbird/3.1.9 In-Reply-To: <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:4962 On 4/19/2011 10:34 AM, rickman wrote: > My UI is not the same, but in the process of messing about with it to > see if it comes close to yours, I found how to do it. The Design > Browser sounds like it is similar to your Hierarchy Viewer. Once I > select the appropriate process the variables are available to add to > the waveform. It seems odd that I can add signals to the waveform > display from the source file, but not variables. Not odd at all. Suppose that two processes each had a variable named cnt_v. Since the variables are not the same, the only way to properly label the waves is by process. > This will help with debugging variables, but it still does not > supplant the Call Stack and breakpoints because variables update in > zero time and so waveforms won't show everything that happens with > them. In a synchronous design, the value of the wave is probably the one I want. If I really need to see the "gate by gate" (delta by delta) value, I trace code and break on a variable value. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!z31g2000vbs.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 22 Apr 2011 10:45:55 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <868e5d81-cab8-4d1d-ad1e-984bc284c7a0@z31g2000vbs.googlegroups.com> References: <8612c07b-2dcd-47dd-adfb-5d0075eef3e6@y31g2000vbp.googlegroups.com> <6a1e8f36-334b-40b3-a391-892fd409d333@w7g2000pre.googlegroups.com> <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <91cei7Fi4lU1@mid.individual.net> NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303494355 32077 127.0.0.1 (22 Apr 2011 17:45:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Apr 2011 17:45:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z31g2000vbs.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.0; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4963 On Apr 22, 12:30=A0am, Mike Treseler wrote: > On 4/19/2011 10:34 AM, rickman wrote: > > > My UI is not the same, but in the process of messing about with it to > > see if it comes close to yours, I found how to do it. =A0The Design > > Browser sounds like it is similar to your Hierarchy Viewer. =A0Once I > > select the appropriate process the variables are available to add to > > the waveform. =A0It seems odd that I can add signals to the waveform > > display from the source file, but not variables. > > Not odd at all. > Suppose that two processes > each had a variable named cnt_v. > Since the variables are not the same, > the only way to properly > label the waves is by process. Why wouldn't the tool know which process a variable is in from the source??? Everything else comes from the source... > > This will help with debugging variables, but it still does not > > supplant the Call Stack and breakpoints because variables update in > > zero time and so waveforms won't show everything that happens with > > them. > > In a synchronous design, > the value of the wave is probably the one I want. > If I really need to see the > "gate by gate" (delta by delta) value, > I trace code and break on a variable value. Not delta by delta, but yes, gate by gate flow. That is what I'm saying. You don't get a choice with variables. If you need to see how they are calculated when used for intermediate values you have to trace the code. With signals every time the value changes, it is reflected in the state of the signal in the waveform display and you only need to look at the source once you have found the location of the problem. Of course there is no one size fits all, but waveforms seem to be the best approach for most problems. Rick From newsfish@newsfish Fri Feb 3 13:12:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!r19g2000prm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Conditional signal assignment or process statement Date: Fri, 22 Apr 2011 12:02:08 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <6df5763a-3ae6-4807-baed-7851d9f89739@o21g2000prh.googlegroups.com> <4ad90d26-dd33-47d5-8ad2-2eb7e9cc1651@z37g2000vbl.googlegroups.com> <87be99d5-98ca-43e0-813a-a8785c027988@bl1g2000vbb.googlegroups.com> <894cf72f-66f4-4877-9438-916fdd8870e1@r6g2000vbz.googlegroups.com> <3ab7ef8d-af96-4ac7-b4f8-c6301a25f4e1@c26g2000vbq.googlegroups.com> NNTP-Posting-Host: 192.31.106.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303498928 14462 127.0.0.1 (22 Apr 2011 19:02:08 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Apr 2011 19:02:08 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r19g2000prm.googlegroups.com; posting-host=192.31.106.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4964 On Apr 20, 9:49=A0pm, KJ wrote: > > On the other hand, if you don't develop any reusable widgets, it > probably doesn't matter where you put your assertions. > > Kevin Jennings It is much easier to control the conditions under which an assertion is evaluated when the assertion is inserted into the design (RTL) code. A single concurrent assertion statement can make sure something allways/never happens. Strategically placing a sequential assertion statement inside an existing branch of the code allows specifically targeting that part of the code. And it is easier to access local variables/signals from within their scope. On the other hand, RTL assertions don't do much good when verifying the gate level model! Andy From newsfish@newsfish Fri Feb 3 13:12:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!u12g2000prn.googlegroups.com!not-for-mail From: "PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion" Newsgroups: comp.lang.vhdl Subject: PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion Date: Sun, 24 Apr 2011 23:43:41 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1303713821 8836 127.0.0.1 (25 Apr 2011 06:43:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Apr 2011 06:43:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u12g2000prn.googlegroups.com; posting-host=183.82.117.168; posting-account=qaN5UAoAAAB_4ToMJWe5zHTmrge20E7i User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4965 PSD to XHTML Conversion, PSD to HTML CSS, Joomla, Wordpress, Drupal, CMS, VBULLETIN, PHPBB and includes convert to XHTML like PSD to XHTML, web designing services, logos and banner design, website building, animation,presentations and virtual tours from XHTML Champs.www.xhtmlchamps.com From newsfish@newsfish Fri Feb 3 13:12:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!news2.glorb.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!a19g2000prj.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Can anyone think of a workaround - Ideally I want to pass an access type into an entity (not for synthesis) Date: Mon, 25 Apr 2011 16:42:55 -0700 (PDT) Organization: http://groups.google.com Lines: 25 Message-ID: <50c4ed33-e155-47b1-b2f0-140536a61af6@a19g2000prj.googlegroups.com> References: NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1303774976 19657 127.0.0.1 (25 Apr 2011 23:42:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Apr 2011 23:42:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a19g2000prj.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.0.10 NET_mmhpset ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4966 On Apr 8, 8:12=A0am, Tricky wrote: > Im building a model of a memory interface. The entity mimics the > interface of the normal memory interface with multiple request, > address, ack and data valid lines, one set per channel. Internally I > have a protected type that handles the memory modelling (dynamically > creating memory locations as they are accessed so I dont have a > monstrous 256Mbyte array declared) and another protected that handles > the read queue. > > As this is modelling a memory in a video system, I want to be able to > dump whole images (ie bypassing the whole interface) into memory, for > example if Im only testing the other bits of the design on the read > side of the interface. I have everything I need for reading/writing > bitmaps to specific array types, but I just need to get these arrays > into this entity. > In the past, I have used a separate transaction type of interface to handle this. It was real basic - send a memory word at a time. However, in VHDL-2008, you should be able to access the shared variable of the memory with an external name and use the methods provided by your protected type. Have not tried this application of external names, but I intend to soon. Best, Jim From newsfish@newsfish Fri Feb 3 13:12:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!multikabel.net!newsfeed20.multikabel.net!eweka.nl!lightspeed.eweka.nl!postnews.google.com!a21g2000prj.googlegroups.com!not-for-mail From: "PSD to XHTML Conversion Services and PSD to HTML CSS Conversion Services, PSD to Joomla, Drupal, Wordpress Conversion" Newsgroups: comp.lang.vhdl Subject: Web design services | website designing | hire a website designer | creative web Date: Mon, 25 Apr 2011 21:59:50 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <67364442-7f11-4d7f-afdc-8fc0d04046b0@a21g2000prj.googlegroups.com> NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1303793991 16833 127.0.0.1 (26 Apr 2011 04:59:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 26 Apr 2011 04:59:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a21g2000prj.googlegroups.com; posting-host=183.82.117.168; posting-account=qaN5UAoAAAB_4ToMJWe5zHTmrge20E7i User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4967 web design services, XHTML Conversion Services, Offshore outsourcing web design & SEO Expert Acedezines provides best services for your website design, search engine optimization, web design services, brochure design, flash intro animation, website designing, wordpress themes. From newsfish@newsfish Fri Feb 3 13:12:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.visyn.net!visyn.net!newsfeed.in-ulm.de!not-for-mail From: Steffen Koepf Newsgroups: comp.lang.vhdl Subject: Very fast PWM in Cyclone III FPGA Date: Thu, 28 Apr 2011 18:52:02 +0000 (UTC) Organization: [ posted via ] IN-Ulm Lines: 27 Sender: Steffen Koepf Message-ID: X-Trace: news.in-ulm.de 1B0ECEB31F3E8713D5B79A9C6A5A2A20 User-Agent: tin/pre-1.4-19990805 ("Preacher Man") (UNIX) (Linux/2.6.30.10 (i686)) Xref: feeder.eternal-september.org comp.lang.vhdl:4980 Hello, i need a very fast PWM in a Cyclone III FPGA. If necessary, a Cyclone IV will do it too. I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. At the moment the Cyclone III is running at 400 MHz, which gives at 80 KHz 5000 Steps. I made it to be able to use the falling edge in my PWM- Comparator, too, so i have now 10000 Steps at 80 KHz. But the resolution is still not enough, i would like to have more steps. Using a -6 speed grade Cyclone III would allow 600 MHz, which gives around 15000 Steps. Does one know a way to get even more? Is there a way to use the SERDES LVDS to get a fast PWM? Is it possible to use the PLL to generate higher frequencies and use them for example by ANDing them for 4 sub-steps (two more bits)? Thanks in advance, Steffen From newsfish@newsfish Fri Feb 3 13:12:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!nuzba.szn.dk!pnx.dk!weretis.net!feeder4.news.weretis.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!e25g2000prf.googlegroups.com!not-for-mail From: rich12345 Newsgroups: comp.lang.vhdl Subject: looking for 14 pin flying lead cable Date: Thu, 28 Apr 2011 16:28:39 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <088d1dda-17d1-45f9-8f4b-f74a6fe4ad47@e25g2000prf.googlegroups.com> NNTP-Posting-Host: 71.142.220.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304033319 26174 127.0.0.1 (28 Apr 2011 23:28:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Apr 2011 23:28:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e25g2000prf.googlegroups.com; posting-host=71.142.220.160; posting-account=5kmk9wkAAAB22-WWGK8UTn8vQ5c3EvdQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4981 I found it on diligent website, $4.00 for the part, $8.00 for shipping. Does anyone have a spare that they would sell for a reasonable price? this is the 14pin 2mm for Xilinx PlatformCable USB DLC9LP -r From newsfish@newsfish Fri Feb 3 13:12:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!hd10g2000vbb.googlegroups.com!not-for-mail From: kclo4 Newsgroups: comp.lang.vhdl Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 29 Apr 2011 04:36:59 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <978437ef-5190-4ca1-a79a-15b956cd4af6@hd10g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 192.54.144.229 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304077019 14649 127.0.0.1 (29 Apr 2011 11:36:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Apr 2011 11:36:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hd10g2000vbb.googlegroups.com; posting-host=192.54.144.229; posting-account=SeKPuAoAAAAYDoY2DhCLjM2K04fcGufr User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxy:8080 (squid/2.5.STABLE3) X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4982 On Apr 28, 8:52=A0pm, Steffen Koepf wrote: > Hello, > > i need a very fast PWM in a Cyclone III FPGA. > If necessary, a Cyclone IV will do it too. > > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KH= z > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. > Why don't you use a NCO? you can have resolution under 1Hz > But the resolution is still not enough, i would like to have more steps. > > Using a -6 speed grade Cyclone III would allow 600 MHz, which gives aroun= d > 15000 Steps. > > Does one know a way to get even more? > Is there a way to use the SERDES LVDS to get a fast PWM? > > Is it possible to use the PLL to generate higher frequencies and use them > for example by ANDing them for 4 sub-steps (two more bits)? > > Thanks in advance, > > Steffen From newsfish@newsfish Fri Feb 3 13:12:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!news-transit.tcx.org.uk!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!a19g2000prj.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.lang.vhdl Subject: Re: looking for 14 pin flying lead cable Date: Fri, 29 Apr 2011 08:03:32 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <1275e28b-60f4-4cf4-8ee8-b16a8c2a66f8@a19g2000prj.googlegroups.com> References: <088d1dda-17d1-45f9-8f4b-f74a6fe4ad47@e25g2000prf.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304089433 21710 127.0.0.1 (29 Apr 2011 15:03:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Apr 2011 15:03:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a19g2000prj.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4983 On Apr 28, 4:28=A0pm, rich12345 wrote: > I found it on diligent website, $4.00 for the part, $8.00 for > shipping. > > Does anyone have a spare that they would sell for a reasonable > price? > > this is the 14pin 2mm for Xilinx PlatformCable USB DLC9LP > > -r You say that you can get it from Digilent for $12.00 US delivered. Just how much less does it have to be to be "a reasonable price", and do you think someone is going to send it to you for that? Just wondering, RK From newsfish@newsfish Fri Feb 3 13:12:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Paul Colin Gloster Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog Subject: Re: Anti-benchmarking clauses Date: Sat, 30 Apr 2011 00:50:34 +0000 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx02.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="28317"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ve9DRdQ7bwGDifbdsZBEicJo31GMExv79NjEJ4tFadQ==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <29a0c7f2-b71a-4220-94d2-39cc51df8a82@m7g2000vbq.googlegroups.com> Cancel-Lock: sha1:hL0umTESL7oLy4cdAibaJCOXorM= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:4984 comp.arch.fpga:15369 comp.lang.verilog:3049 Philippe sent on March 8th, 2011: |---------------------------------------------------------------------| |"It was interesting to read some synthesis benchmarking results on | |comp.lang.vhdl last week. I feel it's high time that EDA vendors drop| |the anti-benchmarking clauses from their license agreements: | | | |[..]" | |---------------------------------------------------------------------| Who could feel confident about products which are not subjected to as much scrutiny as benchmarks from the Standard Performance Evaluation Corporation? From newsfish@newsfish Fri Feb 3 13:12:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.mixmin.net!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sun, 01 May 2011 23:49:25 -0500 From: Harrell31Ola Subject: Re: [Help request] VHDL to Graphics Newsgroups: comp.lang.vhdl UserIpAddress: 91.201.66.6 InternalId: f3c1f461-70b2-4d76-9c0f-4d3258bcc8ea References: <4b5df3d7$0$702$5fc30a8@news.tiscali.it> Message-ID: Date: Sun, 01 May 2011 23:49:25 -0500 Lines: 3 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-0QdIq1ESYOPm48jk7dxsTHwVhrX1KlGoHtcglQgUjXpzvmU3CZd/frzXXnOSzHVikltZ0ZwDjQQ+sq7!7KytpzZicF0QFfxHIQakyZ2p4MwZv0ZzmUYo8TLq3BfPdKQHCwiq2+RJkN5wEmZ33XhA09aZcA== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1002 Xref: feeder.eternal-september.org comp.lang.vhdl:4985 freelance writer From newsfish@newsfish Fri Feb 3 13:12:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: [Help request] VHDL to Graphics Date: Sun, 01 May 2011 23:20:31 -0700 Lines: 9 Message-ID: <9270p3F7i0U1@mid.individual.net> References: <4b5df3d7$0$702$5fc30a8@news.tiscali.it> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 3qnJUND+r7ALPFEc+eJkUw+cwD204hvPn99El8kAc7Z/2dRj0L Cancel-Lock: sha1:Ik0SlgjmwjaTNKF8INxDxMgupVQ= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:4986 On 5/1/2011 9:49 PM, Harrell31Ola wrote: > > [Help request] VHDL to Graphics > freelance writer [Answer] Quartus Web Editon, RTL Viewer freelance reader From newsfish@newsfish Fri Feb 3 13:12:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 02:41:23 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304588483 29695 127.0.0.1 (5 May 2011 09:41:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 09:41:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4987 Hi, I am a little surprised that the following code refuses to synthesize (at least with Quartus and Synopsys (Lattice's)): ********************** library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity real_synth is port( a_in: in unsigned(15 downto 0); b_out: out unsigned(15 downto 0) ); end; architecture synth of real_synth is begin process(a_in) variable r: real; begin r := real(to_integer(a_in)); r := r*1.2; if r<0.0 then r := 0.0; elsif r>65535.0 then r := 65535.0; end if; b_out <= to_unsigned(integer(r),16); end process; end; **************************** Ok, I do understand that real values are a problem when they need to be stored, or transported (with signals/ports). But in this case the mapping of a_in => b_out can be evaluated by brute force (by going through all input states, and running the code inside the process for every possible input combination and noting the output values). Upto today I had thought that all synthesizers would fallback to the brute force method if intelligent algorithm generator fails. It seems that I had mistrusted them, though. Any ideas why the synthesizers DO NOT have this brute-force fallback method? - Topi From newsfish@newsfish Fri Feb 3 13:12:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 03:26:29 -0700 (PDT) Organization: http://groups.google.com Lines: 62 Message-ID: References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304591190 2246 127.0.0.1 (5 May 2011 10:26:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 10:26:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4988 On May 5, 10:41=A0am, Topi wrote: > Hi, > > I am a little surprised that the following code refuses to synthesize > (at least with Quartus and Synopsys (Lattice's)): > > ********************** > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > > entity real_synth is > =A0 =A0 =A0 =A0 port( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 a_in: in unsigned(15 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 b_out: out unsigned(15 downto 0) > =A0 =A0 =A0 =A0 ); > end; > > architecture synth of real_synth is > begin > =A0 =A0 =A0 =A0 process(a_in) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r: real; > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D real(to_integer(a_in)); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D r*1.2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r<0.0 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D 0.0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif r>65535.0 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D 65535.0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 b_out <=3D to_unsigned(integer(r),16); > =A0 =A0 =A0 =A0 end process; > end; > > **************************** > > Ok, I do understand that real values are a problem when they need to > be stored, or transported (with signals/ports). > > But in this case the mapping of a_in =3D> b_out can be evaluated by > brute force (by going through all input states, and running the code > inside the process for every possible input combination and noting the > output values). > > Upto today I had thought that all synthesizers would fallback to the > brute force method if intelligent algorithm generator fails. It seems > that I had mistrusted them, though. > > Any ideas why the synthesizers DO NOT have this brute-force fallback > method? > > - Topi Real types are not appropriate for synthesis in any shape or form. There is no definition of how they exist in binary (because it is not an array type) and so cannot be synthesised into gates and register. You will have to convert your real values to fixed point. Try looking at the new IEEE fixed packages. 93 compatible versions of the library can be found here: http://www.vhdl.org/fphdl/ From newsfish@newsfish Fri Feb 3 13:12:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 10:38:52 +0000 (UTC) Organization: A noiseless patient Spider Lines: 32 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Thu, 5 May 2011 10:38:52 +0000 (UTC) Injection-Info: mx03.eternal-september.org; posting-host="GYkF6yd5NlcG1TQKOHSQHQ"; logging-data="30729"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jLWz58+4wdFXOLLGciawcmI0N+9UOKDc=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:a6BmTo+VOS6U8YqnLFiJkiJaF+s= Xref: feeder.eternal-september.org comp.lang.vhdl:4989 On Thu, 05 May 2011 02:41:23 -0700, Topi wrote: > Hi, > > I am a little surprised that the following code refuses to synthesize > (at least with Quartus and Synopsys (Lattice's)): > > > process(a_in) > variable r: real; > begin > r := real(to_integer(a_in)); > r := r*1.2; > if r<0.0 then > r := 0.0; > elsif r>65535.0 then > r := 65535.0; > end if; > b_out <= to_unsigned(integer(r),16); > end process; Rearrange the computation such that all the real arithmetic operates on constants, to return a (constant) integer or unsigned result, and synthesis tools should behave correctly. For this simple example you can afford to test every interesting input value in simulation against the "real" version to prove that no rounding errors have occurred; in general that may not be feasible. Alternatively, explore the fixed point libraries as Tricky suggested. - Brian From newsfish@newsfish Fri Feb 3 13:12:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!news.alt.net!news.astraweb.com!border5.newsrouter.astraweb.com!not-for-mail From: Allan Herriman Subject: Re: Synthesizing code with intermediate real values Newsgroups: comp.lang.vhdl References: User-Agent: Pan/0.133 (House of Butterflies) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Date: 05 May 2011 12:18:34 GMT Lines: 75 Message-ID: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> Organization: Unlimited download news at news.astraweb.com NNTP-Posting-Host: 59c6cdd3.news.astraweb.com X-Trace: DXC=o9SB[7A6MITLZ1S`DSi2W0=_RHW7EWfMMB7T1k`HXR7B7X] Xref: feeder.eternal-september.org comp.lang.vhdl:4990 On Thu, 05 May 2011 03:26:29 -0700, Tricky wrote: > On May 5, 10:41 am, Topi wrote: >> Hi, >> >> I am a little surprised that the following code refuses to synthesize >> (at least with Quartus and Synopsys (Lattice's)): >> >> ********************** >> >> library ieee; >> use ieee.std_logic_1164.all; >> use ieee.numeric_std.all; >> >> entity real_synth is >>         port( >>                 a_in: in unsigned(15 downto 0); >>                 b_out: out unsigned(15 downto 0) >>         ); >> end; >> >> architecture synth of real_synth is >> begin >>         process(a_in) >>                 variable r: real; >>         begin >>                 r := real(to_integer(a_in)); >>                 r := r*1.2; >>                 if r<0.0 then >>                         r := 0.0; >>                 elsif r>65535.0 then >>                         r := 65535.0; >>                 end if; >>                 b_out <= to_unsigned(integer(r),16); >>         end process; >> end; >> >> **************************** >> >> Ok, I do understand that real values are a problem when they need to be >> stored, or transported (with signals/ports). >> >> But in this case the mapping of a_in => b_out can be evaluated by brute >> force (by going through all input states, and running the code inside >> the process for every possible input combination and noting the output >> values). >> >> Upto today I had thought that all synthesizers would fallback to the >> brute force method if intelligent algorithm generator fails. It seems >> that I had mistrusted them, though. >> >> Any ideas why the synthesizers DO NOT have this brute-force fallback >> method? >> >> - Topi > > Real types are not appropriate for synthesis in any shape or form. It's quite ok to use real types in synthesisable VHDL for code that only gets executed at compile or elaboration time. For example, you could write a function that uses real types internally, which is used to produce a (non real, e.g. unsigned) value which is assigned to a constant. generic myreal : real = 0.0; ... constant foo : natural := myfuncthatusesreals(myreal); This has had major tool support for a long time. Regards, Allan From newsfish@newsfish Fri Feb 3 13:12:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!e21g2000vbz.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: boldport Date: Thu, 5 May 2011 10:58:56 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> NNTP-Posting-Host: 86.6.9.112 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304618336 20322 127.0.0.1 (5 May 2011 17:58:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 17:58:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000vbz.googlegroups.com; posting-host=86.6.9.112; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15421 comp.lang.vhdl:4991 comp.lang.verilog:3061 In a bit of a self promotional move, though probably pretty relevant to this group, I'd like to mention http://www.boldport.com which I released on Monday, and https://www.boldport.com/docs/fpgaproj for easing the migration from GUI to command-line use of FPGA tools, and more effective project/build management. The project is at an early stage, and more features will be added with time. Praise, constructive feedback, and well-mannered bashing are welcome, of course... be as honest as this group knows how to be (feel free to email me privately as well). Finally, I'm looking for early adopter projects, and offer my help with the setup. Thanks for your attention, saar. From newsfish@newsfish Fri Feb 3 13:12:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!24g2000yqk.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 13:12:40 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> NNTP-Posting-Host: 86.60.209.165 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1304626360 8065 127.0.0.1 (5 May 2011 20:12:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 20:12:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 24g2000yqk.googlegroups.com; posting-host=86.60.209.165; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.10 (maverick) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4992 Thanks for the suggestions. My point of interest is towards understanding synthesizing process, not circumventing the problem. As Brian pointed out, in simple cases it _could be feasible_ to crawl all possible combinations to get a truth table a_in =to> b_out. But in more complex cases the result might be too complex to fit in to the target (or to optimize the truth table). Tricky: The synthesizer does not need to implement any real-valued signals in the synthesized netlist. Actually there aren't any in the source code either (the variable is not persistent, so it does not map to a register). The synthesized result could be, e.g. a 64kx16 bit rom memory. Anyway I still don't know/understand why the synthesizer companies have opted out from supporting "discrete input =to> discrete output mapping, even if there are non-trivial intermediate phased". I could easily make a vhdl to vhdl preprosessor to crawl through all possible input combinations and to produce truth table from input to output. Wonder what the synthesizers would think, if e.g. I would replace 8 x 8 multiplier by 65536 entry table. Would it utilize DSP-block (in FPGA) to implement the function? - Topi From newsfish@newsfish Fri Feb 3 13:12:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!postnews.google.com!b35g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Thu, 5 May 2011 13:53:03 -0700 (PDT) Organization: http://groups.google.com Lines: 66 Message-ID: References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304628783 32714 127.0.0.1 (5 May 2011 20:53:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 5 May 2011 20:53:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b35g2000yqn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4993 On May 5, 4:12=A0pm, Topi wrote: > Thanks for the suggestions. > > As Brian pointed out, in simple cases it _could be feasible_ to crawl > all possible combinations to get a truth table a_in =3Dto> b_out. That's not what Brian said at all. He said you can use reals to compute constants that, in the end, vanish in the resulting function output. > But in more complex cases the result might be too complex to fit in to > the target (or to optimize the truth table). > Such as what? Your example is not such an example if that's what you had in mind. For starters, the comparison with 0 is not needed, the input is unsigned, therefore could never be less than 0. Second, rather than taking the input and multiplying by 1.2 and comparing that to 65535.0, one could instead compare r with the computed constant 65535.0 / 1.2 converted to an unsigned. That is what Brian general case suggestion would be for your specific example by the way. There may indeed be more complex examples as you stated, but give an example of such that cannot be trivially changed to be equivalent as is the case with your original posting. > Anyway I still don't know/understand why the synthesizer companies > have opted out from supporting "discrete input =3Dto> discrete output > mapping, even if there are non-trivial intermediate phased". > Most likely because there is little market demand from users. Even real constants didn't use to be supported. Now (and for the past several years) they are. Given a compelling reason the synthesis vendors do support user requests although usually not nearly as fast as some might like. If you can come up with a compelling use case then you should submit it to all the vendors as a feature suggestion. However, you would have to do better than your example where the only motivation you could provide is that you don't like the looks of "65535.0 / 1.2" as compared to "r * 1.2". > I could easily make a vhdl to vhdl preprosessor to crawl through all > possible input combinations and to produce truth table from input to > output. > OK. And then compare what you get with that approach versus computing the constant as suggested here. The metrics of importance to most people would be amount of logic resources used and performance. If your approach is an improvement you're on to something. If not, maybe the synthesis vendors aren't doing such a bad job after all. > Wonder what the synthesizers would think, if e.g. I would replace 8 x > 8 multiplier by 65536 entry table. Would it utilize DSP-block (in > FPGA) to implement the function? > I would find it highly unlikely that any synthesis tool would take a truth table specification in the source code and infer a multiply operation from it and then use a DSP block to implement the multiply...not to say that it couldn't, I would just be very surprised if it did. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:12:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.earthlink.com!news.earthlink.com.POSTED!not-for-mail NNTP-Posting-Date: Fri, 06 May 2011 01:14:11 -0500 Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 06 May 2011 00:14:10 -0600 From: "David M. Palmer" Newsgroups: comp.lang.vhdl Message-ID: <060520110014104755%dmpalmer@email.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-transfer-encoding: 8bit User-Agent: Thoth/1.8.4 (Carbon/OS X) Lines: 42 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.167.133.208 X-Trace: sv3-aQLiw90ow/R+0pFmK2MSnVztRJzagCMeLmEhuuB9RgmfsiNjUX7uxlH7MX7YG9wMhp24Yh8azZyws9a!DWzkqIz+IFz7GR3QK0yoYWGgVE3VPQwF0OR/BLoRZeCd8yGlUWh3XymoER/SgKqKnRmuJl0Ro5al!E6F95Ohle8OUN3heFEL+tZRj X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2358 Xref: feeder.eternal-september.org comp.lang.vhdl:4994 In article , Steffen Koepf wrote: > Hello, > > i need a very fast PWM in a Cyclone III FPGA. > If necessary, a Cyclone IV will do it too. > > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KHz > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. > > But the resolution is still not enough, i would like to have more steps. > > Using a -6 speed grade Cyclone III would allow 600 MHz, which gives around > 15000 Steps. > > Does one know a way to get even more? If you need a value of e.g. 3128.357/5000 out of your PWM, then make your pulse width either 3129 (35.7% of the time) or 3128 (64.3% of the time). If necessary for your application, apply randomness cleverly enough that you don't get significant subharmonics (undertones) of the 80 kHz. > Is there a way to use the SERDES LVDS to get a fast PWM? > > Is it possible to use the PLL to generate higher frequencies and use them > for example by ANDing them for 4 sub-steps (two more bits)? > > > Thanks in advance, > > Steffen > -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com) From newsfish@newsfish Fri Feb 3 13:12:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n10g2000yqf.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: Very fast PWM in Cyclone III FPGA Date: Fri, 6 May 2011 00:25:30 -0700 (PDT) Organization: http://groups.google.com Lines: 130 Message-ID: <62d02e14-dbcb-42c4-ade8-7df6988f912f@n10g2000yqf.googlegroups.com> References: NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1304666730 11514 127.0.0.1 (6 May 2011 07:25:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 May 2011 07:25:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n10g2000yqf.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.6) Gecko/20100625 Firefox/3.6.6,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4995 On Apr 28, 9:52=A0pm, Steffen Koepf wrote: > I need a 80 KHz PWM for direct Gate Control in a Switchmode Power Supply. > > At the moment the Cyclone III is running at 400 MHz, which gives at 80 KH= z > 5000 Steps. I made it to be able to use the falling edge in my PWM- > Comparator, too, so i have now 10000 Steps at 80 KHz. Here is an example of PWM generator with sub-cycle (average) accuracy: input_max is the resolution of pwm you want. count_num defines the pwm frequency. Does it fit to your needs? - Topi ******** library ieee; use ieee.std_logic_1164.all; entity pwm_gen_fast is generic( input_max: integer :=3D 1e6; -- PWM input range max value. count_num: integer :=3D 100e6/80e3 -- number of clk cycles of one PWM cycle. ); port( clk_in: in std_logic; pwm_in: in integer range 0 to input_max; pwm_out: out std_logic ); end; architecture synth of pwm_gen_fast is constant rat_val: integer :=3D (input_max)/(count_num); signal store: integer range 0 to input_max :=3D 0; signal counter: integer range 0 to count_num-1 :=3D 0; signal pwm: std_logic; begin process(clk_in) variable new_store: integer range 0 to input_max+rat_val :=3D 0; variable rst_counter: boolean; variable new_pwm: std_logic; variable new_counter : integer; begin if rising_edge(clk_in) then rst_counter :=3D false; new_pwm :=3D pwm; new_store :=3D store; if new_store < pwm_in then new_store :=3D new_store + rat_val; end if; if counter =3D count_num-1 then new_counter :=3D 0; rst_counter :=3D true; else new_counter :=3D counter + 1; end if; if rst_counter then new_store :=3D new_store - pwm_in; store <=3D new_store; end if; if new_counter =3D 0 then new_pwm :=3D '1'; end if; if new_store >=3D pwm_in then new_pwm :=3D '0'; end if; pwm <=3D new_pwm; counter <=3D new_counter; store <=3D new_store; end if; end process; pwm_out <=3D pwm; end; library ieee; use ieee.std_logic_1164.all; entity tb_pwm_gen_fast is end; architecture tb of tb_pwm_gen_fast is signal clk: std_logic; signal pwm_in: integer range 0 to 100 :=3D 0; signal pwm_out: std_logic; begin DUT: entity work.pwm_gen_fast generic map( input_max =3D> 100, count_num =3D> 10 ) port map( clk_in =3D> clk, pwm_in =3D> pwm_in, pwm_out =3D> pwm_out ); process begin clk <=3D '0'; wait for 500 ns; clk <=3D '1'; wait for 500 ns; end process; process begin pwm_in <=3D 1; wait for 5000 us; pwm_in <=3D 80; wait for 1000 us; pwm_in <=3D 82; wait for 1000 us; pwm_in <=3D 100; wait for 1000 us; pwm_in <=3D 99; wait for 1000 us; assert false report "all done" severity failure; wait; end process; end; ******** From newsfish@newsfish Fri Feb 3 13:12:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Synthesizing code with intermediate real values Date: Fri, 6 May 2011 13:22:14 +0000 (UTC) Organization: A noiseless patient Spider Lines: 57 Message-ID: References: <4dc2959a$0$11101$c3e8da3@news.astraweb.com> <9ec99126-920e-4026-9a4d-c07f88ff71b9@24g2000yqk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 6 May 2011 13:22:14 +0000 (UTC) Injection-Info: mx01.eternal-september.org; posting-host="rXzJ5MDsuKq5UTEB2rLg2g"; logging-data="27745"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX194RSEO5sFRf+bIoB4dszwhe0NLyzgJyuw=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:AR4ZLXyTSpIAt4MN5KQaVSV3Z34= Xref: feeder.eternal-september.org comp.lang.vhdl:4996 On Thu, 05 May 2011 13:53:03 -0700, KJ wrote: > On May 5, 4:12 pm, Topi wrote: >> Thanks for the suggestions. >> >> As Brian pointed out, in simple cases it _could be feasible_ to crawl >> all possible combinations to get a truth table a_in =to> b_out. > > That's not what Brian said at all. He said you can use reals to compute > constants that, in the end, vanish in the resulting function output. Thanks, that was it. > Such as what? Your example is not such an example if that's what you > had in mind. For starters, the comparison with 0 is not needed, the > input is unsigned, therefore could never be less than 0. Second, rather > than taking the input and multiplying by 1.2 and comparing that to > 65535.0, one could instead compare r with the computed constant 65535.0 > / 1.2 converted to an unsigned. That is what Brian general case > suggestion would be for your specific example by the way. Indeed. But to expand on this, the original code would output r * 1.2 in cases where saturation did not occur, so at least an integer constant multiplication is necessary. However it should be a multiplication of the form : r := a_in * to_unsigned(1.2 * 65536) / 65536; where the division is trivial. Now if careful attention is paid to issues of rounding vs. truncation, this will deliver identical results to the original, while eliminating run-time floating point arithmetic; otherwise it may deliver results differing by +/-1 LSB. To be explicit about this, you may need to round the coefficient r := a_in * to_unsigned(1.2 * 65536 + 0.5) / 65536; or the r := (a_in * to_unsigned(1.2 * 65536) + 0.5)/ 65536; or both to match the integer(r) function in the original version. THIS is where I recommend exhaustive testing; comparing the modified process vs. the original, IN SIMULATION, for every input value. Assert the outputs are equal; regard any difference as a failure. This is the brute force approach, but for only 2**16 input values it is the easiest. I have used it up to 2**24 inputs without too much pain. Alternatively, you may find a mathematical analysis to reduce the number of test cases required (otherwise, for 2 independent 32-bit inputs, 2**64 testcases would be required!) Or you may need to justify (and document!) that a 1 LSB error is permissible in your use case; e.g. because the input data has a noise component much grater than this level. - Brian From newsfish@newsfish Fri Feb 3 13:12:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!q30g2000vbs.googlegroups.com!not-for-mail From: Mark Christiaens Newsgroups: comp.lang.vhdl Subject: Accessing field of record aggregate Followup-To: comp.lang.vhdl Date: Wed, 11 May 2011 02:46:16 -0700 (PDT) Organization: http://groups.google.com Lines: 43 Message-ID: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305107177 22970 127.0.0.1 (11 May 2011 09:46:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 May 2011 09:46:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q30g2000vbs.googlegroups.com; posting-host=195.144.71.15; posting-account=VvmngAoAAACfNKqnkCfwI3NfVc3Fvw96 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:4997 I was wondering what is going on in this test case: --------------------------------------------- entity top is end entity top; architecture RTL of top is type rtype is record i1 : integer; i2 : integer; end record; begin process is variable i : rtype; begin i := rtype'(0, 0); -- OK assert i.i1 = 0; -- OK assert rtype'(0, 0).i1 = 0; -- Not OK wait; end process; end architecture RTL; --------------------------------------------- As you can see, I've defined a record type "rtype". Using a record aggregate to initialize a record variable is fine (according to ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of that variable is fine but building a complete expression that uses the record aggregate is not fine. ModelSim complains: # -- Loading package standard # -- Compiling entity top # -- Compiling architecture rtl of top # ** Error: top.vhd(18): Qualified expression type mark rtype is not type std.standard.boolean. # ** Error: top.vhd(18): near ".": expecting ';' # ** Error: top.vhd(22): VHDL Compiler exiting Why exactly is this not allowed? --- Mark Christiaens Discover the Future of VHDL Design www.sigasi.com From newsfish@newsfish Fri Feb 3 13:12:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!194.109.133.85.MISMATCH!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcabb8a$0$41102$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Accessing field of record aggregate Newsgroups: comp.lang.vhdl Date: Wed, 11 May 2011 18:38:34 +0200 References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 69 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305131915 news.xs4all.nl 41102 puiterl/[::ffff:195.242.97.150]:34114 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:4998 Mark Christiaens wrote: > I was wondering what is going on in this test case: > --------------------------------------------- > entity top is > end entity top; > > architecture RTL of top is > type rtype is record > i1 : integer; > i2 : integer; > end record; > > begin > process is > variable i : rtype; > begin > i := rtype'(0, 0); -- OK There is no ambiguity, so a qualifier is not needed. This works just as well: i := (0, 0); Or: i := (i1 => 0, i2 => 0); Even this is OK: i := (others => 0); > assert i.i1 = 0; -- OK > assert rtype'(0, 0).i1 = 0; -- Not OK > wait; > end process; > > end architecture RTL; > --------------------------------------------- > > As you can see, I've defined a record type "rtype". Using a record > aggregate to initialize a record variable is fine (according to > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > that variable is fine but building a complete expression that uses the > record aggregate is not fine. ModelSim complains: > > # -- Loading package standard > # -- Compiling entity top > # -- Compiling architecture rtl of top > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > type std.standard.boolean. > # ** Error: top.vhd(18): near ".": expecting ';' > # ** Error: top.vhd(22): VHDL Compiler exiting > > Why exactly is this not allowed? I don't know exactly why. But I also don't know why you would want to use that construct that way. Taking a record element works with variables, constants and signals. It seems that you want to use a constant built with literals. Using a real constant avoids the whole problem constant c : rtype := (0, 0); ... assert c.i1 = 0; -- OK -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:12:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 11 May 2011 17:29:25 -0500 Date: Wed, 11 May 2011 23:29:24 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> In-Reply-To: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 75 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-sZsWpKVmTNZGrkBTS45k2nBEd3qibI/VEF1kACtCppTJ8vh6KTEuFyF0e+wz6wN+zat9Kd9RauKsHvx!LHciixC7xWfNTH6edI10VNVdYBYrarfArauKxQBft4f43nkhRkdYJxV80marCUQUTTV6/KfTDUVG!ukQM9rQXFBF9gQ0QKNR7eloDvc8= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3319 Xref: feeder.eternal-september.org comp.lang.vhdl:4999 On 11/05/11 10:46, Mark Christiaens wrote: > I was wondering what is going on in this test case: > --------------------------------------------- > entity top is > end entity top; > > architecture RTL of top is > type rtype is record > i1 : integer; > i2 : integer; > end record; > > begin > process is > variable i : rtype; > begin > i := rtype'(0, 0); -- OK > assert i.i1 = 0; -- OK > assert rtype'(0, 0).i1 = 0; -- Not OK > wait; > end process; > > end architecture RTL; > --------------------------------------------- > > As you can see, I've defined a record type "rtype". Using a record > aggregate to initialize a record variable is fine (according to > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > that variable is fine but building a complete expression that uses the > record aggregate is not fine. ModelSim complains: > > # -- Loading package standard > # -- Compiling entity top > # -- Compiling architecture rtl of top > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > type std.standard.boolean. > # ** Error: top.vhd(18): near ".": expecting ';' > # ** Error: top.vhd(22): VHDL Compiler exiting > > Why exactly is this not allowed? In section 6.1 the VHDL standard defines a name as simple_name | operator_symbol | selected_name | indexed_name | slice_name | attribute_name It then defines the prefix of a selected name as prefix ::= name | funtion_call A qualified expression is not a name so the selected_name you've attempted to use is also not a name. It doesn't seem surprising to me as you haven't created an object with a name, just a literal. regards Alan P.S. Cadence ncvhdl helpfully says assert rtype'(0,0).i1 = 0; | ncvhdl_p: *E,QLXNOP (test.vhd,18|22): a qualified expression is not a legal name prefix [6.1] [7.3.4]. errors: 1, warnings: 0 irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting. -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:12:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h36g2000pro.googlegroups.com!not-for-mail From: Mark Christiaens Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate Date: Thu, 12 May 2011 01:00:22 -0700 (PDT) Organization: http://groups.google.com Lines: 88 Message-ID: <6155a8b6-97eb-4e3a-afc7-764ecc89e358@h36g2000pro.googlegroups.com> References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305187222 20924 127.0.0.1 (12 May 2011 08:00:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 May 2011 08:00:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h36g2000pro.googlegroups.com; posting-host=195.144.71.15; posting-account=VvmngAoAAACfNKqnkCfwI3NfVc3Fvw96 User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5000 On May 12, 12:29=A0am, Alan Fitch wrote: > On 11/05/11 10:46, Mark Christiaens wrote: > > > > > > > > > > > I was wondering what is going on in this test case: > > --------------------------------------------- > > entity top is > > end entity top; > > > architecture RTL of top is > > =A0 =A0 type rtype is record > > =A0 =A0 =A0 =A0 i1 : integer; > > =A0 =A0 =A0 =A0 i2 : integer; > > =A0 =A0 end record; > > > begin > > =A0 =A0 process is > > =A0 =A0 =A0 =A0 variable i : rtype; > > =A0 =A0 begin > > =A0 =A0 =A0 =A0 i :=3D rtype'(0, 0); -- OK > > =A0 =A0 =A0 =A0 assert i.i1 =3D 0; -- OK > > =A0 =A0 =A0 =A0 assert rtype'(0, 0).i1 =3D 0; -- Not OK > > =A0 =A0 =A0 =A0 wait; > > =A0 =A0 end process; > > > end architecture RTL; > > --------------------------------------------- > > > As you can see, I've defined a record type "rtype". =A0Using a record > > aggregate to initialize a record variable is fine (according to > > ModelSim ALTERA STARTER EDITION 6.5e), accessing the "i1" field of > > that variable is fine but building a complete expression that uses the > > record aggregate is not fine. =A0ModelSim complains: > > > # -- Loading package standard > > # -- Compiling entity top > > # -- Compiling architecture rtl of top > > # ** Error: top.vhd(18): Qualified expression type mark rtype is not > > type std.standard.boolean. > > # ** Error: top.vhd(18): near ".": expecting ';' > > # ** Error: top.vhd(22): VHDL Compiler exiting > > > Why exactly is this not allowed? > > In section 6.1 the VHDL standard defines a name as > > =A0 simple_name | operator_symbol | selected_name | indexed_name | > slice_name | attribute_name > > It then defines the prefix of a selected name as > > =A0 prefix ::=3D name | funtion_call > > A qualified expression is not a name so the selected_name you've > attempted to use is also not a name. > > It doesn't seem surprising to me as you haven't created an object with a > name, just a literal. > > regards > Alan > > P.S. Cadence ncvhdl helpfully says > > =A0assert rtype'(0,0).i1 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > ncvhdl_p: *E,QLXNOP (test.vhd,18|22): a qualified expression is not a > legal name prefix [6.1] [7.3.4]. > =A0 =A0 =A0 =A0 errors: 1, warnings: 0 > irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting. > > -- > Alan Fitch I was not having a particular use case in mind. I was just curious how "orthogonal" the VHDL grammar exactly is with regards to such expressions. My conclusion is that it's not very orthogonal ;) Anyway, thank you for clarifying. Mark From newsfish@newsfish Fri Feb 3 13:12:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!k17g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Accessing field of record aggregate Date: Thu, 12 May 2011 09:17:38 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <86170afb-c209-44ba-94dc-20a8521314d8@k17g2000vbn.googlegroups.com> References: <18d44099-1b7d-4d71-857d-079d2acd97de@q30g2000vbs.googlegroups.com> <6155a8b6-97eb-4e3a-afc7-764ecc89e358@h36g2000pro.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305217059 10393 127.0.0.1 (12 May 2011 16:17:39 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 12 May 2011 16:17:39 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k17g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5001 On May 12, 4:00=A0am, Mark Christiaens wrote: > I was just curious > how "orthogonal" the VHDL grammar exactly is with regards to such > expressions. =A0My conclusion is that it's not very orthogonal ;) > My conclusion is that your usage is not a measure of orthogonality. KJ From newsfish@newsfish Fri Feb 3 13:12:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Visibility rules Newsgroups: comp.lang.vhdl Date: Fri, 13 May 2011 14:09:12 +0200 Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 98 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305288552 news.xs4all.nl 81484 puiterl/[::ffff:195.242.97.150]:42319 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5002 I am curious how simulators deal with code as shown below when analyzing it: PACKAGE pkg IS FUNCTION min ( a : integer; b : integer ) RETURN integer; END PACKAGE pkg; PACKAGE BODY pkg IS FUNCTION min ( a : integer; b : integer ) RETURN integer IS BEGIN IF a < b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION min; END PACKAGE BODY pkg; ENTITY ent IS END ENTITY ent; USE work.pkg.ALL; ARCHITECTURE arch OF ent IS BEGIN p: PROCESS IS VARIABLE v : integer; BEGIN v := min(123, 456); WAIT; END PROCESS p; END ARCHITECTURE arch; I use ModelSim. Up to version 10.0 (including 10.0beta1) this used to work fine. Version 10.0a (and I suppose 10.0 as well) now complains: ** Error: vhdl/function_min.vhd(34): (vcom-1078) Identifier "min" is not directly visible. Potentially visible declarations are: std.STANDARD.min (physical unit) work.pkg.min (function) So clearly there is a collision now with the physical unit "min" from type TIME. Technote MG539708 by Mentor explains that the above behaviour is LRM compliant. The fact that this used to work in earlier versions is an unlucky event, based on the order in which declarations were found (USE clauses). The clause "USE std.standard.all" always is present implicitly. So, could somebody please analyze the above code in a different simulator to see if it is accepted or not? Additionally, I wonder why a function name "DEL" (instead of "min) *is* accepted. DEL is one of the enumeration literals of type CHARACTER. To add to the fun: this is not accepted by any version of ModelSim: PACKAGE pkg IS COMPONENT del IS END COMPONENT del; END PACKAGE pkg; ENTITY ent IS END ENTITY ent; USE work.pkg.ALL; ARCHITECTURE arch OF ent IS BEGIN del_i: del; END ARCHITECTURE arch; Ah, wait a minute: the clarification of error message 1078 explains why del can be used as function and not as a component (both declared in a package): vcom Message # 1078: The name is ambiguous according to the visibility rules. IEEE Std 1076-1993, 10.4 Use clauses, line 234: Potentially visible declarations that have the same designator are not made directly visible unless each of them is either an enumeration literal specification or the declaration of a subprogram (either by a subprogram declaration or by an implicit declaration). Still, I am curious if my code with function min fails in other simulators. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:12:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!usenet.pasdenom.info!selfless.tophat.at!news.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: Philippe Newsgroups: comp.lang.vhdl,comp.emacs Subject: Emacs VHDL mode with CTAGS / etags Date: Fri, 13 May 2011 07:32:52 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> NNTP-Posting-Host: 83.134.177.166 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305297172 26752 127.0.0.1 (13 May 2011 14:32:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 May 2011 14:32:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=83.134.177.166; posting-account=mL_PkwoAAACZFWJtE__iFzdxdzOYeK1F User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.68 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5003 comp.emacs:3846 Is there anybody out there who still uses CTAGS (or rather: etags) for VHDL? I was surprised to see how crude it really is. No scoping, the regular expressions get confused easily, problems with name clashes... http://www.sigasi.com/content/navigating-through-vhdl-project-emacs-vs-sigasi have a nice weekend! -- Philippe Sigasi From newsfish@newsfish Fri Feb 3 13:12:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4dcd5850$0$81485$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Emacs VHDL mode with CTAGS / etags Newsgroups: comp.lang.vhdl,comp.emacs Followup-To: comp.lang.vhdl Date: Fri, 13 May 2011 18:12:00 +0200 References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 20 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305303120 news.xs4all.nl 81485 puiterl/[::ffff:195.242.97.150]:59599 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5004 comp.emacs:3847 Philippe wrote: > Is there anybody out there who still uses CTAGS (or rather: etags) for > VHDL? Yes, I use vtags in combination with Nedit or Vim. I got vtags from http://tams-www.informatik.uni-hamburg.de/vhdl/tools/vtags/, but it seems not to be accessible from there anymore. > I was surprised to see how crude it really is. No scoping, the > regular expressions get confused easily, problems with name clashes... Still, it is simple to use and adequate in a lot of cases. And it's free. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:12:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: -DeeT Newsgroups: comp.lang.vhdl Subject: slice of signed = unsigned? Date: Fri, 13 May 2011 10:43:11 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: NNTP-Posting-Host: 97.65.186.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305308592 9383 127.0.0.1 (13 May 2011 17:43:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 13 May 2011 17:43:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=97.65.186.18; posting-account=Khn83QoAAAC4ziDcW7Lr35LufiqQCIcd User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.65 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5005 If you take a slice of a signed vector which doesn't include the sign bit, is that slice considered to be signed or unsigned? Here's an illustration: signal v : signed(7 downto 0); alias a is v(3 downto 0); variable i : integer; i := to_integer(a); In the above scenario, what is the range of possible values for 'i'? Is it 0 to 15, or -8 to +7? I ask because a compiler upgrade broke some of my code, by changing this behavior (which admittedly I shouldn't have counted on either way!). Thanks in advance for your thoughts... -DT From newsfish@newsfish Fri Feb 3 13:12:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!feeder.news-service.com!216.196.110.144.MISMATCH!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 13 May 2011 19:11:19 -0500 Date: Sat, 14 May 2011 01:11:18 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Visibility rules References: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> In-Reply-To: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 112 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-fgcWI+v58Zi+qncZqrAftPRIHC68eTgGEorC6RBzMA0Ldzi5tCK/p94hmAkknx/b9rAYRibSud9im8Y!EYlfdCo6pJlMW1D2ORBwdsQ7ijX81HqzYgn7bPCpE9fPzVtDoPNaqS+PmXx4BAkPKHT/aaHGKTMX!FyNPMU0WTVucz40u2pv5OV/BJwI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4441 Xref: feeder.eternal-september.org comp.lang.vhdl:5006 On 13/05/11 13:09, Paul Uiterlinden wrote: > I am curious how simulators deal with code as shown below when analyzing it: > > PACKAGE pkg IS > FUNCTION min > ( > a : integer; > b : integer > ) RETURN integer; > END PACKAGE pkg; > > PACKAGE BODY pkg IS > FUNCTION min > ( > a : integer; > b : integer > ) RETURN integer IS > BEGIN > IF a < b THEN > RETURN a; > ELSE > RETURN b; > END IF; > END FUNCTION min; > END PACKAGE BODY pkg; > > ENTITY ent IS > END ENTITY ent; > > USE work.pkg.ALL; > > ARCHITECTURE arch OF ent IS > BEGIN > p: PROCESS IS > VARIABLE v : integer; > BEGIN > v := min(123, 456); > WAIT; > END PROCESS p; > END ARCHITECTURE arch; > > I use ModelSim. Up to version 10.0 (including 10.0beta1) this used to work > fine. Version 10.0a (and I suppose 10.0 as well) now complains: > > ** Error: vhdl/function_min.vhd(34): (vcom-1078) Identifier "min" is not > directly visible. > Potentially visible declarations are: > std.STANDARD.min (physical unit) > work.pkg.min (function) > > So clearly there is a collision now with the physical unit "min" from type > TIME. > > Technote MG539708 by Mentor explains that the above behaviour is LRM > compliant. The fact that this used to work in earlier versions is an > unlucky event, based on the order in which declarations were found (USE > clauses). The clause "USE std.standard.all" always is present implicitly. > > So, could somebody please analyze the above code in a different simulator to > see if it is accepted or not? > > Additionally, I wonder why a function name "DEL" (instead of "min) *is* > accepted. DEL is one of the enumeration literals of type CHARACTER. > > To add to the fun: this is not accepted by any version of ModelSim: > > PACKAGE pkg IS > COMPONENT del IS > END COMPONENT del; > END PACKAGE pkg; > > ENTITY ent IS > END ENTITY ent; > > USE work.pkg.ALL; > > ARCHITECTURE arch OF ent IS > BEGIN > del_i: del; > END ARCHITECTURE arch; > > Ah, wait a minute: the clarification of error message 1078 explains why del > can be used as function and not as a component (both declared in a > package): > > vcom Message # 1078: > The name is ambiguous according to the visibility rules. > IEEE Std 1076-1993, 10.4 Use clauses, line 234: > Potentially visible declarations that have the same designator are not > made directly visible unless each of them is either an enumeration > literal specification or the declaration of a subprogram (either by a > subprogram declaration or by an implicit declaration). > > Still, I am curious if my code with function min fails in other simulators. > It fails in Cadence: ncvhdl -v93 test.vhd ncvhdl: 10.20-s009: (c) Copyright 1995-2011 Cadence Design Systems, Inc. v := min(123, 456); | ncvhdl_p: *E,IDENRD (test.vhd,34|13): identifier (MIN) is not visible, as it is directly visible via use clauses from more than one design unit. This results in conflict. This object is defined at: STD.STANDARD WORKLIB.PKG Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:12:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d27g2000vbz.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: Emacs VHDL mode with CTAGS / etags Date: Sat, 14 May 2011 03:35:06 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <1321e0c6-e0fc-4dd7-8b6d-2fa8aad433f2@d27g2000vbz.googlegroups.com> References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> <4dcd5850$0$81485$e4fe514c@news.xs4all.nl> NNTP-Posting-Host: 88.71.194.8 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305369307 22559 127.0.0.1 (14 May 2011 10:35:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 14 May 2011 10:35:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d27g2000vbz.googlegroups.com; posting-host=88.71.194.8; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5007 On 13 Mai, 18:12, Paul Uiterlinden wrote: > Philippe wrote: > > Is there anybody out there who still uses CTAGS (or rather: etags) for > > VHDL? I just discovered etags a few weeks ago. Currently I'm working on C code and it really eases the analysis of foreign code. Honestly: etags is one of the most important emacs features that I discovered in the last years I would say. I'm already looking forward to the next VHDL project where I can give etags a try... hhanff > > Yes, I use vtags in combination with Nedit or Vim. > > I got vtags fromhttp://tams-www.informatik.uni-hamburg.de/vhdl/tools/vtags/, but it seems > not to be accessible from there anymore. > > > I was surprised to see how crude it really is. No scoping, the > > regular expressions get confused easily, problems with name clashes... > > Still, it is simple to use and adequate in a lot of cases. And it's free. > > -- > Paul Uiterlindenwww.aimvalley.nl > e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:12:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!.POSTED!not-for-mail From: Alexander Bartolich Newsgroups: comp.lang.vhdl Subject: Re: slice of signed = unsigned? Date: Sat, 14 May 2011 20:02:24 +0000 (UTC) Organization: albasani.net Lines: 38 Message-ID: References: X-Trace: news.albasani.net ybB+XxxaAJKpx8Jo4I8lcVx4Bh0UsKDKtGKHuU8JCuoC727SQORP5iKZ/mA3pC87IBsfAZcPynmWZPLtAbGrNA== NNTP-Posting-Date: Sat, 14 May 2011 20:02:24 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="Y8Z20mHuMJSpZiRG8lgdTokkGqbSI4SdIhodbaHG43q1snISa+y9mDWQN/JlPmBJV9SB+So8P8VtTnkSZXFQaIS/MohT1gLTpkCmeAWfEMVgqkkZzxRCDVGNNPTzPGB+"; mail-complaints-to="abuse@albasani.net" User-Agent: slrn/pre1.0.0-16 (Linux) Cancel-Lock: sha1:6R1QD8MH/2FQOpt9Z4i7xC2LVik= Xref: feeder.eternal-september.org comp.lang.vhdl:5008 -DeeT wrote: > If you take a slice of a signed vector which doesn't include the sign > bit, is that slice considered to be signed or unsigned? Here's an > illustration: > > signal v : signed(7 downto 0); > alias a is v(3 downto 0); > variable i : integer; > i := to_integer(a); IEEE Std 1076-1993 (Revision of IEEE Std 1076-1987), page 75 # 4.3.3.1 Object aliases # [...] # The name must be a static name (see 6.1) that denotes an object. The # base type of the name specified in an alias declaration must be the # same as the base type of the type mark in the subtype indication (if # the subtype indication is present); this type must not be a multi- # dimensional array type. When the object denoted by the name is # referenced via the alias defined by the alias declaration, the following # rules apply: # - If the subtype indication is absent or if it is present and denotes # an unconstrained array type: # - If the alias designator denotes a slice of an object, then the # subtype of the object is viewed as if it were of the subtype # specified by the slice # - Otherwise, the object is viewed as if it were of the subtype # specified in the declaration of the object denoted by the name > In the above scenario, what is the range of possible values for 'i'? > Is it 0 to 15, or -8 to +7? To my understanding the alias is equivalent to a declaration like signal a: signed(3 downto 0); -- host -t mx moderators.isc.org From newsfish@newsfish Fri Feb 3 13:12:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: slice of signed = unsigned? Date: Sat, 14 May 2011 15:47:56 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <16be61c9-9962-4119-b70b-1a7dcb3f3dd4@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 86.135.20.20 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305413276 32608 127.0.0.1 (14 May 2011 22:47:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 14 May 2011 22:47:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=86.135.20.20; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0) Gecko/20100101 Firefox/4.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5009 On May 13, 6:43=A0pm, -DeeT wrote: > If you take a slice of a signed vector which doesn't include the sign > bit, is that slice considered to be signed or unsigned? =A0Here's an > illustration: > > signal v : signed(7 downto 0); > alias a is v(3 downto 0); > variable i : integer; > i :=3D to_integer(a); > > In the above scenario, what is the range of possible values for 'i'? > Is it 0 to 15, or -8 to +7? > > I ask because a compiler upgrade broke some of my code, by changing > this behavior (which admittedly I shouldn't have counted on either > way!). > > Thanks in advance for your thoughts... > -DT Signed and Unsigned are two completely different types, so slicing them just returns a subtype of the base type. But they are similar types, so you can cast from one type to the other without a conversion function. So you could write this instead: i :=3D to_integer( unsigned(a) ); From newsfish@newsfish Fri Feb 3 13:12:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4dd11199$0$81474$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Visibility rules Newsgroups: comp.lang.vhdl Date: Mon, 16 May 2011 13:59:20 +0200 References: <4dcd1f68$0$81484$e4fe514c@news.xs4all.nl> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 30 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1305547161 news.xs4all.nl 81474 puiterl/[::ffff:195.242.97.150]:53205 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5010 Alan Fitch wrote: >> Still, I am curious if my code with function min fails in other >> simulators. >> > > It fails in Cadence: > > ncvhdl -v93 test.vhd > ncvhdl: 10.20-s009: (c) Copyright 1995-2011 Cadence Design Systems, Inc. > v := min(123, 456); > | > ncvhdl_p: *E,IDENRD (test.vhd,34|13): identifier (MIN) is not visible, > as it is directly visible via use clauses from more than one design > unit. This results in conflict. This object is defined at: > STD.STANDARD > WORKLIB.PKG Thanks. That is the correct answer (LRM-wise). If only ModelSim would have given that answer years ago. Now I'm stuck with many many VHDL files that are not LRM compliant. I was happy when I read that in VHDL-2008 the functions minimum and maximum where added, instead of min and max. Those function names where already in use by me. Now I now that min was a bad choice anyway. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:12:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.lang.vhdl,comp.emacs Subject: Re: Emacs VHDL mode with CTAGS / etags Date: Mon, 16 May 2011 11:55:27 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: References: <0520ced9-8558-4493-925f-8fc6dceb2bb9@t16g2000vbi.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1305572127 28728 127.0.0.1 (16 May 2011 18:55:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 16 May 2011 18:55:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5011 comp.emacs:3849 On May 13, 7:32=A0am, Philippe wrote: > Is there anybody out there who still uses CTAGS (or rather: etags) for > VHDL? I was surprised to see how crude it really is. No scoping, the > regular expressions get confused easily, problems with name clashes... > > http://www.sigasi.com/content/navigating-through-vhdl-project-emacs-v... > > have a nice weekend! > > -- > Philippe > Sigasi SPAM? Yup, it's spam. Have a nice day. From newsfish@newsfish Fri Feb 3 13:12:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c1g2000yqe.googlegroups.com!not-for-mail From: "A. M. G. Solo" Newsgroups: sci.electronics.design,sci.electronics.cad,sci.electronics.misc,sci.engr.semiconductors,comp.lang.vhdl Subject: Last Call for Papers: The 2011 International Conference on Modeling, Simulation, and Visualization Methods (MSV'11), USA, July 18-21, 2011 Date: Tue, 17 May 2011 02:30:32 -0700 (PDT) Organization: http://groups.google.com Lines: 271 Message-ID: <754765bb-afd8-44a9-b3c9-8e61b852fd72@c1g2000yqe.googlegroups.com> NNTP-Posting-Host: 174.2.56.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305624632 4559 127.0.0.1 (17 May 2011 09:30:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 17 May 2011 09:30:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c1g2000yqe.googlegroups.com; posting-host=174.2.56.216; posting-account=bZYTWQoAAAD2e2Hqw1r7OWn1oB5-KinJ User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; Trident/4.0; GTB5; SLCC1; .NET CLR 2.0.50727; MDDC; .NET CLR 3.5.30729; .NET CLR 3.0.30618; InfoPath.2; .NET4.0C; OfficeLiveConnector.1.5; OfficeLivePatch.1.3; FDM; AskTbTRL2/5.7.0.231),gzip(gfe) Xref: feeder.eternal-september.org sci.electronics.design:174308 sci.electronics.cad:8246 sci.electronics.misc:3804 sci.engr.semiconductors:782 comp.lang.vhdl:5012 Dear Colleagues: Please share the announcement below with those who might be interested. Thank you very much. Best regards, Organizing Committee ------------ ==================================================== CALL FOR PAPERS - Deadline: May 23, 2011 MSV'11 The 2011 International Conference on Modeling, Simulation and Visualization Methods July 18-21, 2011, Las Vegas, USA ==================================================== INVITATION: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". You are invited to submit a full paper (about 7 pages) for consideration (see instructions below). Full papers will be considered for both, oral presentation and publication in the conference proceedings as full papers. In addition, after the conference, selected authors will be asked to provide an extended version of their papers for publication consideration in research books to be published and indexed by Springer as well as by various journals. For a few examples of recent books and journal issues based on WORLDCOMP (MSV is an important track of WORLDCOMP, a federated congress in CS and CE), see the links below: (indexed by Medline, Scopus, EMBASE, BIOSIS, Biological Abstracts, CSA, Biological Sciences and Living Resources, Biological Sciences, and others): http://www.springer.com/life+sciences/bioinformatics/book/978-1-4419-7045-9 http://www.springer.com/life+sciences/bioinformatics/book/978-1-4419-5912-6 + a number of journal special issues published by BMC Genomics: http://www.biomedcentral.com . Abstract submissions (one/two-page) will be considered for poster presentations and one/two-page publication in the proceedings. The conference proceedings will be made available in printed book as well as online. INDEXING: MSV proceedings will be indexed by Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others (in the past, all tracks of the federated congress, WORLDCOMP, in which MSV is part of have also been included in EI Compendex/Elsevier.) NOTE - Important: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". Therefore, authors who have already submitted papers in response to earlier "Call For Papers" should IGNORE this announcement. (Those who have been notified that their papers have been accepted, MUST still follow the instructions that were emailed to them; including meeting the deadlines mentioned in the notifications that were sent to them). IMPORTANT DATES: May 23, 2011: Submission of papers for evaluation June 6, 2011: Notification of acceptance/not-acceptance June 21, 2011: Registration July 18-21, 2011: The 2011 International Conference on Modeling, Simulation and Visualization Methods (MSV'11) July 30, 2011: Camera-Ready Papers Due for publication in the Final Edition of the proceedings. SCOPE: Topics of interest include, but are not limited to, the following: MSV'11 is composed of a number of tracks (keynote presentations, invited talks, regular research presentations, tutorials, and workshops); all will be held simultaneously, same location and dates: July 18-21, 2011. See below for the topical list: O Simulation languages O Modeling and simulation for computer engineering O Modeling and simulation for education and training O Molecular modeling and simulation O Performance modeling, simulation, and prediction O Modeling, simulation, and emulation of large-scale, volatile environments O Modeling and simulation tools for nanotechnology O Information and scientific visualization O Real-time modeling and simulation O Geometric modeling O Perceptual issues in visualization and modeling O Modeling methodologies O Specification issues for modeling and simulation O Visual interactive simulation and modeling O Visualization tools and systems for simulation and modeling O Java-based modelers O Scalability issues O Numerical methods used in simulation and modeling O Finite and boundary element techniques O Process simulation/modeling O Device simulation/modeling O Circuit simulation/modeling O Performance evaluation and simulation tools O Multi-level modeling O Simulation of machine architectures O Simulation of wireless systems O Simulation and modeling with applications in biotechnology O CAD/CAE/CAM O Prototyping and simulation O Biomedical visualization and applications O Databases and visualization O Interaction paradigms and human factors O Parallel and distributed simulation O Discrete and numeric simulation O Geographic information systems and visualization O Internet, web and security visualization O Virtual reality and simulation O Virtual environments and data visualization O Petri nets and applications O Finite element methods O Soft computing / fuzzy logic O Tools and applications O Object-oriented simulation O Knowledge-based simulation O Emerging technologies and applications USEFUL WEB LINKS: The DBLP list of accepted papers of MSV 2010 appears at: http://www.informatik.uni-trier.de/~ley/db/conf/msv/msv2010.html The main web site of MSV'11 can be found at: http://www.worldacademyofscience.org/worldcomp11/ws/conferences/msv11 SUBMISSION OF PAPERS: This announcement is ONLY for those who MISSED the opportunity to submit their papers in response to earlier "Call For Papers". Therefore, authors who have already submitted papers in response to earlier "Call For Papers" should IGNORE this announcement. Authors who submit papers in response to this announcement, will have their papers evaluated for publication consideration in the Final Edition of the conference proceedings which will go to press in late August 2011 (the conference would then make the necessary arrangements to ship the printed proceedings/book to such authors). The Final Edition of the conference proceedings will be identical to earlier edition except for a number of sections/chapters appended to the proceedings/book. The Final Edition will be indexed by Inspec / IET / The Institute for Engineering and Technology, DBLP / CS Bibliography, and others (in the past, all tracks of the federated congress, WORLDCOMP, in which MSV is part of, have also been included in EI Compendex/Elsevier.) The proceedings will be published in both, printed book/ISBN form as well as online. Prospective authors are invited to submit their papers by uploading them to the evaluation web site at: http://world-comp.org Submissions must be uploaded by May 23, 2011 and they must be in either MS doc (but not docx) or pdf formats (about 5 to 7 pages - single space, font size of 10 to 12). All reasonable typesetting formats are acceptable (later, the authors of accepted papers will be asked to follow a particular typesetting format to prepare their final papers for publication.) Papers must not have been previously published or currently submitted for publication elsewhere. The first page of the paper should include: title of the paper, name, affiliation, postal address, and email address for each author. The first page should also identify the name of the Contact Author and a maximum of 5 topical keywords that would best represent the content of the paper. Finally, the name of the conference (ie, MSV) should be mentioned. The length of the final/Camera-Ready papers (if accepted) will be limited to 7 (two-column IEEE style) pages. Each paper will be peer-reviewed by two experts in the field for originality, significance, clarity, impact, and soundness. In cases of contradictory recommendations, a member of the conference program committee will be charged to make the final decision (accept/reject); often, this would involve seeking help from additional referees by using a double-blinded review process. In addition, all papers whose authors included a member of the conference program committee will be evaluated using the double-blinded review process. (Essay/ philosophical papers will not be refereed but may be considered for discussion/ panels). 2011 PUBLICITY CHAIR: A. M. G. Solo Fellow of British Computer Society Principal/R&D Engineer, Maverick Technologies America Inc. Intelligent Systems Instructor, Trailblazer Intelligent Systems, Inc. GENERAL INFORMATION: MSV 2011 Conference is being held jointly (same location and dates) with a number of other research conferences (WORLDCOMP). WORLDCOMP is the largest annual gathering of researchers in computer science, computer engineering and applied computing. We anticipate to have 2,100 or more attendees from over 85 countries. WORLDCOMP 2011 will be composed of research presentations, keynote lectures, invited presentations, tutorials, panel discussions, and poster presentations. In recent past, keynote/tutorial/panel speakers have included: Prof. David A. Patterson (pioneer/ architecture, U. of California, Berkeley), Dr. K. Eric Drexler (known as Father of Nanotechnology), Prof. John H. Holland (known as Father of Genetic Algorithms; U. of Michigan), Prof. Ian Foster (known as Father of Grid Computing; U. of Chicago & ANL), Prof. Ruzena Bajcsy (pioneer/VR, U. of California, Berkeley), Prof. Barry Vercoe (Founding member of MIT Media Lab, MIT), Dr. Jim Gettys (known as X-man, developer of X Window System, xhost; OLPC), Prof. John Koza (known as Father of Genetic Programming, Stanford U.), Prof. Brian D. Athey (NIH Program Director, U. of Michigan), Prof. Viktor K. Prasanna (pioneer, U. of Southern California), Dr. Jose L. Munoz (NSF Program Director and Consultant), Prof. Jun Liu (Broad Institute of MIT & Harvard U.), Prof. Lotfi A. Zadeh (Father of Fuzzy Logic), Dr. Firouz Naderi (Head, NASA Mars Exploration Program/2000-2005 and Associate Director, Project Formulation & Strategy, Jet Propulsion Lab, CalTech/NASA), and many other distinguished speakers. To get a feeling about the conferences' atmosphere, see the 2010 delegates photos available at: www.pixagogo.com/1676934789 An important mission of WORLDCOMP is "Providing a unique platform for a diverse community of constituents composed of scholars, researchers, developers, educators, and practitioners. The Congress makes concerted effort to reach out to participants affiliated with diverse entities (such as: universities, institutions, corporations, government agencies, and research centers/labs) from all over the world. The congress also attempts to connect participants from institutions that have teaching as their main mission with those who are affiliated with institutions that have research as their main mission. The congress uses a quota system to achieve its institution and geography diversity objectives." One main goal of the congress is to assemble a spectrum of affiliated research conferences, workshops, and symposiums into a coordinated research meeting held in a common place at a common time. This model facilitates communication among researchers in different fields of computer science, computer engineering, and applied computing. The Congress also encourages multi-disciplinary and inter-disciplinary research initiatives; ie, facilitating increased opportunities for cross-fertilization across sub-disciplines. According to "Microsoft Academic Search" (a Microsoft initiative) all tracks of WORLDCOMP are listed as worldwide "Top-ranked Conferences" (based on various metrics but mainly based on the number of citations). You can access "Microsoft Academic Search" to extract citation data for each individual track of worldcomp using the following link: http://academic.research.microsoft.com/ As of March 4, 2011, the papers published in the proceedings have received 14,385 citations which is a higher citation than many reputable journals in computer science. From newsfish@newsfish Fri Feb 3 13:12:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r35g2000prj.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: SystemRDL Date: Thu, 19 May 2011 16:12:32 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1305846753 1426 127.0.0.1 (19 May 2011 23:12:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 19 May 2011 23:12:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r35g2000prj.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5013 I have come across the SystemRDL standard to define a devices register space. Are there any open source tools for generating documentation from systemRDL? I currently use propriety scripts for converting a register definition spreadsheet into code. Before I bash out another scripts to generate a document I thought this could be an opportunity to dabble with this new standard. I don't need all the verification bells and whistles that seem to be offered by commercial tools - just the documentation generator part. From newsfish@newsfish Fri Feb 3 13:12:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: VHDL 2008 syntax error Date: Fri, 20 May 2011 22:01:27 -0700 Organization: A noiseless patient Spider Lines: 31 Message-ID: Injection-Date: Sat, 21 May 2011 05:12:35 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="15937"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19txJ8p20f3JYgXodlQtkDSm+j/KRg/lqU=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:X71Pp/UyJ7qHVEHvtkOWFAebpbs= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5014 I have been learning about VHDL 2008 and wanted to try a simple example of the 2008 enhancements. I created the following test file: entity generic_mux2 is generic (type data_type); port (sel : in bit; a, b : in data_type; z : out data_type ); end entity generic_mux2; architecture rtl of generic_mux2 is begin z <= a when sel = '0' else b; end architecture rtl; I installed ModelSim SE 10.0a. It claims to support a significant subset of the 2008 enhancements. When I try to compile the above file it get: vcom -2008 generic_mux2.vhdl # Model Technology ModelSim SE vcom 10.0a Compiler 2011.02 Feb 20 2011 # -- Loading package STANDARD # -- Compiling entity generic_mux2 # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER # C:/modeltech_10.0a/win32/vcom failed. Does ModelSim SE 10.0 not support generic types? Hard to imagine... This is the first thing mentioned in Peter Ashenden's "VHDL-2008: Just the New Stuff". (and I copied the above example right out of the book) Charles Bailey From newsfish@newsfish Fri Feb 3 13:12:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 21 May 2011 04:29:43 -0500 Date: Sat, 21 May 2011 10:29:43 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 43 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ItRXQZj1F8Q3quZy4JZXA5UIpzokEhPEr1ZdCCNfGP6mZwzm6ALN6ltA55bZLgPv5IMOCjgGrTapvWq!YRzGO9vXP43IE060YgZrS9pLc0RoKFepu0rcDo+a20m7bqBO/v0EOi+jsbvm1Gwa/F1kMrZvFl+3!VOSGeRmodfJ94EJKI4XXCPUwqw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2506 Xref: feeder.eternal-september.org comp.lang.vhdl:5015 On 21/05/11 06:01, logic_guy wrote: > I have been learning about VHDL 2008 and wanted to try a simple example > of the 2008 enhancements. I created the following test file: > entity generic_mux2 is > generic (type data_type); > port (sel : in bit; a, b : in data_type; > z : out data_type ); > end entity generic_mux2; > > architecture rtl of generic_mux2 is > begin > z <= a when sel = '0' else b; > end architecture rtl; > > > I installed ModelSim SE 10.0a. It claims to support a significant > subset of the 2008 enhancements. When I try to compile the above file > it get: > vcom -2008 generic_mux2.vhdl > # Model Technology ModelSim SE vcom 10.0a Compiler 2011.02 Feb 20 2011 > # -- Loading package STANDARD > # -- Compiling entity generic_mux2 > # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER > # C:/modeltech_10.0a/win32/vcom failed. > > Does ModelSim SE 10.0 not support generic types? Hard to imagine... > This is the first thing mentioned in Peter Ashenden's "VHDL-2008: Just > the New Stuff". (and I copied the above example right out of the book) > The VHDL 2008 support is documented under Help > Technotes > vhdl2008 You might also be interested in my colleague John Aynsley's video: http://www.doulos.com/knowhow/video_gallery/#anchor0 regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:12:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 11:27:58 -0700 Lines: 32 Message-ID: <93qegsFdkkU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net SMKCPz641AA5rul8KGNrbQLZk4JJiDy2P2Zxw7HPHPa6FnnEug Cancel-Lock: sha1:28vQ7j3Hh2KSEwnZzhkRi3ysrDY= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5016 On 5/20/2011 10:01 PM, logic_guy wrote: > I have been learning about VHDL 2008 and wanted to try a simple example > of the 2008 enhancements. I created the following test file: > entity generic_mux2 is > generic (type data_type); > port (sel : in bit; a, b : in data_type; > z : out data_type ); > end entity generic_mux2; > > architecture rtl of generic_mux2 is > begin > z<= a when sel = '0' else b; > end architecture rtl; ... > # ** Error: generic_mux2.vhdl(2): near "type": expecting IDENTIFIER > # C:/modeltech_10.0a/win32/vcom failed. ) -- Did you have library ieee; use ieee.std_logic_1164.all; -- at the top? Would a generic entity need an instance and generic map? incr_inst : entity work.generic_mux2 generic map ( data_type => std_ulogic) port map ( ... ); Good luck. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:12:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 14:57:14 -0700 Organization: A noiseless patient Spider Lines: 13 Message-ID: References: Injection-Date: Sat, 21 May 2011 21:57:03 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="30789"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19/FTBOAt+UVahy5V2yIe2eSSs+d+MX4Sg=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:pP9PccpCxjJLrQnfim96K6p+XDk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5017 "Alan Fitch" wrote in message > > The VHDL 2008 support is documented under Help > Technotes > vhdl2008 Both the vhdl2008 and vhdl2008migration technotes are completely mum about the topic of generic types. They don't say they support it and they don't say it's not supported. Apparently, the answer is "no". (The business of generic types does appear to be a fairly big leap for the language.) Charles Bailey From newsfish@newsfish Fri Feb 3 13:12:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Sat, 21 May 2011 20:03:23 -0700 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <93qegsFdkkU1@mid.individual.net> Injection-Date: Sun, 22 May 2011 03:02:36 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="25967"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CaWNGJlK2Tdpu6fHJ7MmDCmlv/r5ThFc=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:fyHAMjDOz9xBLi5loODeTSBSoLQ= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5018 "Mike Treseler" wrote in message news:93qegsFdkkU1@mid.individual.net... > > -- Did you have > library ieee; > use ieee.std_logic_1164.all; > -- at the top? > > Would a generic entity need an instance and generic map? > > incr_inst : entity work.generic_mux2 > generic map ( data_type => std_ulogic) > port map ( ... ); > > Good luck. > > -- Mike Treseler Adding library ieee; use ieee.std_logic_1164.all; to the top doesn't help. Same error message. Charles Bailey From newsfish@newsfish Fri Feb 3 13:12:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a26g2000vbo.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: VHDL 2008 syntax error Date: Tue, 24 May 2011 04:00:06 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <91903f33-8fa0-4455-8f42-222c2f3f9416@a26g2000vbo.googlegroups.com> References: <93qegsFdkkU1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306234806 17590 127.0.0.1 (24 May 2011 11:00:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 May 2011 11:00:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a26g2000vbo.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5019 Hi, I have tried your example with ModelsimPE 10.0b and I got the same error message. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:12:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!s9g2000yqm.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Help Getting some VHDL code Date: Tue, 24 May 2011 16:48:35 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: NNTP-Posting-Host: 82.132.211.5 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306280915 29434 127.0.0.1 (24 May 2011 23:48:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 May 2011 23:48:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000yqm.googlegroups.com; posting-host=82.132.211.5; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5020 Hi I am trying to learn VHDL on modem design Where could I get the hdl code (I think it would be easy to learn form a already made code) for doing PSK modulation? Additionally I am looking for Communications ports -Serial, USB, Ethernet, Memory Microcontroller for DSP purpose -CPU DSP - Filtering Other Digital modulations Thank you in advance for your help! From newsfish@newsfish Fri Feb 3 13:12:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e26g2000vbz.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 05:49:57 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: NNTP-Posting-Host: 68.49.30.149 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306327797 10589 127.0.0.1 (25 May 2011 12:49:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 12:49:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e26g2000vbz.googlegroups.com; posting-host=68.49.30.149; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5021 On May 24, 7:48=A0pm, Peter wrote: > Hi I am trying to learn VHDL on modem design > > Where could I get the hdl code (I think it would be easy to learn form > a already made code) for doing PSK modulation? > > Additionally I am looking for > > Communications ports > > -Serial, USB, Ethernet, > > Memory > > Microcontroller for DSP purpose > =A0 =A0 =A0 =A0 -CPU > > DSP - Filtering > > Other Digital modulations > > Thank you in advance for your help! Opencores is a place to start for existing code. But looking at existing code is not a good way or even a viable way of learning modem design. Some of it you can learn from books. But there will be a lot you need to learn from others. Then you will do well to post in comp.dsp to ask specific questions. You are trying to learn a field that is large and complex. Don't expect it to happen overnight. Rick From newsfish@newsfish Fri Feb 3 13:12:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g28g2000yqa.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 14:55:18 -0700 (PDT) Organization: http://groups.google.com Lines: 89 Message-ID: <0ea4f008-bfe5-4c08-b3cb-d4c7cb08b03c@g28g2000yqa.googlegroups.com> References: NNTP-Posting-Host: 82.132.210.210 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306360518 19066 127.0.0.1 (25 May 2011 21:55:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 21:55:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g28g2000yqa.googlegroups.com; posting-host=82.132.210.210; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5022 On May 25, 1:49=A0pm, rickman wrote: > On May 24, 7:48=A0pm, Peter wrote: > > > > > > > Hi I am trying to learn VHDL on modem design > > > Where could I get the hdl code (I think it would be easy to learn form > > a already made code) for doing PSK modulation? > > > Additionally I am looking for > > > Communications ports > > > -Serial, USB, Ethernet, > > > Memory > > > Microcontroller for DSP purpose > > =A0 =A0 =A0 =A0 -CPU > > > DSP - Filtering > > > Other Digital modulations > > > Thank you in advance for your help! > > Opencores is a place to start for existing code. =A0But looking at > existing code is not a good way or even a viable way of learning modem > design. =A0Some of it you can learn from books. =A0But there will be a lo= t > you need to learn from others. =A0Then you will do well to post in > comp.dsp to ask specific questions. =A0You are trying to learn a field > that is large and complex. =A0Don't expect it to happen overnight. > > Rick Thanks Rick for giving a input! I've already came across that website before when I was looking for DDS. it it Opencores.org? Have you got any code and material that could I use to learn? I would like to get my hard on these books: (have you got any of those?) The student's guide to VHDL by Peter J. Ashenden System-on-a-chip: design and test by Rochit Rajsuman Applications of VHDL to circuit design By Randolph E. Harr, Alec G. Stanculescu The electronic design automation handbook By Dirk Jansen Electronic engineering, Volume 68, Issues 835-840 VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis Proceedings of the 2009 International Conference on Signals, Syatems and ... By Himanshu Soni Software defined radio: origins, drivers, and international perspectives By Wally H. W. Tuttlebee Analog circuit design: structured mixed-mode design, multi-bit sigma- delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan Customizable embedded processors: design technologies and applications By Paolo Ienne, Rainer Leupers New Data Formats for DSP Applications By Manuel Richey Signal processing in telecommunications: proceedings of the 7th International Thyrrhenian Workshop on Digital Communications, Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio Biglieri, Marco Luise Software radio architecture: object-oriented approaches to wireless systems ... By Joseph Mitola VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, Toledo ... By F=E9d=E9ration internationale pour le traitement de Delta-Sigma Understanding Delta-Sigma Data Converters by R. Schreier, G Delta Sigma Data Converters: Theory, Design and Simulation by R. Schreier, G. Temes, S Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation James C. Candy, Gabor C The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A From newsfish@newsfish Fri Feb 3 13:13:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r20g2000yqd.googlegroups.com!not-for-mail From: Peter Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Wed, 25 May 2011 15:30:28 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: References: NNTP-Posting-Host: 82.132.210.208 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306362628 17844 127.0.0.1 (25 May 2011 22:30:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 May 2011 22:30:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r20g2000yqd.googlegroups.com; posting-host=82.132.210.208; posting-account=SCzijgoAAAAa4zEhr_42BlqsvJquENQ2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UALERCHNK X-HTTP-UserAgent: Opera/9.80 (X11; Linux i686; U; en-GB) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5023 On May 25, 1:49=A0pm, rickman wrote: > On May 24, 7:48=A0pm, Peter wrote: > > > > > > > Hi I am trying to learn VHDL on modem design > > > Where could I get the hdl code (I think it would be easy to learn form > > a already made code) for doing PSK modulation? > > > Additionally I am looking for > > > Communications ports > > > -Serial, USB, Ethernet, > > > Memory > > > Microcontroller for DSP purpose > > =A0 =A0 =A0 =A0 -CPU > > > DSP - Filtering > > > Other Digital modulations > > > Thank you in advance for your help! > > Opencores is a place to start for existing code. =A0But looking at > existing code is not a good way or even a viable way of learning modem > design. =A0Some of it you can learn from books. =A0But there will be a lo= t > you need to learn from others. =A0Then you will do well to post in > comp.dsp to ask specific questions. =A0You are trying to learn a field > that is large and complex. =A0Don't expect it to happen overnight. > > Rick Thanks Rick for giving an input! I've already came across that website before when I was looking for DDS. it it Opencores.org? Have you got any code and material that could I use to learn? I would like to get my hard on these books: (have you got any of those?) The student's guide to VHDL by Peter J. Ashenden System-on-a-chip: design and test by Rochit Rajsuman Applications of VHDL to circuit design By Randolph E. Harr, Alec G. Stanculescu The electronic design automation handbook By Dirk Jansen Electronic engineering, Volume 68, Issues 835-840 VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis Proceedings of the 2009 International Conference on Signals, Syatems and ... By Himanshu Soni Software defined radio: origins, drivers, and international perspectives By Wally H. W. Tuttlebee Analog circuit design: structured mixed-mode design, multi-bit sigma- delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan Customizable embedded processors: design technologies and applications By Paolo Ienne, Rainer Leupers New Data Formats for DSP Applications By Manuel Richey Signal processing in telecommunications: proceedings of the 7th International Thyrrhenian Workshop on Digital Communications, Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio Biglieri, Marco Luise Software radio architecture: object-oriented approaches to wireless systems ... By Joseph Mitola VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, Toledo ... By F=E9d=E9ration internationale pour le traitement de Delta-Sigma Understanding Delta-Sigma Data Converters by R. Schreier, G Delta Sigma Data Converters: Theory, Design and Simulation by R. Schreier, G. Temes, S Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation James C. Candy, Gabor C The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A From newsfish@newsfish Fri Feb 3 13:13:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l26g2000yqm.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Help Getting some VHDL code Date: Thu, 26 May 2011 00:29:43 -0700 (PDT) Organization: http://groups.google.com Lines: 94 Message-ID: <9c0a1d7b-d92c-444a-aedf-daf29516d660@l26g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306394983 11366 127.0.0.1 (26 May 2011 07:29:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 26 May 2011 07:29:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l26g2000yqm.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5024 On May 25, 11:30=A0pm, Peter wrote: > On May 25, 1:49=A0pm, rickman wrote: > > > > > > > > > > > On May 24, 7:48=A0pm, Peter wrote: > > > > Hi I am trying to learn VHDL on modem design > > > > Where could I get the hdl code (I think it would be easy to learn for= m > > > a already made code) for doing PSK modulation? > > > > Additionally I am looking for > > > > Communications ports > > > > -Serial, USB, Ethernet, > > > > Memory > > > > Microcontroller for DSP purpose > > > =A0 =A0 =A0 =A0 -CPU > > > > DSP - Filtering > > > > Other Digital modulations > > > > Thank you in advance for your help! > > > Opencores is a place to start for existing code. =A0But looking at > > existing code is not a good way or even a viable way of learning modem > > design. =A0Some of it you can learn from books. =A0But there will be a = lot > > you need to learn from others. =A0Then you will do well to post in > > comp.dsp to ask specific questions. =A0You are trying to learn a field > > that is large and complex. =A0Don't expect it to happen overnight. > > > Rick > > Thanks Rick for giving an input! > > I've already came across that website before when I was looking for > =A0DDS. it it Opencores.org? > > Have you got any code and material that could I use to learn? > > I would like to get my hard on these books: (have you got any of > =A0those?) > > The student's guide to VHDL by Peter J. Ashenden > =A0System-on-a-chip: design and test by Rochit Rajsuman > =A0Applications of VHDL to circuit design By Randolph E. Harr, Alec G. > =A0Stanculescu > =A0The electronic design automation handbook By Dirk Jansen > =A0Electronic engineering, Volume 68, Issues 835-840 > =A0VHDL-2008: just the new stuff By Peter J. Ashenden, Jim Lewis > =A0Proceedings of the 2009 International Conference on Signals, Syatems > =A0and ... By Himanshu Soni > =A0Software defined radio: origins, drivers, and international > =A0perspectives By Wally H. W. Tuttlebee > =A0Analog circuit design: structured mixed-mode design, multi-bit > sigma- > =A0delta ... By Michiel Steyaert, Arthur H. M. van Roermund, Johan > =A0Customizable embedded processors: design technologies and > applications > =A0By Paolo Ienne, Rainer Leupers > =A0New Data Formats for DSP Applications By Manuel Richey > =A0Signal processing in telecommunications: proceedings of the 7th > =A0International Thyrrhenian Workshop on Digital Communications, > =A0Viareggio, Italy, September 10-14, 1995, Volume 1995 by Ezio > Biglieri, > =A0Marco Luise > =A0Software radio architecture: object-oriented approaches to wireless > =A0systems ... By Joseph Mitola > =A0VHDL user's forum in Europe : SIG-VHDL Spring'97 working conference, > =A0Toledo ... By F=E9d=E9ration internationale pour le traitement de > > Delta-Sigma > =A0Understanding Delta-Sigma Data Converters by R. Schreier, G > =A0Delta Sigma Data Converters: Theory, Design and Simulation by R. > =A0Schreier, G. Temes, S > =A0Oversampling Delta-Sigma Data Converters: Theory, Design and > =A0Simulation James C. Candy, Gabor C > =A0The system designer's guide to VHDL-AMS: analog, mixed-signal, and > =A0mixed ... By Peter J. Ashenden, Gregory D. Peterson, Darrell A Have you tried checking amazon.com? Or your local library? From newsfish@newsfish Fri Feb 3 13:13:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!newsfeed.neostrada.pl!unt-exc-02.news.neostrada.pl!unt-spo-a-01.news.neostrada.pl!news.neostrada.pl.POSTED!not-for-mail Date: Fri, 27 May 2011 04:53:37 +0200 From: Piotr User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pl; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: std_logic_vector to integer Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 39 Message-ID: <4ddf1231$0$2456$65785112@news.neostrada.pl> Organization: Telekomunikacja Polska NNTP-Posting-Host: 83.27.148.7 X-Trace: 1306464817 unt-rea-a-01.news.neostrada.pl 2456 83.27.148.7:1720 X-Complaints-To: abuse@news.neostrada.pl Xref: feeder.eternal-september.org comp.lang.vhdl:5025 Hi! I'm beginner. I can't solve this problem. I'm trying to convert std_logic_vector to integer. It doesn't work. I have an error: line 215: Different types for port on entity and component for ------------ -- Code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; entity VectorToInteger is port ( Clk_50MHz: in std_logic; i: in std_logic_vector(7 downto 0); o: out Integer range 300 downto -127); end VectorToInteger; architecture Behavioral of VectorToInteger is begin process(Clk_50MHz, i) begin if (rising_edge(Clk_50MHz)) then o <= conv_integer(i); end if; end process; end Behavioral; ----------------- This is very important for me. Please help me... Piotr From newsfish@newsfish Fri Feb 3 13:13:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "scrts" Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer Date: Fri, 27 May 2011 08:07:19 +0300 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: <4ddf1231$0$2456$65785112@news.neostrada.pl> Injection-Date: Fri, 27 May 2011 05:07:15 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="iT5NBGfOsLgPoft0V0gh3A"; logging-data="26750"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/kEnzGC4hfbNruSVDJD/m/" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6090 X-RFC2646: Format=Flowed; Response X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:bFXiEtNR7z+Ij11YDPs+eaC4NRU= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5026 "Piotr" wrote in message news:4ddf1231$0$2456$65785112@news.neostrada.pl... > Hi! > > I'm beginner. I can't solve this problem. I'm trying to convert > std_logic_vector to integer. > > It doesn't work. I have an error: > line 215: Different types for port on entity and component for > > > ------------ > -- Code: > > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_signed.all; Do not use std_logic_arith and std_logic_signed. Use numeric_std instead. You will find all the required functions there From newsfish@newsfish Fri Feb 3 13:13:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!l18g2000yql.googlegroups.com!not-for-mail From: hhanff Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer Date: Thu, 26 May 2011 22:30:19 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: <55132911-f064-416d-a541-d64aff4b4dbd@l18g2000yql.googlegroups.com> References: <4ddf1231$0$2456$65785112@news.neostrada.pl> NNTP-Posting-Host: 178.3.205.199 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1306474219 2180 127.0.0.1 (27 May 2011 05:30:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 May 2011 05:30:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l18g2000yql.googlegroups.com; posting-host=178.3.205.199; posting-account=TIldIAoAAAD4kpJj3f9wLt8pW9aqX3pw User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5027 On 27 Mai, 07:07, "scrts" wrote: > "Piotr" wrote in message > > news:4ddf1231$0$2456$65785112@news.neostrada.pl... > > > > > > > > > > > Hi! > > > I'm beginner. I can't solve this problem. I'm trying to convert > > std_logic_vector to integer. > > > It doesn't work. I have an error: > > line 215: Different types for port on entity and component for > > > > > ------------ > > -- Code: > > > library IEEE; > > use IEEE.std_logic_1164.all; > > use IEEE.std_logic_arith.all; > > use IEEE.std_logic_signed.all; > > Do not use std_logic_arith and std_logic_signed. Use numeric_std instead. > You will find all the required functions there If you do not know how to convert between different types using numeric_std, you might find this http://www.lothar-miller.de/s9y/uploads/Bilder/Usage_of_numeric_std.pdf helpfull. Greetings from rainy Bremen, hhanff From newsfish@newsfish Fri Feb 3 13:13:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!newsfeed.neostrada.pl!unt-exc-01.news.neostrada.pl!unt-spo-b-01.news.neostrada.pl!news.neostrada.pl.POSTED!not-for-mail Date: Fri, 27 May 2011 08:17:11 +0200 From: Piotr User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; pl; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: std_logic_vector to integer References: <4ddf1231$0$2456$65785112@news.neostrada.pl> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-2; format=flowed Content-Transfer-Encoding: 7bit Lines: 3 Message-ID: <4ddf41e7$0$2453$65785112@news.neostrada.pl> Organization: Telekomunikacja Polska NNTP-Posting-Host: 83.27.150.105 X-Trace: 1306477031 unt-rea-a-01.news.neostrada.pl 2453 83.27.150.105:4171 X-Complaints-To: abuse@news.neostrada.pl Xref: feeder.eternal-september.org comp.lang.vhdl:5028 Thank You very much. I've solved the problem. Piotr From newsfish@newsfish Fri Feb 3 13:13:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!j13g2000pro.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: SystemRDL Date: Tue, 31 May 2011 16:22:13 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> References: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> NNTP-Posting-Host: 203.58.241.190 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1306884134 28414 127.0.0.1 (31 May 2011 23:22:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 May 2011 23:22:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j13g2000pro.googlegroups.com; posting-host=203.58.241.190; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5029 Clearly not a popular standard then? Anyone using at all? On May 20, 9:12=A0am, Dal wrote: > I have come across the SystemRDL standard to define a devices register > space. =A0Are there any open source tools for generating documentation > from systemRDL? > > I currently use propriety scripts for converting a register definition > spreadsheet into code. =A0Before I bash out another scripts to generate > a document I thought this could be an opportunity to dabble with this > new standard. > > I don't need all the verification bells and whistles that seem to be > offered by commercial tools - just the documentation generator part. From newsfish@newsfish Fri Feb 3 13:13:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Tue, 31 May 2011 18:27:00 -0500 Date: Tue, 31 May 2011 16:27:06 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: SystemRDL References: <61fc1cde-f427-4c6e-8760-e6035f77da0b@r35g2000prj.googlegroups.com> <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> In-Reply-To: <912d5c26-28d5-479c-b033-79539dcd1540@j13g2000pro.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 28 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-sGH8AZ6rmyEjQNjIw1gedvg+uauvVQkaaPDjb/a9iG0KxZhAH6f33DxqKEYegUkIBqFFO21Eoyy/NKC!4m0SD5w6rHm+bH2WWHM+oB0nezg+1F9ndmLoGmEz6NDFf2mNtfdHTRJGT3tAKoJbi47Wd6mnUdOA!Zw== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2330 Xref: feeder.eternal-september.org comp.lang.vhdl:5030 On 5/31/2011 4:22 PM, Dal wrote: > Clearly not a popular standard then? > > Anyone using at all? > > > On May 20, 9:12 am, Dal wrote: >> I have come across the SystemRDL standard to define a devices register >> space. Are there any open source tools for generating documentation >> from systemRDL? >> >> I currently use propriety scripts for converting a register definition >> spreadsheet into code. Before I bash out another scripts to generate >> a document I thought this could be an opportunity to dabble with this >> new standard. >> >> I don't need all the verification bells and whistles that seem to be >> offered by commercial tools - just the documentation generator part. > I gave it a look over after you asked; since I'm in the process of putting together a proprietary solution to do much the same. It seemed too complicated by half. Which is, I suppose, better than IP-XACT, which as near as I can tell is too complicated by tenfold. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!noris.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!news.uni-stuttgart.de!news.nask.pl!news.nask.org.pl!news.icm.edu.pl!not-for-mail From: Wojciech M. Zabolotny Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Connecting of IP core simulated in GHDL to pseudoterminal via UART-like interface Followup-To: comp.arch.fpga Date: Thu, 2 Jun 2011 17:45:10 +0000 (UTC) Organization: Dzial Sieciowy ICM, Uniwersytet Warszawski Lines: 53 Message-ID: NNTP-Posting-Host: koral.ise.pw.edu.pl X-Trace: news.net.icm.edu.pl 1307036710 27164 194.29.161.2 (2 Jun 2011 17:45:10 GMT) X-Complaints-To: usenet@news.net.icm.edu.pl NNTP-Posting-Date: Thu, 2 Jun 2011 17:45:10 +0000 (UTC) Keywords: GHDL, VPI, VHDL, simulation, UART, interactive, debug User-Agent: slrn/pre1.0.0-18 (Linux) Xref: feeder.eternal-september.org comp.arch.fpga:15640 comp.lang.vhdl:5031 When working with simulated soft CPUs to be implemented in FPGA, I often needed a possibility to connect terminal emulator (e.g. Minicom) or my own program to serial port of the simulated IP core. Finally I've found a solution, which seems to be good enough to share it with others. I use the pseudoterminal (ptmx) found in Linux to establish communication between GHDL simulator and my terminal program. However GHDL does not offer functions needed to control pseudoterminals, therefore I've prepared a small C library (ghdl_pty.c) providing necessary functions via VPI. Additionally I needed to provide nonblocking reading from the pseudoterminal, to avoid stopping of simulation when no data is available this functionality is also implemented in ghdl_pty.c, in function ghdl_pty_read. >From the VHDL side, my pseudo UART is visible as: component ghdl_uart port ( data_out : out std_logic_vector(7 downto 0); data_in : in std_logic_vector(7 downto 0); dav : out std_logic; -- received data available ready : out std_logic; -- there is free space in transmit buffer empty : out std_logic; -- the transmit buffer is empty rd : in std_logic; -- asynchronous read strobe wr : in std_logic -- asynchronous write strobe ); end component; When new data arrives, "dav" goes high. To read the data, you should set "rd" to '1' and the data will be visible on "data_out". If no more data are in the input queue, "dav" goes low. If you want to write data, you put them on "data_in", and rise "wr". The data are transmitted to the output queue, and later transmitted to the pseudoterminal. Full sources, published as public domain are available on alt.sources usenet group, in thread "Pseudo UART allowing to connect via pseudoterminal to GHDL simulated IP core" ( news: http://http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba ) You can find more information in the "desc.txt" file available in the archive contained in the alt.sources message. I hope, that the emulated UART will be useful for you. Wojciech M. Zabolotny wzabise.pw.edu.pl From newsfish@newsfish Fri Feb 3 13:13:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Vivek Menon Newsgroups: comp.lang.vhdl Subject: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 17:00:10 -0700 (PDT) Organization: http://groups.google.com Lines: 39 Message-ID: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 146.5.8.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307491210 25106 127.0.0.1 (8 Jun 2011 00:00:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 00:00:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.5.8.107; posting-account=GtBy8QoAAADwGUEYPAR_dKzOh-XAf-VG User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5033 I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active. entity shift_out is Port ( --Inputs clk : in std_logic; en : in std_logic; rst : in std_logic; in1 : in std_logic_vector(31 downto 0); -- Outputs shift_val : out std_logic_vector(31 downto 0) ); end entity shift_out; architecture arch of shift_out is signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0'); ... process (clk, rst, in1, en) is begin if rst = '1' then shift_t1 <= (others=>'0'); shift_val <= (others=>'0'); elsif rising_edge(clk) then if (en = '1') then shift_t1 <= shift_t1 ror x"10"; shift_t1 <= in1; end if ; end if; end process; shift_val <= shift_t1; end arch; I am confused with the ror approach, I have tried array slicing and that did not simulate as well. ANy suggestions?? From newsfish@newsfish Fri Feb 3 13:13:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e21g2000vbz.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 23:28:30 -0700 (PDT) Organization: http://groups.google.com Lines: 61 Message-ID: <5e7162d0-1002-492e-a9c1-30fb9c9cc4e1@e21g2000vbz.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307514512 32652 127.0.0.1 (8 Jun 2011 06:28:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 06:28:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e21g2000vbz.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.04 (lucid) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5034 On 8 Jun., 02:00, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > > entity shift_out is > =A0 =A0 =A0 =A0 Port ( > =A0 =A0 =A0 =A0 --Inputs > =A0 =A0 =A0 =A0 clk =A0 =A0 : in std_logic; > =A0 =A0 en =A0 =A0 =A0: in std_logic; > =A0 =A0 rst =A0 =A0 : in std_logic; > =A0 =A0 =A0 =A0 in1 =A0 =A0 : in =A0std_logic_vector(31 downto 0); > > =A0 =A0 =A0 =A0 -- Outputs > =A0 =A0 =A0 =A0 shift_val : out std_logic_vector(31 downto 0) > =A0 =A0 =A0); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 =A0 : std_logic_vector(31 downto 0) :=3D (others =3D> '0'= ); > ... > =A0 =A0 =A0 =A0 process (clk, rst, in1, en) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rst =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 <=3D (others=3D>= '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_val <=3D (others=3D= >'0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (en =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D shift_t1 ror x"10"; =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D in1; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if ; =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 shift_val <=3D shift_t1; > > end arch; > > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. > ANy suggestions?? Hi, What error messages are you getting from the tools? Have you checked wether the ror function works for the data type you are using? Another way to shift/rotate vectors goes like this: shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); -- simple rotate by one, missing an input, but you can overwrite the LSB Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:13:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t16g2000vbi.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Tue, 7 Jun 2011 23:36:23 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: <2afe77ba-4382-4111-9f70-7244096d51db@t16g2000vbi.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307514984 25924 127.0.0.1 (8 Jun 2011 06:36:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 06:36:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t16g2000vbi.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.17) Gecko/20110422 Ubuntu/10.04 (lucid) Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5035 On 8 Jun., 02:00, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > > entity shift_out is > =A0 =A0 =A0 =A0 Port ( > =A0 =A0 =A0 =A0 --Inputs > =A0 =A0 =A0 =A0 clk =A0 =A0 : in std_logic; > =A0 =A0 en =A0 =A0 =A0: in std_logic; > =A0 =A0 rst =A0 =A0 : in std_logic; > =A0 =A0 =A0 =A0 in1 =A0 =A0 : in =A0std_logic_vector(31 downto 0); > > =A0 =A0 =A0 =A0 -- Outputs > =A0 =A0 =A0 =A0 shift_val : out std_logic_vector(31 downto 0) > =A0 =A0 =A0); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 =A0 : std_logic_vector(31 downto 0) :=3D (others =3D> '0'= ); > ... > =A0 =A0 =A0 =A0 process (clk, rst, in1, en) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if rst =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 <=3D (others=3D>= '0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_val <=3D (others=3D= >'0'); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (en =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D shift_t1 ror x"10"; =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 shift_t1 = <=3D in1; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if ; =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; > > =A0 =A0 =A0 =A0 shift_val <=3D shift_t1; > > end arch; > > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. > ANy suggestions?? Hi, What error messages are you getting from the tools? Have you checked wether the ror function works for the data type you are using? Another way to shift/rotate vectors goes like this: shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); -- simple rotate by one, missing an input, but you can overwrite the LSB Also there's some big flaw in your approach. You have no signal to distinguish between load and shift operation. Enable is working for both actions and so you are only always loading when enable is active and do not see any effect of the ror function. Do something like this: Define a port load : in std_logic; and in your enable branch: if load =3D '1' then shift_t1 <=3D in1; else -- rotate shift_t1 <=3D shift_t1(shift_t1'length-2 downto 0) & shift_t1(shift_t1'length-1); end if; Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:13:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!h12g2000pro.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Wed, 8 Jun 2011 06:18:43 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <48b2d219-dbf1-4e9e-95e5-dd770dd1150f@h12g2000pro.googlegroups.com> References: NNTP-Posting-Host: 192.91.147.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307539347 24990 127.0.0.1 (8 Jun 2011 13:22:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 13:22:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000pro.googlegroups.com; posting-host=192.91.147.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLEUCHNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; InfoPath.2; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; MS-RTC LM 8; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5036 Take shift_val out of the clocked process. It should not be assigned in both the process and the concurrent assignment statement. Also, remove everything but clk and rst from the process sensitivity list. Andy From newsfish@newsfish Fri Feb 3 13:13:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Wed, 8 Jun 2011 08:48:32 -0700 (PDT) Organization: http://groups.google.com Lines: 50 Message-ID: <01a0ad2e-f672-47db-90d5-a6b6d6b81c26@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 74.126.85.132 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307548113 31561 127.0.0.1 (8 Jun 2011 15:48:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 15:48:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=74.126.85.132; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB7.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5037 On Jun 7, 8:00=A0pm, Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that kee= ps shifting the input data as long as the enable pin is active. > Have you simulated your design and does it work as intended? If not, then get that working before synthesizing. If so, then I'm surprised because... > if (en =3D '1') then > =A0 shift_t1 <=3D shift_t1 ror x"10"; > =A0 =A0 shift_t1 <=3D in1; The second assignment to shift_t1 will override the first assignment. The net of all this is that the assignment with the 'ror' won't do anything. > I am confused with the ror approach, I have tried array slicing and that = did not simulate as well. Until you get the simulation working properly, it will likely not make much sense for you to try to synthesize. You have a basic issue with your design in that you don't have a method for loading and for shifting the data. Typically one would have a 'load' and a 'shift' input but it might be that you intend to load any time you're not shifting in which case you should have written if (en =3D '1') then shift_t1 <=3D shift_t1 ror x"10"; else -- KJ added shift_t1 <=3D in1; ... > ANy suggestions?? Also, the 'ror' function is defined for unsigned types, not std_logic_vector. function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; I would suggest changing the data type of shift_t1 shift_t1 : unsigned(31 downto 0); Then convert to/from std_logic_vectors on the various assignments. Also see Andy's suggestions. To have the compiler catch the first error that Andy pointed out, consider using std_ulogic rather than std_logic. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail Message-Id: <4def9b9f$0$49048$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Parallel in, Parallel out shift register Newsgroups: comp.lang.vhdl Date: Wed, 08 Jun 2011 17:56:15 +0200 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 100 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1307548575 news.xs4all.nl 49048 puiterl/[::ffff:195.242.97.150]:36768 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5038 Vivek Menon wrote: > I am trying to synthesize and simulate a parallel shift register that > keeps shifting the input data as long as the enable pin is active. > > entity shift_out is > Port ( > --Inputs > clk : in std_logic; > en : in std_logic; > rst : in std_logic; > in1 : in std_logic_vector(31 downto 0); > > -- Outputs > shift_val : out std_logic_vector(31 downto 0) > ); > end entity shift_out; > > architecture arch of shift_out is > > signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0'); > ... > process (clk, rst, in1, en) is > begin > if rst = '1' then > shift_t1 <= (others=>'0'); > shift_val <= (others=>'0'); > elsif rising_edge(clk) then > if (en = '1') then > shift_t1 <= shift_t1 ror x"10"; > shift_t1 <= in1; > end if ; > end if; > end process; > > shift_val <= shift_t1; > > end arch; > > I am confused with the ror approach, Me too. What ror operator? What packages are you using? The only ror operator that I know of is from ieee.numeric_std: ------------------------------------------------------------------------------ -- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 -- compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) ------------------------------------------------------------------------------ -- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment -- out the function (declaration and body) for VHDL 1076-1987 -- compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: ROTATE_RIGHT(ARG, COUNT) > I have tried array slicing and that did not simulate as well. > ANy suggestions?? Posting error messages would be nice. Or observed/expected behaviour. I also suspect a missing else: if (en = '1') then shift_t1 <= shift_t1 ror x"10"; else --< !! shift_t1 <= in1; end if; And for the shift operation I would suggest something like: shift_t1 <= shift_t1(shift_t1'low) & shift_t1(shift_t1'high downto shift_t1'low+1); Which is the same as shift_t1 <= shift_t1(0) & shift_t1(31 downto 1); without the hard coded numbers. For the rest: remove 'in1' and 'en' from the sensitivity list. They are not needed. Oh, and resetting shift_val is not needed: it is not a flip-flop, shift_t1 is. And why using shift_t1 at all? Why not just shift_val? There is no need for the extra signal. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:13:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tranq7.tranquility.net!feeder.erje.net!fdn.fr!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!l6g2000vbn.googlegroups.com!not-for-mail From: JohnSmith Newsgroups: comp.lang.vhdl Subject: simulation script Date: Wed, 8 Jun 2011 09:32:26 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> NNTP-Posting-Host: 84.236.127.63 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307550746 10876 127.0.0.1 (8 Jun 2011 16:32:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 16:32:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l6g2000vbn.googlegroups.com; posting-host=84.236.127.63; posting-account=xPZEcAoAAABZVb8HlkUfjHjXa4_YJ-uv User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5039 Hi, How can I use an environment variable in a ".do" script running it in the modelsim window? I tried the windows environment variable in % characters, but doesnt work. Absolute paths work but I want use this scripts on different computers. vsim -sdftyp {/UUT=%MYDIR%/dir/.../timesim.sdf} ... Thanks From newsfish@newsfish Fri Feb 3 13:13:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l14g2000pro.googlegroups.com!not-for-mail From: MJB Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Wed, 8 Jun 2011 09:45:04 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> NNTP-Posting-Host: 199.46.200.230 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307551504 363 127.0.0.1 (8 Jun 2011 16:45:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 16:45:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l14g2000pro.googlegroups.com; posting-host=199.46.200.230; posting-account=XsPsLQoAAABg05Q6wOj-nB1nqE0qsC-B User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5040 On Jun 8, 9:32=A0am, JohnSmith wrote: > Hi, > > How can I use an environment variable in a ".do" script running it in > the modelsim window? > > I tried the windows environment variable in % characters, but doesnt > work. Absolute paths work but I want use this scripts on different > computers. > > vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > Thanks Try using the Tcl env() function. Modelsim's shell is essentially a Tcl command line evironment and the .do files are .tcl scripts. to get your directory, try /UUT=3Denv(MYDIR)/ ..... I don't have a Modelsim installation handy so this is just off the top of my head. Hope you find the solution! From newsfish@newsfish Fri Feb 3 13:13:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: JohnSmith Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Wed, 8 Jun 2011 10:00:54 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> NNTP-Posting-Host: 84.236.127.63 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307552454 27974 127.0.0.1 (8 Jun 2011 17:00:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Jun 2011 17:00:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=84.236.127.63; posting-account=xPZEcAoAAABZVb8HlkUfjHjXa4_YJ-uv User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5041 On Jun 8, 6:45=A0pm, MJB wrote: > On Jun 8, 9:32=A0am, JohnSmith wrote: > > > Hi, > > > How can I use an environment variable in a ".do" script running it in > > the modelsim window? > > > I tried the windows environment variable in % characters, but doesnt > > work. Absolute paths work but I want use this scripts on different > > computers. > > > vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > > Thanks > > Try using the Tcl env() function. =A0Modelsim's shell is essentially a > Tcl command line evironment and the .do files are .tcl scripts. > > to get your directory, try /UUT=3Denv(MYDIR)/ ..... > > I don't have a Modelsim installation handy so this is just off the top > of my head. =A0Hope you find the solution! Doesnt work.. From newsfish@newsfish Fri Feb 3 13:13:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!69.16.177.254.MISMATCH!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe21.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-GB; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: simulation script References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110608-1, 08/06/2011), Outbound message X-Antivirus-Status: Clean Lines: 36 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe21.ams2 1307605525 82.31.236.233 (Thu, 09 Jun 2011 07:45:25 UTC) NNTP-Posting-Date: Thu, 09 Jun 2011 07:45:25 UTC Organization: virginmedia.com Date: Thu, 09 Jun 2011 08:45:21 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5042 On 08/06/2011 18:00, JohnSmith wrote: > On Jun 8, 6:45 pm, MJB wrote: >> On Jun 8, 9:32 am, JohnSmith wrote: >> >>> Hi, >> >>> How can I use an environment variable in a ".do" script running it in >>> the modelsim window? >> >>> I tried the windows environment variable in % characters, but doesnt >>> work. Absolute paths work but I want use this scripts on different >>> computers. >> >>> vsim -sdftyp {/UUT=%MYDIR%/dir/.../timesim.sdf} ... >> >>> Thanks >> >> Try using the Tcl env() function. Modelsim's shell is essentially a >> Tcl command line evironment and the .do files are .tcl scripts. >> >> to get your directory, try /UUT=env(MYDIR)/ ..... >> >> I don't have a Modelsim installation handy so this is just off the top >> of my head. Hope you find the solution! > > Doesnt work.. > MJB forgot the variable sign, vsim -sdftyp /UUT=$env(MYDIR)... Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:13:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g24g2000vbz.googlegroups.com!not-for-mail From: Matheus Arleson Newsgroups: comp.lang.vhdl Subject: generic circuit for read data from n files Date: Thu, 9 Jun 2011 10:42:40 -0700 (PDT) Organization: http://groups.google.com Lines: 57 Message-ID: <6ac0bf07-8c41-49ad-bf06-447112861e69@g24g2000vbz.googlegroups.com> NNTP-Posting-Host: 189.90.160.57 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307641360 17030 127.0.0.1 (9 Jun 2011 17:42:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 9 Jun 2011 17:42:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g24g2000vbz.googlegroups.com; posting-host=189.90.160.57; posting-account=AlwOaQoAAAAqhN3ZjLkuhW6ExoGtHdap User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.24 (KHTML, like Gecko) Ubuntu/10.04 Chromium/11.0.696.71 Chrome/11.0.696.71 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5043 hello, I'm currently working on a component that has the following behavior: 1) control component: ENTITY CONTROL IS GENERIC (FILE_NUMBER: NATURAL: =3D 10); PORT (FINISHED: IN STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0); CLK: IN std_logic; RST: IN std_logic; ENABLE: OUT STD_LOGIC_VECTOR ((FILE_NUMBER - 1) downto 0)); END CONTROL; 1.1 - Has the function of signaling which file must be read. It indicates that through a bit of door ENABLE. 1.2 - when the file finished being read, it indicates through a bit of door FINISHED. 1.3 - The control then passes to another file and repeat 1 and 2 until no more files to be read. ------------------------- 2) component of the reading of files ENTITY IS ARQ_MOD GENERIC (DATA_SIZE: NATURAL: =3D 16); PORT (ENABLE: IN std_logic; FINISHED: OUT std_logic; OUTPUT_DATA: OUT STD_LOGIC_VECTOR ((DATA_SIZE - 1) downto 0)); ARQ_MOD END; 1.1 - Has the function to open a file when the door ENABLE =3D '1 '. 1.2 - Read the file until the end. 1.3 - FINISHED =3D '1 '. indicates that the file over. 1.4 - OUTPUT_DATA =3D 'Z'. because the modules file are all connected to a bus. -------------------------------- need help on the following issues: * A plan to use a control unit and connect a number N of modules file to this control unit, for example using a LOOP GENERATE. the output of them was connected to a single bus. When ENABLE =3D '0 '-> OUTPUT_DATA =3D' Z ', then only the module in use has possession of the bus. * I would like to know how to pass the path of the file to file_open dynamically. * also, i need some ideas of implementation.... here is the idea of =E2=80=8B=E2=80=8Bthe circuit. http://www.photoshop.com/users/masx/...b35e3090d4c66c thanks. From newsfish@newsfish Fri Feb 3 13:13:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!17g2000prr.googlegroups.com!not-for-mail From: Amish Rughoonundon Newsgroups: comp.lang.vhdl Subject: divide by zero error from XILINX ISE Date: Fri, 10 Jun 2011 08:53:59 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> NNTP-Posting-Host: 65.116.131.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307721353 15024 127.0.0.1 (10 Jun 2011 15:55:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jun 2011 15:55:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 17g2000prr.googlegroups.com; posting-host=65.116.131.6; posting-account=EkeN9woAAABH74ilPlXRsoxaDuvo-cEm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5044 Hi, I have this code. XILINX ISE Is giving me an error HDLParsers:866 "Division by zero" during synthesis. Why is that? Thanks for the help [CODE] CONSTANT CLOCK_FREQUENCY : integer := 50000000; -- Input clock frequency in hertz CONSTANT SWITCHING_FREQUENCY : integer := 400000; -- date drive frequency in hertz CONSTANT CLOCK_END_RAMP_RESET_A : integer := INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ REAL(CLOCK_FREQUENCY)))-1; [/CODE] From newsfish@newsfish Fri Feb 3 13:13:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeds.phibee-telecom.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <4df25005$0$49047$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden Subject: Re: divide by zero error from XILINX ISE Newsgroups: comp.lang.vhdl Date: Fri, 10 Jun 2011 19:10:29 +0200 References: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 33 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1307725829 news.xs4all.nl 49047 puiterl/[::ffff:195.242.97.150]:50857 X-Complaints-To: abuse@xs4all.nl Xref: feeder.eternal-september.org comp.lang.vhdl:5045 Amish Rughoonundon wrote: > Hi, > I have this code. XILINX ISE Is giving me an error HDLParsers:866 > "Division by zero" during synthesis. Why is that? Thanks for the help > > [CODE] > CONSTANT CLOCK_FREQUENCY : integer := 50000000; -- Input > clock frequency in hertz > > CONSTANT SWITCHING_FREQUENCY : integer := 400000; -- date > drive frequency in hertz > > CONSTANT CLOCK_END_RAMP_RESET_A : integer := > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ > REAL(CLOCK_FREQUENCY)))-1; > [/CODE] I have no idea. One thing I do know: your code looks overcomplicated (to me). If I'm not mistaken, the above is identical to: constant CLOCK_END_RAMP_RESET_A : integer := integer(0.5 * real(CLOCK_FREQUENCY) / real(SWITCHING_FREQUENCY)) - 1; For the rest: I don't have real experience with Xilinx (or any other synthesizer for that matter). -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:13:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Vivek Menon Newsgroups: comp.lang.vhdl Subject: Re: Parallel in, Parallel out shift register Date: Fri, 10 Jun 2011 15:15:14 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <111ee521-27c3-49da-89b1-420dc14a5cef@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 146.5.8.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1307744116 1239 127.0.0.1 (10 Jun 2011 22:15:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 10 Jun 2011 22:15:16 +0000 (UTC) In-Reply-To: <4def9b9f$0$49048$e4fe514c@news.xs4all.nl> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=146.5.8.107; posting-account=GtBy8QoAAADwGUEYPAR_dKzOh-XAf-VG User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5046 Thanks for the tips, I was trying to synthesize a shift register using array slicing. Since that was not working, I tried all the remaining options, ror, sra, srl, etc. Here's how I did it finally: architecture arch of shift_out is -- Signals signal shift_t1 : std_logic_vector(1727 downto 0) := (others => '0'); begin process (clk, rst) is begin if rst = '1' then shift_t1 <= (others=>'0'); elsif rising_edge(clk) then if (load = '1') then shift_t1 <= in1; elsif (shift_en ='1') then shift_t1 <= shift_t1(15 downto 0) & shift_t1(1727 downto 16); end if ; end if; end process; shift_val <= shift_t1(15 downto 0); end architecture arch; From newsfish@newsfish Fri Feb 3 13:13:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c26g2000vbq.googlegroups.com!not-for-mail From: Gabor Sz Newsgroups: comp.lang.vhdl Subject: Re: divide by zero error from XILINX ISE Date: Sat, 11 Jun 2011 09:06:11 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <46930f5f-d9fe-4008-babb-747d8916ca56@c26g2000vbq.googlegroups.com> References: <7460e134-de1c-46b7-9983-60576fd9d69f@17g2000prr.googlegroups.com> NNTP-Posting-Host: 71.255.155.168 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307808372 22257 127.0.0.1 (11 Jun 2011 16:06:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 11 Jun 2011 16:06:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c26g2000vbq.googlegroups.com; posting-host=71.255.155.168; posting-account=cfJiJQkAAABsT-oneW1D9Slld_atFpud User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5047 On Jun 10, 11:53=A0am, Amish Rughoonundon wrote: > Hi, > =A0I have this code. XILINX ISE Is giving me an error HDLParsers:866 > "Division by zero" during synthesis. Why is that? Thanks for the help > > [CODE] > CONSTANT CLOCK_FREQUENCY =A0 =A0 =A0 =A0: integer :=3D 50000000; =A0 =A0 = =A0-- Input > clock frequency in hertz > > CONSTANT SWITCHING_FREQUENCY =A0 =A0: integer :=3D 400000; =A0 =A0 =A0 = =A0-- date > drive frequency in hertz > > CONSTANT CLOCK_END_RAMP_RESET_A =A0 =A0 =A0 =A0 =A0 =A0 : integer :=3D > INTEGER((REAL(1)/(REAL(2)*REAL(SWITCHING_FREQUENCY)))/(REAL(1)/ > REAL(CLOCK_FREQUENCY)))-1; > [/CODE] I'm going to take a wild guess that Xilinx is taking 1/CLOCK_FREQUENCY and converting it to integer zero, instead of using a real for the final divide operation. Perhaps using Paul's simplified version will fix the problem. The other possibility is that Xilinx's real format has an underflow for 1/50000000. This might happen if they don't use enough bits when dividing the mantissas for the intermediate result. Either way it could be called a bug. IEEE floating point has defined the temporary precision just for this sort of issue. -- Gabor From newsfish@newsfish Fri Feb 3 13:13:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Post-synthesis simulation errors at generic map Date: Mon, 13 Jun 2011 08:49:53 -0700 (PDT) Organization: http://groups.google.com Lines: 64 Message-ID: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 20.132.68.148 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307980194 9025 127.0.0.1 (13 Jun 2011 15:49:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jun 2011 15:49:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=20.132.68.148; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5049 I think this may be a common problem for the pros out there... I have a project where I use top-level generics to size aspects of the desi= gn. I allow the synthesis tool to use the default bindings, but I like to a= ssign different values during my behavioral testbench to speed things up. Pre-synthesis simulation works great, but post-synthesis or post-route simu= lations crash because the testbench is trying to map generics to a synthesi= zed component with no generics. This must come up often -- is there a stand= ard strategy for this? Configuration=20 Code snippet from the testbench: entity testbench is generic ( HPIXELS : positive :=3D 251; VPIXELS : positive :=3D 2 ); end entity; =20 architecture bhvr of testbench is=20 =20 component camera_top generic ( HPIXELS : positive :=3D 320; VPIXELS : positive :=3D 240; PIXDEPTH : integer range 1 to 16 :=3D 16 ); port ( ... ); end component; begin uut : camera_top generic map ( HPIXELS =3D> HPIXELS, VPIXELS =3D> VPIXELS ) port map ( ... ); end architecture; Errors from simulator (ModelSim PE 10.0a): # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'PIXDEPTH' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'VPIXELS' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut # ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for compo= nent at 'uut'. # (Generic 'HPIXELS' is not on the entity.) # (Entity has no generics.) # Region: /testbench/uut Thanks all. From newsfish@newsfish Fri Feb 3 13:13:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!postnews.google.com!28g2000yqu.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Mon, 13 Jun 2011 12:38:16 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1307993896 15620 127.0.0.1 (13 Jun 2011 19:38:16 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 13 Jun 2011 19:38:16 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 28g2000yqu.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5050 On Jun 13, 11:49=A0am, alivingstone wrote: > I think this may be a common problem for the pros out there... > > Pre-synthesis simulation works great, but post-synthesis or post-route si= mulations crash because the testbench is trying to map generics to a synthe= sized component with no generics. This must come up often -- is there a sta= ndard strategy for this? Configuration > To do this you need to compile and produce a post route simulation file for each and every set of generics that you would like to simulate. In your case, for each specific combination of HPIXELS, VPIXELS and PIXDEPTH that you want to simulate you need to do a new build that has that specific setting and then repeat that process for each set of settings. Then in the testbench you'll need to select (via a generate statement) which specific post-route simulation you want to instantiate. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 14 Jun 2011 08:36:47 -0500 Date: Tue, 14 Jun 2011 14:36:47 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 28 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Kg8DzumCVZQ2qTwXygtQOy/5wy1w2Xve/hT2GJp+sIIv9/qr5pYeJbvK+sPgx1cpRJIGuN3ROqduKNh!XVbA2p8RhuswQFj0E1lyV0ZCTpzXXsCZ7LExzy7fG2Aowj6NX4mwidlQ9PBUJG5MY8+hfLo7G1Pg!SjeJyIQfGGJM6TOnLE8D+x+0 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2597 Xref: feeder.eternal-september.org comp.lang.vhdl:5051 On 13/06/11 20:38, KJ wrote: > On Jun 13, 11:49 am, alivingstone wrote: >> I think this may be a common problem for the pros out there... >> >> Pre-synthesis simulation works great, but post-synthesis or post-route simulations crash because the testbench is trying to map generics to a synthesized component with no generics. This must come up often -- is there a standard strategy for this? Configuration >> > > To do this you need to compile and produce a post route simulation > file for each and every set of generics that you would like to > simulate. In your case, for each specific combination of HPIXELS, > VPIXELS and PIXDEPTH that you want to simulate you need to do a new > build that has that specific setting and then repeat that process for > each set of settings. Then in the testbench you'll need to select > (via a generate statement) which specific post-route simulation you > want to instantiate. > > Kevin Jennings If it's just at the top level, another plan is to write a wrapper architecture for your design with the original generics, and instance your gate level design inside that wrapper. Of course there will be a certain amount of manual faffing to keep the values of the generic in sync, regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:13:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c20g2000vbv.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Tue, 14 Jun 2011 14:23:21 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> NNTP-Posting-Host: 20.132.68.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308086602 3237 127.0.0.1 (14 Jun 2011 21:23:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 14 Jun 2011 21:23:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000vbv.googlegroups.com; posting-host=20.132.68.147; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UHALRCNK X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5052 On Jun 13, 3:38=A0pm, KJ wrote: > On Jun 13, 11:49=A0am, alivingstone wrote: > > > I think this may be a common problem for the pros out there... > KJ- That sounds do-able. Is there a slick way to pass the testbench an argument so that it can generate the correct simulation without having to manually update the file? -Abel > > Pre-synthesis simulation works great, but post-synthesis or post-route = simulations crash because the testbench is trying to map generics to a synt= hesized component with no generics. This must come up often -- is there a s= tandard strategy for this? Configuration > > To do this you need to compile and produce a post route simulation > file for each and every set of generics that you would like to > simulate. =A0In your case, for each specific combination of HPIXELS, > VPIXELS and PIXDEPTH that you want to simulate you need to do a new > build that has that specific setting and then repeat that process for > each set of settings. =A0Then in the testbench you'll need to select > (via a generate statement) which specific post-route simulation you > want to instantiate. > > Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r20g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Tue, 14 Jun 2011 20:37:50 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <252018ef-b8fa-4fd1-9bdb-21239ed77d10@r20g2000yqd.googlegroups.com> References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308109072 3434 127.0.0.1 (15 Jun 2011 03:37:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Jun 2011 03:37:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r20g2000yqd.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; SearchToolbar 1.1; GTB7.0; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5053 On Jun 14, 5:23=A0pm, alivingstone wrote: > On Jun 13, 3:38=A0pm, KJ wrote:> On Jun 13, 11= :49=A0am, alivingstone wrote: > > > > I think this may be a common problem for the pros out there... > > KJ- > > That sounds do-able. Is there a slick way to pass the testbench an > argument so that it can generate the correct simulation without having > to manually update the file? > Simulators will let you set top level generics. If you're using Modelsim, then start it up and type 'vsim' . That will display a dialog box that (among other things) lets you specify top level generics. If you consider that slick, then use that method. If not, then after you have the generics set up in the dialog box, hit return and the resulting command line will be echoed into the transcript window and the simulator will be started. Copy and paste that command into whatever form you would consider to be slick. KJ From newsfish@newsfish Fri Feb 3 13:13:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!dn9g2000vbb.googlegroups.com!not-for-mail From: alivingstone Newsgroups: comp.lang.vhdl Subject: Re: Post-synthesis simulation errors at generic map Date: Wed, 15 Jun 2011 06:14:22 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: References: <0f743096-c9bb-4c7a-80ab-46f4188c3f59@glegroupsg2000goo.googlegroups.com> <87cbde7e-7bbe-432d-bc46-3743b649f08e@c20g2000vbv.googlegroups.com> <252018ef-b8fa-4fd1-9bdb-21239ed77d10@r20g2000yqd.googlegroups.com> NNTP-Posting-Host: 20.132.68.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308143662 28049 127.0.0.1 (15 Jun 2011 13:14:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 15 Jun 2011 13:14:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dn9g2000vbb.googlegroups.com; posting-host=20.132.68.147; posting-account=DxCl9goAAADG_waculUDLRA24J16aofl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: UHALRCNK X-HTTP-UserAgent: Opera/9.80 (Windows NT 5.1; U; en) Presto/2.8.131 Version/11.11,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5054 On Jun 14, 11:37=A0pm, KJ wrote: > On Jun 14, 5:23=A0pm, alivingstone wrote: > > > On Jun 13, 3:38=A0pm, KJ wrote:> On Jun 13, = 11:49=A0am, alivingstone wrote: > > > > > I think this may be a common problem for the pros out there... > > > KJ- > > > That sounds do-able. Is there a slick way to pass the testbench an > > argument so that it can generate the correct simulation without having Thanks KJ. Looks like I can set a generic string "SimType" and just send in the desired simulation type using the -g or -G switch in vsim. > > to manually update the file? > > Simulators will let you set top level generics. =A0If you're using > Modelsim, then start it up and type 'vsim' . =A0That will display > a dialog box that (among other things) lets you specify top level > generics. =A0If you consider that slick, then use that method. > > If not, then after you have the generics set up in the dialog box, hit > return and the resulting command line will be echoed into the > transcript window and the simulator will be started. =A0Copy and paste > that command into whatever form you would consider to be slick. > > KJ From newsfish@newsfish Fri Feb 3 13:13:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: debolina Newsgroups: comp.lang.vhdl Subject: implement Expectation maximization algo in vhdl Date: Thu, 16 Jun 2011 08:22:11 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: <5bb24523-678a-415a-8cea-2d832d31a43b@34g2000pru.googlegroups.com> NNTP-Posting-Host: 117.194.2.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308237731 2458 127.0.0.1 (16 Jun 2011 15:22:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 16 Jun 2011 15:22:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=117.194.2.73; posting-account=m1ToDQoAAABiI3QkpepQ20GRKPZxNno2 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110420 AskTbFXTV5/3.12.2.16749 Firefox/3.6.17,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5055 can anybody help me giving me the idea about implementation of EM algo in vhdl?plz reply From newsfish@newsfish Fri Feb 3 13:13:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Gerhard Newsgroups: comp.lang.vhdl Subject: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 03:05:28 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 62.99.175.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308305210 28555 127.0.0.1 (17 Jun 2011 10:06:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Jun 2011 10:06:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=62.99.175.233; posting-account=N_oVwQoAAAAVT5wpiHpHxQ3LYp9caoKS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; chromeframe/12.0.742.100; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 1.1.4322; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; FDM; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5056 Hi, newbe needs help. My problem: I have a Moor state machine sitting around and waiting. After a falling edge on a port the state machine needs to start out working, which take about 96 clock cycles. the work mainly is clocking data in from a spi interface. After that the state machine wents sleeping again. I try to create a signal (later a variable) and set it in a process which monitors the start signal. The state machine consists of three processes (synced Moor state machine) and monitors my start signal (which is like a reset if not active) and starts out working on the next clock transition. After finishing the work, I try to reset my start signal, after entering the neutral state (sleeping), but .. I always get compiler errors, telling me that the net 'start' is constantely driven from different places .... Please tell me, how i should solve such an scenario in VHDL .... Thinking in 'plain hardware'. I need a FF, which is set by a port signal and some edge of the clock and is reset by some condition .... Sounds quite easy in hardware, but seems not so easy to implement in VHDL for a rouky... Thanks for helping. With best regards gerhard Here some snippets: nDRdy_sync: process begin wait until falling_edge(nDRDY); transfer := '1'; end process; some other: process (mySCLK) begin ... ... transfer := '0'; end process; From newsfish@newsfish Fri Feb 3 13:13:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 11:29:53 +0000 (UTC) Organization: A noiseless patient Spider Lines: 84 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 17 Jun 2011 11:29:53 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="yJp5FpId2jBgPu981SiaiA"; logging-data="21438"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19GIytSs65aN63uutTqN+f4X1qThtapuXA=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:HgUuIxaMhKyU0h8pG3nkk/z8DnY= Xref: feeder.eternal-september.org comp.lang.vhdl:5057 On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > Hi, > > newbe needs help. > > My problem: > I always get compiler errors, telling me that the net 'start' is > constantely driven from different places .... That is a very bad design pattern. There are ways to make it work, but it's unnecessary here. > Please tell me, how i should solve such an scenario in VHDL .... Drive "start" from one single process. The state machine can feed a second signal ("started", or "finished") back to that process to let it know when it is safe to return "start" to zero. > Thinking in 'plain hardware'. I need a FF, which is set by a port signal > and some edge of the clock and is reset by some condition .... > Here some snippets: > > nDRdy_sync: > process > begin > wait until falling_edge(nDRDY); > --transfer := '1'; -- "transfer" should be a signal. -- A variable local to the process is OK but invisible outside the process -- A "shared variable" is likely to cause problems and best avoided. transfer <= '1'; wait until active; -- a signal of type boolean transfer <= '0'; > end process; > > some other: > process (mySCLK) > begin > ... > ... > -- transfer := '0'; active <= true; ... -- now the state machine has returned to idle active <= false; > end process; Incidentally the first of these processes will probably not synthesise into an FPGA. You would be better off adopting synchronous design using one internal clock, for example: nDRdy_sync: process(clk) variable idle: boolean := true; begin if rising_edge(clk) then if idle then if nDRDY = '0' then idle := false; transfer <= '1'; end if; else if active then transfer <= '0'; idle := true; end if; end if; end if; end process; You will also simplify your state machine if you transform the obsolete three-process style into the equivalent single-process state machine. The archives of this group cover state machines on a regular basis. See also http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html and some of Mike Treseler's examples on http://mysite.ncnetwork.net/reszotzl/ - Brian From newsfish@newsfish Fri Feb 3 13:13:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!eq2g2000vbb.googlegroups.com!not-for-mail From: Gerhard Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 07:06:50 -0700 (PDT) Organization: http://groups.google.com Lines: 119 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 62.99.175.233 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308319720 11987 127.0.0.1 (17 Jun 2011 14:08:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 17 Jun 2011 14:08:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: eq2g2000vbb.googlegroups.com; posting-host=62.99.175.233; posting-account=N_oVwQoAAAAVT5wpiHpHxQ3LYp9caoKS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.0; chromeframe/12.0.742.100; .NET CLR 2.0.50727; .NET CLR 3.0.04506.30; .NET CLR 3.0.04506.648; .NET CLR 3.5.21022; .NET CLR 1.1.4322; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; FDM; .NET4.0C; .NET4.0E),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5058 On Jun 17, 1:29=A0pm, Brian Drummond wrote: > On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > > Hi, > > > newbe needs help. > > > My problem: > > I always get compiler errors, telling me that the net 'start' is > > constantely driven from different places .... > > That is a very bad design pattern. There are ways to make it work, but > it's unnecessary here. > > > Please tell me, how i should solve such an scenario in VHDL .... > > Drive "start" from one single process. > > The state machine can feed a second signal ("started", or "finished") > back to that process to let it know when it is safe to return "start" to > zero. > > > Thinking in 'plain hardware'. I need a FF, which is set by a port signa= l > > and some edge of the clock and is reset by some condition .... > > Here some snippets: > > > nDRdy_sync: > > =A0 =A0 =A0 process > > =A0 =A0 =A0 =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0 wait until falling_edge(nDRDY); > > =A0 =A0 =A0 =A0 =A0 =A0 --transfer :=3D '1'; > > -- "transfer" should be a signal. > -- A variable local to the process is OK but invisible outside the proces= s > -- A "shared variable" is likely to cause problems and best avoided. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait until active; =A0 =A0 =A0 =A0-- a signal= of type boolean > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0';> =A0 =A0 =A0 =A0 =A0end pr= ocess; > > > some other: > > =A0 =A0 =A0 process (mySCLK) > > =A0 =A0 =A0 =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 -- transfer :=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D true; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- now the state machine has returned to idle > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D false; > > > =A0 =A0 =A0 =A0 =A0end process; > > Incidentally the first of these processes will probably not synthesise > into an FPGA. You would be better off adopting synchronous design using > one internal clock, for example: > > nDRdy_sync: process(clk) > variable idle: boolean :=3D true; > begin > =A0 =A0if rising_edge(clk) then > =A0 =A0 =A0 if idle then > =A0 =A0 =A0 =A0 =A0if nDRDY =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D false; > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0if active then > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D true; > =A0 =A0 =A0 =A0 =A0end if; > =A0 =A0 =A0 end if; > =A0 =A0end if; > end process; > > You will also simplify your state machine if you transform the obsolete > three-process style into the equivalent single-process state machine. The > archives of this group cover state machines on a regular basis. > > See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html > and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/reszot= zl/ > > - Brian ??? I get the book VHDL-synthese by J=FCrgen Reichardt and Bernd Schwarz, which discuss a three process, two process and one process approach, so I try the first one, because its more clear for the beginning and fully synchronized. Speed isn't an issue here. Ah, I should implement some kind of hand-shaking, one process rise start and waiting for some reply. The other process generate 'stopped' after the work is done and the first process clears the start signal. But, when the state machine enters the idle state and the start signal is still present ..... ok, my state machine runs through some sequential states so I can drop the 'stopped' info earlier, but code will be not very clear ... Strange idea, but syntactically there is a chance of working. Problem is, that the start signal is async (came from another chip, running on another clock, no chance to change that) and is only held active as long as I start reading data via SPI. So I have to sync and I have to stretch this puls until the state machine is done or I have to make changes so the state machine doesnt need a permanent signal for running. Thanks a lot With best regards Gerhard From newsfish@newsfish Fri Feb 3 13:13:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Jun 2011 11:16:17 -0500 Date: Fri, 17 Jun 2011 09:16:19 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> In-Reply-To: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 14 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-e6I59GHh8oOqqiR4qYxKpXQT5cEf14e0GjugGsRMuAgh7hi5j1QOIU6DcEC66cjcWiJOxs7O+n7oLNx!HMWAWAntZwNsfhKCPnRfxiPaTfU+QDZ85i90mDiNLpnfYZIkKQa4/xO7jz+1mpjwNn9T74iyZM2V!Ng== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1493 Xref: feeder.eternal-september.org comp.lang.vhdl:5059 On 6/17/2011 3:05 AM, Gerhard wrote: > Hi, > > newbe needs help. > > My problem: > I have a Moor state machine sitting around and waiting. > Gerhard seems to be working on the Othello exercise. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!nntp-feed.chiark.greenend.org.uk!ewrotcd!news.albasani.net!newsfeed1.swip.net!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 17 Jun 2011 11:37:48 -0500 Date: Fri, 17 Jun 2011 09:37:50 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 142 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-pwLiBRlQvQ63D3l/NC6Vk+CjassQcJqjwOy6LjHAJ2eV1PjgNDJeFUVdv6onSCdlpmG2YmIceYI2SgH!pleBETG5t9Mxdz6uGbNPdXu9OUiU36avTa716i0danqxuS1eZwCL6CUFeu+rdEyfcVBM23wQgK6W!+Q== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 6759 Xref: feeder.eternal-september.org comp.lang.vhdl:5060 On 6/17/2011 7:06 AM, Gerhard wrote: > On Jun 17, 1:29 pm, Brian Drummond wrote: >> On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: >>> Hi, >> >>> newbe needs help. >> >>> My problem: >>> I always get compiler errors, telling me that the net 'start' is >>> constantely driven from different places .... >> >> That is a very bad design pattern. There are ways to make it work, but >> it's unnecessary here. >> >>> Please tell me, how i should solve such an scenario in VHDL .... >> >> Drive "start" from one single process. >> >> The state machine can feed a second signal ("started", or "finished") >> back to that process to let it know when it is safe to return "start" to >> zero. >> >>> Thinking in 'plain hardware'. I need a FF, which is set by a port signal >>> and some edge of the clock and is reset by some condition .... >>> Here some snippets: >> >>> nDRdy_sync: >>> process >>> begin >>> wait until falling_edge(nDRDY); >>> --transfer := '1'; >> >> -- "transfer" should be a signal. >> -- A variable local to the process is OK but invisible outside the process >> -- A "shared variable" is likely to cause problems and best avoided. >> transfer<= '1'; >> wait until active; -- a signal of type boolean >> transfer<= '0';> end process; >> >>> some other: >>> process (mySCLK) >>> begin >>> ... >>> ... >>> -- transfer := '0'; >> >> active<= true; >> ... >> -- now the state machine has returned to idle >> active<= false; >> >>> end process; >> >> Incidentally the first of these processes will probably not synthesise >> into an FPGA. You would be better off adopting synchronous design using >> one internal clock, for example: >> >> nDRdy_sync: process(clk) >> variable idle: boolean := true; >> begin >> if rising_edge(clk) then >> if idle then >> if nDRDY = '0' then >> idle := false; >> transfer<= '1'; >> end if; >> else >> if active then >> transfer<= '0'; >> idle := true; >> end if; >> end if; >> end if; >> end process; >> >> You will also simplify your state machine if you transform the obsolete >> three-process style into the equivalent single-process state machine. The >> archives of this group cover state machines on a regular basis. >> >> See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html >> and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/reszotzl/ >> >> - Brian > > > > ??? > I get the book VHDL-synthese by Jrgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, > so I try the first one, because its more clear for the beginning and > fully synchronized. Speed isn't an issue here. > > Ah, I should implement some kind of hand-shaking, one process rise > start and waiting for some reply. The other process generate 'stopped' > after the work is done and the first process clears the start signal. > > But, when the state machine enters the idle state and the start signal > is still present ..... > ok, my state machine runs through some sequential states so I can drop > the 'stopped' info earlier, but code will be not very clear ... > > Strange idea, but syntactically there is a chance of working. > > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. > So I have to sync and I have to stretch this puls until the state > machine is done or I have to make changes so the state machine doesnt > need a permanent signal for running. > > Thanks a lot > > With best regards > > Gerhard The advantage of the single process state machine is that it works out being cleaner, and really forces the entire thing to be purely synchronous. You're starting to talk about handshaking between multiple processes in order to get a simple state machine working. That's making the logic more and more complex; you want to move in the direction of simple. I don't know how long "as long as I start reading data" is, but the usual way to deal with an asynchronous signal is to re-clock it through a two-flop long shift register. You want to always deal with asynchronous signals at a single point of entry, such as one flip-flop. The moment you've got multiple different logical paths looking at that signal, as you will in most state machine implementations, you've buried yourself in race conditions. Once you've got your resynchronized signal, I'd say to change the state machine to not need a permanent signal. That can actually be encoded as one of the states of the machine; you spend much of your time in an IDLE state, hanging out waiting for the input signal to drop. Signal drops, you transition to other states that do things, and at the end wind up back in IDLE. I can actually think of very few state machines I've written that don't operate on that principle. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Fri, 17 Jun 2011 19:15:23 +0000 (UTC) Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 17 Jun 2011 19:15:23 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="yJp5FpId2jBgPu981SiaiA"; logging-data="28111"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/zNBt7x6Mz9OdCLDL7QsBh604DdhSzBPw=" User-Agent: Pan/0.133 (House of Butterflies) Cancel-Lock: sha1:I9HbSdqb6obejwYOikpAJW7Wy44= Xref: feeder.eternal-september.org comp.lang.vhdl:5061 On Fri, 17 Jun 2011 07:06:50 -0700, Gerhard wrote: > On Jun 17, 1:29 pm, Brian Drummond wrote: >> On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: >> >> > Please tell me, how i should solve such an scenario in VHDL .... >> >> Drive "start" from one single process. >> You will also simplify your state machine if you transform the obsolete >> three-process style into the equivalent single-process state machine. >> The archives of this group cover state machines on a regular basis. > ??? > I get the book VHDL-synthese by Jürgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, so > I try the first one, because its more clear for the beginning and fully > synchronized. Speed isn't an issue here. All three will work, and should generate identical hardware. But the single-process variant is generally easier to get right, and easier to maintain. > Ah, I should implement some kind of hand-shaking, one process rise start > and waiting for some reply. The other process generate 'stopped' after > the work is done and the first process clears the start signal. YES, exactly. > But, when the state machine enters the idle state and the start signal > is still present ..... then it would re-trigger. If the start signal is of indeterminate length, the SM should be designed to wait for start to be retracted before entering idle. (the "transfer" signal in my example should be maintained until n_RDY -> '1') > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. So I have to sync and I > have to stretch this puls until the state machine is done or I have to > make changes so the state machine doesnt need a permanent signal for > running. I think you have an understanding of the remaining issues. - Brian From newsfish@newsfish Fri Feb 3 13:13:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u30g2000vby.googlegroups.com!not-for-mail From: rickman Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Mon, 20 Jun 2011 15:46:03 -0700 (PDT) Organization: http://groups.google.com Lines: 158 Message-ID: <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> NNTP-Posting-Host: 70.109.95.41 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308610785 13855 127.0.0.1 (20 Jun 2011 22:59:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 20 Jun 2011 22:59:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u30g2000vby.googlegroups.com; posting-host=70.109.95.41; posting-account=s2WiBwoAAAAaN13gtaT8f3Lp9XHWI5ks User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5062 On Jun 17, 10:06=A0am, Gerhard wrote: > On Jun 17, 1:29=A0pm, Brian Drummond wrote: > > > > > > > > > > > On Fri, 17 Jun 2011 03:05:28 -0700, Gerhard wrote: > > > Hi, > > > > newbe needs help. > > > > My problem: > > > I always get compiler errors, telling me that the net 'start' is > > > constantely driven from different places .... > > > That is a very bad design pattern. There are ways to make it work, but > > it's unnecessary here. > > > > Please tell me, how i should solve such an scenario in VHDL .... > > > Drive "start" from one single process. > > > The state machine can feed a second signal ("started", or "finished") > > back to that process to let it know when it is safe to return "start" t= o > > zero. > > > > Thinking in 'plain hardware'. I need a FF, which is set by a port sig= nal > > > and some edge of the clock and is reset by some condition .... > > > Here some snippets: > > > > nDRdy_sync: > > > =A0 =A0 =A0 process > > > =A0 =A0 =A0 =A0 =A0begin > > > =A0 =A0 =A0 =A0 =A0 =A0 wait until falling_edge(nDRDY); > > > =A0 =A0 =A0 =A0 =A0 =A0 --transfer :=3D '1'; > > > -- "transfer" should be a signal. > > -- A variable local to the process is OK but invisible outside the proc= ess > > -- A "shared variable" is likely to cause problems and best avoided. > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait until active; =A0 =A0 =A0 =A0-- a sign= al of type boolean > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0';> =A0 =A0 =A0 =A0 =A0end = process; > > > > some other: > > > =A0 =A0 =A0 process (mySCLK) > > > =A0 =A0 =A0 =A0 =A0begin > > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > > =A0 =A0 =A0 =A0 =A0 =A0 ... > > > =A0 =A0 =A0 =A0 =A0 =A0 -- transfer :=3D '0'; > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D true; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ... > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- now the state machine has returned to id= le > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 active <=3D false; > > > > =A0 =A0 =A0 =A0 =A0end process; > > > Incidentally the first of these processes will probably not synthesise > > into an FPGA. You would be better off adopting synchronous design using > > one internal clock, for example: > > > nDRdy_sync: process(clk) > > variable idle: boolean :=3D true; > > begin > > =A0 =A0if rising_edge(clk) then > > =A0 =A0 =A0 if idle then > > =A0 =A0 =A0 =A0 =A0if nDRDY =3D '0' then > > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D false; > > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '1'; > > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0if active then > > =A0 =A0 =A0 =A0 =A0 =A0 transfer <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 idle :=3D true; > > =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 end if; > > =A0 =A0end if; > > end process; > > > You will also simplify your state machine if you transform the obsolete > > three-process style into the equivalent single-process state machine. T= he > > archives of this group cover state machines on a regular basis. > > > See alsohttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode15.html > > and some of Mike Treseler's examples onhttp://mysite.ncnetwork.net/resz= otzl/ > > > - Brian > > ??? > I get the book VHDL-synthese by J=FCrgen Reichardt and Bernd Schwarz, > which discuss a three process, two process and one process approach, > so I try the first one, because its more clear for the beginning and > fully synchronized. Speed isn't an issue here. > > Ah, I should implement some kind of hand-shaking, one process rise > start and waiting for some reply. The other process generate 'stopped' > after the work is done and the first process clears the start signal. > > But, when the state machine enters the idle state and the start signal > is still present ..... > ok, my state machine runs through some sequential states so I can drop > the 'stopped' info earlier, but code will be not very clear ... > > Strange idea, but syntactically there is a chance of working. > > Problem is, that the start signal is async (came from another chip, > running on another clock, no chance to change that) and is only held > active as long as I start reading data via SPI. > So I have to sync and I have to stretch this puls until the state > machine is done or I have to make changes so the state machine doesnt > need a permanent signal for running. Can you explain what makes the start signal go away? You mkae it sound like accessing the SPI port makes it go away which would be perfect if I understand your problem. But you say that your Finite State Machine (FSM) reads the SPI port, finishes and the start signal is still active. So something is not right with my understanding. If the start signal is asserted and cleared independently of your FSM then you need to design your machine to detect the assertion, not the fact that it is asserted. When the FSM gets to the end of its work, the start signal needs to be cleared before the FSM will trigger again, in other words, enter a state where you wait for Start to be false before you enter the state where it waits for Start to be true. If the Start signal can be cleared by the FSM, then do that before entering the state where it waits for the Start signal to be true. That is pretty simple, no? I can't say I understand your last part about stretching the Start signal. It only needs to be true long enough for the FSM to see that it is asserted. As long as that is two clock cycles, it is guaranteed to be seen. Then you only need to see it cleared before you return to the starting state waiting for Start to be true. Have you somehow written your code so that if Start goes away the FSM resets? That would be very bad and should be changed. One other thought, the code you give that seems to be waiting for nDRDY it treating nDRDY as a clock. Probably not a good idea unless nDRDY is not guaranteed to be at least two clock cycles long. Rick From newsfish@newsfish Fri Feb 3 13:13:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: VHDL signal sources problem Date: Tue, 21 Jun 2011 05:23:33 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308659128 3020 127.0.0.1 (21 Jun 2011 12:25:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Jun 2011 12:25:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5063 Hi, I don't understand why the following code won't elaborate. The compiler thinks that v(7 downto 4) is driven by both processes. But process "a" definitely doesn't touch it. Tested with GHDL and Active HDL. Ideas appreciated ... - Topi ***************** library ieee; use ieee.std_logic_1164.all; entity process_for_tester is end; architecture test of process_for_tester is signal v: std_ulogic_vector(7 downto 0); signal i: integer; begin a: process(i) variable n: integer; begin for n in 0 to 3 loop if i mod 2 = 0 then v(n) <= '1'; else v(n) <= '0'; end if; end loop; end process; b: process begin v(7 downto 4) <= "0101"; wait; end process; process begin i <= 0; wait for 1 us; loop i <= i + 1; wait for 1 us; end loop; end process; end; From newsfish@newsfish Fri Feb 3 13:13:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!not-for-mail From: Benjamin Krill Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 16:10:53 +0200 Lines: 28 Message-ID: <1308665454.22729.1.camel@bne> References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Trace: news.uni-berlin.de fctEbyDg6qZ+k0bfl4/HGQ4VcOLNfxSHQj49FBPIUJC4PxcSI= In-Reply-To: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> X-Mailer: Evolution 3.0.2 (3.0.2-2.fc15) Xref: feeder.eternal-september.org comp.lang.vhdl:5064 Hi, On Tue, 2011-06-21 at 05:23 -0700, Topi wrote: > Hi, >=20 > I don't understand why the following code won't elaborate. >=20 > The compiler thinks that v(7 downto 4) is driven by both processes. > But process "a" definitely doesn't touch it. It does touch v ... > a: process(i) > variable n: integer; > begin > for n in 0 to 3 loop > if i mod 2 =3D 0 then > v(n) <=3D '1'; ^^^^^^^^^^ here > else > v(n) <=3D '0'; ^^^^^^^^^^ here > end if; > end loop; > end process; ben From newsfish@newsfish Fri Feb 3 13:13:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.x-privat.org!itgate.net!tornado.fastwebnet.it!53ab2750!not-for-mail From: DavCori80 User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: [OT] One click, one (buggy) life... Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 13 Message-ID: Date: Tue, 21 Jun 2011 16:47:48 +0200 NNTP-Posting-Host: 28.21.170.74 X-Complaints-To: newsmaster@fastweb.it X-Trace: tornado.fastwebnet.it 1308667669 28.21.170.74 (Tue, 21 Jun 2011 16:47:49 CEST) NNTP-Posting-Date: Tue, 21 Jun 2011 16:47:49 CEST Xref: feeder.eternal-september.org comp.lang.vhdl:5065 Hi everyone, I would like to share a youtube clip...one click costs nothing while can save lives sometimes (especially mine). http://www.youtube.com/watch?v=PiCeqtGHpJI Thanks a lot and cheers. DavCori http://www.ar4tro.com From newsfish@newsfish Fri Feb 3 13:13:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 16:25:35 +0100 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="23194"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+uiIpMBHJuQZbC+CxKBZ08P/XlMiU7ge0=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:IPU0AaA7cDNHOKMgg3H5XQIWzGM= Xref: feeder.eternal-september.org comp.lang.vhdl:5066 On Tue, 21 Jun 2011 16:10:53 +0200, Benjamin Krill wrote: >On Tue, 2011-06-21 at 05:23 -0700, Topi wrote: >> Hi, >> >> I don't understand why the following code won't elaborate. >> >> The compiler thinks that v(7 downto 4) is driven by both processes. >> But process "a" definitely doesn't touch it. > >It does touch v ... > >> a: process(i) >> variable n: integer; >> begin >> for n in 0 to 3 loop >> if i mod 2 = 0 then >> v(n) <= '1'; > ^^^^^^^^^^ here >> else >> v(n) <= '0'; > ^^^^^^^^^^ here >> end if; >> end loop; >> end process; Ben is completely correct, but the reason is not at all obvious. It's clear that "n" is statically restricted to be only 0 to 3. However, this isn't enough. The 'for' loop is dynamically elaborated, even though its loop range is in fact static. So the assignment target v(n) has simply "v" as its longest static prefix. Consequently, the process drives all eight bits of v. Since bits (7 downto 4) are never updated, they are permanently driven with 'U'. Because v's type is std_ulogic_vector, the multiple drivers are illegal. If v were a std_logic_vector, the multiple drivers would be resolved and you would see an unchanging 'U' value on v(7 downto 4). The solution is to construct two signals and mux them together. You could use a for-loop to do that: signal p,q,v: std_ulogic_vector(7 downto 0); choose_bits: process(...) begin for i in v'range loop if i>BOUNDARY then v(i) <= p(i); else v(i) <= q(i); end if; end loop; end process; Or something like that. BOUNDARY is a generic or constant indicating where in the vector you should switch over from p to q. By the way, your declaration of n as an integer is redundant and inappropriate. The "loop counter" in a for-loop is implicitly declared, and exists only in the scope of the loop. From newsfish@newsfish Fri Feb 3 13:13:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Tue, 21 Jun 2011 11:11:40 -0500 Date: Tue, 21 Jun 2011 09:11:42 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110414 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 13 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.139.213 X-Trace: sv3-ucYNWq+j1inz3YIH9b8drWeyAwF6GYuinPoLQxMpvEwzkSxSkEuiQm8CYX0Lh2rC0LZxFXYGfxBLd6j!z4wiM+urwAovmKJy4zqjDF6ctkXSR13udxrQsmYNTFV9Q5gI4fpicBqlPUIC+dS0My7jinjVLRkt!hQ== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1713 Xref: feeder.eternal-september.org comp.lang.vhdl:5067 On 6/21/2011 8:25 AM, Jonathan Bromley wrote: > [snip] > By the way, your declaration of n as an integer > is redundant and inappropriate. The "loop counter" > in a for-loop is implicitly declared, and exists > only in the scope of the loop. Huh. I've been using them for years, happily declaring them as variables, and never knew that. You learn something new every day. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!16g2000yqy.googlegroups.com!not-for-mail From: Topi Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Tue, 21 Jun 2011 11:39:23 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <5a16daef-bb11-41d0-9ed8-2e385ba340ee@16g2000yqy.googlegroups.com> References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> <1308665454.22729.1.camel@bne> NNTP-Posting-Host: 62.121.39.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308681563 30538 127.0.0.1 (21 Jun 2011 18:39:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 21 Jun 2011 18:39:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 16g2000yqy.googlegroups.com; posting-host=62.121.39.162; posting-account=PJ8KkAkAAACaT1kxx3kCQsd0eQW-y5rQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5068 On Jun 21, 6:25=A0pm, Jonathan Bromley wrote: > It's clear that "n" is statically restricted to be > only 0 to 3. =A0However, this isn't enough. =A0The 'for' > loop is dynamically elaborated, even though its loop > range is in fact static. =A0So the assignment target > v(n) has simply "v" as its longest static prefix. Thanks, got it. I managed to change it to for-generate and if-generate structure: http://vhdlmodels.blogspot.com/2011/06/registers-getting-even-better.html - Topi From newsfish@newsfish Fri Feb 3 13:13:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: catherine saranya Newsgroups: comp.lang.vhdl Subject: Re: 10bit Calculator design help me! Date: Thu, 23 Jun 2011 07:52:27 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <992e4187-8e19-4a41-bec4-62f84969caff@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 106.51.35.99 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308841642 19149 127.0.0.1 (23 Jun 2011 15:07:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 23 Jun 2011 15:07:22 +0000 (UTC) In-Reply-To: <91atk6$fi5$1@news1-2.kornet.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=106.51.35.99; posting-account=PUIYRAoAAAB5kDjG4MqOzlyeOv9saSkp User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5069 Hey simon, did you manage to get the code for this? I really need it too- if u do have it can u post it on the forum. Thanks From newsfish@newsfish Fri Feb 3 13:13:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!h12g2000pro.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Enumerated integer type Date: Fri, 24 Jun 2011 09:24:45 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: NNTP-Posting-Host: 67.188.14.102 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1308932793 7791 127.0.0.1 (24 Jun 2011 16:26:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Jun 2011 16:26:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000pro.googlegroups.com; posting-host=67.188.14.102; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5070 Hello, I'd like to declare a type like this type mytype is (-1,1); However, it appears that enumerated types aren't allowed to be integers. Is there a way to create an integer subtype where the values of the type are constrained to certain hand-picked values, rather than a range? The workaround for this is to use std_logic and convert it to signed when you need to, but it seems an integer subtype would work better. Colin From newsfish@newsfish Fri Feb 3 13:13:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!cs.uu.nl!weretis.net!feeder1.news.weretis.net!feeder.erje.net!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 24 Jun 2011 13:54:00 -0500 Date: Fri, 24 Jun 2011 19:54:00 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 33 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-o0MTnpb5k6a3SJISow8c26hnDwLfO5Jglofj9XIj1pRoZsrI8cT5uPjwDj6ti+mYgoG6CBQY2tJcNxx!EpjW9gsBBeYjrf9Fo/Nn8JxYiBCzxom6BlBfXa/6hvk8hl/98zjql/c1oeeKaesyMAx6XDvINs/q!cjLgtP4Vsgc6T1tg8PqPhIypCr4= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2042 Xref: feeder.eternal-september.org comp.lang.vhdl:5071 On 24/06/11 17:24, Colin Beighley wrote: > Hello, > > I'd like to declare a type like this > > type mytype is (-1,1); > > However, it appears that enumerated types aren't allowed to be > integers. > > Is there a way to create an integer subtype where the values of the > type are constrained to certain hand-picked values, rather than a > range? The workaround for this is to use std_logic and convert it to > signed when you need to, but it seems an integer subtype would work > better. > > Colin Enumerated types can be a mixture of character literals and identifiers. What you probably want is an integer subtype, e.g. subtype mytype is integer range -1 to 1; Because this is a subtype of integer, it can be assigned to and from integers and other integer subtypes. regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:13:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!aioe.org!feeder.news-service.com!postnews.google.com!gc3g2000vbb.googlegroups.com!not-for-mail From: MJB Newsgroups: comp.lang.vhdl Subject: Re: simulation script Date: Fri, 24 Jun 2011 12:57:58 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <1e07ed24-bd63-43c3-a036-2a73a41f291d@gc3g2000vbb.googlegroups.com> References: <9d641a54-4bb9-44f2-aa64-bdc38ff24202@l6g2000vbn.googlegroups.com> <97a9f4db-e769-4376-906e-8aa8c45de3f2@l14g2000pro.googlegroups.com> NNTP-Posting-Host: 199.46.200.231 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1308945478 3416 127.0.0.1 (24 Jun 2011 19:57:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 24 Jun 2011 19:57:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gc3g2000vbb.googlegroups.com; posting-host=199.46.200.231; posting-account=XsPsLQoAAABg05Q6wOj-nB1nqE0qsC-B User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5072 On Jun 9, 12:45=A0am, HT-Lab wrote: > On 08/06/2011 18:00, JohnSmith wrote: > > > > > > > > > On Jun 8, 6:45 pm, MJB =A0wrote: > >> On Jun 8, 9:32 am, JohnSmith =A0wrote: > > >>> Hi, > > >>> How can I use an environment variable in a ".do" script running it in > >>> the modelsim window? > > >>> I tried the windows environment variable in % characters, but doesnt > >>> work. Absolute paths work but I want use this scripts on different > >>> computers. > > >>> vsim -sdftyp {/UUT=3D%MYDIR%/dir/.../timesim.sdf} ... > > >>> Thanks > > >> Try using the Tcl env() function. =A0Modelsim's shell is essentially a > >> Tcl command line evironment and the .do files are .tcl scripts. > > >> to get your directory, try /UUT=3Denv(MYDIR)/ ..... > > >> I don't have a Modelsim installation handy so this is just off the top > >> of my head. =A0Hope you find the solution! > > > Doesnt work.. > > MJB forgot the variable sign, > > vsim -sdftyp /UUT=3D$env(MYDIR)... > > Hanswww.ht-lab.com Thanks for the correction! :) From newsfish@newsfish Fri Feb 3 13:13:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Sat, 25 Jun 2011 10:30:17 -0700 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:31:38 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="29804"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/qEzb4fvKnyuCYcgXMCYmvy5PCrVCpkKo=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:Q3mYLF905J7ArO3nllPRIR4XkaE= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5073 I looks to me like you need something like this. Here is a basic single-process state machine with a synchronized start pulse. Input signal nDRDY is first synchronized to the state machine clock. When nDRDY makes a 1 -> 0 transition, you will get a 1-clock cycle pulse on start. This starts the state machine going through its steps. When done, it goes back to the IDLE state to wait for another start pulse. TYPE states is (IDLE, S1, S2, S3, S4); SIGNAL state : _states; SIGNAL nDRDY_1, nDRDY_2, start : std_logic; start <= NOT nDRDY_1 and nDRDY_2; clk_proc: PROCESS BEGIN WAIT until rising_edge(clk); nDRDY_1 <= nDRDY; nDRDY_2 <= nDRDY_1; CASE state is WHEN IDLE => If start='1' state <= S1; end if; WHEN S1 => -- Do state 1 processing here -- when done: state <= S2; WHEN S2 => -- Do state 2 processing here -- when done: state <= S3; WHEN S3 => -- Do state 3 processing here -- when done: state <= S4; WHEN S4 => -- Do state 4 processing here -- when done: state <= IDLE; -- Add or subtract states as needed END CASE; END PROCESS; Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: generic circuit for read data from n files Date: Sat, 25 Jun 2011 10:31:41 -0700 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <6ac0bf07-8c41-49ad-bf06-447112861e69@g24g2000vbz.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:31:39 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="29804"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19IOAE5OVFJo7uti0pj7hVCvrW8dyLxMN0=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:VwKoon87Md8hE5mHb39jRlt9vOs= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5074 ARQ_MOD probably needs a CLK input so you can sequence through the input file and output data on OUTPUT_DATA one DATA_SIZE chunk per clock cycle. You may also want a DATA_VALID output to indicate that there is valid data on OUTPUT_DATA on any given clock cycle. You can pass the name of the file to be read to ARQ_MOD via a "string" port type. You may also need to pass string length via a "natural" port type to indicate the number of valid characters in the string. Or, always pass a string with trailing blanks and have ARQ_MOD search for a trailing blank to determine the length of the string. Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: VHDL signal sources problem Date: Sat, 25 Jun 2011 10:47:40 -0700 Organization: A noiseless patient Spider Lines: 21 Message-ID: References: <0ac50663-22a9-4601-91f1-94617a0b2961@g12g2000yqd.googlegroups.com> Injection-Date: Sat, 25 Jun 2011 17:52:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="5377"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19bqSy80Fqtn5mQYyAducUPwtcTWIU4O4g=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:75SamulkDGo+UnOXW0xtFFZ5/uI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5075 Something like this should work: a: process(i) variable t : std_ulogic_vector(3 downto 0); begin for n in 0 to 3 loop if i mod 2 = 0 then t(n) := '1'; else t(n) := '0'; end if; end loop; v(3 downto 0) <= t; end process; -- And, your "b" process can be boiled down to just v(7 downto 4) <= "0101"; Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l2g2000prg.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type Date: Sun, 26 Jun 2011 10:18:58 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: References: NNTP-Posting-Host: 98.234.25.72 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309108738 9588 127.0.0.1 (26 Jun 2011 17:18:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 26 Jun 2011 17:18:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l2g2000prg.googlegroups.com; posting-host=98.234.25.72; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5076 On Jun 24, 11:54=A0am, Alan Fitch wrote: > On 24/06/11 17:24, Colin Beighley wrote: > > > > > > > > > > > Hello, > > > I'd like to declare a type like this > > > type mytype is (-1,1); > > > However, it appears that enumerated types aren't allowed to be > > integers. > > > Is there a way to create an integer subtype where the values of the > > type are constrained to certain hand-picked values, rather than a > > range? The workaround for this is to use std_logic and convert it to > > signed when you need to, but it seems an integer subtype would work > > better. > > > Colin > > Enumerated types can be a mixture of character literals and identifiers. > > What you probably want is an integer subtype, e.g. > > subtype mytype is integer range -1 to 1; > > Because this is a subtype of integer, it can be assigned to and from > integers and other integer subtypes. > > regards > Alan > > -- > Alan Fitch My problem is that I want this type to only be able to assume the values of -1 and 1, not 0. However, I suppose the declaration of a new type for this is inconvenient because if I want to do any math with the type I have to convert to a new integer type if the result assumes a value that is not (-1,1)? From newsfish@newsfish Fri Feb 3 13:13:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 26 Jun 2011 14:37:43 -0500 Date: Sun, 26 Jun 2011 20:37:43 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc13 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 53 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-xfwz7wmSUk6gSbhzIFKoIcXVWRz7duXMMDrxBFZ+sOl+/PvgF9OTfU7yoVu+amforDvXIceYjoxG+aT!lCyh1J3bTjcCV3OwIcPlsu2RPW5jkIC/CdVWwTxZ+IlOJKBcVfkzbKfVWyHNj77CeeddTNRpBTR4!iVkqN+bDeltDPX2P8YYPxWah X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2962 Xref: feeder.eternal-september.org comp.lang.vhdl:5077 On 26/06/11 18:18, Colin Beighley wrote: > On Jun 24, 11:54 am, Alan Fitch wrote: >> On 24/06/11 17:24, Colin Beighley wrote: >> >> >>> Hello, >> >>> I'd like to declare a type like this >> >>> type mytype is (-1,1); >> >>> However, it appears that enumerated types aren't allowed to be >>> integers. >> >>> Is there a way to create an integer subtype where the values of the >>> type are constrained to certain hand-picked values, rather than a >>> range? The workaround for this is to use std_logic and convert it to >>> signed when you need to, but it seems an integer subtype would work >>> better. >> >>> Colin >> >> Enumerated types can be a mixture of character literals and identifiers. >> >> What you probably want is an integer subtype, e.g. >> >> subtype mytype is integer range -1 to 1; >> >> Because this is a subtype of integer, it can be assigned to and from >> integers and other integer subtypes. >> > > My problem is that I want this type to only be able to assume the > values of -1 and 1, not 0. However, I suppose the declaration of a new > type for this is inconvenient because if I want to do any math with > the type I have to convert to a new integer type if the result assumes > a value that is not (-1,1)? I guess you could go the whole hog and declared an enumerated type representing -1 and 1, e.g. type mytype is (minusone, plusone); then overload operators on that type. You'd also have to write conversion functions to and from integer. It's all quite feasible, you just need the time and inclination :-) regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:13:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!q1g2000vbj.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Enumerated integer type Date: Sun, 26 Jun 2011 22:59:51 -0700 (PDT) Organization: http://groups.google.com Lines: 32 Message-ID: <104bc36e-4158-46ab-9402-49e3afb80bf6@q1g2000vbj.googlegroups.com> References: NNTP-Posting-Host: 195.37.178.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309154391 32366 127.0.0.1 (27 Jun 2011 05:59:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Jun 2011 05:59:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q1g2000vbj.googlegroups.com; posting-host=195.37.178.147; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.2.18) Gecko/20110615 Ubuntu/10.04 (lucid) Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5078 On 24 Jun., 18:24, Colin Beighley wrote: > Hello, > > I'd like to declare a type like this > > type mytype is (-1,1); > > However, it appears that enumerated types aren't allowed to be > integers. > > Is there a way to create an integer subtype where the values of the > type are constrained to certain hand-picked values, rather than a > range? The workaround for this is to use std_logic and convert it to > signed when you need to, but it seems an integer subtype would work > better. > > Colin Hi, Not sure what you are about to do with this kind of type declaration You can declare some ordinary enumerated type like : type mytype is (neg,pos); Then you can access the integers then with some simple conversion function: function getint(a : mytype) return integer range -1 to 1; -- or whatever you like to call that function usage example: xx <= xx * getint(neg); Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:13:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c29g2000yqd.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Are there technical reasons why Emacs is better than an IDE? Followup-To: comp.emacs, comp.lang.vhdl Date: Mon, 27 Jun 2011 04:06:04 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309174510 1947 127.0.0.1 (27 Jun 2011 11:35:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 27 Jun 2011 11:35:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c29g2000yqd.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.100 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3950 comp.lang.vhdl:5079 It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL mode. I have posted several articles about the fundamental differences between Emacs and Sigasi: http://www.sigasi.com/emacs It usually boils down to the limitations of regular expressions and pattern matching. There are just certain things that require a parser rather than a simple pattern matcher. To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am interested to hear what you think: are there any _technical_ reasons why Emacs is still better than an IDE solution? Or is it just a matter of "I love this tool and nobody is going to deny me my rights?" http://www.sigasi.com/content/room-improvement thanks Philippe -- Philippe Faes http://www.sigasi.com From newsfish@newsfish Fri Feb 3 13:13:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: boldport Date: Mon, 27 Jun 2011 07:08:03 -0500 Lines: 85 Message-ID: <96ra54FpqdU1@mid.individual.net> References: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 9w2Fmtj983QslkwY5k0awwapZCuJCC1szaJbcLW6vXPZHdULmf Cancel-Lock: sha1:fG/55IqEWMGT9ijiCYBi4ZPUBSg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.arch.fpga:15792 comp.lang.vhdl:5080 comp.lang.verilog:3096 On 5/5/2011 12:58 PM, saar drimer wrote: > In a bit of a self promotional move, though probably pretty relevant > to this group, I'd like to mention [snip] As a reminder and a caution for future posting: http://www.faqs.org/faqs/usenet/advertising/how-to/part1/ which reminded me why your post didn't get much of a feedback even though I found the content rather interesting. > for easing the migration from GUI to command-line use of FPGA tools, > and more effective project/build management. I want to say that I'm on your side when you say that a "command-line" use of FPGA tools is a nice to have, but I have to admit that the overall tendency is to use GUI and integrated environments where the designer has the (deceived) perception that everything is at his own hand and control. We can argue a lifetime on what is better, but IMHO the market has chosen its horse and is not the command-line, regardless efficiency drawbacks. The portability problem is often used as an argument to propose yet another model that will have eventually the same problems of portability that previous models had. That is why I always intend portability in the sense that is easy to carry around for it doesn't depend on system's features or device's features and ultimately tool's features. In addition I believe most of the designers out there are not really moving from a linux machine to a windows machine every day and they don't switch from an ABC device to a CBA device every other day and whenever they would be in the place where they *have to* switch, it's going to be a hard day and no magic can be at hand but a previously thought through approach to design in an as abstract way as possible. Hardware Description Languages have been invented for good because they give the designer a mean which will help him looking at the big picture instead of the gates and flops actually used. And this level of abstraction has an enormous potential that most of the time is overlooked in the names of concepts like "optimization" or "I had to put that GCLK buffer otherwise it wouldn't work!". > > The project is at an early stage, and more features will be added with > time. Praise, constructive feedback, and well-mannered bashing are > welcome, of course... be as honest as this group knows how to be (feel > free to email me privately as well). Finally, I'm looking for early > adopter projects, and offer my help with the setup. Talking about scalability problems, how do you intend to provide help on the long run? Say you have 10 million users instead of 10, I think numbers do play a difference. On top of it, what make your company different from yet another EDA company willing for designers to adopt their approach and strangle them with incompatibility features that will shackle them for the rest of their life? Since is not open-source and is profit oriented, do you think it's enough to say that your approach "is better" to convince designers to change their habits? After all a designer wants to design as much as a painter wants to paint. If art can be made with any tool available in your garage, hardware can follow the same line and be built with just an editor or any available tool you have in your computer (maybe a text editor is enough!). That is why IMHO we should foster good designing approaches that will enhance the portability in terms of code, as opposed to project structure. The project approach is borrowed from the management world and has nothing to do with HDL. Indeed I always asked myself why should I create a project when my goal is to describe how a piece of hardware should work. "Project" is a name poorly defined, a concept poorly defined, with no boundaries and no constraints and that is the root of all your and our problems. > > Thanks for your attention, Believe me, even though I might have sounded harsh, I paid a lot of attention to it! > saar. > > From newsfish@newsfish Fri Feb 3 13:13:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.muc.de!not-for-mail From: Alan Mackenzie Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 27 Jun 2011 21:23:27 +0000 (UTC) Organization: muc.de e.V. Lines: 48 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: marvin.muc.de X-Trace: colin2.muc.de 1309209807 49628 2001:608:1000::2 (27 Jun 2011 21:23:27 GMT) X-Complaints-To: news-admin@muc.de NNTP-Posting-Date: Mon, 27 Jun 2011 21:23:27 +0000 (UTC) User-Agent: tin/1.6.2-20030910 ("Pabbay") (UNIX) (FreeBSD/4.11-RELEASE (i386)) Xref: feeder.eternal-september.org comp.emacs:3951 comp.lang.vhdl:5081 In comp.emacs Philippe Faes wrote: > It is no secret that Sigasi .... Who? What? > .... wants to take on Emacs and the Emacs VHDL mode. Emacs is free software. Anybody may take it on. > I have posted several articles about the fundamental differences > between Emacs and Sigasi: http://www.sigasi.com/emacs It usually boils > down to the limitations of regular expressions and pattern matching. "It"? Differences come down to limitations? Sir, you are not expressing yourself at all clearly. > There are just certain things that require a parser rather than a > simple pattern matcher. Of course there are. What's new? Arbitrarily nested structures (think program source) cannot be parsed by regexps. Try using a push-down automaton. > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Yes. > Or is it just a matter of "I love this tool and nobody is going to deny > me my rights?" Hmmm. On comp.emacs. You wouldn't happen to be trolling, now, would you? > http://www.sigasi.com/content/room-improvement > thanks > Philippe > -- > Philippe Faes > http://www.sigasi.com -- Alan Mackenzie (Nuremberg, Germany). From newsfish@newsfish Fri Feb 3 13:13:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 27 Jun 2011 16:42:37 -0700 Lines: 33 Message-ID: <4E09156D.50400@gmail.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 32oxysq1ELTiY4ZyGsHlbQyXu2unbDrWxLYWlXD1K2VsXRMSwa Cancel-Lock: sha1:dKAE1hiEY2kJptagx1q7GXcdc6k= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:5082 On 6/27/2011 4:06 AM, Philippe Faes wrote: > It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL > mode. I have posted several articles about the fundamental differences > between Emacs and Sigasi: http://www.sigasi.com/emacs > It usually boils down to the limitations of regular expressions and > pattern matching. There are just certain things that require a parser > rather than a simple pattern matcher. The full language is hard for a parser as well, but all you need to cover are the parts that my simulator can't feed back. I am most interested in clean sim interfaces and makefile generation because my simulator is already good and fast at marking errors in syntax (vcom -c a_unit) and elaboration (vsim -c a_unit). Getting these errors fed back to emacs vhdl-mode requires careful configuration and a few custom elisp functions. This seems to be an area where you might have an advantage. > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" In any case, there are many fewer emacs users than non-users, so you have a good chance. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:13:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000pru.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Wed, 29 Jun 2011 12:02:57 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 192.25.142.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309374178 21413 127.0.0.1 (29 Jun 2011 19:02:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 29 Jun 2011 19:02:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000pru.googlegroups.com; posting-host=192.25.142.225; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3954 comp.lang.vhdl:5083 On Jun 27, 4:06=A0am, Philippe Faes wrote: > It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL > mode. I have posted several articles about the fundamental differences > between Emacs and Sigasi:http://www.sigasi.com/emacs > It usually boils down to the limitations of regular expressions and > pattern matching. There are just certain things that require a parser > rather than a simple pattern matcher. > > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" > > http://www.sigasi.com/content/room-improvement > > thanks > > Philippe > > -- > Philippe Faeshttp://www.sigasi.com Just a few off the top: 1) emacs can be run in batch mode, so all of the 'AUTOs' can be updated at once. 2) emacs is a much more powerful editor. There are times you NEED rectangle cut/paste. 3) emacs developers don't spam usenet. I prefer less volatile discussions than editor choices - religion and politics are typically less incendiary. From newsfish@newsfish Fri Feb 3 13:13:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!cleanfeed3-a.proxad.net!nnrp17-1.free.fr!not-for-mail Date: Wed, 29 Jun 2011 22:03:37 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> In-Reply-To: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 11 Message-ID: <4e0b8518$0$16389$426a34cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Jun 2011 22:03:37 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1309377817 news-4.free.fr 16389 82.246.229.10:58095 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.emacs:3955 comp.lang.vhdl:5084 Le 27/06/2011 13:06, Philippe Faes a crit : > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Emacs can do soooooo many more things than VHDL editing. Why use a different IDE for each language ? Nicolas From newsfish@newsfish Fri Feb 3 13:13:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 30 Jun 2011 01:24:55 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <4e0b8518$0$16389$426a34cc@news.free.fr> In-Reply-To: <4e0b8518$0$16389$426a34cc@news.free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 21 Message-ID: <4e0bb447$0$14245$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: a6fa0f48.news.skynet.be X-Trace: 1309389895 news.skynet.be 14245 91.177.169.145:34166 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.emacs:3956 comp.lang.vhdl:5085 On 06/29/2011 10:03 PM, Nicolas Matringe wrote: > Le 27/06/2011 13:06, Philippe Faes a crit : > >> To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am >> interested to hear what you think: are there any _technical_ reasons >> why Emacs is still better than an IDE solution? Or is it just a matter >> of "I love this tool and nobody is going to deny me my rights?" > > Emacs can do soooooo many more things than VHDL editing. > Why use a different IDE for each language ? That is not the proposal, quite the opposite. The proposal is to use Eclipse as the IDE, and Sigasi HDT as its "VHDL mode". Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:13:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.tele.dk!news.tele.dk!small.news.tele.dk!bnewspeer01.bru.ops.eu.uu.net!bnewspeer00.bru.ops.eu.uu.net!emea.uu.net!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Thu, 30 Jun 2011 01:32:26 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> In-Reply-To: <48a44f72-3517-4408-84b5-efc7f258a1d4@34g2000pru.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 49 Message-ID: <4e0bb60a$0$14252$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: a6fa0f48.news.skynet.be X-Trace: 1309390347 news.skynet.be 14252 91.177.169.145:57744 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.emacs:3957 comp.lang.vhdl:5086 On 06/29/2011 09:02 PM, NeedCleverHandle wrote: > On Jun 27, 4:06 am, Philippe Faes wrote: >> It is no secret that Sigasi wants to take on Emacs and the Emacs VHDL >> mode. I have posted several articles about the fundamental differences >> between Emacs and Sigasi:http://www.sigasi.com/emacs >> It usually boils down to the limitations of regular expressions and >> pattern matching. There are just certain things that require a parser >> rather than a simple pattern matcher. >> >> To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am >> interested to hear what you think: are there any _technical_ reasons >> why Emacs is still better than an IDE solution? Or is it just a matter >> of "I love this tool and nobody is going to deny me my rights?" >> >> http://www.sigasi.com/content/room-improvement >> >> thanks >> >> Philippe >> >> -- >> Philippe Faeshttp://www.sigasi.com > > Just a few off the top: > 1) emacs can be run in batch mode, so all of the 'AUTOs' can be > updated at once. The fact that you actually need 'AUTOs' (?) and batch mode shows that a more powerful IDE may be quite useful. > 2) emacs is a much more powerful editor. There are times you NEED > rectangle cut/paste. Whatever it is in emacs, this is certainly not easier than 'Toggle Block Selection' (Shift+Alt+A). > 3) emacs developers don't spam usenet. This is on-topic content, written on a specific occasion by real people. Calling it spam just because you thoroughly dislike the message is a little cheap. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:13:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d14g2000yqb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Thu, 30 Jun 2011 06:19:01 -0700 (PDT) Organization: http://groups.google.com Lines: 12 Message-ID: <4487d336-ac46-4dbd-a69a-d8dd0cc7e42a@d14g2000yqb.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309439942 25036 127.0.0.1 (30 Jun 2011 13:19:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Jun 2011 13:19:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d14g2000yqb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9979) X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRUV X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3960 comp.lang.vhdl:5087 On 27 Jun., 13:06, Philippe Faes wrote: > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Maybe it is just the fact that emacs is for free and good enough, so why bother about Sigasi? I assume you already included open script interface in your sigasi tool to be at least on the obvious parts on-pair with emacs, but as long as I'm fine with gnu tool, I see no reason to check alternatives every 6 months. From newsfish@newsfish Fri Feb 3 13:13:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: How do you introduce delays into 3-state (bi-dir) lines? Date: Thu, 30 Jun 2011 19:36:28 +0300 Organization: A noiseless patient Spider Lines: 1 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 30 Jun 2011 16:36:31 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="10581"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+dAfCOU5DeYhHuzzYgTBlRaKaWhgPjLH8=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.17) Gecko/20110414 Thunderbird/3.1.10 Cancel-Lock: sha1:ibTXGjzNNzJAKN5bEicsfRfTDa0= Xref: feeder.eternal-september.org comp.lang.vhdl:5088 This is needed for bus simulation From newsfish@newsfish Fri Feb 3 13:13:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h25g2000prf.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Thu, 30 Jun 2011 11:33:51 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 83.134.176.236 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309458832 16408 127.0.0.1 (30 Jun 2011 18:33:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 30 Jun 2011 18:33:52 +0000 (UTC) Cc: tzz@lifelogs.com Complaints-To: groups-abuse@google.com Injection-Info: h25g2000prf.googlegroups.com; posting-host=83.134.176.236; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3963 comp.lang.vhdl:5089 Thank you all for your input. The technical arguments I hear are: Mike Treseler wrote: > The full language is hard for a parser as well, > but all you need to cover are the parts > that my simulator can't feed back. Some editor features require a full parser (and: yes, it is hard), including correct navigation and refactoring. > I am most interested in clean sim interfaces > and makefile generation [=85] Duly noted. Sigasi offers some of this, but we know we still need to improve on this. NeedCleverHandle wrote: > 1) emacs can be run in batch mode, so all of the 'AUTOs' can be > updated at once. Note that you are bringing up Verilog as opposed to VHDL now. This particular use case (automatic template expansion in Verilog) would be a good argument for interactive tools rather than batch processing. Checking and updating sensitivity list is something that can easily be done interactively. If you want to discuss any specific other use cases for batch mode, I'll be happy to dig deeper into this subject. > 2) emacs is a much more powerful editor. There are times you NEED > rectangle cut/paste. As Jan Decaluwe points out, Eclipse supports block editing. I am interested to learn of other features that make Emacs a much more powerful editor. Nicolas Matringe wrote: > Emacs can do soooooo many more things than VHDL editing. > Why use a different IDE for each language ? Again as Jan points out: that is exactly my point. The Eclipse platform will offer a wide range of language-specific plug-ins to choose from. Ted Zlatanov (received this by email) wrote: > Emacs has very capable parsers built-in. =A0Whether VHDL editing needs > them is not clear; [...] Emacs has a very capable regex matcher, but not a VHDL parser. A built-in parser enables several things such as semantic highlighting and correct navigation. As I pointed out in my original post, I have discussed this at length elsewhere. I'll throw in one myself: Sorting lines alphabetically is a pain in Eclipse. There are some not- so-stable or not-so-recent plugins that support this feature, but people usually don't install a new plugin just to get one simple operation. Any other thoughts are still more than welcome. -- Philippe From newsfish@newsfish Fri Feb 3 13:13:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe05.ams2.POSTED!00000000!not-for-mail From: William Stevenson Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.0.50 (gnu/linux) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAFVBMVEVMEhl7LzAuAwhMHiLd wLuFQkNaJilixb28AAACHElEQVQ4jV3Ty3biMAwGYMWZskYw8TqjTLtm4pInSPb1OTHrhBS//yPM b9lQWu/Qd6xLLGgcxymEcInlbEPsu3kcCTACwhfwVZ5Br2zOubM99ref4ESkktifvyCnyVD1rwWm cHFuwIUeYOXt8BrKjdWLuJwJ0NmXEBQ8ASjDbi+y3gpcKBiilWO0jGZlF11U+DANc2otWDKip0ow fZhzCA3ivoSl/0ep2eOpjUSB+QGDpSnMl+2EQOUZp0CMFMIYXQL2DVe813i3/wTMmzuJ/AkcPFFq Cj/inMFI2zCqX4UOqfSwzjRNwSLTLuwBi7QJOtfM6GpCBnnzFeBo3g5aZP2d5vAblVR2qQ5SWSPV rwKE2YOCEUZr1Yum4obpxafJ92wqJl7WJUH6GpxhqZiJdsw3yksSfJNvrGwJEvsMHgUUIhLV9Ymc I92EkFpKxeOCWDrnAqg/g4/15sqhcZonlZk5Xtt7fMANBXxClDRSD/GRKoNP7aNq/AnplaKjQfe0 z8XLDcBWxwLvKP4Euo+Arnu/d5XAuiGlB/cJxjmUGtbF+xid7i5eVzOxrrxzWwFkGjNwpPt8z5A+ K9ZIhz9rqkkhxfW9Ee/fH8ALtWRao/E7YPiA9DtKJ9eYH/9BrfwFj/+gjrE84p8Fcrd2MYJ3RVzG O0yaCqvd1uSwut/Axg3vRGKk//sN8FlNW59a/HW/gU2AsX+CB6C4oHaG/7449jZiFODnAAAAAElF TkSuQmCC Message-ID: Cancel-Lock: sha1:+yZ9j/oGkrpMahVMyS75ImxJZzE= MIME-Version: 1.0 Content-Type: text/plain Lines: 7 NNTP-Posting-Host: 81.99.65.51 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe05.ams2 1309461128 81.99.65.51 (Thu, 30 Jun 2011 19:12:08 UTC) NNTP-Posting-Date: Thu, 30 Jun 2011 19:12:08 UTC Organization: virginmedia.com Date: Thu, 30 Jun 2011 20:12:04 +0100 Xref: feeder.eternal-september.org comp.emacs:3964 comp.lang.vhdl:5090 Read "Beautiful Architecture" [1] chapter on emacs for a good look at how and why emacs is great, and how it compares to other architectures, namely Eclipse and Firefox. [1] http://oreilly.com/catalog/9780596517984 Chapter 11 GNU Emacs: Creeping Featurism Is a Strength From newsfish@newsfish Fri Feb 3 13:13:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j31g2000yqe.googlegroups.com!not-for-mail From: Lieven Lemiengre Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Fri, 1 Jul 2011 07:46:35 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309531595 19327 127.0.0.1 (1 Jul 2011 14:46:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 14:46:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j31g2000yqe.googlegroups.com; posting-host=195.144.71.15; posting-account=Ah6zaAoAAAACT7jhwwcVLW7AYlcH3abR User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3970 comp.lang.vhdl:5091 On 30 jun, 21:12, William Stevenson wrote: > Read "Beautiful Architecture" [1] chapter on emacs for a good look at > how and why emacs is great, and how it compares to other architectures, > namely Eclipse and Firefox. > > [1]http://oreilly.com/catalog/9780596517984 > =A0 =A0 Chapter 11 GNU Emacs: Creeping Featurism Is a Strength I looked it up and I quote: "As a development environment, Eclipse provides valuable features that Emacs lacks. For example, the Java Development Tools plug-ins provide extensive support for refactoring and code analysis. In comparison, Emacs has only a limited understanding of the semantic structure of the programs it edit and can't offer comparable support." From newsfish@newsfish Fri Feb 3 13:13:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n5g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Fri, 1 Jul 2011 09:20:34 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309537234 10551 127.0.0.1 (1 Jul 2011 16:20:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 16:20:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n5g2000yqh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5092 On Jun 30, 12:36=A0pm, valtih1978 wrote: > This is needed for bus simulation Check out Ben Cohen's model at the link below http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/de067db0= 14e088d7/7d14832588a0cabb Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:28 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!g12g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Fri, 1 Jul 2011 09:29:30 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <9a20bb33-0f97-4e55-858b-8896f43d1099@g12g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309537770 15462 127.0.0.1 (1 Jul 2011 16:29:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 1 Jul 2011 16:29:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g12g2000yqd.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5093 On Jun 30, 12:36=A0pm, valtih1978 wrote: > This is needed for bus simulation Take a look at Ben Cohen's model at the link below http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/de067db0= 14e088d7/7d14832588a0cabb Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!xmission!nnrp.xmission!not-for-mail From: Jason Earl Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Fri, 01 Jul 2011 13:02:07 -0600 Organization: XMission http://xmission.com/ Lines: 32 Message-ID: <877h81eseo.fsf@notengoamigos.org> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 67.214.244.122 Mime-Version: 1.0 Content-Type: text/plain X-Trace: news.xmission.com 1309546956 6741 67.214.244.122 (1 Jul 2011 19:02:36 GMT) X-Complaints-To: abuse@xmission.com NNTP-Posting-Date: Fri, 1 Jul 2011 19:02:36 +0000 (UTC) Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwCAAAAAByaaZbAAAABGdBTUEAALGPC/xhBQAAAAFz UkdCAK7OHOkAAAAgY0hSTQAAeiYAAICEAAD6AAAAgOgAAHUwAADqYAAAOpgAABdwnLpRPAAAAAlw SFlzAAASmwAAEpsB4JJZDAAAAAl2cEFnAAAAMAAAADAAzu6MVwAAAaFJREFUSMe1VtuxxSAIzIz9 2Iyl2Aj1bBX0k5+LrwjGjJyPy2ROwtGNBJbVCwwwy1UNoOL3f+SBxkj15Lr4NsboN24DWMZxYQNA TjGmjC1gswJiqBbpDeANYMwXBFyAFB5L7ADMBcoSDgAFBSDHR2tA8ABMSB4AawB76pAnILsKx2lm 1VfpgUi3kxrySylRHdmQj40Jva2/jl8EY3Twv/phhsC9nIQR0hnAOUptYsL3RxvAk+YIH2AWsvTH GYBgKn8GaPYm5jNANaCQ8WfAzyH9x0crFfGl9X4QVdg8gEqN2KjBHi6V/iBq6iyAxTqd+Yvupwai VwM9LZkxQ6otihmS6H+mHlK5URwi0UQgWxHoxS5JagBSed7IzJRCallS2pg2QsamcGUFNSHgLZUv augJIUualv1Bv6+yVat1oeMq92s/mBBWQJH7dQX7CnpvWWs/4CazpHlB2RR1BFSzNGdIaTbbLil8 U76BKKU0GztapXP3C78bNYQ6MTQybY8OkIaITf9HPzyHkXE4YXs4mf5VDz+jAepj3RTQ3Ubv0SPy 9AcCrfKh0TBgvgAAACV0RVh0ZGF0ZTpjcmVhdGUAMjAxMS0wMS0wM1QxMDo1MDo1NC0wNzowMIgC s0IAAAAldEVYdGRhdGU6bW9kaWZ5ADIwMTAtMDQtMDVUMTM6MjQ6NDgtMDY6MDCtwF/YAAAAAElF TkSuQmCC User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.0.50 (gnu/linux) Cancel-Lock: sha1:avqlY/9rseIlpnY1JdeznDOlvt0= Xref: feeder.eternal-september.org comp.emacs:3974 comp.lang.vhdl:5094 On Thu, Jun 30 2011, Philippe Faes wrote: [...] > I'll throw in one myself: > Sorting lines alphabetically is a pain in Eclipse. There are some not- > so-stable or not-so-recent plugins that support this feature, but > people usually don't install a new plugin just to get one simple > operation. Emacs has a couple of advantages over tools like Eclipse. The biggest advantage, IMHO, is that it is easy to add new code. You don't have to compile anything, or install any plugins. You can add a new function to your currently running instance of Emacs with just a few keystrokes. I often find myself creating "throw-away" code to do some little editing task that would be very tedious to do otherwise. Not only does Emacs have code for sorting lines (and paragraphs and pages), but it is easy to add code to sort however or whatever you would like. Another big advantage is that you can realistically use it for most of your text editing tasks. I spend quite a bit of my time in front of a computer writing code. However, the fact that the Emacs skills that serve me while writing code are also useful when creating other documents, reading email, planning my day, taking notes, etc. means that time spent learning to use Emacs well can be leveraged across most of my computer-using activities. Personally, I have high hopes that the recent integration of CEDET into Emacs will begin to give Emacs hackers the tools that they need to build smarter Emacs modes. Jason From newsfish@newsfish Fri Feb 3 13:13:29 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!u19g2000vbi.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Mon, 4 Jul 2011 17:22:23 -0700 (PDT) Organization: http://groups.google.com Lines: 31 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309825343 27087 127.0.0.1 (5 Jul 2011 00:22:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 00:22:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u19g2000vbi.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3982 comp.lang.vhdl:5095 Hi everyone, One thing I have trouble understanding is the following. Designers typically spend way more time debugging VHDL code, running simulations, debugging "real" hardware than writing actual code. Therefore, I have trouble understanding why comparing Sigasi to Emacs is so important? A lot of the Emacs feature are basically tools to write code faster (code completion, sensitivity list updating, etc.). Even If I write code 10% faster, this is probably the equivalent of a driver speeding up only to being forced to stop because the light is red. The analogy is imperfect, but basically in real life I'm limited by the simulation speed of my simulator, I'm limited by the synthesis/ p&r of Xilinx/Altera/etc. I'm limited by real-life issues like a faulty board, unclear specifications, project management, etc. Rarely have I felt limited by notepad++ even though it is a simple code editor with syntax highlighting. I agree than Sigasi looks interesting from a code refactoring, project management and code comprehension perspective but less so from a "writing code faster point of view". What would be important for me, is good integration with Xilinx (or Altera) and good integration with Modelsim (or Aldec). Just my 2 cents. Benjamin From newsfish@newsfish Fri Feb 3 13:13:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a7g2000vby.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.lang.vhdl Subject: VHDL Product Announcement: Sigasi Starter Edition Date: Tue, 5 Jul 2011 02:11:01 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309857063 22087 127.0.0.1 (5 Jul 2011 09:11:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 09:11:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a7g2000vby.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5096 Hi everybody, At Sigasi, we have launched the "Sigasi 2.0 Starter Edition", an IDE for the VHDL language. The number one new feature is type-time error checking. The Starter Edition will be permanently free of charge. If your project is small enough, you get to use all of the Pro features as well (Pro version will be launched later this year). Read the full announcement: http://www.sigasi.com/clv/announcing-starter-edition Download: http://www.sigasi.com/clv/download-sigasi-20 best regards Philippe Sigasi From newsfish@newsfish Fri Feb 3 13:13:30 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l18g2000yql.googlegroups.com!not-for-mail From: saar drimer Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: Re: boldport Date: Tue, 5 Jul 2011 10:37:19 -0700 (PDT) Organization: http://groups.google.com Lines: 111 Message-ID: <7c578462-2fad-41fd-8802-be192ec6c3c4@l18g2000yql.googlegroups.com> References: <4206215d-031e-46e0-9e11-c50159662586@e21g2000vbz.googlegroups.com> <96ra54FpqdU1@mid.individual.net> NNTP-Posting-Host: 86.6.9.112 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309890102 31567 127.0.0.1 (5 Jul 2011 18:21:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 18:21:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l18g2000yql.googlegroups.com; posting-host=86.6.9.112; posting-account=kAS_1goAAACUQz31Vzb1j9_dRg4LBLlV User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15842 comp.lang.vhdl:5097 comp.lang.verilog:3108 On Jun 27, 1:08=A0pm, Alessandro Basili wrote: > I want to say that I'm on your side when you say that a "command-line" > use of FPGA tools is a nice to have, but I have to admit that the > overall tendency is to use GUI and integrated environments where the > designer has the (deceived) perception that everything is at his own > hand and control. > > We can argue a lifetime on what is better, but IMHO the market has > chosen its horse and is not the command-line, regardless efficiency > drawbacks. I understand that we do agree that scripted flows are better, so there's no need to argue. My view is that that horse is running out of steam in the face of progress in development methods and complexity. I'm not saying "nice to have", I'm saying that scripted flows are *essential* if we want to adopt any of the good stuff that software development has benefited from in the past decade. I'm talking about revision control, transparent IP/code reuse and distribution, modularity, team-based design, and so on. I also don't think it's the "market" that's made a choice, it's the vendors that have bet on the wrong horse. I've elaborated on this a bit here: https://www.boldport.com/blog/?p=3D369 > The portability problem is often used as an argument to propose yet > another model that will have eventually the same problems of portability > that previous models had. That is why I always intend portability in the > sense that is easy to carry around for it doesn't depend on system's > features or device's features and ultimately tool's features. That's a separate issue of generic vs architecture-specific design, which I've not gotten into in the context of the structure I'm proposing. Or, rather, I'm not arguing for either side. > In addition I believe most of the designers out there are not really > moving from a linux machine to a windows machine every day and they > don't switch from an ABC device to a CBA device every other day and > whenever they would be in the place where they *have to* switch, it's > going to be a hard day and no magic can be at hand but a previously > thought through approach to design in an as abstract way as possible. > > Hardware Description Languages have been invented for good because they > give the designer a mean which will help him looking at the big picture > instead of the gates and flops actually used. And this level of > abstraction has an enormous potential that most of the time is > overlooked in the names of concepts like "optimization" or "I had to put > that GCLK buffer otherwise it wouldn't work!". OK. > Talking about scalability problems, how do you intend to provide help on > the long run? Say you have 10 million users instead of 10, I think > numbers do play a difference. They sure do. 10 million is about two orders of magnitude off from my rough estimate for the potential user space. But the answer is that I don't know... I'll first deal with 10, then 100 and then see how things go. > On top of it, what make your company different from yet another EDA > company willing for designers to adopt their approach and strangle them > with incompatibility features that will shackle them for the rest of > their life? I'm conscious of this, and am doing my best to minimise lock-in, now and for the future (see here: https://www.boldport.com/blog/?p=3D103 ). Of course, there's a certain investment of resources in learning / adopting anything -- my hope is that what I'm proposing / offering has enough benefit for people to make that investment. Maybe I'm wrong; I'm testing my hypothesis right now. > Since is not open-source and is profit oriented, do you think it's > enough to say that your approach "is better" to convince designers to > change their habits? No; that's why I've written that long document. I tried to provide reasoning behind every choice I made, hoping to get feedback and revise as needed. > After all a designer wants to design as much as a painter wants to > paint. If art can be made with any tool available in your garage, > hardware can follow the same line and be built with just an editor or > any available tool you have in your computer (maybe a text editor is > enough!). Yes. > That is why IMHO we should foster good designing approaches that will > enhance the portability in terms of code, as opposed to project structure= . I don't see a reason why we can't have both. > The project approach is borrowed from the management world and has > nothing to do with HDL. Indeed I always asked myself why should I create > a project when my goal is to describe how a piece of hardware should > work. "Project" is a name poorly defined, a concept poorly defined, with > no boundaries and no constraints and that is the root of all your and > our problems. :) > > Thanks for your attention, > > Believe me, even though I might have sounded harsh, I paid a lot of > attention to it! Your feedback is greatly appreciated! I'm happy to continue this discussion here or privately. From newsfish@newsfish Fri Feb 3 13:13:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Tue, 05 Jul 2011 21:41:14 +0200 Lines: 116 Message-ID: <97h7mpF1seU1@mid.individual.net> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 1E3CSUA4426iha9HxMfMAADcMURuIYNnhsTn9rZ2DUWg4GX2bj Cancel-Lock: sha1:CqQn1pxlhyBPlFyHW36/Juxj0uk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.emacs:3984 comp.lang.vhdl:5098 On 7/5/2011 2:22 AM, Benjamin Couillard wrote: > Hi everyone, > > One thing I have trouble understanding is the following. Designers > typically spend way more time debugging VHDL code, running > simulations, debugging "real" hardware than writing actual code. How do you debug your code? Isn't this process of "debugging real hardware" just a matter of reading your code and understanding what it is doing? After all if the hardware doesn't work (except for pathological cases of bad pcb/pca, see later) is just because you wrote something wrong. >From this perspective having an editor that helps you out in the process of reading and editing your file is definitely a powerful tool. Would you write code with notepad? or a word processor? or with a pen and paper? If the answer is no (as I presume), than the added value of a smart editor is not negligible. > Therefore, I have trouble understanding why comparing Sigasi to Emacs > is so important? A lot of the Emacs feature are basically tools to > write code faster (code completion, sensitivity list updating, etc.). > Even If I write code 10% faster, this is probably the equivalent of a > driver speeding up only to being forced to stop because the light is > red. The analogy is imperfect, but basically in real life I'm limited > by the simulation speed of my simulator, I'm limited by the synthesis/ > p&r of Xilinx/Altera/etc. That is why you should spend more time reading and editing the file rather than running simulation. If you try to write an ARM architecture full of peripherals and then assume your simulation will run through and spot all the problems then I understand your frustration, but I also believe the approach is wrong. Project segmentation is a very old technique that is always applicable. Make your components generic enough to be reusable, not too small otherwise you will loose the overview of your design and you will clutter the code with components instantiation. Not to big otherwise you will loose valuable details of the design (usually the brain is the best tool to decide where to put the boundary). At this point test your components individually with a dedicated test bench (try "C-c C-p C-t" on emacs and then let's review your 10% speed increase) in order to trust your basic elements of your design. Only then you can more reliably move to the next step of connecting the components together, to build a bigger piece. Usually this approach force the designer to think about the interface between the components and maybe try to make it standard (like a bus). So the outcome of this process is not only more reliable, but enable the designer to build a mental toolbox of "good practices" rather than "dirty tricks". > I'm limited by real-life issues like a > faulty board, unclear specifications, project management, etc. Rarely > have I felt limited by notepad++ even though it is a simple code > editor with syntax highlighting. The faulty board, unclear specifications, project management, etc. issue are certainly part of the process. This is why your work flow should be such that the PCB is going through a verified building process, your PCA is visually inspected and your components are previously screened for "infant mortality" before you can even think about testing anything. About the unclear specification that is certainly something you need to work out earlier with your customer, otherwise you'll be off doing something different from what he/she had in mind. And this has nothing to do with the hardware at all. Same conclusion applies to the project management problems which are not a good reason to justify your faulty design (even though they maybe blamed for an incomplete one). My background comes from antifuse-logic, where one chip programmed is certainly one chip thrown away if you don't verify your code. Code review and also "rubber duck debugging" are most of the times very good practices that helps you out in getting rid of clumsy and unmaintainable implementations. I understand that it's tempting sometime to "load it and see if it works", but if you face all the problems at once you may get in real trouble with your schedule. IMHO this temptation is mostly due to the volatility of the work, which comes from the nature of the hardware used. The so called firmware we load in fpgas is similar to software from an "easy to change" standpoint and this affect deeply the mindset we have in the design and implementation phase. Should you pay from your own pocket every time you release a version that needs to be one time programmed on a chip at a cost of several K$ I bet my salary you would definitely go back and thoroughly review your process to make sure you don't miss anything anywhere and if you do I bet the second salary you will try to understand what you did wrong the first time. > > I agree than Sigasi looks interesting from a code refactoring, project > management and code comprehension perspective but less so from a > "writing code faster point of view". What would be important for me, > is good integration with Xilinx (or Altera) and good integration with > Modelsim (or Aldec). > Code refactoring is not the only motivation for a good editor. Browsing capabilities in the components structure is extremely important since it allows you to navigate your source in a faster and more efficient way, leaving you the time to think about the problem, as opposed to the simulation where you need to go for a coffee or maybe two, since you are "waiting" for the result. Spending more time with your editor will also allow you to write better maintainable code, since if you do have some sense of aesthetic you will find that a poorly written code is poorly maintainable also. > Just my 2 cents. > In response to the OP I have to say that having an editor instead of a tool is way much better, since editing is something that is part of our daily work and every time we use the editor we learn better how to use it, regardless of the mode. From newsfish@newsfish Fri Feb 3 13:13:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w24g2000yqw.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Tue, 5 Jul 2011 13:54:18 -0700 (PDT) Organization: http://groups.google.com Lines: 1 Message-ID: References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> <877h81eseo.fsf@notengoamigos.org> <97h7mpF1seU1@mid.individual.net> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309899381 29129 127.0.0.1 (5 Jul 2011 20:56:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 5 Jul 2011 20:56:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w24g2000yqw.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:3986 comp.lang.vhdl:5099 Sorry for raising a doubt about Emacs, won't happen again... From newsfish@newsfish Fri Feb 3 13:13:31 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b21g2000yqc.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 00:51:03 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 188.55.63.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309938669 5867 127.0.0.1 (6 Jul 2011 07:51:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 07:51:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b21g2000yqc.googlegroups.com; posting-host=188.55.63.142; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5100 hi all, really i want a help in these 2 problems : 1) I want a structural VHDL code of 1 to 16 Demultiplexers. with an active low Enable signal using 1 to 2 Demultiplexer. [ use Generate statement] __________________________________________________ ____________ 2) Also I need a structure and behavior VHDL code of 5-bits binary counter with a synchronous load signal to preset the counter to a specific initial state. the output of the counter ( Q0 to Q4) are connected to a binary decoder that shows the state of the counter. From newsfish@newsfish Fri Feb 3 13:13:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o4g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 06:06:17 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <3661428b-1616-488f-8514-9fe6efc9d5d5@o4g2000vbv.googlegroups.com> References: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309960201 28466 127.0.0.1 (6 Jul 2011 13:50:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 13:50:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000vbv.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5101 Wheres the problem? Looks like a set of exercises you havent started yet. Or is the problem you're too lazy to do it yourself? On Jul 6, 8:51=A0am, majmoat_ensan wrote: > hi all, > > really i want a help in these 2 problems : > > 1) > I want a structural VHDL code of 1 to 16 Demultiplexers. with an > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate > statement] > > __________________________________________________ ____________ > 2) > Also I need a structure and behavior VHDL code of 5-bits binary > counter with a synchronous load signal to preset the counter to a > specific initial state. the output of the counter ( Q0 to Q4) are > connected to a binary decoder that shows the state of the counter. From newsfish@newsfish Fri Feb 3 13:13:32 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Wed, 06 Jul 2011 18:24:51 +0200 Lines: 48 Message-ID: <97jgiiFe8vU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net WvCidfnDnijK7jfRlm7i1QTFRv4b35+av95WosiLPrXtsJq69D Cancel-Lock: sha1:e58xWOhA+uttXU2n2R4u8lBCMpE= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5102 On 6/25/2011 7:30 PM, logic_guy wrote: > TYPE states is (IDLE, S1, S2, S3, S4); > SIGNAL state : _states; > SIGNAL nDRDY_1, nDRDY_2, start : std_logic; > > start <= NOT nDRDY_1 and nDRDY_2; > > clk_proc: PROCESS > BEGIN > WAIT until rising_edge(clk); > nDRDY_1 <= nDRDY; > nDRDY_2 <= nDRDY_1; > CASE state is > WHEN IDLE => If start='1' > state <= S1; > end if; > WHEN S1 => -- Do state 1 processing here > -- when done: > state <= S2; > WHEN S2 => -- Do state 2 processing here > -- when done: > state <= S3; > WHEN S3 => -- Do state 3 processing here > -- when done: > state <= S4; > WHEN S4 => -- Do state 4 processing here > -- when done: > state <= IDLE; > -- Add or subtract states as needed > END CASE; > END PROCESS; > I would put start in the process to have it clocked. This would avoid any racing problems between nDRDY_1 and nDRDY_2. The clause "when others =>" should also be added, to land always on a "safe" state. I would also honor the OP choice of naming, being the start the input signal to this component. Last comment is on the choice of the structure "WAIT until" which I'm not very accustomed to and seems to me lacking of the "block" view which you would get with an "if then end if" syntax. I extremely appreciated the simplicity of the example and how well it describes what the hardware should do. Al From newsfish@newsfish Fri Feb 3 13:13:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set ffrom two processes ..... Date: Wed, 06 Jul 2011 19:22:02 +0200 Lines: 48 Message-ID: <97jjtqF89fU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net UX7aHc8d0QekkrNBkCJ55QkbSg+vJgM0/428vI4dzWwfwYGHDE Cancel-Lock: sha1:wFBRBpkUyD9hzmiZE2UCvyaFvok= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <5606c1b2-9edc-41bd-ac66-1c76b0dcc9bb@u30g2000vby.googlegroups.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5103 On 6/21/2011 12:46 AM, rickman wrote: > If the start signal is asserted and cleared independently of your FSM > then you need to design your machine to detect the assertion, not the > fact that it is asserted. When the FSM gets to the end of its work, > the start signal needs to be cleared before the FSM will trigger > again, in other words, enter a state where you wait for Start to be > false before you enter the state where it waits for Start to be > true. If you "detect the assertion" there's no need to wait anywhere, since you will need another "assertion". > > If the Start signal can be cleared by the FSM, then do that before > entering the state where it waits for the Start signal to be true. > Again if the FSM is designed to "detect the assertion" as you (and I also would) suggest, there's no need to do anything with it. > I can't say I understand your last part about stretching the Start > signal. It only needs to be true long enough for the FSM to see that > it is asserted. As long as that is two clock cycles, it is guaranteed > to be seen. Then you only need to see it cleared before you return to > the starting state waiting for Start to be true. Have you somehow > written your code so that if Start goes away the FSM resets? That > would be very bad and should be changed. If the start signal is asynchronous it should be first synchronized. Once it's synchronized, why the length should be two clock cycles to be seen? Why would it be bad if the start signal is used to start and reset the FSM? I agree the name would be absolutely wrong, since it should be called "enable". Certainly the reset should be synchronous. > > One other thought, the code you give that seems to be waiting for > nDRDY it treating nDRDY as a clock. Probably not a good idea unless > nDRDY is not guaranteed to be at least two clock cycles long. > I agree is a bad choice to use nDRDY as a clock, but I don't quite understand the argument of two clock cycles long, since there's no other clock in the process being nDRDY the only one. > Rick From newsfish@newsfish Fri Feb 3 13:13:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n5g2000yqh.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: wait for argument a variable? Date: Wed, 6 Jul 2011 13:16:01 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 209.36.247.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1309983449 6011 127.0.0.1 (6 Jul 2011 20:17:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 20:17:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n5g2000yqh.googlegroups.com; posting-host=209.36.247.3; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5104 Simple question: Can the argument in a "wait for (time)" be a variable? (in a test bench of course. not worried about synthesis) i.e. some_integer := 7 ... holdtime := 10 * some_integer * 1 us; wait for holdtime; From newsfish@newsfish Fri Feb 3 13:13:33 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 16:08:38 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309993807 12765 127.0.0.1 (6 Jul 2011 23:10:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 23:10:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5105 On Jul 6, 4:16=A0pm, Shannon wrote: > Simple question: =A0Can the argument in a "wait for (time)" be a > variable? =A0(in a test bench of course. =A0not worried about synthesis) > > i.e. > some_integer :=3D 7 > ... > holdtime :=3D 10 * some_integer * 1 us; > wait for holdtime; Yes. KJ P.S. Wouldn't it be easier to just try this on a simulator rather than posting to a newsgroup? From newsfish@newsfish Fri Feb 3 13:13:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!e7g2000vbw.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: can any one help me in VHDL codes plz Date: Wed, 6 Jul 2011 16:10:09 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <9799d27d-12ec-485c-bcc3-dcbeecba9208@e7g2000vbw.googlegroups.com> References: <055fd9d3-c959-4b7f-8f1f-9d3c77cbf1e2@b21g2000yqc.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1309993809 12771 127.0.0.1 (6 Jul 2011 23:10:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 6 Jul 2011 23:10:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e7g2000vbw.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5106 On Jul 6, 3:51=A0am, majmoat_ensan wrote: > hi all, > > really i want a help in these 2 problems : > > 1) > I want a structural VHDL code of 1 to 16 Demultiplexers. with an > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate > statement] > > __________________________________________________ ____________ > 2) > Also I need a structure and behavior VHDL code of 5-bits binary > counter with a synchronous load signal to preset the counter to a > specific initial state. the output of the counter ( Q0 to Q4) are > connected to a binary decoder that shows the state of the counter. What have you tried so far? What were the results? If you're just fishing for homework help, try a different pond where somebody must be silly enough to bite. KJ From newsfish@newsfish Fri Feb 3 13:13:34 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a10g2000vbz.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 19:20:06 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> NNTP-Posting-Host: 75.37.3.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310005206 30073 127.0.0.1 (7 Jul 2011 02:20:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 02:20:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a10g2000vbz.googlegroups.com; posting-host=75.37.3.30; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5107 On Jul 6, 4:08=A0pm, KJ wrote: > On Jul 6, 4:16=A0pm, Shannon wrote: > > > Simple question: =A0Can the argument in a "wait for (time)" be a > > variable? =A0(in a test bench of course. =A0not worried about synthesis= ) > > > i.e. > > some_integer :=3D 7 > > ... > > holdtime :=3D 10 * some_integer * 1 us; > > wait for holdtime; > > Yes. > > KJ > > P.S. =A0Wouldn't it be easier to just try this on a simulator rather > than posting to a newsgroup? My professors always told me to ask questions in class. If I have a question likely others do too. Thank you for educating more than just me today. From newsfish@newsfish Fri Feb 3 13:13:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.albasani.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Thu, 07 Jul 2011 05:06:17 +0200 Lines: 38 Message-ID: <97km57Ftc7U1@mid.individual.net> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 9bMIysIFuFZIt4kh6wx+fwSzLmHohCq85whSlPMfmH1AGs/CW+ Cancel-Lock: sha1:CE/sJAHoJ2c4OTqyFcS++d2610g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5108 On 7/7/2011 4:20 AM, Shannon wrote: > My professors always told me to ask questions in class. If I have a > question likely others do too. Thank you for educating more than just > me today. Your professors are definitely right in telling you so and I am also very well convinced that none of your professors encouraged you to post a question on a newsgroup if the answer is readily available somewhere else or with some minor effort. In this context I strongly suggest you a couple of readings that will help you out building relationships in the community: from the comp.lang.vhdl FAQ: - http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3 from an interesting link that you can also find in the FAQ but that I would like to underline as well: - http://www.catb.org/~esr/faqs/smart-questions.html#before For what concerns your question in particular, quoting the "IEEE Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition): > The wait statement causes the suspension of a process statement or a procedure. > wait_statement ::= > [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ; > sensitivity_clause ::= on sensitivity_list > sensitivity_list ::= signal_name { , signal_name } > condition_clause ::= until condition > condition ::= boolean_expression > timeout_clause ::= for time_expression Since your variable/constant is of type TIME, your situation does follow the standard. Al From newsfish@newsfish Fri Feb 3 13:13:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b2g2000vbo.googlegroups.com!not-for-mail From: Shannon Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Wed, 6 Jul 2011 20:23:15 -0700 (PDT) Organization: http://groups.google.com Lines: 54 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> NNTP-Posting-Host: 75.37.3.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310009115 4702 127.0.0.1 (7 Jul 2011 03:25:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 03:25:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b2g2000vbo.googlegroups.com; posting-host=75.37.3.30; posting-account=c2U1IAoAAAACL5KLIbFRGXg0ZdxHTwY7 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:2.0.1) Gecko/20100101 Firefox/4.0.1 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5109 wow. seriously? I'm being scolded for asking a simple question. REALLY?? I mean sorry to put you out. Sorry to massively affect the traffic in this NG. If it's beneath you to help then DON'T REPLY! Is this the way you really want to moderate this group? Sheesh. I apologize if my question was not up to your standards. P.S. seriously? On Jul 6, 8:06=A0pm, Alessandro Basili wrote: > On 7/7/2011 4:20 AM, Shannon wrote: > > > My professors always told me to ask questions in class. =A0If I have a > > question likely others do too. =A0Thank you for educating more than jus= t > > me today. > > Your professors are definitely right in telling you so and I am also > very well convinced that none of your professors encouraged you to post > a question on a newsgroup if the answer is readily available somewhere > else or with some minor effort. > > In this context I strongly suggest you a couple of readings that will > help you out building relationships in the community: > > from the comp.lang.vhdl FAQ: > > =A0-http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#0.3 > > from an interesting link that you can also find in the FAQ but that I > would like to underline as well: > > =A0-http://www.catb.org/~esr/faqs/smart-questions.html#before > > For what concerns your question in particular, quoting the "IEEE > Standard VHDL Language Reference Manual" (IEEE Std 1076, 2000 Edition): > > > The wait statement causes the suspension of a process statement or a pr= ocedure. > > wait_statement ::=3D > > [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_= clause ] ; > > sensitivity_clause ::=3D on sensitivity_list > > sensitivity_list ::=3D signal_name { , signal_name } > > condition_clause ::=3D until condition > > condition ::=3D boolean_expression > > timeout_clause ::=3D for time_expression > > Since your variable/constant is of type TIME, your situation does follow > the standard. > > Al From newsfish@newsfish Fri Feb 3 13:13:35 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.ripco.com!news.glorb.com!postnews.google.com!u26g2000vby.googlegroups.com!not-for-mail From: JB Newsgroups: comp.lang.vhdl Subject: Combined AFTER and WHEN statement Date: Thu, 7 Jul 2011 01:44:09 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <799412f6-d220-46c9-b513-52cb1263001e@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 80.14.138.198 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310028250 2205 127.0.0.1 (7 Jul 2011 08:44:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 08:44:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000vby.googlegroups.com; posting-host=80.14.138.198; posting-account=S4wEMQoAAADRjpmXQT29euLGCs6HM3WR User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5110 Hi folks, I'm stuggling with a problem using the following VHDL syntax: <= WHEN ELSE AFTER WHEN ELSE AFTER WHEN ELSE ... ; My testbench was working well with modelsim 6.5. But my client wan't me to use modelsim 6.3, so I tried running it on that version and BOOM: This statement generates 'X' result on my target signal when one of the is true. Is this statement valid VHDL? or is modelsim 6.3 erroneous ? Thanks in adavance. From newsfish@newsfish Fri Feb 3 13:13:36 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!eb1g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Combined AFTER and WHEN statement Date: Thu, 7 Jul 2011 02:55:04 -0700 (PDT) Organization: http://groups.google.com Lines: 28 Message-ID: <4d20acc8-9583-4cf3-8bcf-1ee24d93270e@eb1g2000vbb.googlegroups.com> References: <799412f6-d220-46c9-b513-52cb1263001e@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310034162 29051 127.0.0.1 (7 Jul 2011 10:22:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 7 Jul 2011 10:22:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: eb1g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5111 Hi, I have tried the following test with Modelsim PE 10.0b, no problems. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_when is end entity; architecture test of test_when is signal clk : std_logic := '0'; signal cnt : unsigned(2 downto 0) := (others => '0'); signal sig : std_logic := 'X'; begin clk <= (not clk) after 10 ns; cnt <= cnt + 1 when rising_edge(clk); sig <= '1' when cnt="000" else '0' after 1.5 ns when cnt="001" else 'Z' after 1.5 ns when cnt="010" else 'H'; end architecture; Cheers, hssig From newsfish@newsfish Fri Feb 3 13:13:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Thu, 7 Jul 2011 21:04:04 -0700 Organization: A noiseless patient Spider Lines: 68 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> Injection-Date: Fri, 8 Jul 2011 04:04:38 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="7532"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+da6xgWb7fBT7DGGoJoLimhTfOGIJ89Q8=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:KrmJPJ3PWRT1o1UisWMiR/HLNq0= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5112 "Alessandro Basili" wrote in message news:97jgiiFe8vU1@mid.individual.net... > On 6/25/2011 7:30 PM, logic_guy wrote: >> TYPE states is (IDLE, S1, S2, S3, S4); >> SIGNAL state : _states; >> SIGNAL nDRDY_1, nDRDY_2, start : std_logic; >> >> start <= NOT nDRDY_1 and nDRDY_2; >> >> clk_proc: PROCESS >> BEGIN >> WAIT until rising_edge(clk); >> nDRDY_1 <= nDRDY; >> nDRDY_2 <= nDRDY_1; >> CASE state is >> WHEN IDLE => If start='1' >> state <= S1; >> end if; >> WHEN S1 => -- Do state 1 processing here >> -- when done: >> state <= S2; >> WHEN S2 => -- Do state 2 processing here >> -- when done: >> state <= S3; >> WHEN S3 => -- Do state 3 processing here >> -- when done: >> state <= S4; >> WHEN S4 => -- Do state 4 processing here >> -- when done: >> state <= IDLE; >> -- Add or subtract states as needed >> END CASE; >> END PROCESS; >> > > I would put start in the process to have it clocked. This would avoid > any racing problems between nDRDY_1 and nDRDY_2. It is not necessary to put "start" in the process because it is the AND of nDRDY_1 and nDRDY_2, which are clocked by "clk", so "start" is already synchronized with "clk". Also, "start" should not have any glitches on it the way it is generated in the example. Even if it did, glitches are no problem in a synchronous system as long as the longest latch-to-latch path delay is less than the clock period. > The clause "when others =>" should also be added, to land always on a > "safe" state. An "others" clause is not needed here since "state" is defined with exactly 5 states, so there are no other states. If you did put an "others" clause there some tools would give you a warning that the "others" clause is unreachable. > I would also honor the OP choice of naming, being the start the input > signal to this component. > > Last comment is on the choice of the structure "WAIT until" which I'm > not very accustomed to and seems to me lacking of the "block" view > which > you would get with an "if then end if" syntax. "WAIT until rising_edge(clk);" is a perfectly legitimate way of specifying the clock of a clocked process and is simpler to code than the "if then end if" syntax. I work on a team that has been designing large, multi-million gate ASICs for years and we have 100,000's of lines of VHDL coded like that. Charles From newsfish@newsfish Fri Feb 3 13:13:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 08 Jul 2011 07:02:02 +0200 Lines: 43 Message-ID: <97nha9FtquU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net vbF2UkCAKNA0EVYwHdq9XQODiexpP6p63zSwH8guwuc8r6RlL7 Cancel-Lock: sha1:N/vAySpnoQTezb/zTpPeseeM7bk= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5113 On 7/8/2011 6:04 AM, logic_guy wrote: > "Alessandro Basili" wrote in message >> I would put start in the process to have it clocked. This would avoid >> any racing problems between nDRDY_1 and nDRDY_2. > It is not necessary to put "start" in the process because it is the AND > of nDRDY_1 and nDRDY_2, which are clocked by "clk", so "start" is > already synchronized with "clk". Also, "start" should not have any > glitches on it the way it is generated in the example. Even if it did, > glitches are no problem in a synchronous system as long as the longest > latch-to-latch path delay is less than the clock period. > Indeed, my bad! >> The clause "when others =>" should also be added, to land always on a >> "safe" state. > An "others" clause is not needed here since "state" is defined with > exactly 5 states, so there are no other states. If you did put an > "others" clause there some tools would give you a warning that the > "others" clause is unreachable. > Depending on the encoding (onehot, gray, etc.) the number of FF you are going to use certainly gives you more than 5 states (32 for onehot, 8 for gray). How the synthesizer is going to know what to do in case your FF are presenting a state that is not among the 5? But maybe you care if a bit flip will put your FSM in a state out of which it cannot get out. > "WAIT until rising_edge(clk);" is a perfectly legitimate way of > specifying the clock of a clocked process and is simpler to code than > the "if then end if" syntax. I'm not blaming the illegitimacy of the statement, I simply dislike it as to me it lacks of readability and as well the possibility to include an asynch reset to the process. If you can post a snippet of a code including an asynch reset I would appreciate. > > Charles > > From newsfish@newsfish Fri Feb 3 13:13:37 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!34g2000yqr.googlegroups.com!not-for-mail From: r_hwdesigner Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog Subject: job offer fpga designer genova Date: Fri, 8 Jul 2011 01:28:11 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <4f2117d3-637b-4133-bf81-67e16e05744e@34g2000yqr.googlegroups.com> NNTP-Posting-Host: 79.15.85.115 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310113766 24185 127.0.0.1 (8 Jul 2011 08:29:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Jul 2011 08:29:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 34g2000yqr.googlegroups.com; posting-host=79.15.85.115; posting-account=4cNljQoAAADEztxJHxlcD1P5IeazTZCn User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; CMNTDF; .NET4.0C; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.arch.fpga:15859 comp.lang.vhdl:5114 comp.lang.verilog:3110 we are looking for an fpga designer in Genova with the following knowledges: Operating systems Windows, Linux Programming Languages VHDL, verilog, System Verilog, C++ Tools FPGA synthesis (Precision RTL Mentor, Synplify Synplicity) FPGA verification (QuestaSim, Modelsim) FPGA implementation (QuartusII Altera, ISE Xilinx) Matlab/Simulink Versioning control (Clearcase) Competences, Skills Development of digital communication systems with ASIC/FPGA Verification of implemented functions with development of testbench and test patterns Knowledge of static timing analysis concepts (multi-clock domains, exceptions analysis) Team working capability Languages English (good in writing & speaking) From newsfish@newsfish Fri Feb 3 13:13:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: one signal set from two processes ..... Newsgroups: comp.lang.vhdl Date: Fri, 08 Jul 2011 14:11:27 +0200 References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 29 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1310127087 news2.news.xs4all.nl 21846 puiterl/195.242.97.150:33613 Xref: feeder.eternal-september.org comp.lang.vhdl:5115 Alessandro Basili wrote: >> "WAIT until rising_edge(clk);" is a perfectly legitimate way of >> specifying the clock of a clocked process and is simpler to code than >> the "if then end if" syntax. > > I'm not blaming the illegitimacy of the statement, I simply dislike it > as to me it lacks of readability For me readability is the main reason for using and promoting to use "WAIT UNTIL clk='1'" (or "WAIT UNTIL rising_edge(clk)"). As soon as I see "WAIT UNTIL clk='1'", I know that I need not look further to see what kind of process it is. It is a pure clocked process without any asynchronicities. Another (visual/layout) advantage is the lack of a long stretched if-end-if statement, which eats up indentation as well. > and as well the possibility to include > an asynch reset to the process. If you can post a snippet of a code > including an asynch reset I would appreciate. That is not possible with the WAIT statement. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:13:38 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 8 Jul 2011 08:20:47 -0700 Organization: A noiseless patient Spider Lines: 28 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Injection-Date: Fri, 8 Jul 2011 15:22:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="3710"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ZareYcqkzbTt+rOwPCfFy0BR9RjHraa4=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:ABlXL2DPZaq6ObY4HykVE8UxhHk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5116 "Paul Uiterlinden" wrote in message news:4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl... > For me readability is the main reason for using and promoting to use > "WAIT > UNTIL clk='1'" (or "WAIT UNTIL rising_edge(clk)"). > > As soon as I see "WAIT UNTIL clk='1'", I know that I need not look > further > to see what kind of process it is. It is a pure clocked process > without any > asynchronicities. > > Another (visual/layout) advantage is the lack of a long stretched > if-end-if > statement, which eats up indentation as well. > My sentiments exactly. Also, regarding asynchronous resets, those should be avoided wherever possible. The logic team I work with is just finishing an ASIC with over 900,000 latches. Only a very small handful of those have asynchronous resets. That was for a case where some logic needed to be reset when the clock wasn't running. Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t5g2000yqj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Fri, 8 Jul 2011 09:08:51 -0700 (PDT) Organization: http://groups.google.com Lines: 40 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310141331 11707 127.0.0.1 (8 Jul 2011 16:08:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 8 Jul 2011 16:08:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t5g2000yqj.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5117 On Jul 8, 1:02=A0am, Alessandro Basili wrote: > On 7/8/2011 6:04 AM, logic_guy wrote: > >> The clause "when others =3D>" should also be added, to land always on = a > >> "safe" state. > > An "others" clause is not needed here since "state" is defined with > > exactly 5 states, so there are no other states. =A0If you did put an > > "others" clause there some tools would give you a warning that the > > "others" clause is unreachable. > > Depending on the encoding (onehot, gray, etc.) the number of FF you are > going to use certainly gives you more than 5 states (32 for onehot, 8 > for gray). How the synthesizer is going to know what to do in case your > FF are presenting a state that is not among the 5? > But maybe you care if a bit flip will put your FSM in a state out of > which it cannot get out. > The synthesis tool default is not to implement safe state machines (i.e. ones that return to a particular state if it ever gets into an 'illegal' state). Unless you play with that synthesis tool setting you will not get 'safe state machines'. In particular, you will not get 'safe state machines' regardless of how the FSM states are encoded. But don't take my word for it, try your own state machine with and without an otherwise unreachable 'when others' clause, and you should see that you get the same implementation regardless of state bit encoding...or likely regardless of any other settings other than the tool control specifically for implementing safe state machines. As a parting note, the causes for getting into an illegal state are: - Timing problem - SEU In neither of these situations would it be likely that the correct course of action would be to simply go to some arbitrary reset state. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Sat, 09 Jul 2011 07:23:25 +0200 Lines: 51 Message-ID: <97q6udF98pU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net qlvFxEW6r5nx7U8SnJ219g/vMXYmco6OF0WEbVv6/ByKpChski Cancel-Lock: sha1:UPT35aP6qgYSr0whXIPEtSHY3Vs= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5118 On 7/8/2011 6:08 PM, KJ wrote: > The synthesis tool default is not to implement safe state machines > (i.e. ones that return to a particular state if it ever gets into an > 'illegal' state). > Indeed I used to turn on the "safe" mode in Synplify to have what I "wanted". > Unless you play with that synthesis tool setting you will not get > 'safe state machines'. In particular, you will not get 'safe state > machines' regardless of how the FSM states are encoded. But don't > take my word for it, try your own state machine with and without an > otherwise unreachable 'when others' clause, and you should see that > you get the same implementation regardless of state bit encoding...or > likely regardless of any other settings other than the tool control > specifically for implementing safe state machines. > And indeed the tool tends to optimize away all the "unnecessary" FF regardless of the encoding. What I did not know is that in the "safe" mode the 'when others' clause is not really followed the way it is written and Synplify will resolve the illegal state to the reset state, whether it is asynchronous or synchronous: > http://klabs.org/richcontent/software_content/safe_state_machines_synplify_1.pdf To force the tool to follow the 'when others' clause it is suggested to turn off the the FSM compiler. At this point the 'when others' clause will be exactly followed (provided the "enumerated type" is changed with constants [why???]). > As a parting note, the causes for getting into an illegal state are: > - Timing problem > - SEU > > In neither of these situations would it be likely that the correct > course of action would be to simply go to some arbitrary reset state. > Assuming the design has gone through timing analysis, the SEU is really a concern that in some applications may get you in troubles. That is why some communication protocols for space applications (ex. spacewire) can recover if the FSM fail over the reset state, causing the link on both sides to an "exchange of silence" procedure that will restore communication. I do agree that some time a "safe" state maybe safe from the FSM point of view but system wise doesn't help that much, unless every part of the design is designed to tolerate it. Al From newsfish@newsfish Fri Feb 3 13:13:39 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sat, 09 Jul 2011 19:36:31 +0100 Organization: A noiseless patient Spider Lines: 37 Message-ID: <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="14925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+27ewa7vgP6xijzqdcEjYgrJv20JOz8UM=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:mquP4mwOAkBTJqIS3LeSG7Y7mIg= Xref: feeder.eternal-september.org comp.lang.vhdl:5119 On Thu, 07 Jul 2011 05:06:17 +0200, Alessandro Basili wrote: >from an interesting link that you can also find in the > FAQ but that I would like to underline as well: > > - http://www.catb.org/~esr/faqs/smart-questions.html#before Whoa. First off, what's "not smart" about the OP's question? It shows inquiry, interest, and a reasonable grasp of the basics. Looks fine to me. How many VHDL users do _you_ know who can tell you the _full_ story about the wait statement? It's complicated and subtle. Second, let's not get too hung up about Eric Raymond's priggish and defensive protection of his chosen tribe of hackers. As usual with his stuff, you'll find much wisdom in that article - but also much that irritates and makes little sense outside the self-satisfied community of hackers. Take with a pinch of salt. Sure, the OP could have found the answer for himself. But KJ's suggestion that he try it in a simulator is disingenuous: tools have bugs, and sometimes support non-LRM-conforming constructs because some big customer demanded it, so that's not a safe way to decide what's OK and what's not. And the VHDL LRM is a very densely written and highly technical document; it's usually easier to ask an expert than to ask the LRM, especially if you're not an experienced LRM wonk. To Shannon: yes, wait-for can be given an arbitrary expression provided it yields a result of type "time". The expression is computed at the moment execution hits the wait statement, and its value determines the wait behaviour. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:13:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u2g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sat, 9 Jul 2011 18:32:42 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310261675 25611 127.0.0.1 (10 Jul 2011 01:34:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 10 Jul 2011 01:34:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u2g2000yqb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5120 On Jul 9, 2:36=A0pm, Jonathan Bromley wrote: > > Sure, the OP could have found the answer for himself. =A0 > But KJ's suggestion that he try it in a simulator is > disingenuous: Perhaps you should re-read my post. I answered the OP's question straight off, clearly, concisely and politely. As a postscript, I simply suggested that it would likely be easier to simply try the idea out rather than posting to a newsgroup and waiting for an answer (and did not write it in a way that suggested that the question was somehow beneath the standards of the group). As I did in this case, there are many times in the past when I've suggested that people try it out for themselves. That is sound advice. Trying and doing for yourself in almost all cases makes for a better learning experience than simply reading the words of others. Not only that, but sometimes you find that people post rubbish...but the way that you find out that it is rubbish is by actually trying it out for yourself. You stating that I was being disingenuous when I wasn't seems to show that you got torqued by Basili's response and decided to take it out on both him and me. You likely know the saying about 'Give a man a fish...'. I gave the OP the fish as well as a lesson in fishing. > tools have bugs, and sometimes support > non-LRM-conforming constructs because some big customer > demanded it, so that's not a safe way to decide what's > OK and what's not. You're off on a tangent here...but OK. But let me also point out that in the situations you just described the *only* way to demonstrate the bug or non-conformance is to *use* the tool. > And the VHDL LRM is a very densely > written and highly technical document; it's usually > easier to ask an expert than to ask the LRM, especially > if you're not an experienced LRM wonk. > I agree, but will add - Many times an 'expert' comes in the form of software that can be queried rather than the response from a human. - The human can also be in error as well whether or not they are an 'expert' or not. Learning can come about in many ways, don't discount any method...unless it has really been shown to be a poor learning method, or a method that just simply doesn't work for you. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:40 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Sun, 10 Jul 2011 10:48:16 +0100 Organization: A noiseless patient Spider Lines: 38 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="12386"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19NWa4sexXuplDBQ40zG5utVEYbnPp4o7Y=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:j8PEZHFrBtPF+3l5zPOh1WI3Tow= Xref: feeder.eternal-september.org comp.lang.vhdl:5121 On Sat, 9 Jul 2011 18:32:42 -0700 (PDT), KJ wrote: >As a postscript, I simply suggested that it would likely be easier to >simply try the idea out rather than posting to a newsgroup and waiting >for an answer (and did not write it in a way that suggested that the >question was somehow beneath the standards of the group). Accepted. > You stating that I was being disingenuous when I >wasn't seems to show that you got torqued by Basili's response and >decided to take it out on both him and me. Could be, although I still think it's worth pointing out the possible weakness in "trying it out" as a way of checking whether something is legal in the language. I would never dispute that experiment is a valuable learning tool, though. >- Many times an 'expert' comes in the form of software that can be >queried rather than the response from a human. >- The human can also be in error as well whether or not they are an >'expert' or not. All entirely true. We're in a field where Stuff Is Complicated, and any source of information - experts, commonsense, software, even the LRM - can be flawed by human error. Oftentimes the answer is simple, unambiguous and pretty much universally agreed. But you need to be on your guard for those few places where something goes wrong. For context, and as an excuse: I'm struggling right now (along with a lot of colleagues) on migrating a large codebase from one tool to another, and finding that their LRM conformance is imperfect. So I'm a tad sensitive about such things. Should mention, though, that my woes are with SystemVerilog. VHDL is much better specified and less messy. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:13:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.mixmin.net!news2.arglkargh.de!news.wiretrip.org!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Sun, 10 Jul 2011 15:00:31 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 Message-ID: <4e19a270$0$14260$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 22b74744.news.skynet.be X-Trace: 1310302832 news.skynet.be 14260 91.177.121.47:36527 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:5122 On 07/10/2011 11:48 AM, Jonathan Bromley wrote: > > For context, and as an excuse: I'm struggling right now (along > with a lot of colleagues) on migrating a large codebase from > one tool to another, and finding that their LRM conformance > is imperfect. So I'm a tad sensitive about > such things. Should mention, though, that my woes are with > SystemVerilog. VHDL is much better specified and less messy. Are you also struggling with LRM-compliant but different behavior among tools? (As fas as I can tell, SystemVerilog has produced even more opportunities for nondeterministic races than Verilog.) -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:13:41 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Mon, 11 Jul 2011 11:07:52 +0100 Organization: TRW Conekt Lines: 38 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net xEQerKwXI2JdTRYbeGrtRweXus1ayQ5TUzMEb9XvElU4kuccI= Cancel-Lock: sha1:qkGF8gfDxeLxxsJXsReagNnttvo= sha1:lZPKQstxsS+Xjci0EVFh2Lyu6AU= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5123 Paul Uiterlinden writes: > Alessandro Basili wrote: >> and as well the possibility to include >> an asynch reset to the process. If you can post a snippet of a code >> including an asynch reset I would appreciate. > > That is not possible with the WAIT statement. It sort of is... but it's unpleasant in various ways: process is begin -- do_reset things here wait until reset = '0'; -- wait until reset goes away main : loop wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; -- do one set of things wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; -- do another set of things -- etc.. repeat long wait until line as many times as necessary end loop; end process; Also on "inferred state machines": http://parallelpoints.com/node/69 (apologies to Chrome users, the code wraps rather than providing scroll-bars like in Firefox. I haven't figured out why yet) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:13:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Mon, 11 Jul 2011 15:23:23 +0200 Lines: 102 Message-ID: <980bq7Fpl5U1@mid.individual.net> References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 8VvSpZlFiq8dc3tBdbwoLQ7jym7ohZbHptNRbg/kR/FVrhazTq Cancel-Lock: sha1:4ugfU58CPf36XVxf49pTbJQJs8g= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5124 On 7/9/2011 8:36 PM, Jonathan Bromley wrote: > On Thu, 07 Jul 2011 05:06:17 +0200, Alessandro Basili wrote: > >>from an interesting link that you can also find in the >> FAQ but that I would like to underline as well: >> >> - http://www.catb.org/~esr/faqs/smart-questions.html#before > > Whoa. First off, what's "not smart" about the OP's > question? It shows inquiry, interest, and a reasonable > grasp of the basics. Looks fine to me. How many VHDL > users do _you_ know who can tell you the _full_ story > about the wait statement? It's complicated and subtle. > I have never qualified the question as "not smart" (it's not my fault if the link name is called that way) and indeed I took the time to point out a reference (in this case the LRM) to solve the OP's doubt. My point was rather about the method than the subject. I never talked about "standards" of any question, but I felt that the OP confused the newsgroup with her class: > My professors always told me to ask questions in class. If I have a > question likely others do too. Thank you for educating more than just > me today. which IMHO is not true. Therefore the suggestions to follow the NG's FAQs. > Second, let's not get too hung up about Eric Raymond's > priggish and defensive protection of his chosen tribe > of hackers. As usual with his stuff, you'll find much > wisdom in that article - but also much that irritates > and makes little sense outside the self-satisfied > community of hackers. Take with a pinch of salt. > I do agree that *everything* should be taken with a pinch of salt, even the words of an expert that share his wisdom or simply his point of view. I find Eric Raymond's article quite to the point when he talks about doing something "before you ask", that is why I pointed out the link to that paragraph. If you are concerned that Eric Raymond's article does not embody the spirit of this NG I would probably be on the same boat, nevertheless I take it with the grain of salt it needs to extract any useful information from the noise of nowadays communications. If you think the quoted article is disrespectful and should be removed from the FAQs of this NG than probably we need to face this issue more intensively and I encourage you to send your comments to the editor of the FAQ: > edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska) or maybe open a dedicated thread (which can be ignored by people not interested). > Sure, the OP could have found the answer for himself. That is why I also pointed out the "try yourself first" approach reported in Raymond's article. This approach is surely the most powerful even though potentially very dangerous, since we can be deceived by the fact that "it worked" and miss the grasp on the problem. I doubt though the OP was interested in your mentioned complicated and subtle nuances of the "wait statement". She showed interest in a case where the wait statement was involved and the time expression was a variable of TIME type and that's it (or at least I didn't catch anything between the lines). > But KJ's suggestion that he try it in a simulator is > disingenuous: tools have bugs, and sometimes support > non-LRM-conforming constructs because some big customer > demanded it, so that's not a safe way to decide what's > OK and what's not. And the VHDL LRM is a very densely > written and highly technical document; it's usually > easier to ask an expert than to ask the LRM, especially > if you're not an experienced LRM wonk. Do you really believe the OP would have asked the question if she went through a simulator without any problem? And what is the added value of an expert with the respect to a tool which is used by tons of users who are actively reporting all sorts of bugs? On top of it the OP didn't ask: > Can the argument in a "wait for (time)" be a > variable? since the simulator XYZ is giving me an error of type 123. which would have been much more appropriate, showing the interest of the OP to solve his/her problem and triggering the possibility for a "bug report". I found KJ's suggestion rather to the point and I admit I got a little shaky myself on the OP's reply to that post when she disingenuously wrote about her professors. I do not argue the value of the question, but I do disagree with the process the OP chose to learn something. Have I been too rude? Did I hurt somebody's feeling? Well I didn't intend to, but I do believe the NG is a valuable resource for people to learn, stimulating thoughts and doubting answers, in a process that foster searches and exchange of point of views and I did not read any of the former in the OP's first intent. Al From newsfish@newsfish Fri Feb 3 13:13:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news.musoftware.de!wum.musoftware.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Mon, 11 Jul 2011 17:07:58 +0200 Lines: 65 Message-ID: <980huaF95fU1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 4r1ON0D3uWuNEmH6juQF+Q0Zk1Kd3z8xFmGgGfMVNSMsVdJYbc Cancel-Lock: sha1:dM+Fp+QC8/Ws/AnVAQYLhyQcUdg= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5125 On 7/11/2011 12:07 PM, Martin Thompson wrote: [...] > process is > begin > -- do_reset things here > wait until reset = '0'; -- wait until reset goes away > main : loop > wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; > -- do one set of things > wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; > -- do another set of things > -- etc.. repeat long wait until line as many times as necessary > end loop; > end process; > Isn't the "exit main when reset = '1'" a synchronous reset? The way I read is the following: - wait until rising_edge(clk) and then - if reset = '1' exit the main loop. Am I wrong (*)? > Also on "inferred state machines": > > http://parallelpoints.com/node/69 > very interesting approach. And I do share the same view when you say: > it saves you having to think of names for your states since IMHO what is more critical is the condition under which an FSM moves from one state to the other, rather than the state itself. The suggestion to move at a higher level of description and leave the synthesizer infer whatever is needed to perform the functionality described is the right way of exploiting the language. Too many times we loose ourselves amongst gates and flops forgetting the big picture. Two comments though: - giving the impression that "less code is usually good" is a misconception (as Nemo's father would say about clownfish). Being on the defense line "the smaller the better" usually drives designers to write unreadable and therefore unmaintainable code. - comparing vhdl with C# in terms of lines of code is risky. Hardware acceleration is nothing related to the lines of code and its main goal is to search for tasks in the sequential (and/or multi-threaded) computing that can be performed in parallel by an external device (or additional dedicated CPU) in the hope of being more efficient (number of computations/cycle). Nothing related to lines of code. > (apologies to Chrome users, the code wraps rather than providing scroll-bars > like in Firefox. I haven't figured out why yet) > Didn't work for me as well, but found the following: http://code.google.com/p/chromium/issues/detail?id=10533 even though they claim they fixed this problem... (*) my apologies I cannot try it out myself...reinstalling my pc! :-( From newsfish@newsfish Fri Feb 3 13:13:42 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h14g2000yqd.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.vhdl Subject: [ANN] HercuLeS high-level synthesis tool Date: Mon, 11 Jul 2011 08:35:51 -0700 (PDT) Organization: http://groups.google.com Lines: 44 Message-ID: <955f8beb-c212-4091-bcc8-b30e2d2502f3@h14g2000yqd.googlegroups.com> NNTP-Posting-Host: 94.70.55.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310398726 14318 127.0.0.1 (11 Jul 2011 15:38:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 15:38:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h14g2000yqd.googlegroups.com; posting-host=94.70.55.49; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5126 Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for non- trivial work. HercuLeS allows you to synthesize ANSI C code (certain rules apply) to RTL VHDL. HercuLeS is named after the homonymous constellation and not after the demigod. You can find information on HercuLeS here: http://www.nkavvadias.com/hercules/index.html Some of its features: 1. Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths 2. It is able to synthesize VHDL from code spanning across several C functions 3. Support for both the Synopsys "de-facto standard" libraries and the official IEEE standard libraries 4. Support of synchronous read ROM and RAM memories (directly mapped to FPGA block RAMs) 5. Functions can pass single-dimensional array arguments 6. Support of streaming outputs (producing a sample at a time) You can either code your input in ANSI C or in a bit-accurate typed- assembly language called NAC (N-Address Code). Then, your input is converted to a series of CDFGs (Control/Data Flow Graphs), expressed as Graphviz graphs with user-defined attributes, which again are translated to VHDL code adhering to the FSMD (Finite-State Machine with Datapath) paradigm. I would appreciate if you had a look at the sample files available at the website. They illustrate complete examples of automatically synthesized algorithms such as Bresenham's line drawing algorithm, and the Sieve of Eratosthenes. Overall, eight complete examples can be found at the HercuLeS website. There will be regular updates on the HercuLeS webpage (every 1-1.5 months). The October update, scheduled for 2011/10/11, will allow access to HercuLeS via a web interface! But first I would appreciate feedback on whatever related to the HercuLeS webpage. Best regards, Nikolaos Kavvadias Lecturer, Research Scientist, Hardware developer, Ph.D., M.Sc., B.Sc. From newsfish@newsfish Fri Feb 3 13:13:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.mixmin.net!feeder.news-service.com!postnews.google.com!r27g2000prr.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Synthesis of 'X' Date: Mon, 11 Jul 2011 09:28:19 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 67.188.14.18 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310401700 11999 127.0.0.1 (11 Jul 2011 16:28:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 16:28:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r27g2000prr.googlegroups.com; posting-host=67.188.14.18; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5127 Hello, Is there a standard way in which the value 'X' assigned to a signal gets synthesized? I would assume that it would just trigger a synchronous LUT reset. Thanks, Colin From newsfish@newsfish Fri Feb 3 13:13:43 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z14g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Mon, 11 Jul 2011 09:48:03 -0700 (PDT) Organization: http://groups.google.com Lines: 27 Message-ID: References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310402884 23878 127.0.0.1 (11 Jul 2011 16:48:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 11 Jul 2011 16:48:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z14g2000yqh.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5128 On Jul 11, 12:28=A0pm, Colin Beighley wrote: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? > Since 'X' is the result of driving '0' and '1' together I would hope that this would not be synthesizable. I'm guessing though that you mean 'X' as a "don't care". In that case, I don't think there is a 'standard', but the synthesis tools will report to you what they are using when they come across your use of 'X'. However, you mentioned X getting assigned to a signal which implies you mean sig <=3D 'X'; Maybe you meant a don't care which is sig <=3D '-'; In either case, you're at the mercy of the synthesis tools which as I mentioned should report what value it is using for 'X' or '-'. > I would assume that it would just trigger a synchronous LUT reset. > Wow...that is not at all what I would assume. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:13:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l28g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Tue, 12 Jul 2011 00:47:38 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <2ac48be7-58da-4add-9af9-d112a34b43c2@l28g2000yqc.googlegroups.com> References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310457748 26911 127.0.0.1 (12 Jul 2011 08:02:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 12 Jul 2011 08:02:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l28g2000yqc.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5129 On Jul 11, 5:28=A0pm, Colin Beighley wrote: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? > > I would assume that it would just trigger a synchronous LUT reset. > > Thanks, > Colin Given that LUTs are not even resettable, I dont know how you'd come to this conclusion. 'X's should only ever be used to indicate a problem in simulation, like this: if en =3D '1' then output <=3D a; elsif en =3D '0' then output <=3D 'b; else output <=3D (others =3D> 'X'); end if; If you really mean dont care, its not until recently that the language had much support for dont care ('-', not 'X'). now, in VHDL you can use them in case statements, but thats about it afaik. Before VHDL 2008 it would literally compare the string to dont care, so even if the bits were '1' or '0', the test would fail. now you can write: case? s is when "00--" =3D> --do something with MSBs =3D 0 when "001-" =3D> --etc. From newsfish@newsfish Fri Feb 3 13:13:44 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Tue, 12 Jul 2011 09:46:37 +0100 Organization: TRW Conekt Lines: 88 Message-ID: References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> <980huaF95fU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net AMKRvLDU/0oMhuHMFwniFArdEcTozfSqWedqeqLtJMMqMrekw= Cancel-Lock: sha1:UqmbZTu7aAtCdarbDdzikCul7Lk= sha1:So7bDxCqCJyLxJhKuh9LYrGgNl8= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5130 Alessandro Basili writes: > On 7/11/2011 12:07 PM, Martin Thompson wrote: > [...] >> process is >> begin >> -- do_reset things here >> wait until reset = '0'; -- wait until reset goes away >> main : loop >> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >> -- do one set of things >> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >> -- do another set of things >> -- etc.. repeat long wait until line as many times as necessary >> end loop; >> end process; >> > > Isn't the "exit main when reset = '1'" a synchronous reset? The way I > read is the following: > > - wait until rising_edge(clk) and then wait until rising_edge(clk) or falling_edge(reset) ^^^^^^^^^^^^^^^^^^^^^^ > - if reset = '1' exit the main loop. > > Am I wrong (*)? > reset is also "in the sensitivity list" of the wait statement. >> Also on "inferred state machines": >> >> http://parallelpoints.com/node/69 >> > > very interesting approach. And I do share the same view when you say: > >> it saves you having to think of names for your states > > since IMHO what is more critical is the condition under which an FSM > moves from one state to the other, rather than the state itself. > The suggestion to move at a higher level of description and leave the > synthesizer infer whatever is needed to perform the functionality > described is the right way of exploiting the language. Too many times we > loose ourselves amongst gates and flops forgetting the big picture. > > Two comments though: > > - giving the impression that "less code is usually good" is a > misconception (as Nemo's father would say about clownfish). Being on the > defense line "the smaller the better" usually drives designers to write > unreadable and therefore unmaintainable code. > Yes, it always needs some common-sense applying. But note that I didn't say "smaller is better". "Less code is *usually* good". A much weaker assertion :) > - comparing vhdl with C# in terms of lines of code is risky. Oh, yes of course - it's not meant to be much more than a pseudo-academic "playing with possibilities". My original motivation was simply in response to the originally presented HDL solution to show that the VHDL *could* look much like the C# approach. (Bar the horrible-ness of the clocking construct). But I also feel that "lines of code" is not a metric to be completely discarded. > Hardware acceleration is nothing related to the lines of code and its > main goal is to search for tasks in the sequential (and/or > multi-threaded) computing that can be performed in parallel by an > external device (or additional dedicated CPU) in the hope of being > more efficient (number of computations/cycle). Nothing related to > lines of code. No, but if you can (readably!) do the same thing in many less lines of code, that's a win, surely? LOC matters not to the machine, but it is still a significant metric to the programmer/designer, and even more so to the reviewers of said code. Cheers, Martin (all his own opinions) From newsfish@newsfish Fri Feb 3 13:13:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of 'X' Date: Tue, 12 Jul 2011 12:34:33 +0100 Organization: TRW Conekt Lines: 39 Message-ID: References: <16abce21-841a-4b51-a8c9-ac24397dc235@r27g2000prr.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net 8xk9MUrOp6IVKv8HpJ3Y5Akznywo1BmtSgYnUbwImIaAXfRyA= Cancel-Lock: sha1:RQQUvsJV125zWrkru/E+SEuQnEQ= sha1:wlK2KfS2q6vjysoS8j9kUeeM3QA= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5131 Colin Beighley writes: > Hello, > > Is there a standard way in which the value 'X' assigned to a signal > gets synthesized? 'X' tends not to be assigned to signals directly - it's the result of driving a '0' and a '1' at the same time. You *can* assign it yourself, and synthesis tools *may* treat it as a don't care. (If you want a don't care, '-' is the VHDL value which you can assign to a signal/variable. Synthesis tools (IME) will treat it properly and use that knowledge to optimise logic. Be aware that the normal '=' operator doesn't work that way though - you have to use std_match) > > I would assume that it would just trigger a synchronous LUT reset. > That's an interesting assumption on a few counts: 1) The LUTs are not synchronous 2) *Assuming* you meant a flipflop, the synchronous (or not) nature of a write to a signal depends on the context in which it's written, not the value that's written. 3) *Assuming* 'X' were to be representable and assigned in a clocked process, would the flipflop not just take the value 'X' (as in simulation) and propagate it to the output? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:13:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: one signal set from two processes ..... Date: Tue, 12 Jul 2011 15:20:09 +0200 Lines: 32 Message-ID: <983004F8p9U1@mid.individual.net> References: <4d2854dc-ffd8-4a7b-8f8f-c272f272db1d@a10g2000vbz.googlegroups.com> <97jgiiFe8vU1@mid.individual.net> <97nha9FtquU1@mid.individual.net> <4e16f3ef$0$21846$e4fe514c@news2.news.xs4all.nl> <980huaF95fU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net IIXPQJ7VH/EbEHgkrVJFpwBPVBSwk1eJqYqhLvUQjsNjRJ8l5j Cancel-Lock: sha1:wafoGooBJb/GbHaEqOTAYRYdLvw= User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: X-Enigmail-Version: 1.1.1 Xref: feeder.eternal-september.org comp.lang.vhdl:5132 On 7/12/2011 10:46 AM, Martin Thompson wrote: > Alessandro Basili writes: > >> On 7/11/2011 12:07 PM, Martin Thompson wrote: >> [...] >>> process is >>> begin >>> -- do_reset things here >>> wait until reset = '0'; -- wait until reset goes away >>> main : loop >>> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >>> -- do one set of things >>> wait until rising_edge(clk) or falling_edge(reset); exit main when reset = '1'; >>> -- do another set of things >>> -- etc.. repeat long wait until line as many times as necessary >>> end loop; >>> end process; >>> >> >> Isn't the "exit main when reset = '1'" a synchronous reset? The way I >> read is the following: >> >> - wait until rising_edge(clk) and then > > wait until rising_edge(clk) or falling_edge(reset) > ^^^^^^^^^^^^^^^^^^^^^^ > I was much too distracted by the "exit main when reset = '1';" that I totally miss that! Uhm, talking about readability I do admit the reader sometimes has his/her own responsability :-) My apologies. From newsfish@newsfish Fri Feb 3 13:13:45 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.emacs, comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Message-ID: From: Andreas Ehliar Date: 12 Jul 11 17:47:10 CEST Followup-To: comp.emacs, comp.lang.vhdl References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 107 Xref: feeder.eternal-september.org comp.emacs:4013 comp.lang.vhdl:5133 On 2011-06-27, Philippe Faes wrote: > To end my series of blog posts about Emacs vs. Eclipse/Sigasi, I am > interested to hear what you think: are there any _technical_ reasons > why Emacs is still better than an IDE solution? Or is it just a matter > of "I love this tool and nobody is going to deny me my rights?" Well, I think I could characterize myself as a fairly competent Emacs user. However, just for fun I have just downloaded Sigasi 2.0 to look into whether it could replace Emacs for my VHDL editing tasks. However, do be aware that I've used Emacs as my main editor since about 1998. So this is not likely to be a very fair comparison since I haven't used Sigasi for more than an hour or so by following the tutorial and trying it on one of my own VHDL projects. What follows are some notes from my testing and what I find missing as compared to Emacs. Of course, some of these features may be present but not working in exactly the same way as in Emacs which is why I didn't find them. * When using Emacs I can just type "emacs filename.vhd" (or an alias for emacsclient if I expect that I will need to look into a lot of different files using the same editor instance). I'm not sure how to do this in Sigasi. Merely typing sigasi filename.vhd doesn't seem to work at least and sigasi -h or sigasi --help didn't give me any indication that it is possible to do this from the commandline easily. * It was fairly easy to find and enable the Emacs key scheme which made it quite a bit more comfortable to use for me. Good. * Incremental search worked as expected when pressing C-s and C-r. However, some useful commands in Emacs are not present. Of this the greatest loss is C-w (which adds the string following the cursor to the search string). Very convenient when you want to search for the word you are currently looking at. Nevertheless, merely the presence of an easy to use incremental search is a big plus. * Ctrl-g didn't work to abort a search and return to the start location of the search as expected. However, Ctrl-x Ctrl-x worked as expected which is good. * I use M-q in Emacs all the time when writing text (for example in the form of comments) to make sure that the text is nicely aligned and doesn't exceed a user configurable number of characters per line. (Usually a little less than 80.) In Sigasi M-q doesn't seem to do anything. * There doesn't seem to be any kill ring functionality. (Or similar history functionality for other commands such as search.) * The keys for rectangular cut and paste and string rectangle don't do anything. (Neither the standard keybindings nor the cua-mode version where you press ctrl-enter to start a rectangular selection.) * I couldn't find any keyboard macro functionality :( This is actually a really big issue for me. If you don't have macros you can't do a lot of really really neat tricks. While I don't use keybaord macros every day, they can really save you a lot of work in some situations. See the following youtube clip for some inspiration: http://www.youtube.com/watch?v=zropjwVQlWQ&NR=1 * C-x C-b worked to select the buffer as expected. Good! (However, it is not as powerful as iswitchb-mode in Emacs.) * I turned off the Emacs keybindings to enable the use of C-SPACE for template insertion. I'm somewhat skeptical about how these are implemented, but I admit that this may be because I'm not used to them. * After trying out C-SPACE I changed the keys back to Emacs again. But this change didn't seem to take effect. Perhaps I did something wrong? A restart of Sigasi didn't fix it either. * When opening an existing design which included components written in both VHDL and Verilog there was no support for Verilog at all in the editor. (Since I use both Verilog and VHDL fairly frequently this is an issue for me. If you use Verilog rarely it may not be a big problem though.) All in all, Sigasi seems to be a major step up as compared to some other VHDL editing solutions (for example, I'd much rather use Sigasi than the ISE text editor). However, it will not replace Emacs for me anytime soon I'm afraid. The main reason why it is very hard to get me to change from Emacs to some other editor is that my entire workflow is based around Emacs. This allows me to utilize the same skill set regardless of whether I edit Verilog, VHDL, HTML, C, shell script, or MP3 files. (Yes, I have done some simple editing of MP3 files in Emacs in some situations.) In addition to text editing I'm also using Emacs for reading mail, organizing my schedule, and dealing with my TODO-list. I often find myself running a shell from within Emacs as well. (The unix shell running in split screen with a scratch buffer in Emacs can do some really powerful things when combined with macros.) I could probably spend another hour here merely listing some nice Emacs tricks but I think I'll end here by wishing you good luck. While I don't expect many die hard Emacs users to switch to Sigasi I think you may have a good chance of snatching up people who only use Emacs for VHDL editing. regards /Andreas From newsfish@newsfish Fri Feb 3 13:13:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Tue, 12 Jul 2011 19:17:42 +0100 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="18381"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X3Ccx4j9z2ODDLlM2+Ls08NSbaM0qhWs=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:dmIji/+EGgu1yD/+UdjQnduEPiw= Xref: feeder.eternal-september.org comp.lang.vhdl:5134 On Sun, 10 Jul 2011 15:00:31 +0200, Jan Decaluwe wrote: >Are you also struggling with LRM-compliant but different >behavior among tools? (As fas as I can tell, SystemVerilog >has produced even more opportunities for nondeterministic races >than Verilog.) After all these years, my sanity-preservation strategies are fairly well honed :-) I'm not sure why you think SV is any worse than vanilla Verilog. It also provides various tools to help you if you are perverse enough to want to get things right: clocking blocks, $sampled, ... although those too have their pitfalls, and the poor RTL designer is in just as much of a mess as always (pun intended). -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:13:46 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!tranq7.tranquility.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!195.114.241.41.MISMATCH!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Tue, 12 Jul 2011 22:09:31 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? References: <7d16953f-53bc-4ae0-a828-a27ae7870bf7@n5g2000yqh.googlegroups.com> <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 31 Message-ID: <4e1ca9fc$0$14255$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 864a082d.news.skynet.be X-Trace: 1310501372 news.skynet.be 14255 91.177.8.150:53829 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:5135 On 07/12/2011 08:17 PM, Jonathan Bromley wrote: > On Sun, 10 Jul 2011 15:00:31 +0200, Jan Decaluwe wrote: > >> Are you also struggling with LRM-compliant but different >> behavior among tools? (As fas as I can tell, SystemVerilog >> has produced even more opportunities for nondeterministic races >> than Verilog.) > > After all these years, my sanity-preservation strategies > are fairly well honed :-) I had inferred - probably incorrectly - that the original code was written by someone else :-) > I'm not sure why you think SV is any worse than vanilla > Verilog. Not from personal experience, and perhaps incorrect again. My thoughts about this orginate from reading Janick Bergeron's "Writing Testbenches with SystemVerilog", when he explains program versus module threads and why you need "clocking" blocks to describe proper synchronous behaviour. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:13:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: wait for argument a variable? Date: Tue, 12 Jul 2011 22:15:12 +0100 Organization: A noiseless patient Spider Lines: 44 Message-ID: References: <4f7d2a04-e6b1-4510-bc4a-169d510a2d6b@r18g2000vbs.googlegroups.com> <97km57Ftc7U1@mid.individual.net> <667h179iknb4ln4so8upo577vi50jbe3e9@4ax.com> <4e19a270$0$14260$ba620e4c@news.skynet.be> <4e1ca9fc$0$14255$ba620e4c@news.skynet.be> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="28360"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18k+3l4HVGUighjn4vLq6cjmuf0iJq+V78=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:VkYFfjuJYjFLTmOryGI1rciv8Bk= Xref: feeder.eternal-september.org comp.lang.vhdl:5136 On Tue, 12 Jul 2011 22:09:31 +0200, Jan Decaluwe wrote: >My thoughts about this orginate from reading Janick Bergeron's >"Writing Testbenches with SystemVerilog", when he explains >program versus module threads and why you need "clocking" >blocks to describe proper synchronous behaviour. This is getting a bit OT for c.l.vhdl, but it may at least provide a few moments of schadenfreude. Way back when, program blocks, clocking blocks and modules all worked together in a specific way to give race-free interaction between testbench and DUT. Unfortunately, when SV hit the public streets, people started doing odd things. First they asked what would happen if you used a clocking block without a program block, or vice versa, since there's nothing in the language syntax to say you can't do that. Second, people had the temerity to create verification environments where the DUT/TB division was perhaps not quite so clear-cut as the inventors of clocking and program blocks might have imagined. And finally, they sometimes manipulated signals (and even, horror of horrors, clocking blocks) in a way that wasn't directly related to any clock. Faced with this rebellious and perverse behaviour by users, the SV community had no choice but to specify in reasonable detail what these constructs actually do. And some of those things are not terribly convenient, but at least they are now (since 1800-2009) fairly well defined. Used properly, they are not plagued by nondeterminism. So we're now left with the situation that clocking blocks and programs give a certain set of very useful behaviours if used in just the right way; but, when abused, those same constructs can do remarkably silly things. Anyway... like I said, it's way OT for here. Still kinda fun, though. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:13:47 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Nicholas_Collin_Paul_de_Glouce=C5=BFter?= Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: [ANN] HercuLeS high-level synthesis tool Date: Wed, 13 Jul 2011 11:34:31 +0000 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="9724"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/eKxa9Kt8rQBE62S5j9dC6q0H4xQvhPmTSg5vZz71v8A==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: Cancel-Lock: sha1:YsyqbVV1MZaU6sWpsXb5Btkwx+c= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.verilog:3121 comp.arch.fpga:15891 comp.arch:17081 comp.arch.embedded:23322 comp.lang.vhdl:5137 Dr. Kavvadias sent on July 11th, 2011: |----------------------------------------------------------| |"[..] | | | |You can [..] code your input [..] in a bit-accurate typed-| |assembly language called NAC (N-Address Code). [..] | |[..] | | | |[..]" | |----------------------------------------------------------| Ah, strongly typed assembly languages. One does not see many of those. From newsfish@newsfish Fri Feb 3 13:13:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!y13g2000yqy.googlegroups.com!not-for-mail From: Philippe Faes Newsgroups: comp.emacs,comp.lang.vhdl Subject: Re: Are there technical reasons why Emacs is better than an IDE? Date: Wed, 13 Jul 2011 05:24:56 -0700 (PDT) Organization: http://groups.google.com Lines: 150 Message-ID: <9d298138-b181-4624-8624-3d1a6f7828c2@y13g2000yqy.googlegroups.com> References: <57108121-0931-4a02-9a1f-1936c42be580@c29g2000yqd.googlegroups.com> NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310559897 20018 127.0.0.1 (13 Jul 2011 12:24:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 12:24:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y13g2000yqy.googlegroups.com; posting-host=195.144.71.15; posting-account=Dh2KDAoAAACN2skkW5NrnTSyvGjOAQ7F User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.emacs:4020 comp.lang.vhdl:5138 On Jul 12, 5:47=A0pm, Andreas Ehliar wrote: > Well, I think I could characterize myself as a fairly competent Emacs > user. However, just for fun I have just downloaded Sigasi 2.0 to look > into whether it could replace Emacs for my VHDL editing tasks. > > However, do be aware that I've used Emacs as my main editor since > about 1998. So this is not likely to be a very fair comparison since I > haven't used Sigasi for more than an hour or so by following the > tutorial and trying it on one of my own VHDL projects. Andreas, thank you for your in-depth evaluation. It seems you have focussed on text editing and search operations. Obviously, the tool you have known for years will give you better results. I'm not sure if you have looked at type-time compilation (with error checking), and other advanced VHDL-specific features (navigation, hovers, refactoring). If anybody is to be convinced of dropping Emacs, it would be because of those features. > What follows are some notes from my testing and what I find missing as > compared to Emacs. Of course, some of these features may be present > but not working in exactly the same way as in Emacs which is why I > didn't find them. > > * When using Emacs I can just type "emacs filename.vhd" (or an alias > =A0 for emacsclient if I expect that I will need to look into a lot of > =A0 different files using the same editor instance). > > =A0 I'm not sure how to do this in Sigasi. Merely typing sigasi > =A0 filename.vhd doesn't seem to work at least and sigasi -h or sigasi > =A0 --help didn't give me any indication that it is possible to do this > =A0 from the commandline easily. We'll get that working soon. Thanks for pointing it out. > > * It was fairly easy to find and enable the Emacs key scheme which > =A0 made it quite a bit more comfortable to use for me. Good. Thanks > * Incremental search worked as expected when pressing C-s and > =A0 C-r. However, some useful commands in Emacs are not present. Of this > =A0 the greatest loss is C-w (which adds the string following the cursor > =A0 to the search string). Very convenient when you want to search for > =A0 the word you are currently looking at. Nevertheless, merely the > =A0 presence of an easy to use incremental search is a big plus. > > * Ctrl-g didn't work to abort a search and return to the start > =A0 location of the search as expected. However, Ctrl-x Ctrl-x worked as > =A0 expected which is good. > > * I use M-q in Emacs all the time when writing text (for example in > =A0 the form of comments) to make sure that the text is nicely aligned > =A0 and doesn't exceed a user configurable number of characters per > =A0 line. (Usually a little less than 80.) In Sigasi M-q doesn't seem to > =A0 do anything. Code formatting is mapped to CTRL+SHIFT+F. Remappable, though. > * There doesn't seem to be any kill ring functionality. (Or similar > =A0 history functionality for other commands such as search.) Not that I know of... > * The keys for rectangular cut and paste and string rectangle don't do > =A0 anything. (Neither the standard keybindings nor the cua-mode version > =A0 where you press ctrl-enter to start a rectangular selection.) > Rectangle editing (block select) can be activated using CRTL+ALT+A with normal key bindings. There is also an icon in the tool bar: http://www.vasanth.in/2009/03/31/eclipse-tip-block-selection-mode/ > * I couldn't find any keyboard macro functionality :( This is actually > =A0 a really big issue for me. If you don't have macros you can't do a > =A0 lot of really really neat tricks. While I don't use keybaord macros > =A0 every day, they can really save you a lot of work in some > =A0 situations. See the following youtube clip for some inspiration: > =A0http://www.youtube.com/watch?v=3DzropjwVQlWQ&NR=3D1 Good point. There might be an Eclipse plugin that offers marcros in a way that you need. I'm not sure. > > * C-x C-b worked to select the buffer as expected. Good! (However, it > =A0 is not as powerful as iswitchb-mode in Emacs.) > > * I turned off the Emacs keybindings to enable the use of C-SPACE > =A0 for template insertion. I'm somewhat skeptical about how these are > =A0 implemented, but I admit that this may be because I'm not used to > =A0 them. You can tie the template insertion to another key combination if you like: http://www.sigasi.com/faq/can-i-change-default-key-bindings > > * After trying out C-SPACE I changed the keys back to Emacs again. But > =A0 this change didn't seem to take effect. Perhaps I did something > =A0 wrong? A restart of Sigasi didn't fix it either. Bug in Eclipse. Try "restore to defaults". > * When opening an existing design which included components written in > =A0 both VHDL and Verilog there was no support for Verilog at all in the > =A0 editor. (Since I use both Verilog and VHDL fairly frequently this is > =A0 an issue for me. If you use Verilog rarely it may not be a big > =A0 problem though.) Yeah, we'll get to Verilog. We didn't want to offer syntax highlighting because that could create false expectations. http://www.sigasi.com/keep-me-informed-about-verilog > All in all, Sigasi seems to be a major step up as compared to some > other VHDL editing solutions (for example, I'd much rather use Sigasi > than the ISE text editor). However, it will not replace Emacs for me > anytime soon I'm afraid. > > The main reason why it is very hard to get me to change from Emacs to > some other editor is that my entire workflow is based around > Emacs. This allows me to utilize the same skill set regardless of > whether I edit Verilog, VHDL, HTML, C, shell script, or MP3 > files. (Yes, I have done some simple editing of MP3 files in Emacs in > some situations.) You can edit HTML, C and shell scripts in Eclipse. Just install the right plugin. (No MP3 editing in Eclipse, though!) > In addition to text editing I'm also using Emacs for reading mail, > organizing my schedule, and dealing with my TODO-list. I often find > myself running a shell from within Emacs as well. (The unix shell > running in split screen with a scratch buffer in Emacs can do some > really powerful things when combined with macros.) > > I could probably spend another hour here merely listing some nice > Emacs tricks but I think I'll end here by wishing you good luck. While > I don't expect many die hard Emacs users to switch to Sigasi I think > you may have a good chance of snatching up people who only use Emacs > for VHDL editing. > > regards > /Andreas Thanks for the encouraging words! -- kind regards Philippe From newsfish@newsfish Fri Feb 3 13:13:48 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder.news-service.com!postnews.google.com!u26g2000vby.googlegroups.com!not-for-mail From: Julien REINAULD Newsgroups: comp.lang.vhdl Subject: empty array litteral Date: Wed, 13 Jul 2011 05:54:09 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 88.162.182.86 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310561650 4981 127.0.0.1 (13 Jul 2011 12:54:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 12:54:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u26g2000vby.googlegroups.com; posting-host=88.162.182.86; posting-account=rrbtogoAAABnM_lBzLFGDjhSlgIHQgSY User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux x86_64; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.133 Safari/534.16,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5139 Hi all! According to std.standard: TYPE string IS ARRAY ( positive RANGE <> OF character); "hello" is a valid string litteral "" is a valid string litteral too, it is the empty string. Let TYPE foo IS ARRAY ( positive RANGE <> OF integer); (0, 1, 1, 2, 3, 5) is a valid foo litteral What is the litteral for an empty foo? Thx Julien From newsfish@newsfish Fri Feb 3 13:13:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: empty array litteral Date: Wed, 13 Jul 2011 06:25:42 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: References: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310563543 24464 127.0.0.1 (13 Jul 2011 13:25:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 13:25:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5140 On Jul 13, 1:54=A0pm, Julien REINAULD wrote: > Hi all! > > According to std.standard: > > TYPE string IS ARRAY ( positive RANGE <> OF character); > > "hello" is a valid string litteral > "" is a valid string litteral too, it is the empty string. > > Let > > TYPE foo IS ARRAY ( positive RANGE <> OF integer); > > (0, 1, 1, 2, 3, 5) is a valid foo litteral > > What is the litteral for an empty foo? > > Thx > > Julien That is an interesting question. You can make a null constant like this: constant NULL_FOO : foo(1 downto 2) :=3D (others =3D> 0); then use the constant in place of a literal. From newsfish@newsfish Fri Feb 3 13:13:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: Tom Gardner User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.16) Gecko/20101206 SeaMonkey/2.0.11 MIME-Version: 1.0 Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: [ANN] HercuLeS high-level synthesis tool References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Lines: 17 Message-ID: NNTP-Posting-Host: 94.169.71.150 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1310572172 94.169.71.150 (Wed, 13 Jul 2011 15:49:32 UTC) NNTP-Posting-Date: Wed, 13 Jul 2011 15:49:32 UTC Organization: virginmedia.com Date: Wed, 13 Jul 2011 16:49:32 +0100 Xref: feeder.eternal-september.org comp.lang.verilog:3122 comp.arch.fpga:15895 comp.arch:17091 comp.arch.embedded:23332 comp.lang.vhdl:5141 Nicholas Collin Paul de Glouceſter wrote: > Dr. Kavvadias sent on July 11th, 2011: > |----------------------------------------------------------| > |"[..] | > | | > |You can [..] code your input [..] in a bit-accurate typed-| > |assembly language called NAC (N-Address Code). [..] | > |[..] | > | | > |[..]" | > |----------------------------------------------------------| > > > Ah, strongly typed assembly languages. One does not see many of > those. You do if you are assembling hardware :) From newsfish@newsfish Fri Feb 3 13:13:49 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!e35g2000yqc.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.verilog,comp.arch.fpga,comp.arch,comp.arch.embedded,comp.lang.vhdl Subject: Re: HercuLeS high-level synthesis tool Date: Wed, 13 Jul 2011 10:51:22 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <47b14a51-e117-4276-b89c-1057138b8571@e35g2000yqc.googlegroups.com> References: NNTP-Posting-Host: 94.70.55.49 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310579482 23856 127.0.0.1 (13 Jul 2011 17:51:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 17:51:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e35g2000yqc.googlegroups.com; posting-host=94.70.55.49; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.verilog:3123 comp.arch.fpga:15896 comp.arch:17096 comp.arch.embedded:23336 comp.lang.vhdl:5142 Hi > > Ah, strongly typed assembly languages. One does not see many of > > those. > > You do if you are assembling hardware :) Yes, bit-accurate, strongly-typed (generic) assembly languages is the way to go as an intermediate representation especially for hardware compilation. It provides some other benefits for the infrastructure in the long term. I decided to develop and extend an extremely lightweight typed- assembly language (called NAC), to keep all the infrastructure light and manageable by a single person. It certainly is manageable at the present time. Best regards, Nikolaos Kavvadias From newsfish@newsfish Fri Feb 3 13:13:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r11g2000prd.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 11:40:23 -0700 (PDT) Organization: http://groups.google.com Lines: 84 Message-ID: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 67.188.14.18 Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310582423 20886 127.0.0.1 (13 Jul 2011 18:40:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 13 Jul 2011 18:40:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r11g2000prd.googlegroups.com; posting-host=67.188.14.18; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5143 Hello, I'm trying to write a state machine in VHDL using code like the below, so that I can use for loops in the state machine. This code implements an asynchronous reset. However, in ISE the synthesizer gives me the error : ERROR:HDLCompiler:609=EF=BB=BF : Multiple signals in event expression is no= t synthesizable=EF=BB=BF. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DCODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D state_machine : process begin state_machine_loop : loop wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;=EF=BB=BF=EF=BB=BF next state_machine_loop; end if; =EF=BB=BF internal_loop : for i in 0 to SOME_VALUE loop do_internal_loop_stuff; wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;=EF=BB=BF next state_machine_loop; end if; end loop; end loop; end process; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DEND CODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D So I figured, okay, I'll make a state machine with a synchronous reset, as shown below. However, now I get this error: ERROR:HDLCompiler:926=EF=BB=BF : Multiple wait statements in one process ar= e not supported in this case.=EF=BB=BF =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DCODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D state_machine : process begin state_machine_loop : loop wait until rising_edge(CLOCK); if RST =3D '1' then do_reset_stuff;=EF=BB=BF next state_machine_loop; end if; =EF=BB=BF internal_loop : for i in 0 to SOME_VALUE loop do_internal_loop_stuff; wait until rising_edge(CLOCK); if RST =3D '1' then do_reset_stuff; next state_machine_loop; end if; end loop; end loop; end process =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DEND CODE=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D I'm reading in my copy of The Designers Guide to VHDL : Third Edition that these state machine coding styles ARE part of the IEEE 1076.6- VHDL-200X synthesis standard. I posted this on the Xilinx forum and was told the same thing that the tool told me : multiple wait statements are not supported for synthesis. Are there any other tools that will synthesize this or a similar coding style? I mean, in theory there is nothing un-synthesizable about this code. Thanks, Colin From newsfish@newsfish Fri Feb 3 13:13:50 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 21:44:35 -0700 Organization: A noiseless patient Spider Lines: 33 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Injection-Date: Thu, 14 Jul 2011 04:46:00 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="6444"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/QAAbuEW2bOADPSfBJlv/CZe0vdiqFLjY=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:N0nd9f99jGwsKvwGTaUhS7+LCsk= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5144 Do you really need a loop? Maybe something like this will do what you need: state_machine : PROCESS variable do_internal_loop : boolean; BEGIN WAIT until rising_edge(CLOCK); IF RST = '1' THEN do_reset_stuff; ELSE IF do_internal_loop THEN do_internal_loop_stuff; IF some_end_condition THEN do_internal_loop := false; END IF; ELSE do_non_internal_loop_stuff; IF some_start_condition THEN do_internal_loop := true; END IF; END IF; END IF; END PROCESS; The process will execute once per clock cycle. Various conditional statements decide what to do on each cycle. A process with one WAIT statement as I have shown is definitely synthesizable. Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!m6g2000prh.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Wed, 13 Jul 2011 23:19:51 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.234.25.187 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310624391 23296 127.0.0.1 (14 Jul 2011 06:19:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 14 Jul 2011 06:19:51 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m6g2000prh.googlegroups.com; posting-host=98.234.25.187; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5145 On Jul 13, 9:44=A0pm, "logic_guy" wrote: > Do you really need a loop? =A0Maybe something like this will do what you > need: > > state_machine : PROCESS > variable do_internal_loop : boolean; > BEGIN > =A0 =A0 WAIT until rising_edge(CLOCK); > =A0 =A0 IF RST =3D '1' THEN > =A0 =A0 =A0 do_reset_stuff; > =A0 =A0 ELSE > =A0 =A0 =A0 IF do_internal_loop THEN > =A0 =A0 =A0 =A0 do_internal_loop_stuff; > =A0 =A0 =A0 =A0 IF some_end_condition THEN > =A0 =A0 =A0 =A0 =A0 do_internal_loop :=3D false; > =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 ELSE > =A0 =A0 =A0 =A0 do_non_internal_loop_stuff; > =A0 =A0 =A0 =A0 IF some_start_condition THEN > =A0 =A0 =A0 =A0 =A0 do_internal_loop :=3D true; > =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 END IF; > =A0 =A0 END IF; > END PROCESS; > > The process will execute once per clock cycle. =A0Various conditional > statements decide what to do on each cycle. > > A process with one WAIT statement as I have shown is definitely > synthesizable. > > Charles Bailey Unfortunately the example I provided is pretty boiled down. In reality I need three nested for loops, which starts to get hairy. From newsfish@newsfish Fri Feb 3 13:13:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder2.news.elisa.fi!newsfeed3.funet.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Message-ID: From: Andreas Ehliar Date: 14 Jul 11 09:05:17 CEST References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 21 Xref: feeder.eternal-september.org comp.lang.vhdl:5146 On 2011-07-13, Colin Beighley wrote: > I'm reading in my copy of The Designers Guide to VHDL : Third Edition > that these state machine coding styles ARE part of the IEEE 1076.6- > VHDL-200X synthesis standard. I posted this on the Xilinx forum and > was told the same thing that the tool told me : multiple wait > statements are not supported for synthesis. Are there any other tools > that will synthesize this or a similar coding style? I mean, in theory > there is nothing un-synthesizable about this code. I've been able to synthesize similar state machines in Precision. However, I have not yet jumped ship to this style of FSM design yet. The reason being that it is not possible to do Mealy style state machines in it (AFAIK). Another is that it is quite tedious to handle the reset signal. This posting also implies that Synplify can handle such state machines but I haven't tested this myself: http://www.parallelpoints.com/node/69 regards /Andreas From newsfish@newsfish Fri Feb 3 13:13:51 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Aliaksei Newsgroups: comp.lang.vhdl Subject: Re: free waveform drawing tool Date: Thu, 14 Jul 2011 21:23:26 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <654b992b-7c1f-414d-ac34-91b4e82813ae@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 68.2.84.237 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310703897 14138 127.0.0.1 (15 Jul 2011 04:24:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 04:24:57 +0000 (UTC) In-Reply-To: <874oltklyw.fsf@harnisch.dyndns.org> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.2.84.237; posting-account=DO8HUwoAAABarIvwczwGgNHPyBoOVZ-E User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5147 http://wavedrom.googlecode.com WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics. The project is in progress. Any feedback appreciated. From newsfish@newsfish Fri Feb 3 13:13:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "logic_guy" Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 07:44:48 -0700 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> Injection-Date: Fri, 15 Jul 2011 14:44:47 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="mQvlsRnmnwbzUNzuguuErw"; logging-data="10224"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/B6caon3aEC/GmrByaYnh7HRvvDiGEd20=" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6109 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:5vhnnvVfHRTpOShKp+XOjfne0BI= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5148 "Colin Beighley" wrote in message news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... On Jul 13, 9:44 pm, "logic_guy" wrote: > Do you really need a loop? Maybe something like this will do what you > need: > > state_machine : PROCESS > variable do_internal_loop : boolean; > BEGIN > WAIT until rising_edge(CLOCK); > IF RST = '1' THEN > do_reset_stuff; > ELSE > IF do_internal_loop THEN > do_internal_loop_stuff; > IF some_end_condition THEN > do_internal_loop := false; > END IF; > ELSE > do_non_internal_loop_stuff; > IF some_start_condition THEN > do_internal_loop := true; > END IF; > END IF; > END IF; > END PROCESS; > > The process will execute once per clock cycle. Various conditional > statements decide what to do on each cycle. > > A process with one WAIT statement as I have shown is definitely > synthesizable. > > Charles Bailey > Unfortunately the example I provided is pretty boiled down. In reality > I need three nested for loops, which starts to get hairy. LOOPs in a clocked process are normally used when you need to operate on multiple elements of an array in a single clock cycle. If the operations span multiple clock cycles then you need to define your own counter variable to keep track of what happens on each clock cycle. By expanding on the example I've show, you should be able to do anything you want, and do it with just one WAIT statement. Charles Bailey From newsfish@newsfish Fri Feb 3 13:13:52 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t8g2000prm.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 10:23:19 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310751056 3343 127.0.0.1 (15 Jul 2011 17:30:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 17:30:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000prm.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5149 On Jul 15, 7:44=A0am, "logic_guy" wrote: > "Colin Beighley" wrote in message > > news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... > On Jul 13, 9:44 pm, "logic_guy" wrote: > > > > > > > > > > > Do you really need a loop? Maybe something like this will do what you > > need: > > > state_machine : PROCESS > > variable do_internal_loop : boolean; > > BEGIN > > WAIT until rising_edge(CLOCK); > > IF RST =3D '1' THEN > > do_reset_stuff; > > ELSE > > IF do_internal_loop THEN > > do_internal_loop_stuff; > > IF some_end_condition THEN > > do_internal_loop :=3D false; > > END IF; > > ELSE > > do_non_internal_loop_stuff; > > IF some_start_condition THEN > > do_internal_loop :=3D true; > > END IF; > > END IF; > > END IF; > > END PROCESS; > > > The process will execute once per clock cycle. Various conditional > > statements decide what to do on each cycle. > > > A process with one WAIT statement as I have shown is definitely > > synthesizable. > > > Charles Bailey > > Unfortunately the example I provided is pretty boiled down. In reality > > I need three nested for loops, which starts to get hairy. > > LOOPs in a clocked process are normally used when you need to operate on > multiple elements of an array in a single clock cycle. =A0If the > operations span multiple clock cycles then you need to define your own > counter variable to keep track of what happens on each clock cycle. =A0By > expanding on the example I've show, you should be able to do anything > you want, and do it with just one WAIT statement. > > Charles Bailey Yes, you can use one WAIT statement and synthesize your state machine thus, but you don't gain anything over the : if rst elsif rising_edge(clk) end if : model. However, the benefit of using the WAIT UNTIL RISING_EDGE(CLK) at various places within your process is that you can describe a state machine in a much more abstract, easily understood manner. It's quite a mystery to me that HDL's are still so primitive in some respects - there simply MUST be a better way to do, for instance, nested for loops than keeping track of the variables with the two-process case statement. I've wondered if FPGA bitstreams were not proprietary would there be open-source toolchains that would spring forth and better HDL's as a result? From newsfish@newsfish Fri Feb 3 13:13:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 11:28:50 -0700 (PDT) Organization: http://groups.google.com Lines: 78 Message-ID: <92d928a8-ab10-4860-a9d4-84327d5b6216@a2g2000prf.googlegroups.com> References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310756188 23573 127.0.0.1 (15 Jul 2011 18:56:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 18:56:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5150 On Jul 15, 10:23=A0am, Colin Beighley wrote: > On Jul 15, 7:44=A0am, "logic_guy" wrote: > > > > > > > > > > > "Colin Beighley" wrote in message > > >news:a9201a47-730d-443f-9960-0e2fee37b9e1@m6g2000prh.googlegroups.com... > > On Jul 13, 9:44 pm, "logic_guy" wrote: > > > > Do you really need a loop? Maybe something like this will do what you > > > need: > > > > state_machine : PROCESS > > > variable do_internal_loop : boolean; > > > BEGIN > > > WAIT until rising_edge(CLOCK); > > > IF RST =3D '1' THEN > > > do_reset_stuff; > > > ELSE > > > IF do_internal_loop THEN > > > do_internal_loop_stuff; > > > IF some_end_condition THEN > > > do_internal_loop :=3D false; > > > END IF; > > > ELSE > > > do_non_internal_loop_stuff; > > > IF some_start_condition THEN > > > do_internal_loop :=3D true; > > > END IF; > > > END IF; > > > END IF; > > > END PROCESS; > > > > The process will execute once per clock cycle. Various conditional > > > statements decide what to do on each cycle. > > > > A process with one WAIT statement as I have shown is definitely > > > synthesizable. > > > > Charles Bailey > > > Unfortunately the example I provided is pretty boiled down. In realit= y > > > I need three nested for loops, which starts to get hairy. > > > LOOPs in a clocked process are normally used when you need to operate o= n > > multiple elements of an array in a single clock cycle. =A0If the > > operations span multiple clock cycles then you need to define your own > > counter variable to keep track of what happens on each clock cycle. =A0= By > > expanding on the example I've show, you should be able to do anything > > you want, and do it with just one WAIT statement. > > > Charles Bailey > > Yes, you can use one WAIT statement and synthesize your state machine > thus, but you don't gain anything over the : if rst elsif > rising_edge(clk) end if : model. However, the benefit of using the > WAIT UNTIL RISING_EDGE(CLK) at various places within your process is > that you can describe a state machine in a much more abstract, easily > understood manner. It's quite a mystery to me that HDL's are still so > primitive in some respects - there simply MUST be a better way to do, > for instance, nested for loops than keeping track of the variables > with the two-process case statement. > > I've wondered if FPGA bitstreams were not proprietary would there be > open-source toolchains that would spring forth and better HDL's as a > result? P.S. : gcc, gdb, and a number of microcontrollers spring to mind as an example From newsfish@newsfish Fri Feb 3 13:13:53 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p14g2000yqj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Synthesis of multiple wait statements per VHDL-200X Date: Fri, 15 Jul 2011 14:25:09 -0700 (PDT) Organization: http://groups.google.com Lines: 81 Message-ID: <569a6d4c-831c-4d70-bc63-00f686e80095@p14g2000yqj.googlegroups.com> References: <6a5d43e5-77a1-49b6-b01e-75cb74bcf75a@r11g2000prd.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1310765209 17781 127.0.0.1 (15 Jul 2011 21:26:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 15 Jul 2011 21:26:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p14g2000yqj.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5151 On Jul 15, 1:23=A0pm, Colin Beighley wrote: > > Yes, you can use one WAIT statement and synthesize your state machine > thus, but you don't gain anything over the : if rst elsif > rising_edge(clk) end if : model. It's not clear to me just what you think you gain with your model either. There's nothing inherently wrong about being different, but different is not neccessarily better (assuming that's what you mean by 'don't gain anything...') > However, the benefit of using the > WAIT UNTIL RISING_EDGE(CLK) at various places within your process is > that you can describe a state machine in a much more abstract, easily > understood manner. I disagree, see (1) at the end of this post for how I manipulated your original process into a form that is synthesizable and at least as clear as your process. Repeating things over and over again is error prone which is far worse than what you think may be 'easily understood'. For example, if you start having several conditions tacked on, and then you change those over time as you develop the code both of the following lines of code (separated by large amounts of text) are 'easily understood', but are they both correct or did the designer forget a condition? wait until rising_edge(clock) and (this =3D '1') and (that /=3D 5) and (moon =3D rising); wait until rising_edge(clock) and (this =3D '1') and (moon =3D rising); > It's quite a mystery to me that HDL's are still so > primitive in some respects - there simply MUST be a better way to do, > for instance, nested for loops than keeping track of the variables Keeping track of the variables boils down to the following. Preferring one over the other simply says you like the looks of a 'for' statement rather than an 'if'...but that preference is up to anyone to have and is simply cosmetic for i in 0 to SOME_VALUE loop (your method) if i <=3D SOME_VALUE then (currently synthesizable method) The currently synthesizable method with the 'if' statement has some baggage: - Loop variable must be declared - Loop variable increment is explicit What you're proposing has some baggage: - Global conditions (like checking that Reset =3D '1' and what to do under that condition) must be physically repeated in the code...that is best accomplished via copy/paste which is not good practice in hardly any language - More local condition checking gets problematic. By this I mean conditions that are not quite as global as 'Reset =3D 1' but are not specific to a single code branch. Now you're copying code in certain areas. Again, copy/paste will be your friend but copy/paste is not good practice. > with the two-process case statement. > Ummmm...nobody should be using two-process. Use a single clocked process and a concurrent statement to pick up the unclocked outputs. Kevin Jennings ---- (1) Synthesizable version of the process from your original post. state_machine : process variable i: integer range 0 to SOME_VALUE + 1; begin wait until (rising_edge(CLOCK) or RST =3D '1'); if RST =3D '1' then do_reset_stuff;?? next state_machine_loop; --KJ: What do you mean here?? i :=3D 0; else if i <=3D SOME_VALUE then do_internal_loop_stuff; i :=3D i + 1; end if; end if; end process; From newsfish@newsfish Fri Feb 3 13:13:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!t9g2000vbs.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: 1to8 Demux code, can you look plz Date: Sat, 16 Jul 2011 18:02:37 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> NNTP-Posting-Host: 188.51.4.222 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1310864557 18177 127.0.0.1 (17 Jul 2011 01:02:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 17 Jul 2011 01:02:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t9g2000vbs.googlegroups.com; posting-host=188.51.4.222; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5152 Hi all, I am tried to write VHDL code for 1 to 8 Demux and that's what i finish with it LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY Dmux1to8 IS PORT ( X : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(0 TO 2); En : IN STD_LOGIC; W : OUT STD_LOGIC_VECTOR(0 TO 7)); END Dmux1to2; ARCHITECTURE Structure OF Dmux1to8 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); BEGIN G1: FOR i IN 0 TO 1 GENERATE Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); G2: FOR i IN 2 TO 5 GENERATE Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); END GENERATE ; END GENERATE ; Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO 7) ); END Structure; can any one told me if is it right or not? if there are any mistakes can you help me to correct it ? From newsfish@newsfish Fri Feb 3 13:13:54 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!proxad.net!feeder1-2.proxad.net!cleanfeed2-a.proxad.net!nnrp10-2.free.fr!not-for-mail Date: Sun, 17 Jul 2011 09:48:28 +0200 From: Nicolas Matringe User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; fr; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> In-Reply-To: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Lines: 55 Message-ID: <4e2293c5$0$20183$426a74cc@news.free.fr> Organization: Guest of ProXad - France NNTP-Posting-Date: 17 Jul 2011 09:48:21 MEST NNTP-Posting-Host: 82.246.229.10 X-Trace: 1310888901 news-1.free.fr 20183 82.246.229.10:51482 X-Complaints-To: abuse@proxad.net Xref: feeder.eternal-september.org comp.lang.vhdl:5153 Le 17/07/2011 03:02, majmoat_ensan a crit : > Hi all, Hi > I am tried to write VHDL code for 1 to 8 Demux and that's what i > finish with it > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > use ieee.std_logic_unsigned.all; Do NOT use non-standard libraries like std_logic_arith, std_logic_signed or std_logic_unsigned. Use numeric_std instead. > ENTITY Dmux1to8 IS > PORT ( X : IN STD_LOGIC; > S : IN STD_LOGIC_VECTOR(0 TO 2); > En : IN STD_LOGIC; > W : OUT STD_LOGIC_VECTOR(0 TO 7)); > END Dmux1to2; Although it doesn't change anything in terms of behaviour, it is common practice to declare vectors with a descending range (e.g. 7 downto 0) because the higher index bit is then the leftmost bit (which helps a lot when you use arithmetic vectors) > ARCHITECTURE Structure OF Dmux1to8 IS > SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > BEGIN > G1: FOR i IN 0 TO 1 GENERATE > Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); > G2: FOR i IN 2 TO 5 GENERATE > Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); > END GENERATE ; > END GENERATE ; > Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO > 7) ); There are spaces in your (intended) component name. You can't do this. Besides, it is also common practice to use named association for port maps because it is much less error prone (but is adds a lot of typing unless you use an Editor with MACroS) > END Structure; It is absolutely impossible to say if this is good or not because you don't give the code for components demux1to2 and demux1to8. I find it strange that you map the same demux1to2 component with 3 ports in your first generate loop and only 2 ports in the second one. Nicolas From newsfish@newsfish Fri Feb 3 13:13:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 Jul 2011 11:23:59 -0500 Date: Mon, 18 Jul 2011 09:24:02 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> In-Reply-To: <4e2293c5$0$20183$426a74cc@news.free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Message-ID: Lines: 62 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-BJ0JHiA+vv9NzkfhHJmWuS4yiG2mQui95AHBf5719Nzz7RURR5bkVyOu/RRxN6qum2cc/HiwzkfC24i!GRKR7Qw/K2qCPo99G0kuC0QpmCe632F/JDeICG8DRBpJbm7+ZC6kzdGOg2wZ69ygErOYOv93Bgrl X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3185 Xref: feeder.eternal-september.org comp.lang.vhdl:5154 On 7/17/2011 12:48 AM, Nicolas Matringe wrote: > Le 17/07/2011 03:02, majmoat_ensan a crit : >> Hi all, > > Hi > >> I am tried to write VHDL code for 1 to 8 Demux and that's what i >> finish with it >> >> LIBRARY IEEE; >> USE IEEE.STD_LOGIC_1164.ALL; >> use ieee.std_logic_unsigned.all; > > Do NOT use non-standard libraries like std_logic_arith, std_logic_signed > or std_logic_unsigned. Use numeric_std instead. > > >> ENTITY Dmux1to8 IS >> PORT ( X : IN STD_LOGIC; >> S : IN STD_LOGIC_VECTOR(0 TO 2); >> En : IN STD_LOGIC; >> W : OUT STD_LOGIC_VECTOR(0 TO 7)); >> END Dmux1to2; > > Although it doesn't change anything in terms of behaviour, it is common > practice to declare vectors with a descending range (e.g. 7 downto 0) > because the higher index bit is then the leftmost bit (which helps a lot > when you use arithmetic vectors) > > >> ARCHITECTURE Structure OF Dmux1to8 IS >> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); >> >> BEGIN >> G1: FOR i IN 0 TO 1 GENERATE >> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); >> G2: FOR i IN 2 TO 5 GENERATE >> Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); >> END GENERATE ; >> END GENERATE ; >> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO >> 7) ); > > There are spaces in your (intended) component name. You can't do this. > Besides, it is also common practice to use named association for port > maps because it is much less error prone (but is adds a lot of typing > unless you use an Editor with MACroS) > >> END Structure; > > It is absolutely impossible to say if this is good or not because you > don't give the code for components demux1to2 and demux1to8. I find it > strange that you map the same demux1to2 component with 3 ports in your > first generate loop and only 2 ports in the second one. > > Nicolas Also, you reused 'i' as your loop variable in the inner loop. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:55 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Mon, 18 Jul 2011 18:09:16 -0500 Date: Tue, 19 Jul 2011 00:09:16 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: empty array litteral References: <1903e24a-3097-468a-90e9-7b4a13673514@u26g2000vby.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <_Z-dnUwc2eSBILnTnZ2dnUVZ8lGdnZ2d@brightview.co.uk> Lines: 44 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-h1hdJPfTpbmctc6bqLsZ4B6flScsIoCdOSDhMiO8pPPTBAHcsGBBpJzqwpHn+JKDOE9zIsYc7omaxAH!twJv8W3IfxlYnqEaFKFaNdPFHA9MRuNExWyYw1Df23so+Gh30n3+udhPcud51pxkH7YFyHI6ebfj!4hJapIy8HHOKrRpGa7BfSt/t X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2181 Xref: feeder.eternal-september.org comp.lang.vhdl:5155 On 13/07/11 14:25, Tricky wrote: > On Jul 13, 1:54 pm, Julien REINAULD wrote: >> Hi all! >> >> According to std.standard: >> >> TYPE string IS ARRAY ( positive RANGE <> OF character); >> >> "hello" is a valid string litteral >> "" is a valid string litteral too, it is the empty string. >> >> Let >> >> TYPE foo IS ARRAY ( positive RANGE <> OF integer); >> >> (0, 1, 1, 2, 3, 5) is a valid foo litteral >> >> What is the litteral for an empty foo? >> >> Thx >> >> Julien > > That is an interesting question. > > You can make a null constant like this: > > constant NULL_FOO : foo(1 downto 2) := (others => 0); > > then use the constant in place of a literal. > I haven't tried it, or looked it up in the LRM, but I imagine you may be able to use (1 downto 2 => 0) though of course a named constant is nicer. regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:13:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Tue, 19 Jul 2011 12:36:34 +0200 Lines: 20 Message-ID: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net DHU4JiITXRO22MS+yoK/iwP4+DAo0ByVHUJy30nGrsaBFof2w/ Cancel-Lock: sha1:anDHcNMwYPKEjvI/S4VCjylyLOg= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5156 Mr. Google did not find this article/book (I don't know what it is). Mr. Amazon did not find this article/book (same as before...). It is mentioned in the vmkr documentation by Bell-Northern Research VHDL Group (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps) but no other references found. Does anyone know where I can find this article/book? As a parting note, does anyone have any suggestion/recommendation on the usage of vmkr? Al -- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? From newsfish@newsfish Fri Feb 3 13:13:56 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: "nemgreen@gmail.com" Newsgroups: comp.lang.vhdl Subject: Re: re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Tue, 19 Jul 2011 07:53:24 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <7183d5d4-ade1-47ff-8b3a-810b18764824@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 192.94.31.2 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311087610 3191 127.0.0.1 (19 Jul 2011 15:00:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 19 Jul 2011 15:00:10 +0000 (UTC) In-Reply-To: <98l51iFmp5U1@mid.individual.net> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=192.94.31.2; posting-account=A7jt9goAAAAU2UzdI3fZ3NM4v1Vq2uHr User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5157 ModelSim and Questa have the vmake command to build a makefile from a compi= led library: vmake The vmake utility allows you to use a UNIX or Windows MAKE program to maint= ain individual libraries. You run vmake on a compiled design library. This = utility operates on multiple source files per design unit; it supports Veri= log include files as well as Verilog and VHDL PSL vunit files. From newsfish@newsfish Fri Feb 3 13:13:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 19 Jul 2011 18:31:03 -0500 Date: Wed, 20 Jul 2011 00:31:03 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> In-Reply-To: <98l51iFmp5U1@mid.individual.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 26 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rjIxy30fSGybHj1faUQk4BiLReuDpvTL4ogzYqhFZkFpjZjgbNE+4CIiAhAWkQOOiqNb8QKvuJ8VgIJ!ivSF1ctK1vKZ/oPRkWb6f+3aRmJ1s5FqjdRzEgB4sBDlTSAzXCj5uH+vtBBKWKBFk8Fk9qXE36Qo!JIZop411pM12G8nXbVNoxMoa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1936 Xref: feeder.eternal-september.org comp.lang.vhdl:5158 On 19/07/11 11:36, Alessandro Basili wrote: > Mr. Google did not find this article/book (I don't know what it is). > Mr. Amazon did not find this article/book (same as before...). > > It is mentioned in the vmkr documentation by Bell-Northern Research VHDL > Group > (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhdl/tools/vmkr/doc/vmkr.doc.ps) > but no other references found. > > Does anyone know where I can find this article/book? > > As a parting note, does anyone have any suggestion/recommendation on the > usage of vmkr? > > Al > Try posting your message on the Verification Guild http://verificationguild.com (I think, from memory). Janick started the website, and often posts there, regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:13:57 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h12g2000vbx.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 07:48:59 -0700 (PDT) Organization: http://groups.google.com Lines: 107 Message-ID: References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 90.148.43.73 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311173339 21611 127.0.0.1 (20 Jul 2011 14:48:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 14:48:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h12g2000vbx.googlegroups.com; posting-host=90.148.43.73; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5159 On Jul 18, 7:24=A0pm, Rob Gaddi wrote: > On 7/17/2011 12:48 AM, Nicolas Matringe wrote: > > > > > > > > > > > Le 17/07/2011 03:02, majmoat_ensan a =E9crit : > >> Hi all, > > > Hi > > >> I am tried to write VHDL code for 1 to 8 Demux and that's what i > >> finish with it > > >> LIBRARY IEEE; > >> USE IEEE.STD_LOGIC_1164.ALL; > >> use ieee.std_logic_unsigned.all; > > > Do NOT use non-standard libraries like std_logic_arith, std_logic_signe= d > > or std_logic_unsigned. Use numeric_std instead. > > >> ENTITY Dmux1to8 IS > >> PORT ( X : IN STD_LOGIC; > >> S : IN STD_LOGIC_VECTOR(0 TO 2); > >> En : IN STD_LOGIC; > >> W : OUT STD_LOGIC_VECTOR(0 TO 7)); > >> END Dmux1to2; > > > Although it doesn't change anything in terms of behaviour, it is common > > practice to declare vectors with a descending range (e.g. 7 downto 0) > > because the higher index bit is then the leftmost bit (which helps a lo= t > > when you use arithmetic vectors) > > >> ARCHITECTURE Structure OF Dmux1to8 IS > >> SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > >> BEGIN > >> G1: FOR i IN 0 TO 1 GENERATE > >> Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X); > >> G2: FOR i IN 2 TO 5 GENERATE > >> Dec_left: Demux1to2 PORT MAP ( m(i), S(1)); > >> END GENERATE ; > >> END GENERATE ; > >> Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO > >> 7) ); > > > There are spaces in your (intended) component name. You can't do this. > > Besides, it is also common practice to use named association for port > > maps because it is much less error prone (but is adds a lot of typing > > unless you use an Editor with MACroS) > > >> END Structure; > > > It is absolutely impossible to say if this is good or not because you > > don't give the code for components demux1to2 and demux1to8. I find it > > strange that you map the same demux1to2 component with 3 ports in your > > first generate loop and only 2 ports in the second one. > > > Nicolas > > Also, you reused 'i' as your loop variable in the inner loop. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order ummm if i tried to wrote it in this way is it right or not? LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY Dmux1to8 IS PORT ( X : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(0 TO 2); W : OUT STD_LOGIC_VECTOR(0 TO 7)); END Dmux1to8; ARCHITECTURE Structure OF Dmux1to8 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); BEGIN Dmux1: Dmux1to8 PORT MAP ( X, s(0), m(0), m(1) ) ; Dmux2: Dmux1to8 PORT MAP ( m(0), s(1), m(2), m(3) ) ; Dmux3: Dmux1to8 PORT MAP ( m(1), s(1), m(4), m(5) ) ; Dmux4: Dmux1to8 PORT MAP ( m(2), s(2), w(0), w(1) ) ; Dmux5: Dmux1to8 PORT MAP ( m(3), s(2), w(2), w(3) ) ; Dmux6: Dmux1to8 PORT MAP ( m(4), s(2), w(4), w(5) ) ; Dmux7: Dmux1to8 PORT MAP ( m(5), s(2), w(6), w(7) ) ; END Structure ; From newsfish@newsfish Fri Feb 3 13:13:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 20 Jul 2011 11:35:50 -0500 Date: Wed, 20 Jul 2011 09:35:53 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.18) Gecko/20110616 Lightning/1.0b2 Thunderbird/3.1.11 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 51 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-88gykf82ACnNeERu/5w/BVBY375eNyEE3j7N4l5PQl7VDXiGGSJJoS/3T/sE3qjpfU97ram/gLjdJ4W!10rG4LZnec/hJm39x7bAeoMeDlTr0V/S4lrZ9vfhRJduM3u6ut+nTGIQpsTJna0sjrEDeSy1tNEk X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2822 Xref: feeder.eternal-september.org comp.lang.vhdl:5160 On 7/20/2011 7:48 AM, majmoat_ensan wrote: > [snip] > > ummm if i tried to wrote it in this way is it right or not? > > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > use ieee.std_logic_unsigned.all; > > > ENTITY Dmux1to8 IS > PORT ( X : IN STD_LOGIC; > S : IN STD_LOGIC_VECTOR(0 TO 2); > W : OUT STD_LOGIC_VECTOR(0 TO 7)); > END Dmux1to8; > > ARCHITECTURE Structure OF Dmux1to8 IS > SIGNAL m : STD_LOGIC_VECTOR(0 TO 5); > > BEGIN > Dmux1: Dmux1to8 PORT MAP > ( X, s(0), m(0), m(1) ) ; > Dmux2: Dmux1to8 PORT MAP > ( m(0), s(1), m(2), m(3) ) ; > Dmux3: Dmux1to8 PORT MAP > ( m(1), s(1), m(4), m(5) ) ; > Dmux4: Dmux1to8 PORT MAP > ( m(2), s(2), w(0), w(1) ) ; > Dmux5: Dmux1to8 PORT MAP > ( m(3), s(2), w(2), w(3) ) ; > Dmux6: Dmux1to8 PORT MAP > ( m(4), s(2), w(4), w(5) ) ; > Dmux7: Dmux1to8 PORT MAP > ( m(5), s(2), w(6), w(7) ) ; > END Structure ; No, now you're trying to recursively instantiate the element inside of itself. What on earth are you actually trying to accomplish, and why are you trying to build something as simple as a demux with anything inside of it? Just write the stupid thing in RTL. Honestly even that borders on the insane, the RTL demux should just be written directly into whatever higher level block it was going to go into. http://lmgtfy.com/?q=demultiplexer+vhdl -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:13:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!m3g2000pre.googlegroups.com!not-for-mail From: Daniel Leu Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 20 Jul 2011 10:14:02 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <98l51iFmp5U1@mid.individual.net> NNTP-Posting-Host: 76.254.35.229 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311182043 13050 127.0.0.1 (20 Jul 2011 17:14:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 17:14:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m3g2000pre.googlegroups.com; posting-host=76.254.35.229; posting-account=vg5e4goAAAAGOhAcfiR_nSjiLBi7pokl User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10_6_7) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5161 On Jul 19, 3:36=A0am, Alessandro Basili wrote: > Mr. Google did not find this article/book (I don't know what it is). > Mr. Amazon did not find this article/book (same as before...). > > It is mentioned in the vmkr documentation by Bell-Northern Research VHDL > Group > (http://www.pldworld.com/_hdl/1/tech-www.informatik.uni-hamburg.de/vhd...= ) > but no other references found. > > Does anyone know where I can find this article/book? > > As a parting note, does anyone have any suggestion/recommendation on the > usage of vmkr? Google provides some links if you just search for "makefiles bergeron": - www.vhdl.org/misc/ModelingGuidelines.paper.ps - pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf Regards, Daniel From newsfish@newsfish Fri Feb 3 13:13:58 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!m6g2000prh.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Conditional declarations Date: Wed, 20 Jul 2011 11:14:55 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311185696 17473 127.0.0.1 (20 Jul 2011 18:14:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 18:14:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m6g2000prh.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5162 Hello, I keep running across situations where a conditional variable or signal declaration would be very useful in simulation (for instance, declaring full range integers or reals), but I don't want any of these to attempt to be synthesized. Is there an eloquent way of doing this? I don't believe you can use the generate statement for declarations. I have heard of people using the C preprocessor for this, but this seems like a hack IMO. Colin From newsfish@newsfish Fri Feb 3 13:13:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!x19g2000prc.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Wed, 20 Jul 2011 11:52:09 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311187929 7249 127.0.0.1 (20 Jul 2011 18:52:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 18:52:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x19g2000prc.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5163 On Jul 20, 11:14=A0am, Colin Beighley wrote: > Hello, > > I keep running across situations where a conditional variable or > signal declaration would be very useful in simulation (for instance, > declaring full range integers or reals), but I don't want any of these > to attempt to be synthesized. Is there an eloquent way of doing this? > I don't believe you can use the generate statement for declarations. I > have heard of people using the C preprocessor for this, but this seems > like a hack IMO. > > Colin Okay so I had a brain fart and forgot about --synthesis translate_off. I've also looked into the archives and seen that it doesn't seem to be supported for synthesis, though, except for within conditional generate statements. From newsfish@newsfish Fri Feb 3 13:13:59 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Wed, 20 Jul 2011 14:47:13 -0500 Date: Wed, 20 Jul 2011 20:47:12 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc15 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 34 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-SioX3dfj62tkLiundsiGqLo2Xx2hOXtNe5I9nNqOaasIkfUhcfGUWQAuBHstn8lHxXPwaV5ja6mDdJy!pnybO07QLgtvt5PJzZN1NWK+leLdYn+5wEtXp91BYE3iIiDBs8of7e1Dh7jalQeI6HcmAqZUyzaG!LQfHe7U4VMCCkjaknzwWhapf X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2494 Xref: feeder.eternal-september.org comp.lang.vhdl:5164 On 20/07/11 19:52, Colin Beighley wrote: > On Jul 20, 11:14 am, Colin Beighley wrote: >> Hello, >> >> I keep running across situations where a conditional variable or >> signal declaration would be very useful in simulation (for instance, >> declaring full range integers or reals), but I don't want any of these >> to attempt to be synthesized. Is there an eloquent way of doing this? >> I don't believe you can use the generate statement for declarations. I >> have heard of people using the C preprocessor for this, but this seems >> like a hack IMO. >> >> Colin > > Okay so I had a brain fart and forgot about --synthesis translate_off. > I've also looked into the archives and seen that it doesn't seem to be > supported for synthesis, though, except for within conditional > generate statements. Synthesis meta comments should work fine - just use the right ones :-) I wrote a little technote on the Doulos Website about such issues which might be of interest http://www.doulos.com/knowhow/fpga/technotes/index.php#Technote2 regards Alan P.S. There *is* an option to opt out of being contacted during registration for the download, honestly! -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:14:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h17g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 13:59:43 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311195659 20504 127.0.0.1 (20 Jul 2011 21:00:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 21:00:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h17g2000yqn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5165 On Jul 20, 12:35=A0pm, Rob Gaddi wrote: > > What on earth are you actually trying to accomplish Homework perhaps. From newsfish@newsfish Fri Feb 3 13:14:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!x10g2000vbl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Wed, 20 Jul 2011 14:03:41 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311196186 25698 127.0.0.1 (20 Jul 2011 21:09:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 21:09:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: x10g2000vbl.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5166 On Jul 20, 2:14=A0pm, Colin Beighley wrote: > Hello, > > I keep running across situations where a conditional variable or > signal declaration would be very useful in simulation (for instance, > declaring full range integers or reals), but I don't want any of these > to attempt to be synthesized. Is there an eloquent way of doing this? > I don't believe you can use the generate statement for declarations. I > have heard of people using the C preprocessor for this, but this seems > like a hack IMO. > You can declare signals within a generate statement. Then set the generate condition appropriately to not generate for synthesis. if xxx generate signal xyz_real: real; begin xyz <=3D to_real(xyz_fp); end generate xxx; Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:00 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d1g2000yqm.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 15:09:04 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: NNTP-Posting-Host: 86.45.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311199744 29046 127.0.0.1 (20 Jul 2011 22:09:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 20 Jul 2011 22:09:04 +0000 (UTC) Cc: fearghal.morgan@nuigalway.ie Complaints-To: groups-abuse@google.com Injection-Info: d1g2000yqm.googlegroups.com; posting-host=86.45.244.35; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5167 Hi, I=92d be grateful if anyone could advise on whether an application is available to do the following for VHDL models. Fearghal 1. Make a replica copy of a selected multi-file and hierarchical VHDL design 2. Modify each VHDL file in the copied hierarchical VHDL model (possibly using the make file sequence), in order to bring all (or selected) signals to the top level VHDL entity. 3. Steps: a. modify each VHDL files in turn to bring every (or selected) internal signal as an output signals in VHDL entity b. Modify the associated component declarations within package files to reflect the modified entity ports c. Rebuild the VHDL hierarchy adding the new output ports to all entities in the hierarchy d. Modify all port map assignments to mirror the extended entity ports. My application requires interpreting any existing VHDL model, selecting signals from within the VHDL model to bring to the top level entity in order to connect to a series of display devices. I do not wish to modify the underlying VHDL code. From newsfish@newsfish Fri Feb 3 13:14:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j9g2000prj.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 17:24:14 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: References: NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311207936 14323 127.0.0.1 (21 Jul 2011 00:25:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 00:25:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prj.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5168 On Jul 20, 3:09=A0pm, fearg wrote: > Hi, I=92d be grateful if anyone could advise on whether an application > is available to do the following for VHDL models. > Fearghal > > 1. =A0 =A0 =A0Make a replica copy of a selected multi-file and hierarchic= al VHDL > design > 2. =A0 =A0 =A0Modify each VHDL file in the copied hierarchical VHDL model > (possibly using the make file sequence), in order to bring all (or > selected) signals to the top level VHDL entity. > 3. =A0 =A0 =A0Steps: > a. =A0 =A0 =A0modify each VHDL files in turn to bring every (or selected) > internal signal as an output signals in VHDL entity > b. =A0 =A0 =A0Modify the associated component declarations within package= files > to reflect the modified entity ports > c. =A0 =A0 =A0Rebuild the VHDL hierarchy adding the new output ports to a= ll > entities in the hierarchy > d. =A0 =A0 =A0Modify all port map assignments to mirror the extended enti= ty > ports. > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. It seems VHDL-2008 has some support similar to this. Doulos says that it is not synthesizable, however. http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease= /#hierarchicalnames Look at the section Hierarchical Names. From newsfish@newsfish Fri Feb 3 13:14:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!ft10g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: 1to8 Demux code, can you look plz Date: Wed, 20 Jul 2011 18:18:54 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <1e70f957-6212-4924-add1-13995c0d1e66@ft10g2000vbb.googlegroups.com> References: <30a6f8ca-a5c3-42b3-85d4-0c6e2182fa3d@t9g2000vbs.googlegroups.com> <4e2293c5$0$20183$426a74cc@news.free.fr> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311211501 17305 127.0.0.1 (21 Jul 2011 01:25:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 01:25:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: ft10g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5169 On Jul 20, 10:48=A0am, majmoat_ensan wrote: > > ummm if i tried to wrote it in this way is it right or not? > Not. Not even close (to be more precise) Consider downloading either a free version of Modelsim or GHDL and start compiling and simulating your code. The tool will give you must quicker and more detailed responses to your questions...it will also let you simulate your design to see if it works as you intend. Learning by doing is a very effective method. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:01 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p20g2000yqp.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 18:07:13 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311212098 22877 127.0.0.1 (21 Jul 2011 01:34:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 01:34:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqp.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5170 On Jul 20, 6:09=A0pm, fearg wrote: > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. The easiest method to do what you say in the above paragraph is to simply use the debug capabilities of the synthesis tool. Each tool will let you select arbitrary signals from within a design and bring them out to a set of pins which you select. These signals are generally intended to be connected to a logic analyzer...but there is no reason they can't be connected to the display devices that you require. No code changes required. However, if you have some other reason for requiring a VHDL model thus leading to your steps 1-3d than this method won't work. So you need to decide if you're looking for a VHDL model or simply something that is implemented in hardware. If it's hardware only, use the logic analyzer interface approach. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g5g2000prn.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Attribute that shows if signal is clocked or not? Date: Wed, 20 Jul 2011 19:17:21 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: NNTP-Posting-Host: 98.248.118.123 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311214641 16573 127.0.0.1 (21 Jul 2011 02:17:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 02:17:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g5g2000prn.googlegroups.com; posting-host=98.248.118.123; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5171 Hello, Is there a VHDL attribute that tells whether or not a signal is driven synchronously or asynchronously? I have found a place in my design where I think a latch would be nice to use, but I'd like to have some sort of assert statement like the following to make sure it isn't driven asynchronously. assert latch_enable'synchronous report "Latch enable must be a synchronous signal to avoid glitches" severity failure; Thanks, Colin From newsfish@newsfish Fri Feb 3 13:14:02 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!dp9g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Attribute that shows if signal is clocked or not? Date: Wed, 20 Jul 2011 20:51:05 -0700 (PDT) Organization: http://groups.google.com Lines: 30 Message-ID: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311220617 11093 127.0.0.1 (21 Jul 2011 03:56:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 03:56:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dp9g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5172 On Jul 20, 10:17=A0pm, Colin Beighley wrote: > Hello, > > Is there a VHDL attribute that tells whether or not a signal is driven > synchronously or asynchronously? No > I have found a place in my design > where I think a latch would be nice to use, If this is targetting an FPGA, then check to make sure that the target device actually has a latch primitive. If not, then the synthesis tool will implement the latch with logic and you'll likely find that using a latch is not so nice after all. Even if the FPGA *does* have latches, you'll have to manually check to see that the implemented design actually does use the latch primitive rather than cobbling it together with logic cells. > but I'd like to have some > sort of assert statement like the following to make sure it isn't > driven asynchronously. > Sound like you're into generating internal clock-like signsls...if the target device is an FPGA you'll likely regret this decision. Data hold timing will bite you. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!e8g2000yqi.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Wed, 20 Jul 2011 23:56:03 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: References: NNTP-Posting-Host: 86.45.244.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311231765 25670 127.0.0.1 (21 Jul 2011 07:02:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 07:02:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e8g2000yqi.googlegroups.com; posting-host=86.45.244.35; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5173 thanks for the suggestions Colin and Kevin. I'll look into the synthesis debug and VHDL-2008 options. However, Ideally I'd like an easy to use an application independent of synthesis tools and may have to develop a generic solution myself. Fearghal Morgan From newsfish@newsfish Fri Feb 3 13:14:03 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 21 Jul 2011 10:05:27 +0200 Lines: 16 Message-ID: <98q4u5FfklU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net Re64KJ6ETNrOr+FIc4Cgag1ps1pe6t/ErPtegzx1g7VLuUuM25 Cancel-Lock: sha1:DsVggtuUjP5SjZmBW3YEBWd1OKM= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5174 On 7/20/2011 7:14 PM, Daniel Leu wrote: > Google provides some links if you just search for "makefiles > bergeron": > - www.vhdl.org/misc/ModelingGuidelines.paper.ps This (IMHO very interesting) article is "Guidelines for Writing VHDL Models in a Team Environment". > - pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf > This is "Managing VHDL Models with Makefiles". Thanks for pointing them out, I'm trying to subscribe to "Verification Guild" but I still have some problems. From newsfish@newsfish Fri Feb 3 13:14:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!j9g2000prj.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Thu, 21 Jul 2011 09:13:09 -0700 (PDT) Organization: http://groups.google.com Lines: 29 Message-ID: <19cfaf6d-f58f-4346-bf90-55b5d9f0a1d3@j9g2000prj.googlegroups.com> References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> NNTP-Posting-Host: 67.180.134.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311264872 31649 127.0.0.1 (21 Jul 2011 16:14:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 16:14:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j9g2000prj.googlegroups.com; posting-host=67.180.134.147; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.91 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5175 On Jul 20, 2:03=A0pm, KJ wrote: > On Jul 20, 2:14=A0pm, Colin Beighley wrote: > > > Hello, > > > I keep running across situations where a conditional variable or > > signal declaration would be very useful in simulation (for instance, > > declaring full range integers or reals), but I don't want any of these > > to attempt to be synthesized. Is there an eloquent way of doing this? > > I don't believe you can use the generate statement for declarations. I > > have heard of people using the C preprocessor for this, but this seems > > like a hack IMO. > > You can declare signals within a generate statement. =A0Then set the > generate condition appropriately to not generate for synthesis. > > if xxx generate > =A0 =A0signal xyz_real: =A0real; > begin > =A0 =A0xyz <=3D to_real(xyz_fp); > end generate xxx; > > Kevin Jennings So I think the --synthesis translate_off/on statements will give me the functionality I need for simulation vs synthesis, but a conditional declaration of the #ifdef type would still be useful. Signals declared in generate statements are limited in scope to their generate statement, correct? From newsfish@newsfish Fri Feb 3 13:14:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Thu, 21 Jul 2011 09:32:20 -0700 Lines: 21 Message-ID: <98r2l5Fjb4U1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net cwRujlUFp+KtK0AgSWoCWQxXkPWGBGei77OGWm11ay4FkrlMVe Cancel-Lock: sha1:TqnM+a2CcG2WNhhBMnuCF+E6+44= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5176 On 7/20/2011 11:56 PM, fearg wrote: > thanks for the suggestions Colin and Kevin. > I'll look into the synthesis debug and VHDL-2008 options. > However, Ideally I'd like an easy to use an application independent of > synthesis tools How will you connect the "display devices" to the fpga without editing code and running synthesis to make the new interface. > and may have to develop a generic solution myself. 1. Copy code 2. Edit the code (manual or script) 3. Synthesize the code and load an fpga image 4. Hook up the displays and test. Seems to me that it might be easier to write a testbench and watch the internal waves directly, as Kevin suggests. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:14:04 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!v7g2000vbk.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Conditional declarations Date: Thu, 21 Jul 2011 09:40:10 -0700 (PDT) Organization: http://groups.google.com Lines: 70 Message-ID: References: <02d19f59-5e7e-4c42-8bb1-0171d69c9f72@m6g2000prh.googlegroups.com> <6f67e2e7-6eb1-449a-ad09-66bfad04e371@x10g2000vbl.googlegroups.com> <19cfaf6d-f58f-4346-bf90-55b5d9f0a1d3@j9g2000prj.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311266410 14639 127.0.0.1 (21 Jul 2011 16:40:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 21 Jul 2011 16:40:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v7g2000vbk.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5177 On Jul 21, 12:13=A0pm, Colin Beighley wrote: > On Jul 20, 2:03=A0pm, KJ wrote: > > > > > > > On Jul 20, 2:14=A0pm, Colin Beighley wrote: > > > > Hello, > > > > I keep running across situations where a conditional variable or > > > signal declaration would be very useful in simulation (for instance, > > > declaring full range integers or reals), but I don't want any of thes= e > > > to attempt to be synthesized. Is there an eloquent way of doing this? > > > I don't believe you can use the generate statement for declarations. = I > > > have heard of people using the C preprocessor for this, but this seem= s > > > like a hack IMO. > > > You can declare signals within a generate statement. =A0Then set the > > generate condition appropriately to not generate for synthesis. > > > if xxx generate > > =A0 =A0signal xyz_real: =A0real; > > begin > > =A0 =A0xyz <=3D to_real(xyz_fp); > > end generate xxx; > > > Kevin Jennings > > So I think the --synthesis translate_off/on statements will give me > the functionality I need for simulation vs synthesis, but a > conditional declaration of the #ifdef type would still be useful. > Signals declared in generate statements are limited in scope to their > generate statement, correct?- Hide quoted text - > Yes, the signals are limited in scope to being within the generate statement. But that doesn't mean that they can't access things that are outside of scope. You asked for a conditional method to declare signals (and presumably use them) for simulation but not synthesis. That's precisely what the language itself can provide you with the generate statement. The translate_off/on has some limitations: - translate_off/on is not conditional 'as-is' (which would seem to violate what you said you were looking for). People do play games with how they write the text to accomplish their specific goals, but it is always kludgy - translate_off/on is a pragma that is embedded within a comment...so it rightfully gets ignored by other tools. This implies that your simulations will compile and run just fine, only when you run the synthesis tool do you find that you have an 'off' without an 'on' or typed 'translate off' or 'translate on' or some other simple misspelling. They don't necessarily take long to clean up and fix, but why bother when the generate statement is accepted by all tools since it is part of the language and does what it appears that you need? If it doesn't perhaps you should explain a bit more about how the example I gave you doesn't meet your needs and we can go from there. About the only limitation of the generate statement I can think of is that it is only applicable inside the architecture of an entity. In particular it cannot be used in code that is in a package. There you would have to use translate_off/on. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Attribute that shows if signal is clocked or not? Date: Thu, 21 Jul 2011 13:37:37 -0400 Organization: Alacron, Inc. Lines: 40 Message-ID: References: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 21 Jul 2011 17:37:56 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="2280"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+rpnt6Ydi6/ecaanBcM/K4" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <6ea926a5-34c8-4bbc-ba2d-3dc13fe456f7@dp9g2000vbb.googlegroups.com> Cancel-Lock: sha1:CzLC9HdfEfm33BCg6SUUGk7Vk8Q= Xref: feeder.eternal-september.org comp.lang.vhdl:5178 KJ wrote: > On Jul 20, 10:17 pm, Colin Beighley wrote: >> Hello, >> >> Is there a VHDL attribute that tells whether or not a signal is driven >> synchronously or asynchronously? > > No > >> I have found a place in my design >> where I think a latch would be nice to use, > > If this is targetting an FPGA, then check to make sure that the target > device actually has a latch primitive. If not, then the synthesis > tool will implement the latch with logic and you'll likely find that > using a latch is not so nice after all. > > Even if the FPGA *does* have latches, you'll have to manually check to > see that the implemented design actually does use the latch primitive > rather than cobbling it together with logic cells. > >> but I'd like to have some >> sort of assert statement like the following to make sure it isn't >> driven asynchronously. >> > > Sound like you're into generating internal clock-like signsls...if the > target device is an FPGA you'll likely regret this decision. Data > hold timing will bite you. > > Kevin Jennings Regardless of your target, most synthesis tools will warn when you create latches. I haven't seen any that allow you to promote a latch warning to an error, but you can always grep the synthesis report to see if any latch warnings were generated. I'm sure that reading through the warnings after synthesis is a useful exercise anyway... -- Gabor From newsfish@newsfish Fri Feb 3 13:14:05 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!i6g2000yqe.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: Assertions Date: Fri, 22 Jul 2011 04:21:07 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 194.200.65.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311333667 14565 127.0.0.1 (22 Jul 2011 11:21:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 11:21:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i6g2000yqe.googlegroups.com; posting-host=194.200.65.239; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5179 Hello We do our development work in VHDL. We are starting to formulate our ABV strategy and are currently thinking of using PSL assertions to either imbed in the VHDL code or define the PSL assertions as vunits. However, another line of thought is to use System Verilog assertions with the VHDL RTL, since later on we want to go down the UVM strategy and Random Constrained Verification. QS: Does anyone have any feel for 1) how easy/difficult it is to connect the System Verilog assertions to the VHDL RTL? 2) How easy/difficult it will be to debug the assertions if we adopt the System Verilog assertions and VHDL? Thanks J From newsfish@newsfish Fri Feb 3 13:14:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe13.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Assertions References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> In-Reply-To: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110722-0, 22/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 67 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe13.ams2 1311347827 82.31.236.233 (Fri, 22 Jul 2011 15:17:07 UTC) NNTP-Posting-Date: Fri, 22 Jul 2011 15:17:07 UTC Organization: virginmedia.com Date: Fri, 22 Jul 2011 16:17:15 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5180 On 22/07/2011 12:21, thunder wrote: > Hello > > We do our development work in VHDL. > Good! > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. You will probably use both. > > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy I wouldn't worry to much, there is quite some similarity between PSL and SVA as both standards are maintained/developed by Accellera. If you use VHDL then I would suggest you stick with PSL. You will learn it quicker than SVA as you can use familiar operators and constructs (AND, OR, is, to, rising_edge etc). I also believe IMHO that PSL is easier to learn than SVA. The disadvantage of PSL (as is with VHDL) is that EDA vendors seem to spend their R&D budget on SV and SVA only. This is not because these languages are superior but simply because of the 20/80 rule (80% of their revenue comes from 20% of their customers and these 20% are all big Verilog/SV ASIC users). For PSL you also need to use a bit of extra code as bins and related verification constructs are not part of the standard. > and Random Constrained Verification. You can do CR with VHDL as well. Jim Lewis has a great CR package on his website. What is lacking is support for a constraint solver but you should be able to cook something up using the FLI/VHPI. > > QS: Does anyone have any feel for > 1) how easy/difficult it is to connect the System Verilog > assertions to the VHDL RTL? Not difficult, you simply "bind" the SVA module to your VHDL entity/architecture. Note that SVA does not support embedded assertions. > 2) How easy/difficult it will be to debug the assertions if > we adopt the System Verilog assertions and VHDL? It depends on your simulator but I suspect no different from debugging PSL. Good luck, Hans www.ht-lab.com > > > Thanks > > J From newsfish@newsfish Fri Feb 3 13:14:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 22 Jul 2011 14:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: <13559aa6-3773-4e6a-bfd8-814e2e0365f8@r18g2000vbs.googlegroups.com> References: NNTP-Posting-Host: 86.46.41.133 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311371752 12327 127.0.0.1 (22 Jul 2011 21:55:52 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 21:55:52 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=86.46.41.133; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5181 Colin, the hierarchical access in VHDL-2008 is useful. I do need to synthesise the model with signal brought to the top level though. Fearghal > > It seems VHDL-2008 has some support similar to this. Doulos says that > it is not synthesizable, however.http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200... > Look at the section Hierarchical Names. From newsfish@newsfish Fri Feb 3 13:14:06 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b19g2000yqj.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 22 Jul 2011 15:16:21 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> NNTP-Posting-Host: 86.46.41.133 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311373833 960 127.0.0.1 (22 Jul 2011 22:30:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 22 Jul 2011 22:30:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b19g2000yqj.googlegroups.com; posting-host=86.46.41.133; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5182 Kevin, I generally use Xilinx XST synthesis tool. Could you please point me to the debug facility within XST which allows the bringing of internal signals to the top level (if this exists)? I should clarify my requirement further: For any existing design VHDL model entity (e.g, designX), I wish to automatically modify the VHDL files to bring selected output signals from low levels of the design hierarchy to the designX entity. I then instantiate designX within another VHDL model (designTop) which contains the host interface and display device controller, and connect the newly accessible signals as required for output to host and display devices. If the above can be automated, I can quickly take any design and connect its internal signals to my host and display interfaces. I do not wish to use a logic analyser facility. > The easiest method to do what you say in the above paragraph is to > simply use the debug capabilities of the synthesis tool. =A0Each tool > will let you select arbitrary signals from within a design and bring > them out to a set of pins which you select. =A0These signals are > generally intended to be connected to a logic analyzer...but there is > no reason they can't be connected to the display devices that you > require. =A0No code changes required. > > However, if you have some other reason for requiring a VHDL model thus > leading to your steps 1-3d than this method won't work. =A0So you need > to decide if you're looking for a VHDL model or simply something that > is implemented in hardware. =A0If it's hardware only, use the logic > analyzer interface approach. > > Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: abhishekshishodia Newsgroups: comp.lang.vhdl Subject: Design Built-in Self Test Date: Fri, 22 Jul 2011 23:05:20 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <72360074-df74-4637-8bf9-e8725151f1ba@a2g2000prf.googlegroups.com> NNTP-Posting-Host: 117.211.93.74 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311401467 20257 127.0.0.1 (23 Jul 2011 06:11:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 23 Jul 2011 06:11:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=117.211.93.74; posting-account=fcag1AoAAACji3PtI5a5Ab8a5Gkwbqqb User-Agent: G2/1.0 X-HTTP-Via: 1.0 Webcat-Skein-C010001296-GEHY2E (awarrenhttp/2.0.0.5.4) X-Google-Web-Client: true X-Google-Header-Order: ARLEUHNKCV X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.1),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5183 Hello freinds, I am final yr. graduating student of enginnering. I have to do a major project for which I have decided to design Built-in self test fo memory testing. Please tell me how could I design memory(eg. RAM) in VHDL. I only know that I could need ModelSIM and synopsys software dc_shell for doing this. Please tell me how could I implement RAM in VHDL and then design a built-in self test for testing that memory. -Abhishek From newsfish@newsfish Fri Feb 3 13:14:07 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!df3g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Design Built-in Self Test Date: Sat, 23 Jul 2011 10:05:40 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: References: <72360074-df74-4637-8bf9-e8725151f1ba@a2g2000prf.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311441547 3792 127.0.0.1 (23 Jul 2011 17:19:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 23 Jul 2011 17:19:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: df3g2000vbb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5184 On Jul 23, 2:05=A0am, abhishekshishodia wrote: > Hello freinds, > > I am final yr. graduating student of enginnering. I have to do a major > project for which I have decided =A0to design Built-in self test fo > memory testing. > Please tell me how could I design memory(eg. RAM) in VHDL. I only know > that I could need ModelSIM and synopsys software dc_shell for doing > this. Please tell me how could I implement RAM in VHDL and then design > a built-in self test for testing that memory. > Try using Google http://lmgtfy.com/?q=3Dhow+could+I+implement+RAM+in+VHDL+and+then+design+ Some examples that pop out http://quartushelp.altera.com/current/mergedProjects/hdl/vhdl/vhdl_pro_ram_= inferred.htm http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.h= tml KJ From newsfish@newsfish Fri Feb 3 13:14:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sun, 24 Jul 2011 00:27:45 +0200 Lines: 11 Message-ID: <99106uFbt6U1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net 5rOYWxieqiwSMUIBvOqdvA+nPokXt/0SOCBtc7y7nMYcDScFcV Cancel-Lock: sha1:AXqEQz91s6nWfY8xUkMy5997aVY= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5185 On 7/20/2011 1:31 AM, Alan Fitch wrote: > Try posting your message on the Verification Guild > http://verificationguild.com (I think, from memory). Janick started the > website, and often posts there, > In case somebody maybe interested, the article in the subject is indeed this one: "Managing VHDL Models with Makefiles" by Janick Bergeron (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) From newsfish@newsfish Fri Feb 3 13:14:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o4g2000vbv.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Sun, 24 Jul 2011 06:53:05 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> NNTP-Posting-Host: 86.46.39.61 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311515585 6463 127.0.0.1 (24 Jul 2011 13:53:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 24 Jul 2011 13:53:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o4g2000vbv.googlegroups.com; posting-host=86.46.39.61; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5186 Hi, if I can extracta listing of component and signal hierarchy from ISE (to a file), I could investigate writing a program to automate the addition and connection of lower level signals up to the top level. Its tedious manually, and would benefit from automation. I'd require the generation of a listing something like the following from an EDA tool: topLevel/LA1:A1/LB1:B1/LC1:C1/sigX sigLC1X where: LA1 is the label for component A1, instantiated in topLevel VHDL model LB1 is the label for component B1, instantiated in A1 VHDL model LC1 is the label for component C1, instantiated in B1 VHDL model sigX is VHDL model C1 entity signal sigLC1X is the port map signal in the VHDL model B1, used to connect to component C1 port sigX topLevel/LA1:A1/LB1:B1/LC1:C1/sigY sigLC1Y topLevel/LA1:A1/LB1:B1/LC2:C1/sigX sigLC2X topLevel/LA1:A1/LB1:B1/LC2:C1/sigY sigLC2Y topLevel/LA1:A1/LB1:B1/LC3:C2/sigP sigLC3P etc Note: in this example, component C1 is used twice in VHDL model B1. sigLC2X is the port map signal in the VHDL model B1, used to connect to component C2 port sigX I would be grateful for any advice. regards, Fearghal From newsfish@newsfish Fri Feb 3 13:14:08 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!transit3.readnews.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!dp9g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Mon, 25 Jul 2011 05:57:25 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311598646 2706 127.0.0.1 (25 Jul 2011 12:57:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 25 Jul 2011 12:57:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dp9g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5187 On 24 Jul., 00:27, Alessandro Basili wrote: > On 7/20/2011 1:31 AM, Alan Fitch wrote: > > > Try posting your message on the Verification Guild > >http://verificationguild.com(I think, from memory). Janick started the > > website, and often posts there, > > In case somebody maybe interested, the article in the subject is indeed > this one: > > "Managing VHDL Models with Makefiles" by Janick Bergeron > (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) Where can the tools described be downloaded ? Cheers, hssig From newsfish@newsfish Fri Feb 3 13:14:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Mon, 25 Jul 2011 16:32:05 +0200 Lines: 18 Message-ID: <995d36FlvbU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net bUS7jSuUlGmRNLqgpzdPewfw99GSuTz9Zi+V/Ze6HNhmz4chN+ Cancel-Lock: sha1:FA2p291dKg1ZWmWa7iQz880Y0Dc= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5188 On 7/25/2011 2:57 PM, hssig wrote: In case somebody maybe interested, the article in the subject is indeed >> this one: >> >> "Managing VHDL Models with Makefiles" by Janick Bergeron >> (http://pldworld.pe.kr/_hdl/1/RESOURCES/QUALIS/library/mb004.pdf) > > > > > Where can the tools described be downloaded ? > http://sourceforge.net/projects/vmk/ > Cheers, hssig > From newsfish@newsfish Fri Feb 3 13:14:09 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Tue, 26 Jul 2011 08:05:52 +0200 Lines: 65 Message-ID: <9973q0Fvb9U1@mid.individual.net> References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net B7uofcO8EF1pwe7a0GHqAw9tXQ1YK6Smygfjmfoy4SODPIZsnE Cancel-Lock: sha1:FRKuzNzpH/7l4UiFB1MKk8CF2Vc= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5189 On 7/24/2011 3:53 PM, fearg wrote: > Hi, > > if I can extracta listing of component and signal hierarchy from ISE > (to a file), Emacs speedbar does it for you, you only need the vhdl file(s). > I could investigate writing a program to automate the > addition and connection of lower level signals up to the top level. > Its tedious manually, and would benefit from automation. > For testing purposes you may add a jtag port to every component, connect it in a daisy chain and play around with Boundary Scan Register and Instruction Register. But you cannot have it operational while you are in (IN/EX)TEST mode. > I'd require the generation of a listing something like the following > from an EDA tool: [snip] > Note: in this example, component C1 is used twice in VHDL model B1. > sigLC2X is the port map signal in the VHDL model B1, used to > connect to component C2 port sigX > I once was convinced that defining the signals in a package so that they are seen as global and therefore "available" to the whole hierarchy was a good thing. In that case I could have set the registers in one module and use it in another without the need to go through In/Out. In that approach connecting a signal to the top level was as simple as doing: pin_out <= global_signal; I found later on it was a very bad practice, since it resulted in a very poorly reusable code and I spent most of my time trying to remember where the heck in my code I was using those registers (pretty much the same as any other programming/description language). > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. I'm assuming your "existing VHDL model" is an open hierarchical model where you have access to all the components interfaces it uses. If that is the case editing the code and picking up the signals you want (as suggested) is much simpler. If your "existing VHDL model" is the output of an edif2vhdl converter or a back-annotate process there's no way to do what you want, since I'm pretty convinced the output vhdl would be rather "flat" as opposed to hierarchical. Bear in mind that if a signal is not accessible from the top level it might be a good thing. After all you are interested in the functionality of the code, not the details of the flops and gates. And if you are debugging the module there's no better place than your simulation, much more effective and less time consuming. Set aside that if your are targeting a antifuse logic device all your tries will end up in a lot of chips thrown out of the window. Al From newsfish@newsfish Fri Feb 3 13:14:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!y8g2000vba.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Exponential code in VHDL Date: Wed, 27 Jul 2011 02:19:26 -0700 (PDT) Organization: http://groups.google.com Lines: 13 Message-ID: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311758467 7948 127.0.0.1 (27 Jul 2011 09:21:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 09:21:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y8g2000vba.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5190 Hi all, I am about implementing a VHDL code but I am facing problem, I have an exponential operation and I want to run that code op an FPGA board!! Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / 8.5))); Would you please help me in that? Many thanks in advance... Zaid From newsfish@newsfish Fri Feb 3 13:14:10 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!v7g2000vbk.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 27 Jul 2011 05:36:08 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311770270 19289 127.0.0.1 (27 Jul 2011 12:37:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 12:37:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v7g2000vbk.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.19) Gecko/20110707 Firefox/3.6.19,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5191 Is there a possibility to use that tool under Windows (7) ? How do I have to install it? Cheers, hssig From newsfish@newsfish Fri Feb 3 13:14:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Wed, 27 Jul 2011 15:18:18 +0200 Lines: 17 Message-ID: <99ahgpF1ndU1@mid.individual.net> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net ROWFufP2WkP/eBl4YbjG+Asu9+Sl6TmZhJ/eFcgAEOezTh52/U Cancel-Lock: sha1:+NyZ4byOOoR+U/CYNhpmIWL5sqg= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> X-Enigmail-Version: 1.2 Xref: feeder.eternal-september.org comp.lang.vhdl:5192 On 7/27/2011 2:36 PM, hssig wrote: > Is there a possibility to use that tool under Windows (7) ? How do I > have to install it? I think it is possible, if you have cygwin installed: http://www.cygwin.com/ you should be able to install with a simple "make" command from the top level directory. I have to say I have not tried it yet. Just looking into it these days. > > Cheers, > hssig > From newsfish@newsfish Fri Feb 3 13:14:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe24.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> In-Reply-To: <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110727-0, 27/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 24 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe24.ams2 1311778336 82.31.236.233 (Wed, 27 Jul 2011 14:52:16 UTC) NNTP-Posting-Date: Wed, 27 Jul 2011 14:52:16 UTC Organization: virginmedia.com Date: Wed, 27 Jul 2011 15:52:28 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5193 On 27/07/2011 13:36, hssig wrote: > Is there a possibility to use that tool under Windows (7) ? How do I > have to install it? > > Cheers, > hssig > As suggested earlier why don't you simply use vmake from Modelsim? Vmake can be used without a valid license (just extract after running the installer). Use vcom (also no valid license required) to compile your design followed by running vmake. You can now use any make program under windows (I use nmake from Visual C++) to process it. Vmake can also handle Verilog files but unfortunately not SystemC. Good luck, Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:14:11 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 27 Jul 2011 11:09:00 -0500 Date: Wed, 27 Jul 2011 09:09:02 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> In-Reply-To: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 21 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-PCc6DgvvJ7WjBjw15MDBoWXcEBb9ZvsdiSt651r+HcIvne7HhKlIqfX36VWE+cmBZDDHfJz9bvJkqMG!TD2WzP/sDdeoUIUXrFqRxLwSylWRnBcz3F/oI4OctJp8DBjArI3TsUTukTaZhF++j53HB7swHwJR X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1701 Xref: feeder.eternal-september.org comp.lang.vhdl:5194 On 7/27/2011 2:19 AM, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: X = (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Yeah, bound the range of y sufficiently that you can implement the entire thing in a RAM lookup table. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!t8g2000prm.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Wed, 27 Jul 2011 10:23:57 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 216.191.123.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311787788 12298 127.0.0.1 (27 Jul 2011 17:29:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 27 Jul 2011 17:29:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t8g2000prm.googlegroups.com; posting-host=216.191.123.37; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-HTTP-Via: 1.1 SRV-QC-ISA02 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5195 On 27 juil, 05:19, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid One simple way would be to use a look-up table implemented in a ROM. With "y" being the address and X being the data read at "y" address. This solution would work well if the range of "y" in bits is smaller or equal to 16 bits. If "y" is 32-bit wide then I don't think a look- up table implemented in a FPGA-Rom will work. From newsfish@newsfish Fri Feb 3 13:14:12 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c8g2000prn.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Assertions Date: Wed, 27 Jul 2011 18:20:11 -0700 (PDT) Organization: http://groups.google.com Lines: 35 Message-ID: References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311816012 4662 127.0.0.1 (28 Jul 2011 01:20:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 01:20:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c8g2000prn.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5196 Hi, > We do our development work in VHDL. > > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. > > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy > and Random Constrained Verification. I would keep it simple. For assertions in a VHDL program, I would use PSL. Before you invest in System Verilog, you might want to take a look at: http://www.mentor.com/company/industry_keynotes/upload/DVCon-2011.pdf Their claim is that SV + UVM + CRV, but instead that you need an additional intelligent testbench tool to effectively do verification. Hence, it is a significant investment in tools. OTOH, in VHDL, in addition to our Randomization package that Hans mentioned, you might want to also check out our Coverage Package. The 2.1 release takes you part of the way to more effective verification, however, in the next several releases (2.2 due soon), the capability is growing. Check it out at: http://www.synthworks.com/downloads/index.htm Best, Jim From newsfish@newsfish Fri Feb 3 13:14:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!feeder1.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!a2g2000prf.googlegroups.com!not-for-mail From: noobie Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Thu, 28 Jul 2011 00:31:40 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <907e30c3-a94a-4dfe-948b-646bbe444c86@a2g2000prf.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 122.174.105.155 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311838301 4846 127.0.0.1 (28 Jul 2011 07:31:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 07:31:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a2g2000prf.googlegroups.com; posting-host=122.174.105.155; posting-account=T25uaQkAAACANge_Tfmo0_JXOli3REzM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.124 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5197 On Jul 27, 2:19=A0pm, Zaid Al-Hilli wrote: > Hi all, > > I am about implementing a VHDL code but I am facing problem, I have an > exponential operation and I want to run that code op an FPGA board!! > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) / > 8.5))); > > Would you please help me in that? > > Many thanks in advance... > > Zaid Use Taylor series expansion for the calculation of this equation. Use fixed point arithmetic. From newsfish@newsfish Fri Feb 3 13:14:13 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!feeder.erje.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Newsgroups: comp.lang.vhdl Date: Thu, 28 Jul 2011 11:15:07 +0200 References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 29 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1311844507 news2.news.xs4all.nl 23870 puiterl/195.242.97.150:44935 Xref: feeder.eternal-september.org comp.lang.vhdl:5198 HT-Lab wrote: > On 27/07/2011 13:36, hssig wrote: >> Is there a possibility to use that tool under Windows (7) ? How do I >> have to install it? >> >> Cheers, >> hssig >> > > As suggested earlier why don't you simply use vmake from Modelsim? The major difference of course between vmake and a program like vmk is that vmake creates a makefile from already compiled libraries and that vmk creates a makefile directly from the VHDL sources. So for the initial compilation vmk must be used. Or manual compilation, and optional use of the vcom option "-just eapbc" and wildcards for the VHDL files. But that does not always work, for example if packages uses other packages from the same library. For keeping libraries up to date vmake might be more convenient to use. I use both vmake and vmk. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:14:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!fv14g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 28 Jul 2011 05:32:13 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311856760 28645 127.0.0.1 (28 Jul 2011 12:39:20 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 12:39:20 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fv14g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.19) Gecko/20110707 Firefox/3.6.19,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5199 Hi Hans, do you have a real example to share in which you use vmake from Modelsim ? Cheers, Hssig From newsfish@newsfish Fri Feb 3 13:14:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Should VHDL allow Unicode identifiers and comments Date: 28 Jul 2011 19:13:48 GMT Lines: 20 Message-ID: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Trace: individual.net aFh+Km90xgzFVXRn2JvSPg7hUXLFSC9HygmIs/r06UcbEGiZE= Cancel-Lock: sha1:o0DtTJGtX0kwIS8qhTACav8+Y5Q= User-Agent: Pan/0.133 (House of Butterflies) Xref: feeder.eternal-september.org comp.lang.vhdl:5200 Hi all, I'm asking for a bit of input from the community... As the title says, would you find it of use to allow Unicode identifiers and comments in a future VHDL revision? Would this be: a) Something VHDL should not allow b) Something that doesn't bother you either way c) Something you'd find useful sometimes d) Something you'd make use of all the time e) Something that you'd switch away from SystemVerilog just to get at (maybe I'm asking the wrong crowd for that :) Thanks, Martin -- http://parallelpoints.com/ From newsfish@newsfish Fri Feb 3 13:14:14 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Thu, 28 Jul 2011 16:10:19 -0500 Organization: A noiseless patient Spider Lines: 24 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 28 Jul 2011 21:10:19 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="N63w/DHusx/mn4zn8Evv7g"; logging-data="23350"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Nu2CuKGcewfw4hsEqqOCc" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <99dqncFsnU1@mid.individual.net> Cancel-Lock: sha1:GO+tSqYjKzviUQ1RsAj70Uxl97Y= Xref: feeder.eternal-september.org comp.lang.vhdl:5201 On 7/28/2011 2:13 PM, Martin Thompson wrote: > Hi all, > > I'm asking for a bit of input from the community... > > As the title says, would you find it of use to allow Unicode identifiers > and comments in a future VHDL revision? > > Would this be: > a) Something VHDL should not allow > b) Something that doesn't bother you either way > c) Something you'd find useful sometimes > d) Something you'd make use of all the time > e) Something that you'd switch away from SystemVerilog just to get at > (maybe I'm asking the wrong crowd for that :) > > Thanks, > Martin > b, Regards, Chris Fetlon From newsfish@newsfish Fri Feb 3 13:14:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u12g2000prc.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Assertions Date: Thu, 28 Jul 2011 14:10:32 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <42fa03bd-67f3-4173-aab7-21938e7f092e@i6g2000yqe.googlegroups.com> NNTP-Posting-Host: 76.115.22.169 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311887433 17030 127.0.0.1 (28 Jul 2011 21:10:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Jul 2011 21:10:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u12g2000prc.googlegroups.com; posting-host=76.115.22.169; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5202 > We do our development work in VHDL. > > We are starting to formulate our ABV strategy and are currently > thinking of using PSL assertions to either imbed in the VHDL code or > define the PSL assertions as vunits. For VHDL, I would stick with PSL. > However, another line of thought is to use System Verilog assertions > with the VHDL RTL, since later on we want to go down the UVM strategy > and Random Constrained Verification. As an alternative to SV, check out our free open-source VHDL packages for functional coverage and randomization. At the end of the day, I think functional coverage is going to become more and more important. Currently our functional coverage methodology is setup so you can capture high-fidelity functional coverage models and use these go guide your randomization. The packages are available at: http://www.synthworks.com/downloads Best, Jim From newsfish@newsfish Fri Feb 3 13:14:15 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 28 Jul 2011 16:19:07 -0500 Date: Thu, 28 Jul 2011 14:19:09 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments References: <99dqncFsnU1@mid.individual.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 32 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-hSQ+/AaZB6qSPWLZuX8ga0zOIjeEQbchCsoPpX9W6F3A4y82kxIgVBM5XG0yd6pTcRr1VUABSouTMdG!DFWwFz/bm2hl4kThySdwHcFsWfqn2zO4QNM4oHDkFbXYl0g6F0OC25ZlLZpYVA/oPnnMh1h5q/7R X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1998 Xref: feeder.eternal-september.org comp.lang.vhdl:5203 On 7/28/2011 2:10 PM, Christopher Felton wrote: > On 7/28/2011 2:13 PM, Martin Thompson wrote: >> Hi all, >> >> I'm asking for a bit of input from the community... >> >> As the title says, would you find it of use to allow Unicode identifiers >> and comments in a future VHDL revision? >> >> Would this be: >> a) Something VHDL should not allow >> b) Something that doesn't bother you either way >> c) Something you'd find useful sometimes >> d) Something you'd make use of all the time >> e) Something that you'd switch away from SystemVerilog just to get at >> (maybe I'm asking the wrong crowd for that :) >> >> Thanks, >> Martin >> > > b, > > Regards, > Chris Fetlon Unless the introduction of said identifiers started breaking my existing tools, in which case (a). -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Thu, 28 Jul 2011 16:45:02 -0700 Lines: 24 Message-ID: <99eakqFo0rU1@mid.individual.net> References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net vUM7bot19e7eLiPWOCfQqQKAe67CpacAMgfbIzCpzHDueqtA6E Cancel-Lock: sha1:ORB23iG1sss9VjLe1lA15X0whBQ= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <99dqncFsnU1@mid.individual.net> Xref: feeder.eternal-september.org comp.lang.vhdl:5204 On 7/28/2011 12:13 PM, Martin Thompson wrote: > Hi all, > > I'm asking for a bit of input from the community... > > As the title says, would you find it of use to allow Unicode identifiers > and comments in a future VHDL revision? > > Would this be: > a) Something VHDL should not allow > b) Something that doesn't bother you either way > c) Something you'd find useful sometimes c) Yes, will be helpful in the near future. Otherwise everyone will have a different library for it. > d) Something you'd make use of all the time > e) Something that you'd switch away from SystemVerilog just to get at > (maybe I'm asking the wrong crowd for that :) > > Thanks, > Martin > From newsfish@newsfish Fri Feb 3 13:14:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t38g2000prj.googlegroups.com!not-for-mail From: JSreeniv Newsgroups: comp.lang.vhdl Subject: Regarding to the DUT configuration in testbench Date: Thu, 28 Jul 2011 19:29:03 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <76b40fe2-f4f9-4f86-83af-d93d2f0d5dd1@t38g2000prj.googlegroups.com> NNTP-Posting-Host: 203.92.217.80 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1311906544 16213 127.0.0.1 (29 Jul 2011 02:29:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 02:29:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t38g2000prj.googlegroups.com; posting-host=203.92.217.80; posting-account=cCqSmQoAAAD72P5YVFrs1ZNFbeH4XiZ1 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HURAELSCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/533.4 (KHTML, like Gecko) Chrome/5.0.375.125 Safari/533.4,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5205 Hi, I was exploring the DUT connectivity with my testbench(TB). What i am doing: With my encrypted DUT i wrote a TB (for reception) MIL 1553 FE by configuring the register to the mode as RT and start sending the command and number of data on 1553_rx lines (where the command and data are Valid) w.r.t the standard and after some response time the transmitter will send a status word followed by data word on 1553_tx lines. The actual query is that can i configure one DUT as BC mode and again same DUT as RT mode (Here we can change DUT names while configuring in ModelSim) so that my TB can handle the communication between BC and RT mode. Since i have only RT terminal register set i can access whatever i want, but i don't have register set for BC but mode setting facility is available for the register. Could anyone suggest me whether this is possible or not and some more analysis. Thanks Nivas. From newsfish@newsfish Fri Feb 3 13:14:16 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> In-Reply-To: <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 110728-1, 28/07/2011), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: NNTP-Posting-Host: 82.31.236.233 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1311926302 82.31.236.233 (Fri, 29 Jul 2011 07:58:22 UTC) NNTP-Posting-Date: Fri, 29 Jul 2011 07:58:22 UTC Organization: virginmedia.com Date: Fri, 29 Jul 2011 08:58:35 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5206 On 28/07/2011 13:32, hssig wrote: > Hi Hans, > > do you have a real example to share in which you use vmake from > Modelsim ? > > > Cheers, Hssig > Hi Hssig, If you have Modelsim installed then you can use one of their examples: Navigate to ..\examples\tutorials\vhdl\basicSimulation, then execute vlib work vcom *.vhd vmake > Makefile nmake modify one of the VHDL files and run nmake/make etc again. I would recommend you have a quick look at the vmap command as well as you might need it. Good luck, Hans. www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:14:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Fri, 29 Jul 2011 10:55:58 +0100 Organization: Parallel Points Lines: 17 Message-ID: References: <99dqncFsnU1@mid.individual.net> <99eakqFo0rU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net vz/yZxrWka9/m9mv7gPasQwyBk4fAvcYSrooiaQ6cxQKZhO9Q= Cancel-Lock: sha1:XtzvsmPJdk/nyO8psK/iZcjjoGc= sha1:uOhrOKTaBfCvLpO0Tv4oG2j9f4o= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5207 Mike Treseler writes: >> c) Something you'd find useful sometimes > > c) Yes, will be helpful in the near future. > Otherwise everyone will have a different library for it. > I'm not sure I follow Mike - library for what? The original question was about using Unicode within a VHDL source file (for example, variable names and comments). Or are you thinking of having a Unicode "string" replacement - which is a whole different ballgame, but one we maybe ought to think of also! Cheers, Martin From newsfish@newsfish Fri Feb 3 13:14:17 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!r18g2000vbs.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Fri, 29 Jul 2011 03:41:24 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <59f442ea-cd33-4d80-9ea6-7b4f8fc00e59@r18g2000vbs.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311936084 26579 127.0.0.1 (29 Jul 2011 10:41:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 10:41:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r18g2000vbs.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5208 On Jul 27, 7:23=A0pm, Benjamin Couillard wrote: > On 27 juil, 05:19, Zaid Al-Hilli wrote: > > > Hi all, > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) = / > > 8.5))); > > > Would you please help me in that? > > > Many thanks in advance... > > > Zaid > > One simple way would be to use a look-up table implemented in a ROM. > With "y" being the address and X being the data read at "y" address. > This solution would work well if the range of "y" in bits is smaller > or equal to 16 bits. If "y" is 32-bit wide then I don't think a look- > up table implemented in a FPGA-Rom will work. Thanks a lot! From newsfish@newsfish Fri Feb 3 13:14:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p19g2000yqa.googlegroups.com!not-for-mail From: Zaid Al-Hilli Newsgroups: comp.lang.vhdl Subject: Re: Exponential code in VHDL Date: Fri, 29 Jul 2011 03:41:57 -0700 (PDT) Organization: http://groups.google.com Lines: 26 Message-ID: <48b56b50-ad96-49e7-b784-d91a0fb11877@p19g2000yqa.googlegroups.com> References: <6ed03801-9a0e-4368-bdc0-57208e6d7d2a@y8g2000vba.googlegroups.com> NNTP-Posting-Host: 156.83.0.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1311936118 26839 127.0.0.1 (29 Jul 2011 10:41:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 29 Jul 2011 10:41:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p19g2000yqa.googlegroups.com; posting-host=156.83.0.157; posting-account=LM0U2goAAACleGp6JGa5rJniGZDMIzml User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5209 On Jul 27, 6:09=A0pm, Rob Gaddi wrote: > On 7/27/2011 2:19 AM, Zaid Al-Hilli wrote: > > > Hi all, > > > I am about implementing a VHDL code but I am facing problem, I have an > > exponential operation and I want to run that code op an FPGA board!! > > > Generally speaking the assignment is: =A0X =3D (1 / (1+ exp((y + 87.8) = / > > 8.5))); > > > Would you please help me in that? > > > Many thanks in advance... > > > Zaid > > Yeah, bound the range of y sufficiently that you can implement the > entire thing in a RAM lookup table. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Thanks a lot! From newsfish@newsfish Fri Feb 3 13:14:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Sat, 30 Jul 2011 00:58:13 -0700 Lines: 25 Message-ID: <99hrsqFfgaU1@mid.individual.net> References: <99dqncFsnU1@mid.individual.net> <99eakqFo0rU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net iDBVZKrbI5LAEQTVvfX+iQUIYUAbVwCEfLOt6jULkztok6ANfB Cancel-Lock: sha1:38dZ3xOSQ5J4uMmLUjTlCrpCPdM= User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5210 On 7/29/2011 2:55 AM, Martin Thompson wrote: > Mike Treseler writes: > >>> c) Something you'd find useful sometimes >> >> c) Yes, will be helpful in the near future. >> Otherwise everyone will have a different library for it. >> > > I'm not sure I follow Mike - library for what? The original question > was about using Unicode within a VHDL source file (for example, variable > names and comments). OK. In that case probably (b) for English speakers. > Or are you thinking of having a Unicode "string" replacement - which is > a whole different ballgame, but one we maybe ought to think of also! Yes, I was thinking strings. That seems safe and probably useful. Programming languages without Unicode strings built-in suffer as a result. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:14:18 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Monitoring inout signal transactions Date: Sat, 30 Jul 2011 13:03:14 +0300 Organization: A noiseless patient Spider Lines: 37 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 30 Jul 2011 10:03:28 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="26843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jNOhoRvdpGVarG3XhF2fIjCKOSJSWzT8=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 Cancel-Lock: sha1:iEGjCoEd3ZHPuuImo9yzMsYH8pY= Xref: feeder.eternal-september.org comp.lang.vhdl:5211 entity SPY is port (A : inout Std_Logic); end SPY; architecture ARCH of SPY is begin process begin report time'image(now) & ": a = " & std_logic'image(a); wait on a'transaction; end process; end architecture; architecture TB is signal A: std_logic; begin SPY_I: entity SPY(a) process begin wait for 1 fs; a <= 'Z'; wait for 1 ps; a <= '1'; wait for 5 ns; a <= '0'; wait for 20 ns; end process I do not drive the signal from the Spy, so output must be (U, Z, 1, 0). Right? Yet, simulator tells 'a = U' all four times! I observed this hacking the Zero-Ohm model. Ben Cohen temporarly assigns a and b to Z there. I do not understand why but that is a solution to get the normal output (U,Z,1,0). Another is to change port type inout -> in. Is is supposed VHDL behaviour? IMO, it is strange furthermore because I consider normal, architecture-declared signals, as inout because you can read and write them but no problem happens when the monitoring process is located within the same architecture that drives the signal rather than in a separate entity. From newsfish@newsfish Fri Feb 3 13:14:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!newsreader4.netcologne.de!news.netcologne.de!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!news-xxxfer.readnews.com!postnews.google.com!h4g2000vbw.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 30 Jul 2011 04:07:57 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <87ad8c30-e4c5-4ed9-80b0-e417d079288e@h4g2000vbw.googlegroups.com> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312024078 21639 127.0.0.1 (30 Jul 2011 11:07:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 30 Jul 2011 11:07:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h4g2000vbw.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5212 Hi Hans, I have tried to run the example. But when typing "vmake > Makefile" I get the error message: # The vmake utility must be run from a Unix shell or a Windows/DOS prompt. I am using Modelsim PE 10.0b Cheers, Hssig From newsfish@newsfish Fri Feb 3 13:14:19 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 30 Jul 2011 14:42:35 +0100 Organization: A noiseless patient Spider Lines: 23 Message-ID: <992837p9u8qvgpi5ms8vm06lfn65c7df5a@4ax.com> References: <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <7105a575-6370-4d67-bf65-b6c1f16c7f0c@fv14g2000vbb.googlegroups.com> <87ad8c30-e4c5-4ed9-80b0-e417d079288e@h4g2000vbw.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="32458"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/NEtrPeWSw+czlc6l7NZCfOWeZ6yF4wFQ=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:g5mr78W5hXjoJCvy9SH6ZoIFl+Q= Xref: feeder.eternal-september.org comp.lang.vhdl:5213 On Sat, 30 Jul 2011 04:07:57 -0700 (PDT), hssig wrote: >I have tried to run the example. But when typing "vmake > Makefile" I >get the error message: ># The vmake utility must be run from a Unix shell or a Windows/DOS >prompt. Well, it's hard to see how the error message could be any clearer :-) Obviously you're running from within ModelSim's GUI, or Tcl console. Fortunately Tcl comes to your rescue here: exec vmake > Makefile should do what you want. Of course, you *could* perhaps RTFM and run vmake directly from the command prompt... PS: exec is Tcl's command to run an external program. It does a pretty good job of faking-up the environment to fool the program into thinking it has been run from the DOS prompt. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sat, 30 Jul 2011 14:59:57 +0100 Organization: A noiseless patient Spider Lines: 43 Message-ID: <0i383714a24kf80143p3tcph945sdfqgef@4ax.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+Hw6EITjG1JWFqBk9RhgkZTpq9pSEMYBA=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:RxpNQWtyP0GvwnSAuJuTSKQcZw4= Xref: feeder.eternal-september.org comp.lang.vhdl:5214 On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer wrote: >I often use records within records, or records within records within >records, ad nausea. It's nice that I can currently do the following: > >A.A.A <= X; >A.A.B <= Y; >A.A.C <= Z; > >However, there's a lot of repetition in my code, so I often prefer the >following: > >A <= ( A => ( A => X, > B => Y, > C => Z ) ); > >The benefit is more noticeable with long and descriptive names for the >elements, but the problem is that if my intention is to set only the >A, B, and C leaf elements and leave any others unchanged it doesn't >seem possible. How about an alias? alias AA: ABC_record_type is A.A; ... AA.A <= X; Doesn't quite do what you asked for (I don't think that's possible) but it does simplify the naming problem somewhat. Functions and procedures might be useful too: procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is begin T.A <= X; ... end; ... tweakJustTheLeafParts(A.A); -- does A.A.A <= X; Watch out for multiple drivers, though, as Rob Gaddi points out. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:20 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is Partial Record Assignment Possible? Date: Sat, 30 Jul 2011 15:01:13 +0100 Organization: A noiseless patient Spider Lines: 46 Message-ID: References: <0i383714a24kf80143p3tcph945sdfqgef@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vB4ZMw9nHfDcC82jGk9Ze8/kj5vcEoAI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:1BfQQJYrD0aB9g5oKS4FiThS5LY= Xref: feeder.eternal-september.org comp.lang.vhdl:5215 On Sat, 30 Jul 2011 14:59:57 +0100, Jonathan Bromley .... sent a long-dead post by mistake. Sorry, please ignore. >On Fri, 6 Aug 2010 10:34:38 -0700 (PDT), Sudoer > wrote: > >>I often use records within records, or records within records within >>records, ad nausea. It's nice that I can currently do the following: >> >>A.A.A <= X; >>A.A.B <= Y; >>A.A.C <= Z; >> >>However, there's a lot of repetition in my code, so I often prefer the >>following: >> >>A <= ( A => ( A => X, >> B => Y, >> C => Z ) ); >> >>The benefit is more noticeable with long and descriptive names for the >>elements, but the problem is that if my intention is to set only the >>A, B, and C leaf elements and leave any others unchanged it doesn't >>seem possible. > >How about an alias? > > alias AA: ABC_record_type is A.A; > ... > AA.A <= X; > >Doesn't quite do what you asked for (I don't think that's >possible) but it does simplify the naming problem somewhat. > >Functions and procedures might be useful too: > procedure tweakJustTheLeafParts(signal T: inout ABC_record_type) is > begin > T.A <= X; > ... > end; > ... > tweakJustTheLeafParts(A.A); -- does A.A.A <= X; > >Watch out for multiple drivers, though, as Rob Gaddi points out. From newsfish@newsfish Fri Feb 3 13:14:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Sat, 30 Jul 2011 15:04:40 +0100 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="6137"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/81G+NraD2NXqwdQ8Xqs3nyWaILUSN3vI=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:DBz2FJ0D7ZTqJCCWZViSd8Jm4X0= Xref: feeder.eternal-september.org comp.lang.vhdl:5216 On 28 Jul 2011 19:13:48 GMT, Martin Thompson wrote: >Hi all, > >I'm asking for a bit of input from the community... > >As the title says, would you find it of use to allow Unicode identifiers >and comments in a future VHDL revision? I'm not sure I see any use for it. What do you have in mind? Unicode *strings* and file-IO might well be useful, but I guess that's a very different story. A new type, either built-in or in std.standard, for Unicode *characters* would be a good start. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Newsgroups: comp.lang.vhdl Subject: Re: Monitoring inout signal transactions Date: Sat, 30 Jul 2011 15:49:05 +0000 (UTC) Organization: void Lines: 45 Message-ID: References: NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1312040945 585 192.168.128.1 (30 Jul 2011 15:49:05 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Sat, 30 Jul 2011 15:49:05 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5217 valtih1978 wrote: > entity SPY is > port (A : inout Std_Logic); > end SPY; > > architecture ARCH of SPY is > begin > > process begin > report time'image(now) & ": a = " & std_logic'image(a); > wait on a'transaction; > end process; > > end architecture; > > > architecture TB is > signal A: std_logic; > begin > SPY_I: entity SPY(a) > process begin > wait for 1 fs; > a <= 'Z'; wait for 1 ps; > a <= '1'; wait for 5 ns; > a <= '0'; wait for 20 ns; > end process > > I do not drive the signal from the Spy, so output must be (U, Z, 1, 0). > Right? Yet, simulator tells 'a = U' all four times! Signal A in the Testbench TB has multiple sources[1]: spy's inout port and the driver from the process in the testbench. The inout source from spy is initialized with 'U' by default. That 'U' overdrives the other assignments like usual. If you initialize the inout port using 'Z', spy will report the values assigned by the testbench process. ... port (A: inout std_logic := 'Z'); ... [1]: LRM(93) 4.3.1.2 line 183 Enrik From newsfish@newsfish Fri Feb 3 13:14:21 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Mon, 01 Aug 2011 09:58:21 +0100 Organization: TRW Conekt Lines: 42 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Trace: individual.net t34vnpKcwg6m/3STJrI7qgWd+Q49rpKMjc28OFtsGrul7V8bg= Cancel-Lock: sha1:bh3chlQM3sT03WRzapj/IB5uPio= sha1:q9tAzFkwLk8hdVzrh8t/S2fi+CQ= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5218 Jonathan Bromley writes: > On 28 Jul 2011 19:13:48 GMT, Martin Thompson > wrote: > >>Hi all, >> >>I'm asking for a bit of input from the community... >> >>As the title says, would you find it of use to allow Unicode identifiers >>and comments in a future VHDL revision? > > I'm not sure I see any use for it. What do you have in mind? > The original question was asked without much in mind beyond allowing you to call a variable 'chteau' (to pull an example from the other end of the scale spectrum to our usual fare here :) > Unicode *strings* and file-IO might well be useful, but > I guess that's a very different story. A new type, either > built-in or in std.standard, for Unicode *characters* would > be a good start. >From other comments, Unicode strings appear to be of much more value than Unicode identifiers and comments. Although once you allow Unicode strings in a source file, you've opened the "source-file encoding" can of worms already, and then (I believe) allowing Unicode in comments becomes easy. Unicode identifiers may have some negative impact of parsing efficiency? In which case, as you say, W_CHARACTER here we (might) come. However, it also sounds like a large (huge?) amount of work which *may* be better spent elsewhere. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:14:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Mon, 01 Aug 2011 11:03:01 +0100 Organization: A noiseless patient Spider Lines: 15 Message-ID: <06uc379imelvn6oc6dp66avibm5ki8eukk@4ax.com> References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="13803"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19s6+12bWhn7/8HLXlLVAL+F9Svawf0Gd0=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:c0i+0AKilkQGDeEAsrn0iRjfHZA= Xref: feeder.eternal-september.org comp.lang.vhdl:5219 On Mon, 01 Aug 2011 09:58:21 +0100, Martin Thompson wrote: >The original question was asked without much in mind beyond >allowing you to call a variable 'chteau' C'est tout possible de faire son logiciel sans aucun accent :-) >it also sounds like a large (huge?) amount of work which >*may* be better spent elsewhere. I think I tend to agree. The EDA industry as a whole is irremediably Anglophone, and muddles through pretty well without internationalization. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:22 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed.straub-nv.de!news-1.dfn.de!news.dfn.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Tue, 02 Aug 2011 11:50:01 +0100 Organization: TRW Conekt Lines: 19 Message-ID: References: <99dqncFsnU1@mid.individual.net> <06uc379imelvn6oc6dp66avibm5ki8eukk@4ax.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net utlvgH2YKRwQx4p/iryemghQaFxkWbMVEUcwps+psB/5rCegU= Cancel-Lock: sha1:H2Ckq/1eXI/O/bgSQcVH66a6q4M= sha1:RNxQol+6A6G85q69Z93aBEMaROM= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5220 Jonathan Bromley writes: > The EDA industry as a whole is > irremediably Anglophone, I like that description :) > and muddles through pretty well > without internationalization. and likely will continue to do so! Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:14:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Tue, 02 Aug 2011 14:38:49 +0300 Organization: A noiseless patient Spider Lines: 18 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 2 Aug 2011 11:38:50 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="21297"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18kIW/iKKvNWlvQ/FsZoh4Xak7AqeArRrM=" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 In-Reply-To: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> Cancel-Lock: sha1:YAyjYeOhwQVuidsVmHdRDiQ1lr8= Xref: feeder.eternal-september.org comp.lang.vhdl:5221 This is fine. But have you seen how it works? Given process begin c <= '1'; wait for 3 ns; c <= '0'; wait for 3 ns; c <= '1'; wait for 3 ns; end process; a <= c; I: entity ZeroOhm port map(a, b); it produces https://lh4.googleusercontent.com/-grNH7UAwVBw/Tjfe1819oII/AAAAAAAAADs/3jX6VMhFojA/s800/0ohm.png The problem is those transitions of the order of the delays. That is, listeners will not see your signal if the clock period is the same order as the line delay. Though, the bus driver may produce a perfect signal. From newsfish@newsfish Fri Feb 3 13:14:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: =?UTF-8?Q?Nicholas_Collin_Paul_de_Glouce=C5=BFter?= Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Fri, 5 Aug 2011 18:20:35 +0000 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <99dqncFsnU1@mid.individual.net> Mime-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="8323328-894931490-1312568451=:3551" Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="549"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+jPPPYLtUxjbe0YlO/Qnb8nBRf7rZBQVpoluxFFtUEvA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <99dqncFsnU1@mid.individual.net> Cancel-Lock: sha1:BGXnoH1IPuXLF2oOT0lz+iKF7mQ= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:5222 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-894931490-1312568451=:3551 Content-Type: TEXT/PLAIN; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Martin Thompson sent on July 28th, 2011: |-------------------------------------------------------------------------| |"Hi all, | | | |I'm asking for a bit of input from the community... | | | |As the title says, would you find it of use to allow Unicode identifiers | |and comments in a future VHDL revision? | | | |Would this be: | |a) Something VHDL should not allow | |b) Something that doesn't bother you either way | |c) Something you'd find useful sometimes | |d) Something you'd make use of all the time | |e) Something that you'd switch away from SystemVerilog just to get at | | (maybe I'm asking the wrong crowd for that :) | | | |Thanks, | |Martin | | | |-- | |http://parallelpoints.com/ " | |-------------------------------------------------------------------------| Hi Mr. Thompson, I respond more to point out that Unicode support in actual source code (such as identifiers) was added to Ada and one of the compiler developers which added this support remarked that it was not worth the hassle. Anyhow, as for my own voting: c) or maybe even d). Back to the issue of hassle in the real World though, there is a valid argument for a) because many tools such as text editors and terminals are still screwing up Unicode (such as UTF-8 versus UTF-7) years after it was introduced. Almost nothing around screws up ASCII (aside from CR and LF issues). Regards, Nicholas Collin Paul de Glouce=C5=BFter in Unicode (you asked for it) --8323328-894931490-1312568451=:3551-- From newsfish@newsfish Fri Feb 3 13:14:23 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!p5g2000vbl.googlegroups.com!not-for-mail From: fearg Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Fri, 5 Aug 2011 10:52:38 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: References: <8d63fee4-1d07-4066-8534-29eac6de7a38@p20g2000yqp.googlegroups.com> <05079553-9b34-40cb-a879-d4918cc70b6f@o4g2000vbv.googlegroups.com> <9973q0Fvb9U1@mid.individual.net> NNTP-Posting-Host: 212.129.66.131 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312566758 1429 127.0.0.1 (5 Aug 2011 17:52:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 5 Aug 2011 17:52:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p5g2000vbl.googlegroups.com; posting-host=212.129.66.131; posting-account=w-YNLwoAAAC2SICo0QpTgmGHNmTX2E5x User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5223 Al, thankyou for the suggestions. Please excuse the delay in replying. I've been on vacation. I will try the emacs solution. Also, since I plan to replicate the original design and modify the copy as described, the global signal suggestion may be be useful. regards, Fearghal From newsfish@newsfish Fri Feb 3 13:14:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!f20g2000yqm.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: help with binary decoder Date: Sat, 6 Aug 2011 10:33:43 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <059c7662-2449-4f35-b944-53555ef39aa7@f20g2000yqm.googlegroups.com> NNTP-Posting-Host: 90.148.52.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312652122 28027 127.0.0.1 (6 Aug 2011 17:35:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Aug 2011 17:35:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f20g2000yqm.googlegroups.com; posting-host=90.148.52.225; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5224 hi all; i have this code for a 5-bits binary counter : LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY counter IS PORT ( count : OUT unsigned (4 DOWNTO 0); load : IN STD_LOGIC; pre :IN unsigned (4 DOWNTO 0); Clk : IN STD_LOGIC); END counter; ARCHITECTURE Behavioral OF counter IS SIGNAL c : unsigned(4 DOWNTO 0) := "00000"; BEGIN count <= c; PROCESS(Clk) BEGIN IF( rising_edge(Clk) ) THEN IF(load = '1') THEN c <= pre; ELSE c <= c + 1; END IF; END IF; END PROCESS; END Behavioral; I want to connect the output to a binary decoder that shows the state of the counter how can i do that? can any one help me plz From newsfish@newsfish Fri Feb 3 13:14:24 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a31g2000vbt.googlegroups.com!not-for-mail From: majmoat_ensan Newsgroups: comp.lang.vhdl Subject: help with binary decoder Date: Sat, 6 Aug 2011 10:38:26 -0700 (PDT) Organization: http://groups.google.com Lines: 37 Message-ID: <53dec8e3-9712-499f-948b-c490600de36f@a31g2000vbt.googlegroups.com> NNTP-Posting-Host: 90.148.52.225 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312652426 30814 127.0.0.1 (6 Aug 2011 17:40:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 6 Aug 2011 17:40:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a31g2000vbt.googlegroups.com; posting-host=90.148.52.225; posting-account=-OOGzgoAAABEh5fDaYutd4PwFaBQpeUI User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.0) AppleWebKit/534.30 (KHTML, like Gecko) Chrome/12.0.742.122 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5225 hi all; i have this code for a 5-bits binary counter : LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY counter IS PORT ( count : OUT unsigned (4 DOWNTO 0); load : IN STD_LOGIC; pre :IN unsigned (4 DOWNTO 0); Clk : IN STD_LOGIC); END counter; ARCHITECTURE Behavioral OF counter IS SIGNAL c : unsigned(4 DOWNTO 0) := "00000"; BEGIN count <= c; PROCESS(Clk) BEGIN IF( rising_edge(Clk) ) THEN IF(load = '1') THEN c <= pre; ELSE c <= c + 1; END IF; END IF; END PROCESS; END Behavioral; I want to connect the output to a binary decoder that shows the state of the counter how can i do that? can any one help me plz From newsfish@newsfish Fri Feb 3 13:14:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!gegeweb.org!news.glorb.com!postnews.google.com!p20g2000yqp.googlegroups.com!not-for-mail From: Hendrik Eeckhaut Newsgroups: comp.lang.vhdl Subject: Re: automating bringing of signals in hierarchical VHDL model to top level entity Date: Mon, 8 Aug 2011 01:37:57 -0700 (PDT) Organization: http://groups.google.com Lines: 41 Message-ID: References: NNTP-Posting-Host: 195.144.71.15 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1312792678 31427 127.0.0.1 (8 Aug 2011 08:37:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 08:37:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p20g2000yqp.googlegroups.com; posting-host=195.144.71.15; posting-account=fhflvgoAAAAsi8MNddt9P71xOtFYaqiV User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/534.24 (KHTML, like Gecko) Chrome/11.0.696.57 Safari/534.24,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5226 On Jul 21, 12:09=A0am, fearg wrote: > Hi, I=92d be grateful if anyone could advise on whether an application > is available to do the following for VHDL models. > Fearghal > > 1. =A0 =A0 =A0Make a replica copy of a selected multi-file and hierarchic= al VHDL > design > 2. =A0 =A0 =A0Modify each VHDL file in the copied hierarchical VHDL model > (possibly using the make file sequence), in order to bring all (or > selected) signals to the top level VHDL entity. > 3. =A0 =A0 =A0Steps: > a. =A0 =A0 =A0modify each VHDL files in turn to bring every (or selected) > internal signal as an output signals in VHDL entity > b. =A0 =A0 =A0Modify the associated component declarations within package= files > to reflect the modified entity ports > c. =A0 =A0 =A0Rebuild the VHDL hierarchy adding the new output ports to a= ll > entities in the hierarchy > d. =A0 =A0 =A0Modify all port map assignments to mirror the extended enti= ty > ports. > > My application requires interpreting any existing VHDL model, > selecting signals from within the VHDL model to bring to the top level > entity in order to connect to a series of display devices. I do not > wish to modify the underlying VHDL code. Seems like you need a powerful VHDL refactoring tool. Sigasi HDT (http://www.sigasi.com/sigasi-hdt) does not completely automate the transformation you describe, but it will definitely help you avoid errors and will save you a lot of time. With Sigasi you can easily add ports and keep your complete design hierarchy consistent. If you are a student you can get an educational license, otherwise you can download a 4-week trial via http://www.sigasi.com/user/register Regards, Hendrik. From newsfish@newsfish Fri Feb 3 13:14:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!195.114.241.69.MISMATCH!feeder.news-service.com!postnews.google.com!en1g2000vbb.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: PSL book suggestions Date: Mon, 8 Aug 2011 07:44:47 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.200.65.239 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312814773 26996 127.0.0.1 (8 Aug 2011 14:46:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 14:46:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: en1g2000vbb.googlegroups.com; posting-host=194.200.65.239; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-HTTP-Via: 1.1 IMGKLISA1 X-Google-Web-Client: true X-Google-Header-Order: VCRUHALSNK X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18 GTB7.1 ( .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5227 All We are just starting to implement PSL assertions for our VHDL IP code. Just wondered, if any one has any suggestions for relevant PSL books to act as tutorial/reference? I have managed to download a fair amount of documents on PSL assertions from the Web and have written some simple assertions. I am aware of the Ben Cohen book on PSL/Sugar and would be interested on any reviews on this book. Thanks in advance JO From newsfish@newsfish Fri Feb 3 13:14:25 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Colin Paul Gloster Newsgroups: comp.lang.vhdl Subject: Re: PSL book suggestions Date: Mon, 8 Aug 2011 19:15:01 +0000 Organization: A noiseless patient Spider Lines: 16 Message-ID: References: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Injection-Info: mx04.eternal-september.org; posting-host="kheEuXGHhE2Z5eF1gAST+A"; logging-data="30323"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/L5MJBuXagTwhBFu327S/wq+A23DG5TN8AEHpChke9QA==" User-Agent: Alpine 2.00 (LNX 1167 2008-08-23) In-Reply-To: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> Cancel-Lock: sha1:74dq5qaoyX9SpJUYPkh/FLCeaew= X-X-Sender: Colin_Paul@Bluewhite64.example.net Xref: feeder.eternal-september.org comp.lang.vhdl:5228 JO sent on August 8th, 2011: |-----------------------------------------------------------------------| |"We are just starting to implement PSL assertions for our VHDL IP code.| | | |Just wondered, if any one has any suggestions for relevant PSL books | |to act as tutorial/reference? I have managed to download a fair amount | |of documents on PSL assertions from the Web and have written some | |simple assertions. | | | |I am aware of the Ben Cohen book on PSL/Sugar and would be interested | |on any reviews on this book." | |-----------------------------------------------------------------------| I have not read that particular book but I have read other things by Ben Cohen. He is a very good author. From newsfish@newsfish Fri Feb 3 13:14:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!n35g2000yqf.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: PSL assertion book suggestion Date: Mon, 8 Aug 2011 13:25:45 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <84fe67b1-9bf0-43bc-8a83-f0a524f6b083@n35g2000yqf.googlegroups.com> NNTP-Posting-Host: 86.163.47.141 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1312835269 8562 127.0.0.1 (8 Aug 2011 20:27:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 8 Aug 2011 20:27:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n35g2000yqf.googlegroups.com; posting-host=86.163.47.141; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-GB; rv:1.9.2.18) Gecko/20110614 Firefox/3.6.18,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5229 Hi All We have started using PSL assertins for our VHDL IP. I have downloadded some material from Google search and have written a small number of assertions. I wondered if any one has any suggestions for books to act as a more advanced tutorial/reference om PSL assertions. The google search pointef me to Ben Cohens' book on PSL/Sugar. I wonder if any one has used this book and if so have any comments on it. Thanks in advance JO From newsfish@newsfish Fri Feb 3 13:14:26 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!news.belwue.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: PSL book suggestions Date: Wed, 10 Aug 2011 14:54:28 +0200 Organization: InterNetNews at News.BelWue.DE (Stuttgart, Germany) Lines: 34 Message-ID: References: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> NNTP-Posting-Host: creonic.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.belwue.de 1312980869 14918 131.246.218.4 (10 Aug 2011 12:54:29 GMT) X-Complaints-To: news@news.belwue.de NNTP-Posting-Date: Wed, 10 Aug 2011 12:54:29 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.18) Gecko/20110617 Lightning/1.0b2 Thunderbird/3.1.11 In-Reply-To: <971ab531-ce37-4675-84ef-381662d69fcc@en1g2000vbb.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:5230 Hi, I have been working with "A Practical Introduction to PSL" from Cindy Eisner and Dana Fisman. It contains plenty of examples for the single PSL operators. The only drawback for us was that the presented high-level-assertions are currently not supported by our simulator (RivieraPro). But it seems Aldec is working on that. An additional chapter with real-world examples would have been nice though. Regards, Matthias Am 08.08.2011 16:44, schrieb thunder: > All > > We are just starting to implement PSL assertions for our VHDL IP code. > > Just wondered, if any one has any suggestions for relevant PSL books > to act as tutorial/reference? I have managed to download a fair amount > of documents on PSL assertions from the Web and have written some > simple assertions. > > I am aware of the Ben Cohen book on PSL/Sugar and would be interested > on any reviews on this book. > > > Thanks in advance > > > JO From newsfish@newsfish Fri Feb 3 13:14:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!q1g2000vbj.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Wed, 10 Aug 2011 18:31:24 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1313026383 15589 127.0.0.1 (11 Aug 2011 01:33:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 11 Aug 2011 01:33:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q1g2000vbj.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5231 On Aug 2, 7:38=A0am, valtih1978 wrote: > This is fine. But have you seen how it works? > > Given > =A0 =A0 =A0 =A0 process begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 c <=3D '1'; wait for 3 ns; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 c <=3D '0'; wait for 3 ns; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 c <=3D '1'; wait for 3 ns; > =A0 =A0 =A0 =A0 end process; > =A0 =A0 =A0 =A0 a <=3D c; > =A0 =A0 =A0 =A0 I: entity ZeroOhm port map(a, b); > > it produces > > https://lh4.googleusercontent.com/-grNH7UAwVBw/Tjfe1819oII/AAAAAAAAAD... > > The problem is those transitions of the order of the delays. That is, > listeners will not see your signal if the clock period is the same order > as the line delay. Though, the bus driver may produce a perfect signal. This isn't a problem with the VHDL model of a delay, it's a problem with the design. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed3.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 11 Aug 2011 14:48:02 +0300 Lines: 11 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: pepper.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1313063282 24080 2001:708:310:3430:203:baff:fe7d:42dd (11 Aug 2011 11:48:02 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Thu, 11 Aug 2011 11:48:02 +0000 (UTC) User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/21.3 (usg-unix-v) Cancel-Lock: sha1:E2JKwC1FJOL+x+5wlo6Qp142L7c= Xref: feeder.eternal-september.org comp.lang.vhdl:5232 Paul Uiterlinden writes: > I use both vmake and vmk. Now that we're on the topic, what's a good make tool to use with vmake on Windows? Gnu make included in Cygwin doesn't seem to like the generated makefiles... I've been using make from unxutils, but it seems to have a problem with time and imagines my files have a modification time in the future and so on. It works, though. From newsfish@newsfish Fri Feb 3 13:14:27 2012 Path: mx04.eternal-september.org!eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.n-ix.net!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Enrik Berkhan Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Thu, 11 Aug 2011 13:36:51 +0000 (UTC) Organization: void Lines: 9 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1313069811 4702 192.168.128.1 (11 Aug 2011 13:36:51 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Thu, 11 Aug 2011 13:36:51 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5233 Anssi Saari wrote: > > Now that we're on the topic, what's a good make tool to use with vmake > on Windows? Gnu make included in Cygwin doesn't seem to like the > generated makefiles... Have you tried vmake's `-cygdrive' (IIRC) command line option? Enrik From newsfish@newsfish Fri Feb 3 13:14:28 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Fri, 12 Aug 2011 11:28:17 +0300 Lines: 29 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: pepper.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1313137697 30784 2001:708:310:3430:203:baff:fe7d:42dd (12 Aug 2011 08:28:17 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Fri, 12 Aug 2011 08:28:17 +0000 (UTC) User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/21.3 (usg-unix-v) Cancel-Lock: sha1:VywxBONpW3bS5x6wMUievO6tpgM= Xref: feeder.eternal-september.org comp.lang.vhdl:5234 Enrik Berkhan writes: > Anssi Saari wrote: >> >> Now that we're on the topic, what's a good make tool to use with vmake >> on Windows? Gnu make included in Cygwin doesn't seem to like the >> generated makefiles... > > Have you tried vmake's `-cygdrive' (IIRC) command line option? I take it that option is either new or non-existing? I'm using Modelsim 6.5 and 6.6. The specific error message from Gnu Make 3.81 in Cygwin is Makefile:153: *** multiple target patterns. Stop. On line 153 and onwards I have: $(WORK__altera_tb) \ $(WORK__altera_tb__behavior) : altera_tb.vhd \ $(IEEE__std_logic_1164) $(VCOM) -93 -O0 altera_tb.vhd Anyways, looks like I stumbled on a working make: GNU Make 3.82 Built for i386-pc-mingw32 I.e. the one included with mingw. From newsfish@newsfish Fri Feb 3 13:14:28 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!xlned.com!feeder5.xlned.com!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e44ffea$0$23840$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Newsgroups: comp.lang.vhdl Date: Fri, 12 Aug 2011 12:26:50 +0200 References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 15 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1313144810 news2.news.xs4all.nl 23840 puiterl/195.242.97.150:58900 Xref: feeder.eternal-september.org comp.lang.vhdl:5235 Anssi Saari wrote: > Paul Uiterlinden writes: > >> I use both vmake and vmk. > > Now that we're on the topic, what's a good make tool to use with vmake > on Windows? Sorry, I don't know. I don't use Windows. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:14:29 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.swapon.de!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Fri, 12 Aug 2011 17:52:47 +0200 Lines: 22 Message-ID: <9al0ifF23kU1@mid.uni-berlin.de> References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de hTTTvRj+Rbf9S0opO4ATEQyvo5CwTIGhqKuNmNM28rO7748FU= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.18) Gecko/20110616 Thunderbird/3.1.11 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5236 On 12.08.11 10:28, wrote Anssi Saari: > The specific error message from Gnu Make 3.81 in Cygwin is > Makefile:153: *** multiple target patterns. Stop. > > On line 153 and onwards I have: > > $(WORK__altera_tb) \ > $(WORK__altera_tb__behavior) : altera_tb.vhd \ > $(IEEE__std_logic_1164) > $(VCOM) -93 -O0 altera_tb.vhd There is a ":" in $(IEEE__std_logic_1164), right? > Anyways, looks like I stumbled on a working make: > > GNU Make 3.82 > Built for i386-pc-mingw32 > > I.e. the one included with mingw. Make 3.80 should also work with DOS-colons in path names. regards, Bart From newsfish@newsfish Fri Feb 3 13:14:29 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Enrik Berkhan Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 13 Aug 2011 17:13:23 +0000 (UTC) Organization: void Lines: 39 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1313255603 24959 192.168.128.1 (13 Aug 2011 17:13:23 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Sat, 13 Aug 2011 17:13:23 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5237 Anssi Saari wrote: > Enrik Berkhan writes: >> Have you tried vmake's `-cygdrive' (IIRC) command line option? > > I take it that option is either new or non-existing? I'm using > Modelsim 6.5 and 6.6. I'm using an Altera Modelsim ASE OEM version, obviously based on 6.6d. The header line in the generated Makefiles says 'vmake 2.2'. $ vmake -h Usage: vmake -help vmake [-fullsrcpath] [-cygdrive] [-nolinewrap] [-f ] [-ignore ] [-du ] [] [> on Windows 7. Without `-cygdrive', vmake genrates something like this: ... LIB_IEEE = C:/altera/11.0/modelsim_ase/win32aloem/../ieee ... This variable introduces the spurious colon in the rules when expanded, leading to the error you described. With `-cygdrive', the line reads: ... LIB_IEEE = /cygdrive/c/altera/11.0/modelsim_ase/win32aloem/../ieee ... and everything will work fine with make under Cygwin. What vmake does not handle correctly though are path names containing spaces. Enrik From newsfish@newsfish Fri Feb 3 13:14:30 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a17g2000yqk.googlegroups.com!not-for-mail From: ttsmnl@yahoo.com Newsgroups: comp.lang.vhdl Subject: Testbench\Package Signal Visibility Date: Sat, 13 Aug 2011 16:07:58 -0700 (PDT) Organization: http://groups.google.com Lines: 103 Message-ID: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> NNTP-Posting-Host: 128.170.224.11 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1313276878 21730 127.0.0.1 (13 Aug 2011 23:07:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 13 Aug 2011 23:07:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a17g2000yqk.googlegroups.com; posting-host=128.170.224.11; posting-account=Tk_SggkAAAC5vmgfB7Xu3xZv2-esveRO User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.9.0.10636) X-Google-Web-Client: true X-Google-Header-Order: AELNKCHRUV X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5238 First thanks for the input. Somewhat new to VHDL. I hope I can protray my question easily enough to get a quick accurate answer. I have a testbench which has multiple large procedures. I have these repeated in many testbenches which is inefficient and not neat. These procedures "take in" many (>50) signals and vectors when inititiated from my testbench stimulus. The procedure declaration may define just one input, however the procedure will "take in" and execute a large testbench signal set as it is defined at that time. This large signal set is not required as part of the procedure decleration signal set, since they are all visible within the testbench. Below is a brief example in text which I hope helps instead of displaying my huge example. procedure SIMULATE_GPS_IN ( signal SIM_SESSION : in string(1 to 10) ) begin ---- in this procedure, many many sigals and vectors are being utilized. However since they are all in the tesbench ---- they are visible, and don't have to be passed into the procedure as part of the declaration statement ---- like the "SIM_SESSION" input string shown above. end SIMULATE_GPS_IN; STIMULUS : process reset <= '0' ; wait for 10us; reset <= '1' ; -- Test #1 A <= "0010"; B <= '1'; C <= X"1234"; -- these signals are viewed ("taken in") by the procedure wait for 1us; SIMULATE_GPS_IN (3); -- invoking procedure -- add self checking tests here. -- Test #2 A <= "1000"; B <= '0'; C <= X"3421"; -- these signals are viewed ("taken in") by the procedure wait for 1us; SIMULATE_GPS_IN (2); -- invoking procedure -- add self checking tests here. -- Test #3 A <= "1111"; -- these signals are viewed ("taken in") by the procedure (using B, C's previous stimulus values) wait for 1us; SIMULATE_GPS_IN (7); -- invoking procedure -- add self checking tests here. end process; Now for my question: The signals A, B, and C are utilized (read) by the procedure when invoked. This all works great. Now when I switch to a composite package and place all procedures within; can I still pass just one variable into the package (and thus into the procedure within the package), or do I now have to pass A, B, and C along with the SIM_SESSION string value in the procedure call. Again my signal set is huge, so when implemented inside the testbench (without a package), the simulation portion of the testbench is very neat and easy to read (not cluttered with each individual signal). But again, it is not very neat to repeat every procedure in every testbench. If I can not make the signals available (global) to the package, then I will have to change my procedures to look like this. procedure SIMULATE_GPS_IN ( signal A : in std_logic; signal B : in std_logic_vector(31 downto 0); signal C : in std_logic_vector(31 downto 0); signal SIM_SESSION : in string(1 to 10) ) begin ------ logic , ...................... end SIMULATE_GPS_IN; STIMULUS : process reset <= '0' ; wait for 10us; reset <= '1' ; -- Test #1 wait for 1us; SIMULATE_GPS_IN (A, B, C, 3); -- invoking procedure with all data signals which are utilized to execute logic. -- add self checking tests here. ..... ..... end process; I am trying to avoid making huge procedure declarations. If I have to then I can't preserve the "neatness" of the testbench style when not using a package. I HOPE that all makes sense. I believe it is a pretty straight forward issue, but I just can't figure out how (or if) I can make all the signals globally visible to the package without passing them through huge procedure calls. Again (ahead of time) thanks to you experts out there!! From newsfish@newsfish Fri Feb 3 13:14:30 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!d7g2000vbv.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Testbench\Package Signal Visibility Date: Sun, 14 Aug 2011 00:48:31 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <50e1810b-6508-425f-800c-8e37936cdee7@d7g2000vbv.googlegroups.com> References: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> NNTP-Posting-Host: 213.104.217.142 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1313308111 16567 127.0.0.1 (14 Aug 2011 07:48:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Aug 2011 07:48:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d7g2000vbv.googlegroups.com; posting-host=213.104.217.142; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:5.0) Gecko/20100101 Firefox/5.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5239 Putting signals inside a package is perfectly legal VHDL, but dont try and synthesise it. It is not good practice and at least one vendor (Altera) just refuses to compile them. With your procedures, personally I would like to see the declaration have all the ins/outs rather than randomly accessing signals internally - it makes it more self contained and a bit clearer whats going on. And instead of having one big procedure, why not break it up into several smaller procedures, then it would be clearer to another user what was going on: eg: GPS_INIT(a,b,c); GPS_DO_STUFF(a,b,c); GPS_SHUTDOWN(a,b,c); From newsfish@newsfish Fri Feb 3 13:14:31 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Sun, 14 Aug 2011 10:57:04 +0300 Organization: A noiseless patient Spider Lines: 1 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 14 Aug 2011 07:57:13 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="6065"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX196q/QVDd3vS27mw3xnmPOWr19uoS/4P1Q=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Cancel-Lock: sha1:6YPgpZ1ictzoC3/c3GHjYfMkrrA= Xref: feeder.eternal-september.org comp.lang.vhdl:5240 What is wrong with my "design"? From newsfish@newsfish Fri Feb 3 13:14:31 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Testbench\Package Signal Visibility Date: Sun, 14 Aug 2011 11:22:58 +0100 Organization: A noiseless patient Spider Lines: 116 Message-ID: References: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="17924"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/de7D/SlgW+pkvp6iJMYaGTFIVxK1EWj8=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:jCxa2zEFtjy6ZZl+waoUWJN6CsQ= Xref: feeder.eternal-september.org comp.lang.vhdl:5241 On Sat, 13 Aug 2011 16:07:58 -0700 (PDT), ttsmnl@yahoo.com wrote: >First thanks for the input. Somewhat new to VHDL. I hope I can protray >my question easily enough to get a quick accurate answer. > >I have a testbench which has multiple large procedures. I have these >repeated in many testbenches which is inefficient and not neat. These >procedures "take in" many (>50) signals and vectors when inititiated >from my testbench stimulus. The procedure declaration may define just >one input, however the procedure will "take in" and execute a large >testbench signal set as it is defined at that time. This large signal >set is not required as part of the procedure decleration signal set, >since they are all visible within the testbench. This is a fairly standard problem so I hope the group will excuse me if I repeat my standard solution, which has appeared here before. As you suspected, moving the procedures into a package is: 1) A Very Good Idea - because it avoids all that copy-paste and gives you a block of code that you can simply import into future testbench projects; 2) A Darned Nuisance - because you now must pass all the relevant testbench signals to your procedures as explicit arguments. The explicit argument list is not a problem in the package itself; in fact it's a pretty good idea, because it forces you to design and document the procedure's signal interface clearly in the code itself. The problem comes when you try to *use* the procedure in your testbench, because EVERY time you need to call it you must pass in a huge pile of signals as arguments. All this you know already. Luckily there is a reasonably clean way out. Before starting, though, let me repeat something that you have already clearly understood: There are two distinct kinds of argument (parameter) to this sort of procedure. First there are the signals, usually defined in the testbench, that represent some bus or interface to the DUT. EVERY TIME you call the procedure, you must pass this same set of signals to it. Secondly, there are the arguments that decide how THIS SPECIFIC RUN of the procedure will do its work. With that in mind, let's run a super-simple example that illustrates the principles: a procedure to generate a pulse on some signal. Here it is, in a package (just the body, for brevity): package body pulsegen_pkg is --- Generate a pulse on any signal S. procedure pulse ( duration: in time; --- This run's behaviour signal S: inout std_logic --- Which signal to hit ) is begin S <= '1'; wait for duration; S <= '0'; end; end package body pulsegen_pkg; Now let's move into the testbench. use work.pulsegen_pkg.all; architecture TB of my_testbench is signal test: std_logic; begin test_driver: process --- Here's the important bit. Redeclare --- a new version of your pulse procedure. --- It simply specializes the package's --- procedure so that it works on my --- chosen signal. procedure pulse (duration: in time) is begin pulse(duration, test); end; begin test <= '0'; pulse(20 ns); --- Much easier. Pulses 'test'. wait for 200 ns; pulse(30 ns); ... end process; end architecture TB; This seems to me to be the best of both worlds: - you have the procedure in a package where it belongs - you have clearly documented, in the testbench code, the set of signals that the proc will manipulate - each call to the procedure now has only the "what's different this time" arguments; the set of signals it uses is predefined by the process's version of the procedure Of course, it's your choice whether you use the same name for the procedure or a completely different name. If your set of signals is some big complicated bus structure, and you call bus read and write procedures many times during a testbench process, this approach can be a really big benefit. The package procedure is totally re-usable - you can bring it into any testbench, any time in the future, without copy/paste - but unfortunately it is necessary to rewrite the "alias" procedure for each new application. It's not really a big deal, though. Hope this helps. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:31 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c19g2000yqe.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Sun, 14 Aug 2011 09:32:06 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1313339526 14361 127.0.0.1 (14 Aug 2011 16:32:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Aug 2011 16:32:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c19g2000yqe.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5242 On Aug 14, 3:57=A0am, valtih1978 wrote: > What is wrong with my "design"? You said it yourself..."That is, listeners will not see your signal if the clock period is the same order as the line delay." This implies that your design is such that the clock and the data are in a race condition at the 'listener' and some bad thing will occur due to the data delay being on the order of the clock period. You started that post with "The problem is...'. You said it's a problem, so therefore it's a problem. My point is simply that the 'problem' has nothing to do with the VHDL model for a delay. Therefore, it must be a problem with what that VHDL model is actually modelling. Assuming that your VHDL model is modelling your design, then the problem is with your design. Precisely what that problem may be and how to address, I don't know since I don't have access to your design. Your original question was simply for a VHDL model for a bi-directional delay line presumably to model either a long printed circuit board delay, or perhaps a cable or something that is in your design. Now you have such a model. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:32 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeds.phibee-telecom.net!newsreader4.netcologne.de!news.netcologne.de!nx01.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!fv14g2000vbb.googlegroups.com!not-for-mail From: thunder Newsgroups: comp.lang.vhdl Subject: VHDL and System Verilog Assertions Date: Sun, 14 Aug 2011 10:42:35 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: <32b6f72e-75ed-4049-ae10-a3a6a1f55ee6@fv14g2000vbb.googlegroups.com> NNTP-Posting-Host: 94.8.67.22 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1313343756 24853 127.0.0.1 (14 Aug 2011 17:42:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 14 Aug 2011 17:42:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: fv14g2000vbb.googlegroups.com; posting-host=94.8.67.22; posting-account=fYOi-AoAAAAftKwn8h0pIn0WrxqvjnVx User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.17) Gecko/20110420 Firefox/3.6.17 GTB7.1 (.NET CLR 3.5.30729) GTBA,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5243 Hi All I started off implementing PSL assertions to the VHDL IP that we develop (after reading the advice in this newsgroup) However, management decision is that we need to implement System Verilog assertions since eventually we want to build a UVM compliant test bench. My question is : how to interface the VHDL RTL to the SVA? From what i can see, only the vunit method is viable. Embedding it directly in the VHDL RTL is not possible ? Is that correct? Also another question : We use Cadence ncsim for our simulation. Any one have any experience of how easy/difficult it is to debug the SVA in the VHDL IP/Cadence ncsim environment ? Thanks in advance JO From newsfish@newsfish Fri Feb 3 13:14:32 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: VHDL and System Verilog Assertions Date: Sun, 14 Aug 2011 19:09:05 +0100 Organization: A noiseless patient Spider Lines: 29 Message-ID: <1i3g475phne2uc0ogrj97dhibkkrs6qam5@4ax.com> References: <32b6f72e-75ed-4049-ae10-a3a6a1f55ee6@fv14g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="30357"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19u67wKc2uE0BvmiIygwq78f9UaYmBKhOU=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:B8vk6GdQUEXzlHod0T4aFECgg8Q= Xref: feeder.eternal-september.org comp.lang.vhdl:5244 On Sun, 14 Aug 2011 10:42:35 -0700 (PDT), thunder wrote: >However, management decision is that we need to implement System >Verilog assertions since eventually we want to build a UVM compliant >test bench. > >My question is : how to interface the VHDL RTL to the SVA? From what i >can see, only the vunit method is viable. Embedding it directly in the >VHDL RTL is not possible ? Is that correct? Write a module containing the SVA, with ports whose names match the signals in the RTL that you wish to monitor. Use SystemVerilog "bind" directive to inject an instance of this module into your VHDL RTL. All the major simulators support this methodology, but the precise details of how to get port names right, etc, vary from one tool to another. >Also another question : We use Cadence ncsim for our simulation. Any >one have any experience of how easy/difficult it is to debug the SVA >in the VHDL IP/Cadence ncsim environment ? Should be fine. Again, all the major tools have excellent support for mixed-language including waveform viewing etc. This is one of the sweet spots for SV "bind", and it was enthusiastically adopted by all the vendors almost as soon as SV hit the streets. It should be mature and easy to use. -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:33 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed1.swip.net!newsfeed3.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Mon, 15 Aug 2011 16:04:10 +0300 Lines: 14 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: pepper.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1313413450 10217 2001:708:310:3430:203:baff:fe7d:42dd (15 Aug 2011 13:04:10 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Mon, 15 Aug 2011 13:04:10 +0000 (UTC) User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/21.3 (usg-unix-v) Cancel-Lock: sha1:BWZErU7ybmtVpKUAzddUmf5CZS0= Xref: feeder.eternal-september.org comp.lang.vhdl:5246 Enrik Berkhan writes: > Anssi Saari wrote: >> Enrik Berkhan writes: >>> Have you tried vmake's `-cygdrive' (IIRC) command line option? >> >> I take it that option is either new or non-existing? I'm using >> Modelsim 6.5 and 6.6. > > I'm using an Altera Modelsim ASE OEM version, obviously based on 6.6d. > The header line in the generated Makefiles says 'vmake 2.2'. OK. I only checked Modelsim 6.5, there was no -cygdrive there. But yes, 6.6 has it. So, multiple solutions already. Thanks. From newsfish@newsfish Fri Feb 3 13:14:33 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder2.news.elisa.fi!feeder1.news.elisa.fi!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Should VHDL allow Unicode identifiers and comments Date: Mon, 15 Aug 2011 16:20:15 +0300 Lines: 20 Message-ID: References: <99dqncFsnU1@mid.individual.net> NNTP-Posting-Host: pepper.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: news.cc.tut.fi 1313414415 10217 2001:708:310:3430:203:baff:fe7d:42dd (15 Aug 2011 13:20:15 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Mon, 15 Aug 2011 13:20:15 +0000 (UTC) User-Agent: Gnus/5.101 (Gnus v5.10.10) Emacs/21.3 (usg-unix-v) Cancel-Lock: sha1:hI0ZlCtL3eRnBqPWOA22FKlbOuM= Xref: feeder.eternal-september.org comp.lang.vhdl:5247 Martin Thompson writes: > Hi all, > > I'm asking for a bit of input from the community... > > As the title says, would you find it of use to allow Unicode identifiers > and comments in a future VHDL revision? > > Would this be: > c) Something you'd find useful sometimes I liked an example snippet in Python I saw some time ago. There's another one at http://programmers.stackexchange.com/questions/16010/is-it-bad-to-use-unicode-characters-in-variable-names for example. After all, if your angle is phi, then why bother writing it out when you can just use 'φ' instead? From newsfish@newsfish Fri Feb 3 13:14:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Mon, 15 Aug 2011 20:05:30 +0300 Organization: A noiseless patient Spider Lines: 20 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 15 Aug 2011 17:05:39 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="17906"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/q6PGVvE2F1MGvn9nEcK8i31jlqqofTkc=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> Cancel-Lock: sha1:0blnptAgjAwx7IjqQEEosx46VRQ= Xref: feeder.eternal-september.org comp.lang.vhdl:5248 On 14.08.2011 19:32, KJ wrote: > "That is, listeners will not see your signal if > the clock period is the same order as the line delay." This implies > that your design is such that the clock and the data are in a race > condition at the 'listener' and some bad thing will occur due to the > data delay being on the order of the clock period. 1) Wherever you have clock and data there is always race between them. 2) It definitely makes sense to simulate the board delays when they are substantial compared to the clock period. SDRAM access is a perfect example where you need to simulate the long delays on a 3-state bus. If you want to match the simulation with reality, you need to use them. SDRAM interface employs the source-synchrony. Is it a bad design? Also, it makes sense to simulate with delays even when they are short but accumulate and risk to exeed the clock period. Yes, delays are used right to simulate the race conditions. The delay simulation is a sign of bad design! From newsfish@newsfish Fri Feb 3 13:14:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Testbench\Package Signal Visibility Date: Mon, 15 Aug 2011 20:35:24 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 15 Aug 2011 17:35:34 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="30474"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PGRKZjnUdPW6UCNp36FCs0Xl7TklN9Xg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> Cancel-Lock: sha1:5jAiQqtNht1RM9QduGkKNKCFmkc= Xref: feeder.eternal-september.org comp.lang.vhdl:5249 > can I still pass just one variable into the package The package looks like read-only creature. I think this is a reason you cannot easily read-write variables in them. From newsfish@newsfish Fri Feb 3 13:14:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p5g2000vbl.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Mon, 15 Aug 2011 12:40:34 -0700 (PDT) Organization: http://groups.google.com Lines: 53 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1313438047 16344 127.0.0.1 (15 Aug 2011 19:54:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Aug 2011 19:54:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p5g2000vbl.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5250 On Aug 15, 1:05=A0pm, valtih1978 wrote: > On 14.08.2011 19:32, KJ wrote: With each post you go off on a tangent that is unrelated to anything you posted previously, so this will be my last response on this thread. Good luck on whatever it is you are working on. > > > "That is, listeners will not see your signal if > > the clock period is the same order as the line delay." =A0This implies > > that your design is such that the clock and the data are in a race > > condition at the 'listener' and some bad thing will occur due to the > > data delay being on the order of the clock period. > > 1) Wherever you have clock and data there is always race between them. Are you trying to make a point with your statement? Other than stating the obvious? > 2) It definitely makes sense to simulate the board delays when they are > substantial compared to the clock period. > It makes more sense to perform static timing analysis...which is not done with a VHDL simulator nor will it need a VHDL model. > SDRAM access is a perfect example where you need to simulate the long > delays on a 3-state bus. If you want to match the simulation with > reality, you need to use them. SDRAM interface employs the > source-synchrony. Is it a bad design? > 'Bad' is a value judgment that is best left out of any technical discussion. As for SDRAM being a perfect example of where you need to simulate to account for timing delays, I disagree. A functional simulation and timing analysis are what you need for any design...not just SDRAM. There is nothing inherently *worse* about an SDRAM interface timing failure than any other sort of timing failure. > Also, it makes sense to simulate with delays even when they are short > but accumulate and risk to exeed the clock period. Yes, delays are used > right to simulate the race conditions. As I said, it makes *more* sense to perform timing analysis. > The delay simulation is a sign of > bad design! This statement makes no sense. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:35 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Testbench\Package Signal Visibility Date: Mon, 15 Aug 2011 13:55:51 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <7b1551e8-e5be-448a-901d-597efb5c34fa@glegroupsg2000goo.googlegroups.com> References: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.196.226.195 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1313441751 21635 127.0.0.1 (15 Aug 2011 20:55:51 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 15 Aug 2011 20:55:51 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.196.226.195; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5251 If a package and a variable are in a process scope, a procedure call can write those process variables. Variables declared *inside* the package are immutable. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:14:35 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Tue, 16 Aug 2011 11:12:52 +0300 Organization: A noiseless patient Spider Lines: 48 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Aug 2011 08:13:12 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="20561"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ep4EQA9w9DjZ6YWXhqS6yMZzmWr3yiyM=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: Cancel-Lock: sha1:1kLU9nEwD4Xf3z6jWdWHkdfe6CY= Xref: feeder.eternal-september.org comp.lang.vhdl:5252 On 15.08.2011 22:40, KJ wrote: > 'Bad' is a value judgment that is best left out of any technical discussion. We should keep talking about "a problem with the design" and "wrong design" instead. They are more technical. Right? > Are you trying to make a point with your statement? Other than > stating the obvious? I'm observing that somebody, who stated that "simulation of long delays implies the races between clock and data and, thus, is a sign of 'untechnical' design" is unable to remember this previous statement he made and uses it as a good pretext to shame the other party as being inconsistent. >> 2) It definitely makes sense to simulate the board delays when they >> are substantial compared to the clock period. > It makes more sense to perform static timing analysis...which is not done with a VHDL simulator nor will it need a VHDL model. Good luck with simulating "the timing analysis" > There is nothing inherently *worse* about an SDRAM interface timing failure than any other sort of timing failure. *Worse* is a from of 'untechical bad'. I never stated that. I simulate the whole FPGA design without delays and synthesis will tell me if timing problems exist. There is no problem. Now, you communicate with external device. You check your basic (calibration) design with functional model with no delay between them. This will work at low speeds. Then, you increase speeds and calibrate the fpga model so that it samples sdram responses at in the middle of the data valid window. You end up with fpga design that can communicate with ram at ultra high speed. But, functional simulation will fail. When the board works in reality with this fpga design but memory model connected to it responds differently in simulation, this does not mean that there are races or design is "intechnical". It only means that the board delays are so long that they must be taken into account and adjusted to put simulation in correspondence with reality. You cannot do functional simulation without introducing these delays. From newsfish@newsfish Fri Feb 3 13:14:36 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h14g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Tue, 16 Aug 2011 05:33:46 -0700 (PDT) Organization: http://groups.google.com Lines: 17 Message-ID: <8f730369-05d8-47eb-973e-dcc0b6b309cf@h14g2000yqd.googlegroups.com> References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1313498924 23174 127.0.0.1 (16 Aug 2011 12:48:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 16 Aug 2011 12:48:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h14g2000yqd.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5253 On Aug 16, 4:12=A0am, valtih1978 wrote: > > =A0> It makes more sense to perform static timing analysis...which is not > done with a VHDL simulator nor will it need a VHDL model. > > Good luck with simulating "the timing analysis" > Just in case you want to actually learn something rather than just rambling on which I won't engage you in any longer... - Research the term 'static timing analysis' which is what I said needed to be performed. - Then learn how to perform this type of analysis - Then tell us how important a simulator was to you in performing that analysis (Hint: the answer is 'none') KJ From newsfish@newsfish Fri Feb 3 13:14:36 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you introduce delays into 3-state (bi-dir) lines? Date: Tue, 16 Aug 2011 20:09:52 +0300 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: <84aac66b-cc8f-463e-bab0-29ebb5c71e32@n5g2000yqh.googlegroups.com> <001ee207-9c3e-4c59-a1b1-35c1dd704553@c19g2000yqe.googlegroups.com> <8f730369-05d8-47eb-973e-dcc0b6b309cf@h14g2000yqd.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 16 Aug 2011 17:10:03 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="8520"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181n+Hf5X6V55LxURSnYJVXiasrOnXyWi8=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:5.0) Gecko/20110624 Thunderbird/5.0 In-Reply-To: <8f730369-05d8-47eb-973e-dcc0b6b309cf@h14g2000yqd.googlegroups.com> Cancel-Lock: sha1:Ho+R52SHUByIvc8Q4qZxDoTLsNI= Xref: feeder.eternal-september.org comp.lang.vhdl:5254 Thanks to you, I've learned a lot of interesting things: 1) long delays necessarily imply the clock race with data 2) 'bad' is untechnical word and simulating with board-long delays implies untechnical design 3) simulating with delays becomes less important when you reach the board level. 4) and timing analysis must be preferred instead. Thanks. From newsfish@newsfish Fri Feb 3 13:14:38 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!goblin1!goblin3!goblin.stu.neva.ru!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Date: Sat, 20 Aug 2011 18:50:01 +0300 Lines: 9 Message-ID: References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> <4e44ffea$0$23840$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: coffee.modeemi.fi Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1313855401 17164 2001:708:310:3430:202:a5ff:fe4f:4ed8 (20 Aug 2011 15:50:01 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Sat, 20 Aug 2011 15:50:01 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.2 (gnu/linux) Cancel-Lock: sha1:0D7ZI2qrRhJL8b94Z1iBbuCU3Wg= Xref: feeder.eternal-september.org comp.lang.vhdl:5262 Paul Uiterlinden writes: > Sorry, I don't know. I don't use Windows. Damn, it's a long time since I've been able to say that, even professionally. At least documentation has in recent years been Wrod always, even if real work was done in Linux. You hiring?-) From newsfish@newsfish Fri Feb 3 13:14:38 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e564688$0$2427$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: "Writing Makefiles for VHDL models" by Janick Bergeron Newsgroups: comp.lang.vhdl Date: Thu, 25 Aug 2011 14:56:40 +0200 References: <98l51iFmp5U1@mid.individual.net> <99106uFbt6U1@mid.individual.net> <061f103a-541c-4909-b411-ec14ef3d589f@dp9g2000vbb.googlegroups.com> <995d36FlvbU1@mid.individual.net> <75ac2c77-ca65-4eb2-8e7e-e0f1e69448ab@v7g2000vbk.googlegroups.com> <4e31289b$0$23870$e4fe514c@news2.news.xs4all.nl> <4e44ffea$0$23840$e4fe514c@news2.news.xs4all.nl> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 25 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1314277000 news2.news.xs4all.nl 2427 puiterl/195.242.97.150:57771 Xref: feeder.eternal-september.org comp.lang.vhdl:5264 Anssi Saari wrote: > Paul Uiterlinden writes: > >> Sorry, I don't know. I don't use Windows. > > Damn, it's a long time since I've been able to say that, even > professionally. I pitty you. > At least documentation has in recent years been Wrod > always, even if real work was done in Linux. > > You hiring?-) Not personally. :-) You might check the WEB addres in my signature, although there are no direct vacancies at the moment. And the location is the Netherlands. But I don't see that as a problem. :-) -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:14:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!feeder2.cambriumusenet.nl!feed.tweaknews.nl!195.238.0.231.MISMATCH!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Date: Mon, 29 Aug 2011 10:04:48 +0200 From: Jan Decaluwe User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Thunderbird/3.1.10 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl,comp.lang.verilog Subject: A free lunch Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 28 Message-ID: <4e5b4815$0$5039$ba620e4c@news.skynet.be> Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: c39580fa.news.skynet.be X-Trace: 1314605077 news.skynet.be 5039 91.177.24.84:33284 X-Complaints-To: usenet-abuse@skynet.be Xref: feeder.eternal-september.org comp.lang.vhdl:5265 comp.lang.verilog:3156 The Python community is about to offer us a free lunch. A new compliant interpreter, pypy, is already 4.3x faster than cPython, and getting faster everyday. It shows that there is not conceptual reason why high-level dynamic languages should be slow. For MyHDL, an HDL implemented as a Python library, the results are even more spectacular: my benchmarks run 8-20x faster on pypy. In a single strike, this makes MyHDL simulation performance competitive with Verilog/VHDL. Apart from the fact that MyHDL makes a good "scripting" companion to Verilog/VHDL, there is another reason why I post to these newsgroups: the benchmark results may be useful to users and developers of other open source simulators also. For example, icarus Verilog is quite consistent, but GHDL is not. In one benchmark, it is 100x slower than the fastest simulator. http://myhdl.org/doku.php/performance Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com From newsfish@newsfish Fri Feb 3 13:14:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n19g2000prh.googlegroups.com!not-for-mail From: guranditta guranditta Newsgroups: comp.lang.vhdl Subject: regarding thesis Date: Wed, 31 Aug 2011 09:43:15 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: NNTP-Posting-Host: 42.109.47.209 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1314808995 29455 127.0.0.1 (31 Aug 2011 16:43:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 31 Aug 2011 16:43:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n19g2000prh.googlegroups.com; posting-host=42.109.47.209; posting-account=p_JzfgoAAADsPgTGAUr7G1n3dv8YNRp0 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5266 hello sir, i am doing thesis in m.tech . my topic is vlsi implementation of triple data encryption standard fips 46-3 , 64 bit processor . i need a vhdl code for substitution box s-box which is 4*16 matrix based , means 16 row and 4 coulmn plz help me .. thanx. From newsfish@newsfish Fri Feb 3 13:14:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!s7g2000yqd.googlegroups.com!not-for-mail From: ihk Newsgroups: comp.lang.vhdl Subject: trouble connecting an out std_logic_vector port to aggregate of signals Date: Thu, 1 Sep 2011 01:48:12 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: <3b107b10-9e0f-4d18-81ef-9f442ff2156b@s7g2000yqd.googlegroups.com> NNTP-Posting-Host: 81.63.147.107 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1314867773 18527 127.0.0.1 (1 Sep 2011 09:02:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 1 Sep 2011 09:02:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s7g2000yqd.googlegroups.com; posting-host=81.63.147.107; posting-account=MQ2vpQoAAACuQbeJKK2hrHSmfd2ThpVm User-Agent: G2/1.0 X-HTTP-Via: 1.1 ch05px01 (squid/3.1.0.6) X-Google-Web-Client: true X-Google-Header-Order: ARLUECHVFNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; .NET CLR 2.0.50727; hci4.djdw567564sds4892),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5267 Hello, Can a VHDL guru help me explaining why for a component defined like this component nios is port ( pio_in : in std_logic_vector(15 downto 0), pio_out : out std_logic_vector(7 downto 0) ); I can do the following assignment: nios_1 : nios port map ( pio_in => ( 0 => pll_locked, 1 => pll_clkswitch, others => '0') ); but the following gives syntax error (in Altera Quartus) nios_1 : nios port map ( pio_out => ( 0 => led1, 1 => led2, others => open) ); The only way I can make this works is if I do the assignment to pio_out like this: nios_1 : nios port map ( pio_out(0) => led1, pio_out(1) => led2 ); Thanks and best regards, Ivo From newsfish@newsfish Fri Feb 3 13:14:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!i21g2000yqd.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: regarding thesis Date: Thu, 1 Sep 2011 02:17:21 -0700 (PDT) Organization: http://groups.google.com Lines: 18 Message-ID: <36e31606-ca75-4d01-bccb-a699d976f66f@i21g2000yqd.googlegroups.com> References: NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1314868750 28379 127.0.0.1 (1 Sep 2011 09:19:10 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 1 Sep 2011 09:19:10 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i21g2000yqd.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9979) X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRUV X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5268 On 31 Aug., 18:43, guranditta guranditta wrote: > hello sir, > =A0 =A0 =A0 =A0 =A0 =A0 i am doing thesis in m.tech . my topic is vlsi > implementation of triple data encryption standard fips 46-3 =A0 , =A064 > bit processor . i need a vhdl code for substitution box =A0 s-box =A0whic= h > is 4*16 matrix based , means 16 row and 4 coulmn plz help me .. Doing efficient S-Box is one of the keys to get good implementation. So if you like to earn your degree you need to do it on your own, as no one discloses good solutions. If this is not required, define s_box as array of vectors and use the following line: s_box :=3D ("0000", "0001",....,"1111"); bye Thomas From newsfish@newsfish Fri Feb 3 13:14:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!s7g2000yqk.googlegroups.com!not-for-mail From: Pontus Newsgroups: comp.lang.vhdl Subject: Re: trouble connecting an out std_logic_vector port to aggregate of signals Date: Thu, 1 Sep 2011 13:40:13 -0700 (PDT) Organization: http://groups.google.com Lines: 62 Message-ID: <9d0b8cfa-364b-4393-a622-85c7bba03827@s7g2000yqk.googlegroups.com> References: <3b107b10-9e0f-4d18-81ef-9f442ff2156b@s7g2000yqd.googlegroups.com> NNTP-Posting-Host: 213.185.243.153 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1314910024 32301 127.0.0.1 (1 Sep 2011 20:47:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 1 Sep 2011 20:47:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s7g2000yqk.googlegroups.com; posting-host=213.185.243.153; posting-account=868sxwkAAAAOFYbrf1WhaucleDP4lbWZ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; sv-SE; rv:1.9.2.20) Gecko/20110805 Ubuntu/10.04 (lucid) Firefox/3.6.20,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5269 Not beeing a guru, I should perhaps not attempt an answer... (Gurus usually have several limo's, I don't) I have been bitten by similar issues before, portmaps where parts of a vector should connect, others stay open, etc. I think this is an effect of the language trying to limit the missuses rather than to allow non-precise statements to be accepted. Or perhaps it's some vendors non-compliance to the standard. Your solution seems pretty clean and expressive, your problem was probably getting the compiler to accept the code. When I struggled with this, I got some informative compile errors from the simulator (modelsim or riviera, can't remember witch). HTH -- Pontus On 1 Sep, 10:48, ihk wrote: > Hello, > > Can a VHDL guru help me explaining why for a component defined like > this > > component nios is > =A0 =A0port ( > =A0 =A0 =A0 =A0pio_in =A0 : in =A0std_logic_vector(15 downto 0), > =A0 =A0 =A0 =A0pio_out : out std_logic_vector(7 downto 0) > ); > > I can do the following assignment: > > nios_1 : nios > =A0 =A0port map ( > =A0 =A0 =A0 =A0pio_in =A0 =3D> ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0 =A0 =A0 =A0 =A0 =A0 =3D> pll_locked, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 1 =A0 =A0 =A0 =A0 =A0 =3D> pll_clkswitch, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 others =A0 =A0 =A0=3D> '0') > =A0 ); > > but the following gives syntax error (in Altera Quartus) > > nios_1 : nios > =A0 =A0port map ( > =A0 =A0 =A0 =A0pio_out =A0 =3D> ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0 =A0 =A0 =A0 =A0 =A0 =3D> led1, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 1 =A0 =A0 =A0 =A0 =A0 =3D> led2, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 others =A0 =A0=3D> open) > =A0 ); > > The only way I can make this works is if I do the assignment to > pio_out like this: > nios_1 : nios > =A0 =A0port map ( > =A0 =A0 =A0 =A0pio_out(0) =A0=3D> led1, > =A0 =A0 =A0 =A0pio_out(1) =A0=3D> led2 > =A0 ); > > Thanks and best regards, > Ivo From newsfish@newsfish Fri Feb 3 13:14:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.litech.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Sep 2011 12:02:17 -0500 Date: Fri, 02 Sep 2011 10:04:05 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Retrieving a signal parameter's name Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 14 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-vRlf55Fu7M7kJyCZxgWYcmWAT3skOSr82rGpMcOmJb0QOPJWpXDdNh2rOCtW4Pv+XQL/+0JM2AdMypk!a6Yz32HhLjxOn41ZXLaHSClHAcgCEm96ERRSAC5/jyVIgAuTfGsuZxN14fSIQEVw9ZeKMz1ocDRa X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1476 Xref: feeder.eternal-september.org comp.lang.vhdl:5270 This should be far easier to figure out than it is. If I've got a signal as a parameter to a procedure, such as procedure test_ext_irq( signal irq_line : out boolean; irq_mask : in t_wb_data) Is there any way for me to get the name of the actual signal connected to irq_line to use it in an assertion? irq_line'simple_name just gives me irq_line, a thing I find tremendously unhelpful. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:41 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Retrieving a signal parameter's name Date: Fri, 02 Sep 2011 18:24:10 +0100 Organization: A noiseless patient Spider Lines: 25 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="24801"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/jFj/En3JttOZXDd10FDCwQ8i40+Ylkss=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:lNYChQz2sIunjTv20O/MVbpAEK8= Xref: feeder.eternal-september.org comp.lang.vhdl:5271 On Fri, 02 Sep 2011 10:04:05 -0700, Rob Gaddi wrote: >This should be far easier to figure out than it is. If I've got a >signal as a parameter to a procedure, such as > >procedure test_ext_irq( > signal irq_line : out boolean; > irq_mask : in t_wb_data) > >Is there any way for me to get the name of the actual signal connected >to irq_line to use it in an assertion? irq_line'simple_name just gives >me irq_line, a thing I find tremendously unhelpful. Rob, I don't believe there is any direct way to do this. You can, of course, provide a string input parameter and feed it the actual signal's 'SIMPLE_NAME. But that is somewhat self-defeating. This is one of those things that would be facilitated by text-preprocessing macros.... Sorry! -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:41 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!just2write2.myftp.org!feeder.erje.net!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Fri, 02 Sep 2011 18:38:45 -0500 Date: Sat, 03 Sep 2011 00:38:44 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0) Gecko/20110816 Thunderbird/6.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: trouble connecting an out std_logic_vector port to aggregate of signals References: <3b107b10-9e0f-4d18-81ef-9f442ff2156b@s7g2000yqd.googlegroups.com> In-Reply-To: <3b107b10-9e0f-4d18-81ef-9f442ff2156b@s7g2000yqd.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 56 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-H696jEwQv4+Y9CQaUqapMz3Sy6GjcI7kvO70kt1BsuugeZ7i9lqTZOT0Xj/hq5A2ejkUpQReJSa6/H4!sUtlV04Uc9SCdOh7D5/YTC7ZMeeHnTXUGNRjbgoE5KIBQ9tbHUlilYMB+9UuRYXiHySRuvg0KhxD!5M+XGHzqx9MSVfNC6azy3uo4y8I= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2609 Xref: feeder.eternal-september.org comp.lang.vhdl:5272 On 01/09/11 09:48, ihk wrote: > Hello, > > Can a VHDL guru help me explaining why for a component defined like > this > > component nios is > port ( > pio_in : in std_logic_vector(15 downto 0), > pio_out : out std_logic_vector(7 downto 0) > ); > > I can do the following assignment: > > nios_1 : nios > port map ( > pio_in => ( > 0 => pll_locked, > 1 => pll_clkswitch, > others => '0') > ); > > but the following gives syntax error (in Altera Quartus) > > nios_1 : nios > port map ( > pio_out => ( > 0 => led1, > 1 => led2, > others => open) > ); As far as I remember that's just not legal. You can't say others => open. But I'll have to look at the standard to be really sure. > > The only way I can make this works is if I do the assignment to > pio_out like this: > nios_1 : nios > port map ( > pio_out(0) => led1, > pio_out(1) => led2 > ); > If I recall correctly, that's illegal in VHDL93, but legal in VHDL87. In VHDL 93 the standard was modified to say that if you map parts of a vector, you either have to do associate all elements, or leave all elements open. I.e. not a mixture. regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:14:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!feeder2-2.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!v18g2000yqj.googlegroups.com!not-for-mail From: Insight Realm Newsgroups: comp.lang.vhdl Subject: Configuring FPGA bulk chips Date: Mon, 5 Sep 2011 17:17:20 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <151d5bfb-18d9-4a37-8cc6-04ca84c66674@v18g2000yqj.googlegroups.com> NNTP-Posting-Host: 178.73.198.66 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315269199 18280 127.0.0.1 (6 Sep 2011 00:33:19 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 6 Sep 2011 00:33:19 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v18g2000yqj.googlegroups.com; posting-host=178.73.198.66; posting-account=wwUqXgoAAAAI6fneWjoMtZsVX824AtMM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; rv:6.0.1) Gecko/20100101 Firefox/6.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5273 Hi there, I found a cheap lot of 4 FPGA chips. What would I need in order to use them? Do I need to create a PCB design? Are there boards for sale where you can just plug in the chips? Thank you. From newsfish@newsfish Fri Feb 3 13:14:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Configuring FPGA bulk chips Date: Tue, 6 Sep 2011 09:40:35 +0000 (UTC) Organization: A noiseless patient Spider Lines: 47 Message-ID: References: <151d5bfb-18d9-4a37-8cc6-04ca84c66674@v18g2000yqj.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 6 Sep 2011 09:40:35 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="qAdDANJsLWqXAvsVHU9uOQ"; logging-data="25556"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Dl9jftV6oOF6QJr7HZr8L22xQgoHiotM=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:b2cIoXkPngyDPyMWompPOpI9atk= Xref: feeder.eternal-september.org comp.lang.vhdl:5274 On Mon, 05 Sep 2011 17:17:20 -0700, Insight Realm wrote: > Hi there, > > I found a cheap lot of 4 FPGA chips. What would I need in order to use > them? Do I need to create a PCB design? Are there boards for sale where > you can just plug in the chips? > > Thank you. Hoo boy. And you forgot the only important bit of information ... which FPGA. Manufacturer, series, size, package. But never mind. There are no suitable boards ... unless you lucked out and found the exact FPGA used here http://www.fpga4fun.com/ http://www.knjn.com/FPGA-PCI.html or http://www.knjn.com/ShopBoards_PCI.html And I'm not sure he still sells the boards on their own. So you probably have to get busy with pcb123. http://www.sunstone.com/PCB123-CAD-Software.aspx Or if your FPGA is in a BGA package, you need something a bit more heavy duty. Keeping costs down, look at freepcb http://www.freepcb.com/ Both run under Wine, if you aren't using Windows. Then you need to design hardware for them. For which you need tools from the FPGA manufacturer, Xilinx, Altera, Atmel etc. Check that the FPGA you have is supported by the free tools before downloading 4GB or so of tool... You may have to dig around their website to find obsolete (cough, sorry, legacy* tool versions if these FPGAs aren't current. But you'll probably find that a new commercially available board is so cheap it's simply not worth the bother. For example http://enterpoint.co.uk/products/ has http://enterpoint.co.uk/products/educational/polmaddie/polmaddie-3/ Lots of I/O, and ready to go. - Brian From newsfish@newsfish Fri Feb 3 13:14:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a12g2000yqi.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Is this an LRM thing, or Modelsim Bug? Date: Tue, 6 Sep 2011 07:01:14 -0700 (PDT) Organization: http://groups.google.com Lines: 36 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315318138 3963 127.0.0.1 (6 Sep 2011 14:08:58 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 6 Sep 2011 14:08:58 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a12g2000yqi.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20100101 Firefox/6.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5275 Ive got this code: library ieee; use ieee.std_logic_1164.all; entity play_TB is generic ( DEBUG : boolean := true ); end entity; architecture rtl of play_TB is signal test : std_logic; begin process begin if DEBUG then test <= '0'; end if; wait; end process; test <= '1'; end rtl; This quite correctly has test set to 'X' when the simulation runs. But if DEBUG is false, test remains at 'U'. So is this an LRM thing, or is it a modelsim bug? From newsfish@newsfish Fri Feb 3 13:14:43 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Jonathan Bromley Newsgroups: comp.lang.vhdl Subject: Re: Is this an LRM thing, or Modelsim Bug? Date: Tue, 06 Sep 2011 15:53:56 +0100 Organization: A noiseless patient Spider Lines: 56 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Info: mx04.eternal-september.org; posting-host="N23lZmI09LFKjfOxaAG7ag"; logging-data="25814"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18lyR7hyUu2IqOV0I5cX55Aw7EW6DP4/2g=" X-Newsreader: Forte Free Agent 3.3/32.846 Cancel-Lock: sha1:D/p6RrgK5/E2AmEVk585R2/QnRg= Xref: feeder.eternal-september.org comp.lang.vhdl:5276 On Tue, 6 Sep 2011 07:01:14 -0700 (PDT), Tricky wrote: >Ive got this code: > >library ieee; >use ieee.std_logic_1164.all; > >entity play_TB is > generic ( > DEBUG : boolean := true > ); > > >end entity; > >architecture rtl of play_TB is > signal test : std_logic; >begin > > > process > begin > if DEBUG then > test <= '0'; > end if; > > wait; > end process; > > test <= '1'; > >end rtl; > >This quite correctly has test set to 'X' when the simulation runs. > >But if DEBUG is false, test remains at 'U'. > >So is this an LRM thing, or is it a modelsim bug? I'm sure that's correct per LRM. Your process represents a driver on 'test'. If you choose, at runtime, not to write to 'test' then the driver will stay at its default value of 'U'. If you use generic DEBUG to if-generate the process, then of course the driver will disappear completely if DEBUG is false. You could also consider initializing 'test' to 'Z' somewhere; perhaps in its declaration (so *all* drivers start at 'Z') or at the start of the process, independent of the value of DEBUG (in which case the driver will be 'U' for the first delta cycle). -- Jonathan Bromley From newsfish@newsfish Fri Feb 3 13:14:43 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!gz5g2000vbb.googlegroups.com!not-for-mail From: Nick Anghelidi Newsgroups: comp.lang.vhdl Subject: Re: Configuring FPGA bulk chips Date: Tue, 6 Sep 2011 08:38:47 -0700 (PDT) Organization: http://groups.google.com Lines: 58 Message-ID: <1a77de92-5947-4e89-aadc-dce485e73461@gz5g2000vbb.googlegroups.com> References: <151d5bfb-18d9-4a37-8cc6-04ca84c66674@v18g2000yqj.googlegroups.com> NNTP-Posting-Host: 24.246.88.140 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315325185 12703 127.0.0.1 (6 Sep 2011 16:06:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 6 Sep 2011 16:06:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gz5g2000vbb.googlegroups.com; posting-host=24.246.88.140; posting-account=-22M8QoAAACSaKSBueLWPewVEjKJ6laD User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; rv:6.0.1) Gecko/20100101 Firefox/6.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5277 On Sep 6, 2:40=A0am, Brian Drummond wrote: > On Mon, 05 Sep 2011 17:17:20 -0700, Insight Realm wrote: > > Hi there, > > > I found a cheap lot of 4 FPGA chips. What would I need in order to use > > them? Do I need to create a PCB design? Are there boards for sale where > > you can just plug in the chips? > > > Thank you. > > Hoo boy. > > And you forgot the only important bit of information ... which FPGA. > Manufacturer, series, size, package. > > But never mind. > > There are no suitable boards ... unless you lucked out and found the > exact FPGA used herehttp://www.fpga4fun.com/http://www.knjn.com/FPGA-PCI.= html > orhttp://www.knjn.com/ShopBoards_PCI.html > > And I'm not sure he still sells the boards on their own. > > So you probably have to get busy with pcb123.http://www.sunstone.com/PCB1= 23-CAD-Software.aspx > Or if your FPGA is in a BGA package, you need something a bit more heavy > duty. Keeping costs down, look at freepcbhttp://www.freepcb.com/ > Both run under Wine, if you aren't using Windows. > > Then you need to design hardware for them. For which you need tools from > the FPGA manufacturer, Xilinx, Altera, Atmel etc. Check that the FPGA you > have is supported by the free tools before downloading 4GB or so of > tool... You may have to dig around their website to find obsolete (cough, > sorry, legacy* tool versions if these FPGAs aren't current. > > But you'll probably find that a new commercially available board is so > cheap it's simply not worth the bother. For examplehttp://enterpoint.co.u= k/products/ > hashttp://enterpoint.co.uk/products/educational/polmaddie/polmaddie-3/ > Lots of I/O, and ready to go. > > - Brian Hi Brian, Well... I haven't really decided about which FPGA. I saw this offer on ebay so I thought I might try to see if it is a better alternative than buying the full board. I checked the enterpoint site but I need something high-end which are costing a lot. Instead of paying on one high end board maybe I can get more capabilities (more medium boards) using cheaper (bulk + PCB + whatever work would be required) boards. Thanks a lot for the detailed response. Regards, Nick From newsfish@newsfish Fri Feb 3 13:14:44 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Is this an LRM thing, or Modelsim Bug? Date: Wed, 07 Sep 2011 11:38:47 +0100 Organization: TRW Conekt Lines: 27 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net /BexAlAO2LlfTwR/SkTgPwswAjU6GhaNxFstvjUBI0haDbpvY= Cancel-Lock: sha1:7xYXuO62BOjoIyj6QqF4syyHpN0= sha1:vDLybUWmEElI9kOquNGCKJbVRp0= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5278 Tricky writes: > Ive got this code: > process > begin > if DEBUG then > test <= '0'; > end if; > > wait; > end process; This process has a driver in it. When DEBUG is false, that driver doesn't get any assignments to change it from its default state of 'U'. You could either initialise the signal, or provide a default driver (maybe to 'Z') in the process, or if..generate the whole process (which removes the driver as well) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:14:44 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!o10g2000vby.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Fast Counter Date: Wed, 7 Sep 2011 12:07:35 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315422568 15460 127.0.0.1 (7 Sep 2011 19:09:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 7 Sep 2011 19:09:28 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o10g2000vby.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5279 Hi, I need a 700 MHz to 800Mhz synchronous 16 bit counter. The counter will also have a Start, Reset and Stop pins. Reset will intialize the counter to zero. Start will let the counter run on each rising edge of the 700 or 800 Mhz clock. And stop will stop the counter and user will be able to read the value. I do not know 1. What FPGA or CPLD will be able to do this task at the above mentioned high frequency? 2. Do I need a PLL inside the FPGA or CPLD to produce such kind of clock? 3. How can I generate this kind of clock? Any advice will be appreciated. jess From newsfish@newsfish Fri Feb 3 13:14:45 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 07 Sep 2011 15:33:34 -0500 Date: Wed, 07 Sep 2011 13:35:25 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> Lines: 30 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-0dGNjP4YN5YSXDoYzZTkcj/iZQh0Zp7wXfi079IUggZ+IRbeEzGJNLBc5IrdbrVO3Z67e2OiqnYbrSD!F8wxDo+CdjU2rcc9zgUpvcKpJYJIajIOFAi/kWjWEKF9gF6SDOYMlpWpJJPobYv8OspqG4O5kfi7 X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2101 Xref: feeder.eternal-september.org comp.lang.vhdl:5280 On 9/7/2011 12:07 PM, Jessica Shaw wrote: > Hi, > > I need a 700 MHz to 800Mhz synchronous 16 bit counter. The counter > will also have a Start, Reset and Stop pins. > > Reset will intialize the counter to zero. Start will let the counter > run on each rising edge of the 700 or 800 Mhz clock. And stop will > stop the counter and user will be able to read the value. > > I do not know > > 1. What FPGA or CPLD will be able to do this task at the above > mentioned high frequency? > 2. Do I need a PLL inside the FPGA or CPLD to produce such kind of > clock? > 3. How can I generate this kind of clock? > > Any advice will be appreciated. > > jess A 400 MHz counter in an FPGA is difficult. 800 MHz is probably impossible. Possibly run 4 14-bit, 200 MHz counters in parallel on 4 different clock phases and then sort out the outputs after the stop happens? -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:45 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.visyn.net!visyn.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!feeds.phibee-telecom.net!feeder.news-service.com!postnews.google.com!s20g2000yql.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Wed, 7 Sep 2011 13:38:12 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315427990 6111 127.0.0.1 (7 Sep 2011 20:39:50 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 7 Sep 2011 20:39:50 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000yql.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5281 Hi, Why is it dfficult? Jess From newsfish@newsfish Fri Feb 3 13:14:46 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed101.telia.com!starscream.dk.telia.net!fu-berlin.de!uni-berlin.de!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Thu, 08 Sep 2011 00:25:42 +0200 Lines: 10 Message-ID: <9cq9b6Fso4U1@mid.uni-berlin.de> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: news.uni-berlin.de HY0keFiVbdL8UYwynBpaDwo3bQ9YqKiNWVjGhOSN8fpm6mA3w= User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; de; rv:1.9.2.21) Gecko/20110830 Thunderbird/3.1.13 In-Reply-To: <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:5282 On 07.09.11 13:38:12 Jessica Shaw wrote: > Hi, > > Why is it dfficult? Why is it difficult to build and drive a car with 1000 km/h (620 mph)? There are physical limits. In both cases. regards, Bart From newsfish@newsfish Fri Feb 3 13:14:46 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!ecngs!feeder.ecngs.de!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!e14g2000yqi.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Wed, 7 Sep 2011 16:28:18 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315438178 12723 127.0.0.1 (7 Sep 2011 23:29:38 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 7 Sep 2011 23:29:38 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: e14g2000yqi.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5283 Hi, ok, so you can get a jet engine car but it will be difficult to drive it on the road. So, what are the difficulties with making such a FPGA? Second, what should be the good solution? jess From newsfish@newsfish Fri Feb 3 13:14:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news2.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 07 Sep 2011 18:45:42 -0500 Date: Wed, 07 Sep 2011 16:47:51 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> In-Reply-To: <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 37 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-uk9KRj+OKXtliK8umgDWxT+KnpiSSH8BkVpXNW6f5caJRO1iO2cHTpW6DDVyhvfWmlElSqDAUFpk5Uu!q/S/OpPZV/fIZKAmDPm4jNb5yqgZSPEcbUQIlMCYWzKQLIbzbrGQPKu9JtBmjTrI2rvWnczKTFag X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2787 Xref: feeder.eternal-september.org comp.lang.vhdl:5284 On 9/7/2011 4:28 PM, Jessica Shaw wrote: > Hi, > > ok, so you can get a jet engine car but it will be difficult to drive > it on the road. So, what are the difficulties with making such a > FPGA? > A mid-range sedan costs $12,000 or so, and mostly just works. A jet engine costs about $2M, and requires pretty regular maintenance. A company called Achronix makes crazy high-speed FPGAs that might be able to do what you're talking about. I've never talked to them about pricing, but I wouldn't expect to be able to walk away with any of their stuff for under $10K, and wouldn't be shocked it it's well higher. > Second, what should be the good solution? > FPGAs are fundamentally not that fast, certainly far slower than the equivalent ASIC at the same technology. Generally, the solution to speed problems in FPGAs is to find ways to parallelize your task instead of brute forcing it with MHz. Hence my first response to you. By the way, the question of what is it you're actually trying to do is one of those things that always comes up. It sounds as if you're trying to basically make a high-resolution stopwatch. There are all manner of dirty tricks that can be played to make that happen that don't require a preposterously high-speed clock. "Time digital converter" are your Google terms. > jess -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z18g2000yqb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Wed, 7 Sep 2011 20:11:22 -0700 (PDT) Organization: http://groups.google.com Lines: 75 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315451813 24255 127.0.0.1 (8 Sep 2011 03:16:53 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 8 Sep 2011 03:16:53 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z18g2000yqb.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5285 On Sep 7, 7:28=A0pm, Jessica Shaw wrote: > Hi, > > ok, so you can get a jet engine car but it will be difficult to drive > it on the road. So, what are the difficulties with making such a > FPGA? > The short answer is that there are tradeoffs that are based on technology as well as market demand. The FPGA companies' customers make use of capabilities that are unique to FPGAs and are willing to compromise on things like top speed or low power consumption. Providing things like re-programmability and a fairly generic pool of logic that can implement basically any arbitrary function which FPGAs do quite well doesn't come 'free'. Historically, the price to be paid has meant that you will pay a higher piece price, run slower and consume more power than you would if you have the resources and business case to develop a custom single function part. Without getting into a debate about the merits of each cost, suffice it to say that there is sufficient market demand for such programmable products to keep companies in business and profitable. There are many niches that one can play in the programmable logic world and be profitable. Some of these niches involve providing lower power or higher performance than some other companies FPGA. However, within each niche product, you'll find something that you can't do (or can't do well) with that part that you can with some other part. Before there were even FPGAs, there were PLDs which provide much the same type of functionality but were blazingly fast compared to those first FPGAs...but again, there were tradeoffs, notably the amount of logic that could be implemented in a single device. So, in the end, if you're a user of an FPGA, it really doesn't matter "what are the difficulties with making such a FPGA" as you asked. Your job is to find the FPGA that has the right set of features for your application. > Second, what should be the good solution? > Before there can be a solution there must first be a full discovery of what the constraints really are so nobody here will be able to confidently offer up what will be a 'good' solution for you. You can get possible solutions that happen to work for you, but since we don't know your constraints we don't really know if any proposed solution would really be 'good'. For example, you didn't state any latency requirement on when the count must be valid relative to the assertion of 'stop'. If there is none, than one can play the simple game of having four counters running on different phases of 200 MHz. At the end, simply add the value of the four counters to get the final result. This approach would obviously take more logic than a hypothetical single 16 bit counter, but since you have not stated any logic resource constraints for the counter one would have no idea of whether or not this approach is 'good' for you. So logic resource are another possible constraint. Counters do not have to be binary, a 16 bit LFSR will run quite fast but then it requires interpretation of the output in order to figure out what the binary equivalent value...but maybe that's OK in your application. So counting sequence is another possible constraint. There likely is a programmable part that can implement a full 16 bit binary counter in minimal resources but maybe the cost is too high and it makes the product not profitable so that part can't be used. As you can see, there are likely all kinds of constraints that one may not necessarily realize up front. It is up to you to understand your function and performance goals, the constraints that you must live within and come up with the optimal solution...that's what is known as engineering. In short, you have to look at tradeoffs. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o9g2000vbo.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Thu, 8 Sep 2011 12:15:47 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315509762 9136 127.0.0.1 (8 Sep 2011 19:22:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 8 Sep 2011 19:22:42 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000vbo.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5286 > Kevin Jennings wrote: > For example, you didn't state any latency requirement on when the > count must be valid relative to the assertion of 'stop'. =A0If there is > none, than one can play the simple game of having four counters > running on different phases of 200 MHz. =A0At the end, simply add the > value of the four counters to get the final result. > Can you advice more on how can I use four counters running on different phases of 200MHz. I am little confused about different phases. Can you advice some application notes or examples. Thanks jess From newsfish@newsfish Fri Feb 3 13:14:48 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!newsreader4.netcologne.de!news.netcologne.de!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!o26g2000vbi.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Thu, 8 Sep 2011 13:36:01 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315514162 22252 127.0.0.1 (8 Sep 2011 20:36:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 8 Sep 2011 20:36:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o26g2000vbi.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5287 A timing waveform or block diagram would work too jess From newsfish@newsfish Fri Feb 3 13:14:48 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Thu, 08 Sep 2011 16:20:57 -0500 Date: Thu, 08 Sep 2011 14:22:45 -0700 From: Rob Gaddi User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> In-Reply-To: <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <4MmdneiG7oknrPTTnZ2dnUVZ_qednZ2d@lmi.net> Lines: 35 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 70.36.197.87 X-Trace: sv3-2XeEXjBsmbeiKxOl3GkZIr5HbkUJJ4AK02sm8y/rQOt4raJkCmVyu65W6MKP9SRjnSMwILBzfjpDEM3!VgPB0lwtM4Ws/0DG4UOlV6Xt75M/MwWaCax99BSoAsbJVgvwv8+FO8l6bJxBq+VtasqDC//1XDhq X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2937 Xref: feeder.eternal-september.org comp.lang.vhdl:5288 On 9/8/2011 12:15 PM, Jessica Shaw wrote: >> Kevin Jennings wrote: >> For example, you didn't state any latency requirement on when the >> count must be valid relative to the assertion of 'stop'. If there is >> none, than one can play the simple game of having four counters >> running on different phases of 200 MHz. At the end, simply add the >> value of the four counters to get the final result. >> > > Can you advice more on how can I use four counters running on > different phases of 200MHz. I am little confused about different > phases. Can you advice some application notes or examples. > > Thanks > jess > Different phases as in, you run your external 200 MHz clock into a PLL (or DLL, depending on what the FPGA you're using has, they'll serve the same purpose) and bring out four 200 MHz clocks, each 1.25 ns apart from the next (4 * 1.25 ns = 5 ns = 1/200 MHz). Then you have four counters with four enable flip-flops, each running on a different one of those clock phases. Your start and stop pulses control the enable flops. Then you put some downstream logic on one of those clock phases that, after you've gotten a stop pulse, adds up the results of those four counters. The fact that you'll have some number of counters with N counts, and some with N-1 gives you an effective 1.25 ns resolution on your timing. -- Rob Gaddi, Highland Technology Email address is currently out of order From newsfish@newsfish Fri Feb 3 13:14:49 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Would you like the alternative to Zero Ohm? Date: Fri, 09 Sep 2011 17:21:17 +0300 Organization: A noiseless patient Spider Lines: 65 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 9 Sep 2011 14:21:18 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="2197"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19OkyqIL/KaY6KucD1SCBO61dvn9kSAFas=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0) Gecko/20110812 Thunderbird/6.0 Cancel-Lock: sha1:ZDJuH5isohrDGmUHehqFKh24o6c= Xref: feeder.eternal-september.org comp.lang.vhdl:5289 Notorious Ben Cohen's Zero Ohm model is recommended wherever you need a delay in a bi-dir line. But, have you tried it yourself? It corrupts your signal as much as the delay it is asked to introduce (see the diagrams http://valjok.blogspot.com/2011/08/half-duplex-better-than-zero-ohm.html)! I had to simulate a DDR-400 (a transfer every 2.5 ns) with 4.5 ns borad delay. No chance. It seems that Ben introduces the Z-state into target signal every driver transaction. This is done to break feedbacks in bi-dir channel. However, the lines are normally half-duplex. There is no need to simulate the reflections or another end driver while current driver is broadcasting. User introduces the z-state moments himslef when switches between signle-driver modes. He needs z-gap to prevent driver congestion. He does this in appropriate time, only once per direction switch. Based on that, I have created an alternative switch model. It detects the driver broadcast direction automatically, by watching who breaks the z-state, and serves as repeater then. entity Z_SWITCH is generic (LAG: time := 1 ns); port ( A, B: inout std_logic := 'Z' -- must be Z-separated or A takes precedence ); end entity; architecture WAIT_FOR_Z of Z_SWITCH is procedure P(constant NAME: string; signal X: in std_logic; variable X_TIMEOUT: in time; signal Y: out std_logic; variable Y_TIMEOUT: inout time) is begin if now > X_TIMEOUT and X /= 'Z' then L1: loop Y <= transport X after LAG; Y_TIMEOUT := now + LAG; if X = 'Z' then exit L1; end if; wait on X; end loop; end if; end procedure; begin process variable A_TO, B_TO: time := - 10 ns; -- signal will propagate up to this time, do not loop it back. begin wait on A, B; P("A->B", A, A_TO, B, B_TO); -- until A iz not Z P("B->A", B, B_TO, A, A_TO); -- until B is not Z end process; end architecture; This defeats the joy of simulation the strong-weak interaction during the congestion. But, at least, the normal signal is not destroyed. No more corruption instead of delay! Do you still give links to Ben Cohen? From newsfish@newsfish Fri Feb 3 13:14:49 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b20g2000vbz.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Sat, 10 Sep 2011 18:05:18 -0700 (PDT) Organization: http://groups.google.com Lines: 77 Message-ID: <60c48af4-3198-4237-96ff-2565ad27a9a7@b20g2000vbz.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315703217 31657 127.0.0.1 (11 Sep 2011 01:06:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 11 Sep 2011 01:06:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b20g2000vbz.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5290 On Sep 8, 3:15=A0pm, Jessica Shaw wrote: > > Kevin Jennings wrote: > > For example, you didn't state any latency requirement on when the > > count must be valid relative to the assertion of 'stop'. =A0If there is > > none, than one can play the simple game of having four counters > > running on different phases of 200 MHz. =A0At the end, simply add the > > value of the four counters to get the final result. > > Can you advice more on how can I use four counters running on > different phases of 200MHz. I am little confused about different > phases. Can you advice some application notes or examples. > Actually, you don't need to run four different phases of the clock as I mentioned, you can run the four counters on the same 200 MHz clock that is phase locked to the 800 MHz which might be a simpler situation to describe in this forum. Either approach is viable, there can be other ways to accomplish the same thing as well.. Start with a free running two bit counter that is clocked by your 800 MHz clock. If on a particular clock cycle you want to advance your counter by 1 then what you would do is set a bit in a four bit vector. Something like this... signal Counter_Enable: std_ulogic_vector(0 to 3); signal Counter: natural range Counter_Enable'range; ... if rising_edge(Clock_800MHz) then -- Free running counter if (Reset =3D '1') or (Counter =3D 3) then Counter <=3D 0; Counter_Enable <=3D (others =3D> '0'); else Counter <=3D Counter + 1; end if; Counter_Enable(Counter) <=3D Count_By_1; end if; Now assume that you have a 200 MHz clock that is phase locked to the 800 MHz clock. The first thing you would want to do is resynchronize the Counter_Enable to the slower clock like this... Counter_Enable_Sync_200M <=3D Counter_Enable when rising_edge(Clock_200M); The reason for this is that the individual bits of 'Counter_Enable', since they are clocked by the 800 MHz clock, will be changing at times that will make meeting timing difficult. By syncing them to the 200 MHz clock, now you have a counter enable that will be there for an entire 200 MHz clock cycle. So you use those to bump the individual counters like this... for i in Counter_Enable_Sync_200M'range loop if (Counter_Enable_Sync_200M =3D '1') then Counter_200M(i) <=3D Counter_200M(i) + 1; end if; end loop; At the end, you add the four counters up to get the final output... Counter_Out <=3D Counter_200M(0) + Counter_200M(1) + Counter_200M(2) + Counter_200M(3) Also, note that each of the four 'Counter_200M' counters would only need to be 14 bits rather than 16 since at most they count one time every four of the 800 MHz clocks. I've left out some of the details, but outlined it enough that you should be able to follow the general idea. One other point that you've left out of your description is what is generating the 700-800 MHz input that you are counting in the first place. What I've described presumes that you have such a clock cycle and can then derive the slower clock from that faster clock...maybe that's your situation, maybe not. Like I said before, you haven't described enough for anyone to know what problem is being solved. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!eb1g2000vbb.googlegroups.com!not-for-mail From: "hdlcohen@gmail.com" Newsgroups: comp.lang.vhdl Subject: Re: Would you like the alternative to Zero Ohm? Date: Sun, 11 Sep 2011 06:06:30 -0700 (PDT) Organization: http://groups.google.com Lines: 89 Message-ID: <3a7fc369-ae30-4fff-9bb7-e254f494c075@eb1g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 68.5.246.16 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315746390 26644 127.0.0.1 (11 Sep 2011 13:06:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 11 Sep 2011 13:06:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: eb1g2000vbb.googlegroups.com; posting-host=68.5.246.16; posting-account=05LLWQoAAAB_doFp3zl0iF3Zv0ie3dM1 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/534.30 (KHTML, like Gecko) Ubuntu/11.04 Chromium/12.0.742.112 Chrome/12.0.742.112 Safari/534.30,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5291 On Sep 9, 7:21=A0am, valtih1978 wrote: > Notorious Ben Cohen's Zero Ohm model is recommended wherever you need a > delay in a bi-dir line. But, have you tried it yourself? > > It corrupts your signal as much as the delay it is asked to introduce > (see the diagramshttp://valjok.blogspot.com/2011/08/half-duplex-better-th= an-zero-ohm.h... > I had to simulate a DDR-400 (a transfer every 2.5 ns) with 4.5 ns borad > delay. No chance. > > It seems that Ben introduces the Z-state into target signal every driver > transaction. This is done to break feedbacks in bi-dir channel. However, > the lines are normally half-duplex. There is no need to simulate the > reflections or another end driver while current driver is broadcasting. > User introduces the z-state moments himslef when switches between > signle-driver modes. He needs z-gap to prevent driver congestion. He > does this in appropriate time, only once per direction switch. Based on > that, I have created an alternative switch model. It detects the driver > broadcast direction automatically, by watching who breaks the z-state, > and serves as repeater then. > > entity Z_SWITCH is > =A0 =A0 generic (LAG: time :=3D 1 ns); > =A0 =A0 port ( > =A0 =A0 =A0 =A0 A, B: inout std_logic :=3D 'Z' -- must be Z-separated or = A takes > precedence > =A0 =A0 ); > end entity; > > architecture WAIT_FOR_Z of Z_SWITCH is > procedure P(constant NAME: string; signal X: in std_logic; variable > X_TIMEOUT: in time; > =A0 =A0 signal Y: out std_logic; variable Y_TIMEOUT: inout time) is > begin > =A0 =A0 =A0 =A0 if now > X_TIMEOUT and X /=3D 'Z' then > =A0 =A0 =A0 =A0 =A0 =A0 L1: loop > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Y <=3D transport X after LAG; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Y_TIMEOUT :=3D now + LAG; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if X =3D 'Z' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 exit L1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait on X; > =A0 =A0 =A0 =A0 =A0 =A0 end loop; > =A0 =A0 =A0 =A0 end if; > > end procedure; > > begin > > =A0 =A0 process > =A0 =A0 =A0 =A0 variable A_TO, B_TO: time :=3D - 10 ns; -- signal will pr= opagate > up to this time, do not loop it back. > =A0 =A0 begin > =A0 =A0 =A0 =A0 wait on A, B; > =A0 =A0 =A0 =A0 P("A->B", A, A_TO, B, B_TO); -- until A iz not Z > =A0 =A0 =A0 =A0 P("B->A", B, B_TO, A, A_TO); -- until B is not Z > =A0 =A0 end process; > > end architecture; > > This defeats the joy of simulation the strong-weak interaction during > the congestion. But, at least, the normal signal is not destroyed. No > more corruption instead of delay! > > Do you still give links to Ben Cohen? Links to my models is available from VhdlCohen PublishingListing of directory: /vhdlcohen/vhdl http://bit.ly/pCu5Xx I also uploaded it http://systemverilog.us/zohm0_ea.vhd There is also http://systemverilog.us/switch1.vhd -------------------------------------------------------------------------- Ben Cohen (831) 345-1759 http://www.systemverilog.us/ [e-mail address removed] * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example, 2001 ISBN 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115 -------------------------------------------------------------------------- From newsfish@newsfish Fri Feb 3 13:14:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!l4g2000vbz.googlegroups.com!not-for-mail From: fl Newsgroups: comp.lang.vhdl Subject: Is there delta=0 except at the beginning moment? Date: Sun, 11 Sep 2011 07:24:46 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: NNTP-Posting-Host: 98.242.174.50 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315751087 10643 127.0.0.1 (11 Sep 2011 14:24:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 11 Sep 2011 14:24:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l4g2000vbz.googlegroups.com; posting-host=98.242.174.50; posting-account=SZ_svQkAAACWRFG2bDA-zgq8ILyl4-vo User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; FCTB100229; GTB7.1; EasyBits GO v1.0; InfoPath.2; OfficeLiveConnector.1.3; OfficeLivePatch.0.0; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; XF_mmhpset),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5292 Hi, I find that only at the simulation beginning that delta =0. Other time it is at least +1, or larger. I want to know that it is possible that delta=0 in the middle of simulation? Thanks. From newsfish@newsfish Fri Feb 3 13:14:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sun, 11 Sep 2011 18:20:23 -0500 Date: Mon, 12 Sep 2011 00:20:23 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0.2) Gecko/20110906 Thunderbird/6.0.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Is there delta=0 except at the beginning moment? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: Lines: 18 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-Oc5xi0wPt9N6QICUaPpG+0k3Snlx/LxeGRzpzhyPc2I1k6KvrqW+6pi6z64ZN18VeSdlesd0CGecC8e!W/W6m/04dPQzNWRkPItftOjkJk02haQuZDXqPycnz3Z5wokBaoe6+EiqV2+dZrKlA9YfUqxCsRfO!YIxufgoExa1YyDOLBZF6vPawuyY= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1651 Xref: feeder.eternal-september.org comp.lang.vhdl:5293 On 11/09/11 15:24, fl wrote: > Hi, > I find that only at the simulation beginning that delta =0. Other time > it is at least +1, or larger. I want to know that it is possible that > delta=0 in the middle of simulation? > > Thanks. What do mean by "in the middle of the simulation"? If you set a break point, or single step the code, you can see delta=0. regards Alan P.S. Or write a simulation where time doesn't advance :-) -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:14:51 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!j19g2000yqc.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Local packages Date: Mon, 12 Sep 2011 00:46:09 -0700 (PDT) Organization: http://groups.google.com Lines: 48 Message-ID: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315813569 14517 127.0.0.1 (12 Sep 2011 07:46:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 12 Sep 2011 07:46:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: j19g2000yqc.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-HTTP-Via: 1.1 squid3 (squid/3.0.STABLE8) X-Google-Web-Client: true X-Google-Header-Order: HUALESRCVFNK X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.21) Gecko/20110830 Firefox/3.6.21,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5294 Hi, I want to use VHDL-2008 generic packages so that I can pass a generic to the package from the generic of a component (in which the package is used), I read about "local packages" in VHDL-2008, but the problem with them is that I need the package instantiation after the generic part and before the port declaration of the component. But this is not the declarative part of an entity. Is that kind of generic structure possible at all in VHDL-2008? library ieee; use ieee.std_logic_1164.all; package pkg_test is generic( NUM : positive :=77); type t_type is array(0 to NUM) of std_logic_vector(NUM downto 0); end package; library ieee; use ieee.std_logic_1164.all; entity test_component is generic( NUM_TEST : positive := 4 ); -- THIS is NOT the declarative part of an entity library work; use work.pkg_test.all; package pkg_test_inst is new work.pkg_test -- Local Package 2008 ???? generic map( NUM => NUM_TEST); library work; use work.pkg_test_inst.all; port( SigIn : in t_type; SigOut : out t_type ); -- THIS is the declarative part of an entity end entity; architecture test of test_component is begin SigOut <= SigIn; end architecture; From newsfish@newsfish Fri Feb 3 13:14:51 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 12:01:17 +0300 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 12 Sep 2011 09:01:17 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="19243"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/9qvZK1enxKTpV6BsvyUYo/Ljs6CdJ50c=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 In-Reply-To: <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Cancel-Lock: sha1:XmWCKQeBDJiflNV/yOvdY/IsVjQ= Xref: feeder.eternal-september.org comp.lang.vhdl:5295 On 7.09.2011 23:38, Jessica Shaw wrote: > Hi, > > Why is it dfficult? > > Jess Because FPGA gates _are emulated_. You might wonder why ASICs, easily running at 4 GHz today, do only at 400 MHz in case of FPGAs. FPGAs are intended to emulate the logic. They do it much faster and more efficiently than SW emulation on usual processor-based (super-) computers. However, emulation is still achieved through configuration of the real HW. That means that you must have abudance of HW resources that may be configured into this or that mode. Some true gates are used as switches rather than do useful job. Others stay unused because FPGA designers are not application aware and, therefore, cannot be sure which resources will be necessary, they cannot optimize placement and routing for user to minimize the paths. In result, you have 10x larger, more expensive, power-hungry device than ASIC. It is as much slower because signals must pass through configuration switches and suboptimal routing, around unused resources and drive unused gates. Comp.arch.fpga is the place to ask for FPGA caps. From newsfish@newsfish Fri Feb 3 13:14:52 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Martin Thompson Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 11:02:34 +0100 Organization: TRW Conekt Lines: 64 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: individual.net Tct3GJCsi8iE7iBk3G8vRQ+LIfPQln7Tx1LqpmAQJnENrV++g= Cancel-Lock: sha1:nzUUMCuFWM7tToQ0Iz/KNgqpApo= sha1:1JB6GFKQ2Ke5zpBX6DpZlQ6ankg= User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.1.50 (windows-nt) Xref: feeder.eternal-september.org comp.lang.vhdl:5296 valtih1978 writes: > > Because FPGA gates _are emulated_. > I'm not sure that's a fair representation! True, there are no user-accessible "gates" as such, but there are a plethora of low-level configurable logic elements of various sorts, which are real enough! > You might wonder why ASICs, easily running at 4 GHz today, do only at > 400 MHz in case of FPGAs. > > FPGAs are intended to emulate the logic. FPGAs are intended to *implement* some logic. If you want to use it for the narrow world of emulating an ASIC, that's fine. I don't. I build products with them. > They do it much faster and more > efficiently than SW emulation on usual processor-based (super-) > computers. However, emulation is still achieved through configuration of the > real HW. That means that you must have abudance of HW resources that may be > configured into this or that mode. Those who target FPGAs must be well aware of these resources, so that they use them to their best advantage. Just throwing an ASIC netlist at them will not realise the sort of results that an experienced and talented FPGA user will. (I had "designer" rather than "user" in here first, but that might cause confusion with the paragraph below...) > Some true gates are used as switches rather than do useful job. Others > stay unused because FPGA designers are not application aware and, > therefore, cannot be sure which resources will be necessary, I assume you mean the designers of the FPGA silicon, not people like me who design logic to in said silicon. Who are often called FPGA designers as well... > they cannot optimize placement and routing for user to minimize the > paths. In result, you have 10x larger, more expensive, power-hungry > device than ASIC. It is as much slower because signals must pass > through configuration switches and suboptimal routing, around unused > resources and drive unused gates. On the upside, they are * Cheap enough * Small enough * Low power enough for an awful lot of real applications outside of "emulating ASICs". And they have vastly lower NRE and are completely field reconfigurable (unlike ASICs). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardware From newsfish@newsfish Fri Feb 3 13:14:52 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 17:39:14 +0300 Organization: A noiseless patient Spider Lines: 27 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 12 Sep 2011 14:39:15 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="18000"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19h2ad0CPmmraexUEAx1/LKyNRJRRIY52g=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: Cancel-Lock: sha1:ErgdEyKrcIUdtRx46Tk9PxP2e18= Xref: feeder.eternal-september.org comp.lang.vhdl:5297 > but there are a plethora of low-level configurable logic elements of various sorts, which are real enough! In which point do I say otherwise? > FPGAs are intended to *implement* some logic. If you want to use it for the narrow world of emulating an ASIC, that's fine. I don't. I build products with them. > On the upside, they are * Cheap enough * Small enough * Low power enough * And they have vastly lower NRE and are completely field reconfigurable (unlike ASICs). That is why we emulate our circuits in FPGAs rather than produce them in silicon. Please, do not confuse the emulation with simulation (aka prototyping). Both emulation and simulation mimic some object. The difference is that in simulation (prototyping) you study the behaviour, including internals of your model. Using emulator, you do not care about the model. The emulation means (at least as how understand it) that there is some SW (machine or circuit) that runs on top of another, HW layer (machine or circuit). Emulated part will be more flexible but executes 10x slower. The prototypes are simulations implemented in FPGA. FPGAs are ideal to speed up simulation. But, they are also ideal for emulating any user logic outside the domain of logic simulation. From newsfish@newsfish Fri Feb 3 13:14:52 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!1g2000vbu.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 10:41:41 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <8270c1ed-6c77-48d8-a16c-efdabf963b76@1g2000vbu.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> <4MmdneiG7oknrPTTnZ2dnUVZ_qednZ2d@lmi.net> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1315849301 32305 127.0.0.1 (12 Sep 2011 17:41:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 12 Sep 2011 17:41:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 1g2000vbu.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5298 Rob Wrote > Different phases as in, you run your external 200 MHz clock into a PLL > (or DLL, depending on what the FPGA you're using has, they'll serve the > same purpose) and bring out four 200 MHz clocks, each 1.25 ns apart from > the next (4 * 1.25 ns =3D 5 ns =3D 1/200 MHz). > > Then you have four counters with four enable flip-flops, each running on > a different one of those clock phases. =A0Your start and stop pulses > control the enable flops. > > Then you put some downstream logic on one of those clock phases that, > after you've gotten a stop pulse, adds up the results of those four > counters. =A0The fact that you'll have some number of counters with N > counts, and some with N-1 gives you an effective 1.25 ns resolution on > your timing. Will I have four stop and start pulses to control the flip flops? I did not understand the part saying that The fact that you'll have some number of counters with Ncounts, and some with N-1 gives you an effective 1.25 ns resolution on your timing. Thans jess From newsfish@newsfish Fri Feb 3 13:14:53 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!bl1g2000vbb.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 09:21:34 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315849684 3551 127.0.0.1 (12 Sep 2011 17:48:04 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 12 Sep 2011 17:48:04 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: bl1g2000vbb.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5299 Valtih, I don't believe your definitions of emulation and simulation are commonly used in industry, but I see your point (with your clarification). I agree with Martin however, that FPGAs IMPLEMENT logic. We often think of them as emulating gates, but modern FPGA synthesis tools do not compile a design down to gates and then emulate the (groups of) gates with FPGA resources, they compile the design to FPGA resources directly. Descriptions of the implementation (ntelists, etc.) often use familiar sounding gate terminology, but that is a documentation artifact, not based on how the synthesis tool does its job. The implemented logic may be used as a prototype for an ASIC that it is emulating (industry standard definition thereof, as a replacement for, or augmentation of, simulation). Or the implemented logic may be the final product. If you designed a board 20+ years ago, you would not say that PALs and SSI circuits (74xx) emulated the logic you wanted, you would say they IMPLEMENTED the logic you wanted. When I was in college, we studied IMPLEMENTING logic functions (often represented as series of gates, truth tables, sum-of-products, etc.) using SSI components like multiplexers, decoders, etc. When I got into industry, PALs/PLAs were the main tool of choice, and such tricks were "obsolete". Little did I know that in a few short years, I would be dusting off those same tricks designing FPGAs (before FPGA synthesis got much better). Throwing a figure like "10x slower" around is a bit short-sighted. They can be 10x slower, but they can also be much less slower, depending on what you are trying to accomplish, and on the available resources in the FPGA device. Andy From newsfish@newsfish Fri Feb 3 13:14:53 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!d12g2000vba.googlegroups.com!not-for-mail From: Jessica Shaw Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter Date: Mon, 12 Sep 2011 12:31:18 -0700 (PDT) Organization: http://groups.google.com Lines: 9 Message-ID: <2983202c-4361-470d-b79b-f607d3937695@d12g2000vba.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <9cq9b6Fso4U1@mid.uni-berlin.de> <38c41b9f-54c2-44d5-980d-738779fd1b5c@e14g2000yqi.googlegroups.com> <413c9b71-ded0-4274-9fbc-d011bd63f159@o9g2000vbo.googlegroups.com> <60c48af4-3198-4237-96ff-2565ad27a9a7@b20g2000vbz.googlegroups.com> NNTP-Posting-Host: 75.99.47.75 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1315855878 3867 127.0.0.1 (12 Sep 2011 19:31:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 12 Sep 2011 19:31:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d12g2000vba.googlegroups.com; posting-host=75.99.47.75; posting-account=iicy7AoAAAAv6C1ybBN40677Q2fKgiLK User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.0; WOW64; Trident/4.0; GTB7.1; SLCC1; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET4.0C; .NET CLR 3.0.30729; WinNT-A8I 10.03.2011; AskTbORJ/5.12.3.17451),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5300 Hi KJ, You are suggesting that I should use 800MHz clock and divided into four 200MHz clocks. Each clock will be running a counter. A two bit counter will be running on 800 MHz clock. Will the four counters have their own enbale, stop and start signals? Is free running counter is the "counter" defined as signal? jess From newsfish@newsfish Fri Feb 3 13:14:54 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: implementation vs. emulation Date: Tue, 13 Sep 2011 10:55:42 +0300 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 13 Sep 2011 07:55:43 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="6600"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/XE83vzZbOMotFVyxAXqLOq5Ew9k57obE=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> Cancel-Lock: sha1:CbxinI0R/Iaxw4dOOTjLq1KP010= Xref: feeder.eternal-september.org comp.lang.vhdl:5301 Thank you explaining the difference between implemention and emulation. Indeed, personal computers, ASICs, FPGAs are the technologies to implement user algorithms. You just say: implement that for me and compiler does the job. This is ok, but, I do not see why ASICs are different in this respect. There is Design Compiler. It does the same thing as FPGA-oriented synthesis - it maps HDL to the gates available in target technology (see them packed in LUTS, FPGA in technology view). More importantly, this abstraction from implementation details brings us away from from the question: _why universal computers are ten times slower than the special-purpose ones?_ Highlighting that synthesizer produces "soft gates" out of RTL description unveils the virtual computation on top of native one. This is important here because it answers Jessica's question. From newsfish@newsfish Fri Feb 3 13:14:54 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!o9g2000vbo.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Thu, 15 Sep 2011 08:52:09 -0700 (PDT) Organization: http://groups.google.com Lines: 23 Message-ID: <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316103441 25262 127.0.0.1 (15 Sep 2011 16:17:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 15 Sep 2011 16:17:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o9g2000vbo.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5302 On Sep 13, 2:55=A0am, valtih1978 wrote: > This is ok, but, I do not see why ASICs are > different in this respect. There is Design Compiler. It does the same > thing as FPGA-oriented synthesis - it maps HDL to the gates available in > target technology (see them packed in LUTS, FPGA in technology view). Don't be fooled by the pretty little pictures shown in Technology view. They are put there so we humans (who think in gates) can tell what function is being implemented by the LUT. It is not indicative of the way the Synplify tool works. If you doubt that, then why did Synopsys fail twice in the market with DC-based FPGA synthesis tools (before they bought Synplify)? Because they focused on gates, with a LUT-packer bolted on (same as most of the early FPGA tools, especially schematic capture based). Synplify and others were targeting FPGA resources directly. I begged Synopsys to add RAM inference to their FPGA Compiler II. They just asked; "Why would you need that?" Their competition already knew why, which is why we switched, in addition to vastly superior QOR. When they bought Synplicity, their FPGA synthesis business had been dwindled down to mostly ASIC customers who wanted to use FPGAs for ASIC emulation. Andy From newsfish@newsfish Fri Feb 3 13:14:55 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sat, 17 Sep 2011 19:14:21 +0300 Organization: A noiseless patient Spider Lines: 10 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Sep 2011 16:14:24 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="2568"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18ZRswT/9Fofr+KO1PwDQOfp/0x2DI03ZY=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> Cancel-Lock: sha1:CGR8iASSPSzNGM6dkjzbHfUdfig= Xref: feeder.eternal-september.org comp.lang.vhdl:5303 Support from the major FPGA vendor is very good. It is natural because HW achieves its supercomputer performance through the fine grain parallelism. It consists of millions of tiny parallel processors - the gates. Thus, it seems impossible to extract the available parallelism out of RTL description without compiling it into a netlist. Should it be a target fpga or virtual technology. Let's suppose you compile RTL directly into target fpga technology right away and, thus, achieve the most optimal FPGA implementation ever possible. How do you explain Jessica why you are still 10x behind ASIC? From newsfish@newsfish Fri Feb 3 13:14:55 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d18g2000yqm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sat, 17 Sep 2011 10:15:22 -0700 (PDT) Organization: http://groups.google.com Lines: 42 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316279838 14097 127.0.0.1 (17 Sep 2011 17:17:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 17 Sep 2011 17:17:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d18g2000yqm.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5304 On Sep 17, 12:14=A0pm, valtih1978 wrote: > > Let's suppose you compile RTL directly into target fpga technology right > away and, thus, achieve the most optimal FPGA implementation ever > possible. How do you explain Jessica why you are still 10x behind ASIC? I already explained the reason in my first post on this topic over a week ago, perhaps you should read the first half of the post. http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/73c00c74f67= 75d11/173b156f9e0a5825?hl=3Den#173b156f9e0a5825 To reiterate a bit, ASICs are single function parts, FPGAs are run- time programmable. At the lowest level, both parts are all built on the same basic technology and will have the same speed at that level (i.e. the transistor level). In order to provide run-time programmable parts, FPGAs are designed such that the end user does not have direct control all the way down to the transistor level. The primitive elements for a user for implementing logic in an FPGA are mostly look up tables and flip flops. There are no 'gates' that the user has control over. The reason that FPGAs exist at all is because there is market demand for a component that - Implements arbitrary logic where the ability to implement any design change is not limited by the FPGA, nor does it require payment to the FPGA supplier to implement the change. In other words, the cost and implementation time for a design change is completely under the control of the designer that *uses* the FPGA, not the supplier of the FPGA. - Other technologies such as ASICs and CPLDs have not been able to crush FPGAs out of the market. In fact, the opposite has been happening for a long time: ASICs and CPLDs design starts are being squeezed out by FPGA designs. The 'design cost' that a user will pay for choosing an FPGA over an ASIC is speed and power. The market currently supports many niches for implementing logic designs. FPGAs, CPLDs and ASICs fill different niches, they each are optimal for certain designs and sub-optimal for others...that's the way it is, get on with it. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:55 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sat, 17 Sep 2011 21:55:40 +0300 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sat, 17 Sep 2011 18:55:43 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="32075"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jpTauDbJn3OgklKXWls02sUpUgUkJT04=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: Cancel-Lock: sha1:NdyfLiuc+E8b/Co3WpFPyEQ5Q0w= Xref: feeder.eternal-september.org comp.lang.vhdl:5305 Actually, it was rhetoric question with the purpose to show that whether mapping to FPGA is immediate or undergoes virtual gate representation is not important for FPGA vs. ASIC performance. Regarding your marketing manifest, adding that "FPGAs are designed such that the end user does not have direct control all the way down to the transistor level" does not add very much to it. How do you run you design on FPGA if you have no control over its "gates"? Actually, it says that "we do not allow you to turn our general-purpose computer into app-specific one by design". I'm sure, that the problem is not a design. You cannot do that in principle. FPGA stays a fixed, hardwired general-purpose piece of computer. It executes user app at the higher level. In other words, it emulates user circuit rather than implements it natively. As any emulation, it is is 10x slower. 'Niches' do not change this principle. So, you cannot bypass this picture. From newsfish@newsfish Fri Feb 3 13:14:56 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!s20g2000yql.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sat, 17 Sep 2011 18:08:17 -0700 (PDT) Organization: http://groups.google.com Lines: 112 Message-ID: <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316308097 14621 127.0.0.1 (18 Sep 2011 01:08:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 18 Sep 2011 01:08:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s20g2000yql.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5306 On Sep 17, 2:55=A0pm, valtih1978 wrote: > Actually, it was rhetoric question with the purpose to show that whether > mapping to FPGA is immediate or undergoes virtual gate representation is > not important for FPGA vs. ASIC performance. > It appears that you don't even read your postings. Your stated question was "How do you explain Jessica why you are still 10x behind ASIC?" That's not a very good example of a 'rhetorical question'... > Regarding your marketing manifest, adding that "FPGAs are designed such > that the end user does not have direct control all the way down to the > transistor level" does not add very much to it. Actually it has everything to do with 'it', but you do not seem to be understanding 'it'. In this case, 'it' is the difference in system level performance of an ASIC versus and FPGA. The reason for that difference has to do with the fact that FPGA manufacturers saw a market need for a device that can implement arbitrary logic (like an ASIC can) but is user programmable. In order to implement the 'user programmable' part of their product, some of the potential performance of the raw silicon technology was used leaving less performance for the end user. FPGA manufacturers were not the first to see that need and market such a part they are one of many. > How do you run you > design on FPGA if you have no control over its "gates"? Here you're wrong on at least a couple of fronts: - FPGAs implement logic with lookup table memory, not in logic gates. - Since one can implement logic with lookup table memory and no gates the lack of 'control over its gates' is not relevant...there are no 'gates' to control and yet functional designs can be implemented just fine. - 'Gates' are not the real primitive device, they are themselves an abstraction. Transistors are the primitive. Control of voltage, current and charge is the game. - I never said anything about controlling 'gates' in the first place. What I said was "...does not have direct control all the way down to the transistor level". 'Transistors' are not 'gates'. Transistors can be used to implement a 'gate', but the reverse is not true. > Actually, it > says that "we do not allow you to turn our general-purpose computer into > app-specific one by design". That's your interpretation...I disagree with it completely, but you can have that. Computers have a definition (perhaps you should look up generally accepted definitions), but those generally accepted definitions do not include 'FPGA' or 'ASIC'. An FPGA or ASIC or discrete logic gates or even discrete transistors can be used to implement a computer. However, none of those devices are in any a 'general-purpose computer' or any other type of computer. > I'm sure, that the problem is not a design. > You cannot do that in principle. FPGA stays a fixed, hardwired > general-purpose piece of computer. Not true at all...see previous paragraph...and you should probably research the definition of computer as well. > It executes user app at the higher > level. As does an ASIC design...unless you really think that ASIC designers design everything down to the transistor level. Gates are an abstraction. A high level design language like VHDL can be used to describe an intended function. That description can be used to implement a design in many technologies. The technology chosen does not change the 'user app' therefore that 'user app' cannot be at any different level then if a different technology choice had been used. > In other words, it emulates user circuit rather than implements > it natively. Not true. From a black box perspective, an FPGA and an ASIC can be designed to implement exactly the same function. They simply have different primitive elements that can be manipulated by the designer. The choice of technology used to implement a design does not imply that one is an emulation of the other. > As any emulation, it is is 10x slower. > Not true either. A discrete logic gate implementation or a discrete transistor implementation would be much slower than an FPGA...but they would not be an emulation as defined by most reasonable sources. But you appear to suggest with this statement that an implementation that is 10x slower is an emulation. If so, I've provided the counter- example to your statement, thereby disproving it. Perhaps if you peruse the following links and do some more research, you will discover what the word emulation is generally accepted to mean: - http://en.wikipedia.org/wiki/Emulation - http://www.merriam-webster.com/dictionary/emulation?show=3D0&t=3D13163066= 55 > So, you cannot bypass this picture. No idea what picture you think is being bypassed. You can choose to use the words 'implementation' and 'emulation' how you want, that's your choice. However, since those words already have accepted definitions that are different than what you have chosen don't expect to get much acceptance of your usage. This is the last I have to say on this thread. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:14:56 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sun, 18 Sep 2011 13:37:48 +0300 Organization: A noiseless patient Spider Lines: 49 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Sun, 18 Sep 2011 10:37:51 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="28712"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+vK9A1fr3EZOVudq+8+qeQh1vRQ2wMyBA=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> Cancel-Lock: sha1:BDe0U3058noAIjcGDK0eXvcLCeM= Xref: feeder.eternal-september.org comp.lang.vhdl:5307 > Actually it has everything to do with 'it', but you do not seem to be understanding 'it'. Thanks. Next time, I will know that redundancy adds very much because "it also has to do with it". > Not true at all...see previous paragraph...and you should probably research the definition of computer as well. I know the right definition! Computers are the people who do computations! FPGAs fall into absolutely different category! > Not true either. A discrete logic gate implementation or a discrete transistor implementation would be much slower than an FPGA Good job. To be more honest, you had to compare the latest integral nanoscale desktop processor against large mechanical relay logic from 30-ties. The first computers used that technology. This way, you would have proven much stronger thesis: our flexible SW completely outdoes any HW implementation! Following this line of reasoning, we can recall that first uProcessors were running at 1 mhz. Today FPGAs can emulate them 100 times faster. Now, people must stop thinking that FPGAs are slower than ASIC implementation. I just cannot understand why today 4 GHz processor can run at 400 mhz maximum when implemented in FPGA? >As does an ASIC design...unless you really think that ASIC designers design everything down to the transistor level. Gates are an abstraction. Transistors are an abstraction. Сopper and electrons are an abstraction. Everything is and abstraction. We like abstractions because they help use to understand. Me, Xilinx and Synopsys use gate netilst abstraction to understand the implementation. > You can choose to use the words 'implementation' and 'emulation' how you want. However, since those words already have accepted definitions that are different than what you have chosen don't expect to get much acceptance of your usage. How picture of user gates emulated by FPGA can not correspond to this definition? > This is the last I have to say on this thread. Thank you for the warning. It would be very nice. We can be prepared. From newsfish@newsfish Fri Feb 3 13:14:57 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sun, 18 Sep 2011 16:11:03 +0300 Organization: A noiseless patient Spider Lines: 4 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 18 Sep 2011 13:11:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="17267"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qfvlxnVMIqXTIE4XpmCk38llSomQC33I=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> Cancel-Lock: sha1:STmscLPY8gjtgrfkBpV5fCkAVpc= Xref: feeder.eternal-september.org comp.lang.vhdl:5308 The very name, FPGA means "gate array", says that FPGA provides the programmable gates. They are virtual abstractions, like you like to say, implemented by hard silicon gates at the bottom level. Don't be scared to distribute this view. From newsfish@newsfish Fri Feb 3 13:14:57 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l7g2000vbz.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Sun, 18 Sep 2011 13:04:38 -0700 (PDT) Organization: http://groups.google.com Lines: 11 Message-ID: <73c6232a-bc24-43b7-8f27-964baa297e29@l7g2000vbz.googlegroups.com> References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> NNTP-Posting-Host: 192.35.35.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316376627 14070 127.0.0.1 (18 Sep 2011 20:10:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 18 Sep 2011 20:10:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l7g2000vbz.googlegroups.com; posting-host=192.35.35.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5309 On Sep 18, 5:37=A0am, valtih1978 wrote: > I just cannot understand why today 4 GHz processor can > run at 400 mhz maximum when implemented in FPGA? That 4 GHz processor won't run at 4 GHz if it is implemented in ASIC gates either. Does that mean that ASICs only emulate circuits too? (rhetorical!) Andy From newsfish@newsfish Fri Feb 3 13:14:58 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Mon, 19 Sep 2011 12:57:19 +0300 Organization: A noiseless patient Spider Lines: 3 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> <73c6232a-bc24-43b7-8f27-964baa297e29@l7g2000vbz.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Sep 2011 09:57:20 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="QBT+O74JS95FuBrjnY7M3A"; logging-data="14498"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19E0StvAOZEWyQ+c4R3QWQ01v+RlX9HfoE=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:6.0.2) Gecko/20110902 Thunderbird/6.0.2 In-Reply-To: <73c6232a-bc24-43b7-8f27-964baa297e29@l7g2000vbz.googlegroups.com> Cancel-Lock: sha1:rgeiOQh2UtC2VYrcobDcQcMrTUQ= Xref: feeder.eternal-september.org comp.lang.vhdl:5310 How 4 GHz ASIC, that is capable running at 4 GHz, cannot run at 4 GHz? Sounds like a controversy. From newsfish@newsfish Fri Feb 3 13:14:58 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u20g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: implementation vs. emulation Date: Mon, 19 Sep 2011 11:11:18 -0700 (PDT) Organization: http://groups.google.com Lines: 10 Message-ID: References: <2M2dnZOJP6yCSPrTnZ2dnUVZ_tWdnZ2d@lmi.net> <90c9dcf7-7362-4afc-aff2-2b5357c60a1a@s20g2000yql.googlegroups.com> <86f17352-54ce-4c87-80b2-7e284421f9ec@bl1g2000vbb.googlegroups.com> <3c10afab-7f01-4e19-a564-af5c43e42eaf@o9g2000vbo.googlegroups.com> <4f964626-b302-4ea8-8e77-fe5540a0992c@s20g2000yql.googlegroups.com> <73c6232a-bc24-43b7-8f27-964baa297e29@l7g2000vbz.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316456237 31330 127.0.0.1 (19 Sep 2011 18:17:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 19 Sep 2011 18:17:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u20g2000yqj.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5311 On Sep 19, 4:57=A0am, valtih1978 wrote: > How 4 GHz ASIC, that is capable running at 4 GHz, cannot run at 4 GHz? > Sounds like a controversy. No, just function-specific limitations on clock rate. Depends on what you are trying to do on the chip. Just because a technology is rated for a given maximum clock rate, does not mean you can calculate pi to the millionth decimal place in one clock cycle on it. Andy From newsfish@newsfish Fri Feb 3 13:14:59 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: churchy Newsgroups: comp.lang.vhdl Subject: nonstandard use Date: Wed, 21 Sep 2011 11:41:37 -0700 Organization: A noiseless patient Spider Lines: 11 Message-ID: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Injection-Info: mx04.eternal-september.org; posting-host="BVCeUgoIuRmdCpXoYafBdg"; logging-data="18918"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18hXF5C8W+tJYwpY7TqQRHZxc6O6RgoamY=" User-Agent: Alpine 2.00 (BSF 1167 2008-08-23) Cancel-Lock: sha1:exUmRRcresJ1PoLU6IMoDetBNaM= X-X-Sender: ron@localhost Xref: feeder.eternal-september.org comp.lang.vhdl:5312 Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard "semi-analog" manner? Doing things like using a gate as a comparator etc. For example, can leftover gates in a device be used to clock the device with something like the classic 2 not, 2 resistor & a cap oscillator? CPLDs are nominally still gates but it seem like FPGA might get a little weird with this though basically externally both ae supposed to look like simple logic. 3ch From newsfish@newsfish Fri Feb 3 13:14:59 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed1.swip.net!uio.no!news.ctrl-c.liu.se!nntp Newsgroups: comp.lang.vhdl Subject: Re: nonstandard use Message-ID: From: Andreas Ehliar Date: 21 Sep 11 21:29:05 CEST References: Nntp-Posting-Host: sabor.isy.liu.se User-Agent: slrn/0.9.8.1pl1 (Linux) Lines: 18 Xref: feeder.eternal-september.org comp.lang.vhdl:5313 On 2011-09-21, churchy wrote: > Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard > "semi-analog" manner? Doing things like using a gate as a comparator etc. > I wouldn't recommend it, but you can certainly do something like this. You can certainly implement something like a ring oscillator in an FPGA if you felt like it. One of the neatest ways to abuse an FPGA to do analog processin that I've seen can be seen on bunnie's blog at http://www.bunniestudios.com/wordpress/?page_id=22 and http://www.bunniestudios.com/blog/?page_id=24 (a way to create a DAC using just an FPGA and some resistors). And another favourite: http://www.informatics.sussex.ac.uk/users/adrianth/cacm99/node3.html http://www.informatics.sussex.ac.uk/users/adrianth/ascot/paper/paper.html /Andreas From newsfish@newsfish Fri Feb 3 13:14:59 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!i23g2000yqm.googlegroups.com!not-for-mail From: Jezmo Newsgroups: comp.lang.vhdl Subject: Cambridge U.K and the use of verilog Date: Sat, 24 Sep 2011 13:13:32 -0700 (PDT) Organization: http://groups.google.com Lines: 4 Message-ID: <39bafea5-2662-4baa-b2d5-5a52eed69521@i23g2000yqm.googlegroups.com> NNTP-Posting-Host: 86.135.45.186 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1316895315 1287 127.0.0.1 (24 Sep 2011 20:15:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 24 Sep 2011 20:15:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i23g2000yqm.googlegroups.com; posting-host=86.135.45.186; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.186 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5314 Does anyone know why there is a sudden increase in the number of cambridge companies asking for new hires who work in verilog ? I hope it isn't down to an increase in the number of American CTOs who don't understand VHDL. From newsfish@newsfish Fri Feb 3 13:15:00 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!hd1g2000vbb.googlegroups.com!not-for-mail From: Jezmo Newsgroups: comp.lang.vhdl Subject: Re: nonstandard use Date: Sat, 24 Sep 2011 13:47:46 -0700 (PDT) Organization: http://groups.google.com Lines: 15 Message-ID: <0f042f30-c8d6-4757-8997-3ced9167dde1@hd1g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 86.135.45.186 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1316897369 22499 127.0.0.1 (24 Sep 2011 20:49:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 24 Sep 2011 20:49:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: hd1g2000vbb.googlegroups.com; posting-host=86.135.45.186; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.186 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5315 On Sep 21, 7:41=A0pm, churchy wrote: > Is it reasonable to use the gates in CPLD/FPGA "gates" in a nonstandard > "semi-analog" manner? Doing things like using a gate as a comparator etc. > > For example, can leftover gates in a device be used to clock the device > with something like the classic 2 not, 2 resistor & a cap oscillator? > > CPLDs are nominally still gates but it seem like FPGA might get a little > weird with this though basically externally both ae supposed to look like > simple logic. > > =A0 =A03ch It is possible with CPLDs and I have done it myself, I doubt that it would work with FPGAs due to the complex nature of the output drivers. From newsfish@newsfish Fri Feb 3 13:15:00 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!g33g2000yqc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Cambridge U.K and the use of verilog Date: Mon, 26 Sep 2011 01:01:39 -0700 (PDT) Organization: http://groups.google.com Lines: 8 Message-ID: <341b7381-bbec-45ce-b0ba-d9b0265e3007@g33g2000yqc.googlegroups.com> References: <39bafea5-2662-4baa-b2d5-5a52eed69521@i23g2000yqm.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1317024367 27366 127.0.0.1 (26 Sep 2011 08:06:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 26 Sep 2011 08:06:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g33g2000yqc.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.2) Gecko/20100101 Firefox/6.0.2,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5316 On Sep 24, 9:13=A0pm, Jezmo wrote: > Does anyone know why there is a sudden increase in the number of > cambridge companies asking for new hires who work in verilog ? I hope > it isn't down to an increase in the number of American CTOs who don't > understand VHDL. Is it not just a recruitment drive by the local ASIC producers, whom I always understood to be more common verilog users than VHDL? From newsfish@newsfish Fri Feb 3 13:15:01 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!o11g2000yqc.googlegroups.com!not-for-mail From: postcy postcy Newsgroups: comp.lang.vhdl Subject: Webhosting, Domain Name, Data Center Cyprus, Hosting Services Date: Tue, 27 Sep 2011 00:01:14 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <7d77aa9d-e451-43b1-bd45-640e9ac25c60@o11g2000yqc.googlegroups.com> NNTP-Posting-Host: 183.82.117.168 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1317106987 14926 127.0.0.1 (27 Sep 2011 07:03:07 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Sep 2011 07:03:07 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o11g2000yqc.googlegroups.com; posting-host=183.82.117.168; posting-account=9MfT4AoAAACUO7EaKg6GTqcWUhlqMvMQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22 GTB7.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5317 Webhosting =96 postcy - a leading web hosting company. We offer webhosting, domain name, data center cyprus, hosting services at affordable cost.for more details www.postcy.com for more details: http://www.postcy.com From newsfish@newsfish Fri Feb 3 13:15:01 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z20g2000vbl.googlegroups.com!not-for-mail From: Jezmo Newsgroups: comp.lang.vhdl Subject: Re: Cambridge U.K and the use of verilog Date: Tue, 27 Sep 2011 01:23:48 -0700 (PDT) Organization: http://groups.google.com Lines: 16 Message-ID: <99cc1481-2ca4-495e-bb7c-fb461dae0a7e@z20g2000vbl.googlegroups.com> References: <39bafea5-2662-4baa-b2d5-5a52eed69521@i23g2000yqm.googlegroups.com> <341b7381-bbec-45ce-b0ba-d9b0265e3007@g33g2000yqc.googlegroups.com> NNTP-Posting-Host: 86.182.234.37 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1317111828 32715 127.0.0.1 (27 Sep 2011 08:23:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Sep 2011 08:23:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z20g2000vbl.googlegroups.com; posting-host=86.182.234.37; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.186 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5318 On Sep 26, 4:01=A0am, Tricky wrote: > On Sep 24, 9:13=A0pm, Jezmo wrote: > > > Does anyone know why there is a sudden increase in the number of > > cambridge companies asking for new hires who work in verilog ? I hope > > it isn't down to an increase in the number of American CTOs who don't > > understand VHDL. > > Is it not just a recruitment drive by the local ASIC producers, whom I > always understood to be more common verilog users than VHDL? You may well be right, I had a strange call from a recruitment firm asking me if I wanted to do processor design in VHDL and then started asking me about had I done verification using verilog and systemverilog, sometimes it really makes you wonder if they understand what the hell they are talking about. From newsfish@newsfish Fri Feb 3 13:15:01 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!dm9g2000vbb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Cambridge U.K and the use of verilog Date: Tue, 27 Sep 2011 05:42:47 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: References: <39bafea5-2662-4baa-b2d5-5a52eed69521@i23g2000yqm.googlegroups.com> <341b7381-bbec-45ce-b0ba-d9b0265e3007@g33g2000yqc.googlegroups.com> <99cc1481-2ca4-495e-bb7c-fb461dae0a7e@z20g2000vbl.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1317127453 992 127.0.0.1 (27 Sep 2011 12:44:13 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 27 Sep 2011 12:44:13 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: dm9g2000vbb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.8.7.9979) X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRUV X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5319 On 27 Sep., 10:23, Jezmo wrote: > You may well be right, I had a strange call from a recruitment firm > asking me if I wanted to do processor design in VHDL and then started > asking me about had I done verification using verilog and > systemverilog, sometimes it really makes you wonder if they understand > what the hell they are talking about. I see a trend to design RTL in VHDL and build testbenches in SV. Another trend is usage of IP in whatever language you get the IP, resulting in mixed language designs. So you need designers with good skills in VHDL but also able to understand a bit Verilog (SV, C,...). bye Thomas From newsfish@newsfish Fri Feb 3 13:15:02 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!goblin3!goblin.stu.neva.ru!pit-in1.telstra.net!news.telstra.net!news1.optus.net.au!optus!newsfeeder.syd.optusnet.com.au!news.optusnet.com.au!not-for-mail Date: Sun, 02 Oct 2011 03:52:45 +1100 From: John Kent User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Fast Counter References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 23 Message-ID: <4e874563$0$3032$afc38c87@news.optusnet.com.au> NNTP-Posting-Host: 210.49.216.139 X-Trace: 1317487971 3032 210.49.216.139 Xref: feeder.eternal-september.org comp.lang.vhdl:5320 Get a CPU with 800MHZ FSB and put NOPs on the bus :-) On 8/09/2011 5:07 AM, Jessica Shaw wrote: > Hi, > > I need a 700 MHz to 800Mhz synchronous 16 bit counter. The counter > will also have a Start, Reset and Stop pins. > > Reset will intialize the counter to zero. Start will let the counter > run on each rising edge of the 700 or 800 Mhz clock. And stop will > stop the counter and user will be able to read the value. > > I do not know > > 1. What FPGA or CPLD will be able to do this task at the above > mentioned high frequency? > 2. Do I need a PLL inside the FPGA or CPLD to produce such kind of > clock? > 3. How can I generate this kind of clock? > > Any advice will be appreciated. > > jess From newsfish@newsfish Fri Feb 3 13:15:02 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!gd10g2000vbb.googlegroups.com!not-for-mail From: Jezmo Newsgroups: comp.lang.vhdl Subject: Re: Cambridge U.K and the use of verilog Date: Tue, 4 Oct 2011 13:21:37 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <39bafea5-2662-4baa-b2d5-5a52eed69521@i23g2000yqm.googlegroups.com> <341b7381-bbec-45ce-b0ba-d9b0265e3007@g33g2000yqc.googlegroups.com> <99cc1481-2ca4-495e-bb7c-fb461dae0a7e@z20g2000vbl.googlegroups.com> NNTP-Posting-Host: 86.186.55.6 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1317760641 19648 127.0.0.1 (4 Oct 2011 20:37:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 4 Oct 2011 20:37:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gd10g2000vbb.googlegroups.com; posting-host=86.186.55.6; posting-account=pVZ58AoAAAAu_AZao2TMTkPLIgfi-fRU User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.187 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5321 On Sep 27, 1:42=A0pm, Thomas Stanka wrote: > On 27 Sep., 10:23, Jezmo wrote: > > > You may well be right, I had a strange call from a recruitment firm > > asking me if I wanted to do processor design in VHDL and then started > > asking me about had I done verification using verilog and > > systemverilog, sometimes it really makes you wonder if they understand > > what the hell they are talking about. > > I see a trend to design RTL in VHDL and build testbenches in SV. > Another trend is usage of IP in whatever language you get the IP, > resulting in mixed language designs. > So you need designers with good skills in VHDL but also able to > understand a bit Verilog (SV, C,...). > > bye Thomas Well it just so happens that I am working on a JESD204B interface which may need to be written in verilog depending on what people want, so that will be fun, possibly. From newsfish@newsfish Fri Feb 3 13:15:03 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!postnews.google.com!t11g2000yqk.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Alias array / array of aliases Date: Wed, 5 Oct 2011 10:05:38 -0700 (PDT) Organization: http://groups.google.com Lines: 22 Message-ID: NNTP-Posting-Host: 174.62.66.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1317834340 30712 127.0.0.1 (5 Oct 2011 17:05:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 5 Oct 2011 17:05:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t11g2000yqk.googlegroups.com; posting-host=174.62.66.19; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.186 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5322 Hello, I'm looking to do something like the following. --code- signal signal_a, signal b : unsigned(3 downto 0); type registers is array 0 to 1 of unsigned(3 downto 0); alias my_regs : registers is (signal_a,signal_b); --end code-- So essentially I have a bunch of signals in a module and want to group them as an array of registers using aliases. The other way around is possible - declaring the array of registers as signals and then declaring the individual signals using aliases. However, I can't do it as I've shown, at least not using Xilinx's tools. Any suggestions? Thanks, Colin From newsfish@newsfish Fri Feb 3 13:15:03 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.eweka.nl!eweka.nl!feeder3.eweka.nl!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-ID: <4E8DC022.6060004@xs4all.nl> Date: Thu, 06 Oct 2011 16:50:10 +0200 From: Pieter Hulshoff User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Colin Beighley Subject: Re: Alias array / array of aliases References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 35 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1317912610 news2.news.xs4all.nl 2410 phulshof/195.242.97.150:37764 Xref: feeder.eternal-september.org comp.lang.vhdl:5323 Colin Beighley wrote: > Hello, > > I'm looking to do something like the following. > > --code- > > signal signal_a, signal b : unsigned(3 downto 0); > > type registers is array 0 to 1 of unsigned(3 downto 0); > > alias my_regs : registers is (signal_a,signal_b); > > --end code-- > > So essentially I have a bunch of signals in a module and want to group > them as an array of registers using aliases. The other way around is > possible - declaring the array of registers as signals and then > declaring the individual signals using aliases. However, I can't do it > as I've shown, at least not using Xilinx's tools. Any suggestions? I'm not sure why you want to use an alias for this. Why not use something like: declaration: SIGNAL my_regs : registers; concurrent assignment: my_regs <= (signal_a, signal_b); ? (exact syntax not checked, but I'm sure you get the idea :) ) Kind regards, Pieter Hulshoff From newsfish@newsfish Fri Feb 3 13:15:04 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!m37g2000yqc.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Local packages Date: Fri, 7 Oct 2011 00:35:46 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1317972947 21452 127.0.0.1 (7 Oct 2011 07:35:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 7 Oct 2011 07:35:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m37g2000yqc.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5324 No response or suggestion yet. >From the Aldec newsletter: "Do you know that the majority of hardware description languages (including SystemVerilog) is developed by companies that purchased IEEE-SA membership and individual users have no say in the process? VHDL does not follow this trend, and the working group developing the next version of the standard is looking for passionate individuals who would like to spend some time improving the language. Everyone is welcome and encouraged to visit www.eda.org and help make a decision." My post does show a generic construct which could be essential in our FPGA designs if supported. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:15:04 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news.astraweb.com!border2.a.newsrouter.astraweb.com!hitnews.eu!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Local packages References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111006-1, 06/10/2011), Outbound message X-Antivirus-Status: Clean Lines: 32 Message-ID: <6WAjq.65$Bf2.33@newsfe02.ams2> NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1317985026 86.29.13.122 (Fri, 07 Oct 2011 10:57:06 UTC) NNTP-Posting-Date: Fri, 07 Oct 2011 10:57:06 UTC Organization: virginmedia.com Date: Fri, 07 Oct 2011 11:57:10 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5325 On 07/10/2011 08:35, hssig wrote: > No response or suggestion yet. That is probably because not many of us can try your example. Modelsim (which is what I use) currently only supports constant generics on packages but I understand the second 10.1 beta release should expand on this. Reading the LRM is just too painful...;-) Hans www.ht-lab.com > > > From the Aldec newsletter: > > "Do you know that the majority of hardware description languages > (including SystemVerilog) is developed by companies that purchased > IEEE-SA membership and individual users have no say in the process? > VHDL does not follow this trend, and the working group developing the > next version of the standard is looking for passionate individuals who > would like to spend some time improving the language. Everyone is > welcome and encouraged to visit www.eda.org and help make a decision." > > > My post does show a generic construct which could be essential in our > FPGA designs if supported. > > > Cheers, hssig From newsfish@newsfish Fri Feb 3 13:15:05 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Fri, 07 Oct 2011 09:40:09 -0400 Organization: Alacron, Inc. Lines: 43 Message-ID: References: <4E8DC022.6060004@xs4all.nl> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 7 Oct 2011 13:40:36 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="23572"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+6Pv1Z7WN8+zHWFbL/OGy5" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <4E8DC022.6060004@xs4all.nl> Cancel-Lock: sha1:q66tMB94CQn+IH42CMB1tBS+zUs= Xref: feeder.eternal-september.org comp.lang.vhdl:5326 Pieter Hulshoff wrote: > Colin Beighley wrote: >> Hello, >> >> I'm looking to do something like the following. >> >> --code- >> >> signal signal_a, signal b : unsigned(3 downto 0); >> >> type registers is array 0 to 1 of unsigned(3 downto 0); >> >> alias my_regs : registers is (signal_a,signal_b); >> >> --end code-- >> >> So essentially I have a bunch of signals in a module and want to group >> them as an array of registers using aliases. The other way around is >> possible - declaring the array of registers as signals and then >> declaring the individual signals using aliases. However, I can't do it >> as I've shown, at least not using Xilinx's tools. Any suggestions? > > I'm not sure why you want to use an alias for this. Why not use something like: > > declaration: > SIGNAL my_regs : registers; > > concurrent assignment: > my_regs <= (signal_a, signal_b); > > ? (exact syntax not checked, but I'm sure you get the idea :) ) > > Kind regards, > > Pieter Hulshoff > I've run into similar situations. The problem is that concurrent assignments are one-way. What if I'm using these signals to connect inout ports of sub-modules? Usually this gets painful when you need to use a generate loop. -- Gabor From newsfish@newsfish Fri Feb 3 13:15:05 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Sun, 9 Oct 2011 10:42:21 -0700 (PDT) Organization: http://groups.google.com Lines: 14 Message-ID: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> References: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.196.226.24 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318182141 30957 127.0.0.1 (9 Oct 2011 17:42:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 9 Oct 2011 17:42:21 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.196.226.24; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5327 I don't use aliases because they are invisible in simulation. If you want an array of registers, you will need to declare a type and subtype as shown below. This has nothing to do with Xilinx tools. It is the vhdl language. -- Mike Treseler package stack_pkg is constant reg_len_c : positive := 32; constant array_len_c : positive := 32; subtype reg_t is std_logic_vector(reg_len_c-1 downto 0); type regs_t is array (0 to array_len_c-1) of reg_t; constant reg_init_c : reg_t := (others => '0'); end package stack_pkg; From newsfish@newsfish Fri Feb 3 13:15:05 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n15g2000vbn.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Local packages Date: Mon, 10 Oct 2011 04:58:39 -0700 (PDT) Organization: http://groups.google.com Lines: 7 Message-ID: <82438539-f006-4de1-9109-d86fadda51ce@n15g2000vbn.googlegroups.com> References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> <6WAjq.65$Bf2.33@newsfe02.ams2> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318248272 9850 127.0.0.1 (10 Oct 2011 12:04:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Oct 2011 12:04:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n15g2000vbn.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5328 >the second 10.1 beta release Yes, I will participate in the second phase of Modeslim 10.1 beta program. We will see ... Cheers, hssig From newsfish@newsfish Fri Feb 3 13:15:06 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Testbench\Package Signal Visibility Date: Mon, 10 Oct 2011 11:24:44 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <30200857.515.1318271084944.JavaMail.geo-discussion-forums@prgv7> References: <0bc5e8fb-1b21-4880-9dd2-a7485aba7414@a17g2000yqk.googlegroups.com> <7b1551e8-e5be-448a-901d-597efb5c34fa@glegroupsg2000goo.googlegroups.com> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.196.226.157 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318272109 29879 127.0.0.1 (10 Oct 2011 18:41:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 10 Oct 2011 18:41:49 +0000 (UTC) In-Reply-To: <7b1551e8-e5be-448a-901d-597efb5c34fa@glegroupsg2000goo.googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.196.226.157; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5329 sorry, Variables declared inside the procedure are immutable. --------- Glad no one reads this stuff ;) -- Mike From newsfish@newsfish Fri Feb 3 13:15:06 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!y36g2000pro.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Tue, 11 Oct 2011 10:45:47 -0700 (PDT) Organization: http://groups.google.com Lines: 73 Message-ID: <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> NNTP-Posting-Host: 174.62.66.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318355147 20725 127.0.0.1 (11 Oct 2011 17:45:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 11 Oct 2011 17:45:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y36g2000pro.googlegroups.com; posting-host=174.62.66.19; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.23) Gecko/20110921 Ubuntu/10.04 (lucid) Firefox/3.6.23,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5330 It's not quite as elegant as I had hoped, but here's what I've been doing. Leveraging the resolved nature of the std_logic (and hence slv, signed, and unsigned), I'm putting a procedure at the end of my sequential assignment process for the state machine of the module that does the address based IO. In each clock cycle the companion combinatorial process decides the values that will be assigned to the registers in the procedure update_regs, and then if the external logic wants to write to a register the value written to that register will resolve to the external logic's value. I tend to use the resolution capabilities of std_logic and derived types pretty heavily in this way, does anyone have any comment on best practices in this regard? Note - it's easy to use signals in the module that are of greater / smaller length than the data bus, you just need to be careful with your conversions to signed/unsigned know what you're doing with the unused bits. If they're greater you have to use more than 1 address, for instance unused bits + MSb's at addr X and LSb's at addr X + 1. --CODE-- entity module is port( CLK,RST : in std_logic; REG_ADDR : in unsigned(1 downto 0); REG_WR : in std_logic; REG_DATA_IN : in std_logic_vector(3 downto 0); REG_DATA_OUT : out std_logic_vector(3 downto 0) ); end entity; architecture behavioral of module is signal sig_a_signed : signed(3 downto 0); signal sig_b_slv : std_logic_vector(3 downto 0); signal sig_c_unsigned : unsigned(3 downto 0); begin sequential_assignments : process(RST,CLK) procedure reset_regs; procedure update_regs; procedure register_io is begin case to_integer(REG_ADDR) is when 0 => if REG_WR = '1' then sig_a_signed <= signed(REG_DATA_IN); end if; REG_DATA_OUT <= std_logic_vector(sig_a_signed); when 1 => if REG_WR = '1' then sig_b_slv <= REG_DATA_IN; end if; REG_DATA_OUT <= sig_b_slv; when 2 => if REG_WR = '1' then sig_c_unsigned <= unsigned(REG_DATA_IN); end if; REG_DATA_OUT <= std_logic_vector(sig_c_unsigned); when others => REG_DATA_OUT <= (others => '-'); end case; end procedure; begin if RST = '1' then reset_regs; elsif rising_edge(CLK) then update_regs; register_io; end if; end process sequential_assignments; end architecture; --END CODE-- From newsfish@newsfish Fri Feb 3 13:15:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!r36g2000prr.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Tue, 11 Oct 2011 10:47:10 -0700 (PDT) Organization: http://groups.google.com Lines: 3 Message-ID: <4bdbc973-9711-4523-b2fe-61ae40ea1339@r36g2000prr.googlegroups.com> References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> NNTP-Posting-Host: 174.62.66.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318355231 21547 127.0.0.1 (11 Oct 2011 17:47:11 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 11 Oct 2011 17:47:11 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r36g2000prr.googlegroups.com; posting-host=174.62.66.19; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.23) Gecko/20110921 Ubuntu/10.04 (lucid) Firefox/3.6.23,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5331 Note that in the last post I didn't include the combinatorial process or flesh out the reset or update procedures, as I thought it was unnecessary to explain. From newsfish@newsfish Fri Feb 3 13:15:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!postnews.google.com!l39g2000pro.googlegroups.com!not-for-mail From: Vikram Newsgroups: comp.lang.vhdl,comp.arch.embedded,comp.dsp,sci.electronics.basics,sci.electronics.components Subject: Register Now: Four Channel Design Features that Will Open Your Eyes with Eric Bogatin - Santa Clara, CA (FREE) - Nov'7 Date: Tue, 11 Oct 2011 13:45:05 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <8f7ef864-ad34-46a6-98a2-4a44160660e9@l39g2000pro.googlegroups.com> NNTP-Posting-Host: 8.4.225.30 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318368228 27015 127.0.0.1 (11 Oct 2011 21:23:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 11 Oct 2011 21:23:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l39g2000pro.googlegroups.com; posting-host=8.4.225.30; posting-account=ROblUgoAAABUCieY-adRND7iPJOdhLol User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/535.1 (KHTML, like Gecko) Chrome/14.0.835.202 Safari/535.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5332 comp.arch.embedded:25026 comp.dsp:34365 sci.electronics.basics:24839 sci.electronics.components:4426 Eric Bogatin is coming to Silicon Valley, don't miss out his upcoming talk on Four Channel Design Features that Will Open Your Eyes. For registration & more details: Register at http://www.fpgacentral.com/si-techtalk OR RSVP at http://events.linkedin.com/Four-Channel-Design-Features-that-Will/pub/816764 Successful channel design above 5 Gbps does not happen by accident. Four specific signal integrity problems typically contribute to increased deterministic jitter and eye closure. However, these problems can be minimized by identifying their root cause and optimizing the physi-cal design of the interconnects to minimize these prob-lems. In this brief lecture by Eric Bogatin, we introduce the four problems, their root cause and a methodology to optimize channel interconnect design to improve eye quality. These design techniques apply to serial links even above 15 Gbps. Agenda 5:00 - 5:30 PM Registration, Networking & Refreshments 5:30 - 6:30 PM Tech Talk 6:30 - 7:00 PM Q & A Session More details: http://www.fpgacentral.com From newsfish@newsfish Fri Feb 3 13:15:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u6g2000vbo.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Tue, 11 Oct 2011 18:33:02 -0700 (PDT) Organization: http://groups.google.com Lines: 85 Message-ID: <4ea90b6f-3c3f-472b-aa94-09dd10631fc8@u6g2000vbo.googlegroups.com> References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1318383286 21803 127.0.0.1 (12 Oct 2011 01:34:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 01:34:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u6g2000vbo.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5333 On Oct 11, 1:45=A0pm, Colin Beighley wrote: > It's not quite as elegant as I had hoped, but here's what I've been > doing. > > Leveraging the resolved nature of the std_logic (and hence slv, > signed, and unsigned), I'm putting a procedure at the end of my > sequential assignment process for the state machine of the module that > does the address based IO. Your example does not demonstrate any use of 'the resolved nature of the std_logic', what you have will work just as well with the unresolved type std_ulogic. That's OK, I wouldn't recommend using 'the resolved nature of the std_logic' in any code intended to be synthesized...certainly not for addressable registers. > In each clock cycle the companion > combinatorial process decides the values that will be assigned to the > registers in the procedure update_regs, and then if the external logic > wants to write to a register the value written to that register will > resolve to the external logic's value. > What you've described here (about 'resolve to the external logic's value') is not what you've shown in your code. Your example code simply shows addressable registers...and you should ask yourself why you think you need a separate combinatorial process, the clocked process you have is all you need...much cleaner. > I tend to use the resolution capabilities of std_logic and derived > types pretty heavily in this way, does anyone have any comment on best > practices in this regard? > 1. You're not using the resolution capabilities of std_logic...I'm not sure why you think you are. I'm guessing that since you have an 'update_regs' (not shown) and it probably updates the same signals as 'register_io' that you think this is using resolved logic. If that's the case then you're mistaken, the 'register_io' procedure is simply higher priority than 'update_regs' since it will have the final word. This is not intended as a criticism of your code, just that your terminology about using resolved logic is not correct. Resolved logic has to do with multiple drivers of a signal...and a single process (even with multiple procedures) can never create multiple drivers of any signal. 2. If you were making use of the resolution capabilities of std_logic in your example code and that code was intended to be synthesized, that would be a mistake. Since you're not, your code looks OK. > Note - it's easy to use signals in the module that are of greater / > smaller length than the data bus, you just need to be careful with > your conversions to signed/unsigned know what you're doing with the > unused bits. If they're greater you have to use more than 1 address, > for instance unused bits + MSb's at addr X and LSb's at addr X + 1. > I tend to define a record that defines all of the bits that are writable whether they are used to control anything or not like this... type t_THIS_PORT is record Reserved: std_ulogic_vector(31 downto 24); Pointer: std_ulogic_vector(23 downto 0); end record t_THIS_PORT; Next I define a pair of functions called 'to_std_ulogic_vector' and 'from_std_ulogic_vector' that work with this record type and do exactly what the name suggests. Repeat this for all read/write registers. Now the register updates (such as your 'sig_a_signed <=3D signed(REG_DATA_IN);') become 'sig_a <=3D from_std_ulogic_vector(REG_DATA_IN'). By itself, this isn't really much different than what you have, but it also cleanly takes care of things like bit widths not matching the external updater as well as when you have ports with lot of bit fields and you want to change those definitions around a bit. In my case, all I would change is the code inside the 'to_std_ulogic_vector' and 'from_std_ulogic_vector' functions and re-synthesize. In fact, if all that is changing is the widths/bit locations of existing fields (i.e. not adding/removing any fields), then all I update is the record definition without touching the source code for the function at all. No having to hunt through and places where bit 9 needs to be used rather than bit 8 to control something. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:08 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b6g2000vbz.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Local packages Date: Wed, 12 Oct 2011 01:10:05 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> <6WAjq.65$Bf2.33@newsfe02.ams2> <82438539-f006-4de1-9109-d86fadda51ce@n15g2000vbn.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318407005 9386 127.0.0.1 (12 Oct 2011 08:10:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 08:10:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b6g2000vbz.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5334 First try with Modelsim Pe 10.1beta2 vcom -2008 test_compnent.vhd # Model Technology ModelSim PE vcom 10.1 Beta 2 Compiler 2011.10 Oct 1 2011 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package pkg_test # -- Compiling entity test_component # ** Error: test_compnent.vhd(15): near "library": syntax error # -- Loading package pkg_test # ** Error: test_compnent.vhd(16): A member of an uninstantiated package is referenced outside the scope of the package. # ** Error: test_compnent.vhd(17): VHDL Compiler exiting # C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:15:08 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Alias array / array of aliases Newsgroups: comp.lang.vhdl Date: Wed, 12 Oct 2011 11:14:41 +0200 References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 69 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1318410881 news2.news.xs4all.nl 2438 puiterl/195.242.97.150:45083 Xref: feeder.eternal-september.org comp.lang.vhdl:5335 Colin Beighley wrote: > --CODE-- > entity module is > port( > CLK,RST : in std_logic; > > REG_ADDR : in unsigned(1 downto 0); > REG_WR : in std_logic; > REG_DATA_IN : in std_logic_vector(3 downto 0); > REG_DATA_OUT : out std_logic_vector(3 downto 0) > ); > end entity; > > architecture behavioral of module is > signal sig_a_signed : signed(3 downto 0); > signal sig_b_slv : std_logic_vector(3 downto 0); > signal sig_c_unsigned : unsigned(3 downto 0); > begin > > sequential_assignments : process(RST,CLK) > procedure reset_regs; > procedure update_regs; > > procedure register_io is > begin > case to_integer(REG_ADDR) is > when 0 => > if REG_WR = '1' then sig_a_signed <= signed(REG_DATA_IN); end > if; > REG_DATA_OUT <= std_logic_vector(sig_a_signed); > when 1 => > if REG_WR = '1' then sig_b_slv <= REG_DATA_IN; end if; > REG_DATA_OUT <= sig_b_slv; > when 2 => > if REG_WR = '1' then sig_c_unsigned <= unsigned(REG_DATA_IN); > end if; > REG_DATA_OUT <= std_logic_vector(sig_c_unsigned); > when others => > REG_DATA_OUT <= (others => '-'); > end case; > end procedure; > begin > if RST = '1' then > reset_regs; > elsif rising_edge(CLK) then > update_regs; > register_io; > end if; > end process sequential_assignments; > > end architecture; > --END CODE-- This code does not make any sense to me. In procedure register_io you drive a new value to say sig_a_signed. At the same moment, you drive the value of sig_a_signed to REG_DATA_OUT. But that is the *old* value of sig_a_signed. The new value appears on sig_a_signed only after a delta delay. Have you simulated this code? Admittedly, I have not, other than reading the code and perform some mental simulation. As KJ already pointed out, there isn't any resolving involved in this code. That was the thing that made me look at your code in the first place. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:15:09 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4e955e02$0$2410$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Is there delta=0 except at the beginning moment? Newsgroups: comp.lang.vhdl Date: Wed, 12 Oct 2011 11:29:38 +0200 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 34 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1318411779 news2.news.xs4all.nl 2410 puiterl/195.242.97.150:43087 Xref: feeder.eternal-september.org comp.lang.vhdl:5336 fl wrote: > Hi, > I find that only at the simulation beginning that delta =0. Other time > it is at least +1, or larger. I want to know that it is possible that > delta=0 in the middle of simulation? A late reply. I suppose you only see deltas larger than zero because you put break points in synthesisable code. In general, these are processes that wake up on signal events. Primary input signals generated in a testbench (such as a clock) usually change at times with a delta=1. Other signals after that, so delta >= 2. Take for example a clock generator: clk_gen: clk <= NOT clk AFTER half_clk_period; Or: clk_gen: PROCESS IS BEGIN WAIT for half_clk_period; clk <= NOT clk; END PROCESS clk_gen; Put a break point on the line "clk <= NOT clk;" in the process and you'll see times that are multiples of half_clk_period, all with delta=0. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:15:09 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!v102.xanadu-bbs.net!news.glorb.com!postnews.google.com!k10g2000vbn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Wed, 12 Oct 2011 05:10:05 -0700 (PDT) Organization: http://groups.google.com Lines: 21 Message-ID: References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1318421405 29313 127.0.0.1 (12 Oct 2011 12:10:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 12:10:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k10g2000vbn.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5337 On Oct 12, 5:14=A0am, Paul Uiterlinden wrote: > > This code does not make any sense to me. In procedure register_io you dri= ve > a new value to say sig_a_signed. At the same moment, you drive the value = of > sig_a_signed to REG_DATA_OUT. But that is the *old* value of sig_a_signed= . > The new value appears on sig_a_signed only after a delta delay. > I believe that the 'REG_*' interface signals represent a typical read/ write interface to some external processor. Presumably that processor would need the ability to read from registers hence the 'REG_DATA_OUT <=3D ...' statements. Putting this inside the clocked process presumes that the processor is expected to wait one clock cycle after setting the address before REG_DATA_OUT would be valid. Far better to have an explicit read command and wait (or acknowledge) handshake signals for an interface definition, but that's off topic. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:09 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!easy.in-chemnitz.de!feeder.news-service.com!postnews.google.com!r39g2000prh.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Wed, 12 Oct 2011 10:07:30 -0700 (PDT) Organization: http://groups.google.com Lines: 6 Message-ID: <72a60faf-f42f-448b-bb25-455e8a1fc6fa@r39g2000prh.googlegroups.com> References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: 174.62.66.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318439577 24605 127.0.0.1 (12 Oct 2011 17:12:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 17:12:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: r39g2000prh.googlegroups.com; posting-host=174.62.66.19; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.23) Gecko/20110921 Ubuntu/10.04 (lucid) Firefox/3.6.23,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5338 Thanks for the advice, guys! My understanding of resolved signals was that you could do multiple assignments within a process to a signal and that only the last one would take affect. Is this not an attribute specific only to resolved signals? I have simulated this and it seems to work fine, is there a reason I shouldn't synthesize a design like this? From newsfish@newsfish Fri Feb 3 13:15:10 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!db5g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Wed, 12 Oct 2011 12:29:47 -0700 (PDT) Organization: http://groups.google.com Lines: 19 Message-ID: <16c463c9-530b-41ae-aee6-d324c1022561@db5g2000vbb.googlegroups.com> References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> <72a60faf-f42f-448b-bb25-455e8a1fc6fa@r39g2000prh.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1318447896 15190 127.0.0.1 (12 Oct 2011 19:31:36 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 19:31:36 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: db5g2000vbb.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5339 On Oct 12, 1:07=A0pm, Colin Beighley wrote: > Thanks for the advice, guys! My understanding of resolved signals was > that you could do multiple assignments within a process to a signal > and that only the last one would take affect. Remove the word 'resolved' from your sentence and your sentence will be correct. > Is this not an attribute > specific only to resolved signals? No, it is true for all signals. > I have simulated this and it seems > to work fine, is there a reason I shouldn't synthesize a design like > this? I didn't see anything wrong in the method demonstrated by your example code. Should synthesize just fine. From newsfish@newsfish Fri Feb 3 13:15:10 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!h13g2000pro.googlegroups.com!not-for-mail From: Colin Beighley Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Wed, 12 Oct 2011 13:48:32 -0700 (PDT) Organization: http://groups.google.com Lines: 2 Message-ID: References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> <72a60faf-f42f-448b-bb25-455e8a1fc6fa@r39g2000prh.googlegroups.com> <16c463c9-530b-41ae-aee6-d324c1022561@db5g2000vbb.googlegroups.com> NNTP-Posting-Host: 174.62.66.19 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318452924 2880 127.0.0.1 (12 Oct 2011 20:55:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 12 Oct 2011 20:55:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: h13g2000pro.googlegroups.com; posting-host=174.62.66.19; posting-account=_oVm6woAAABjvAcs4ROtQzxo3fVWHiPd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.23) Gecko/20110921 Ubuntu/10.04 (lucid) Firefox/3.6.23,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5340 Again, thanks for the advice, KJ. I guess I should read up on resolved signals. From newsfish@newsfish Fri Feb 3 13:15:11 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!v8g2000vbe.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases Date: Fri, 14 Oct 2011 07:52:03 -0700 (PDT) Organization: http://groups.google.com Lines: 20 Message-ID: References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> <72a60faf-f42f-448b-bb25-455e8a1fc6fa@r39g2000prh.googlegroups.com> <16c463c9-530b-41ae-aee6-d324c1022561@db5g2000vbb.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1318603923 32201 127.0.0.1 (14 Oct 2011 14:52:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 14 Oct 2011 14:52:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v8g2000vbe.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:7.0.1) Gecko/20100101 Firefox/7.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5341 On Oct 12, 9:48=A0pm, Colin Beighley wrote: > Again, thanks for the advice, KJ. I guess I should read up on resolved > signals. resolution functions need to be defined for a type. The only resolved type in VHDL is std_logic. This allows std_logic to be driven from multiple processes. The main use of this is to simulate tri-state busses. with a resolution function, you can do this in your code (outside of a process) a <=3D '1'; a <=3D '0'; and when you simulate it you get 'X' if you tried this with a std_ulogic, it would give you an error when you compiled the code (before you even got to the simulation) because std_ulogic is not resolved, and multiple drivers are banned. From newsfish@newsfish Fri Feb 3 13:15:11 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!feeder2.ecngs.de!ecngs!feeder.ecngs.de!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 15 Oct 2011 03:51:15 -0500 Date: Sat, 15 Oct 2011 09:51:15 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux i686; rv:6.0.2) Gecko/20110906 Thunderbird/6.0.2 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Alias array / array of aliases References: <1640298.196.1318182141280.JavaMail.geo-discussion-forums@prmr13> <89dde43d-f4d5-4fbb-a2d2-9f736b2f3cc0@y36g2000pro.googlegroups.com> <4e955a81$0$2438$e4fe514c@news2.news.xs4all.nl> <72a60faf-f42f-448b-bb25-455e8a1fc6fa@r39g2000prh.googlegroups.com> <16c463c9-530b-41ae-aee6-d324c1022561@db5g2000vbb.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-ID: <6tWdnXOk5P4e1ATTnZ2dnUVZ8s2dnZ2d@brightview.co.uk> Lines: 13 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-BPms8mAkDa6jGR5LiFyDs7VAJ9uMz3SSqgElHOduYRCSiOi/n1oDUT00sRQQ7MVNBWshKFaZ7USOqRX!Eu6+H/45uWxl2Ufv2CSX1110w4fF+XDrlmAgvHYwdsFa+8g7+r4/6F2WFEqEEgqd6xdLu2LTGDuE!k4Isw2dQD5wOeZTqOAn1k2m77s0= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1943 Xref: feeder.eternal-september.org comp.lang.vhdl:5342 On 12/10/11 21:48, Colin Beighley wrote: > Again, thanks for the advice, KJ. I guess I should read up on resolved > signals. Hi Colin, what you're describing is a property of the way signals are updated. After looking up "resolved", try looking up "inertial delay". kind regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:15:12 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe26.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Local packages References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> <6WAjq.65$Bf2.33@newsfe02.ams2> <82438539-f006-4de1-9109-d86fadda51ce@n15g2000vbn.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111016-1, 16/10/2011), Outbound message X-Antivirus-Status: Clean Lines: 59 Message-ID: NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe26.ams2 1318841377 86.29.13.122 (Mon, 17 Oct 2011 08:49:37 UTC) NNTP-Posting-Date: Mon, 17 Oct 2011 08:49:37 UTC Organization: virginmedia.com Date: Mon, 17 Oct 2011 09:49:37 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5343 On 12/10/2011 09:10, hssig wrote: > First try with Modelsim Pe 10.1beta2 .. > # ** Error: test_compnent.vhd(16): A member of an uninstantiated > package is referenced outside the scope of the package. > # ** Error: test_compnent.vhd(17): VHDL Compiler exiting > # C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed. > > > Cheers, > hssig Hi Hssig, I found the same, apparently full generics including type generics will not be supported until 10.2. Does anybody know if Aldec supports type generics? (see modified Doulos example below). Hans www.ht-lab.com library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std_unsigned.all; entity incrementer is generic (type data_type); port (I : in data_type; O : out data_type; inc : in boolean); end entity incrementer; architecture RTL of incrementer is begin O <= I + '1' when inc = true; end architecture RTL; library ieee; use ieee.std_logic_1164.all; entity top is port (I : in std_logic_vector(7 downto 0); O : out std_logic_vector(7 downto 0)); end entity top; architecture RTL of top is begin incr_inst : entity work.incrementer generic map ( data_type => std_logic_vector(7 downto 0), increment => true ) port map ( I => I, O => O, inc => true ); end architecture RTL; From newsfish@newsfish Fri Feb 3 13:15:12 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!not-for-mail From: Matthias Alles Newsgroups: comp.lang.vhdl Subject: Re: Local packages Date: Mon, 17 Oct 2011 15:21:23 +0200 Organization: InterNetNews at News.BelWue.DE (Stuttgart, Germany) Lines: 77 Message-ID: References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> <6WAjq.65$Bf2.33@newsfe02.ams2> <82438539-f006-4de1-9109-d86fadda51ce@n15g2000vbn.googlegroups.com> NNTP-Posting-Host: creonic.eit.uni-kl.de Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: news.belwue.de 1318857683 21465 131.246.218.4 (17 Oct 2011 13:21:23 GMT) X-Complaints-To: news@news.belwue.de NNTP-Posting-Date: Mon, 17 Oct 2011 13:21:23 +0000 (UTC) User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.23) Gecko/20110922 Lightning/1.0b2 Thunderbird/3.1.15 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5344 Hi Hans, a quick try with RivieraPro 2011.06 gives: COMP96 ERROR COMP96_0666: "Declaring interface types that appear as generics in design entities, components, blocks, or subprograms is not supported yet. Please contact Aldec Support to receive the latest status." "test.vhd" 6 12 For the upcoming 2011.10 release they promise the support of new VHDL constructs. Maybe this one will be supported then. Best regards, Matthias Am 17.10.2011 10:49, schrieb HT-Lab: > On 12/10/2011 09:10, hssig wrote: >> First try with Modelsim Pe 10.1beta2 > .. >> # ** Error: test_compnent.vhd(16): A member of an uninstantiated >> package is referenced outside the scope of the package. >> # ** Error: test_compnent.vhd(17): VHDL Compiler exiting >> # C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed. >> >> >> Cheers, >> hssig > > Hi Hssig, > > I found the same, apparently full generics including type generics will > not be supported until 10.2. > > Does anybody know if Aldec supports type generics? (see modified Doulos > example below). > > Hans > www.ht-lab.com > > > library ieee; > use ieee.std_logic_1164.all; > use IEEE.numeric_std_unsigned.all; > > entity incrementer is > generic (type data_type); > port (I : in data_type; > O : out data_type; > inc : in boolean); > end entity incrementer; > > architecture RTL of incrementer is > > begin > O <= I + '1' when inc = true; > end architecture RTL; > > library ieee; > use ieee.std_logic_1164.all; > > entity top is > port (I : in std_logic_vector(7 downto 0); > O : out std_logic_vector(7 downto 0)); > end entity top; > > architecture RTL of top is > > begin > > incr_inst : entity work.incrementer > generic map ( data_type => std_logic_vector(7 downto 0), > increment => true ) > port map ( I => I, O => O, inc => true ); > > end architecture RTL; From newsfish@newsfish Fri Feb 3 13:15:12 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.unit0.net!cyclone01.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe07.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Local packages References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> <6WAjq.65$Bf2.33@newsfe02.ams2> <82438539-f006-4de1-9109-d86fadda51ce@n15g2000vbn.googlegroups.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111017-0, 17/10/2011), Outbound message X-Antivirus-Status: Clean Lines: 88 Message-ID: <0bYmq.1167$z92.746@newsfe07.ams2> NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe07.ams2 1318866748 86.29.13.122 (Mon, 17 Oct 2011 15:52:28 UTC) NNTP-Posting-Date: Mon, 17 Oct 2011 15:52:28 UTC Organization: virginmedia.com Date: Mon, 17 Oct 2011 16:52:27 +0100 Xref: feeder.eternal-september.org comp.lang.vhdl:5345 Hi Matthias, Thanks for trying it out. It looks like Mentor is not that far behind. Regards, Hans. www.ht-lab.com On 17/10/2011 14:21, Matthias Alles wrote: > Hi Hans, > > a quick try with RivieraPro 2011.06 gives: > > COMP96 ERROR COMP96_0666: "Declaring interface types that appear as > generics in design entities, components, blocks, or subprograms is not > supported yet. Please contact Aldec Support to receive the latest > status." "test.vhd" 6 12 > > For the upcoming 2011.10 release they promise the support of new VHDL > constructs. Maybe this one will be supported then. > > Best regards, > Matthias > > > Am 17.10.2011 10:49, schrieb HT-Lab: >> On 12/10/2011 09:10, hssig wrote: >>> First try with Modelsim Pe 10.1beta2 >> .. >>> # ** Error: test_compnent.vhd(16): A member of an uninstantiated >>> package is referenced outside the scope of the package. >>> # ** Error: test_compnent.vhd(17): VHDL Compiler exiting >>> # C:/EDA/Mentor/modelsim/10.1beta/win32pe/vcom failed. >>> >>> >>> Cheers, >>> hssig >> >> Hi Hssig, >> >> I found the same, apparently full generics including type generics will >> not be supported until 10.2. >> >> Does anybody know if Aldec supports type generics? (see modified Doulos >> example below). >> >> Hans >> www.ht-lab.com >> >> >> library ieee; >> use ieee.std_logic_1164.all; >> use IEEE.numeric_std_unsigned.all; >> >> entity incrementer is >> generic (type data_type); >> port (I : in data_type; >> O : out data_type; >> inc : in boolean); >> end entity incrementer; >> >> architecture RTL of incrementer is >> >> begin >> O<= I + '1' when inc = true; >> end architecture RTL; >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity top is >> port (I : in std_logic_vector(7 downto 0); >> O : out std_logic_vector(7 downto 0)); >> end entity top; >> >> architecture RTL of top is >> >> begin >> >> incr_inst : entity work.incrementer >> generic map ( data_type => std_logic_vector(7 downto 0), >> increment => true ) >> port map ( I => I, O => O, inc => true ); >> >> end architecture RTL; > From newsfish@newsfish Fri Feb 3 13:15:13 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.albasani.net!feeder.news-service.com!postnews.google.com!y35g2000pre.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Local packages Date: Mon, 17 Oct 2011 16:46:31 -0700 (PDT) Organization: http://groups.google.com Lines: 24 Message-ID: <1848eeb8-42dc-4f5b-80e6-ec7f9358d8a2@y35g2000pre.googlegroups.com> References: <6700e992-fa19-4372-859e-78b79711c2b7@j19g2000yqc.googlegroups.com> NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1318895192 31153 127.0.0.1 (17 Oct 2011 23:46:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 17 Oct 2011 23:46:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y35g2000pre.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:7.0.1) Gecko/20100101 Firefox/7.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5346 Hi Hssig, It looks to me like the structure of your entity is incorrect. Structure of the entity is: entity identifier is entity_header entity_declarative_part [ begin entity_statement_part ] end [ entity ] [ entity_simple_name ] ; Local package declarations go in the entity_declarative_part. OTOH, generic and port clauses go in the entity_header. VHDL-2008 has another feature that will solve your problem in a easier fashion. Composites can now have unconstrained elements. As a result you can declare: type t_type is array(integer range <>) of std_logic_vector; then use it as: signal A : t_type(0 to NUM)(NUM downto 0) ; Good luck, Jim From newsfish@newsfish Fri Feb 3 13:15:13 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g27g2000pro.googlegroups.com!not-for-mail From: self Newsgroups: comp.lang.vhdl Subject: PHDL a new HDL for PCB design Date: Thu, 27 Oct 2011 19:28:14 -0700 (PDT) Organization: http://groups.google.com Lines: 158 Message-ID: NNTP-Posting-Host: 68.35.127.28 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1319768946 1537 127.0.0.1 (28 Oct 2011 02:29:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 28 Oct 2011 02:29:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g27g2000pro.googlegroups.com; posting-host=68.35.127.28; posting-account=buE9zAoAAADInp_5AizVMCbrLTmYl6wQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; OfficeLiveConnector.1.4; OfficeLivePatch.1.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5347 Guys I want to give you an update on the HDL for PCB work I have been doing. Lately I have collaborated with the Configurable Computing Lab at Brigham Young University to introduce a new, super simple HDL for board design capture. A compiler has been written and tested on a few board designs. The syntax of the language is highly simplified and efficient compared to VHDL or even Verilog. The language lets you first define devices, where functional port names are associated with pin numbers. Then your instantiate those devices and connect nets to the ports. Device ports can be single pins or busses. You can look at the complete code for an example design in these files https://phdl.svn.sourceforge.net/svnroot/phdl/trunk/projects/FMC_DAC/phdl/devices.phdl https://phdl.svn.sourceforge.net/svnroot/phdl/trunk/projects/FMC_DAC/phdl/fmc_dac.phdl For boards with Xilinx FPGAs I have published a utility that automatically generates the device declaration and instantiation template to cut down on typing and mistakes. Please let me know what you think. I include some example code below for your convenience. Here is a sample syntax for the device definition. Note that data busses and repeated signals like GND are handled with a single line declaration. // Analog Devices high speed DAC device ad9739 is attr refPrefix = "U"; attr refDes = ""; attr name = ""; attr value = ""; attr pkg_type = "ANALOG_DEVICES_BC-160-1"; attr mfgr = "Analog Devices"; attr PartNumber = "AD9739BBCZ"; attr cost = "70.00"; pin[13:0] DB1_P = {L14,L13,L12,L11,L10,L9,L8,L7,L6,L5,L4,L3,L2,L1}; pin[13:0] DB1_N = {M14,M13,M12,M11,M10,M9,M8,M7,M6,M5,M4,M3,M2,M1}; pin[13:0] DB0_P = {N14,N13,N12,N11,N10,N9,N8,N7,N6,N5,N4,N3,N2,N1}; pin[13:0] DB0_N = {P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1}; pin[1:8] VDDC = {C1, C2, D1, D2, E1, E2, E3, E4}; pin[1:14] VSSC = {A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5}; pin[1:8] VDDA = {A10, A11, B10, B11, C10, C11, D10, D11}; pin[1:8] VSSA = {A12, A13, B12, B13, C12, C13, D12, D13}; pin[1:18] VSSA_SHIELD = {A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3, F4, E11, E12, E13, E14, F11, F12}; pin NC = {A14}; pin[1:4] IOUTN = {A7, B7, C7, D7}; pin[1:4] IOUTP = {A8, B8, C8, D8}; pin I120 = {B14}; pin VREF = {C14}; pin IPTAT = {D14}; pin DACCLK_N = {C3}; pin DACCLK_P = {D3}; pin IRQ = {F13}; pin RESET = {F14}; pin CS = {G13}; pin SDIO = {G14}; pin SCLK = {H13}; pin SDO = {H14}; pin[1:4] VDD33 = {J3,J4,J11,J12}; pin[1:6] VDD = {G1, G2, G3, G4, G11, G12}; pin[1:10] VSS = {H1, H2, H3, H4, H11, H12, K3, K4, K11, K12}; pin SYNC_OUT_P = {J1}; pin SYNC_OUT_N = {J2}; pin SYNC_IN_P = {K1}; pin SYNC_IN_N = {K2}; pin DCO_P = {J13}; pin DCO_N = {J14}; pin DCI_P = {K13}; pin DCI_N = {K14}; end device; And here is some sample code of how the parts are wired up. design fmc_dac is // device definitions include "devices.phdl"; // Power and ground nets. net +3V3, +2V5, +1V8, 1V8_sense, gnd; // net VDDC, VDDA; // DAC Signals. net IOUTP, IOUTN; net[13:0] DB1_P, DB1_N, DB0_P, DB0_N; net DACCLK_P, DACCLK_N, DCI_P, DCI_N, DCO_P, DCO_N, SYNC_IN_P, SYNC_IN_N, SYNC_OUT_P, SYNC_OUT_N; net IRQ, RESET, SPI_CS, SPI_SCLK, SPI_SDO, SPI_SDI; net IRQ_2V5, RESET_2V5, SPI_CS_2V5, SPI_SCLK_2V5, SPI_SDO_2V5, SPI_SDI_2V5; net DAC_VREF, IPTAT, I120; net analog_out; // Clock signals. net samp_clk_in, bal_clock_p, bal_clock_n, coup_clock_p, coup_clock_n; net clock_buf_p, clock_buf_n; net ADCLK914_Vref; net out_coup_clock_p, out_coup_clock_n; // Test signals. net test_trace_bottom, test_trace_top; begin // This the fast DAC itself. Note how concisely the busses are connected. inst fast_dac of ad9739 is refDes = "U1"; VDDC = <+1V8>; VSSC = ; VDDA = <+3V3>; VSSA = ; VSSA_SHIELD = ; NC = open; IOUTN = ; IOUTP = ; I120 = I120; VREF = DAC_VREF; IPTAT = IPTAT; DACCLK_N = DACCLK_P; // clock polarity reversed for better routing. DACCLK_P = DACCLK_N; IRQ = IRQ; RESET = RESET; CS = SPI_CS; SDIO = SPI_SDI; SCLK = SPI_SCLK; SDO = SPI_SDO; VDD33 = <+3V3>; VDD = <+1V8>; VSS = ; SYNC_OUT_P = SYNC_OUT_P; SYNC_OUT_N = SYNC_OUT_N; SYNC_IN_P = SYNC_IN_P; SYNC_IN_N = SYNC_IN_N; DCO_P = DCO_P; DCO_N = DCO_N; DCI_P = DCI_P; DCI_N = DCI_N; DB1_P = DB1_P; DB1_N = DB1_N; DB0_P = DB0_P; DB0_N = DB0_N; end inst; From newsfish@newsfish Fri Feb 3 13:15:13 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Fri, 28 Oct 2011 09:59:37 +0000 (UTC) Organization: A noiseless patient Spider Lines: 66 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 28 Oct 2011 09:59:37 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="18417"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19rvNQ4Lsrytyo+Mp40ITH/b8O8j1D5t9U=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:2eZzfC/y+SKAC8RkUmaSEjhuBus= Xref: feeder.eternal-september.org comp.lang.vhdl:5348 On Thu, 27 Oct 2011 19:28:14 -0700, self wrote: > Guys > > I want to give you an update on the HDL for PCB work I have been doing. > Lately I have collaborated with the Configurable Computing Lab at > Brigham Young University to introduce a new, super simple HDL for board > design capture. A compiler has been written and tested on a few board > designs. > > The syntax of the language is highly simplified and efficient compared > to VHDL or even Verilog. > For boards with Xilinx FPGAs I have published a utility that > automatically generates the device declaration and instantiation > template to cut down on typing and mistakes. > > Please let me know what you think. It's a noble effort, but... To be honest, I suspect many of the changes from VHDL syntax are for no good reason (except looking "cool" to C programmers) and may be counterproductive. The most obvious example on a first look: Lose the "include". Learn from VHDL's use of packages and libraries, and move to something similar (or just copy it) Or discover that you have to write a new component library for virtually every PCB you make. Because includes don't scale beyond trivial examples. Even C programmers have to use a crude hack with #defines to avoid accidentally #including the same header file twice. And then consider namespace pollution. When you try to use the Spartan-3E-1000 from Jim's component library with the ADC from Fred's, you will find they both defined a Resistor and a Capacitor, and then you're stuck. Either you convince them to let you delete bits of their libraries, or you get to write your own... VHDL gives you tools like embedded configurations to solve the problem: Library Jim; Library Fred; ... use Fred.Components.all; ... for U1: Spartan3E_1000 use Jim.Components.Spartan3E_1000; Then, VHDL gives you generics and ports. These map quite well to your attrs and pins, so why change them? For example, you have to deal with things like half a dozen package types for resistors - even on the same board. Use the generic map to override the package type, and the port map to connect the pins. Sorry to be so critical, but you did ask. - Brian From newsfish@newsfish Fri Feb 3 13:15:14 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!4g2000yqu.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Fri, 28 Oct 2011 05:52:12 -0700 (PDT) Organization: http://groups.google.com Lines: 52 Message-ID: <2d34c7a3-8882-457f-9ae7-649eedfb5c00@4g2000yqu.googlegroups.com> References: NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1319806332 26864 127.0.0.1 (28 Oct 2011 12:52:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 28 Oct 2011 12:52:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 4g2000yqu.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.1; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5349 On Oct 27, 10:28=A0pm, self wrote: > Guys > > I want to give you an update on the HDL for PCB work I have been > doing. =A0Lately I have collaborated with the Configurable Computing Lab > at Brigham Young University to introduce a new, super simple HDL for > board design capture. The first question would be 'Why?'...followed by 'What improvements over current art does this bring to the table?'...so that would be some first metrics to hurdle...so we'll see how those questions get answered. > > The syntax of the language is highly simplified and efficient compared > to VHDL or even Verilog. These languages are not typically used to design boards so you're comparing your language to something that is not typically used for that purpose. The board design info is buried in a database that is unique to the specific design tool. VHDL and Verilog files can be generated as output from those tools, but that makes those files artifacts, not design files. > =A0The language lets you first define devices, > where functional port names are associated with pin numbers. =A0Then > your instantiate those devices and connect nets to the ports. =A0Device > ports can be single pins or busses. > OK...that would be an expected feature of any PCB design tool whether it is a schematic capture tool or a language. > > Please let me know what you think. > One basic piece of information that every part would need in a board design is the physical location on a board. While a property/ attribute could be defined for the part that will eventually contain that information for a particular board design that information would need to be editable on a per-instance basis. I'm pretty sure that when it comes to placement and layout, PCB people would prefer a graphic tool, not a text editor because part placement is concerned with visualizing interconnects (i.e. the 'rats nests'). This would end up meaning that your new language would, at best, become another file output artifact of the design tool, not the native design itself. In that sense, it would not appear to offer anything more than VHDL or Verilog...and since those languages are standards, your language would offer less. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:14 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Fri, 28 Oct 2011 09:31:06 -0700 Organization: Highland Technology, Inc. Lines: 48 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 28 Oct 2011 16:30:29 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DYs2I1YE9u8m/9i6AwWUPg"; logging-data="6811"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19SC+r21RQ/tt8T7vqdJknv" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 In-Reply-To: Cancel-Lock: sha1:WMJLOLlITxFR4TH1UfyQnern5js= Xref: feeder.eternal-september.org comp.lang.vhdl:5350 On 10/27/2011 7:28 PM, self wrote: > Guys > > I want to give you an update on the HDL for PCB work I have been > doing. Lately I have collaborated with the Configurable Computing Lab > at Brigham Young University to introduce a new, super simple HDL for > board design capture. A compiler has been written and tested on a few > board designs. [snip] Not sure I see the point to the exercise. When I'm writing VHDL to target an FPGA I've got access to a large (infinite if you consider device migration to be an option) number of repetitive resources. Under these circumstances, the idea of a language+compiler makes a lot of sense; it's mapping my high-level description of what I want onto these physical resources. That's when a text-based language is at it's best. The price I pay is, when I want to connect up the pseudo-devices I've built, I'm forced to use structural descriptions in my HDL. This is when a text-based language is at its worst. VHDL or Verilog, take your pick, both are wildly inferior to schematic capture at allowing you to visualize a design built by connecting together pre-existing blocks. Even if those blocks are just one file over. If there were any industry-standard schematic format, one that I could trust I could still open files in a decade from now, I'd use it for my structural hookup in a heartbeat. PCB design is all the connection of pre-existing blocks. You're not going to have a tool that compiles your high-level description to 2N4400s and 2N4402s. On top of that, where in an FPGA I only very rarely give a damn about placement, routing, etc, on a PCB it's absolutely critical. Impedance matching and termination issues, cross-talk issues, noise immunity issues (damn switchers), thermocouple effects, all matter and all need to be taken into account by hand. The board sitting on my desk right now has 550 parts on it, which makes it the least complex thing I've designed in a long while by nearly half. The idea of trying to put those parts together in one long sequential list rather than a graphic spread across two dimensions and multiple sheets, and to even hope to get it right, strikes me as abject lunacy. If it ain't broke... -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Fri Feb 3 13:15:15 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Direct entity instantiation... Date: Fri, 28 Oct 2011 18:33:35 +0000 (UTC) Organization: A noiseless patient Spider Lines: 91 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Fri, 28 Oct 2011 18:33:35 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="23925"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/n/JeOLGRh7RS6PWsRJSkBWfQJ9MdoWro=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:8Eipvlk+mQLqnpbc7uBWenubadA= Xref: feeder.eternal-september.org comp.lang.vhdl:5351 I have traditionally used components rather than directly instantiating entities, mostly out of habit, (or should I say, following established precedent :-) But now that I actually try direct instantiation, I am finding surprises... Simple example below ... I am instantiating two entities A_comp and B_comp from two component libraries A and B - one by component instantiation, the other directly. (Each entity asserts on elaboration, so that I can see it in synthesis or simulation) A (the component) just works (in Modelsim Actel Edition, 6.6) though I would have expected a Use clause or embedded configuration to be required. The library clause alone is enough to find it. Xilinx XST, alarmingly, doesn't even need that ! (Some magic in the project files finds it instead) B (the entity) can only be instantiated from library Work, not the library it is supposed to be in (and for this exercise, it has been compiled into both) Modelsim reports : "Illegal expanded name prefix" at b and "Cannot find expanded name b.b_comp" even though b_comp is in library B, and it has no trouble finding a.a_comp. Is this expected behaviour, that the only valid library for direct instantiation is "work"? And if so, why? It doesn't seem normal for the VHDL language to single out one specific library name like this... - Brian entity Toplevel is end Toplevel; library A; library B; --use A.all; --use B.all; architecture Behavioral of Toplevel is component A_comp end component; begin A : A_comp; B : entity B.B_comp(Behavioral); B2 : entity work.B_comp(Behavioral); end Behavioral; -------------------------- entity A_comp is end A_comp; architecture Behavioral of A_comp is function AA return boolean is begin assert false report "AA called" severity warning; return True; end function AA; constant AAA : boolean := AA; begin end Behavioral; -------------------------- entity B_comp is end B_comp; architecture Behavioral of B_comp is function BB return boolean is begin assert false report "BB called" severity warning; return True; end function BB; constant BBB : boolean := BB; begin end Behavioral; -------------------------- From newsfish@newsfish Fri Feb 3 13:15:15 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Newsgroups: comp.lang.vhdl Subject: Re: Direct entity instantiation... Date: Fri, 28 Oct 2011 20:16:37 +0000 (UTC) Organization: void Lines: 19 Message-ID: References: NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1319832997 23875 192.168.128.1 (28 Oct 2011 20:16:37 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Fri, 28 Oct 2011 20:16:37 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5352 Brian Drummond wrote: > Is this expected behaviour, that the only valid library for direct > instantiation is "work"? And if so, why? It doesn't seem normal for the > VHDL language to single out one specific library name like this... No, i wouldn't expect that. In your example, there seems to be a name conflict. If you change > B : entity B.B_comp(Behavioral); to > B1 : entity B.B_comp(Behavioral); it'll work. At least for me :) (Modelsim Altera Starter Edition 6.6d) Don't know why this doesn't happen for A, though. Enrik From newsfish@newsfish Fri Feb 3 13:15:15 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.bt.com!news.bt.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 29 Oct 2011 04:14:31 -0500 Date: Sat, 29 Oct 2011 10:14:28 +0100 From: MK User-Agent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.23) Gecko/20110920 Lightning/1.0b2 Thunderbird/3.1.15 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <9o-dnet7N6NqXjbTnZ2dnUVZ7qWdnZ2d@bt.com> Lines: 69 X-Usenet-Provider: http://www.giganews.com X-AuthenticatedUsername: NoAuthUser X-Trace: sv3-IRYKCzRmw77aCqwTvKZO3W+fX7W3is26FBlMSRmfz6qyQw2bpYa1axpd54TjVnv060CJQHUnLn/3WW8!NFguWNoehW2ry+9IYcdV98BbmPAT7mhIaJoQucTeUOiBk4gH2r9VLzzstfxCqYd2UB3cr/dxqz1P X-Complaints-To: abuse@btinternet.com X-DMCA-Complaints-To: abuse@btinternet.com X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4790 Xref: feeder.eternal-september.org comp.lang.vhdl:5353 On 28/10/2011 17:31, Rob Gaddi wrote: > On 10/27/2011 7:28 PM, self wrote: >> Guys >> >> I want to give you an update on the HDL for PCB work I have been >> doing. Lately I have collaborated with the Configurable Computing Lab >> at Brigham Young University to introduce a new, super simple HDL for >> board design capture. A compiler has been written and tested on a few >> board designs. > > [snip] > > Not sure I see the point to the exercise. When I'm writing VHDL to > target an FPGA I've got access to a large (infinite if you consider > device migration to be an option) number of repetitive resources. Under > these circumstances, the idea of a language+compiler makes a lot of > sense; it's mapping my high-level description of what I want onto these > physical resources. That's when a text-based language is at it's best. > > The price I pay is, when I want to connect up the pseudo-devices I've > built, I'm forced to use structural descriptions in my HDL. This is when > a text-based language is at its worst. VHDL or Verilog, take your pick, > both are wildly inferior to schematic capture at allowing you to > visualize a design built by connecting together pre-existing blocks. > Even if those blocks are just one file over. If there were any > industry-standard schematic format, one that I could trust I could still > open files in a decade from now, I'd use it for my structural hookup in > a heartbeat. > > PCB design is all the connection of pre-existing blocks. You're not > going to have a tool that compiles your high-level description to > 2N4400s and 2N4402s. On top of that, where in an FPGA I only very rarely > give a damn about placement, routing, etc, on a PCB it's absolutely > critical. Impedance matching and termination issues, cross-talk issues, > noise immunity issues (damn switchers), thermocouple effects, all matter > and all need to be taken into account by hand. > > The board sitting on my desk right now has 550 parts on it, which makes > it the least complex thing I've designed in a long while by nearly half. > The idea of trying to put those parts together in one long sequential > list rather than a graphic spread across two dimensions and multiple > sheets, and to even hope to get it right, strikes me as abject lunacy. > > If it ain't broke... > > Very interested in your second paragraph Brian, (The price I pay is ........). I find the (visualising) difficulty so great with VHDL that I do all my designs using Aldec HDL block diagram editor for the top level so that I can visualise the thing and it can stitch together all the connections. I (literally) can't imagine doing a complex design in text - I would end up doodling a block diagram in a notebook. On the other hand I would find it incredibly tedious to use the Block Diagram Editor to model/design a (for instance) SPI interface. The Aldec BDE compiles to standard and reasonably readable VHDL. I think the point with PCBs is that the existing tools make the switch between graphics and text at about the right place already - at least when used sensibly. I have seen some pcb schematics where just about every part with more than 8 pins has named stubs for every pin and thus a reasonable graphical tool is reduced to combining the worst features of text and graphic approaches. I can see use in a "PHDL" as an output from a pcb CAD system but it would need a lot more work (as pointed out in previous posts) to be any use. Michael Kellett From newsfish@newsfish Fri Feb 3 13:15:16 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Sat, 29 Oct 2011 05:56:50 -0500 Date: Sat, 29 Oct 2011 11:56:50 +0100 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux i686; rv:7.0) Gecko/20110927 Thunderbird/7.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Direct entity instantiation... References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 74 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-rD1kYCxnxPpfZzqnN8KZNI91Aa6hnppDdC/vC0Q9BA3gZ9G68s4nAVx4fFZrgJjtmHTPbZGM5926ckl!wodVnpiuZfenqRf1xAfincE5zAq/4ppaMURQ3CbTz1kfZ5LNHxW7h/frJU0UTyNRzDfuhZKafHQw!vhVi35+f8zzQ5uO+kfUHfDFPvg== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 4034 Xref: feeder.eternal-september.org comp.lang.vhdl:5354 On 28/10/11 21:16, enrik@starfleet.inka.de wrote: > Brian Drummond wrote: >> Is this expected behaviour, that the only valid library for direct >> instantiation is "work"? And if so, why? It doesn't seem normal for the >> VHDL language to single out one specific library name like this... > > No, i wouldn't expect that. In your example, there seems to be a name > conflict. If you change > >> B : entity B.B_comp(Behavioral); > > to > >> B1 : entity B.B_comp(Behavioral); > > it'll work. At least for me :) (Modelsim Altera Starter Edition 6.6d) > > Don't know why this doesn't happen for A, though. > > Enrik Hi Brian, as Enrik says there is a name conflict for B. The 2002 standard says "All concurrent statements may be labeled. Such labels are implicitly declared at the beginning of the declarative part of the innermost enclosing entity declaration, architecture body, block statement, or generate statement." So the label B is hiding the library B, because label B is declared in an enclosing scope. Regarding the second case, I think (!) the visibility is as follows: (all references to 1076-2002). 1. Section 5, specifications, says "A specification always relates to named entities that already exist; thus a given specification must either follow or (in certain cases) be contained within the declaration of the entity to which it relates. Furthermore, a specification must always appear either immediately within the same declarative part as that in which the declaration of the named entity appears, or (in the case of specifications that relate to design units or the interface objects of design units, subprograms, or block statements) immediately within the declarative part associated with the declaration of the design unit, subprogram body, or block statement." which means a configuration specification for a component must appear in the declarative region associated with the declaration of the component. So in your case, the component A_Comp is declared in the entity, therefore a configuration specification appears in the entity declarative region. 2. In 5.2.2 it is specified that there is a default binding indication if a component instance is not explicitly bound (which would appear in the entity declarative region). That default binding indication binds a visible entity declaration, which includes the case "c) An entity declaration denoted by L.C, where L is the target library and C is the simple name of the instantiated component. The target library is the library logical name of the library containing the design unit in which the component C is declared." which applies in your case. So because the implicit specification appears before the label A: has been declared, the library A is not hidden. regards Alan -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:15:16 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Direct entity instantiation... Date: Sat, 29 Oct 2011 11:46:51 +0000 (UTC) Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sat, 29 Oct 2011 11:46:51 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="15308"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/lvFZSdKQPDvJ4nWnZnU7Rns0YWsvtziE=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:eKKlmOW4nm79ZCt/2+NNN2QWE/k= Xref: feeder.eternal-september.org comp.lang.vhdl:5355 On Sat, 29 Oct 2011 11:56:50 +0100, Alan Fitch wrote: > On 28/10/11 21:16, enrik@starfleet.inka.de wrote: >> Brian Drummond wrote: >>> Is this expected behaviour, that the only valid library for direct >>> instantiation is "work"? And if so, why? It doesn't seem normal for >>> the VHDL language to single out one specific library name like this... >> >> No, i wouldn't expect that. In your example, there seems to be a name >> conflict. If you change >> >>> B : entity B.B_comp(Behavioral); >>> B1 : entity B.B_comp(Behavioral); >> >> it'll work. At least for me :) ( > Hi Brian, > as Enrik says there is a name conflict for B. ... > So the label B is hiding the library B, because label B is declared in > an enclosing scope. Thanks guys! Don't know why I didn't see that myself. It does clear one layer of confusion so that I can go on and look at the real problem. Step 1) Find problems with a real design and vendor tools... Step 2) Create a simple test case that fails in a different but vaguely similar way, (THIS is where I introduced the name conflict) Step 3) Find that the test case also fails in Modelsim Step 4) Post to Usenet, exposing a basic beginner mistake to the world... Now I can move on to Step 5... looking for the real problem. > Regarding the second case, I think (!) the visibility is as follows: > (all references to 1076-2002). ... > > So because the implicit specification appears before the label A: has > been declared, the library A is not hidden. Thank you! - Brian From newsfish@newsfish Fri Feb 3 13:15:17 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!1g2000vbx.googlegroups.com!not-for-mail From: Elnaz Newsgroups: comp.lang.vhdl Subject: Distributed Arithmetic in VHDL Date: Sun, 30 Oct 2011 07:55:33 -0700 (PDT) Organization: http://groups.google.com Lines: 5 Message-ID: <2b86715d-239c-4d31-a253-b6e2dacd2937@1g2000vbx.googlegroups.com> NNTP-Posting-Host: 143.215.144.78 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1319986533 24223 127.0.0.1 (30 Oct 2011 14:55:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 30 Oct 2011 14:55:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: 1g2000vbx.googlegroups.com; posting-host=143.215.144.78; posting-account=ID3FFgoAAACqV9V3tSIyR3FgGDa8emhT User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20100101 Firefox/7.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5356 Hi everybody, I need a simple vhdl code for signed distributed arithmetic. I want to calculate the result of an inner product with distributed arithmetic (FIR filter). Can you guide me to some sources please? From newsfish@newsfish Fri Feb 3 13:15:17 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Direct entity instantiation... Date: Sun, 30 Oct 2011 22:33:36 +0000 (UTC) Organization: A noiseless patient Spider Lines: 24 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Sun, 30 Oct 2011 22:33:36 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="3634"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/MvbKa0Us9BEIVoStjLvz7xpNqDEGXPto=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:9xgvAFgdjhxkx9ZZ9DU0Pn6X9H8= Xref: feeder.eternal-september.org comp.lang.vhdl:5357 On Sat, 29 Oct 2011 11:46:51 +0000, Brian Drummond wrote: > On Sat, 29 Oct 2011 11:56:50 +0100, Alan Fitch wrote: > >> On 28/10/11 21:16, enrik@starfleet.inka.de wrote: >>> No, i wouldn't expect that. In your example, there seems to be a name >>> conflict. ... >> So the label B is hiding the library B, because label B is declared in >> an enclosing scope. > Don't know why I didn't see that myself. It does clear one layer of > confusion so that I can go on and look at the real problem. Which turned out to be a different name conflict, but also hiding the library. Thanks for providing the extra eyes... I've been spoiled by the Gnat Ada compiler, which is uncannily good at diagnostics : after "Cannot find name ..." types of errors, it prints a list of likely candidates with the reason they are hidden or not uniquely resolved... - Brian From newsfish@newsfish Fri Feb 3 13:15:17 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!goblin3!goblin1!goblin.stu.neva.ru!news2.euro.net!feeder.news-service.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe06.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Gary's comment on languages Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111030-1, 30/10/2011), Outbound message X-Antivirus-Status: Clean Lines: 41 Message-ID: <9rurq.10248$V_3.9715@newsfe06.ams2> NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe06.ams2 1320055621 86.29.13.122 (Mon, 31 Oct 2011 10:07:01 UTC) NNTP-Posting-Date: Mon, 31 Oct 2011 10:07:01 UTC Organization: virginmedia.com Date: Mon, 31 Oct 2011 10:07:01 +0000 Xref: feeder.eternal-september.org comp.lang.vhdl:5358 Hi All, I found the statement below (VHDL is better than Verilog) from Gary Smith quite refreshing (if that is the right word) if you consider he operates in the same "world" as Aart De Geus (CEO Synopsys) who said that VHDL is dead and perhaps more infamously Joe Costello (ex CEO Cadence) who said that VHDL was a $400 million dollar mistake. Gary replied to a John Cooley question on C/C++/SystemC Synthesis: http://www.deepchip.com/items/0494-02.html Hans www.ht-lab.com PS I am not trying to start a language war, we all know that both Verilog and VHDL are great RTL languages. From: Gary Smith Hi, John, A little history for those that aren't into language development. VHDL is a superior RTL language over Verilog. FORTRAN and Ada are superior parallel languages over C and the multiple C variants. The point is that unless there is a major revolt among Embedded Programmers we are stuck with C and SystemC. Catapult C, coming from the C side, and Forte, coming from the SystemC side, have done the best job of meeting design engineers demands based on inferior languages. Just as Design Compiler did for the RTL engineers. We've done a lot of ESL based tape outs over the last eight years. Saying that Catapult C is a failure is like saying Design Compiler was a failure in 1994. It ain't perfect but it's the best we've got; and it's improving every year. Don't blame the tools, blame the language. - Gary Smith Gary Smith EDA Santa Clara, CA From newsfish@newsfish Fri Feb 3 13:15:18 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l12g2000vby.googlegroups.com!not-for-mail From: Nikolaos Kavvadias Newsgroups: comp.lang.vhdl,comp.lang.verilog,comp.arch.fpga,comp.arch.embedded Subject: [ANN] Free web access to the HercuLeS high-level synthesis tool Date: Mon, 31 Oct 2011 05:10:40 -0700 (PDT) Organization: http://groups.google.com Lines: 34 Message-ID: <064f184b-ee86-44e0-8057-fdf9e48b8466@l12g2000vby.googlegroups.com> NNTP-Posting-Host: 94.70.8.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1320063150 32286 127.0.0.1 (31 Oct 2011 12:12:30 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 31 Oct 2011 12:12:30 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l12g2000vby.googlegroups.com; posting-host=94.70.8.211; posting-account=lD5X3AoAAAB2_KDReA0WuoP_A_fBgycC User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:7.0.1) Gecko/20100101 Firefox/7.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5359 comp.lang.verilog:3193 comp.arch.fpga:16679 comp.arch.embedded:25350 Dear all i'm pleased to announce that free access to the web interface of the HercuLeS high-level synthesis tool is now available. HercuLeS allows you to synthesize ANSI C code or generic-assembly code (certain rules apply) to RTL VHDL. The web interface can be accessed from here: http://www.nkavvadias.com/cgi-bin/herc.cgi A short how-to, simulation packages and ready-to-use examples are accessible from the same page. Additional information can be found here: http://www.nkavvadias.com/hercules/index.html The major limitation of the free web service is that user programs should not expand to more than 25 generic assembly (NAC) statements. All the provided examples in the small-examples.zip file respect this limitation. Contact ------- HercuLeS information: hercules-info#at#nkavvadias.com (replace #at# appropriately) Personal email: nikolaos.kavvadias#at#gmail-dot-com (replace #at# and -dot- appropriately). Best regards, Nikolaos Kavvadias Research Scientist, Hardware developer Ph.D., M.Sc., B.Sc. From newsfish@newsfish Fri Feb 3 13:15:18 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.news-service.com!news2.euro.net!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4eaeaa57$0$6862$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Direct entity instantiation... Newsgroups: comp.lang.vhdl Date: Mon, 31 Oct 2011 15:01:59 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 182 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1320069719 news2.news.xs4all.nl 6862 puiterl/195.242.97.150:46526 Xref: feeder.eternal-september.org comp.lang.vhdl:5360 Brian Drummond wrote: > On Sat, 29 Oct 2011 11:46:51 +0000, Brian Drummond wrote: > >> On Sat, 29 Oct 2011 11:56:50 +0100, Alan Fitch wrote: >> >>> On 28/10/11 21:16, enrik@starfleet.inka.de wrote: > >>>> No, i wouldn't expect that. In your example, there seems to be a name >>>> conflict. > ... >>> So the label B is hiding the library B, because label B is declared in >>> an enclosing scope. > >> Don't know why I didn't see that myself. It does clear one layer of >> confusion so that I can go on and look at the real problem. > > Which turned out to be a different name conflict, but also hiding the > library. Thanks for providing the extra eyes... > > I've been spoiled by the Gnat Ada compiler, which is uncannily good at > diagnostics : after "Cannot find name ..." types of errors, it prints a > list of likely candidates with the reason they are hidden or not uniquely > resolved... Yep, the error messages by ModelSim/QuestaSim leaves quite a bit to be desired in the clarity department. A year ago I entered a service request to get a more clear message for the 'No feasible entries for subprogram ""' error. Below is my complete SR text. The answer was: Unfortunately, the ER was turned down by Questa Engineering. Suggested using one of the linting tools: Leda, HDLint, nLint or SureLint. Sigh.... I have no idea if these tools would produce a better error message in my case.. The reasons for turning down my SR are: -criticality of the issue, -the number of customers reporting the issue, -the resources involved in making the change, -strategic product direction. Of course, we all can do something about the second point. Anyhow, here is the text of my service request: One of the most dreaded error messages that exists when analyzing VHDL with vcom is the message 'No feasible entries for subprogram ""'. Even for seasoned VHDL programmers it is sometime daunting to solve such an error. Let alone the time it takes for a novice VHDL programmer to solve such an error. The reason why it can be daunting to solve such an error, is that vcom does not give any additional information as of why there are no feasible entries. Or even what the entries are that have been considered before deaclaring it an error. So what I would like to suggest is to enhance the error message with more information, and possibly the reason for the error. Ideally, this should give the user enough information to solve the problem in no time. I hope what I proposes is technically feasible. As an example, take the following piece of code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE my_pkg IS PROCEDURE my_proc (ch: natural; n: natural ); PROCEDURE my_proc (ch: natural; n: std_logic_vector ); PROCEDURE my_proc (ch: natural; n: std_ulogic ); END PACKAGE my_pkg; PACKAGE BODY my_pkg IS PROCEDURE my_proc (ch: natural; n: natural ) IS BEGIN END PROCEDURE my_proc; PROCEDURE my_proc (ch: natural; n: std_logic_vector ) IS BEGIN END PROCEDURE my_proc; PROCEDURE my_proc (ch: natural; n: std_ulogic ) IS BEGIN END PROCEDURE my_proc; END PACKAGE BODY my_pkg; ENTITY e IS END ENTITY e; USE work.my_pkg.ALL; -- LIBRARY ieee; -- USE ieee.std_logic_1164.ALL; -- Missing! ARCHITECTURE a OF e IS BEGIN doit: PROCESS IS BEGIN my_proc(123, '0'); -- Type mismatch due to std_(u)logic is not visible my_proc(123, nn => 0); -- Wrong formal parameter name WAIT; END PROCESS doit; END ARCHITECTURE a; Current vcom errors: ** Error: no_feasible_entries.vhd(36): No feasible entries for subprogram "my_proc". ** Error: no_feasible_entries.vhd(37): No feasible entries for subprogram "my_proc". ** Error: no_feasible_entries.vhd(40): VHDL Compiler exiting The first call of my_proc is not OK, because std_(u)logic is not visible. Therefore, the actual for the second parameter is only interpreted as a character or bit. It took me more than five minutes before I figured out that USE clause with std_logic_1164 was missing and that that was the culprit. The not so experienced user who made this error was stumped for much much longer. The second call of my_proc is not OK, because the name of a formal is not correct. Also this situation can be daunting at times. That's why I would like to propose a much more verbose error message. Something along these lines: ** Error: no_feasible_entries.vhd(36): No feasible entries for subprogram "my_proc". Visible declaration of subprogram "my_proc": work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [natual]); work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [std_logic_vector]); work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [std_ulogic]); Possible interpretation of subprogram call: work.my_pkg.my_proc(ch => [natural constant]; n => [character constant]); work.my_pkg.my_proc(ch => [natural constant]; n => [bit constant]); Matched parameter(s) : ch Unmatched parameter : n (type error) ** Error: no_feasible_entries.vhd(37): No feasible entries for subprogram "my_proc". Visible declaration of subprogram "my_proc": work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [natual]); work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [std_logic_vector]); work.my_pkg.my_proc(constant ch: in [natural]; constant n: in [std_ulogic]); Possible interpretation of subprogram call: work.my_pkg.my_proc(ch => [natural constant]; nn => [character constant]); work.my_pkg.my_proc(ch => [natural constant]; nn => [bit constant]); work.my_pkg.my_proc(ch => [natural constant]; nn => [std_ulogic constant]); (assuming missing USE clause is present) Matched parameter(s) : ch Unmatched parameter : nn (no such name) Missing parameter(s) : n So first of all I would like to know what declarations of the subprogram are visible. Secondly, I would like to know what possible interpretations there are for my subprogram call. Finally, it would be very usefull to have an overview of matched, unmatched and missing parameters, given the visible declarations and the possible interpretations of the call. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:15:19 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!a12g2000vbz.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Tue, 1 Nov 2011 00:18:01 -0700 (PDT) Organization: http://groups.google.com Lines: 38 Message-ID: <464e50ef-5ff0-4876-b8c1-cd229a1f7589@a12g2000vbz.googlegroups.com> References: NNTP-Posting-Host: 194.94.26.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1320132297 30275 127.0.0.1 (1 Nov 2011 07:24:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 1 Nov 2011 07:24:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: a12g2000vbz.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:7.0.1) Gecko/20100101 Firefox/7.0.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5361 Hi, someone remembering EDIF? It can be used for all kinds of netlists. Schematic, Circuit (eg. IP-Cores) and also PCBs. And it's standardized. (IEC 61690-2) As already mentioned by others, netlist files are in general created and read by some software, rarely by humans. So complexity shouldn't be the problem. (One might think of some XEDIF format in the future, which makes a hhange in the syntax to something XML compatible to ease up software design) So, what has this "new PHDL" to offer instead of endless lists of name assignments? I could see some attributes for device naming purposes and even a cost factor in the example. But where can one describe locations, track attributes, timing constraints and other relevant things that come to mind when designing a PCB? Instead of just another netlist format it would be more interesting to have a "language" that just concentrates on doing the real design stuff for PCBs, such as constraints, while the pure netlisting is already solved and noone wants to do it "by hand" anyway. In the FPGA world we find something similar in the UCF files (from Xilinx, other vendors may have differnt names for the same). Tools read in some netlist and then apply the UCF constraints to allow controll over the physical layout. Something similar for PCBs, in a standardized way(!), would be nice indeed. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:15:19 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!i6g2000prm.googlegroups.com!not-for-mail From: self Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Mon, 14 Nov 2011 18:24:53 -0800 (PST) Organization: http://groups.google.com Lines: 99 Message-ID: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> References: NNTP-Posting-Host: 68.35.127.28 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1321323896 25937 127.0.0.1 (15 Nov 2011 02:24:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Nov 2011 02:24:56 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i6g2000prm.googlegroups.com; posting-host=68.35.127.28; posting-account=buE9zAoAAADInp_5AizVMCbrLTmYl6wQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; OfficeLiveConnector.1.4; OfficeLivePatch.1.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5362 Hello Guys, Thanks for responding. I want to apologize for the original out of context post. I intended to reply to an existing thread where we were already talking about using HDL to describe circuits for PCB construction. I'll try to explain here now. I have been designing printed circuit assemblies for over 20 years. During that time HDL has almost completely taken over the logic design business. You all know the advantages of text for logic design but I will repeat some of them here. - Abstraction - Portability - Standardization - Readability - Maintainability - Efficiency - Version control compatibility - Code generation PHDL (PCB HDL) is an attempt to achieve the same advantages for printed circuit connectivity definition, the part of the printed circuit design process that is currently done with schematic diagrams. PHDL does nothing for the layout part of the design process because that is naturally a drafting operation and we are pretty satisfied with the commercial tools available for layout. Printed circuit design connectivity definition is a much simpler task than logic design. You are only instantiating chips and wiring them up. You don't need data types, signal assignments or boolean functions for example. For that reason we developed a super simple HDL specifically for the task of designing printed circuit boards. Also, printed circuit board design is a very important engineering task, perhaps as important as logic design, so it deserves its own language optimized for that purpose. PHDL is a design language. Component ports are associated with their physical pin numbers in a device declaration. Then you instantiate parts and attach signals to them, nothing fancy. The language has many syntactical features that provide abstraction, reduce typing and help minimize errors. The current version of the compiler already provides a good bit of error checking. At first I thought that we could use VHDL but it does not directly support pin numbers in component declarations. You have to devise some new attributes and process them specially to associate pin numbers with entity ports. The pin number attribute cannot be on the same line with the entity port but rather has to follow all the port declarations. You would have to play a similar game for all the other stuff like PKG_TYPE, PART_NUMBER, etc. The syntax gets very ugly and requires a tremendous amount of typing. Our compiler can already output netlist formats for PADS and Eagle. It is easy to create more output formats and we want to support Altium and VHDL netlist outputs. The VHDL would be for anyone who might want to simulate or graphically view the structure of their design in an RTL viewer. Eilert, I like your idea of a standard language for PCB physical constraints but you would have to get a bunch of CAE companies to agree on a standard. That's not what we are trying to do. Our compiler is written in java so you can run it on any machine, including a smart phone in a pinch. The compiler executeable is a "jar" file that can be archived along with the board design for infinite maintainability. Of course, the board design source is text and text editors will exist forever. I find PHDL syntax to be quite readable and it provides both // and /* */ style comment operators. I find myself writing the comments first then filling in the circuits afterwords. To avoid most of the typing on big FPGA boards I wrote a Xilinx2PHDL converter that automatically generates most of the text for the board. When you have text design entry it opens up all kinds of possibilities for autogeneration. I'm working on the Actel2PHDL and Altera2PHDL converters now. To my mind the biggest advantage of PHDL over graphical schematics is compatibility with version control tools. Because it is text, I can look back at every change ever made to the design. We have already designed several printed circuit boards using PHDL. Originally I thought it would be best for high pin count FPGA boards but we have used it for analog and power boards and those read well also. It is amazing how a few comments can help with the board design process. On the other hand, we understand that a lot of people just like drawing pictures of board designs and are willing to use proprietary tools to do it. We are just offering an alternative to those HDL types who prefer a very direct and open design methodology. Anyway, that is enough for today. Pete From newsfish@newsfish Fri Feb 3 13:15:20 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Rob Gaddi Newsgroups: comp.lang.vhdl Subject: SystemVerilog for verification Date: Tue, 15 Nov 2011 09:28:01 -0800 Organization: Highland Technology, Inc. Lines: 30 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 15 Nov 2011 17:26:20 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DYs2I1YE9u8m/9i6AwWUPg"; logging-data="7228"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/PwY8AB6JlXjgciWtVLvk4" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20111105 Thunderbird/8.0 Cancel-Lock: sha1:NIWSuwCrEJRyY2R3YWP5ltpp8Qc= Xref: feeder.eternal-september.org comp.lang.vhdl:5363 Oh good, a topic to start a flame war with... So I consider myself pretty comfortable with VHDL. I use it for my synthesizable designs. I use it for my testbenches. Occasionally I'll write a VHDL behavioral model and run it through my simulator just to generate timing diagram waveforms for people. I can, given sufficient time and energy, muddle through reading Verilog. Never written a line of it. But I'm getting a vague sense, possibly out of frustration, that a whole lot of verification benches, especially as you're trying to get up into transaction level bus models, get easier in SystemVerilog than they are doing it in VHDL, even with the 2008 improvements. I'm pretty used to doing OOP in languages like Python, C++, and Perl, and the idea of calling bus_master.write(address, data); seems like a pretty natural way of stringing a bench together. The options for doing similar in VHDL (procedures with a billion signal parameters or entities with abstract req/ack ports and 'transaction signaling) seem, comparatively, pretty crude. I've made them work time and again, but I can't say I've ever sat back and read it back over and said "You know, that's pretty elegant." I have no intention of giving up VHDL for my synthesizables; I cling to strong typing like Linus to his blanket. But am I doing myself a disservice by not learning SV? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix. From newsfish@newsfish Fri Feb 3 13:15:20 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!p7g2000pre.googlegroups.com!not-for-mail From: NeedCleverHandle Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Tue, 15 Nov 2011 11:08:43 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: References: NNTP-Posting-Host: 65.60.96.146 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1321384224 27581 127.0.0.1 (15 Nov 2011 19:10:24 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 15 Nov 2011 19:10:24 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p7g2000pre.googlegroups.com; posting-host=65.60.96.146; posting-account=n4ptawoAAADIy4CdzQZ8-XZTeH7G74EM User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.8 (KHTML, like Gecko) Chrome/17.0.938.0 Safari/535.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5364 On Nov 15, 9:28=A0am, Rob Gaddi wrote: > Oh good, a topic to start a flame war with... > > So I consider myself pretty comfortable with VHDL. =A0I use it for my > synthesizable designs. =A0I use it for my testbenches. =A0Occasionally I'= ll > write a VHDL behavioral model and run it through my simulator just to > generate timing diagram waveforms for people. > > I can, given sufficient time and energy, muddle through reading Verilog. > =A0 Never written a line of it. =A0But I'm getting a vague sense, possibl= y > out of frustration, that a whole lot of verification benches, especially > as you're trying to get up into transaction level bus models, get easier > in SystemVerilog than they are doing it in VHDL, even with the 2008 > improvements. > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. =A0The options for doin= g > similar in VHDL (procedures with a billion signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. =A0I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." > > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. =A0But am I doing myself a > disservice by not learning SV? > > -- > Rob Gaddi, Highland Technology --www.highlandtechnology.com > Email address domain is currently out of order. =A0See above to fix. I use VHDL and Verilog in equal amounts. When asked which I prefer, I always say "the other one" - there's always something the other language does better. SystemVerilog has a lot of the features of VHDL that I miss when coding in Verilog - IMnsHO, enough that I think you should look at it. If only I could trust Brand-X to synthesize it properly - right now I use it for verification only. RK From newsfish@newsfish Fri Feb 3 13:15:20 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Tue, 15 Nov 2011 13:16:51 -0600 Organization: A noiseless patient Spider Lines: 43 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Tue, 15 Nov 2011 19:16:51 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="LAkyUQyz6k9Ol2KuME6NXQ"; logging-data="19476"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX187x1Ax2YppnQpRaGkRYfWF" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: Cancel-Lock: sha1:D5ZFOdnuibd2MC2jtUbGsNX3PZI= Xref: feeder.eternal-september.org comp.lang.vhdl:5365 On 11/15/2011 11:28 AM, Rob Gaddi wrote: > Oh good, a topic to start a flame war with... > > So I consider myself pretty comfortable with VHDL. I use it for my > synthesizable designs. I use it for my testbenches. Occasionally I'll > write a VHDL behavioral model and run it through my simulator just to > generate timing diagram waveforms for people. > > I can, given sufficient time and energy, muddle through reading Verilog. > Never written a line of it. But I'm getting a vague sense, possibly out > of frustration, that a whole lot of verification benches, especially as > you're trying to get up into transaction level bus models, get easier in > SystemVerilog than they are doing it in VHDL, even with the 2008 > improvements. > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. The options for doing > similar in VHDL (procedures with a billion signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." > > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. But am I doing myself a > disservice by not learning SV? > I use Python via MyHDL for all my verification unless dictated otherwise. As you point out, you can easily build up transaction interfaces to the DUT. With MyHDL bridging the HLL to the cycles and bits is a breeze. I have used it successfully on our last mixed-sginal ASIC design (small'sh design but all verification via Python/MyHDL). I do keep up with SystemVerilog but that is mainly out of curiosity and for job prospects if I ever need it. Not all places are open to alternative solutions. Also, integrating my signal-processing system design/simulations and leveraging it for HDL verification is straight-forward. Regards, Chris From newsfish@newsfish Fri Feb 3 13:15:22 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe23.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111115-1, 15/11/2011), Outbound message X-Antivirus-Status: Clean Lines: 58 Message-ID: NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe23.ams2 1321435380 86.29.13.122 (Wed, 16 Nov 2011 09:23:00 UTC) NNTP-Posting-Date: Wed, 16 Nov 2011 09:23:00 UTC Organization: virginmedia.com Date: Wed, 16 Nov 2011 09:23:01 +0000 Xref: feeder.eternal-september.org comp.lang.vhdl:5366 On 15/11/2011 17:28, Rob Gaddi wrote: > Oh good, a topic to start a flame war with... > > So I consider myself pretty comfortable with VHDL. I use it for my > synthesizable designs. I use it for my testbenches. Occasionally I'll > write a VHDL behavioral model and run it through my simulator just to > generate timing diagram waveforms for people. > > I can, given sufficient time and energy, muddle through reading Verilog. > Never written a line of it. But I'm getting a vague sense, possibly out > of frustration, that a whole lot of verification benches, especially as > you're trying to get up into transaction level bus models, get easier in > SystemVerilog than they are doing it in VHDL, even with the 2008 > improvements. > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. The options for doing > similar in VHDL (procedures with a billion signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." > > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. But am I doing myself a > disservice by not learning SV? > It can never hurt to learn a new language and to have something else to mention on your CV, but make sure it is actually useful to you. If you are planning to use a verification framework like OVM/UVM/VMM etc then I would say go for it and learn SV (or SC). Make sure however that your employer has the budget to buy a simulator capable of handling SV for verification and not just for design (huge price difference). If you need more verification power like constraint random, functional coverage etc then you can perfectly stay with VHDL. Just check out some of the packages available on the web like Jim Lewis' excellent Constraint Random and Coverage packages. http://www.synthworks.com/downloads/index.htm Throw in some PSL goodness and you have a very powerful/capable functional verification environment. Given you like OOP you might also want to check out SystemC, if you are a Modelsim user then it is the cheapest way to get access to an OOP language, TLM2.0, AMS(?) and CR. The interface between VHDL and SystemC is pretty good. You might even be able to use OVM via the free OVM-ML package from Cadence although I haven't played with it myself. Good luck, Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:15:22 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Wed, 16 Nov 2011 08:39:03 -0600 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 16 Nov 2011 14:39:03 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="LAkyUQyz6k9Ol2KuME6NXQ"; logging-data="20826"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18VO1s6ARAHLMpCEJj/dToO" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: Cancel-Lock: sha1:4d/TNAQDkCuiDdYcIYdzrT6eMig= Xref: feeder.eternal-september.org comp.lang.vhdl:5367 > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. The options for doing > similar in VHDL (procedures with a billion signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." > > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. But am I doing myself a > disservice by not learning SV? > If you do decide to use SystemVerilog for verification, get the 3rd edition of "SystemVerilog for Verification" http://www.buchhandel.de/detailansicht.aspx?isbn=9781461407140 Very good resource! Chris From newsfish@newsfish Fri Feb 3 13:15:23 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Wed, 16 Nov 2011 09:02:58 -0600 Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 16 Nov 2011 15:02:59 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="LAkyUQyz6k9Ol2KuME6NXQ"; logging-data="30448"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/chFHl3S4RR+5MQLnp0AdW" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: Cancel-Lock: sha1:GGgKAqWYQbiFY0uw3A7J/+6PM9Y= Xref: feeder.eternal-september.org comp.lang.vhdl:5368 > > Given you like OOP you might also want to check out SystemC, if you are > a Modelsim user then it is the cheapest way to get access to an OOP > language, TLM2.0, AMS(?) and CR. The interface between VHDL and SystemC > is pretty good. You might even be able to use OVM via the free OVM-ML > package from Cadence although I haven't played with it myself. > I think SystemC/C++, in this context, is a waste of time and effort. Every verification effort that I have been involved with that uses SystemC has had to devoted a fair number of resources to C++ development and maintenance. In my opinion SystemC/C++ is antiquated and there are better options available. I believe Hans' main point is, if you want to use the advanced verification features of SV you will need to shell out some money for an SV simulator. And a cheaper alternative is SystemC. But my take, SystemC is anti-productive, you are better off leveraging SV/Python/Ruby/Matlab/Java any HLL that empowers the developer. SystemC is for the large organizations that can devote the resources. In my opinion you will spend more money developing C++ code than you will on an SV enabled simulator. Regards, Chris From newsfish@newsfish Fri Feb 3 13:15:23 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!y42g2000yqh.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Wed, 16 Nov 2011 11:00:25 -0800 (PST) Organization: http://groups.google.com Lines: 136 Message-ID: References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> NNTP-Posting-Host: 192.91.173.36 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1321470498 30574 127.0.0.1 (16 Nov 2011 19:08:18 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 16 Nov 2011 19:08:18 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: y42g2000yqh.googlegroups.com; posting-host=192.91.173.36; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5369 On Nov 14, 8:24=A0pm, self wrote: > Hello Guys, > > Thanks for responding. > > I want to apologize for the original out of context post. I intended > to reply to an existing thread where we were already talking about > using HDL to describe circuits for PCB construction. I'll try to > explain here now. > > I have been designing printed circuit assemblies for over 20 years. > During that time HDL has almost completely taken over the logic design > business. =A0You all know the advantages of text for logic design but I > will repeat some of them here. > > - Abstraction > - Portability > - Standardization > - Readability > - Maintainability > - Efficiency > - Version control compatibility > - Code generation > > PHDL (PCB HDL) is an attempt to achieve the same advantages for > printed circuit connectivity definition, the part of the printed > circuit design process that is currently done with schematic > diagrams. =A0PHDL does nothing for the layout part of the design process > because that is naturally a drafting operation and we are pretty > satisfied with the commercial tools available for layout. > > Printed circuit design connectivity definition is a much simpler task > than logic design. =A0You are only instantiating chips and wiring them > up. You don't need data types, signal assignments or boolean functions > for example. For that reason we developed a super simple HDL > specifically for the task of designing printed circuit boards. Also, > printed circuit board design is a very important engineering task, > perhaps as important as logic design, so it deserves its own language > optimized for that purpose. > > PHDL is a design language. =A0Component ports are associated with their > physical pin numbers in a device declaration. Then you instantiate > parts and attach signals to them, nothing fancy. =A0The language has > many syntactical features that provide abstraction, reduce typing and > help minimize errors. The current version of the compiler already > provides a good bit of error checking. > > At first I thought that we could use VHDL but it does not directly > support pin numbers in component declarations. You have to devise some > new attributes and process them specially to associate pin numbers > with entity ports. =A0The pin number attribute cannot be on the same > line with the entity port but rather has to follow all the port > declarations. You would have to play a similar game for all the other > stuff like PKG_TYPE, PART_NUMBER, etc. The syntax gets very ugly and > requires a tremendous amount of typing. > > Our compiler can already output netlist formats for PADS and Eagle. It > is easy to create more output formats and we want to support Altium > and VHDL netlist outputs. The VHDL would be for anyone who might want > to simulate or graphically view the structure of their design in an > RTL viewer. > > Eilert, I like your idea of a standard language for PCB physical > constraints but you would have to get a bunch of CAE companies to > agree on a standard. That's not what we are trying to do. > > Our compiler is written in java so you can run it on any machine, > including a smart phone in a pinch. =A0The compiler executeable is a > "jar" file that can be archived along with the board design for > infinite maintainability. Of course, the board design source is text > and text editors will exist forever. > > I find PHDL syntax to be quite readable and it provides both // and /* > */ style comment operators. =A0I find myself writing the comments first > then filling in the circuits afterwords. > > To avoid most of the typing on big FPGA boards I wrote a Xilinx2PHDL > converter that automatically generates most of the text for the > board. =A0When you have text design entry it opens up all kinds of > possibilities for autogeneration. I'm working on the Actel2PHDL and > Altera2PHDL converters now. > > To my mind the biggest advantage of PHDL over graphical schematics is > compatibility with version control tools. Because it is text, I can > look back at every change ever made to the design. > > We have already designed several printed circuit boards using PHDL. > Originally I thought it would be best for high pin count FPGA boards > but we have used it for analog and power boards and those read well > also. =A0It is amazing how a few comments can help with the board design > process. > > On the other hand, we understand that a lot of people just like > drawing pictures of board designs and are willing to use proprietary > tools to do it. We are just offering an alternative to those HDL types > who prefer a very direct and open design methodology. > > Anyway, that is enough for today. > > =A0 Pete Several years ago, I looked at using vhdl for pwb netlists. Most schematic capture systems understand the distinction between a symbol and a package. The same symbol may map into multiple packages, each with different pin numbers. You can make the vhdl entities be the packages, and components the "schematic symbols" Then you define configurations to map component (with logical port names) to entities (with phisical port names). These can be named configurations that each map one component to one entity. Then you would just code up your netlist instantiating the components, and write a configuration that defines which package each component will use. The part I could not figure out was that most schematic capture systems are capable of using symbols that represent part of a package, not the whole package (e.g. quad nand gate parts, resistor networks, etc.). So I eventually dropped the idea. I like drawing schematics better anyway. I don't have to name a wire if I don't want to, it takes care of it for me. I can have one symbol pin or wire represent an entire bus and one symbol represent multiple components (e.g. 32 pullup resistors) or multiple parts of one or more components, etc. Purely structural use of HDL is one of its weaker applications. You might as well code an edif netlist. It is difficult to visualize interconnect between a half dozen high port-count components when the only clue you have is matching signal names. Andy From newsfish@newsfish Fri Feb 3 13:15:24 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z22g2000prd.googlegroups.com!not-for-mail From: Dal Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Wed, 16 Nov 2011 13:51:34 -0800 (PST) Organization: http://groups.google.com Lines: 56 Message-ID: References: NNTP-Posting-Host: 220.233.20.160 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1321480295 9231 127.0.0.1 (16 Nov 2011 21:51:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 16 Nov 2011 21:51:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z22g2000prd.googlegroups.com; posting-host=220.233.20.160; posting-account=cLKrmQoAAADvYn7mqHe2j39Tnor0ErkH User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HELCSRUA X-HTTP-UserAgent: Mozilla/5.0 (Linux; U; Android 2.2; en-au; HTC Legend Build/FRF91) AppleWebKit/533.1 (KHTML, like Gecko) Version/4.0 Mobile Safari/533.1,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5370 I have been using SV to implement a test bench for my current project. I didn't get into OVM/UML but just used the language to create a simple test environment. I find the language features very useful (objects, randomization, queues, fork/join etc) and a very 'natural' way to develop test code. I can't see myself going back. SV seems suitable for simple and complex designs and also allows the engineer to start simply which is important as I was self taught as training is non-existant in my part of the world. I would always still use VHDL for synthesizable code. My only gripe is there does seem to be a premium on the licence (at least with Cadence). I am disappointed vendors didn't treat it as Verilog from a licencing point of view. Darrin On Nov 16, 4:28=A0am, Rob Gaddi wrote: > Oh good, a topic to start a flame war with... > > So I consider myself pretty comfortable with VHDL. =A0I use it for my > synthesizable designs. =A0I use it for my testbenches. =A0Occasionally I'= ll > write a VHDL behavioral model and run it through my simulator just to > generate timing diagram waveforms for people. > > I can, given sufficient time and energy, muddle through reading Verilog. > =A0 Never written a line of it. =A0But I'm getting a vague sense, possibl= y > out of frustration, that a whole lot of verification benches, especially > as you're trying to get up into transaction level bus models, get easier > in SystemVerilog than they are doing it in VHDL, even with the 2008 > improvements. > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. =A0The options for doin= g > similar in VHDL (procedures with a billion signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. =A0I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." > > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. =A0But am I doing myself a > disservice by not learning SV? > > -- > Rob Gaddi, Highland Technology --www.highlandtechnology.com > Email address domain is currently out of order. =A0See above to fix. From newsfish@newsfish Fri Feb 3 13:15:24 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!transit4.readnews.com!postnews.google.com!n6g2000vbg.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Wed, 16 Nov 2011 20:53:59 -0800 (PST) Organization: http://groups.google.com Lines: 222 Message-ID: <1c1a040c-4f56-46bf-b70c-40cf39f7bcde@n6g2000vbg.googlegroups.com> References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1321505649 29456 127.0.0.1 (17 Nov 2011 04:54:09 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Nov 2011 04:54:09 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n6g2000vbg.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5371 On Nov 14, 9:24=A0pm, self wrote: > > I have been designing printed circuit assemblies for over 20 years. > During that time HDL has almost completely taken over the logic design > business. That's not quite what has happened. Roughly 30 years ago programmable logic parts came into existence. Fundamentally, the input to these parts is a bit stream that encodes a functional description of the logic to be implemented. As the capabilities of these parts changed it became feasible to rapidly and less expensively (as compared to a board re-design) deploy logic function changes to an existing board. Also, over these 30 years the capacity of that described logic has increased many times over. HDLs have not "taken over the logic design business", they are simply a more productive tool for describing large amounts of logic, the output of which is a bitstream. Printed circuit boards on the other hand have only increased in density incrementally over that same time frame. Whether or not the density has reached the point where a text description is 'better' or not is an opinion that everyone can have, but not all parts of a board are simply hooking up pins on large parts. There are analog sections and some power sections that greatly benefit from a 2D graphical description (i.e. schematic) and are much worse off in a linear text file. > You all know the advantages of text for logic design but I > will repeat some of them here. > > - Abstraction > - Portability > - Standardization > - Readability > - Maintainability > - Efficiency > - Version control compatibility > - Code generation > > PHDL (PCB HDL) is an attempt to achieve the same advantages for > printed circuit connectivity definition, the part of the printed > circuit design process that is currently done with schematic > diagrams. Unfortunately, you have not presented any data or even mentioned that you have measured anything to indicate that PHDL (or any other HDL) description is a better and more efficient tool for printed circuit board design capture. As I asked in my first post 'What improvements over current art does this bring to the table?'...if PHDL is measurably better than schematics than you should be able to measure that difference. If it's not, and it's just another tool that one could use, OK...but don't assume that any benefits of using one type of tool then get inherited by another type of use. > PHDL does nothing for the layout part of the design process > because that is naturally a drafting operation and we are pretty > satisfied with the commercial tools available for layout. > OK...but then where does one look to find out where in the circuit resistor R123 is located, what is it connected to etc.? Layout defines reference designators...reference designators are needed to relate back to the generating source file (schematic or PHDL) in order to maintain the design. None of this matters for 'logic design' that results in a bitstream that gets loaded into a programmable logic part. While net list generation (i.e. schematic capture) is a completely separate process from layout the two processes are not totally independent. You still need something out of the layout tool that gets put back to the 'source' whether that source is a schematic or a PHDL text file or some other file. Since schematics can be hierarchical with the same circuit repeated more than once, you can't even say that the reference designator could be used to instantiate the part in PHDL since, for a repeated circuit, one would have a single PHDL file (or section of a file) that describes something to be instantiated...but it needs to be instantiated more than once. Copy/ paste/label each copy? If so, then live with the law that anything that gets copied by a human will eventually change from whatever it was first copied from. > Printed circuit design connectivity definition is a much simpler task > than logic design. =A0You are only instantiating chips and wiring them > up. While your statement is true, it would be challenging at best to look at the description of even a simple filter in text form to determine the function...so this form would likely not be benefiting the people who have to pick up and support a design after the original designer has moved on. > You don't need data types, signal assignments or boolean functions > for example. For that reason we developed a super simple HDL > specifically for the task of designing printed circuit boards. Also, > printed circuit board design is a very important engineering task, > perhaps as important as logic design, so it deserves its own language > optimized for that purpose. > It is deserving and today the language optimized for that purpose is a graphical schematics so again we get back to my question 'What improvements over current art does this bring to the table?'. You still need to be better than the incumbent to gather outside support. PHDL might very well be better than schematics, but if it is you should be able to measure some improvement somewhere, not simply state that it is better than something that is not used for design (i.e. VHDL as the board design source) and leave it at that. > PHDL is a design language. =A0Component ports are associated with their > physical pin numbers in a device declaration. Then you instantiate > parts and attach signals to them, nothing fancy. =A0The language has > many syntactical features that provide abstraction, reduce typing and > help minimize errors. The current version of the compiler already > provides a good bit of error checking. > Simply noting that everything in the above paragraph is equally true for schematics as well. > Our compiler can already output netlist formats for PADS and Eagle. It > is easy to create more output formats and we want to support Altium > and VHDL netlist outputs. The VHDL would be for anyone who might want > to simulate or graphically view the structure of their design in an > RTL viewer. > RTL viewer generated schematics are usually...well...something that you don't like to view. > To avoid most of the typing on big FPGA boards ...extra work that is created by choosing to go with linear text files... > I wrote a Xilinx2PHDL > converter that automatically generates most of the text for the > board. At least there is a solution to the problem that was self- created...well for certain suppliers I guess. Does every part supplier need a converter in order to be productive using PHDL? Samsung? Intel? On Semi? Lucent? Fairchild? > When you have text design entry it opens up all kinds of > possibilities for autogeneration. I'm working on the Actel2PHDL and > Altera2PHDL converters now. > Perhaps you should expound on what those possibilities might be as compared to schematics. Hierarchy, parameters, generation and reuse are already there with schematics. What did you have in mind? > To my mind the biggest advantage of PHDL over graphical schematics is > compatibility with version control tools. Because it is text, I can > look back at every change ever made to the design. > Any file can be version controlled...whether it is a proprietary data format or not. So the biggest advantage you see then is the ability to use 'diff' to see what has changed which you cannot do with a version controlled schematic. OK...but since a schematic simply documents intended connections between devices, the net list CAE file output (which is a text file as well) can be similarly 'diffed'. Since the PHDL file is not going to be the 'only' design artifact file there will need to be other files as well as part of the board design process. So how is the ability to run 'diff' on a PHDL file fundamentally any better than running 'diff' on the net list output from the CAE tools? Lastly, if what you state actually is the biggest advantage, then ask yourself who benefits and who pays the cost? Is the cost worth it to the one who has to pay it? These are all different ways of stating 'What improvements over current art does this bring to the table?' > We have already designed several printed circuit boards using PHDL. > Originally I thought it would be best for high pin count FPGA boards > but we have used it for analog and power boards and those read well > also. =A0It is amazing how a few comments can help with the board design > process. > Comments though do not create circuits...therefore one must always accept that they can be inaccurate and/or misleading > On the other hand, we understand that a lot of people just like > drawing pictures of board designs and are willing to use proprietary > tools to do it. We are just offering an alternative to those HDL types > who prefer a very direct and open design methodology. > People also like to see better ways of doing things and are willing to change to those better ways. But when there is no indication or it is not 'obvious' in what way something 'new' is better than the 'old way' one should question if 'new' is 'better' or 'worse' or just 'different'...ideally being able to back that up with some form of measurement to support. As a last point, consider that FPGA tools in some ways return to the graphical roots for improving designer productivity. FPGA suppliers provide various widgets (PLLs, memory controllers, image processing functions, etc.) that can be parameterized by the user with a GUI wizard for the intended usage. Those widgets in turn can be instantiated in a graphical tool as well to very quickly generate a complete design (Altera's SOPC Builder being an example). So even the area where HDLs are most prominently used by a designer, there is market pull for a graphical tool to improve productivity...rather counter to your possible thesis that the text only approach might be better. > Anyway, that is enough for today. > > =A0 Pete Thanks for providing the info, hopefully take what I say not so much as constructive input as it was intended rather than as a rant. Kevin From newsfish@newsfish Fri Feb 3 13:15:25 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p5g2000vbm.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Wed, 16 Nov 2011 21:05:46 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> <1c1a040c-4f56-46bf-b70c-40cf39f7bcde@n6g2000vbg.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1321506349 5320 127.0.0.1 (17 Nov 2011 05:05:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 17 Nov 2011 05:05:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p5g2000vbm.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5372 On Nov 16, 11:53=A0pm, KJ wrote: > > Thanks for providing the info, hopefully take what I say not so much > as constructive input as it was intended rather than as a rant. > Delete the 'not so much' from above... From newsfish@newsfish Fri Feb 3 13:15:25 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t38g2000prg.googlegroups.com!not-for-mail From: self Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Sun, 20 Nov 2011 06:27:19 -0800 (PST) Organization: http://groups.google.com Lines: 91 Message-ID: <9613c79e-f7f9-43f4-b73c-a7083e849ba7@t38g2000prg.googlegroups.com> References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> NNTP-Posting-Host: 68.35.127.28 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1321799242 25757 127.0.0.1 (20 Nov 2011 14:27:22 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Nov 2011 14:27:22 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t38g2000prg.googlegroups.com; posting-host=68.35.127.28; posting-account=buE9zAoAAADInp_5AizVMCbrLTmYl6wQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; OfficeLiveConnector.1.4; OfficeLivePatch.1.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5373 Andy I also started down the "VHDL for PCB" path. I figured out how to use VHDL attributes to add the extra info we need for PCB netlist creation. For example, here is how a component declaration might look using VHDL. -- This component is a 1:4 LVDS clock buffer. entity sy89832u is port( en : inout STD_LOGIC; -- enable pin. internally pulled high. vref : out std_logic; vt : in std_logic; gnd : in std_logic; vcc : in std_logic_vector(1 downto 0); in_p : in STD_LOGIC; in_n : in STD_LOGIC; q_p : out STD_LOGIC_VECTOR(3 downto 0); q_n : out STD_LOGIC_VECTOR(3 downto 0)); -- some part attibutes. attribute pcbl_partlevel of sy89832u : entity is true; attribute pcbl_package_type of sy89832u : entity is "MLF-16"; attribute pcbl_part_number of sy89832u : entity is "SY89832UMI"; attribute pcbl_part_cost of sy89832u : entity is 15.23; -- the pin numbers. attribute pcbl_pin_list of en : signal is "8"; attribute pcbl_pin_list of vref : signal is "10"; attribute pcbl_pin_list of vt : signal is "11"; attribute pcbl_pin_list of gnd : signal is "13"; attribute pcbl_pin_list of vcc : signal is "7,14"; attribute pcbl_pin_list of in_p : signal is "12"; attribute pcbl_pin_list of in_n : signal is "9"; attribute pcbl_pin_list of q_p : signal is "5,3,1,15"; attribute pcbl_pin_list of q_n : signal is "6,4,2,16"; end sy89832u; It is not too bad but I don't like how the pin numbers are located down below, disassociated from the port declaration. Also, talking to compiler designers, I learned that VHDL is notoriously difficult to parse. VHDL is difficult for the board designer and difficult for the compiler designer. That is why I dropped the idea of using VHDL for PCB design. Here is how a similar device declaration looks in PHDL // an clock buffer IC device sy898533 is attr refPrefix = "U"; attr refDes = ""; attr pkg_type = "SY898533LKZ"; attr mfgr = "MICREL"; attr partNumber = "SY898533LKZ"; attr cost = "4.45"; pin[1:3] vcc = {10,13,18}; pin clk_p = {4}; pin clk_n = {5}; pin pclk_p = {6}; pin pclk_n = {7}; pin clk_en = {2}; pin clk_sel = {3}; pin[1:2] nc = {8,9}; pin[0:3] q_p = {20,17,15,12}; pin[0:3] q_n = {19,16,14,11}; pin vee = {1}; end device; We optimized the syntax to be easy to type and to be easy to parse. I really like the way that the list of pin numbers is on the same line with the port declaration. I like your suggestion about creating record type busses and routing those between subsystems. Record types is on the To Do list for PHDL. I can imagine a record for a DDR3 interface that combines all the data, address, clocks and control lines into a single record. Signals from that record would be connected to the individual memory chips. I think it would be quite readable. It is possible to do record busses in some proprietary graphical schematic tools. Unfortunately, every tool does it differently. Even different versions of the same tool will differ in this sort of thing. Our goal is to create an open and free methodology that we could use for any project that we choose and for any layout back-end program. We don't want to be controlled by some CAE vendor. We insist that we control our intellectual property by creating and maintaining it in a portable format. We want to be free. Anyway, that's our goal. :-) Pedro From newsfish@newsfish Fri Feb 3 13:15:26 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!k5g2000pre.googlegroups.com!not-for-mail From: self Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Sun, 20 Nov 2011 09:07:20 -0800 (PST) Organization: http://groups.google.com Lines: 93 Message-ID: References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> <1c1a040c-4f56-46bf-b70c-40cf39f7bcde@n6g2000vbg.googlegroups.com> NNTP-Posting-Host: 68.35.127.28 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1321809174 30462 127.0.0.1 (20 Nov 2011 17:12:54 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Nov 2011 17:12:54 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k5g2000pre.googlegroups.com; posting-host=68.35.127.28; posting-account=buE9zAoAAADInp_5AizVMCbrLTmYl6wQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; OfficeLiveConnector.1.4; OfficeLivePatch.1.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5374 KJ The idea of textual PCB design entry is a small paradigm shift and a lot of people react emotionally so thanks for your comments. Everybody I know uses VHDL or Verilog for even very simple CPLD designs. Of course, for large FPGA's and ASIC design HDL is the preferred entry method for now. On board design, I also thought that the analog portions of board design were best done with schematics, till I tried PHDL. Now I find that the ability to mix lines of comments with lines of design text actually makes PHDL more expressive than proprietary schematic entry methods, even for analog circuits. Also, at least for the kinds of board I do, PCB design is getting simpler over time. What used to require a board full of ECL logic now easily runs inside a low cost FPGA. Switching regulators used to be quite a challenge to capture. These days, I always use an integrate controller that usually includes the power FET and often includes the required inductor as well. It only takes a few lines of PHDL (plus comments) to capture a switching regulator design. You are right, I don't have any hard data on productivity but I have been using schematic entry for over twenty years and now I have done several designs in PHDL. My subjective impression is that PHDL is faster, more accurate, more readable and less annoying than proprietary graphical schematic tools. I use the Vim text editor and we wrote a sytax highlighter control file for Vim that makes PHDL design entry really pleasant. When working with schematic entry tools I keep track of how much time I spend on non-productive tool fiddling and how much on actual design entry. I think it is 90% fiddling and 10% actual work. In PHDL, I feel the ratio is reversed, 10% fiddling and 90% design entry. With respect to efficiency, I find that pure text PHDL design entry actually requres less typing than the schematic editor that I normally use (Mentor DxDesigner). I find most of the text can be autogenerated (FPGA) or cut and pasted from the pdf data sheet. I find the reduction of typing (and fiddling) really reduces my error rate and lets me focus on the actual design. Again, this is just an objective observation. Let me know what you think after you have tried PHDL. Searching for components by refdes is something that is very unwieldy in most schematic editor tools. Of course, searching for text within a text file like PHDL source is very natural. The PHDL compiler controls the mapping between design pathname and refdes in an open CSV format file that can be searched to quickly locate any refdes within the design hierarchy. Furthermore, we are extending the funtionality of the refdes idea to contain some hierarchical information. This makes it really easy, in the layout tool, to quickly select all the components in one part of the design. As far as I know, this is a very simple but valuable improvement over how schematics usually handle refdes. With respect to version control, diff'ing the source design is much better than diff'ing the machine generated netlist output. I have actually tried almost all of the graphical logic generation tools to supposedly improve designer productivity, Xilinx DSP System Generator, Altera DSP Builder, Aldec BDE block diagram editor, National Instruments Labview FPGA,... For production designs I always use strait HDL entry for maintainability. How many proprietary tools do you want to pay maintenance on just to be able to edit your own design? PHDL is free and open. You could actually archive the PHDL compiler (jar file) along with your design for infinite maintainability. I am getting together with the compiler designers tomorrow. We are going to talk about new features for version 2 two of PHDL. The new features will definitely include 1) Hierarchical design - for modularity. Once we have this, PHDL won't be linear text but, instead, organized functionally. 2) VHDL output - for design analysis, simulation and graphical viewing. This is an easy way to get pictures out of your PHDL design. 3) Altium netlist output - Altium is coming on in popularity. People request Altium netlist format more than any other. 4) Record Type nets - We want to do this better and simpler than VHDL. Ie., we want to be able to combine inputs and outputs in a single record. 5) Full parser re-write - The guys want to do a little "refactoring" now that they have written a compiler and are a lot smarter. Once again, thanks for the comments and ideas. The very fact that you guys are participating on this use group means you are looking for new ideas. Maybe PHDL is not for you. Best wishes, Pedro From newsfish@newsfish Fri Feb 3 13:15:26 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!u37g2000prh.googlegroups.com!not-for-mail From: self Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Sun, 20 Nov 2011 09:15:46 -0800 (PST) Organization: http://groups.google.com Lines: 93 Message-ID: <96e4b092-3bd3-4e47-ada8-2f07d3462638@u37g2000prh.googlegroups.com> References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> <1c1a040c-4f56-46bf-b70c-40cf39f7bcde@n6g2000vbg.googlegroups.com> NNTP-Posting-Host: 68.35.127.28 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1321809461 1067 127.0.0.1 (20 Nov 2011 17:17:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 20 Nov 2011 17:17:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: u37g2000prh.googlegroups.com; posting-host=68.35.127.28; posting-account=buE9zAoAAADInp_5AizVMCbrLTmYl6wQ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; OfficeLiveConnector.1.4; OfficeLivePatch.1.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5375 KJ The idea of textual PCB design entry is a small paradigm shift and a lot of people react emotionally so thanks for your comments. Everybody I know uses VHDL or Verilog for even very simple CPLD designs. Of course, for large FPGA's and ASIC design HDL is the preferred entry method for now. On board design, I also thought that the analog portions of board design were best done with schematics, till I tried PHDL. Now I find that the ability to mix lines of comments with lines of design text actually makes PHDL more expressive than proprietary schematic entry methods, even for analog circuits. Also, at least for the kinds of board I do, PCB design is getting simpler over time. What used to require a board full of ECL logic now easily runs inside a low cost FPGA. Switching regulators used to be quite a challenge to capture. These days, I always use an integrate controller that usually includes the power FET and often includes the required inductor as well. It only takes a few lines of PHDL (plus comments) to capture a switching regulator design. You are right, I don't have any hard data on productivity but I have been using schematic entry for over twenty years and now I have done several designs in PHDL. My subjective impression is that PHDL is faster, more accurate, more readable and less annoying than proprietary graphical schematic tools. I use the Vim text editor and we wrote a sytax highlighter control file for Vim that makes PHDL design entry really pleasant. When working with schematic entry tools I keep track of how much time I spend on non-productive tool fiddling and how much on actual design entry. I think it is 90% fiddling and 10% actual work. In PHDL, I feel the ratio is reversed, 10% fiddling and 90% design entry. With respect to efficiency, I find that pure text PHDL design entry actually requres less typing than the schematic editor that I normally use (Mentor DxDesigner). I find most of the text can be autogenerated (FPGA) or cut and pasted from the pdf data sheet. I find the reduction of typing (and fiddling) really reduces my error rate and lets me focus on the actual design. Again, this is just an objective observation. Let me know what you think after you have tried PHDL. Searching for components by refdes is something that is very unwieldy in most schematic editor tools. Of course, searching for text within a text file like PHDL source is very natural. The PHDL compiler controls the mapping between design pathname and refdes in an open CSV format file that can be searched to quickly locate any refdes within the design hierarchy. Furthermore, we are extending the funtionality of the refdes idea to contain some hierarchical information. This makes it really easy, in the layout tool, to quickly select all the components in one part of the design. As far as I know, this is a very simple but valuable improvement over how schematics usually handle refdes. With respect to version control, diff'ing the source design is much better than diff'ing the machine generated netlist output. I have actually tried almost all of the graphical logic generation tools to supposedly improve designer productivity, Xilinx DSP System Generator, Altera DSP Builder, Aldec BDE block diagram editor, National Instruments Labview FPGA,... For production designs I always use strait HDL entry for maintainability. How many proprietary tools do you want to pay maintenance on just to be able to edit your own design? PHDL is free and open. You could actually archive the PHDL compiler (jar file) along with your design for infinite maintainability. I am getting together with the compiler designers tomorrow. We are going to talk about new features for version 2 of PHDL. The new features will probably include 1) Hierarchical design - for modularity. Once we have this, PHDL won't be linear text but, instead, organized functionally. 2) VHDL output - for design analysis, simulation and graphical viewing. This is an easy way to get pictures out of your PHDL design. 3) Altium netlist output - Altium is coming on in popularity. People request Altium netlist format more than any other. 4) Record Type nets - (maybe) We want to do this better and simpler than VHDL. Ie., we want to be able to combine inputs and outputs in a single record. 5) Full parser re-write - The guys want to do a little "refactoring" now that they have written a compiler and are a lot smarter. Once again, thanks for the comments and ideas. The very fact that you guys are participating on this usenet group means you are looking for new ideas. Maybe PHDL is not for you. Best wishes, Pedro From newsfish@newsfish Fri Feb 3 13:15:26 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p16g2000yqd.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: PHDL a new HDL for PCB design Date: Wed, 23 Nov 2011 08:56:55 -0800 (PST) Organization: http://groups.google.com Lines: 57 Message-ID: References: <144a4537-b0cf-4445-b579-e83ca39b1edf@i6g2000prm.googlegroups.com> <1c1a040c-4f56-46bf-b70c-40cf39f7bcde@n6g2000vbg.googlegroups.com> <96e4b092-3bd3-4e47-ada8-2f07d3462638@u37g2000prh.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1322067415 369 127.0.0.1 (23 Nov 2011 16:56:55 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 23 Nov 2011 16:56:55 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p16g2000yqd.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5376 On Nov 20, 11:15=A0am, self wrote: > > 1) Hierarchical design - for modularity. Once we have this, PHDL won't > be linear text but, instead, organized functionally. How will it handle reference designators when you instantiate the same hierarchical module more than once in a design? Are reference designators now required to be hierarchical paths? Most schematic entry tools do not require you to define a reference designator when you instantiate the component, they will do that automatically when the extract the netlist (and annotate a cross- reference for you). And they will allow board layout to resequence them per physical location once the components are placed on the board. Unlike the pdf schematic which is searcable, when I'm probing the board, there is no search feature for it. That's why I infinitely prefer reference designators sequenced per layout, not per schematic organization. Now that schematic drawings are ultimately released as a multi-page pdf with searchable text, the advantages of a textual netlist over a schematic are nil, while the disadvantages are considerable. Tools exist for graphically comparing two schematic versions to easily identify the changes, even when they are "cosmetic". Keep in mind that what you may consider "cosmetic" may be critical to the understanding imparted to the reader. Comments are cosmetic too, but very useful. Must you entirely re-define a component that is in a different package? Most systems separate logical parts that get instantiated from physical packages that are included in the netlist for a variety of reasons (e.g. multiple package choices per instantiated logical part, multiple logical parts per physical package, etc.). How does/ will PHDL handle these scenarios? Cadence had a spreadsheet-type system that was an alternative to schematic capture for board design. It might have worked pretty well for backplane design, but was a complete dud for general purpose board design. I can easily see that if you use integrated power supply controllers as the extent of your analog design, then you may not appreciate the contextual awareness that a schematic diagram provides over a netlist. Most non-trivial analog circuits are easier to understand when presented appropriately in a graphical context. Spice may be universal, but nobody uses it to convey a circuit to another human. Don't underestimate the value of a well-drawn schematic (not a computer generated one) for the customer, reviewers, maintainers, technicians, etc. Even in FPGA design, I often long for the ability to re-arrange a computer generated diagram of my code for presentation, documentation, etc. Productivity is a lot more than simply getting a design out of your head and into a board. And therein are the shortcomings of text-based board design. Andy From newsfish@newsfish Fri Feb 3 13:15:27 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!tudelft.nl!txtfeed1.tudelft.nl!feed.xsnews.nl!border-1.ams.xsnews.nl!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe12.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111124-1, 24/11/2011), Outbound message X-Antivirus-Status: Clean Lines: 49 Message-ID: <1PIzq.46688$T%1.11902@newsfe12.ams2> NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe12.ams2 1322211645 86.29.13.122 (Fri, 25 Nov 2011 09:00:45 UTC) NNTP-Posting-Date: Fri, 25 Nov 2011 09:00:45 UTC Organization: virginmedia.com Date: Fri, 25 Nov 2011 09:02:20 +0000 Xref: feeder.eternal-september.org comp.lang.vhdl:5377 On 16/11/2011 15:02, Christopher Felton wrote: > >> >> Given you like OOP you might also want to check out SystemC, if you are >> a Modelsim user then it is the cheapest way to get access to an OOP >> language, TLM2.0, AMS(?) and CR. The interface between VHDL and SystemC >> is pretty good. You might even be able to use OVM via the free OVM-ML >> package from Cadence although I haven't played with it myself. >> > > I think SystemC/C++, in this context, is a waste of time and effort. > Every verification effort that I have been involved with that uses > SystemC has had to devoted a fair number of resources to C++ development > and maintenance. In my opinion SystemC/C++ is antiquated and there are > better options available. Interesting, my experience is actually the opposite. I have seen a large number of companies that are quite successful with SystemC. You are right that most of these were large companies, that is those that use virtual prototyping but I have also seen single users quite successfully use SystemC for their development. Regarding better languages, yes, I guess we all know that C++ has many pitfalls and allows users to write in-comprehensible, un-portable mind boggling complex code. However, I still believe that SystemC (and the free reference simulator) is one of those hidden gems of the EDA world. If you can discipline your development and adhere to some good coding practises you will be amazed what you can achieve with SystemC. Hans www.ht-lab.com > > I believe Hans' main point is, if you want to use the advanced > verification features of SV you will need to shell out some money for an > SV simulator. And a cheaper alternative is SystemC. But my take, SystemC > is anti-productive, you are better off leveraging > SV/Python/Ruby/Matlab/Java any HLL that empowers the developer. SystemC > is for the large organizations that can devote the resources. In my > opinion you will spend more money developing C++ code than you will on > an SV enabled simulator. > > Regards, > Chris From newsfish@newsfish Fri Feb 3 13:15:27 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!postnews.google.com!cu3g2000vbb.googlegroups.com!not-for-mail From: LM Newsgroups: comp.lang.vhdl Subject: How do you use serial port or any other bus Date: Sat, 26 Nov 2011 15:35:18 -0800 (PST) Organization: http://groups.google.com Lines: 6 Message-ID: NNTP-Posting-Host: 91.153.127.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322350955 31505 127.0.0.1 (26 Nov 2011 23:42:35 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 26 Nov 2011 23:42:35 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: cu3g2000vbb.googlegroups.com; posting-host=91.153.127.251; posting-account=UU21RQoAAABFblXB3bPKIYLuA1-cz8zH User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.2) Gecko/20100101 Firefox/6.0.2,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5378 What I know there is no serial port or ethernet port in VHDL. But some FPGAs have them and much more. How are they used. I want to load packets of data from server/host to a FPGA and drive things. But what is easy with controllers is not easy (or is it) with FPGAs. From newsfish@newsfish Fri Feb 3 13:15:28 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 26 Nov 2011 21:22:06 -0600 Date: Sat, 26 Nov 2011 22:22:06 -0500 From: David Bishop User-Agent: Mozilla/5.0 (Windows NT 6.0; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 12 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-yYaFEiydYL3HQ1QBSc64qdr2xFb9RJy0IfnAy2a+zrJIMFkwatlQ9vCiVBN5KBsu7rDcKo1Xsr30aew!aGUMp+QAPuH7uxqIQUMiwSvz1KLXtNQvnUWOaVbvAO3YVV7BYOlGPFOTD+gKATj2QdZJZkA9K/Q= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1716 Xref: feeder.eternal-september.org comp.lang.vhdl:5379 On 11/26/2011 6:35 PM, LM wrote: > What I know there is no serial port or ethernet port in VHDL. But some > FPGAs have them and much more. How are they used. VHDL does not define interfaces, just a way to design them. > I want to load packets of data from server/host to a FPGA and drive > things. But what is easy with controllers is not easy (or is it) with > FPGAs. You will have to check out the IP library that comes with the FPGA design tools. It may have what you want. From newsfish@newsfish Fri Feb 3 13:15:28 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!diablo1.news.osn.de!news.osn.de!diablo2.news.osn.de!feeder2-2.proxad.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!w7g2000yqc.googlegroups.com!not-for-mail From: LM Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Date: Sat, 26 Nov 2011 22:31:37 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: <724dfb4c-55d9-4f60-ab4c-02428c45dc9c@w7g2000yqc.googlegroups.com> References: NNTP-Posting-Host: 91.153.127.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1322375940 28355 127.0.0.1 (27 Nov 2011 06:39:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 27 Nov 2011 06:39:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w7g2000yqc.googlegroups.com; posting-host=91.153.127.251; posting-account=UU21RQoAAABFblXB3bPKIYLuA1-cz8zH User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.2) Gecko/20100101 Firefox/6.0.2,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5380 > > I want to load packets of data from server/host to a FPGA and drive > > things. But what is easy with controllers is not easy (or is it) with > > FPGAs. > > You will have to check out the IP library that comes with the FPGA > design tools. =A0 It may have what you want. You are probably right. Its better to ask this in FPGA group. I dont think all FPGA users design their ethernet controllers or other such devices, but still they can be used. From newsfish@newsfish Fri Feb 3 13:15:28 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-in-01.newsfeed.easynews.com!easynews!core-easynews-01!easynews.com!en-nntp-16.dc1.easynews.com.POSTED!not-for-mail From: Rich Webb Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Organization: Line Eater Memorial Fund Message-ID: References: X-Newsreader: Forte Agent 6.00/32.1186 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit User-Agent: Hamster-Pg/1.25.2.0 X-Antivirus: avast! (VPS 111105-3, 11/05/2011), Outbound message X-Antivirus-Status: Clean Lines: 19 X-Complaints-To: abuse@easynews.com X-Complaints-Info: Please be sure to forward a copy of ALL headers otherwise we will be unable to process your complaint properly. Date: Sun, 27 Nov 2011 07:57:00 -0500 Xref: feeder.eternal-september.org comp.lang.vhdl:5381 On Sat, 26 Nov 2011 15:35:18 -0800 (PST), LM wrote: >What I know there is no serial port or ethernet port in VHDL. But some >FPGAs have them and much more. How are they used. > >I want to load packets of data from server/host to a FPGA and drive >things. But what is easy with controllers is not easy (or is it) with >FPGAs. A standard async serial port is just a shift register inside of a state machine. The outer state machine reacts to the start-bit detection and shifts from [idle] to [active]. Detect the bit states with a sample clock near the expected middle of each bit (or use a higher speed clock and do a majority vote, for noise mitigation). For completeness, handle parity checking, framing errors, and break states. At the end of the [active] bit count and stop-bit detection, return to [idle]. -- Rich Webb Norfolk, VA From newsfish@newsfish Fri Feb 3 13:15:29 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Christopher Felton Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Sun, 27 Nov 2011 10:53:04 -0600 Organization: A noiseless patient Spider Lines: 72 Message-ID: References: <1PIzq.46688$T%1.11902@newsfe12.ams2> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 27 Nov 2011 16:53:06 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="/SL0d2puQr5HwSIlohl2EQ"; logging-data="2792"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX191a5We/VhPA/c1nlCKMxrd" User-Agent: Mozilla/5.0 (Macintosh; U; PPC Mac OS X 10.5; en-US; rv:1.9.2.24) Gecko/20111103 Thunderbird/3.1.16 In-Reply-To: <1PIzq.46688$T%1.11902@newsfe12.ams2> Cancel-Lock: sha1:YsLKMJgP8F7ABxAK6+8fWschfWY= Xref: feeder.eternal-september.org comp.lang.vhdl:5382 On 11/25/11 3:02 AM, HT-Lab wrote: > On 16/11/2011 15:02, Christopher Felton wrote: >> >>> >>> Given you like OOP you might also want to check out SystemC, if you are >>> a Modelsim user then it is the cheapest way to get access to an OOP >>> language, TLM2.0, AMS(?) and CR. The interface between VHDL and SystemC >>> is pretty good. You might even be able to use OVM via the free OVM-ML >>> package from Cadence although I haven't played with it myself. >>> >> >> I think SystemC/C++, in this context, is a waste of time and effort. >> Every verification effort that I have been involved with that uses >> SystemC has had to devoted a fair number of resources to C++ development >> and maintenance. In my opinion SystemC/C++ is antiquated and there are >> better options available. > > > Interesting, my experience is actually the opposite. I have seen a large > number of companies that are quite successful with SystemC. You are > right that most of these were large companies, that is those that use > virtual prototyping but I have also seen single users quite successfully > use SystemC for their development. It depends on how you measure success. I was trying to convey, IMO, the *cost* to use SystemC/C++ (cost in time and resources). The projects I have experience with that used SystemC, most would consider their efforts successful. But the companies could assign half a dozen or more programmers to the problem. I have not seen efforts were one or two developers were able to leverage SystemC. If someone has years of experience pumping out C++ code, they might do very well. I do believe it is possible just not plausible for a single developer or small team. > > Regarding better languages, yes, I guess we all know that C++ has many > pitfalls and allows users to write in-comprehensible, un-portable mind > boggling complex code. > > However, I still believe that SystemC (and the free reference simulator) > is one of those hidden gems of the EDA world. If you can discipline your > development and adhere to some good coding practises you will be amazed > what you can achieve with SystemC. I believe any technology, regardless how old or new, can be successfully utilized by someone who completely understands what the technology provides and can make up for the short-comings with time and/or resources. In this case I believe the OP wants to highly leverage a technology for verification, I don't think SystemC is the best choice. Chris > > Hans > www.ht-lab.com > > >> >> I believe Hans' main point is, if you want to use the advanced >> verification features of SV you will need to shell out some money for an >> SV simulator. And a cheaper alternative is SystemC. But my take, SystemC >> is anti-productive, you are better off leveraging >> SV/Python/Ruby/Matlab/Java any HLL that empowers the developer. SystemC >> is for the large organizations that can devote the resources. In my >> opinion you will spend more money developing C++ code than you will on >> an SV enabled simulator. >> >> Regards, >> Chris > From newsfish@newsfish Fri Feb 3 13:15:29 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w1g2000vba.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Date: Sun, 27 Nov 2011 12:48:05 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: References: NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1322426885 906 127.0.0.1 (27 Nov 2011 20:48:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 27 Nov 2011 20:48:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w1g2000vba.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5383 On Nov 26, 6:35=A0pm, LM wrote: > What I know there is no serial port or ethernet port in VHDL. But some > FPGAs have them and much more. How are they used. > > I want to load packets of data from server/host to a FPGA and drive > things. But what is easy with controllers is not easy (or is it) with > FPGAs. Whether or not something is 'easy' depends on the particular skills of the individual that asks the question as well as the capabilities of the devices that are being considered for implementation. There is a large gap in complexity between the two interfaces that you mentioned (serial or ethernet). Most (or all) of either interface can be implemented in an FPGA, sometimes it makes sense to do so, other times it does not. Since you haven't stated your requirements, you need to work that out yourself first. Poke around at the FPGA supplier web sites for IP blocks that look like they might fit your needs or may influence what you think you need. Many things will enter into the decision of whether or not you should use an FPGA or something else (budgets, design complexity, resource usage, etc.) Simply stating that you want to 'load packets of data from server/host to a FPGA and drive things' isn't much of a functional requirement definition for anyone to help you out much. Whether or not something is 'easy with controllers' but maybe 'not easy' with an FPGA simply suggests that you're more familiar with controllers but that by itself isn't much of a constraint to try to work within (i.e. maybe you need it to be very easy from a design perspective because you only have two weeks to complete the hardware design). I would suggest clarifying what you think you need from a function and performance perspective and then work on what your constraints are and then post that description after which you'll probably get some good feedback from this group as well as comp.arch.fpga and probably other groups as well. Right now there isn't much to go on so the feedback will probably not be very useful other than to stimulate you to do more research. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:30 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p16g2000yqd.googlegroups.com!not-for-mail From: sdaau Newsgroups: comp.lang.vhdl Subject: A python grepper script to split / select / filter VCD signals Followup-To: comp.lang.vhdl Date: Sun, 27 Nov 2011 14:09:33 -0800 (PST) Organization: http://groups.google.com Lines: 50 Message-ID: <206288c2-4052-4621-8e8c-69ccc9c817e4@p16g2000yqd.googlegroups.com> NNTP-Posting-Host: 87.60.144.211 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322432721 28288 127.0.0.1 (27 Nov 2011 22:25:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 27 Nov 2011 22:25:21 +0000 (UTC) Cc: ghdl-discuss@gna.org, geda-user@delorie.com Complaints-To: groups-abuse@google.com Injection-Info: p16g2000yqd.googlegroups.com; posting-host=87.60.144.211; posting-account=TTEhNQoAAABt3FC2bHuMAVnWW8CNEKrZ User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux i686; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5384 Hi everyone, Apologies for cross-posting - just wanted to post about this, since I had trouble finding something similar elsewhere. The GHDL webpage currently says: http://ghdl.free.fr/ghdl/Simulation-options.html > Currently, there is no way to select signals to be dumped: > all signals are dumped, which can generate big files. ... and as I didn't have much luck finding existing VCD signal "splitters" (that would isolate a signal from a bundle), here's my attempt at a python script that will act as a "grepper" for vcd signals: http://sdaaubckp.svn.sourceforge.net/viewvc/sdaaubckp/single-scripts/vcd-sig-grep.py?view=markup As always, the usual YMMV applies :) For myself, the script was tested under python 2.7 (which seems slightly faster) and 3.2 on Ubuntu 11.04 Linux, and should work with piping to stdin - I have pretty much tested it only with GHDL output, as in: ghdl -r test_workbench --stop-time=20000us --vcd=/dev/stdout | python2.7 vcd-sig-grep.py --sigs="signal1,signal2" > tmpout.vcd ... and for test workbench, I've just used the file/approach here: SourceForge.net: ngspice: VHDL sim'd .vcd data - as analog sim source - http://sourceforge.net/projects/ngspice/forums/forum/133842/topic/4839104 Note there is no special handling of '$dumpvars' and such (however, GHDL seems not to output them anyways)... I've tested the .vcd output with gtkwave only, seems to be read in fine. Well, if there's a similar tool that I obviously missed (apart from gtkwave used with a tcl script, which is used in the above ngspice- users entry), I sure would like to know about it. Otherwise, I hope the community may find this useful... Cheers! From newsfish@newsfish Fri Feb 3 13:15:30 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w1g2000vba.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Function result not locally static in case expression Date: Mon, 28 Nov 2011 01:36:18 -0800 (PST) Organization: http://groups.google.com Lines: 56 Message-ID: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322473097 22719 127.0.0.1 (28 Nov 2011 09:38:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 28 Nov 2011 09:38:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w1g2000vba.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.8 (KHTML, like Gecko) Chrome/17.0.928.0 Safari/535.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5385 Hello, I wrote the following helper function to decode a chip select for addressing a particular register in custom processor peripherals. function CE_decode(CE_bit,CE_width : integer) return std_logic_vector is variable v_tmp : std_logic_vector(0 to CE_width-1) := (others => '0'); begin v_tmp(CE_bit) := '1'; return v_tmp; end function CE_decode; The problem is that Xilinx XST returns a warning: WARNING:HDLParsers:817 Choice CE_decode is not a locally static expression. I confirmed that the warning is actually redundant but I would still like to get rid of it. I am using the function in a context like this: C_NUM_REG : integer := 4; p_slv_reg_write : process(Bus2IP_Clk) is begin if rising_edge(Bus2IP_Clk) then case slv_reg_write_sel is when CE_decode(0, C_NUM_REG) => slv_reg0 <= Bus2IP_Data; when CE_decode(1, C_NUM_REG) => slv_reg1 <= Bus2IP_Data; when CE_decode(2, C_NUM_REG) => slv_reg2 <= Bus2IP_Data; when CE_decode(3, C_NUM_REG) => slv_reg3 <= Bus2IP_Data; when others => null; end case; end if; end process p_slv_reg_write; Instead of using the CE_decode function I can of course just write a static expression, but this gets hard to maintain and needs modification each time the number of registers in the peripheral changes. And it is hard to spot a mistake if there are 32 registers which CE is actually being decoded, e.g. "00000000000000000010000000000000". Can somebody please suggest how to work around the warning or suggest a better way in place of CE_decode function? Thank you! From newsfish@newsfish Fri Feb 3 13:15:30 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Date: Mon, 28 Nov 2011 12:58:08 +0200 Organization: A noiseless patient Spider Lines: 6 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Nov 2011 10:58:09 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="9175"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX193+1VoIIoO/akP8bNh4OiEcLdiwPuKXAg=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 In-Reply-To: Cancel-Lock: sha1:xARTApeXq5pmjR5kvaCkg8vzZZA= Xref: feeder.eternal-september.org comp.lang.vhdl:5386 > Whether or not something is 'easy with controllers' but maybe 'not easy' with an FPGA simply suggests that you're more familiar with controllers No. It means that controllers have a built-in rs232 controller, which can be easily commanded to send a byte. This is one simple line of C code. From newsfish@newsfish Fri Feb 3 13:15:31 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Bart Fox Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Mon, 28 Nov 2011 12:29:08 +0100 Organization: A noiseless patient Spider Lines: 14 Message-ID: References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Nov 2011 11:29:08 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="6N+JcEzFProc3RKf6dVbew"; logging-data="19538"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18hIznxvClPpwQhxV/PaBme" User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.6; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 In-Reply-To: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Cancel-Lock: sha1:F2rxtPUYjoPbs4r72RELCbqVRiE= Xref: feeder.eternal-september.org comp.lang.vhdl:5387 > Can somebody please suggest how to work around the warning or suggest > a better way > in place of CE_decode function? Try to define and use some constants: constant ce_slv_reg0_c : std_logic_vector := CE_decode(0, C_NUM_REG); constant ce_slv_reg1_c : std_logic_vector := CE_decode(1, C_NUM_REG); constant ce_slv_reg2_c : std_logic_vector := CE_decode(2, C_NUM_REG); constant ce_slv_reg3_c : std_logic_vector := CE_decode(3, C_NUM_REG); They should be static enough for VHDL. regards, Bart From newsfish@newsfish Fri Feb 3 13:15:31 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Enrik Berkhan Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Mon, 28 Nov 2011 11:24:13 +0000 (UTC) Organization: void Lines: 57 Message-ID: References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1322479453 16518 192.168.128.1 (28 Nov 2011 11:24:13 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Mon, 28 Nov 2011 11:24:13 +0000 (UTC) User-Agent: tin/1.9.6-20101126 ("Burnside") (UNIX) (Linux/2.6.38-8-generic (x86_64)) Xref: feeder.eternal-september.org comp.lang.vhdl:5388 a s wrote: > [...] > The problem is that Xilinx XST returns a warning: > WARNING:HDLParsers:817 Choice CE_decode is not a locally static > expression. > [...] > C_NUM_REG : integer := 4; > > p_slv_reg_write : process(Bus2IP_Clk) is > begin > if rising_edge(Bus2IP_Clk) then > case slv_reg_write_sel is > when CE_decode(0, C_NUM_REG) => > slv_reg0 <= Bus2IP_Data; > when CE_decode(1, C_NUM_REG) => > slv_reg1 <= Bus2IP_Data; > when CE_decode(2, C_NUM_REG) => > slv_reg2 <= Bus2IP_Data; > when CE_decode(3, C_NUM_REG) => > slv_reg3 <= Bus2IP_Data; > when others => null; > end case; > end if; > end process p_slv_reg_write; > [...] > Can somebody please suggest how to work around the warning or suggest > a better way > in place of CE_decode function? You could use if-constructs like this: p_slv_reg_write : process(Bus2IP_Clk) is begin if rising_edge(Bus2IP_Clk) then if slv_reg_write_sel = CE_decode(0, C_NUM_REG) then slv_reg0 <= Bus2IP_Data; end if; if slv_reg_write_sel = CE_decode(1, C_NUM_REG) then slv_reg1 <= Bus2IP_Data; end if; if slv_reg_write_sel = CE_decode(2, C_NUM_REG) then slv_reg2 <= Bus2IP_Data; end if; if slv_reg_write_sel = CE_decode(3, C_NUM_REG) then slv_reg3 <= Bus2IP_Data; end if; end if; end process p_slv_reg_write; Note that 'elsif' has intentionally not been used to avoid priority decoders and because CE_decode() already guarantees non-overlapping conditions. If you put slv_regX into an array, you can even use a for loop instead of explicitly writing all those if's. Enrik From newsfish@newsfish Fri Feb 3 13:15:32 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: External name elaboration order Date: Mon, 28 Nov 2011 13:32:23 +0200 Organization: A noiseless patient Spider Lines: 62 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Nov 2011 11:32:24 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="20709"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+yx0F6psVp85EYeFY1a9JlpRIUWOTh+KU=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 Cancel-Lock: sha1:6gHaP5vSkZ4Jgga5DCJJxt5jWxg= Xref: feeder.eternal-september.org comp.lang.vhdl:5389 In "Designer's guide to VHDL", Chapter 18, I read: - BEGIN QUOTE - "We can use an external constant name (or an alias of such a name) in an expression, provided the constant has been elaborated and given a value by the time the expression is evaluated. In some cases, expressions are evaluated during elaboration of a design." "We can ensure this is the case by writing the part of the design that includes the constant declaration prior to the part of the design that contains the external constant name. VHDLs elaboration rules specify that the design is elaborated in depth-first top-to-bottom order." "We now assemble the design and test bench in a top-level entity and architecture: architecture level of top is begin assert false report "Width = " & to_string(<>); duv : entity work.design(rtl); "The external constant name in the concurrent assertion statement, on the other hand, is not evaluated until the model is executed, by which time the model is completely elaborated. Thus, the external constant name is allowed to precede the instance of the design under test in which the constant is declared. - END QUOTE - It says that to be sure that referenced constant is evaluated prior to external name reference is evaluated, "declare the constant prior to the part of the design that contains the external constant name". But, in example we see the opposite: constant is declared in the instance below the assertion elaboration! Then, it reassures us that this is ok and develops this idea by denying it! "VHDL has a related rule regarding elaboration of a signal referenced by an external signal name. If such a name (or an alias of such a name) is used in a port map, the signal declaration must have been previously elaborated. The reason is that the hierarchy of signal nets and drivers is built during elaboration. If a signal used in a port map is not yet elaborated, the elaborator would have to revisit elaboration of that part of the design hierarchy once the signal declaration was encountered. In general, allowing such use of external signal names would make elaboration of signal nets indefinitely complicated. The rule preventing such use allows elaboration to proceed in a well-defined order, and is not onerous in practice." That is, they say that situation is the same and object, referenced in external name, must be elaborated before external name. alias DONE_SIG is <>; -- Legal begin DUT: entity WORK.MY_DESIGN port map (s1, S2, S3); We do not want to re-elaborate the alias, once the signal declaration was encountered during instance elaboration. Right? After all, I could not understand if your VHDL example is correct or not. From newsfish@newsfish Fri Feb 3 13:15:32 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Mon, 28 Nov 2011 14:01:54 +0200 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 28 Nov 2011 12:01:54 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="30843"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19ZWZE+uYu3oOeShel/w1nHKwTjzarqHyI=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:7.0.1) Gecko/20110929 Thunderbird/7.0.1 In-Reply-To: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Cancel-Lock: sha1:1Dp1AOLbKe/KJc0yoRIHMtanvNM= Xref: feeder.eternal-september.org comp.lang.vhdl:5390 On 28.11.2011 11:36, a s wrote: > Hello, > > I wrote the following helper function to decode a chip select for > addressing a particular register in custom processor peripherals. > > function CE_decode(CE_bit,CE_width : integer) return > std_logic_vector is > variable v_tmp : std_logic_vector(0 to CE_width-1) := (others => > '0'); > v_tmp(CE_bit) := '1'; Normally, breaking vec := (CE_BIT => '1', others => '0') into your code solves the problem. I would first ensure that args are constants: constant CE_bit,CE_width : integer From newsfish@newsfish Fri Feb 3 13:15:33 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Mon, 28 Nov 2011 13:08:25 +0000 (UTC) Organization: A noiseless patient Spider Lines: 56 Message-ID: References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 28 Nov 2011 13:08:25 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="27764"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+TqX2dDP1RWL802G+LDjrkW838Nqde5mA=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:XLut9/5nIEaflaoCg13q5Wbwmzw= Xref: feeder.eternal-september.org comp.lang.vhdl:5391 On Mon, 28 Nov 2011 01:36:18 -0800, a s wrote: > Hello, > > I wrote the following helper function to decode a chip select for > addressing a particular register in custom processor peripherals. > > function CE_decode(CE_bit,CE_width : integer) return ... ... and using it as > > p_slv_reg_write : process(Bus2IP_Clk) is begin > if rising_edge(Bus2IP_Clk) then > case slv_reg_write_sel is > when CE_decode(0, C_NUM_REG) => > slv_reg0 <= Bus2IP_Data; > when CE_decode(1, C_NUM_REG) => > slv_reg1 <= Bus2IP_Data; > when CE_decode(2, C_NUM_REG) => > slv_reg2 <= Bus2IP_Data; > when CE_decode(3, C_NUM_REG) => > slv_reg3 <= Bus2IP_Data; > when others => null; > end case; > end if; > end process p_slv_reg_write; > > Instead of using the CE_decode function I can of course just write a > static expression, ... > Can somebody please suggest how to work around the warning or suggest a > better way > in place of CE_decode function? > Bart Fox has one good solution : use the CE_Decode function to create your static expressions (constants) ... but another way is to realise the purpose of the case statement is to evaluate once, and simply compare against a static list (effectively a list of constants. So another way is to write a new function subtype reg_addr is natural range 0 to C_NUM_REG; -- Use a subtype here so synthesis doesn't use 32-bit arithmetic! function select_reg(selector : ) return reg_addr is -- a simple exercise... case select_reg(slv_reg_write_sel) is when 0 => slv_reg0 <= Bus2IP_Data; when 1 => slv_reg1 <= Bus2IP_Data; when 2 => slv_reg2 <= Bus2IP_Data; when 3 => slv_reg3 <= Bus2IP_Data; when others => null; end case; -- Brian From newsfish@newsfish Fri Feb 3 13:15:33 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g20g2000prb.googlegroups.com!not-for-mail From: sebs Newsgroups: comp.lang.vhdl Subject: incremental generic association Date: Mon, 28 Nov 2011 12:53:54 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: NNTP-Posting-Host: 210.7.32.45 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322513640 20509 127.0.0.1 (28 Nov 2011 20:54:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 28 Nov 2011 20:54:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g20g2000prb.googlegroups.com; posting-host=210.7.32.45; posting-account=_T50ywoAAACoNQE5dgLgi5huXdbqV6n6 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.2 (KHTML, like Gecko) Chrome/15.0.874.120 Safari/535.2,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5392 Hi, In my toplevel testbench I'd like to only change one generic of a component somewhere in my design. This component has many generics that have no default binding. They are all set by the hierarchy above. so in my testbench I want to do something like the following in order to change only the generic g_Segment, but leave the rest alone. configuration blub of my_tb is for tb for C_data_src: data_src for behav for C_segment : segment use entity work.segment generic map (g_Segments => 10); end for; end for; end for; end configuration blub; Unfortunately Modelsim complains about all generics that have no default value ... "Formal generic ... has OPEN or no actual association with it." Although all generics are defined in the architecture where C_segment is instantiated. Why would i need to define all generics in the generic map of the configuration, when I want to only override one of them? From newsfish@newsfish Fri Feb 3 13:15:33 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!l24g2000yqm.googlegroups.com!not-for-mail From: a s Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Tue, 29 Nov 2011 01:05:28 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <6a688521-1594-4724-8911-b8f034a3da4d@l24g2000yqm.googlegroups.com> References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> NNTP-Posting-Host: 137.138.46.147 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322557529 16683 127.0.0.1 (29 Nov 2011 09:05:29 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Nov 2011 09:05:29 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l24g2000yqm.googlegroups.com; posting-host=137.138.46.147; posting-account=-2dErQoAAACnd6wzi8aKUkKuyzdyU5ST User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ASELCHRU X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1) AppleWebKit/535.8 (KHTML, like Gecko) Chrome/17.0.928.0 Safari/535.8,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5393 Thank you all! These suggestions above are all very interesting. I decided to go with Brian's suggestions and implemented the following function. I checked it in simulation and synthesis and the function passed without warnings. Anyway, I would appreciate to receive a comment if someone spots a weak point. function select_reg(selector : std_logic_vector; C_NUM_REG : integer) return natural is subtype reg_addr_t is natural range 0 to C_NUM_REG-1; variable reg_addr : reg_addr_t := 0; begin for i in 0 to C_NUM_REG-1 loop if selector(i) = '1' then reg_addr := i; exit; end if; end loop; return reg_addr; end function select_reg; Thanks again! From newsfish@newsfish Fri Feb 3 13:15:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!cc2g2000vbb.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: incremental generic association Date: Tue, 29 Nov 2011 05:24:03 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <718cbefd-c65c-4936-a36e-1f5cbd9baf97@cc2g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322573134 14422 127.0.0.1 (29 Nov 2011 13:25:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Nov 2011 13:25:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: cc2g2000vbb.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5394 >Although all generics are defined in the architecture 1. Generics are defined in the entity, not in the architecture 2. Do you provide default values for the generics ? They are necessary if you do not want to map them in "generic map". Cheers, hssig From newsfish@newsfish Fri Feb 3 13:15:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!m10g2000vbc.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: incremental generic association Date: Tue, 29 Nov 2011 09:31:12 -0800 (PST) Organization: http://groups.google.com Lines: 20 Message-ID: <23dfbb8a-3b7a-4bb8-8707-b55522bf3d15@m10g2000vbc.googlegroups.com> References: <718cbefd-c65c-4936-a36e-1f5cbd9baf97@cc2g2000vbb.googlegroups.com> NNTP-Posting-Host: 70.34.173.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1322592734 22138 127.0.0.1 (29 Nov 2011 18:52:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Nov 2011 18:52:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m10g2000vbc.googlegroups.com; posting-host=70.34.173.3; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.2; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5395 On Nov 29, 8:24=A0am, hssig wrote: > >Although all generics are defined in the architecture > > 1. Generics are defined in the entity, not in the architecture > 2. Do you provide default values for the generics ? They are > necessary if you do not want to map them in "generic map". > > Cheers, > hssig What sebs meant to say is that the *values for* all generics are defined in the architecture where C_segment is instantiated. There is more than one generic being mapped, sebs wants to override only one of them in the testbench (or more generally speaking, he wants to override a subset of all of the generics and can't rely on entity defined defaults, if they happen to have defaults). I don't think this can be done. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:34 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!c18g2000yqj.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Tue, 29 Nov 2011 10:55:22 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <719b99d7-28ca-4cfe-ab1d-35b2d625a5d1@c18g2000yqj.googlegroups.com> References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> <6a688521-1594-4724-8911-b8f034a3da4d@l24g2000yqm.googlegroups.com> NNTP-Posting-Host: 192.91.147.35 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322593046 25138 127.0.0.1 (29 Nov 2011 18:57:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 29 Nov 2011 18:57:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c18g2000yqj.googlegroups.com; posting-host=192.91.147.35; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5396 Why are you passing c_num_reg to the function? The 'range attribute from the selector argument will give you what you want: function select_reg(selector : std_logic_vector) return natural is variable reg_addr : natural range selector'range; begin for i in selector'range loop if selector(i) = '1' then reg_addr := i; exit; end if; end loop; return reg_addr; end function select_reg; Note that the function returns the same value whether no bits or set or selector'low is set. May not be a problem in your application. If you need to encode only a slice of a vector, then call the function with the slice instead of the whole vector. Andy From newsfish@newsfish Fri Feb 3 13:15:35 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.eclipse.net.uk!news.eclipse.net.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 29 Nov 2011 13:16:43 -0600 From: Dave Fraser Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Date: Tue, 29 Nov 2011 19:16:40 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3.50 (darwin) Cancel-Lock: sha1:WFRz8ZYxmS0db5m6MoM5qek5Yw0= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 22 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 91.85.36.145 X-Trace: sv3-9oJ8SCvXsAXbWroy38QXFbbjgakgKj+QPaNcXCIwWKv51sVOj1Ktalw33Hebg6Z6mJWPlcSrIQG7Wnt!8Vkjs/9+0AWKWnpA1LmpcfLLPwgmKeiHN9JHepkAeKizKyqVmHqXqU6+kJqHmwscuE/AzogPhxjC!+p0HBk6eei6oaBL1kUVUvWHMQuQfSg85cLdUWl+GTkvwP3FaqyIXfXnN X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 1698 Xref: feeder.eternal-september.org comp.lang.vhdl:5397 An alternative would be to define the registers as an array of vectors and index the array directly:- architecture ... of ... is type register_file is array (range 0 to C_NUM_REG) of std_logic_vector(...); signal slv_reg : register_file ; begin p_slv_reg_write : process(Bus2IP_Clk) is begin if rising_edge(Bus2IP_Clk) then slv_reg(slv_reg_write_sel) <= Bus2IP_Data; end if; end process p_slv_reg_write; end architecture .... Then just use slv_reg(0) in place of slv_reg0 etc. From newsfish@newsfish Fri Feb 3 13:15:35 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!nntp.brightview.co.uk!news.brightview.co.uk.POSTED!not-for-mail NNTP-Posting-Date: Tue, 29 Nov 2011 19:07:37 -0600 Date: Wed, 30 Nov 2011 01:07:37 +0000 From: Alan Fitch Organization: Home User-Agent: Mozilla/5.0 (X11; Linux i686; rv:8.0) Gecko/20111115 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: External name elaboration order References: In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Message-ID: Lines: 105 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-gBpnOOLiJ8IzTWVQ0NvJa10cE7CJ1C2hCGToZPhg+mYlo71t+Wo2C1+H4u7+wGi43ssQHw+WHclQC48!wEbQj7/SQ9rQ4eEBvTRwmTqhJixuHcOBEmpJ1TPWVZQprqyRoAzHbOzb5CPaiJo13aqWGLA/jp6h!QaTNf5p1f7OUWdIbh2Ewb6EI4A== X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 5044 Xref: feeder.eternal-september.org comp.lang.vhdl:5398 On 28/11/11 11:32, valtih1978 wrote: > In "Designer's guide to VHDL", Chapter 18, I read: > > - BEGIN QUOTE - > "We can use an external constant name (or an alias of such a name) in an > expression, provided the constant has been elaborated and given a value > by the time the expression is evaluated. In some cases, expressions are > evaluated during elaboration of a design." > > "We can ensure this is the case by writing the part of the design that > includes the constant declaration prior to the part of the design that > contains the external constant name. VHDLs elaboration rules specify > that the design is elaborated in depth-first top-to-bottom order." > Hi, I understand that to say in the first part of the quote above that if you evaluate an expression which refers to an constant external name *during elaboration* then you can ensure the constant has been elaborated before the evaluation of the expression, by declaring the constant first. > "We now assemble the design and test bench in a top-level entity and > architecture: > > architecture level of top is > begin > assert false report "Width = " & to_string(< : natural>>); > duv : entity work.design(rtl); > > "The external constant name in the concurrent assertion statement, on > the other hand, is not evaluated until the model is executed, by which > time the model is completely elaborated. Thus, the external constant > name is allowed to precede the instance of the design under test in > which the constant is declared. > That is if you evaluate an expression using a constant external name *during simulation* then there is no such restriction, since elaboration is complete by the time simulation starts. > - END QUOTE - > > It says that to be sure that referenced constant is evaluated prior to > external name reference is evaluated, "declare the constant prior to the > part of the design that contains the external constant name". Yes, if you want to evaluate the expression during elaboration. But, in > example we see the opposite: constant is declared in the instance below > the assertion elaboration! > No, the example shown shows evaluation of the expression *during simulation*. > Then, it reassures us that this is ok and develops this idea by denying it! > > "VHDL has a related rule regarding elaboration of a signal referenced by > an external signal name. If such a name (or an alias of such a name) is > used in a port map, the signal declaration must have been previously > elaborated. The reason is that the hierarchy of signal nets and drivers > is built during elaboration. If a signal used in a port map is not yet > elaborated, the elaborator would have to revisit elaboration of that > part of the design hierarchy once the signal declaration was > encountered. In general, allowing such use of external signal names > would make elaboration of signal nets indefinitely complicated. The rule > preventing such use allows elaboration to proceed in a well-defined > order, and is not onerous in practice." > > That is, they say that situation is the same and object, referenced in > external name, must be elaborated before external name. > The paragraph you quote refers specifically to use of a signal referenced by an external signal name *in a port map*. > > alias DONE_SIG is <>; -- Legal > begin > DUT: entity WORK.MY_DESIGN port map (s1, S2, S3); > > We do not want to re-elaborate the alias, once the signal declaration > was encountered during instance elaboration. Right? > The alias you show doesn't refer to a signal in the port map, so I don't think this example relates to the paragraph you quote. regards Alan > After all, I could not understand if your VHDL example is correct or not. -- Alan Fitch From newsfish@newsfish Fri Feb 3 13:15:36 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder4.news.weretis.net!npeer.de.kpn-eurorings.net!npeer-ng0.de.kpn-eurorings.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Function result not locally static in case expression Date: Tue, 29 Nov 2011 23:26:07 -0800 Lines: 25 Message-ID: <9jm44gFecuU1@mid.individual.net> References: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net 5L3f4rekKLfoZX2PcUtB0gdLkyl8jaaoXPKryhhb/EBG/kQ6lE Cancel-Lock: sha1:KsjyZfXg0cnYlxeX8qwG3dYj4sk= User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: <47247a14-76e1-4507-8f32-447a48c04c67@w1g2000vba.googlegroups.com> Xref: feeder.eternal-september.org comp.lang.vhdl:5399 On 11/28/2011 1:36 AM, a s wrote: > Can somebody please suggest how to work around the warning or suggest > a better way > in place of CE_decode function? Selects are a stubborn problem. My last looked something like: type cs_t is (ram, rom, led, keys, io); type cs_bits_t is array (cs_t) of std_ulogic; type cs_bytes_t is array (cs_t) of byte_t; signal cs_s : cs_t; signal cs_bits_s : cs_bits_t; signal rdy_bits_s : cs_bits_t; signal data_bytes_s : cs_bytes_t; -- some limits record -- some table of adr limit records: type cs_table_t is array (cs_t) of cs_limits_t; function cs_all return cs_bits_t is ...for loop for all selects cs_s <= cs_now(cs_bits_s); d <= data_bytes_s(cs_s); -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:15:36 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.albasani.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Alessandro Basili Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Date: Wed, 30 Nov 2011 17:37:18 +0100 Lines: 20 Message-ID: <9jn4duFgpaU1@mid.individual.net> References: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Trace: individual.net TtV5Og0j/icifUViCwyJKwWZw4HC+tg4QMcC39cShuCXTqVt9A Cancel-Lock: sha1:RYwI6Vi5DDEzZqkZaHhf1NMkiNI= User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: Xref: feeder.eternal-september.org comp.lang.vhdl:5400 On 11/28/2011 11:58 AM, valtih1978 wrote: >> Whether or not something is 'easy with > controllers' but maybe 'not easy' with an FPGA simply suggests that > you're more familiar with controllers > > No. It means that controllers have a built-in rs232 controller, which > can be easily commanded to send a byte. This is one simple line of C code. Again "easily commanded" to send a byte is just a matter of familiarity. I'm not aware of any function specified by the ANSI C standard that will accommodate the communication with a controller, therefore I presume that someone has got the time and the will to port the C library to the specific architecture of the controller you may have referred to, as well as the compiler, linker, assembler, archiver and possibly a splitter to produce (EEP)ROM images as well as a debugger. As I see it there's a lot behind the "simple line of C code" which may as well be behind any FPGA. "Nothing is easy for the unwilling" Thomas Fuller. From newsfish@newsfish Fri Feb 3 13:15:36 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: How do you use serial port or any other bus Date: Wed, 30 Nov 2011 21:20:33 +0200 Organization: A noiseless patient Spider Lines: 8 Message-ID: References: <9jn4duFgpaU1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 30 Nov 2011 19:20:35 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="5068"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+bk3Po3fabZgG4ZMp0QKG/gBipVz/SLUs=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: <9jn4duFgpaU1@mid.individual.net> Cancel-Lock: sha1:/9D4X/kRR0w4G2JREycmFi+HSKo= Xref: feeder.eternal-september.org comp.lang.vhdl:5401 > Again "easily commanded" to send a byte is just a matter of familiarity. It is not, again. It is a matter of what you develop further: controllers do have a predefined processor and UART. They are supplied with established compiler, linker, assembler, archiver and possibly a splitter to produce (EEP)ROM images as well as a debugger. Normally, you will not do uC vendor's job. When you start from FPGA, you must have synthesize an UART first. From newsfish@newsfish Fri Feb 3 13:15:37 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!zen.net.uk!dedekind.zen.co.uk!news.glorb.com!postnews.google.com!gl2g2000vbb.googlegroups.com!not-for-mail From: rykardu Newsgroups: comp.lang.vhdl Subject: Cache Memory Date: Thu, 1 Dec 2011 12:46:38 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: NNTP-Posting-Host: 200.20.196.226 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1322772506 26838 127.0.0.1 (1 Dec 2011 20:48:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 1 Dec 2011 20:48:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: gl2g2000vbb.googlegroups.com; posting-host=200.20.196.226; posting-account=YTekzgoAAADZ2ZlzwUs1oDgSKm4wRE4o User-Agent: G2/1.0 X-HTTP-Via: 1.1 proxyibm.corp.int.gov.br:3128 (squid/2.7.STABLE7) X-Google-Web-Client: true X-Google-Header-Order: HUALESRCVFNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5402 I'm working on a processor model written in vhdl and I'm looking for a model for a cache memory written in vhdl. The architecture of an embedded cache microarchitectureproposed by Tannenbaum. This cache must be of type copy back, set associative using two sets (2-way), with 64 positions, each set with a capacity to store blocks of 4 words of 16 bits. When a memory read is requested, the cache controller must determine whether it is a success or a failure and if the block stored in the cache is valid. If a hit, the word address must be supplied to the processor. If one fails, the main memory to be accessed, the cache should be refreshed and the bit of validity must be activated before the word to be supplied to the processor. When a write memory is requested, the cache controller must immediately determine whether it is a success or a failure. If a hit, the cache should be updated with the new word. If one fails, the cache must be updated with the new block and then the new word must be written in the cache. The replacement policy chooses the set of blocks that used less often. Only blocks that have been modified to be written back to main memory. This will need to add a bit of modification, indicating that that block was changed while in cache. The cache control is done by the microprogram. The main memory to the processor in question is 4K words of 16 bits. So, some components i have built but other not (for copy back, data_buffer) etc. I read here to try the website (www.gaisler.com) but 404. tks From newsfish@newsfish Fri Feb 3 13:15:37 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feeder1-2.proxad.net!proxad.net!feeder1-1.proxad.net!198.186.194.247.MISMATCH!news-out.readnews.com!transit3.readnews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe18.iad.POSTED!00000000!not-for-mail Message-ID: <4ED8211F.1080404@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Using Xilinx VHDL code with UNISIM on Altera toolset Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 15 NNTP-Posting-Host: 70.64.82.220 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe18.iad 1322787108 70.64.82.220 (Fri, 02 Dec 2011 00:51:48 UTC) NNTP-Posting-Date: Fri, 02 Dec 2011 00:51:48 UTC Date: Thu, 01 Dec 2011 18:51:43 -0600 Xref: feeder.eternal-september.org comp.lang.vhdl:5403 Hello, I've recently downloaded some VHDL code (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to port this code to run on an Altera FPGA. However, the VHDL code makes reference to the UNISIM library. I am wondering if it would be possible to modify this code so that it can run on an Altera processor. What functionality is offered by the UNISIM library, and is it possible to replicate this functionality using Xilinx tools? Thank you, Nicholas From newsfish@newsfish Fri Feb 3 13:15:37 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w1g2000vba.googlegroups.com!not-for-mail From: backhus Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset Date: Thu, 1 Dec 2011 22:49:58 -0800 (PST) Organization: http://groups.google.com Lines: 31 Message-ID: <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> References: <4ED8211F.1080404@usask.ca> NNTP-Posting-Host: 194.94.26.216 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1322808599 6611 127.0.0.1 (2 Dec 2011 06:49:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 2 Dec 2011 06:49:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w1g2000vba.googlegroups.com; posting-host=194.94.26.216; posting-account=lfdCIgoAAADzxqdfy5_JJnuIHN62Ng9K User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Ubuntu; X11; Linux i686; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5404 On 2 Dez., 01:51, Nicholas Kinar wrote: > Hello, > > I've recently downloaded some VHDL code > (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to > port this code to run on an Altera FPGA. > > However, the VHDL code makes reference to the UNISIM library. =A0I am > wondering if it would be possible to modify this code so that it can run > on an Altera processor. =A0What functionality is offered by the UNISIM > library, and is it possible to replicate this functionality using Xilinx > tools? > > Thank you, > > Nicholas Hi Nicholas, UNISIM mainly contains primitive elements of the XILINX FPGAs, but this may also include special I/O elements and even stuff like DCMs etc. Browse the code to find what elements from UNISIM are instantiated. In most cases (like for AND2 etc.) you will find simple replacements in the Altera libraries. For other stuff you have to find something that comes close and adapt the design, since some elements are specific for each vendors FPGA fabric. Have a nice synthesis Eilert From newsfish@newsfish Fri Feb 3 13:15:38 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe17.iad.POSTED!00000000!not-for-mail Message-ID: <4ED8E48E.8010600@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> In-Reply-To: <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 47 NNTP-Posting-Host: 70.64.82.220 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe17.iad 1322837141 70.64.82.220 (Fri, 02 Dec 2011 14:45:41 UTC) NNTP-Posting-Date: Fri, 02 Dec 2011 14:45:41 UTC Date: Fri, 02 Dec 2011 08:45:34 -0600 Xref: feeder.eternal-september.org comp.lang.vhdl:5405 > Hi Nicholas, > UNISIM mainly contains primitive elements of the XILINX FPGAs, but > this may also include special I/O elements and even stuff like DCMs > etc. > > Browse the code to find what elements from UNISIM are instantiated. > In most cases (like for AND2 etc.) you will find simple replacements > in the Altera libraries. > For other stuff you have to find something that comes close and adapt > the design, since some elements are specific for each vendors FPGA > fabric. > > Have a nice synthesis > Eilert Thanks, Eilert; this is very much appreciated! By removing "UNISIM" from "library IEEE, UNISIM;" I was able to see errors caused by not having the UNISIM library available. Most of these errors seem to be associated with not having the following functions available: log2 int_select as well as the following identifiers: YES NO It appears that log2 is the logarithm to the base 2. Alternately, int_select appears to be something that selects between integers. YES and NO might map to boolean values. Is there any VHDL source or documentation available for log2, the init_select, and the YES and NO values? Nicholas From newsfish@newsfish Fri Feb 3 13:15:38 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Re: External name elaboration order Date: Sun, 04 Dec 2011 18:39:21 +0200 Organization: A noiseless patient Spider Lines: 22 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Sun, 4 Dec 2011 16:39:22 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="10763"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Be1npWXWIiXdRLyZJaQnGNdRGudXb2Ds=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 In-Reply-To: Cancel-Lock: sha1:yxZ/goSelloiUxTOdpg9bIMVYNo= Xref: feeder.eternal-september.org comp.lang.vhdl:5406 >> That is, they say that situation is the same and object, referenced in >> external name, must be elaborated before external name. >> > > The paragraph you quote refers specifically to use of a signal > referenced by an external signal name *in a port map*. Yes, but it says that external constant evaluation during simulation "is related" to external signals in the port map during elaboration. do they say that external constant evaluation is treated in the same way as port map elaboration? Also, I could not understand why (and how) the signals, declared in the body of subinstance, are different from port map? I do not see essential difference between elaboration and evaluation. The elaboration establishes the references. Evaluation uses em. Indeed, you cannot use unestablished reference. But, in the same way, you cannot establish it either until referenced object is elaborated. How making exclusions for constants and port maps improves the situation? From newsfish@newsfish Fri Feb 3 13:15:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!n6g2000vbg.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Why isnt buffer used more often? Date: Mon, 5 Dec 2011 00:44:42 -0800 (PST) Organization: http://groups.google.com Lines: 6 Message-ID: NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1323074803 9438 127.0.0.1 (5 Dec 2011 08:46:43 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 5 Dec 2011 08:46:43 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n6g2000vbg.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5407 Is there any reason more people dont use the buffer port type? is there anything you cant do with it that you can do with an internal signal? Is it just an old thing that old synthesisors wouldnt support it, and it has fallen out of favour? From newsfish@newsfish Fri Feb 3 13:15:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: "scrts" Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? Date: Mon, 5 Dec 2011 10:54:33 +0200 Organization: A noiseless patient Spider Lines: 9 Message-ID: References: Injection-Date: Mon, 5 Dec 2011 08:54:46 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="iT5NBGfOsLgPoft0V0gh3A"; logging-data="7572"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/3lPVn8FNeOobdRd4xq+rd" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.6157 X-RFC2646: Format=Flowed; Original X-Newsreader: Microsoft Outlook Express 6.00.2900.5931 Cancel-Lock: sha1:PzVwY8Map5sNVs+9zCflRu3+s3M= X-Priority: 3 X-MSMail-Priority: Normal Xref: feeder.eternal-september.org comp.lang.vhdl:5408 >"Tricky" wrote in message >news:bee42e96-9d0f-438f-8a58-5f6cc2dcd879@n6g2000vbg.googlegroups.com... > Is there any reason more people dont use the buffer port type? is > there anything you cant do with it that you can do with an internal > signal? Probably because it could mess up the design flow understanding. From newsfish@newsfish Fri Feb 3 13:15:39 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: Brian Drummond Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? Date: Mon, 5 Dec 2011 10:17:03 +0000 (UTC) Organization: A noiseless patient Spider Lines: 26 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Injection-Date: Mon, 5 Dec 2011 10:17:03 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="DkTdSjxOCm6DqG+Uf7eArg"; logging-data="27214"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19CpACiTpufkmfOiZQgWFGdZX1qvW6sxqI=" User-Agent: Pan/0.134 (Wait for Me; GIT cb32159 master) Cancel-Lock: sha1:0S/h+UNlYpdFbL2FYCKiBwsEwFY= Xref: feeder.eternal-september.org comp.lang.vhdl:5409 On Mon, 05 Dec 2011 10:54:33 +0200, scrts wrote: >>"Tricky" wrote in message >>news:bee42e96-9d0f-438f-8a58-5f6cc2dcd879@n6g2000vbg.googlegroups.com... >> Is there any reason more people dont use the buffer port type? is there >> anything you cant do with it that you can do with an internal signal? > > Probably because it could mess up the design flow understanding. I don't see how, really. It could certainly mess up the process of verifying the design, mostly because synthesis tools would pour out thousands of spurious warnings, presumably hangovers from a much earlier release that might have got it wrong. (For the record I never did see an actual problem, at least as far back as Leonardo/Galileo, but there may have been some) There were some (to my eyes, apparently unnecessary) rules about connecting internal Buffer ports to higher level Out ports or vice-versa, that made it difficult to mix the two styles, so Buffer was not as useful in practice as it looked. - Brian From newsfish@newsfish Fri Feb 3 13:15:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d10g2000vbf.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset Date: Mon, 5 Dec 2011 02:28:27 -0800 (PST) Organization: http://groups.google.com Lines: 58 Message-ID: References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> <4ED8E48E.8010600@usask.ca> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1323080907 7590 127.0.0.1 (5 Dec 2011 10:28:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 5 Dec 2011 10:28:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d10g2000vbf.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5410 On Dec 2, 2:45=A0pm, Nicholas Kinar wrote: > > Hi Nicholas, > > UNISIM mainly contains primitive elements of the XILINX FPGAs, but > > this may also include special I/O elements and even stuff like DCMs > > etc. > > > Browse the code to find what elements from UNISIM are instantiated. > > In most cases (like for AND2 etc.) you will find simple replacements > > in the Altera libraries. > > For other stuff you have to find something that comes close and adapt > > the design, since some elements are specific for each vendors FPGA > > fabric. > > > Have a nice synthesis > > =A0 =A0Eilert > > Thanks, Eilert; this is very much appreciated! =A0By removing "UNISIM" > from "library IEEE, UNISIM;" I was able to see errors caused by not > having the UNISIM library available. > > Most of these errors seem to be associated with not having the > following functions available: > > log2 > int_select > > as well as the following identifiers: > > YES > NO > > It appears that log2 is the logarithm to the base 2. =A0Alternately, > int_select appears to be something that selects between integers. YES > and NO might map to boolean values. > > Is there any VHDL source or documentation available for log2, the > init_select, and the YES and NO values? > > Nicholas If you have a copy of modelsim with the unisim libraries, see if you can view the source code here. It is Xilinx Proprietary so you may not have the source. As for log2, its a fairly universal function you can write easily with a for loop: function log2( i : natural) return integer is variable temp : integer :=3D i; variable ret_val : integer :=3D 1; --log2 of 0 should equal 1 because you still need 1 bit to represent 0 begin while temp > 1 loop ret_val :=3D ret_val + 1; temp :=3D temp / 2; end loop; return ret_val; end function; From newsfish@newsfish Fri Feb 3 13:15:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!rt.uk.eu.org!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe07.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111204-1, 04/12/2011), Outbound message X-Antivirus-Status: Clean Lines: 14 Message-ID: NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe07.ams2 1323084831 86.29.13.122 (Mon, 05 Dec 2011 11:33:51 UTC) NNTP-Posting-Date: Mon, 05 Dec 2011 11:33:51 UTC Organization: virginmedia.com Date: Mon, 05 Dec 2011 11:33:51 +0000 Xref: feeder.eternal-september.org comp.lang.vhdl:5411 On 05/12/2011 08:44, Tricky wrote: > Is there any reason more people dont use the buffer port type? is > there anything you cant do with it that you can do with an internal > signal? > > Is it just an old thing that old synthesisors wouldnt support it, and > it has fallen out of favour? With the VHDL2008 capability of reading an output port I guess it will become obsolete? Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:15:40 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!z12g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? Date: Mon, 5 Dec 2011 08:29:02 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <478b7497-8374-4bb2-8563-ebf9d1c3bdeb@z12g2000yqm.googlegroups.com> References: NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1323102542 2830 127.0.0.1 (5 Dec 2011 16:29:02 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 5 Dec 2011 16:29:02 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z12g2000yqm.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5412 On Dec 5, 5:33=A0am, HT-Lab wrote: > > With the VHDL2008 capability of reading an output port I guess it will > become obsolete? > > Hanswww.ht-lab.com Depends on whether reading an output in 2008 version returns the driven value or the resolved value of the output. Andy From newsfish@newsfish Fri Feb 3 13:15:41 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!q9g2000yqe.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset Date: Mon, 5 Dec 2011 08:26:28 -0800 (PST) Organization: http://groups.google.com Lines: 22 Message-ID: <55aa0ea2-4b00-4cbf-8a4f-e2e227344fc5@q9g2000yqe.googlegroups.com> References: <4ED8211F.1080404@usask.ca> NNTP-Posting-Host: 192.35.35.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1323102754 4942 127.0.0.1 (5 Dec 2011 16:32:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 5 Dec 2011 16:32:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: q9g2000yqe.googlegroups.com; posting-host=192.35.35.34; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5413 On Dec 1, 6:51=A0pm, Nicholas Kinar wrote: > Hello, > > I've recently downloaded some VHDL code > (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to > port this code to run on an Altera FPGA. > > However, the VHDL code makes reference to the UNISIM library. =A0I am > wondering if it would be possible to modify this code so that it can run > on an Altera processor. =A0What functionality is offered by the UNISIM > library, and is it possible to replicate this functionality using Xilinx > tools? > > Thank you, > > Nicholas Check the licensing restrictions on the unisim library and for any other code from Xilinx. Most I've seen restricts use to Xilinx FPGAs only. Andy From newsfish@newsfish Fri Feb 3 13:15:41 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Mike Treseler Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? Date: Mon, 5 Dec 2011 12:58:55 -0800 (PST) Organization: http://groups.google.com Lines: 5 Message-ID: <24802038.247.1323118735780.JavaMail.geo-discussion-forums@prnu18> References: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.196.226.77 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1323118736 7674 127.0.0.1 (5 Dec 2011 20:58:56 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 5 Dec 2011 20:58:56 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.196.226.77; posting-account=ZqHybgoAAABt1ai6Zyp1GRmY8aIKjt9u User-Agent: G2/1.0 X-Google-Web-Client: true Xref: feeder.eternal-september.org comp.lang.vhdl:5414 Buffer ports worked fine last time I tried it. As I recall, it was sig'driving_value that used to fail silently in synthesis. I don't use buffer ports now because variables can drive both ports and nodes in process scope. -- Mike Treseler From newsfish@newsfish Fri Feb 3 13:15:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder5.xlned.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!209.197.12.246.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe02.iad.POSTED!00000000!not-for-mail Message-ID: <4EE0DB4A.1010803@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset References: <4ED8211F.1080404@usask.ca> <55aa0ea2-4b00-4cbf-8a4f-e2e227344fc5@q9g2000yqe.googlegroups.com> In-Reply-To: <55aa0ea2-4b00-4cbf-8a4f-e2e227344fc5@q9g2000yqe.googlegroups.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 12 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe02.iad 1323359053 70.64.71.190 (Thu, 08 Dec 2011 15:44:13 UTC) NNTP-Posting-Date: Thu, 08 Dec 2011 15:44:13 UTC Date: Thu, 08 Dec 2011 09:44:10 -0600 Xref: feeder.eternal-september.org comp.lang.vhdl:5415 On 05/12/2011 10:26 AM, Andy wrote: > > Check the licensing restrictions on the unisim library and for any > other code from Xilinx. Most I've seen restricts use to Xilinx FPGAs > only. > > Andy Thank you; I will check this out. Nicholas From newsfish@newsfish Fri Feb 3 13:15:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder7.xlned.com!news2.euro.net!209.197.12.242.MISMATCH!nx01.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe12.iad.POSTED!00000000!not-for-mail Message-ID: <4EE0F6F3.9020209@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> <4ED8E48E.8010600@usask.ca> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 25 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe12.iad 1323366134 70.64.71.190 (Thu, 08 Dec 2011 17:42:14 UTC) NNTP-Posting-Date: Thu, 08 Dec 2011 17:42:14 UTC Date: Thu, 08 Dec 2011 11:42:11 -0600 Xref: feeder.eternal-september.org comp.lang.vhdl:5416 > > If you have a copy of modelsim with the unisim libraries, see if you > can view the source code here. It is Xilinx Proprietary so you may not > have the source. > As for log2, its a fairly universal function you can write easily with > a for loop: > > function log2( i : natural) return integer is > variable temp : integer := i; > variable ret_val : integer := 1; --log2 of 0 should equal 1 because > you still need 1 bit to represent 0 > begin > while temp> 1 loop > ret_val := ret_val + 1; > temp := temp / 2; > end loop; > > return ret_val; > end function; Thank you; this is very useful. Nicholas From newsfish@newsfish Fri Feb 3 13:15:42 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!nx01.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!l24g2000yqm.googlegroups.com!not-for-mail From: Andy Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset Date: Fri, 9 Dec 2011 07:07:16 -0800 (PST) Organization: http://groups.google.com Lines: 55 Message-ID: References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> <4ED8E48E.8010600@usask.ca> NNTP-Posting-Host: 192.91.171.42 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1323443325 29101 127.0.0.1 (9 Dec 2011 15:08:45 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 9 Dec 2011 15:08:45 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: l24g2000yqm.googlegroups.com; posting-host=192.91.171.42; posting-account=q3CrIgoAAADDNQ3yqoe93AhtWVzpzUbS User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHCNK X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 6.1; WOW64; Trident/4.0; SLCC2; .NET CLR 2.0.50727; .NET CLR 3.5.30729; .NET CLR 3.0.30729; Media Center PC 6.0; InfoPath.2; .NET4.0C; .NET4.0E; MS-RTC LM 8),gzip(gfe) Xref: feeder.eternal-september.org comp.lang.vhdl:5417 On Dec 5, 4:28=A0am, Tricky wrote: > If you have a copy of modelsim with the unisim libraries, see if you > can view the source code here. It is Xilinx Proprietary so you may not > have the source. > As for log2, its a fairly universal function you can write easily with > a for loop: > > function log2( i : natural) return integer is > =A0 variable temp =A0 =A0: integer :=3D i; > =A0 variable ret_val : integer :=3D 1; --log2 of 0 should equal 1 because > you still need 1 bit to represent 0 > begin > =A0 while temp > 1 loop > =A0 =A0 ret_val :=3D ret_val + 1; > =A0 =A0 temp =A0 =A0:=3D temp / 2; > =A0 end loop; > > =A0 return ret_val; > end function;- Hide quoted text - > > - Show quoted text - This really should not be called log2() because it does not return the base 2 logarithm of the argument. It returns log2(i) + 1 instead. For example, log2(1) =3D 0, log2(2) =3D 1 and log2(0) is undefined. -- this (untested) function returns the base 2 logarithm of n:(n >=3D 1) function log2(n : positive) return natural is variable temp : positive :=3D n; variable retval : natural :=3D 0; begin while temp > 1 loop retval :=3D retval + 1; temp :=3D temp / 2; end loop; return retval; end function log2; I don't know if Xilinx's unisim log2() is similarly mathematically flawed, but I wanted to make sure that someone googling for a mathematical function "vhdl log2()" is not mislead. You can probably tell from the context of how Xilinx uses it whether or not their's is mathematically accurate, or just logically convenient. When calculating the number of bits required to represent the range 0 to n, use log2(n) + 1. However, the upper index of an appropriately sized unsigned subtype would be log2(n), assuming the lower index is 0. subtype n_range is natural range 0 to n; subtype n_unsigned is unsigned(log2(n_range'high) downto 0); variable x : natural range 0 to 0; -- is a constant Andy From newsfish@newsfish Fri Feb 3 13:15:43 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe17.iad.POSTED!00000000!not-for-mail Message-ID: <4EE39E88.40608@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> <4ED8E48E.8010600@usask.ca> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 48 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe17.iad 1323540111 70.64.71.190 (Sat, 10 Dec 2011 18:01:51 UTC) NNTP-Posting-Date: Sat, 10 Dec 2011 18:01:51 UTC Date: Sat, 10 Dec 2011 12:01:44 -0600 Xref: mx04.eternal-september.org comp.lang.vhdl:5418 > This really should not be called log2() because it does not return the > base 2 logarithm of the argument. It returns log2(i) + 1 instead. For > example, log2(1) = 0, log2(2) = 1 and log2(0) is undefined. > > -- this (untested) function returns the base 2 logarithm of n:(n>= 1) > function log2(n : positive) return natural is > variable temp : positive := n; > variable retval : natural := 0; > begin > while temp> 1 loop > retval := retval + 1; > temp := temp / 2; > end loop; > return retval; > end function log2; > > I don't know if Xilinx's unisim log2() is similarly mathematically > flawed, but I wanted to make sure that someone googling for a > mathematical function "vhdl log2()" is not mislead. You can probably > tell from the context of how Xilinx uses it whether or not their's is > mathematically accurate, or just logically convenient. > > When calculating the number of bits required to represent the range 0 > to n, use log2(n) + 1. However, the upper index of an appropriately > sized unsigned subtype would be log2(n), assuming the lower index is > 0. > > subtype n_range is natural range 0 to n; > subtype n_unsigned is unsigned(log2(n_range'high) downto 0); > > variable x : natural range 0 to 0; -- is a constant > > Andy Thanks, Andy; this is very helpful. I have now created a VHDL library with the log2 code. So this now takes care of the log2 function. My next step in porting the code is to fix errors related to unknown identifiers "int_select" as well as "yes" and "no". I am assuming that these are also defined in the UNISIM library? Nicholas From newsfish@newsfish Fri Feb 3 13:15:43 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!nx01.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe22.iad.POSTED!00000000!not-for-mail Message-ID: <4EE40D0B.4040008@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Using Xilinx VHDL code with UNISIM on Altera toolset References: <4ED8211F.1080404@usask.ca> <2139c946-2d7c-472d-99c8-32f8fb119040@w1g2000vba.googlegroups.com> <4ED8E48E.8010600@usask.ca> <4EE39E88.40608@usask.ca> In-Reply-To: <4EE39E88.40608@usask.ca> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 16 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe22.iad 1323568402 70.64.71.190 (Sun, 11 Dec 2011 01:53:22 UTC) NNTP-Posting-Date: Sun, 11 Dec 2011 01:53:22 UTC Date: Sat, 10 Dec 2011 19:53:15 -0600 Xref: mx04.eternal-september.org comp.lang.vhdl:5419 On 10/12/2011 12:01 PM, Nicholas Kinar wrote: > > My next step in porting the code is to fix errors related to unknown > identifiers "int_select" as well as "yes" and "no". I am assuming that > these are also defined in the UNISIM library? > > Nicholas > > It turns out that "int_select" is a function in the common.vhd file distributed with the SDRAM controller code. "Yes" and "No" are simply constants in the common package found within the common.vhd file. This seems to complete the final piece of the puzzle. Nicholas From newsfish@newsfish Fri Feb 3 13:15:44 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!d12g2000prg.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: SystemVerilog for verification Date: Mon, 12 Dec 2011 17:37:18 -0800 (PST) Organization: http://groups.google.com Lines: 118 Message-ID: <04f80f76-7764-4665-9e3b-b86663b0c305@d12g2000prg.googlegroups.com> References: NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1323740320 32345 127.0.0.1 (13 Dec 2011 01:38:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 13 Dec 2011 01:38:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d12g2000prg.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5421 Hi Rob, > I can, given sufficient time and energy, muddle through reading Verilog. > Never written a line of it. But I'm getting a vague sense, possibly > out of frustration, that a whole lot of verification benches, especially > as you're trying to get up into transaction level bus models, get easier > in SystemVerilog than they are doing it in VHDL, even with the 2008 > improvements. > > I'm pretty used to doing OOP in languages like Python, C++, and Perl, > and the idea of calling bus_master.write(address, data); seems like a > pretty natural way of stringing a bench together. For VHDL-2008, we looked at adding an interface construct. I wanted an upgrade from the record based IO I use. However at the same time, I also worked out acceptable resolution functions for integer, time, and real and found I can get by without an interface construct. >From a users perspective, I create a package, define a record, and define procedures that use the record. Then calls to the procedures in the package are of the following form (where bus_master is a record object whose elements are a resolved type): write(bus_master, address, data) ; On the other hand with OOP, the complexity of the tasks is about the same and the call is (where bus_master is a class object): bus_master.write(address, data); >From a VHDL purist perspective, it feels a little kludgey to initialize the bus_master signal object to give the drivers a default value, however, from a pragmatic perspective, it works and it does not require any new language features. Also from a pragmatic perspective, the current VHDL solution is good enough that I think we (the VHDL language committee) needs to focus our attention on other things. However, if someone is interested in putting forward a proposal, please step up and do it. If you are interested in what is happening with VHDL, see http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome There is always room for more helpers. With popular SV OOP methodologies, creating a transaction based testbench requires lots of fork and join to both initialize objects and create the concurrency. Sure with OOP, you can and are dynamically elaborating the testbench, however, how often are you plugging and unplugging components during a simulation run - never had much use for guarded blocks, but I suspect that they will handle this just fine. > The options for doing similar in VHDL (procedures with a billion > signal parameters or entities > with abstract req/ack ports and 'transaction signaling) seem, > comparatively, pretty crude. I've made them work time and again, but I > can't say I've ever sat back and read it back over and said "You know, > that's pretty elegant." When I use a BFM to do the interface waveform generation, I always use the req/ack ports. However, for simple interfaces that do not warrant a BFM, I just put the interface signals in the record and am done with it. I generally use the BFM because there is other stuff that is convenient to put in there, such as protocol checkers (VHDL or PSL) and interface waveform loggers. > I have no intention of giving up VHDL for my synthesizables; I cling to > strong typing like Linus to his blanket. But am I doing myself a > disservice by not learning SV? At the end of the day, it may end up like VHS vs Betamax and politics and/or marketing BS may determine the winner and not actual capability. As Hans mentioned, check out our Functional Coverage and Randomization packages at: http://www.synthworks.com/downloads The randomization packages rely on procedural randomization. Used by itself, procedural randomization requires a little more thought to get a balanced distribution of stimulus values, however, when combined with the intelligent coverage modeling supported by our functional coverage packages, it does better than simple solver based randomization. I am guessing that the results are similar to the intelligent randomization testbench tools for which you will have to purchase an additional license. See the documentation for more details. To help you go further, our testbench class (shameless advertising plug) also comes with packages for creating scoreboards, resolving integers, real, and time, creating memory models (using a methodology that is easier than using an array), and utilities. If you are considering switching to SV for testbenches and the costs are ok, make sure to take a class first (not a plug as our focus is on VHDL) as this will give you a better idea of what you are getting into - before you make the investment. Also, no reason not to check out the free materials out there - Mentor and Aldec both have SV web presentations recorded on their websites. Best, Jim P.S. If you are a senior member of the VHDL community, you should be participating in the VHDL standards. VHDL is an individual based standard and while membership in IEEE, IEEE-SA, and DASC are always greatly appreciated, they are not required for participation. For more details see: http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome Don't let your good ideas be overlooked. Particularly those of you who have OOP experience. From newsfish@newsfish Fri Feb 3 13:15:44 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!f30g2000pri.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: incremental generic association Date: Mon, 12 Dec 2011 18:03:39 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <88f5e5ad-2c47-40b4-a4dc-4e0e8edb5630@f30g2000pri.googlegroups.com> References: NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1323741905 16569 127.0.0.1 (13 Dec 2011 02:05:05 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 13 Dec 2011 02:05:05 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f30g2000pri.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5422 Hi Sebs, See Peter Ashenden's book. Below is my paraphrase. With component instantiation, you are creating a local object with local ports and local generics. By default, component name binds to entity name, local ports map to entity formal ports, and local generics map to entity formal generics. When you choose to map the entity formal generics, you must specify a value for each formal generic - either a new value or the value from a component. Hence change your generic map to: generic map ( g_Segments => 10, -- formal generic getting new value g_One => g_One, -- formal generic getting local generic ... -- map all of the formal generics ); Thanks for posting this as it clarified my understanding of this. I had thought it was as easy as what you posted, but I do remember having done it as above. Best, Jim From newsfish@newsfish Fri Feb 3 13:15:45 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d5g2000prf.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? Date: Mon, 12 Dec 2011 18:14:57 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: References: <478b7497-8374-4bb2-8563-ebf9d1c3bdeb@z12g2000yqm.googlegroups.com> NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1323743346 30495 127.0.0.1 (13 Dec 2011 02:29:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 13 Dec 2011 02:29:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d5g2000prf.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5423 On Dec 5, 8:29=A0am, Andy wrote: > Depends on whether reading an output in 2008 version returns the > driven value or the resolved value of the output. Driving value: Ports of mode out have identical semantics to ports of mode buffer. Jim From newsfish@newsfish Fri Feb 3 13:15:45 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d17g2000prl.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: External name elaboration order Date: Mon, 12 Dec 2011 18:34:32 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <558395b2-bf89-4da1-bfc2-52d19b08de53@d17g2000prl.googlegroups.com> References: NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1323743672 1589 127.0.0.1 (13 Dec 2011 02:34:32 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 13 Dec 2011 02:34:32 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d17g2000prl.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5424 Hi Valtih1978 (interesting name), You don't quite have the terminology correct. The "external name" is the hierarchical reference: <> The constant, which is in the entity duv, is: constant WIDTH : natural := 5 ; Hence, the required order is: architecture level of top is begin -- instantiating DUV first makes objects declared in it elaborate first duv : entity work.design(rtl); -- now do external name references: assert false report "Width = " & to_string(<>); end level ; Best, Jim From newsfish@newsfish Fri Feb 3 13:15:46 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news-2.dfn.de!news.dfn.de!news.uni-stuttgart.de!newsfeed.in-ulm.de!not-for-mail From: Steffen Koepf Newsgroups: comp.lang.vhdl Subject: Converted signed 16 Bit to unsigned? Date: Wed, 14 Dec 2011 22:03:41 +0000 (UTC) Organization: [ posted via ] IN-Ulm Lines: 25 Sender: Steffen Koepf Message-ID: X-Trace: news.in-ulm.de 2722C3B15F0758B00E83A8C128930240 User-Agent: tin/pre-1.4-19990805 ("Preacher Man") (UNIX) (Linux/2.6.30.10 (i686)) Xref: mx04.eternal-september.org comp.lang.vhdl:5425 Hello, I have a AD Converter that delivers a 16 Bit signed value 8000 - 0 - 7FFF I want to convert this to unsigned 16 Bit from 0 - 8000 - FFFF by signal RecRegA : std_logic_vector (15 downto 0); signal RecRegA1 : std_logic_vector (15 downto 0); RecRegA1 <= std_logic_vector(unsigned(RecRegA) + 32768); This works in the lower 3/4 range. But as soon as the result exceeds 7FFF the result is unpredictable. Why? Thanks in advance, Steffen From newsfish@newsfish Fri Feb 3 13:15:46 2012 Path: eternal-september.org!mx04.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Converted signed 16 Bit to unsigned? Date: Wed, 14 Dec 2011 17:52:37 -0500 Organization: Alacron, Inc. Lines: 29 Message-ID: References: Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 14 Dec 2011 22:52:57 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="348"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX186W1rSWdWSI1VW4RMdAwMM" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: Cancel-Lock: sha1:K2T3VCljbsyJ+KY81OWI0ZGPbuM= Xref: mx04.eternal-september.org comp.lang.vhdl:5426 Steffen Koepf wrote: > Hello, > > I have a AD Converter that delivers a 16 Bit signed value 8000 - 0 - 7FFF > > I want to convert this to unsigned 16 Bit from 0 - 8000 - FFFF > > by > > signal RecRegA : std_logic_vector (15 downto 0); > > signal RecRegA1 : std_logic_vector (15 downto 0); > > > RecRegA1 <= std_logic_vector(unsigned(RecRegA) + 32768); > > > This works in the lower 3/4 range. But as soon as the result exceeds 7FFF > the result is unpredictable. Why? > > Thanks in advance, > > Steffen > > That's a lot of conversions. All you really need to do is invert the MSB of the first vector. What libraries are you using? -- Gabor From newsfish@newsfish Fri Feb 3 13:15:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!news-out.readnews.com!transit4.readnews.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.21.MISMATCH!npeer03.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe10.iad.POSTED!00000000!not-for-mail Message-ID: <4EE9722E.6020603@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Getting rid of packages in VHDL code Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 20 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe10.iad 1323921973 70.64.71.190 (Thu, 15 Dec 2011 04:06:13 UTC) NNTP-Posting-Date: Thu, 15 Dec 2011 04:06:13 UTC Date: Wed, 14 Dec 2011 22:06:06 -0600 Xref: mx04.eternal-september.org comp.lang.vhdl:5427 Hello, I am working with some VHDL code (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to use an automated tool to convert the VHDL code to Verilog (http://www.ocean-logic.com/downloads.htm). Unfortunately, the automated tool does not seem to support VHDL packages (containing functions). The "proper way" to convert the code would be to do the conversion by hand, but in the meantime: Is there a way to remove the packages from the VHDL code? Is there another way to bundle functions instead of using packages? There are two files in the download that demonstrate the use of packages: sdramcntl.vhd and common.vhd. Thank you, Nicholas From newsfish@newsfish Fri Feb 3 13:15:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!feeder.erje.net!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Date: Thu, 15 Dec 2011 16:11:00 +0100 From: Pieter Hulshoff User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111108 Fedora/3.1.16-1.fc14 Lightning/1.0b3pre Thunderbird/3.1.16 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Why isnt buffer used more often? References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 13 Message-ID: <4eea0e04$0$6898$e4fe514c@news2.news.xs4all.nl> NNTP-Posting-Host: 195.242.97.150 X-Trace: 1323961860 news2.news.xs4all.nl 6898 phulshof/195.242.97.150:36607 Xref: mx04.eternal-september.org comp.lang.vhdl:5428 On 12/05/11 09:44, Tricky wrote: > Is there any reason more people dont use the buffer port type? is > there anything you cant do with it that you can do with an internal > signal? > > Is it just an old thing that old synthesisors wouldnt support it, and > it has fallen out of favour? Other than on top-level, we use type BUFFER for all our block output ports. We've not had any trouble with that for over 14 years now. Kind regards, Pieter Hulshoff From newsfish@newsfish Fri Feb 3 13:15:47 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!cs.uu.nl!weretis.net!feeder1.news.weretis.net!feeder.erje.net!newsreader4.netcologne.de!news.netcologne.de!nx02.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe10.iad.POSTED!1f62a51f!not-for-mail From: Stephen Williams User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Getting rid of packages in VHDL code References: <4EE9722E.6020603@usask.ca> In-Reply-To: <4EE9722E.6020603@usask.ca> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 29 Message-ID: <7EqGq.17629$mJ.5357@newsfe10.iad> X-Complaints-To: abuse2@dslextreme.com NNTP-Posting-Date: Thu, 15 Dec 2011 18:03:47 UTC Organization: DSL Extreme Date: Thu, 15 Dec 2011 10:03:46 -0800 Xref: mx04.eternal-september.org comp.lang.vhdl:5429 Icarus Verilog has been growing the ability to parse and elaborate VHDL, and it does support packages, although not yet functions. You can then use the verilog code generator to effectively get a conversion from VHDL to Verilog. The intent is to support mixed language VHDL/Verilog simulations, but the ability to translate comes more or less for free. All this is in the current git master, and it is very much a work in progress. On 12/14/2011 08:06 PM, Nicholas Kinar wrote: > Hello, > > I am working with some VHDL code > (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to use > an automated tool to convert the VHDL code to Verilog > (http://www.ocean-logic.com/downloads.htm). > > Unfortunately, the automated tool does not seem to support VHDL packages > (containing functions). The "proper way" to convert the code would be > to do the conversion by hand, but in the meantime: -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From newsfish@newsfish Fri Feb 3 13:15:48 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe17.iad.POSTED!00000000!not-for-mail Message-ID: <4EEA438F.6010000@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Getting rid of packages in VHDL code References: <4EE9722E.6020603@usask.ca> <7EqGq.17629$mJ.5357@newsfe10.iad> In-Reply-To: <7EqGq.17629$mJ.5357@newsfe10.iad> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 43 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe17.iad 1323975575 70.64.71.190 (Thu, 15 Dec 2011 18:59:35 UTC) NNTP-Posting-Date: Thu, 15 Dec 2011 18:59:35 UTC Date: Thu, 15 Dec 2011 12:59:27 -0600 Xref: mx04.eternal-september.org comp.lang.vhdl:5430 On 15/12/2011 12:03 PM, Stephen Williams wrote: > > Icarus Verilog has been growing the ability to parse and elaborate > VHDL, and it does support packages, although not yet functions. You > can then use the verilog code generator to effectively get a > conversion from VHDL to Verilog. The intent is to support mixed > language VHDL/Verilog simulations, but the ability to translate > comes more or less for free. > > All this is in the current git master, and it is very much a work > in progress. > That's great Stephen; you share some very marvelous news. So Icarus can indeed convert VHDL to Verilog! Icarus is actually the primary Verilog simulator that I use, and I didn't know this feature was making it into the git master. Over the past couple of days (and even weeks), I have been trying various proprietary simulators to do mixed-mode (VHDL and Verilog) simulation, but I find it very frustrating to work with these crippled and buggy software packages. I have been going around in circles trying to work with both VHDL and Verilog. I will clone the current Icarus git master and try to compile the most recent version of Icarus. 1) Is there a tutorial/manual page on how to convert VHDL to Verilog using Icarus? I suspect that it could be similar to the one shown here: http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator 2) Is there a way to get rid of the VHDL functions in the code by replacing the functions with a similar construct supported by Icarus Verilog? Many thanks, Nicholas From newsfish@newsfish Fri Feb 3 13:15:48 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe08.iad.POSTED!1f62a51f!not-for-mail From: Stephen Williams User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Getting rid of packages in VHDL code References: <4EE9722E.6020603@usask.ca> <7EqGq.17629$mJ.5357@newsfe10.iad> <4EEA438F.6010000@usask.ca> In-Reply-To: <4EEA438F.6010000@usask.ca> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Lines: 54 Message-ID: X-Complaints-To: abuse2@dslextreme.com NNTP-Posting-Date: Thu, 15 Dec 2011 19:20:15 UTC Organization: DSL Extreme Date: Thu, 15 Dec 2011 11:20:13 -0800 Xref: mx04.eternal-september.org comp.lang.vhdl:5431 On 12/15/2011 10:59 AM, Nicholas Kinar wrote: > That's great Stephen; you share some very marvelous news. So Icarus can > indeed convert VHDL to Verilog! It can also simulate it without conversion. Or at least some bits of it. This is a work in progress. > Icarus is actually the primary Verilog simulator that I use, and I > didn't know this feature was making it into the git master. Over the > past couple of days (and even weeks), I have been trying various > proprietary simulators to do mixed-mode (VHDL and Verilog) simulation, > but I find it very frustrating to work with these crippled and buggy > software packages. I have been going around in circles trying to work > with both VHDL and Verilog. The main intent is to support mixed language simulations, not to make a converter. Conversion comes for free, but it sounds like you'd be just as happy with mixed language simulations. > 1) Is there a tutorial/manual page on how to convert VHDL to Verilog > using Icarus? I suspect that it could be similar to the one shown here: > http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator There is no tutorial or documentation on how to use the VHDL support. The page you point out above is for the VHDL code generator (i.e. to convert Verilog to VHDL) but you are trying to go the other way. It *is* very much a work in progress and documentation is needed. > 2) Is there a way to get rid of the VHDL functions in the code by > replacing the functions with a similar construct supported by Icarus > Verilog? Better would be to actually get Icarus Verilog to support the code that you have, rather then change it to what Icarus Verilog can support, but in the short term it may be more expedient to change your code to what Icarus Verilog can support. No, I do not know of any tools that can do that automatically. You might want to lurk and/or ask about it on the iverilog-devel mailing list. P.S. (and pardon the marketing) The VHDL/mixed language support was sponsored/paid for. That model works well for me and if there are specific needs you would like addressed with higher priority, I, and possibly others on the iverilog-devel mailing list, am open to doing contract work to address your specific needs. I am actively looking for more sponsorships for this open source work. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." From newsfish@newsfish Fri Feb 3 13:15:49 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news1.as3257.net!nx01.iad01.newshosting.com!newshosting.com!69.16.185.16.MISMATCH!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!newsfe17.iad.POSTED!00000000!not-for-mail Message-ID: <4EEA4D49.5050002@usask.ca> From: Nicholas Kinar User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: Getting rid of packages in VHDL code References: <4EE9722E.6020603@usask.ca> <7EqGq.17629$mJ.5357@newsfe10.iad> <4EEA438F.6010000@usask.ca> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 46 NNTP-Posting-Host: 70.64.71.190 X-Complaints-To: internet.abuse@sjrb.ca X-Trace: newsfe17.iad 1323978064 70.64.71.190 (Thu, 15 Dec 2011 19:41:04 UTC) NNTP-Posting-Date: Thu, 15 Dec 2011 19:41:04 UTC Date: Thu, 15 Dec 2011 13:40:57 -0600 Xref: mx04.eternal-september.org comp.lang.vhdl:5432 On 15/12/2011 1:20 PM, Stephen Williams wrote: > The main intent is to support mixed language simulations, not to make > a converter. Conversion comes for free, but it sounds like you'd be > just as happy with mixed language simulations. Thanks for your response, Stephen! I would indeed be just as happy with mixed language simulations. > >> 1) Is there a tutorial/manual page on how to convert VHDL to Verilog >> using Icarus? I suspect that it could be similar to the one shown here: >> http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator > > There is no tutorial or documentation on how to use the VHDL support. > The page you point out above is for the VHDL code generator (i.e. to > convert Verilog to VHDL) but you are trying to go the other way. It > *is* very much a work in progress and documentation is needed. Okay, I suppose that there has to be some command-line switches that can be used to do the conversion. I suspect that either reading the code or looking at the command-line help would be insightful. I will try to ask about it on the iverilog-devel mailing list. > >> 2) Is there a way to get rid of the VHDL functions in the code by >> replacing the functions with a similar construct supported by Icarus >> Verilog? > > Better would be to actually get Icarus Verilog to support the code > that you have, rather then change it to what Icarus Verilog can support, > but in the short term it may be more expedient to change your code to > what Icarus Verilog can support. No, I do not know of any tools that > can do that automatically. > > You might want to lurk and/or ask about it on the iverilog-devel > mailing list. Hmm, I would wonder if I could simply modify the VHDL file by hand to use something similar to functions. I will try to compile the Icarus Verilog code from git and then ask about changing the code on the iverilog-devel mailing list. Nicholas From newsfish@newsfish Fri Feb 3 13:15:49 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!news.tele.dk!news.tele.dk!small.news.tele.dk!feed118.news.tele.dk!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail From: David Belohrad Newsgroups: comp.lang.vhdl Subject: psl assertion for dynamically created signal length Date: Fri, 16 Dec 2011 10:10:50 +0100 Message-ID: <87vcpgzxt1.fsf@beesknees.cern.ch> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.2 (gnu/linux) Cancel-Lock: sha1:EepAPJxRePs7fc8XD/sg2/Qm298= MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Lines: 20 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 137.138.197.99 X-Trace: news.sunsite.dk DXC=eZ:OHfIj9CS[eoV[BRG`:]YSB=nbEKnk[AZMjG7T4m[^0V[^BPLO90YPmlZ]lVB_ {PulsexS[*25]; not PulsexS}; However, the PulsexS duration is not given as constant, but its length is setup by master entity. So ideally I'd like to have something like: psl assert always {StartPulsexS} |=> {PulsexS[*PulseLengthxD]; not PulsexS}; where PulseLengthxD is a type of either std_logic_vector/unsigned/integer... but apparently nothing like this works in mentor modelsim.... How to write such constraint? thanks d. From newsfish@newsfish Fri Feb 3 13:15:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.x-privat.org!feed.xsnews.nl!border-1.ams.xsnews.nl!cyclone02.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe28.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Re: psl assertion for dynamically created signal length References: <87vcpgzxt1.fsf@beesknees.cern.ch> In-Reply-To: <87vcpgzxt1.fsf@beesknees.cern.ch> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 111215-2, 15/12/2011), Outbound message X-Antivirus-Status: Clean Lines: 35 Message-ID: NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe28.ams2 1324032030 86.29.13.122 (Fri, 16 Dec 2011 10:40:30 UTC) NNTP-Posting-Date: Fri, 16 Dec 2011 10:40:30 UTC Organization: virginmedia.com Date: Fri, 16 Dec 2011 10:40:33 +0000 Xref: mx04.eternal-september.org comp.lang.vhdl:5434 On 16/12/2011 09:10, David Belohrad wrote: > Dear All, > > I'd like to produce following like PSL construct: > > psl assert always {StartPulsexS} |=> {PulsexS[*25]; not PulsexS}; > > However, the PulsexS duration is not given as constant, but its length > is setup by master entity. So ideally I'd like to have something like: > > psl assert always {StartPulsexS} |=> {PulsexS[*PulseLengthxD]; not PulsexS}; > > where PulseLengthxD is a type of either > std_logic_vector/unsigned/integer... but apparently nothing like this > works in mentor modelsim.... > > How to write such constraint? > > thanks > > d. I believe that PSL ranges must be static (resolved during compile/elaboration), thus PulseLengthxD must be a constant. Search the PSL reference manual for "Range" Can you run multiple tests? In that case you can make PulseLengthxD a top level generic and invoke Modelsim with vsim -GPulseLengthxD=xx Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:15:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n6g2000vbg.googlegroups.com!not-for-mail From: mksuth Newsgroups: comp.lang.vhdl Subject: Can a vhdl function return a range? Date: Fri, 16 Dec 2011 10:53:47 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: NNTP-Posting-Host: 67.62.51.170 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1324061627 32300 127.0.0.1 (16 Dec 2011 18:53:47 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 16 Dec 2011 18:53:47 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n6g2000vbg.googlegroups.com; posting-host=67.62.51.170; posting-account=Q0yMNQoAAACGirFDx4sD_uQ3VcH3lbSY User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/535.7 (KHTML, like Gecko) Chrome/16.0.912.63 Safari/535.7,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5435 I'd like to use a function to compute the 'X downto Y' range of a vector. Is there a clean way of doing this? -- something like this would be nice: function get_slice(n : natural) return range is begin return (n+1)*4 downto n*4; end function -- so I can use it on an slv like this: a <= b(get_slice(2)); From newsfish@newsfish Fri Feb 3 13:15:50 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!da3g2000vbb.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Can a vhdl function return a range? Date: Fri, 16 Dec 2011 11:30:00 -0800 (PST) Organization: http://groups.google.com Lines: 30 Message-ID: <9574639a-88a0-4e65-a119-259e7334c99a@da3g2000vbb.googlegroups.com> References: NNTP-Posting-Host: 50.77.206.245 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324063800 22201 127.0.0.1 (16 Dec 2011 19:30:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 16 Dec 2011 19:30:00 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: da3g2000vbb.googlegroups.com; posting-host=50.77.206.245; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.2; .NET CLR 2.0.50727; .NET CLR 1.1.4322; InfoPath.2; MS-RTC LM 8; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5436 On Dec 16, 1:53=A0pm, mksuth wrote: > I'd like to use a function to compute the 'X downto Y' range of a > vector. Is there a clean way of doing this? > > -- something like this would be nice: > function get_slice(n : natural) return range is > begin > =A0 =A0return (n+1)*4 downto n*4; > end function > > -- so I can use it on an slv like this: > a <=3D b(get_slice(2)); No you can't return a range. However you could instead send the vector and the selection into get_slice to have it return the vector slice. function get_slice(v: std_logic_vector; n : natural) return std_logic_vector is begin return v((n+1)*4 downto n*4); end function -- so you can use it on an slv like this: a <=3D get_slice(b, 2); The difference between the two approaches on the usage are basically cosmetic. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:51 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!feed.news.qwest.net!mpls-nntp-06.inet.qwest.net!news-out.readnews.com!transit3.readnews.com!postnews.google.com!z17g2000vbe.googlegroups.com!not-for-mail From: manolis kaliorakis Newsgroups: comp.lang.vhdl Subject: convert boolean to std_logic Date: Sat, 17 Dec 2011 05:56:21 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <3358eb5d-5db4-4286-afb2-6db01fa2113f@z17g2000vbe.googlegroups.com> NNTP-Posting-Host: 85.75.67.208 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1324130181 17568 127.0.0.1 (17 Dec 2011 13:56:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 17 Dec 2011 13:56:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: z17g2000vbe.googlegroups.com; posting-host=85.75.67.208; posting-account=_qX70QoAAADxBlFMFCOH_IKGym5fgyXF User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5437 Hello to all, I am a beginner in using vhdl. I want to convert a signal boolean to std_logic. How could I achieve this? I am using these libraries: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Thanks in advance From newsfish@newsfish Fri Feb 3 13:15:51 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!usenet-fr.net!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!s26g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: convert boolean to std_logic Date: Sat, 17 Dec 2011 07:56:16 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: <9a342b5e-8c33-498e-84b8-907be4252f49@s26g2000yqd.googlegroups.com> References: <3358eb5d-5db4-4286-afb2-6db01fa2113f@z17g2000vbe.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324137821 30106 127.0.0.1 (17 Dec 2011 16:03:41 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 17 Dec 2011 16:03:41 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s26g2000yqd.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5438 On Dec 17, 8:56=A0am, manolis kaliorakis wrote: > Hello to all, > > I am a beginner in using vhdl. I want to convert a signal boolean to > std_logic. How could I achieve this? > I am using these libraries: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; KJ note: Do not use the following libraries, use ieee.numeric_std instead > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > You have to create your own function...here it is function To_Std_Logic(L: BOOLEAN) return std_ulogic is begin if L then return('1'); else return('0'); end if; end function To_Std_Logic; Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:52 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!da3g2000vbb.googlegroups.com!not-for-mail From: manolis kaliorakis Newsgroups: comp.lang.vhdl Subject: Re: convert boolean to std_logic Date: Sat, 17 Dec 2011 09:58:39 -0800 (PST) Organization: http://groups.google.com Lines: 33 Message-ID: <4c692341-6bce-48ed-b9f0-105e705e973e@da3g2000vbb.googlegroups.com> References: <3358eb5d-5db4-4286-afb2-6db01fa2113f@z17g2000vbe.googlegroups.com> <9a342b5e-8c33-498e-84b8-907be4252f49@s26g2000yqd.googlegroups.com> NNTP-Posting-Host: 85.75.67.208 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324144720 3028 127.0.0.1 (17 Dec 2011 17:58:40 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sat, 17 Dec 2011 17:58:40 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: da3g2000vbb.googlegroups.com; posting-host=85.75.67.208; posting-account=_qX70QoAAADxBlFMFCOH_IKGym5fgyXF User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5439 On Dec 17, 5:56=A0pm, KJ wrote: > On Dec 17, 8:56=A0am, manolis kaliorakis > wrote: > > > Hello to all, > > > I am a beginner in using vhdl. I want to convert a signal boolean to > > std_logic. How could I achieve this? > > I am using these libraries: > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > KJ note: =A0Do not use the following libraries, use ieee.numeric_std > instead > > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > k > You have to create your own function...here it is > > =A0 =A0 function To_Std_Logic(L: BOOLEAN) return std_ulogic is > =A0 =A0 begin > =A0 =A0 =A0 =A0 if L then > =A0 =A0 =A0 =A0 =A0 =A0 return('1'); > =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 return('0'); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 end function To_Std_Logic; > > Kevin Jennings Thanks for your response.It was very helpfull From newsfish@newsfish Fri Feb 3 13:15:52 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!border3.nntp.ams.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!d10g2000vbk.googlegroups.com!not-for-mail From: fofo Newsgroups: comp.lang.vhdl Subject: A gray counter Date: Mon, 19 Dec 2011 02:25:25 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <193b0cf1-d1e1-4f94-b38e-390105be23dc@d10g2000vbk.googlegroups.com> NNTP-Posting-Host: 134.158.98.29 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1324290325 24366 127.0.0.1 (19 Dec 2011 10:25:25 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 19 Dec 2011 10:25:25 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d10g2000vbk.googlegroups.com; posting-host=134.158.98.29; posting-account=GQvePwoAAACe5_0QjXQVygMoFepQWj6c User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5440 Hello, I'm trying to write a gray counter 4 bits code and what I'm doing is counting in binary then arranging in gray ^ ^! This idea, could it be synthesized and how to think physically when writing HDL codes? then how to check my code for syntax errors??? Thanks a lot From newsfish@newsfish Fri Feb 3 13:15:53 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!o14g2000vbo.googlegroups.com!not-for-mail From: MBodnar Newsgroups: comp.lang.vhdl Subject: Re: Can a vhdl function return a range? Date: Mon, 19 Dec 2011 04:43:34 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: References: <9574639a-88a0-4e65-a119-259e7334c99a@da3g2000vbb.googlegroups.com> NNTP-Posting-Host: 4.59.139.131 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324298614 11910 127.0.0.1 (19 Dec 2011 12:43:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 19 Dec 2011 12:43:34 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: o14g2000vbo.googlegroups.com; posting-host=4.59.139.131; posting-account=er1mVAoAAACeGcBwCiEuZAmH5XJGQKa5 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5441 On Dec 16, 2:30=A0pm, KJ wrote: > On Dec 16, 1:53=A0pm, mksuth wrote: > > > I'd like to use a function to compute the 'X downto Y' range of a > > vector. Is there a clean way of doing this? > > > -- something like this would be nice: > > function get_slice(n : natural) return range is > > begin > > =A0 =A0return (n+1)*4 downto n*4; > > end function > > > -- so I can use it on an slv like this: > > a <=3D b(get_slice(2)); > > No you can't return a range. =A0However you could instead send the > vector and the selection into get_slice to have it return the vector > slice. > > function get_slice(v: std_logic_vector; n : natural) return > std_logic_vector is > begin > =A0 =A0return v((n+1)*4 downto n*4); > end function > > -- so you can use it on an slv like this: > a <=3D get_slice(b, 2); > > The difference between the two approaches on the usage are basically > cosmetic. > > Kevin Jennings I don't have a compiler in front of me, but I wonder if this would be YACDA (yet another cosmetically-different approach): function get_range(n : natural) return std_logic_vector is variable v : std_logic_vector((n+1)*4 downto n*4)) :=3D (others =3D> '0'); begin return v; end function -- usage a <=3D b(get_range(2)'range); I like this less than KJ's approach (especially because his get_slice takes in the aggregate vector, clearly expressing intent), but I thought I'd still pose it for discussion. MB From newsfish@newsfish Fri Feb 3 13:15:53 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news2.arglkargh.de!news.glorb.com!postnews.google.com!d10g2000vbh.googlegroups.com!not-for-mail From: mksuth Newsgroups: comp.lang.vhdl Subject: Re: Can a vhdl function return a range? Date: Mon, 19 Dec 2011 07:18:46 -0800 (PST) Organization: http://groups.google.com Lines: 11 Message-ID: <2e1754ef-9e33-42b9-b07f-9196a60de7e7@d10g2000vbh.googlegroups.com> References: <9574639a-88a0-4e65-a119-259e7334c99a@da3g2000vbb.googlegroups.com> NNTP-Posting-Host: 67.62.51.170 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1324308033 11168 127.0.0.1 (19 Dec 2011 15:20:33 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 19 Dec 2011 15:20:33 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d10g2000vbh.googlegroups.com; posting-host=67.62.51.170; posting-account=Q0yMNQoAAACGirFDx4sD_uQ3VcH3lbSY User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/535.7 (KHTML, like Gecko) Chrome/16.0.912.63 Safari/535.7,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5442 Thanks for the replies. KJ's solution works great provided you're using it on the RHS of the assignment (as in my original example), but it doesn't work on the LHS of an assignment: get_slice(a,2) <= b; -- will not compile MB's solution on the other hand will work for both the LHS and RHS of an assignment. From newsfish@newsfish Fri Feb 3 13:15:53 2012 Path: eternal-september.org!mx04.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: A gray counter Date: Mon, 19 Dec 2011 11:42:16 -0500 Organization: Alacron, Inc. Lines: 26 Message-ID: References: <193b0cf1-d1e1-4f94-b38e-390105be23dc@d10g2000vbk.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 19 Dec 2011 16:43:25 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="4110"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19fLGox0gm+cNXypPMwh39z" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <193b0cf1-d1e1-4f94-b38e-390105be23dc@d10g2000vbk.googlegroups.com> Cancel-Lock: sha1:TN62dDo0ahOSl1l5mIhuOirbjig= Xref: mx04.eternal-september.org comp.lang.vhdl:5443 fofo wrote: > Hello, > > I'm trying to write a gray counter 4 bits code and what I'm doing is > counting in binary then arranging in gray ^ ^! > This idea, could it be synthesized and how to think physically when > writing HDL codes? then how to check my code for syntax errors??? > > Thanks a lot The main reason to use a Gray code counter is to make sure only one output changes at a time for ease of crossing clock-domains. If you have a standard synchronous binary counter and convert its outputs into Gray code, you don't really have what you want because there will be decoding glitches on the Gray coded outputs. So the first thing you need to realize for synthesis is that you want to preform the binary to Gray conversion on the "next" binary count state and then register the Gray converted signals in the same clock domain as the binary count. This is pretty common technique for building dual-clocked FIFO's, so you might want to look for FIFO code for examples. -- Gabor From newsfish@newsfish Fri Feb 3 13:15:54 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!b32g2000yqn.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Can a vhdl function return a range? Date: Mon, 19 Dec 2011 12:04:23 -0800 (PST) Organization: http://groups.google.com Lines: 23 Message-ID: <35953d45-cdd2-4715-99ef-af27ad151fcb@b32g2000yqn.googlegroups.com> References: <9574639a-88a0-4e65-a119-259e7334c99a@da3g2000vbb.googlegroups.com> <2e1754ef-9e33-42b9-b07f-9196a60de7e7@d10g2000vbh.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324325071 23753 127.0.0.1 (19 Dec 2011 20:04:31 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 19 Dec 2011 20:04:31 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: b32g2000yqn.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5444 On Dec 19, 10:18=A0am, mksuth wrote: > Thanks for the replies. > > KJ's solution works great provided you're using it on the RHS of the > assignment (as in my original example), but it doesn't work on the LHS > of an assignment: > > get_slice(a,2) <=3D b; -- will not compile > > MB's solution on the other hand will work for both the LHS and RHS of > an assignment. The slice on the left hand side will be useful only under the following conditions: - The slice selection is constant (like in your example, it is '2') - You use this inside a process Otherwise you'll find that other drivers of the signal (i.e. the other assignment statements that assign the other bits of the vector) will cause you problems...in particular, synthesis will fail for having multiple drivers. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:54 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!d10g2000vbk.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Can a vhdl function return a range? Date: Tue, 20 Dec 2011 01:21:20 -0800 (PST) Organization: http://groups.google.com Lines: 20 Message-ID: <08ed8f52-4b89-4558-b4e9-0d64c31728e2@d10g2000vbk.googlegroups.com> References: <9574639a-88a0-4e65-a119-259e7334c99a@da3g2000vbb.googlegroups.com> <2e1754ef-9e33-42b9-b07f-9196a60de7e7@d10g2000vbh.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324372968 26214 127.0.0.1 (20 Dec 2011 09:22:48 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 20 Dec 2011 09:22:48 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: d10g2000vbk.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:8.0) Gecko/20100101 Firefox/8.0,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5445 On Dec 19, 3:18=A0pm, mksuth wrote: > Thanks for the replies. > > KJ's solution works great provided you're using it on the RHS of the > assignment (as in my original example), but it doesn't work on the LHS > of an assignment: > > get_slice(a,2) <=3D b; -- will not compile > > MB's solution on the other hand will work for both the LHS and RHS of > an assignment. You cant do this, because functions return a constant and not a signal. So the returned value has no reference back to "a". In this case, you would have to do this: a( get_slice(a,2)'range ) <=3D b; It works the other way around because you can assign a constant to a signal. From newsfish@newsfish Fri Feb 3 13:15:55 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!n22g2000prh.googlegroups.com!not-for-mail From: Sili con Newsgroups: comp.lang.vhdl Subject: Mobile Applications Conference Bangalore on 15-October Date: Wed, 21 Dec 2011 20:28:24 -0800 (PST) Organization: http://groups.google.com Lines: 41 Message-ID: <9a93483e-d355-4e4f-b6d2-4e0f284fb4e1@n22g2000prh.googlegroups.com> NNTP-Posting-Host: 119.226.228.157 Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324528199 20899 127.0.0.1 (22 Dec 2011 04:29:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 22 Dec 2011 04:29:59 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n22g2000prh.googlegroups.com; posting-host=119.226.228.157; posting-account=yp-rVgoAAAD2P2pD-x4Rfb-5YktBj6ko User-Agent: G2/1.0 X-HTTP-Via: 1.1 mail.thesmarttechie.com:8090 (squid/2.6.STABLE9) X-Google-Web-Client: true X-Google-Header-Order: HUALESRCVF X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.12) Gecko/20101026 Firefox/3.6.12,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5446 Hi, I got to know of an exciting event happening in Bangalore on Jan 21st. I guess Mobile World India 2012 comes with the exciting keynote sessions on =91How Operators will meet the Future Traffic Demand=92, =91Wha= t Makes a mobile application successful=92 and =91The Future of Mobile Technology . I believe it is worth attending as there are interesting topics. (See the Sessions below). When: January 21, 2012 (Saturday) Where: NIMHANS Convention Centre, Hosur Road, Near Diary Circle, Bangalore. Time: 8.30AM to 5.50PM The Conference organizers will call you back to confirm. When I called, they had 300 more seats left. Please find below is the url to go through the website http://tinyurl.com/mobilewb Thanks, Raj Sessions on: Digital Marketing: Innovative strategy , Social Media Marketing Strategy, Strategic Marketing - The Need of the Hour, Mobile Marketing: True Mobile Strategy, Role of marketing mix in digital era, Effective Mobile Marketing: Reach to mass community. From newsfish@newsfish Fri Feb 3 13:15:55 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed1.swip.net!newsfeed2.funet.fi!newsfeeds.funet.fi!news.cc.tut.fi!not-for-mail From: Anssi Saari Newsgroups: comp.lang.vhdl Subject: Re: Version control for VHDL projects. Date: Thu, 22 Dec 2011 19:16:59 +0200 Lines: 9 Message-ID: References: <5a3b818e-0b9e-41b1-b6a1-30158b890245@y17g2000yqd.googlegroups.com> <29e07c8a-7c27-4115-9b79-cb0a314780f2@k13g2000yqe.googlegroups.com> <134e9906-bcdb-4f02-9f83-b5289621010c@z11g2000yqz.googlegroups.com> <534c13eb-e4d0-4f6d-b8b2-668fad9bb46a@q23g2000yqd.googlegroups.com> NNTP-Posting-Host: 2001:708:310:3430:216:35ff:fe3e:dee7 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: news.cc.tut.fi 1324574219 14799 2001:708:310:3430:216:35ff:fe3e:dee7 (22 Dec 2011 17:16:59 GMT) X-Complaints-To: abuse@tut.fi NNTP-Posting-Date: Thu, 22 Dec 2011 17:16:59 +0000 (UTC) User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) Cancel-Lock: sha1:hPXmo6TTK6ScL8s85bcNTX++YJA= Xref: mx04.eternal-september.org comp.lang.vhdl:5447 KJ writes: > Interestingly enough, it seems there might be movement afoot to > address this limitation when version SVN 1.7.0 comes out based on the > following thread...or maybe I'm just hoping... > http://groups.google.com/group/tortoisesvn/browse_frm/thread/0337cb91d0eedef8?hl=en# Old thread, but now that svn 1.7.0 has been out a while, I take it this issue with tagging externals was indeed addressed in svn? From newsfish@newsfish Fri Feb 3 13:15:56 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.bbs-scene.org!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!f33g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Version control for VHDL projects. Date: Thu, 22 Dec 2011 11:46:21 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <3c1fe0ba-f2a1-490e-82d2-651168987b1d@f33g2000yqh.googlegroups.com> References: <5a3b818e-0b9e-41b1-b6a1-30158b890245@y17g2000yqd.googlegroups.com> <29e07c8a-7c27-4115-9b79-cb0a314780f2@k13g2000yqe.googlegroups.com> <134e9906-bcdb-4f02-9f83-b5289621010c@z11g2000yqz.googlegroups.com> <534c13eb-e4d0-4f6d-b8b2-668fad9bb46a@q23g2000yqd.googlegroups.com> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1324583181 29855 127.0.0.1 (22 Dec 2011 19:46:21 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 22 Dec 2011 19:46:21 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: f33g2000yqh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB6.5; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5448 On Dec 22, 12:16=A0pm, Anssi Saari wrote: > KJ writes: > > Interestingly enough, it seems there might be movement afoot to > > address this limitation when version SVN 1.7.0 comes out based on the > > following thread...or maybe I'm just hoping... > >http://groups.google.com/group/tortoisesvn/browse_frm/thread/0337cb91... > > Old thread, but now that svn 1.7.0 has been out a while, I take it this > issue with tagging externals was indeed addressed in svn? The TortoiseSVN folks appear to have implemented this, but it looks like there was some problem with what was implemented in version 1.7.0 (http://groups.google.com/group/tortoisesvn/browse_frm/thread/ 2e177939eb4a5b77?hl=3Den#) They are currently up to version 1.7.3 which fixes "some nasty bugs in TortoiseSVN 1.7.2 which in some specific situations could make it crash" (http://groups.google.com/group/tortoisesvn/browse_frm/thread/ b98f1e75307fbc35/208835526c8bc206?hl=3Den&lnk=3Dgst&q=3Dtortoisesvn +1.7+released#208835526c8bc206) It is still on my 'to do' list to see how well the new feature actually works. I like TortoiseSVN, but this limitation with externals was frustrating...and the Perl script method didn't work for me on some computers. Hopefully TortoiseSVN has this working now. Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:56 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: ralvarexo@googlemail.com Newsgroups: comp.lang.vhdl Subject: concurrent signal assignment: order can matter? Date: Wed, 28 Dec 2011 12:27:22 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 77.209.248.119 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1325104043 9907 127.0.0.1 (28 Dec 2011 20:27:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 28 Dec 2011 20:27:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=77.209.248.119; posting-account=xYelzAoAAABIfC5crnu9ZaMNbxR4ZFh_ User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5449 Hi, until now I thought that with concurrent statements order does not matter. = Then I wanted to demonstrate delta delay effects with several versions of a= n RS-FF. However, the simulator I use (Active HDL 8.3) produces different results fo= r the following 3 versions: concurrent_1: qni <=3D not (s and qi); qi <=3D not (r and qni); =20 concurrent_1: qi <=3D not (r and qni);=20 qni <=3D not (s and qi); concurrent_3_with_process: process(s,qi) begin qni <=3D not (s and qi); end process; =20 process(r, qni) begin qi <=3D not (r and qni); =20 end process;=20 I would have expected that all 3 versions fail when r and s are simultaneou= sly change from 0 to 1. However, only the 3rd fails as expected, the other 2 are simulated without = any warning, but different result - order matters! I was under the impression that a concurrent assignment is a short hand for= a process with the same assigment AND all righthand signals in the sensiti= vity list. But according to the results it looks as if the assignments are = evaluated/updated only once, i.e. no implied sensitivity list. While all 3 variants will produce the same HW during synthesis they behave = in a different way during simulation. What is even more disturbing is that = the order of concurrent statemenst matters during simulation, IMO negating = the concept of delta delays. I am aware that the resulting HW will likely show some other behaviour (met= astability) depending on the actual elements used, but this example was cho= osen to show the inner workings of the simulator. Is this behaviour of the simulator in accordance with the standard? Greetings, Mike From newsfish@newsfish Fri Feb 3 13:15:57 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!tudelft.nl!txtfeed1.tudelft.nl!feeder3.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!n39g2000yqh.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: concurrent signal assignment: order can matter? Date: Thu, 29 Dec 2011 13:24:37 -0800 (PST) Organization: http://groups.google.com Lines: 78 Message-ID: References: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1325193877 17543 127.0.0.1 (29 Dec 2011 21:24:37 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 29 Dec 2011 21:24:37 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: n39g2000yqh.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.2; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5450 On Dec 28, 3:27=A0pm, ralvar...@googlemail.com wrote: > While all 3 variants will produce the same HW during synthesis they behav= e in a different way during simulation. What is even more disturbing is tha= t the order of concurrent statemenst matters during simulation, IMO negatin= g the concept of delta delays. > > I am aware that the resulting HW will likely show some other behaviour (m= etastability) depending on the actual elements used, but this example was c= hoosen to show the inner workings of the simulator. > > Is this behaviour of the simulator in accordance with the standard? > You might want to check that your simulator isn't reporting something after all. What I get when running your example on Modelsim is an infinite loop when R and S switch simultaneously. Below, I've also posted the full code. Kevin Jennings # Loading std.standard # Loading ieee.std_logic_1164(body) # Loading work.foo_sig_assignment(rtl) # ** Error: (vsim-3601) Iteration limit reached at time 1 ns. --- Start of code --- library ieee; use ieee.std_logic_1164.all; entity foo_sig_assignment is end foo_sig_assignment; architecture RTL of foo_sig_assignment is begin concurrent_1: block signal r: std_logic; signal s: std_logic; signal qi: std_logic; signal qni: std_logic; begin r <=3D '0', '1' after 1 ns; s <=3D '0', '1' after 1 ns; qni <=3D not (s and qi); qi <=3D not (r and qni); end block concurrent_1; concurrent_2: block signal r: std_logic; signal s: std_logic; signal qi: std_logic; signal qni: std_logic; begin r <=3D '0', '1' after 1 ns; s <=3D '0', '1' after 1 ns; qi <=3D not (r and qni); qni <=3D not (s and qi); end block concurrent_2; concurrent_3_with_process: block signal r: std_logic; signal s: std_logic; signal qi: std_logic; signal qni: std_logic; begin r <=3D '0', '1' after 1 ns; s <=3D '0', '1' after 1 ns; process(s,qi) begin qni <=3D not (s and qi); end process; process(r, qni) begin qi <=3D not (r and qni); end process; end block concurrent_3_with_process; end RTL; --- End of code --- From newsfish@newsfish Fri Feb 3 13:15:57 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news-transit.tcx.org.uk!rt.uk.eu.org!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4efdcaae$0$6871$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: concurrent signal assignment: order can matter? Newsgroups: comp.lang.vhdl Date: Fri, 30 Dec 2011 15:29:01 +0100 References: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 85 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1325255342 news2.news.xs4all.nl 6871 puiterl/195.242.97.150:40087 Xref: mx04.eternal-september.org comp.lang.vhdl:5451 ralvarexo@googlemail.com wrote: > Hi, > > until now I thought that with concurrent statements order does not matter. Your thoughts are correct. > Then I wanted to demonstrate delta delay effects with several versions of > an RS-FF. However, the simulator I use (Active HDL 8.3) produces different > results for the following 3 versions: > > concurrent_1: > qni <= not (s and qi); > qi <= not (r and qni); > > concurrent_1: > qi <= not (r and qni); > qni <= not (s and qi); > > concurrent_3_with_process: > process(s,qi) > begin > qni <= not (s and qi); > end process; > > process(r, qni) > begin > qi <= not (r and qni); > end process; Then Active HDL 8.3 is in error. > I would have expected that all 3 versions fail when r and s are > simultaneously change from 0 to 1. However, only the 3rd fails as > expected, the other 2 are simulated without any warning, but different > result - order matters! What exactly are the results? > I was under the impression that a concurrent assignment is a short hand > for a process with the same assigment AND all righthand signals in the > sensitivity list. That is correct. > But according to the results it looks as if the > assignments are evaluated/updated only once, i.e. no implied sensitivity > list. > > While all 3 variants will produce the same HW during synthesis they behave > in a different way during simulation. What is even more disturbing is that > the order of concurrent statemenst matters during simulation, IMO negating > the concept of delta delays. > > I am aware that the resulting HW will likely show some other behaviour > (metastability) depending on the actual elements used, but this example > was choosen to show the inner workings of the simulator. > > Is this behaviour of the simulator in accordance with the standard? As said before: no. What I would expect is an error message like Kevin already has shown is produced by ModelSim: "Iteration limit reached". It is same situation as this concurrent signal assignment, providing the value of s is not unknown: s <= not s; The value of s toggles every delta cycle, without any progression in "real" time. Things change if you add an "after" clause: s <= not s after 1 ns; Then you can observe the resulting wave form. You can do the same in your original code and observe the resulting wave forms. They should be identical in all three cases. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:15:57 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder1.enfer-du-nord.net!newsfeed.eweka.nl!feeder3.eweka.nl!81.171.88.15.MISMATCH!eweka.nl!lightspeed.eweka.nl!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Michael Hermann Newsgroups: comp.lang.vhdl Subject: Re: concurrent signal assignment: order can matter? Date: Fri, 30 Dec 2011 08:11:10 -0800 (PST) Organization: http://groups.google.com Lines: 82 Message-ID: <3689600.780.1325261470994.JavaMail.geo-discussion-forums@vbdz6> References: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 62.87.110.186 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1325265060 26902 127.0.0.1 (30 Dec 2011 17:11:00 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Dec 2011 17:11:00 +0000 (UTC) In-Reply-To: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.87.110.186; posting-account=xYelzAoAAABIfC5crnu9ZaMNbxR4ZFh_ User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5452 Hi Kevin and Paul, thanks for confirming my thoughts. I tried Kevins code and my simulator also barfed on all 3 versions - as expected. So the good news is that concurrent IS concurrent. Of course I now tried to find out why my experiment failed. It took quite a while but now I have hopefully narrowed it down to a more or less minimalistic version. (As a side note: I wanted NOT to use the example a <= not a; because everybody believes in oscillation problems here, independet of delta cycles or not). Well, now it looks like for HDL 8.3 there is a difference in the one-file version and the more traditional separation in testbench and unit under test. The one file minimalistic version fails (which is OK): --- library ieee; use ieee.std_logic_1164.all; entity rsff_tb is end rsff_tb; architecture tb of rsff_tb is signal i : std_logic; signal q : std_logic; signal qi, qni: std_logic; begin qi <= i nand qni; qni <= i nand qi; q <= qi; i <= '0', '1' after 1ns; end tb; --- The two file version does NOT fail in HDL 8.3! --- test bench (first file) library ieee; use ieee.std_logic_1164.all; entity rsff_tb is end rsff_tb; architecture tb of rsff_tb is signal i : std_logic; signal q : std_logic; begin UUT: entity rsff port map (i => i, q => q); i <= '0', '1' after 1ns; end tb; --- --- unit under test (second file) library ieee; use ieee.std_logic_1164.all; entity rsff is port ( i: in std_logic; q: out std_logic ); end; architecture fail of rsff is signal qi, qni: std_logic; begin --process(i,qni,qi) --begin qi <= i nand qni; qni <= i nand qi; --end process; q <= qi; end; --- If I wrap the signal assignments in the UUT again by the process (comments), then the two-file version fails again, i.e. shows the expected behaviour. Strange! Up to a better explanation I have to believe HDL 8.3 is incorrect here. Mike From newsfish@newsfish Fri Feb 3 13:15:58 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!newsfeed.eweka.nl!feeder3.eweka.nl!81.171.88.15.MISMATCH!eweka.nl!lightspeed.eweka.nl!postnews.google.com!p13g2000yqd.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: concurrent signal assignment: order can matter? Date: Fri, 30 Dec 2011 11:54:29 -0800 (PST) Organization: http://groups.google.com Lines: 63 Message-ID: <9a091cfd-0578-4258-8fa1-7f8d6997560c@p13g2000yqd.googlegroups.com> References: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> <3689600.780.1325261470994.JavaMail.geo-discussion-forums@vbdz6> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1325274889 29835 127.0.0.1 (30 Dec 2011 19:54:49 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Dec 2011 19:54:49 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p13g2000yqd.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.2; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5453 On Dec 30, 11:11=A0am, Michael Hermann wrote: > Hi Kevin and Paul, > The two file version does NOT fail in HDL 8.3! > > --- test bench (first file) Seems to me the test bench should be the second file, not the first. Inside the architecture you instantiate the entity 'raff' which hasn't been compiled yet if you have a completely empty work library. That is likely not contributing to your particular probllem, just a comment. Modelsim also had the following complaints when compiling your code 'as-is' (other than swapping the order so that 'raff' is compiled first. ** Error: C:/Sim/Junk/Junk3.vhd(111): Unknown entity 'rsff'. Use expanded name. ** Warning: [4] C:/Sim/Junk/Junk3.vhd(112): (vcom-1207) An abstract literal and an identifier must have a separator between them. The error has to do with the following line of code UUT: entity rsff port map (i =3D> i, q =3D> q); which should be UUT: entity work.rsff port map (i =3D> i, q =3D> q); The warning is to the following line of code i <=3D '0', '1' after 1ns; which should be i <=3D '0', '1' after 1 ns; Again, these most likely have nothing to do with your problem, so this is just a comment but I believe in both cases Modelsim is correct to the LRM which would mean that Active HDL 8.3 is not correctly reporting non-compliant stuff that it should (unless you are disabling or otherwise ignoring these complaints). > > If I wrap the signal assignments in the UUT again by the process (comment= s), then the two-file version fails again, i.e. shows the expected behaviou= r. > I'm still not clear just what you mean by 'expected behaviour'. What I would expect for any model of an RS flip flop is an infinite loop and the simulator to stop if 'R' and 'S' are set at exactly the same time. I'm not sure if that's what you expect or not, but that would be the correct 'response' in this situation. In any case, when running the code you posted (both forms with and without the process) Modelsim does stop with an infinite loop reporting the following error: ** Error: (vsim-3601) Iteration limit reached at time 1 ns. > Strange! Up to a better explanation I have to believe HDL 8.3 is incorrec= t here. > The fact that you are getting different end results would indicate that Active HDL is not correct in one case. Does Active HDL ever report an infinite loop and stop for you? Kevin Jennings From newsfish@newsfish Fri Feb 3 13:15:58 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed.kamp.net!nx02.iad01.newshosting.com!newshosting.com!news-out.readnews.com!transit3.readnews.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Michael Hermann Newsgroups: comp.lang.vhdl Subject: Re: concurrent signal assignment: order can matter? Date: Fri, 30 Dec 2011 13:13:24 -0800 (PST) Organization: http://groups.google.com Lines: 39 Message-ID: <4292779.1086.1325279604643.JavaMail.geo-discussion-forums@vbyc2> References: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 62.87.72.162 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1325279607 13615 127.0.0.1 (30 Dec 2011 21:13:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 30 Dec 2011 21:13:27 +0000 (UTC) In-Reply-To: <28386304.1112.1325104042930.JavaMail.geo-discussion-forums@vbbdf9> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=62.87.72.162; posting-account=xYelzAoAAABIfC5crnu9ZaMNbxR4ZFh_ User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5454 Hi Kevin, sorry for the confusion: With "first" and "second" I did not want to imply an order, actually I just wanted to separate the two files. Could have said Unit-file and TB-file as well. They are actually compiled in the required order, otherwise it would not work at all. The missing "work" in front of the entity probably works (no pun intended), because the rsff is in the current working library which is just what work indicates. So it is surely cleaner to write work.rsff but I do understand why Active HDL does not complain here. Same for the 1ns. But at least for the 1ns you are still correct, that IF this is wrong according to the LRM then Active HDL should at least issue a warning. It does not. Now for the IMO more interesting stuff: For this particular description of a RSFF and the concept of delta cycles I would expect the oscillation. In fact this is what Active HDL probably sees in the one-file case and also in the two-file case with process(). At least the simulation stops at 1ns because of "delta cycle limit reached" - perfect for me. The reason I'm digging into this is because I want to explain the working of the simulator in a lecture. I planned to show how the concept of delta cycles enables a sequential machine to simulate concurrency in a deterministic way. I also wanted to show some limits. Therefore the RSFF example, because a RSFF is normally a circuit which is quite well-behaved. Correct me if I'm wrong, but in this admittedly constructed case the oscillation is due to a) the specific description b) the delta cycle concept. Since my original experiment failed, revealing a potential problem in Active HDL, I have not progressed to the next step. This would have been to replace the two-liner by a one-liner like qi <= s nand (r nand qi); Same result in HW but now I would expect no oscillation during simulation, since the feedback is now calculated in a single cycle and no change of qi is detected after the update phase. Again, this example does not tell anything about the behaviour of the synthesized HW, it shall merely illustrate the kind of problem the delta cycle concept solves and where there are limits. But before I can explain this with some degree of confidence to innocent students I must make sure I understand the topic myself well enough. There I got trapped. For your last question: Yes, as I said I can get Active HDL into the loop and stop with an appropriate kernel message. But not as often as intended, your Modelsim seems right now the better, i.e. more standard compliant simulator! Mike From newsfish@newsfish Fri Feb 3 13:15:59 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!xlned.com!feeder5.xlned.com!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!post.news.xs4all.nl!news.xs4all.nl!not-for-mail Message-Id: <4f01e68d$0$6914$e4fe514c@news2.news.xs4all.nl> From: Paul Uiterlinden Subject: Re: Why isnt buffer used more often? Newsgroups: comp.lang.vhdl Date: Mon, 02 Jan 2012 18:17:00 +0100 References: Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 23 NNTP-Posting-Host: 195.242.97.150 X-Trace: 1325524621 news2.news.xs4all.nl 6914 puiterl/195.242.97.150:47265 Xref: mx04.eternal-september.org comp.lang.vhdl:5455 Tricky wrote: > Is there any reason more people dont use the buffer port type? is > there anything you cant do with it that you can do with an internal > signal? The only reason people started using OUT in stead of BUFFER is because of its name. I would say if the names were reversed, everybody still would have used OUT with the bonus of not having to resort to ugly things a internal signals to be able to read back the value of such a port, let alone using INOUT for that reason. In our company BUFFER has always been the standard for outputs. Never had much trouble with that, except on top level, where foundries insisted on OUT. But that was easy to fix. Now with VHDL-2008, things have relaxed a bit more, so you can even mix BUFFER and OUT. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not. From newsfish@newsfish Fri Feb 3 13:15:59 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!news.glorb.com!postnews.google.com!m20g2000vbf.googlegroups.com!not-for-mail From: Francesco Bonizzi Newsgroups: comp.lang.vhdl Subject: Is this a Ghdl/gtkwave bug? Date: Fri, 6 Jan 2012 01:33:01 -0800 (PST) Organization: http://groups.google.com Lines: 8 Message-ID: <745e7cd0-93d7-435c-9546-f8974a04e4b2@m20g2000vbf.googlegroups.com> NNTP-Posting-Host: 80.116.92.3 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1325842381 32662 127.0.0.1 (6 Jan 2012 09:33:01 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Jan 2012 09:33:01 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m20g2000vbf.googlegroups.com; posting-host=80.116.92.3; posting-account=SWQjFQoAAADJbdA-SXxqj2CY48vfzMoi User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/535.7 (KHTML, like Gecko) Chrome/16.0.912.63 Safari/535.7,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5456 I'm using ghdl+gtkwave for studying, on Windows 7. I run simulations by calling some shell in a .bat file, usually when I got some sintax error, i see the messagges in dos window, but in some case that I didn't understand, there are no errors but gtkwave doesn't runs. Is this a bug? Can someone help me please? Thanks a lot. From newsfish@newsfish Fri Feb 3 13:16:00 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 09 Jan 2012 22:09:32 -0600 Date: Mon, 09 Jan 2012 21:08:16 -0700 From: Rob Doyle User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: GHDL and Tristate Busses Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Message-ID: Lines: 97 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-3wwuXP6R2y3Rjq0Tm/IYJ+cw4JBWcISC2jKqZ1cuQKf9r0/ROUC8erbpeSpCo+809Lj6pkqxC1ld8XS!p8WFpJZ0qUNckL/vBQx1/F7Wgacq0LPW5tJG0Og5KROiEgaRffAB6WLSzlxkHVSv/0G3zFnc408= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3096 Xref: mx04.eternal-september.org comp.lang.vhdl:5458 Sorry if this is a stupid question... I have a simple tristate bus simulation that I can't make work with GHDL. Attached. It generates the following error: error: invalid memory access (dangling accesses or stack size too small) error: simulation failed I've tried increasing the stack size but it still fails. It seems to work with the Xilinx Webpack.... Any clues? $ ghdl --version GHDL 0.29.1 (20100301) [Sokcho edition] Compiled with GNAT Version: GPL 2009 (20090519) mcode code generator Written by Tristan Gingold. Copyright (C) 2003 - 2010 Tristan Gingold. GHDL is free software, covered by the GNU General Public License. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Rob. ------------ begin test_asdf.vhd --------------- library ieee; use ieee.std_logic_1164.all; entity test_asdf is end test_asdf; architecture behav of test_asdf is signal clk : std_logic := '0'; signal rst : std_logic; signal data : std_logic; signal dir : std_logic; begin uut : entity work.asdf (rtl) port map ( clk => clk, rst => rst, data => data, dir => dir ); process begin wait for 10 ns; clk <= not(clk); end process; rst <= '1', '0' after 80 ns; data <= '0' when dir = '0' else 'Z'; end behav; -------------- end test_asdf.vhd -------- ------------- start asdf.vhd -------------- library ieee; use ieee.std_logic_1164.all; entity asdf is port ( clk : in std_logic; rst : in std_logic; data : inout std_logic; dir : out std_logic); end asdf; architecture rtl of asdf is signal toggle : std_logic; begin process(clk, rst) begin if rst = '1' then toggle <= '0'; elsif rising_edge(clk) then toggle <= not(toggle); end if; end process; data <= '1' when toggle = '1' else 'Z'; dir <= toggle; end rtl; -------------- end asdf.vhd ----------------- From newsfish@newsfish Fri Feb 3 13:16:00 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!news.internetdienste.de!news.tu-darmstadt.de!news.belwue.de!rz.uni-karlsruhe.de!inka.de!chekov.starfleet.inka.de!.POSTED!not-for-mail From: Enrik Berkhan Newsgroups: comp.lang.vhdl Subject: Re: GHDL and Tristate Busses Date: Tue, 10 Jan 2012 08:07:57 +0000 (UTC) Organization: void Lines: 27 Message-ID: References: NNTP-Posting-Host: chekov.starfleet.local X-Trace: chekov.starfleet.local 1326182877 912 192.168.128.1 (10 Jan 2012 08:07:57 GMT) X-Complaints-To: usenet@starfleet.inka.de NNTP-Posting-Date: Tue, 10 Jan 2012 08:07:57 +0000 (UTC) User-Agent: tin/2.0.0-20110623 ("Burnside") (UNIX) (Linux/3.0.0-14-generic (x86_64)) Xref: mx04.eternal-september.org comp.lang.vhdl:5459 Hi, Rob Doyle wrote: > I have a simple tristate bus simulation that I can't make work with > GHDL. Attached. > > It generates the following error: > > error: invalid memory access (dangling accesses or stack size too small) > error: simulation failed > > I've tried increasing the stack size but it still fails. > > It seems to work with the Xilinx Webpack.... > > Any clues? Your testbench will run for ever. Looks like your GHDL version leaks memory in this case or something. Either make the clock stop after some time or tell ghdl to stop after some time like this: $ ./test_asdf --stop-time=1us On my system (Debian 6.0.3 x86_64, GHDL 0.29 from the distribution), your code runs without a growing process. Modelsim is happy, too. Enrik From newsfish@newsfish Fri Feb 3 13:16:00 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!news1.google.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Tue, 10 Jan 2012 11:07:41 -0600 Message-ID: <4F0C7012.1050407@gmail.com> Date: Tue, 10 Jan 2012 10:06:26 -0700 From: Rob Doyle User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl To: Enrik Berkhan Subject: Re: GHDL and Tristate Busses References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 38 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-LKRlXs1ctjIWxe81Dyh8AZyjW2l9T5vO3zbrWZkRlChqMH5tQFaTvcnmSbQjqGXCNdQBW75AmSK1iCj!BOOFrfNZg4oZBc1uE5dylREgi2XnuT2YHTo9djHzGSoGIiEv8Q== X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2223 Xref: mx04.eternal-september.org comp.lang.vhdl:5460 On 1/10/2012 1:07 AM, Enrik Berkhan wrote: > Hi, > > Rob Doyle wrote: >> I have a simple tristate bus simulation that I can't make work with >> GHDL. Attached. >> >> It generates the following error: >> >> error: invalid memory access (dangling accesses or stack size too small) >> error: simulation failed >> >> I've tried increasing the stack size but it still fails. >> >> It seems to work with the Xilinx Webpack.... >> >> Any clues? > > Your testbench will run for ever. Looks like your GHDL version leaks > memory in this case or something. Either make the clock stop after some > time or tell ghdl to stop after some time like this: > > $ ./test_asdf --stop-time=1us > > On my system (Debian 6.0.3 x86_64, GHDL 0.29 from the distribution), your code > runs without a growing process. Modelsim is happy, too. > > Enrik That's a clue. I tried to stop it as you suggest and it gives the same error message. Maybe something is broken in the windoze version... Rob. From newsfish@newsfish Fri Feb 3 13:16:01 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!w4g2000vbc.googlegroups.com!not-for-mail From: Brian Davis Newsgroups: comp.lang.vhdl Subject: Re: GHDL and Tristate Busses Date: Tue, 10 Jan 2012 16:47:03 -0800 (PST) Organization: http://groups.google.com Lines: 27 Message-ID: <8825dc4f-bbbb-47da-b206-c73ae8110b27@w4g2000vbc.googlegroups.com> References: NNTP-Posting-Host: 72.64.4.151 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1326242823 6846 127.0.0.1 (11 Jan 2012 00:47:03 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 11 Jan 2012 00:47:03 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: w4g2000vbc.googlegroups.com; posting-host=72.64.4.151; posting-account=lnHhkgkAAABF41pHRI0fD7i5XBxJ4xSp User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:9.0.1) Gecko/20100101 Firefox/9.0.1,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5461 Rob Doyle wrote: > > I have a simple tristate bus simulation that I can't make work with > GHDL. =A0Attached. > error: invalid memory access (dangling accesses or stack size too small) > These tristate crashes are a known issue with Windows versions of GHDL later than 0.25 Version 0.25 does _not_ have this issue: http://ghdl.free.fr/ghdl-installer-0.25.exe Or, a handy bundle of GHDL 0.25 + GTKwave with win installer: http://sourceforge.net/projects/fpgalibre/files/GHDL/0.25_Windows/ghdl-0.= 25.msi/download Building the latest 0.29.1 GHDL sources with a stack alignment of 16 makes this crash go away, but I never figured out why. see also: https://mail.gna.org/public/ghdl-discuss/2011-08/msg00007.html https://mail.gna.org/public/ghdl-discuss/2011-03/msg00023.html https://mail.gna.org/public/ghdl-discuss/2011-03/msg00005.html Brian From newsfish@newsfish Fri Feb 3 13:16:01 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!tudelft.nl!txtfeed1.tudelft.nl!feeder2.cambriumusenet.nl!feed.tweaknews.nl!193.201.147.82.MISMATCH!border2.hitnews.com!cyclone03.ams2.highwinds-media.com!news.highwinds-media.com!voer-me.highwinds-media.com!npeersf01.ams.highwinds-media.com!newsfe02.ams2.POSTED!00000000!not-for-mail From: HT-Lab Reply-To: hans64@htminuslab.com User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 Newsgroups: comp.lang.vhdl Subject: Open Source VHDL Verification Methodology Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Antivirus: avast! (VPS 120120-0, 20/01/2012), Outbound message X-Antivirus-Status: Clean Lines: 6 Message-ID: NNTP-Posting-Host: 86.29.13.122 X-Complaints-To: http://netreport.virginmedia.com X-Trace: newsfe02.ams2 1327069126 86.29.13.122 (Fri, 20 Jan 2012 14:18:46 UTC) NNTP-Posting-Date: Fri, 20 Jan 2012 14:18:46 UTC Organization: virginmedia.com Date: Fri, 20 Jan 2012 14:18:49 +0000 Xref: mx04.eternal-september.org comp.lang.vhdl:5462 For those that haven't seen it, http://www.aldec.com/en/solutions/functional_verification/os_vvm Hans www.ht-lab.com From newsfish@newsfish Fri Feb 3 13:16:02 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Oliver Mattos Newsgroups: comp.lang.vhdl Subject: Spartan 6 MPMC - more ports? Date: Fri, 20 Jan 2012 14:05:41 -0800 (PST) Organization: http://groups.google.com Lines: 17 Message-ID: <3953827.44.1327097141350.JavaMail.geo-discussion-forums@vby8> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 129.31.247.62 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1327097264 11955 127.0.0.1 (20 Jan 2012 22:07:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 20 Jan 2012 22:07:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=129.31.247.62; posting-account=BoFZ7woAAAA7wHGZYr2CLL_k1FRcSXFT User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5463 Hi, I have a Spartan 6 project with 7 IP cores wanting VFBC connections to a me= mory controller. My problem is the MPMC configuration tool won't seem to l= et me do that because the MPMC can't be configured to have that many VFBC c= onnections. I'm trying to build a picture-in-picture device for HDMI (6 inputs, 1 outpu= t). Is there a way to "chain" memory controllers to achieve this? Alternative= ly is there a VFBC bus "splitter/arbitrator" to allow me to connect multipl= e VFBC IO cores to a single MPMC port? I am reasonably certain memory band= width will be OK, providing arbitration/buffering is ok. (I am a bit new to Xilinx EDA tools, and am probably a bit off topic for th= is group - please be kind!) From newsfish@newsfish Fri Feb 3 13:16:02 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!t30g2000vbx.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Open Source VHDL Verification Methodology Date: Tue, 24 Jan 2012 04:52:26 -0800 (PST) Organization: http://groups.google.com Lines: 9 Message-ID: <6cf9339a-a913-466d-b95d-731c8669b383@t30g2000vbx.googlegroups.com> References: NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1327409547 27273 127.0.0.1 (24 Jan 2012 12:52:27 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Jan 2012 12:52:27 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: t30g2000vbx.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5464 Hi, I have tried the fifo example with Modelsim, the simulation performs as expected. In my opinion the adoption of coverage definition and collection seems not that easy because there are some complex dependencies. Nevertheless I will give a try in my next own testbench. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:16:02 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: "M. Norton" Newsgroups: comp.lang.vhdl Subject: Sanity check on a weird bit of math and std_logic_unsigned Date: Tue, 24 Jan 2012 08:33:23 -0800 (PST) Organization: http://groups.google.com Lines: 57 Message-ID: <10928718.2186.1327422803192.JavaMail.geo-discussion-forums@vbtr6> Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 4.30.68.10 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1327422803 1942 127.0.0.1 (24 Jan 2012 16:33:23 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 24 Jan 2012 16:33:23 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=4.30.68.10; posting-account=v9UqVgoAAACxPpoiLScISA5bnH5h5YwY User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5465 Hello folks, I'm having to do surgery on something a contractor left us. One small prob= lem was that he took a file with numeric_std already defined and used and t= hen for his own additions added std_logic_unsigned (thanks SO much.) Anyho= w, I am having to carefully evaluate what he's doing so that I don't unnece= ssarily break something that is already working. Not especially well comme= nted either, so I'm having to infer intent from the code as well. So, I run into a bit of code where he's putting in a little filter and I am= having trouble trying to figure out what the hell he was getting at, becau= se as far as I can tell, there's code that will never get executed due to t= he way the math works. [code snippet, encapsulated in ye olde clocked process] if (pulse_event_true =3D '1') then if ((X"08000000" + count - (X"0000 & count(31 downto 16))) < X"08000000"= ) then count <=3D (the above equation); else count <=3D X"08000000"; end if; else count <=3D count - (X"0000 & count(31 downto 16)); end if; [/code] Okay, so when there's a pulse, he adds a constant to the count, and otherwi= se it decays slowly. No trouble there. The problem I've got is that he do= es that bounds check at the beginning to make sure he doesn't exceed 0x0800= 0000 before he does the addition, otherwise he just caps out at 0x08000000.= =20 The part I don't get is that the saturation limit is exactly the same as th= e constant he's adding. By my reasoning, the count value could never excee= d 0x08000000 except as a starting condition, and then we might have somethi= ng large enough that it would wrap around 0xfffffffff and then trigger the = top clause. This is covered by the fact that the count has an asynchronous= reset to 0, and has a synchronous reset to 0 (software controlled elsewher= e). Thus as far as I can tell, this count is going to stay at 0 until a pu= lse comes along, get set to 0x08000000, decay awhile until the next pulse. = When another pulse comes along, there's no mathematical way the current co= unt plus 0x08000000 will ever NOT be greater than or equal to 0x08000000 an= d thus just gets pegged back to the count. It seems to be working adequately by all reports, but it kind of bugs me. = And I'm taking out the std_logic_unsigned crap, so I can pretty easily conv= ert the math to x <=3D x - shift_right(x,8), but there's that damned as-far= -as-I-can-tell-non-executing-code that I have to decide whether to keep or = just simplify to what is happening. Any ideas folks? Am I missing a case whereby C + f(t) is ever < C for all = f(t) being non-negative? Thanks for any responses. Mark From newsfish@newsfish Fri Feb 3 13:16:03 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!m11g2000yqe.googlegroups.com!not-for-mail From: KJ Newsgroups: comp.lang.vhdl Subject: Re: Sanity check on a weird bit of math and std_logic_unsigned Date: Tue, 24 Jan 2012 20:04:23 -0800 (PST) Organization: http://groups.google.com Lines: 189 Message-ID: <1913f5a7-a9c1-4566-b28e-58a0d9643997@m11g2000yqe.googlegroups.com> References: <10928718.2186.1327422803192.JavaMail.geo-discussion-forums@vbtr6> NNTP-Posting-Host: 99.184.242.197 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1327464374 8416 127.0.0.1 (25 Jan 2012 04:06:14 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Jan 2012 04:06:14 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m11g2000yqe.googlegroups.com; posting-host=99.184.242.197; posting-account=TJOePQoAAADr-f6dDt_fMmacSJMCG-pd User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: ARLUEHNKC X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 8.0; Windows NT 5.1; Trident/4.0; GTB7.2; .NET CLR 1.1.4322; .NET CLR 2.0.50727; .NET CLR 3.0.4506.2152; .NET CLR 3.5.30729; InfoPath.3; .NET4.0C),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5466 On Jan 24, 11:33=A0am, "M. Norton" wrote: > Hello folks, > > I'm having to do surgery on something a contractor left us. =A0One small = problem was that he took a file with numeric_std already defined and used a= nd then for his own additions added std_logic_unsigned (thanks SO much.) = =A0Anyhow, I am having to carefully evaluate what he's doing so that I don'= t unnecessarily break something that is already working. =A0Not especially = well commented either, so I'm having to infer intent from the code as well. > While not on the point of your post, let me suggest that a good general check that you haven't broken something is to create a testbench that instances both the original code and your new code, drives all of the inputs to both identically and then add assertions to check that the outputs of both are always the same. You're dependent on the quality of the testbench to make sure that you cover as much of the cases as possible, but that will always be the case anyway. > So, I run into a bit of code where he's putting in a little filter and I = am having trouble trying to figure out what the hell he was getting at, bec= ause as far as I can tell, there's code that will never get executed due to= the way the math works. > > Okay, so when there's a pulse, he adds a constant to the count, and other= wise it decays slowly. =A0No trouble there. =A0The problem I've got is that= he does that bounds check at the beginning to make sure he doesn't exceed = 0x08000000 before he does the addition, otherwise he just caps out at 0x080= 00000. > > The part I don't get is that the saturation limit is exactly the same as = the constant he's adding. =A0By my reasoning, the count value could never e= xceed 0x08000000 except as a starting condition, and then we might have som= ething large enough that it would wrap around 0xfffffffff and then trigger = the top clause. =A0This is covered by the fact that the count has an asynch= ronous reset to 0, and has a synchronous reset to 0 (software controlled el= sewhere). =A0Thus as far as I can tell, this count is going to stay at 0 un= til a pulse comes along, get set to 0x08000000, decay awhile until the next= pulse. =A0When another pulse comes along, there's no mathematical way the = current count plus 0x08000000 will ever NOT be greater than or equal to 0x0= 8000000 and thus just gets pegged back to the count. > I'm not sure what the function of pulse_event_true is supposed to represent, but it is operating as a synchronous reset; when pulse_event_true is '1' then count is set to X"08000000". At first, I didn't exhaustively test the 2^28 different possible starting conditions for count, but I did test four of them (including all bits set to 'U') and in all cases, pulse_event_true set to '1' caused count to be set to X"08000000". Next I synthesized it with Quartus. If the innermost loop is logically useless than it might synthesize away completely and a build with the code 'as is' and one without the innermost 'if' statement ideally should produce the exact same output. If it did then it would prove that the innermost check is useless. Alas, such was not the case. Your original code synthesized to 100+ Altera ALUTs, the code with the 'if' statement removed synthesized to 33 ALUTs. While the same output file would be sufficient to prove the innermost loop useless, getting different results does not prove anything. The next thought was '2^28 isn't *that* big of a number (268+ million) so create a testbench that initializes count to a value, set pulse_event_true to 1 and see if count goes to X"08000000" at the next clock. Repeat for all possible values of count. The code to do all of this is posted below. It looks like it will take ~2 hours to complete. So far it is ~1/3 of the way through and has not hit an assertion. Assuming that it really does complete that will show that the innermost 'if' statement really is useless and can be removed...and based on the synthesis information you will save some logic by getting rid of it. My guess is that the entire inner 'if' statement used to be quite different and evolved into the present form over time. If the contractor archived any earlier builds you might peruse those to see the evolution of that block of code to satisfy your curiousity. At some point though that code took a poor mutation (in fact, it might have only been one mutation that occurred several weeks after not having looked at the code in a while). So now would be a good time for natural selection to takes its turn and wipe out that code. > It seems to be working adequately by all reports, but it kind of bugs me.= =A0And I'm taking out the std_logic_unsigned crap, so I can pretty easily = convert the math to x <=3D x - shift_right(x,8), but there's that damned as= -far-as-I-can-tell-non-executing-code that I have to decide whether to keep= or just simplify to what is happening. > > Any ideas folks? =A0Am I missing a case whereby C + f(t) is ever < C for = all f(t) being non-negative? > Unless there is something about using the non-standard libraries that makes it function differently (but I doubt it) than I would say you should be able to remove it. However, before doing that surgery you should probably run my testbench with the original code modified only with my 'kj_*' input additions and run that sim but I'm confident that it should pass sim as well. In any case, now you have a testbench that exhaustively tests this code snippet which will either run to completion indicating the code is safe to remove or it will stop indicating the precise condition that really does trigger the 'if' statement. And, assuming you archive the bench, you'll have the proof necessary to show that the code was not needed in case there is ever a question about why the code was removed. Kevin Jennings [Start of code] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity count_saturate is port ( kj_rst: in std_ulogic; kj_cnt: in unsigned(31 downto 0); clock: in std_ulogic :=3D '0'; pulse_event_true: in std_ulogic :=3D '0'; count: buffer unsigned(31 downto 0)); end count_saturate; architecture rtl of count_saturate is begin process(clock) begin if rising_edge(clock) then if (kj_rst =3D '1') then count <=3D kj_cnt; else if (pulse_event_true =3D '1') then if ((X"08000000" + count - (X"0000" & count(31 downto 16))) < X"08000000") then count <=3D (X"08000000" + count - (X"0000" & count(31 downto 16))); else count <=3D X"08000000"; end if; else count <=3D count - (X"0000" & count(31 downto 16)); end if; end if; end if; end process; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_count_saturate is end tb_count_saturate; architecture rtl of tb_count_saturate is signal clock: std_ulogic :=3D '0'; signal pulse_event_true: std_ulogic :=3D '0'; signal count: unsigned(31 downto 0); signal sim_complete: std_ulogic :=3D '0'; signal kj_rst: std_ulogic; signal kj_cnt: unsigned(31 downto 0); begin clock <=3D not(clock) and not(sim_complete) after 5 ns; MAIN : process begin for i in 0 to 16#08000000# loop kj_rst <=3D '1'; kj_cnt <=3D to_unsigned(i, kj_cnt'length); pulse_event_true <=3D '0'; wait until falling_edge(clock); assert (count =3D to_unsigned(i, kj_cnt'length)) report "OOPS! Incorrect value for count" severity ERROR; kj_rst <=3D '0'; pulse_event_true <=3D '1'; wait until falling_edge(clock); assert (count =3D X"08000000") report "OOPS! Incorrect value for count" severity ERROR; if i mod 256 =3D 0 then report "Loop #" & integer'image(i); end if; end loop; sim_complete <=3D '1'; wait; end process MAIN; DUT : entity work.count_saturate port map( kj_rst =3D> kj_rst, kj_cnt =3D> kj_cnt, clock =3D> clock, pulse_event_true =3D> pulse_event_true, count =3D> count); end rtl; [End of code] From newsfish@newsfish Fri Feb 3 13:16:03 2012 Path: eternal-september.org!mx04.eternal-september.org!.POSTED!not-for-mail From: valtih1978 Newsgroups: comp.lang.vhdl Subject: Open file path specification Date: Wed, 25 Jan 2012 15:32:02 +0200 Organization: A noiseless patient Spider Lines: 6 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Wed, 25 Jan 2012 13:32:05 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="3XE32DeEtc4VZZTOU4vv0g"; logging-data="28715"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19jwUdPCRv4M10d8RAEskuq8RqPhXctFu8=" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:8.0) Gecko/20111105 Thunderbird/8.0 Cancel-Lock: sha1:XFAOzT6WwBIbpsYbMLS/LuxBvcs= Xref: mx04.eternal-september.org comp.lang.vhdl:5467 In which format the file name should be given? Can it be absolute? When it is relative, it is relative to what? I see that Modelsim has current working dir, whereas Active-HDL looks for files in the project dir, where are the sources. They do not care if file name starts with /root in Windows. From newsfish@newsfish Fri Feb 3 13:16:04 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!i10g2000pbl.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Open Source VHDL Verification Methodology Date: Wed, 25 Jan 2012 12:47:12 -0800 (PST) Organization: http://groups.google.com Lines: 25 Message-ID: References: <6cf9339a-a913-466d-b95d-731c8669b383@t30g2000vbx.googlegroups.com> NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1327524432 7718 127.0.0.1 (25 Jan 2012 20:47:12 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 25 Jan 2012 20:47:12 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i10g2000pbl.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:9.0.1) Gecko/20100101 Firefox/9.0.1,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5468 Also don't miss that there will be a webinar on Thursday Jan 26. Go to: http://www.aldec.com/en/events The presentation examples will be similar to the examples in the user guides for the individual packages. Currently the user guides are only available at: http://www.synthworks.com/downloads @hssig > In my opinion the adoption of coverage definition and > collection seems not that easy because there are some > complex dependencies. With OS-VVM/CoveragePkg, coverage can be modeled incrementally, and hence, you can create as complicated coverage model as you are willing to write. If you find a problem that you don't think it can handle, drop me a line. I have numerous revision plans for the package, maybe we will learn that some are more important than others. Best Regards, Jim SynthWorks VHDL Training From newsfish@newsfish Fri Feb 3 13:16:04 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!weretis.net!feeder1.news.weretis.net!news.solani.org!.POSTED!not-for-mail From: Christopher Head Newsgroups: comp.lang.vhdl Subject: Re: Spartan 6 MPMC - more ports? Date: Wed, 25 Jan 2012 23:55:00 -0800 Organization: solani.org Lines: 11 Message-ID: <20120125235500.5c920ad2@kruskal.chead> References: <3953827.44.1327097141350.JavaMail.geo-discussion-forums@vby8> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Trace: solani.org 1327564500 21423 eJwFwYEBwDAEBMCV8F5kHKX2HyF3RGj08WA4lzsGrZZaq8xmjkLvLi7S4y9ruOAzFR4rjjwZFxCI (26 Jan 2012 07:55:00 GMT) X-Complaints-To: abuse@news.solani.org NNTP-Posting-Date: Thu, 26 Jan 2012 07:55:00 +0000 (UTC) X-User-ID: eJwFwYEBwDAEBMCVwuN1HKT2HyF3jpAYWniYry8/WPVtZVpPZU2juHDBXJyEcAZJ+RXHQx8jsRDC X-Newsreader: Claws Mail 3.7.10 (GTK+ 2.24.8; x86_64-pc-linux-gnu) Cancel-Lock: sha1:JGJft01buhJqeoRJdJkmca3WVMw= X-NNTP-Posting-Host: eJwNx8EBwCAIA8CZRBJhHANl/xHs/Q6bi3WcoGMw359KyHBtxbYWR6cjiilMAiopq7wT69oDJ10Rog== Xref: mx04.eternal-september.org comp.lang.vhdl:5469 On Fri, 20 Jan 2012 14:05:41 -0800 (PST) Oliver Mattos wrote: > (I am a bit new to Xilinx EDA tools, and am probably a bit off topic > for this group - please be kind!) You may get better results in comp.arch.fpga as this group is more intended for language discussions rather than vendor-specific hardware primitives. Chris From newsfish@newsfish Fri Feb 3 13:16:04 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!newsfeed.kamp.net!newsfeed0.kamp.net!feeder2.cambriumusenet.nl!feed.tweaknews.nl!postnews.google.com!i18g2000yqf.googlegroups.com!not-for-mail From: james.purvis@students.plymouth.ac.uk Newsgroups: comp.lang.vhdl Subject: Stimulus Counter (from Opto-Sensors) Date: Fri, 27 Jan 2012 08:50:44 -0800 (PST) Organization: http://groups.google.com Lines: 142 Message-ID: <286e518a-62dc-4230-91f8-15f9e3420ccd@i18g2000yqf.googlegroups.com> NNTP-Posting-Host: 141.163.99.27 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1327683044 13405 127.0.0.1 (27 Jan 2012 16:50:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 27 Jan 2012 16:50:44 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: i18g2000yqf.googlegroups.com; posting-host=141.163.99.27; posting-account=UMIPGgoAAAC1yaJeOB7XcF_PijwYWU_r User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRUAELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.16 (KHTML, like Gecko) Chrome/10.0.648.127 Safari/534.16,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5470 Hi, I am a student of robotics at Plymouth University, England. I have been using VHDL pretty solidly for about 5 months now and I have come up against a rather devious problem. The project at hand is using a small differential drive robot with an Altera Cyclone II FPGA and an ATmel 64. Using the two active IR sensors on the robot we are to make a line follower (easy part) that makes a "Happy" sound when it detects that it has been on a black line twice (or more) within ten seconds and a "Sad" sound if it has hit the line less than twice. The code below is an entity which I intend to chose one of the two input frequencies (Happy and Sad) and output the relevant one according to the conditions previously specified. [code] library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.numeric_std.all; Use IEEE.math_real.all; entity NoiseSelect is port ( -- Input ports LftS : in std_logic; -- Left Opto-Sensor RgtS : in std_logic; -- Right Opto-Sensor Happy : in std_logic; Sad : in std_logic; HappyDone : in std_logic; SadDone : in std_logic; Clk : in std_logic; -- 1 Hz SysClk : in std_logic; -- 50 MHz -- Output ports TenFlagOut : out std_logic; Outfreq : out std_logic ); end NoiseSelect; architecture Selecter of NoiseSelect is signal CanPlay : std_logic; signal Count : unsigned (3 downto 0); signal TenFlag : std_logic; signal StimCount : unsigned (5 downto 0); signal StimCountFlag : std_logic; signal StimCountReset : std_logic; begin TenFlagOut <= TenFlag; StimCountFlag <= RgtS or LftS; --CanPlay <= not(HappyDone) and not(sadDone); -------------------------------------------- TenSecCount: process(Clk,Count,TenFlag) begin if (Clk'event) and (Clk = '1') then -- Every one second if (TenFlag = '0') then -- provided Tens flag is 0 Count <= Count + 1; -- increment counter elsif (TenFlag = '1') then -- until counter reaches 9 (0 to 9 = 10) Count <= "0000"; -- then reset counter to 0 end if; end if; end process; -------------------------------------------- CountReset: process(Clk,Count,TenFlag) begin if (Count = "1001") then -- When counter reaches 9 TenFlag <= '1'; -- Show that 10 seconds have passed else TenFlag <= '0'; -- Else keep 10 sec flag low end if; end process; -------------------------------------------- StimulusCount: process(RgtS,LftS,TenFlag,StimCount) begin if (SysClk'event) and (SysClk = '1') then if (StimCountFlag = '1') and (StimCountReset = '0') then StimCount <= StimCount + 1; elsif (StimCountFlag = '0') and (StimCountReset = '0') then StimCount <= StimCount; elsif (StimCountReset = '1') then StimCount <= "000000"; end if; end if; end process; -------------------------------------------- StimCountRes: process(TenFlag,StimCountReset) begin if (TenFlag'event) and (TenFlag = '0') then StimCountReset <= '1'; end if; if (TenFlag = '1') then StimCountReset <= '0'; elsif (TenFlag = '0') then StimCountReset <= '0'; end if; end process; -------------------------------------------- end Selecter; [/code] I have also tried the following amendment: [code] -------------------------------------------- StimulusCount: process(RgtS,LftS,TenFlag,StimCount) begin if (SysClk'event) and (SysClk = '1') then if (StimCountFlag = '1') then StimCount <= StimCount + 1; elsif (StimCountReset = '1') then StimCount <= "000000"; end if; end if; end process; -------------------------------------------- StimCountRes: process(TenFlag,StimCountReset) begin if (TenFlag'event) and (TenFlag = '0') then StimCountReset <= '1'; else StimCountReset <= '0'; end if; end process; -------------------------------------------- [/code] I have tried a lot of different methods to get this to work, but my biggest gripe at the moment is that when using SignalTap II "StimCount" is determined to be a Combinational Group and I cannot prove that it counts, whilst "Count" is a Registered group and works perfectly. I will be honest, I'm pretty sure that I've got completely the wrong method for StimCount at the moment, so any help or insight would be greatly appreciated. Image of node finder: http://imageshack.us/photo/my-images/685/nodefinder.png/ Cheers James From newsfish@newsfish Fri Feb 3 13:16:05 2012 Path: eternal-september.org!mx04.eternal-september.org!.POSTED!not-for-mail From: Gabor Newsgroups: comp.lang.vhdl Subject: Re: Stimulus Counter (from Opto-Sensors) Date: Fri, 27 Jan 2012 14:45:47 -0500 Organization: Alacron, Inc. Lines: 180 Message-ID: References: <286e518a-62dc-4230-91f8-15f9e3420ccd@i18g2000yqf.googlegroups.com> Reply-To: gabor@alacron.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Fri, 27 Jan 2012 19:47:57 +0000 (UTC) Injection-Info: mx04.eternal-september.org; posting-host="SUqs68xEs9YfAtSSdphhXg"; logging-data="25169"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+gku9JfxAZToVfbA2ds73K" User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) In-Reply-To: <286e518a-62dc-4230-91f8-15f9e3420ccd@i18g2000yqf.googlegroups.com> Cancel-Lock: sha1:GfFC2TFL+/xOq1mrAWxT03WQXSE= Xref: mx04.eternal-september.org comp.lang.vhdl:5471 james.purvis@students.plymouth.ac.uk wrote: > Hi, > > I am a student of robotics at Plymouth University, England. I have > been using VHDL pretty solidly for about 5 months now and I have come > up against a rather devious problem. The project at hand is using a > small differential drive robot with an Altera Cyclone II FPGA and an > ATmel 64. Using the two active IR sensors on the robot we are to make > a line follower (easy part) that makes a "Happy" sound when it detects > that it has been on a black line twice (or more) within ten seconds > and a "Sad" sound if it has hit the line less than twice. The code > below is an entity which I intend to chose one of the two input > frequencies (Happy and Sad) and output the relevant one according to > the conditions previously specified. > > [code] > library IEEE; > Use IEEE.std_logic_1164.all; > Use IEEE.numeric_std.all; > Use IEEE.math_real.all; > > entity NoiseSelect is > port > ( > -- Input ports > LftS : in std_logic; -- Left Opto-Sensor > RgtS : in std_logic; -- Right Opto-Sensor > Happy : in std_logic; > Sad : in std_logic; > HappyDone : in std_logic; > SadDone : in std_logic; > Clk : in std_logic; -- 1 Hz > SysClk : in std_logic; -- 50 MHz > > -- Output ports > TenFlagOut : out std_logic; > Outfreq : out std_logic > ); > end NoiseSelect; > > architecture Selecter of NoiseSelect is > > signal CanPlay : std_logic; > signal Count : unsigned (3 downto 0); > signal TenFlag : std_logic; > signal StimCount : unsigned (5 downto 0); > signal StimCountFlag : std_logic; > signal StimCountReset : std_logic; > > begin > > TenFlagOut <= TenFlag; > StimCountFlag <= RgtS or LftS; > > --CanPlay <= not(HappyDone) and not(sadDone); > -------------------------------------------- > TenSecCount: process(Clk,Count,TenFlag) > begin > if (Clk'event) and (Clk = '1') then -- Every one second > if (TenFlag = '0') then -- provided Tens flag is 0 > Count <= Count + 1; -- increment counter > elsif (TenFlag = '1') then -- until counter reaches 9 (0 to 9 = > 10) > Count <= "0000"; -- then reset counter to 0 > end if; > end if; > end process; > -------------------------------------------- > CountReset: process(Clk,Count,TenFlag) > begin > if (Count = "1001") then -- When counter reaches 9 > TenFlag <= '1'; -- Show that 10 seconds have passed > else > TenFlag <= '0'; -- Else keep 10 sec flag low > end if; > end process; > -------------------------------------------- > StimulusCount: process(RgtS,LftS,TenFlag,StimCount) > begin > if (SysClk'event) and (SysClk = '1') then > if (StimCountFlag = '1') and (StimCountReset = '0') then > StimCount <= StimCount + 1; > elsif (StimCountFlag = '0') and (StimCountReset = '0') then > StimCount <= StimCount; > elsif (StimCountReset = '1') then > StimCount <= "000000"; > end if; > end if; > end process; > -------------------------------------------- > StimCountRes: process(TenFlag,StimCountReset) > begin > if (TenFlag'event) and (TenFlag = '0') then > StimCountReset <= '1'; > end if; > if (TenFlag = '1') then > StimCountReset <= '0'; > elsif (TenFlag = '0') then > StimCountReset <= '0'; > end if; > end process; > -------------------------------------------- > end Selecter; > [/code] > > I have also tried the following amendment: > [code] > -------------------------------------------- > StimulusCount: process(RgtS,LftS,TenFlag,StimCount) > begin > if (SysClk'event) and (SysClk = '1') then > if (StimCountFlag = '1') then > StimCount <= StimCount + 1; > elsif (StimCountReset = '1') then > StimCount <= "000000"; > end if; > end if; > end process; > -------------------------------------------- > StimCountRes: process(TenFlag,StimCountReset) > begin > if (TenFlag'event) and (TenFlag = '0') then > StimCountReset <= '1'; > else > StimCountReset <= '0'; > end if; > end process; > -------------------------------------------- > [/code] > > I have tried a lot of different methods to get this to work, but my > biggest gripe at the moment is that when using SignalTap II > "StimCount" is determined to be a Combinational Group and I cannot > prove that it counts, whilst "Count" is a Registered group and works > perfectly. I will be honest, I'm pretty sure that I've got completely > the wrong method for StimCount at the moment, so any help or insight > would be greatly appreciated. > > Image of node finder: http://imageshack.us/photo/my-images/685/nodefinder.png/ > > Cheers > > James For a clocked process, ONLY the clock should be in the sensitivity list. The only exception is a clocked process with async reset, in which case the sensitivity list should contain clock and reset. For example: StimulusCount: process(SysClk) begin if (SysClk'event) and (SysClk = '1') then if (StimCountFlag = '1') then StimCount <= StimCount + 1; elsif (StimCountReset = '1') then StimCount <= "000000"; end if; end if; end process; For a process to be combinatorial, there should be no 'event dependencies and all of the right hand side signals should be in the sensitivity list. For example: StimCountRes: process(TenFlag) begin if (TenFlag = '0') then StimCountReset <= '1'; else StimCountReset <= '0'; end if; end process; This describes a simple inverter. If you really wanted a pulse on the falling edge of TenFlag, then you would need some other event like a SysClk edge to reset the signal. As originally coded only an edge on TenFlag would cause the else clause to trigger, and that would probably only work for simulation. I would have expected synthesis to give an error. -- Gabor From newsfish@newsfish Fri Feb 3 13:16:06 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!v14g2000vbc.googlegroups.com!not-for-mail From: Tricky Newsgroups: comp.lang.vhdl Subject: Re: Stimulus Counter (from Opto-Sensors) Date: Mon, 30 Jan 2012 01:08:27 -0800 (PST) Organization: http://groups.google.com Lines: 220 Message-ID: References: <286e518a-62dc-4230-91f8-15f9e3420ccd@i18g2000yqf.googlegroups.com> NNTP-Posting-Host: 194.202.236.125 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1327914886 23124 127.0.0.1 (30 Jan 2012 09:14:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Jan 2012 09:14:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: v14g2000vbc.googlegroups.com; posting-host=194.202.236.125; posting-account=bxxNUQoAAAAOvH5kNfyphc6xU-C2jogm User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESRCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 5.1; rv:9.0.1) Gecko/20100101 Firefox/9.0.1,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5472 On Jan 27, 7:45=A0pm, Gabor wrote: > james.pur...@students.plymouth.ac.uk wrote: > > Hi, > > > I am a student of robotics at Plymouth University, England. I have > > been using VHDL pretty solidly for about 5 months now and I have come > > up against a rather devious problem. The project at hand is using a > > small differential drive robot with an Altera Cyclone II FPGA and an > > ATmel 64. Using the two active IR sensors on the robot we are to make > > a line follower (easy part) that makes a "Happy" sound when it detects > > that it has been on a black line twice (or more) within ten seconds > > and a "Sad" sound if it has hit the line less than twice. The code > > below is an entity which I intend to chose one of the two input > > frequencies (Happy and Sad) and output the relevant one according to > > the conditions previously specified. > > > [code] > > library IEEE; > > Use IEEE.std_logic_1164.all; > > Use IEEE.numeric_std.all; > > Use IEEE.math_real.all; > > > entity NoiseSelect is > > =A0 =A0port > > =A0 =A0( > > =A0 =A0 =A0 =A0 =A0 =A0-- Input ports > > =A0 =A0 =A0 =A0 =A0 =A0LftS =A0 =A0 =A0 =A0 =A0 =A0: in =A0 =A0std_logi= c; =A0 -- Left Opto-Sensor > > =A0 =A0 =A0 =A0 =A0 =A0RgtS =A0 =A0 =A0 =A0 =A0 =A0: in =A0 =A0std_logi= c; =A0 -- Right Opto-Sensor > > =A0 =A0 =A0 =A0 =A0 =A0Happy =A0 =A0 =A0 =A0 =A0 : in =A0 =A0std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0Sad =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in= =A0 =A0std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0HappyDone =A0 =A0 =A0 : in =A0 =A0std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0SadDone =A0 =A0 =A0 =A0 : in =A0 =A0std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0Clk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in= =A0 =A0std_logic; =A0 -- 1 Hz > > =A0 =A0 =A0 =A0 =A0 =A0SysClk =A0 =A0 =A0 =A0 =A0: in =A0 =A0std_logic;= =A0 -- 50 MHz > > > =A0 =A0 =A0 =A0 =A0 =A0-- Output ports > > =A0 =A0 =A0 =A0 =A0 =A0TenFlagOut : out std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0Outfreq : out std_logic > > =A0 =A0); > > end NoiseSelect; > > > architecture Selecter of NoiseSelect is > > > =A0 =A0signal CanPlay =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: =A0 =A0 =A0 = std_logic; > > =A0 =A0signal Count =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: =A0 =A0 = =A0 unsigned (3 downto 0); > > =A0 =A0signal TenFlag =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: =A0 =A0 =A0 = std_logic; > > =A0 =A0signal StimCount =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: =A0 =A0 =A0 un= signed (5 downto 0); > > =A0 =A0signal StimCountFlag =A0 =A0 =A0 =A0 =A0 =A0: =A0 =A0 =A0 std_lo= gic; > > =A0 =A0signal StimCountReset =A0 : =A0 =A0 =A0 std_logic; > > > begin > > > TenFlagOut <=3D TenFlag; > > StimCountFlag <=3D RgtS or LftS; > > > --CanPlay <=3D not(HappyDone) and not(sadDone); > > -------------------------------------------- > > =A0 =A0TenSecCount: process(Clk,Count,TenFlag) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (Clk'event) and (Clk =3D '1') then -- Every o= ne second > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (TenFlag =3D '0') then =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- provided Tens flag is 0 > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Count <=3D Count= + 1; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- increment counter > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0elsif (TenFlag =3D '1') then =A0= =A0 =A0 =A0 =A0 =A0 =A0-- until counter reaches 9 (0 to 9 =3D > > 10) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Count <=3D "0000= "; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- then reset counter to 0 > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > =A0 =A0CountReset: =A0 =A0 process(Clk,Count,TenFlag) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (Count =3D "1001") then =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0-- When counter reaches 9 > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0TenFlag <=3D '1'; =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Show that= 10 seconds have passed > > =A0 =A0 =A0 =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0TenFlag <=3D '0'; =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Else keep= 10 sec flag low > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > =A0 =A0StimulusCount: process(RgtS,LftS,TenFlag,StimCount) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (SysClk'event) and (SysClk =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (StimCountFlag =3D '1') and (= StimCountReset =3D '0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCount <=3D S= timCount + 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0elsif (StimCountFlag =3D '0') an= d (StimCountReset =3D '0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCount <=3D S= timCount; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0elsif (StimCountReset =3D '1') t= hen > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCount <=3D "= 000000"; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > =A0 =A0StimCountRes: process(TenFlag,StimCountReset) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (TenFlag'event) and (TenFlag =3D '0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCountReset <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0if (TenFlag =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCountReset <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0elsif (TenFlag =3D '0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCountReset <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > end Selecter; > > [/code] > > > I have also tried the following amendment: > > [code] > > -------------------------------------------- > > =A0 =A0StimulusCount: process(RgtS,LftS,TenFlag,StimCount) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (SysClk'event) and (SysClk =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (StimCountFlag =3D '1') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCount <=3D S= timCount + 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0elsif (StimCountReset =3D '1') t= hen > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCount <=3D "= 000000"; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > =A0 =A0StimCountRes: process(TenFlag,StimCountReset) > > =A0 =A0begin > > =A0 =A0 =A0 =A0 =A0 =A0if (TenFlag'event) and (TenFlag =3D '0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCountReset <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0StimCountReset <=3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0end process; > > -------------------------------------------- > > [/code] > > > I have tried a lot of different methods to get this to work, but my > > biggest gripe at the moment is that when using SignalTap II > > "StimCount" is determined to be a Combinational Group and I cannot > > prove that it counts, whilst "Count" is a Registered group and works > > perfectly. I will be honest, I'm pretty sure that I've got completely > > the wrong method for StimCount at the moment, so any help or insight > > would be greatly appreciated. > > > Image of node finder:http://imageshack.us/photo/my-images/685/nodefinde= r.png/ > > > Cheers > > > James > > For a clocked process, ONLY the clock should be in the sensitivity list. > The only exception is a clocked process with async reset, in which case > the sensitivity list should contain clock and reset. =A0For example: > > StimulusCount: process(SysClk) > begin > =A0 =A0 =A0 =A0 if (SysClk'event) and (SysClk =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (StimCountFlag =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StimCount <=3D StimCount = + 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif (StimCountReset =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StimCount <=3D "000000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end if; > end process; > > For a process to be combinatorial, there should be no 'event > dependencies and all of the right hand side signals should > be in the sensitivity list. =A0For example: > > StimCountRes: process(TenFlag) > begin > =A0 =A0 =A0 =A0 if (TenFlag =3D '0') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StimCountReset <=3D '1'; > =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StimCountReset <=3D '0'; > =A0 =A0 =A0 =A0 end if; > end process; > > This describes a simple inverter. =A0If you really wanted a pulse on the > falling edge of TenFlag, then you would need some other event like > a SysClk edge to reset the signal. =A0As originally coded only an > edge on TenFlag would cause the else clause to trigger, and that > would probably only work for simulation. =A0I would have expected > synthesis to give an error. > > -- Gabor It wont cause an error, because synthesisors ignore sensitivity lists, and in this case will simply put an inverter, as you suggested. The only reason to tidy up excessive sensitivity lists is for speeding up simulation - it has no effect on synthesis. A bigger issue is when signal are missed from the sensitivity list (like the 3rd process in the OPs code - Sysclk is missing) because then the hardware will not behave like the code. From newsfish@newsfish Fri Feb 3 13:16:06 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!feeder.erje.net!newsfeed.straub-nv.de!proxad.net!feeder1-2.proxad.net!74.125.46.80.MISMATCH!postnews.google.com!m5g2000yqk.googlegroups.com!not-for-mail From: hssig Newsgroups: comp.lang.vhdl Subject: Re: Open Source VHDL Verification Methodology Date: Mon, 30 Jan 2012 01:49:46 -0800 (PST) Organization: http://groups.google.com Lines: 6 Message-ID: References: <6cf9339a-a913-466d-b95d-731c8669b383@t30g2000vbx.googlegroups.com> NNTP-Posting-Host: 217.91.93.34 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1327916986 12838 127.0.0.1 (30 Jan 2012 09:49:46 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Jan 2012 09:49:46 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: m5g2000yqk.googlegroups.com; posting-host=217.91.93.34; posting-account=tyIEqAoAAAB-tb0DAydFT7AqCtqUS1go User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; de; rv:1.9.2.22) Gecko/20110902 Firefox/3.6.22,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5473 >Currently the user guides are only available at: http://www.synthworks.com/downloads Thank you for the link. Cheers, hssig From newsfish@newsfish Fri Feb 3 13:16:06 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!p21g2000yqm.googlegroups.com!not-for-mail From: roleohibachi Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Active-HDL/Xilinx Core FIFO Gen Sim Problem Date: Mon, 30 Jan 2012 09:32:29 -0800 (PST) Organization: http://groups.google.com Lines: 36 Message-ID: NNTP-Posting-Host: 140.32.16.13 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1327945566 15592 127.0.0.1 (30 Jan 2012 17:46:06 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Jan 2012 17:46:06 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: p21g2000yqm.googlegroups.com; posting-host=140.32.16.13; posting-account=QUGBkwoAAACxIVmgl6_xWpDCj0ZEA-f6 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUARELSCNK X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1) AppleWebKit/535.7 (KHTML, like Gecko) Chrome/16.0.912.77 Safari/535.7,gzip(gfe) Xref: mx04.eternal-september.org comp.arch.fpga:17125 comp.lang.vhdl:5474 Hi there, I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I used Aldec's design flow tools to implement a Coregen FIFO, and am using a recent, manufacturer-compiled version of XilinxCoreLib. The project (3 files: my vhdl, the fifo_generator vhdl and the fifo_gen .edn) compiles just fine, but when I go to simulate in Waveform Editor, the part responds "dumb" (all outputs and internal signals floating, no matter the input), and I get the following warnings: # ELBREAD: Warning: Library fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib not found. # ELBREAD: Warning: Design unit fifo_generator_v4_3_fifo_generator_v4_3_xst_1 instantiated in corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in searched libraries: corefifo_test, fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib. # ELBREAD: Warning: Component /fifo1/BU2 : fifo_generator_v4_3_fifo_generator_v4_3_xst_1 not bound. # ELBREAD: Warning: Design unit GND instantiated in corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in searched libraries: corefifo_test, spartan3a. # ELBREAD: Warning: Component /fifo1/GND : GND not bound. I've checked what exists in my XilinxCoreLib, and I've got all the following: fifo_generator_v4_3 fifo_generator_v4_3_bhv_as fifo_generator_v4_3_bhv_preload0 fifo_generator_v4_3_bhv_ss fifo_generator_v4_3_xst So I know that the xst source exists, and is compiled into the library. Any help would be greatly appreciated! From newsfish@newsfish Fri Feb 3 13:16:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!s9g2000vbc.googlegroups.com!not-for-mail From: Benjamin Couillard Newsgroups: comp.arch.fpga,comp.lang.vhdl Subject: Re: Active-HDL/Xilinx Core FIFO Gen Sim Problem Date: Mon, 30 Jan 2012 15:58:26 -0800 (PST) Organization: http://groups.google.com Lines: 52 Message-ID: References: NNTP-Posting-Host: 184.145.148.53 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1327967906 18912 127.0.0.1 (30 Jan 2012 23:58:26 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Mon, 30 Jan 2012 23:58:26 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: s9g2000vbc.googlegroups.com; posting-host=184.145.148.53; posting-account=d6rREgoAAAD9Yw3nMSUmtdHVlgasip1j User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKUARELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows NT 6.1; WOW64) AppleWebKit/535.7 (KHTML, like Gecko) Chrome/16.0.912.77 Safari/535.7,gzip(gfe) Xref: mx04.eternal-september.org comp.arch.fpga:17131 comp.lang.vhdl:5475 On 30 jan, 12:32, roleohibachi wrote: > Hi there, > I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I > used Aldec's design flow tools to implement a Coregen FIFO, and am > using a recent, manufacturer-compiled version of XilinxCoreLib. > The project (3 files: my vhdl, the fifo_generator vhdl and the > fifo_gen .edn) compiles just fine, but when I go to simulate in > Waveform Editor, the part responds "dumb" (all outputs and internal > signals floating, no matter the input), and I get the following > warnings: > > # ELBREAD: Warning: Library > fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib not found. > # ELBREAD: Warning: Design unit > fifo_generator_v4_3_fifo_generator_v4_3_xst_1 instantiated in > corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in > searched libraries: corefifo_test, > fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib. > # ELBREAD: Warning: Component /fifo1/BU2 : > fifo_generator_v4_3_fifo_generator_v4_3_xst_1 not bound. > # ELBREAD: Warning: Design unit GND instantiated in > corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in > searched libraries: corefifo_test, spartan3a. > # ELBREAD: Warning: Component /fifo1/GND : GND not bound. > > I've checked what exists in my XilinxCoreLib, and I've got all the > following: > =A0 fifo_generator_v4_3 > =A0 fifo_generator_v4_3_bhv_as > =A0 fifo_generator_v4_3_bhv_preload0 > =A0 fifo_generator_v4_3_bhv_ss > =A0 fifo_generator_v4_3_xst > > So I know that the xst source exists, and is compiled into the > library. > > Any help would be greatly appreciated! 1 - First, you must download the 10.1 libraries for Aldec 8.1, not the newest verion of the Xilinx libraries since they probably are for version ISE 13.1. Make sure you do not download libraries for Aldec 8.3 either. 2 - If you go in the library manager in Active-HDL, check the different Xilinx libraries and you should be able to see what version of the fifo generator you have. For example, check unisim or Xilinxcorelib, names similar to that. 3 - There is a global library file somewhere for Aldec, don't remember where exactly, but if your library is missing in the library manager, you need to add this library to the global library file. From newsfish@newsfish Fri Feb 3 13:16:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!c20g2000vbb.googlegroups.com!not-for-mail From: Thomas Stanka Newsgroups: comp.lang.vhdl Subject: Re: Stimulus Counter (from Opto-Sensors) Date: Tue, 31 Jan 2012 07:05:57 -0800 (PST) Organization: http://groups.google.com Lines: 48 Message-ID: References: <286e518a-62dc-4230-91f8-15f9e3420ccd@i18g2000yqf.googlegroups.com> NNTP-Posting-Host: 62.156.180.251 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1328022357 23580 127.0.0.1 (31 Jan 2012 15:05:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Jan 2012 15:05:57 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: c20g2000vbb.googlegroups.com; posting-host=62.156.180.251; posting-account=bAGr7AkAAAA2LF5BXuStutxP-ZPQ9FeP User-Agent: G2/1.0 X-HTTP-Via: 1.1 webwasher (Webwasher 6.9.0.11735) X-Google-Web-Client: true X-Google-Header-Order: ASELNKCHRUV X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; de; rv:1.9.1.3) Gecko/20090824 Firefox/3.5.3 (.NET CLR 3.5.30729),gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5476 On 27 Jan., 17:50, james.pur...@students.plymouth.ac.uk wrote: > Use IEEE.math_real.all; I would first get rid of unused libraries, you never know when they strike back. Your design uses 3 different clock domains (Clk, SysClk and TenFlag) the signal crossings between these clock domains are not secure, this will screw up your hardware. Your StimCountRes-Process is complete weird. I can't think of a hardware representation that would represent the code behavior. I would start using only one clock domain (SysClk) and use oversampling to detect rising edge of Clk every second. A lot of the code seems to me quite complex description of simple needed functionality (eg in clocked prcoess you don't need line to hold value (A <= A); On a first glance all your code could be written in the following process syncronous to SysClk. I would prefer to use reset in every case, to ensure your design starts in defined state. signal Clk_Edge_Sr : std_ulogic_vector(3 downto 0); process(SysClk, Reset) if Reset = RESET_ACTIVE then Clk_Edgedetect <= '0'; Clk_Edge_Sr <= (others => '0'); Second <= 0; TenFlag <= '0' elsif rising_egde(SysClk) Clk_Edge_Sr <= Clk_Edge_Sr(2 downto 0) & Clk; if StimCountFlag = '1' then StimCount <= StimCount+1; end if; if Clk_Edge_Sr(3 downto 1) = "011" then StimCount <= (others => '0); if Second < 9 then Second <= Second +1 TenFlag <= '0'; else Second <= 0; TenFlag <= '1'; end if; end if; end if; From newsfish@newsfish Fri Feb 3 13:16:07 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: Michael Seery Newsgroups: comp.lang.vhdl Subject: Re: Active-HDL/Xilinx Core FIFO Gen Sim Problem Date: Tue, 31 Jan 2012 07:39:58 -0800 (PST) Organization: http://groups.google.com Lines: 12 Message-ID: <27188224.121.1328024398822.JavaMail.geo-discussion-forums@yqjq2> References: Reply-To: comp.lang.vhdl@googlegroups.com NNTP-Posting-Host: 140.32.16.14 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1328024399 12209 127.0.0.1 (31 Jan 2012 15:39:59 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Jan 2012 15:39:59 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=140.32.16.14; posting-account=QUGBkwoAAACxIVmgl6_xWpDCj0ZEA-f6 User-Agent: G2/1.0 X-Google-Web-Client: true Xref: mx04.eternal-september.org comp.lang.vhdl:5477 Thanks for your help. Turns out, all the libraries were spot-on, and it did= n't make a difference whether it was attached globally or locally.=20 Called Aldec, took an hour. Made a newbie mistake. Here's the details, for = anyone with the same problem later: I was including the EDIF (.edn) file in the compilation. The EDIF is for sk= ipping synthesis and has nothing to do with compiling. It was automatically= generated by the CoreGen Wizard, and I had just assumed it was a dependenc= y for the FIFO. The compiler was allowing it, but in elaboration, it barfed= . All I had to do was exclude the .edn file from compilation, and everythin= g worked. Thanks again. From newsfish@newsfish Fri Feb 3 13:16:08 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!k6g2000vbz.googlegroups.com!not-for-mail From: MBodnar Newsgroups: comp.lang.vhdl Subject: Re: Active-HDL/Xilinx Core FIFO Gen Sim Problem Date: Tue, 31 Jan 2012 11:28:16 -0800 (PST) Organization: http://groups.google.com Lines: 29 Message-ID: References: <27188224.121.1328024398822.JavaMail.geo-discussion-forums@yqjq2> NNTP-Posting-Host: 4.59.139.131 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1328038097 21770 127.0.0.1 (31 Jan 2012 19:28:17 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Tue, 31 Jan 2012 19:28:17 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: k6g2000vbz.googlegroups.com; posting-host=4.59.139.131; posting-account=er1mVAoAAACeGcBwCiEuZAmH5XJGQKa5 User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HUALESNKRC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 6.1; en-US; rv:1.9.2.16) Gecko/20110319 Firefox/3.6.16,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5478 On Jan 31, 10:39=A0am, Michael Seery wrote: > Thanks for your help. Turns out, all the libraries were spot-on, and it d= idn't make a difference whether it was attached globally or locally. > Called Aldec, took an hour. Made a newbie mistake. Here's the details, fo= r anyone with the same problem later: > I was including the EDIF (.edn) file in the compilation. The EDIF is for = skipping synthesis and has nothing to do with compiling. It was automatical= ly generated by the CoreGen Wizard, and I had just assumed it was a depende= ncy for the FIFO. The compiler was allowing it, but in elaboration, it barf= ed. All I had to do was exclude the .edn file from compilation, and everyth= ing worked. > > Thanks again. Hi Michael, Glad you figured it out! Ultimately, they are different forms of the same thing, to be used for different purposes. CoreGen generates lots of fun stuff in addition to the *.vhd or *.ngc. Careful with your wording, though. There is an immense difference between "compiling for simulation" and "compiling for synthesis." Both are "compiling." And EDIFs can be used in simulation, with proper library support. Cheers, MB From newsfish@newsfish Fri Feb 3 13:16:08 2012 Path: eternal-september.org!mx04.eternal-september.org!feeder.eternal-september.org!news.glorb.com!postnews.google.com!g4g2000pbi.googlegroups.com!not-for-mail From: JimLewis Newsgroups: comp.lang.vhdl Subject: Re: Sanity check on a weird bit of math and std_logic_unsigned Date: Wed, 1 Feb 2012 09:48:15 -0800 (PST) Organization: http://groups.google.com Lines: 74 Message-ID: <55065010-692e-474f-ada4-1b97068bb27a@g4g2000pbi.googlegroups.com> References: <10928718.2186.1327422803192.JavaMail.geo-discussion-forums@vbtr6> NNTP-Posting-Host: 98.232.142.130 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1328118495 2077 127.0.0.1 (1 Feb 2012 17:48:15 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 1 Feb 2012 17:48:15 +0000 (UTC) Complaints-To: groups-abuse@google.com Injection-Info: g4g2000pbi.googlegroups.com; posting-host=98.232.142.130; posting-account=1KCIgQgAAAAQJJrGC8DwZ5vNFUMQMLDs User-Agent: G2/1.0 X-Google-Web-Client: true X-Google-Header-Order: HNKRAUELSC X-HTTP-UserAgent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US) AppleWebKit/534.10 (KHTML, like Gecko) Chrome/8.0.552.237 Safari/534.10,gzip(gfe) Xref: mx04.eternal-september.org comp.lang.vhdl:5479 Hi Mark, I think the key here is to put "_" in the literals to make them readable. It is X"0800_0000" and not X"8000_0000". So if we ignore the decay temporarily. The count has to be greater than or equal to X"F800_0000" to cause a roll over and for the if statement to be false. The following assignment looks odd to me since it is huge decay rather than a saturation: count <=3D X"0800_0000"; The shift is a by 16: x <=3D x - shift_right(x,16), Best, Jim > I'm having to do surgery on something a contractor left us. =A0One small = problem was that he took a file with numeric_std already defined and used a= nd then for his own additions added std_logic_unsigned (thanks SO much.) = =A0Anyhow, I am having to carefully evaluate what he's doing so that I don'= t unnecessarily break something that is already working. =A0Not especially = well commented either, so I'm having to infer intent from the code as well. > > So, I run into a bit of code where he's putting in a little filter and I = am having trouble trying to figure out what the hell he was getting at, bec= ause as far as I can tell, there's code that will never get executed due to= the way the math works. > > [code snippet, encapsulated in ye olde clocked process] > if (pulse_event_true =3D '1') then > =A0 =A0if ((X"08000000" + count - (X"0000 & count(31 downto 16))) < X"080= 00000") then > =A0 =A0 =A0 =A0count <=3D (the above equation); > =A0 =A0else > =A0 =A0 =A0 =A0count <=3D X"08000000"; > =A0 =A0end if; > else > =A0 =A0count <=3D count - (X"0000 & count(31 downto 16)); > end if; > [/code] > > Okay, so when there's a pulse, he adds a constant to the count, and other= wise it decays slowly. =A0No trouble there. =A0The problem I've got is that= he does that bounds check at the beginning to make sure he doesn't exceed = 0x08000000 before he does the addition, otherwise he just caps out at 0x080= 00000. > > The part I don't get is that the saturation limit is exactly the same as = the constant he's adding. =A0By my reasoning, the count value could never e= xceed 0x08000000 except as a starting condition, and then we might have som= ething large enough that it would wrap around 0xfffffffff and then trigger = the top clause. =A0This is covered by the fact that the count has an asynch= ronous reset to 0, and has a synchronous reset to 0 (software controlled el= sewhere). =A0Thus as far as I can tell, this count is going to stay at 0 un= til a pulse comes along, get set to 0x08000000, decay awhile until the next= pulse. =A0When another pulse comes along, there's no mathematical way the = current count plus 0x08000000 will ever NOT be greater than or equal to 0x0= 8000000 and thus just gets pegged back to the count. > > It seems to be working adequately by all reports, but it kind of bugs me.= =A0And I'm taking out the std_logic_unsigned crap, so I can pretty easily = convert the math to x <=3D x - shift_right(x,8), but there's that damned as= -far-as-I-can-tell-non-executing-code that I have to decide whether to keep= or just simplify to what is happening. > > Any ideas folks? =A0Am I missing a case whereby C + f(t) is ever < C for = all f(t) being non-negative? > > Thanks for any responses. > > Mark